1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997 Free Software Foundation, Inc.
3 Contributed by Jeff Law (law@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
39 /* The size of the callee register save area. Right now we save everything
40 on entry since it costs us nothing in code size. It does cost us from a
41 speed standpoint, so we want to optimize this sooner or later. */
42 #define REG_SAVE_BYTES (16)
44 /* Global registers known to hold the value zero.
46 Normally we'd depend on CSE and combine to put zero into a
47 register and re-use it.
49 However, on the mn10x00 processors we implicitly use the constant
50 zero in tst instructions, so we might be able to do better by
51 loading the value into a register in the prologue, then re-useing
52 that register throughout the function.
54 We could perform similar optimizations for other constants, but with
55 gcse due soon, it doesn't seem worth the effort.
57 These variables hold a rtx for a register known to hold the value
58 zero throughout the entire function, or NULL if no register of
59 the appropriate class has such a value throughout the life of the
68 fprintf (file, "#\tGCC For the Matsushita MN10300\n");
70 fprintf (file, "# -O%d\n", optimize);
72 fprintf (file, "\n\n");
73 output_file_directive (file, main_input_filename);
77 /* Print operand X using operand code CODE to assembly language output file
81 print_operand (file, x, code)
90 /* These are normal and reversed branches. */
91 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
100 fprintf (file, "ge");
103 fprintf (file, "gt");
106 fprintf (file, "le");
109 fprintf (file, "lt");
112 fprintf (file, "cc");
115 fprintf (file, "hi");
118 fprintf (file, "ls");
121 fprintf (file, "cs");
128 /* This is used for the operand to a call instruction;
129 if it's a REG, enclose it in parens, else output
130 the operand normally. */
131 if (GET_CODE (x) == REG)
134 print_operand (file, x, 0);
138 print_operand (file, x, 0);
141 /* These are the least significant word in a 64bit value. */
143 switch (GET_CODE (x))
147 output_address (XEXP (x, 0));
152 fprintf (file, "%s", reg_names[REGNO (x)]);
157 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
165 switch (GET_MODE (x))
168 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
169 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
170 print_operand_address (file, GEN_INT (val[0]));
173 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
174 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
175 print_operand_address (file, GEN_INT (val[0]));
179 print_operand_address (file,
180 GEN_INT (CONST_DOUBLE_LOW (x)));
187 print_operand_address (file, x);
195 /* Similarly, but for the most significant word. */
197 switch (GET_CODE (x))
201 x = adj_offsettable_operand (x, 4);
202 output_address (XEXP (x, 0));
207 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
212 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1);
220 switch (GET_MODE (x))
223 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
224 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
225 print_operand_address (file, GEN_INT (val[1]));
231 print_operand_address (file,
232 GEN_INT (CONST_DOUBLE_HIGH (x)));
240 print_operand_address (file, GEN_INT (-1));
242 print_operand_address (file, GEN_INT (0));
251 if (GET_CODE (XEXP (x, 0)) == REG)
252 output_address (gen_rtx (PLUS, SImode, XEXP (x, 0), GEN_INT (0)));
254 output_address (XEXP (x, 0));
259 output_address (GEN_INT ((~INTVAL (x)) & 0xff));
262 /* For shift counts. The hardware ignores the upper bits of
263 any immediate, but the assembler will flag an out of range
264 shift count as an error. So we mask off the high bits
265 of the immediate here. */
267 if (GET_CODE (x) == CONST_INT)
269 fprintf (file, "%d", INTVAL (x) & 0x1f);
275 switch (GET_CODE (x))
279 output_address (XEXP (x, 0));
288 fprintf (file, "%s", reg_names[REGNO (x)]);
293 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
296 /* This will only be single precision.... */
302 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
303 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
304 print_operand_address (file, GEN_INT (val));
313 print_operand_address (file, x);
322 /* Output assembly language output for the address ADDR to FILE. */
325 print_operand_address (file, addr)
329 switch (GET_CODE (addr))
332 if (addr == stack_pointer_rtx)
333 print_operand_address (file, gen_rtx (PLUS, SImode,
337 print_operand (file, addr, 0);
342 if (REG_P (XEXP (addr, 0))
343 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
344 base = XEXP (addr, 0), index = XEXP (addr, 1);
345 else if (REG_P (XEXP (addr, 1))
346 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
347 base = XEXP (addr, 1), index = XEXP (addr, 0);
350 print_operand (file, index, 0);
352 print_operand (file, base, 0);;
356 output_addr_const (file, addr);
359 output_addr_const (file, addr);
365 can_use_return_insn ()
367 /* size includes the fixed stack space needed for function calls. */
368 int size = get_frame_size () + current_function_outgoing_args_size;
370 /* And space for the return pointer. */
371 size += current_function_outgoing_args_size ? 4 : 0;
373 return (reload_completed
375 && !regs_ever_live[2]
376 && !regs_ever_live[3]
377 && !regs_ever_live[6]
378 && !regs_ever_live[7]
379 && !frame_pointer_needed);
382 /* Count the number of tst insns which compare a data or address
383 register with zero. */
385 count_tst_insns (dreg_countp, areg_countp)
391 /* Assume no tst insns exist. */
395 /* If not optimizing, then quit now. */
399 /* Walk through all the insns. */
400 for (insn = get_insns (); insn; insn = NEXT_INSN (insn))
404 /* Ignore anything that is not a normal INSN. */
405 if (GET_CODE (insn) != INSN)
408 /* Ignore anything that isn't a SET. */
409 pat = PATTERN (insn);
410 if (GET_CODE (pat) != SET)
413 /* Check for a tst insn. */
414 if (SET_DEST (pat) == cc0_rtx
415 && GET_CODE (SET_SRC (pat)) == REG)
417 if (REGNO_REG_CLASS (REGNO (SET_SRC (pat))) == DATA_REGS)
420 if (REGNO_REG_CLASS (REGNO (SET_SRC (pat))) == ADDRESS_REGS)
424 /* Setting an address register to zero can also be optimized,
425 so count it just like a tst insn. */
426 if (GET_CODE (SET_DEST (pat)) == REG
427 && GET_CODE (SET_SRC (pat)) == CONST_INT
428 && INTVAL (SET_SRC (pat)) == 0
429 && REGNO_REG_CLASS (REGNO (SET_DEST (pat))) == ADDRESS_REGS)
439 /* We need to end the current sequence so that count_tst_insns can
440 look at all the insns in this function. Normally this would be
441 unsafe, but it's OK in the prologue/epilogue expanders. */
444 /* Determine if it is profitable to put the value zero into a register
445 for the entire function. If so, set ZERO_DREG and ZERO_AREG. */
446 if (regs_ever_live[2] || regs_ever_live[3]
447 || regs_ever_live[6] || regs_ever_live[7]
448 || frame_pointer_needed)
450 int dreg_count, areg_count;
452 /* Get a count of the number of tst insns which use address and
454 count_tst_insns (&dreg_count, &areg_count);
456 /* If there's more than one tst insn using a data register, then
457 this optimization is a win. */
459 && (!regs_ever_live[2] || !regs_ever_live[3]))
461 if (!regs_ever_live[2])
463 regs_ever_live[2] = 1;
464 zero_dreg = gen_rtx (REG, SImode, 2);
468 regs_ever_live[3] = 1;
469 zero_dreg = gen_rtx (REG, SImode, 3);
473 zero_dreg = NULL_RTX;
475 /* If there's more than two tst insns using an address register,
476 then this optimization is a win. */
478 && (!regs_ever_live[6] || !regs_ever_live[7]))
480 if (!regs_ever_live[6])
482 regs_ever_live[6] = 1;
483 zero_areg = gen_rtx (REG, SImode, 6);
487 regs_ever_live[7] = 1;
488 zero_areg = gen_rtx (REG, SImode, 7);
492 zero_areg = NULL_RTX;
496 zero_dreg = NULL_RTX;
497 zero_areg = NULL_RTX;
500 /* Start a new sequence. */
503 /* SIZE includes the fixed stack space needed for function calls. */
504 size = get_frame_size () + current_function_outgoing_args_size;
505 size += (current_function_outgoing_args_size ? 4 : 0);
507 /* If this is an old-style varargs function, then its arguments
508 need to be flushed back to the stack. */
509 if (current_function_varargs)
511 emit_move_insn (gen_rtx (MEM, SImode,
512 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
514 gen_rtx (REG, SImode, 0));
515 emit_move_insn (gen_rtx (MEM, SImode,
516 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
518 gen_rtx (REG, SImode, 1));
521 /* And now store all the registers onto the stack with a
522 single two byte instruction. */
523 if (regs_ever_live[2] || regs_ever_live[3]
524 || regs_ever_live[6] || regs_ever_live[7]
525 || frame_pointer_needed)
526 emit_insn (gen_store_movm ());
528 /* Now put the frame pointer into the frame pointer register. */
529 if (frame_pointer_needed)
530 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
532 /* Allocate stack for this frame. */
534 emit_insn (gen_addsi3 (stack_pointer_rtx,
538 /* Load zeros into registers as needed. */
540 emit_move_insn (zero_dreg, const0_rtx);
543 emit_move_insn (zero_areg, const0_rtx);
551 /* SIZE includes the fixed stack space needed for function calls. */
552 size = get_frame_size () + current_function_outgoing_args_size;
553 size += (current_function_outgoing_args_size ? 4 : 0);
555 /* Maybe cut back the stack, except for the register save area.
557 If the frame pointer exists, then use the frame pointer to
560 If the stack size + register save area is more than 255 bytes,
561 then the stack must be cut back here since the size + register
562 save size is too big for a ret/retf instruction.
564 Else leave it alone, it will be cut back as part of the
565 ret/retf instruction, or there wasn't any stack to begin with.
567 Under no circumstanes should the register save area be
568 deallocated here, that would leave a window where an interrupt
569 could occur and trash the register save area. */
570 if (frame_pointer_needed)
572 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
575 else if ((regs_ever_live[2] || regs_ever_live[3]
576 || regs_ever_live[6] || regs_ever_live[7])
577 && size + REG_SAVE_BYTES > 255)
579 emit_insn (gen_addsi3 (stack_pointer_rtx,
585 /* For simplicity, we just movm all the callee saved registers to
586 the stack with one instruction.
588 ?!? Only save registers which are actually used. Reduces
589 stack requirements and is faster. */
590 if (regs_ever_live[2] || regs_ever_live[3]
591 || regs_ever_live[6] || regs_ever_live[7]
592 || frame_pointer_needed)
593 emit_jump_insn (gen_return_internal_regs (GEN_INT (size + REG_SAVE_BYTES)));
598 emit_insn (gen_addsi3 (stack_pointer_rtx,
601 emit_jump_insn (gen_return_internal ());
605 emit_jump_insn (gen_return ());
610 /* Update the condition code from the insn. */
613 notice_update_cc (body, insn)
617 switch (get_attr_cc (insn))
620 /* Insn does not affect CC at all. */
624 /* Insn does not change CC, but the 0'th operand has been changed. */
625 if (cc_status.value1 != 0
626 && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
627 cc_status.value1 = 0;
631 /* Insn sets the Z,N flags of CC to recog_operand[0].
634 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
635 cc_status.value1 = recog_operand[0];
639 /* Insn sets the Z,N,V flags of CC to recog_operand[0].
642 cc_status.flags |= CC_NO_CARRY;
643 cc_status.value1 = recog_operand[0];
647 /* The insn is a compare instruction. */
649 cc_status.value1 = SET_SRC (body);
653 /* The insn is a compare instruction. */
655 cc_status.value1 = SET_SRC (body);
656 cc_status.flags |= CC_INVERTED;
660 /* Insn doesn't leave CC in a usable state. */
669 /* Return true if OP is a valid call operand. */
672 call_address_operand (op, mode)
674 enum machine_mode mode;
676 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
679 /* What (if any) secondary registers are needed to move IN with mode
680 MODE into a register from in register class CLASS.
682 We might be able to simplify this. */
684 secondary_reload_class (class, mode, in)
685 enum reg_class class;
686 enum machine_mode mode;
691 /* Memory loads less than a full word wide can't have an
692 address or stack pointer destination. They must use
693 a data register as an intermediate register. */
694 if (GET_CODE (in) == MEM
695 && (mode == QImode || mode == HImode)
696 && (class == ADDRESS_REGS || class == SP_REGS))
701 /* We can't directly load sp + const_int into a data register;
702 we must use an address register as an intermediate. */
704 && class != ADDRESS_REGS
705 && class != SP_OR_ADDRESS_REGS
706 && (in == stack_pointer_rtx
707 || (GET_CODE (in) == PLUS
708 && (XEXP (in, 0) == stack_pointer_rtx
709 || XEXP (in, 1) == stack_pointer_rtx))))
712 if (GET_CODE (in) == PLUS
713 && (XEXP (in, 0) == stack_pointer_rtx
714 || XEXP (in, 1) == stack_pointer_rtx))
719 /* Otherwise assume no secondary reloads are needed. */
724 initial_offset (from, to)
727 /* The difference between the argument pointer and the frame pointer
728 is the size of the callee register save area. */
729 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
731 if (regs_ever_live[2] || regs_ever_live[3]
732 || regs_ever_live[6] || regs_ever_live[7]
733 || frame_pointer_needed)
734 return REG_SAVE_BYTES;
739 /* The difference between the argument pointer and the stack pointer is
740 the sum of the size of this function's frame, the callee register save
741 area, and the fixed stack space needed for function calls (if any). */
742 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
744 if (regs_ever_live[2] || regs_ever_live[3]
745 || regs_ever_live[6] || regs_ever_live[7]
746 || frame_pointer_needed)
747 return (get_frame_size () + REG_SAVE_BYTES
748 + (current_function_outgoing_args_size
749 ? current_function_outgoing_args_size + 4 : 0));
751 return (get_frame_size ()
752 + (current_function_outgoing_args_size
753 ? current_function_outgoing_args_size + 4 : 0));
756 /* The difference between the frame pointer and stack pointer is the sum
757 of the size of this function's frame and the fixed stack space needed
758 for function calls (if any). */
759 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
760 return (get_frame_size ()
761 + (current_function_outgoing_args_size
762 ? current_function_outgoing_args_size + 4 : 0));
767 /* Flush the argument registers to the stack for a stdarg function;
768 return the new argument pointer. */
770 mn10300_builtin_saveregs (arglist)
774 tree fntype = TREE_TYPE (current_function_decl);
775 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
776 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
778 ? UNITS_PER_WORD : 0);
781 offset = plus_constant (current_function_arg_offset_rtx, argadj);
783 offset = current_function_arg_offset_rtx;
785 emit_move_insn (gen_rtx (MEM, SImode, current_function_internal_arg_pointer),
786 gen_rtx (REG, SImode, 0));
787 emit_move_insn (gen_rtx (MEM, SImode,
789 (current_function_internal_arg_pointer, 4)),
790 gen_rtx (REG, SImode, 1));
791 return copy_to_reg (expand_binop (Pmode, add_optab,
792 current_function_internal_arg_pointer,
793 offset, 0, 0, OPTAB_LIB_WIDEN));
796 /* Return an RTX to represent where a value with mode MODE will be returned
797 from a function. If the result is 0, the argument is pushed. */
800 function_arg (cum, mode, type, named)
801 CUMULATIVE_ARGS *cum;
802 enum machine_mode mode;
809 /* We only support using 2 data registers as argument registers. */
812 /* Figure out the size of the object to be passed. */
814 size = int_size_in_bytes (type);
816 size = GET_MODE_SIZE (mode);
818 /* Figure out the alignment of the object to be passed. */
821 cum->nbytes = (cum->nbytes + 3) & ~3;
823 /* Don't pass this arg via a register if all the argument registers
825 if (cum->nbytes > nregs * UNITS_PER_WORD)
828 /* Don't pass this arg via a register if it would be split between
829 registers and memory. */
830 if (type == NULL_TREE
831 && cum->nbytes + size > nregs * UNITS_PER_WORD)
834 switch (cum->nbytes / UNITS_PER_WORD)
837 result = gen_rtx (REG, mode, 0);
840 result = gen_rtx (REG, mode, 1);
849 /* Return the number of registers to use for an argument passed partially
850 in registers and partially in memory. */
853 function_arg_partial_nregs (cum, mode, type, named)
854 CUMULATIVE_ARGS *cum;
855 enum machine_mode mode;
861 /* We only support using 2 data registers as argument registers. */
864 /* Figure out the size of the object to be passed. */
866 size = int_size_in_bytes (type);
868 size = GET_MODE_SIZE (mode);
870 /* Figure out the alignment of the object to be passed. */
873 cum->nbytes = (cum->nbytes + 3) & ~3;
875 /* Don't pass this arg via a register if all the argument registers
877 if (cum->nbytes > nregs * UNITS_PER_WORD)
880 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
883 /* Don't pass this arg via a register if it would be split between
884 registers and memory. */
885 if (type == NULL_TREE
886 && cum->nbytes + size > nregs * UNITS_PER_WORD)
889 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
892 /* Output a tst insn. */
894 output_tst (operand, insn)
900 /* If we have a data register which is known to be zero throughout
901 the function, then use it instead of doing a search. */
902 if (zero_dreg && REGNO_REG_CLASS (REGNO (operand)) == DATA_REGS)
905 xoperands[0] = operand;
906 xoperands[1] = zero_dreg;
908 output_asm_insn ("cmp %1,%0", xoperands);
912 /* Similarly for address registers. */
913 if (zero_areg && REGNO_REG_CLASS (REGNO (operand)) == ADDRESS_REGS)
916 xoperands[0] = operand;
917 xoperands[1] = zero_areg;
919 output_asm_insn ("cmp %1,%0", xoperands);
923 /* We can save a byte if we can find a register which has the value
925 temp = PREV_INSN (insn);
926 while (optimize && temp)
930 /* We allow the search to go through call insns. We record
931 the fact that we've past a CALL_INSN and reject matches which
932 use call clobbered registers. */
933 if (GET_CODE (temp) == CODE_LABEL
934 || GET_CODE (temp) == JUMP_INSN
935 || GET_CODE (temp) == BARRIER)
938 if (GET_CODE (temp) == CALL_INSN)
941 if (GET_CODE (temp) == NOTE)
943 temp = PREV_INSN (temp);
947 /* It must be an insn, see if it is a simple set. */
948 set = single_set (temp);
951 temp = PREV_INSN (temp);
955 /* Are we setting a data register to zero (this does not win for
958 If it's a call clobbered register, have we past a call?
960 Make sure the register we find isn't the same as ourself;
961 the mn10300 can't encode that.
963 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
964 so the code to detect calls here isn't doing anything useful. */
965 if (REG_P (SET_DEST (set))
966 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
967 && !reg_set_between_p (SET_DEST (set), temp, insn)
968 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
969 == REGNO_REG_CLASS (REGNO (operand)))
970 && REGNO (SET_DEST (set)) != REGNO (operand)
972 || !call_used_regs[REGNO (SET_DEST (set))]))
975 xoperands[0] = operand;
976 xoperands[1] = SET_DEST (set);
978 output_asm_insn ("cmp %1,%0", xoperands);
981 temp = PREV_INSN (temp);
987 impossible_plus_operand (op, mode)
989 enum machine_mode mode;
991 extern rtx *reg_equiv_mem;
994 if (GET_CODE (op) != PLUS)
997 if (XEXP (op, 0) == stack_pointer_rtx
998 || XEXP (op, 1) == stack_pointer_rtx)
1004 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1005 for the btst insn which may examine memory or a register (the memory
1006 variant only allows an unsigned 8 bit integer). */
1008 const_8bit_operand (op, mode)
1010 enum machine_mode mode;
1012 return (GET_CODE (op) == CONST_INT
1014 && INTVAL (op) < 256);
1017 /* Similarly, but when using a zero_extract pattern for a btst where
1018 the source operand might end up in memory. */
1020 mask_ok_for_mem_btst (len, bit)
1033 /* MASK must bit into an 8bit value. */
1034 return (((mask & 0xff) == mask)
1035 || ((mask & 0xff00) == mask)
1036 || ((mask & 0xff0000) == mask)
1037 || ((mask & 0xff000000) == mask));
1040 /* Return 1 if X contains a symbolic expression. We know these
1041 expressions will have one of a few well defined forms, so
1042 we need only check those forms. */
1044 symbolic_operand (op, mode)
1046 enum machine_mode mode;
1048 switch (GET_CODE (op))
1055 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1056 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1057 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1063 /* Try machine dependent ways of modifying an illegitimate address
1064 to be legitimate. If we find one, return the new valid address.
1065 This macro is used in only one place: `memory_address' in explow.c.
1067 OLDX is the address as it was before break_out_memory_refs was called.
1068 In some cases it is useful to look at this to decide what needs to be done.
1070 MODE and WIN are passed so that this macro can use
1071 GO_IF_LEGITIMATE_ADDRESS.
1073 Normally it is always safe for this macro to do nothing. It exists to
1074 recognize opportunities to optimize the output.
1076 But on a few ports with segmented architectures and indexed addressing
1077 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1079 legitimize_address (x, oldx, mode)
1082 enum machine_mode mode;
1084 /* Uh-oh. We might have an address for x[n-100000]. This needs
1085 special handling to avoid creating an indexed memory address
1086 with x-100000 as the base. */
1087 if (GET_CODE (x) == PLUS
1088 && symbolic_operand (XEXP (x, 1), VOIDmode))
1090 /* Ugly. We modify things here so that the address offset specified
1091 by the index expression is computed first, then added to x to form
1092 the entire address. */
1094 rtx regx1, regx2, regy1, regy2, y;
1096 /* Strip off any CONST. */
1098 if (GET_CODE (y) == CONST)
1101 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1103 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1104 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1105 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1106 regx1 = force_reg (Pmode,
1107 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1108 return force_reg (Pmode, gen_rtx (PLUS, Pmode, regx1, regy1));