/* Definitions of target machine for GNU compiler. Matsushita MN10300 series
- Copyright (C) 1996, 1997 Free Software Foundation, Inc.
+ Copyright (C) 1996, 1997, 1998 Free Software Foundation, Inc.
Contributed by Jeff Law (law@cygnus.com).
This file is part of GNU CC.
class that represents their union. */
enum reg_class {
- NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS, DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
+ NO_REGS, DATA_REGS, ADDRESS_REGS, SP_REGS,
+ DATA_OR_ADDRESS_REGS, SP_OR_ADDRESS_REGS,
+ GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES
};
#define N_REG_CLASSES (int) LIM_REG_CLASSES
#define REGNO_REG_CLASS(REGNO) \
((REGNO) < 4 ? DATA_REGS : \
(REGNO) < 9 ? ADDRESS_REGS : \
- (REGNO) == 9 ? SP_REGS: 0)
+ (REGNO) == 9 ? SP_REGS : 0)
/* The class value for index registers, and the one for base regs. */
-
#define INDEX_REG_CLASS DATA_REGS
#define BASE_REG_CLASS SP_OR_ADDRESS_REGS
#define REG_CLASS_FROM_LETTER(C) \
((C) == 'd' ? DATA_REGS : \
(C) == 'a' ? ADDRESS_REGS : \
- (C) == 'x' ? SP_REGS : NO_REGS)
+ (C) == 'y' ? SP_REGS : NO_REGS)
/* Macros to check register numbers against specific register classes. */
(((regno) > 3 && regno < FIRST_PSEUDO_REGISTER) \
|| (reg_renumber[regno] > 3 && reg_renumber[regno] < FIRST_PSEUDO_REGISTER))
+#define REGNO_OK_FOR_BIT_BASE_P(regno) \
+ (((regno) > 3 && regno < 10) \
+ || (reg_renumber[regno] > 3 && reg_renumber[regno] < 10))
+
#define REGNO_OK_FOR_INDEX_P(regno) \
(((regno) >= 0 && regno < 4) \
|| (reg_renumber[regno] >= 0 && reg_renumber[regno] < 4))
&& GET_MODE (OP) == QImode \
&& (CONSTANT_ADDRESS_P (XEXP (OP, 0)) \
|| (GET_CODE (XEXP (OP, 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (OP, 0)) \
+ && REG_OK_FOR_BIT_BASE_P (XEXP (OP, 0)) \
&& XEXP (OP, 0) != stack_pointer_rtx) \
|| (GET_CODE (XEXP (OP, 0)) == PLUS \
&& GET_CODE (XEXP (XEXP (OP, 0), 0)) == REG \
- && REG_OK_FOR_BASE_P (XEXP (XEXP (OP, 0), 0)) \
+ && REG_OK_FOR_BIT_BASE_P (XEXP (XEXP (OP, 0), 0)) \
&& XEXP (XEXP (OP, 0), 0) != stack_pointer_rtx \
&& GET_CODE (XEXP (XEXP (OP, 0), 1)) == CONST_INT \
&& INT_8_BITS (INTVAL (XEXP (XEXP (OP, 0), 1))))))
/* Nonzero if X is a hard reg that can be used as an index
or if it is a pseudo reg. */
#define REG_OK_FOR_INDEX_P(X) \
- ((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+ ((REGNO (X) >= 0 && REGNO(X) <= 3) || REGNO (X) >= 10)
/* Nonzero if X is a hard reg that can be used as a base reg
or if it is a pseudo reg. */
#define REG_OK_FOR_BASE_P(X) \
- ((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= FIRST_PSEUDO_REGISTER)
+ ((REGNO (X) >= 4 && REGNO(X) <= 9) || REGNO (X) >= 10)
+#define REG_OK_FOR_BIT_BASE_P(X) \
+ ((REGNO (X) >= 4 && REGNO(X) <= 9))
#else
/* Nonzero if X is a hard reg that can be used as an index. */
#define REG_OK_FOR_INDEX_P(X) REGNO_OK_FOR_INDEX_P (REGNO (X))
/* Nonzero if X is a hard reg that can be used as a base reg. */
#define REG_OK_FOR_BASE_P(X) REGNO_OK_FOR_BASE_P (REGNO (X))
+/* Nonzero if X is a hard reg that can be used as a base reg. */
+#define REG_OK_FOR_BIT_BASE_P(X) REGNO_OK_FOR_BIT_BASE_P (REGNO (X))
#endif
\f
}")
(define_insn ""
- [(set (match_operand:QI 0 "general_operand" "=d,*a,d,*a,d,*a,d,*a,d,m")
- (match_operand:QI 1 "general_operand" "0,0,I,I,a,d,di,ia,m,d"))]
+ [(set (match_operand:QI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m")
+ (match_operand:QI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))]
"register_operand (operands[0], QImode)
|| register_operand (operands[1], QImode)"
"*
}")
(define_insn ""
- [(set (match_operand:HI 0 "general_operand" "=d,*a,d,*a,d,*a,d,*a,d,m")
- (match_operand:HI 1 "general_operand" "0,0,I,I,a,d,di,ia,m,d"))]
+ [(set (match_operand:HI 0 "general_operand" "=dx,*a,dx,*a,dx,*a,dx,*a,dx,m")
+ (match_operand:HI 1 "general_operand" "0,0,I,I,a,dx,dxi,ia,m,dx"))]
"register_operand (operands[0], HImode)
|| register_operand (operands[1], HImode)"
"*
(define_insn ""
[(set (match_operand:SI 0 "general_operand"
- "=d,a,d,a,dm,dm,am,am,d,d,a,a,aR,x")
+ "=dx,ax,dx,ax,dxm,dxm,axm,axm,dx,dx,ax,ax,axR,y")
(match_operand:SI 1 "general_operand"
- "0,0,I,I,d,a,d,a,dim,aim,dim,aim,x,aR"))]
+ "0,0,I,I,dx,ax,dx,ax,dixm,aixm,dixm,aixm,xy,axR"))]
"register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode)"
"*
}")
(define_insn ""
- [(set (match_operand:SF 0 "general_operand" "=d,a,d,a,dam,da")
- (match_operand:SF 1 "general_operand" "0,0,G,G,da,daim"))]
+ [(set (match_operand:SF 0 "general_operand" "=dx,ax,dx,ax,daxm,dax")
+ (match_operand:SF 1 "general_operand" "0,0,G,G,dax,daxim"))]
"register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode)"
"*
(define_insn ""
[(set (match_operand:DI 0 "general_operand"
- "=d,a,d,a,dm,dm,am,am,d,d,a,a")
+ "=dx,ax,dx,ax,dxm,dxm,axm,axm,dx,dx,ax,ax")
(match_operand:DI 1 "general_operand"
- "0,0,I,I,d,a,d,a,dim,aim,dim,aim"))]
+ "0,0,I,I,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
"register_operand (operands[0], DImode)
|| register_operand (operands[1], DImode)"
"*
(define_insn ""
[(set (match_operand:DF 0 "general_operand"
- "=d,a,d,a,dm,dm,am,am,d,d,a,a")
+ "=dx,ax,dx,ax,dxm,dxm,axm,axm,dx,dx,ax,ax")
(match_operand:DF 1 "general_operand"
- "0,0,G,G,d,a,d,a,dim,aim,dim,aim"))]
+ "0,0,G,G,dx,ax,dx,ax,dxim,axim,dxim,axim"))]
"register_operand (operands[0], DFmode)
|| register_operand (operands[1], DFmode)"
"*
;; Go ahead and define tstsi so we can eliminate redundant tst insns
;; when we start trying to optimize this port.
(define_insn "tstsi"
- [(set (cc0) (match_operand:SI 0 "register_operand" "da"))]
+ [(set (cc0) (match_operand:SI 0 "register_operand" "dax"))]
""
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
(define_insn ""
- [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "d")))]
+ [(set (cc0) (zero_extend:SI (match_operand:QI 0 "memory_operand" "dx")))]
""
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
(define_insn ""
- [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "d")))]
+ [(set (cc0) (zero_extend:SI (match_operand:HI 0 "memory_operand" "dx")))]
""
"* return output_tst (operands[0], insn);"
[(set_attr "cc" "set_znv")])
(define_insn "cmpsi"
[(set (cc0)
- (compare (match_operand:SI 0 "register_operand" "!*d*a,da")
- (match_operand:SI 1 "nonmemory_operand" "!*0,dai")))]
+ (compare (match_operand:SI 0 "register_operand" "!*d*a*x,dax")
+ (match_operand:SI 1 "nonmemory_operand" "!*0,daxi")))]
""
"@
add 0,%0
}")
(define_insn ""
- [(set (match_operand:SI 0 "register_operand" "=d,a,a,da,x,&!da")
- (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,da")
- (match_operand:SI 2 "nonmemory_operand" "J,J,L,dai,i,da")))]
+ [(set (match_operand:SI 0 "register_operand" "=dx,ax,ax,dax,xy,!dax")
+ (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0,0,0,dax")
+ (match_operand:SI 2 "nonmemory_operand" "J,J,L,daxi,i,dax")))]
""
- "@
- inc %0
- inc %0
- inc4 %0
- add %2,%0
- add %2,%0
- mov %2,%0\;add %1,%0"
+ "*
+{
+ switch (which_alternative)
+ {
+ case 0:
+ case 1:
+ return \"inc %0\";
+ case 2:
+ return \"inc4 %0\";
+ case 3:
+ case 4:
+ return \"add %2,%0\";
+ case 5:
+ /* I'm not sure if this can happen or not. Might as well be prepared
+ and generate the best possible code if it does happen. */
+ if (true_regnum (operands[0]) == true_regnum (operands[1]))
+ return \"add %2,%0\";
+ if (true_regnum (operands[0]) == true_regnum (operands[2]))
+ return \"add %1,%0\";
+
+ /* We have to copy one of the sources into the destination, then add
+ the other source to the destination.
+
+ Carefully select which source to copy to the destination; a naive
+ implementation will waste a byte when the source classes are different
+ and the destination is an address register. Selecting the lowest
+ cost register copy will optimize this sequence. */
+ if (REGNO_REG_CLASS (true_regnum (operands[1]))
+ == REGNO_REG_CLASS (true_regnum (operands[0])))
+ return \"mov %1,%0\;add %2,%0\";
+ return \"mov %2,%0\;add %1,%0\";
+ }
+}"
[(set_attr "cc" "set_zn,none_0hit,none_0hit,set_zn,none_0hit,set_zn")])
;; ----------------------------------------------------------------------
;; SUBTRACT INSTRUCTIONS
;; ----------------------------------------------------------------------
-(define_insn "subsi3"
- [(set (match_operand:SI 0 "register_operand" "=da")
+(define_expand "subsi3"
+ [(set (match_operand:SI 0 "register_operand" "")
+ (minus:SI (match_operand:SI 1 "register_operand" "")
+ (match_operand:SI 2 "nonmemory_operand" "")))]
+ ""
+ "")
+
+(define_insn ""
+ [(set (match_operand:SI 0 "register_operand" "=dax")
(minus:SI (match_operand:SI 1 "register_operand" "0")
- (match_operand:SI 2 "nonmemory_operand" "dai")))]
+ (match_operand:SI 2 "nonmemory_operand" "daxi")))]
""
"sub %2,%0"
[(set_attr "cc" "set_zn")])
;; ----------------------------------------------------------------------
(define_insn "mulsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand" "=dx")
(mult:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "register_operand" "d")))]
+ (match_operand:SI 2 "register_operand" "dx")))]
""
"*
{
[(set_attr "cc" "set_zn")])
(define_insn "udivmodsi4"
- [(set (match_operand:SI 0 "general_operand" "=d")
+ [(set (match_operand:SI 0 "general_operand" "=dx")
(udiv:SI (match_operand:SI 1 "general_operand" "0")
- (match_operand:SI 2 "general_operand" "d")))
+ (match_operand:SI 2 "general_operand" "dx")))
(set (match_operand:SI 3 "general_operand" "=&d")
(umod:SI (match_dup 1) (match_dup 2)))]
""
[(set_attr "cc" "set_zn")])
(define_insn "divmodsi4"
- [(set (match_operand:SI 0 "general_operand" "=d")
+ [(set (match_operand:SI 0 "general_operand" "=dx")
(div:SI (match_operand:SI 1 "general_operand" "0")
- (match_operand:SI 2 "general_operand" "d")))
+ (match_operand:SI 2 "general_operand" "dx")))
(set (match_operand:SI 3 "general_operand" "=d")
(mod:SI (match_dup 1) (match_dup 2)))]
""
;; ----------------------------------------------------------------------
(define_insn "andsi3"
- [(set (match_operand:SI 0 "register_operand" "=d,d")
+ [(set (match_operand:SI 0 "register_operand" "=dx,dx")
(and:SI (match_operand:SI 1 "register_operand" "%0,0")
- (match_operand:SI 2 "nonmemory_operand" "N,di")))]
+ (match_operand:SI 2 "nonmemory_operand" "N,dxi")))]
""
"*
{
;; ----------------------------------------------------------------------
(define_insn "iorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand" "=dx")
(ior:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "nonmemory_operand" "di")))]
+ (match_operand:SI 2 "nonmemory_operand" "dxi")))]
""
"or %2,%0"
[(set_attr "cc" "set_znv")])
;; ----------------------------------------------------------------------
(define_insn "xorsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand" "=dx")
(xor:SI (match_operand:SI 1 "register_operand" "%0")
- (match_operand:SI 2 "nonmemory_operand" "di")))]
+ (match_operand:SI 2 "nonmemory_operand" "dxi")))]
""
"xor %2,%0"
[(set_attr "cc" "set_znv")])
;; ----------------------------------------------------------------------
(define_insn "one_cmplsi2"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand" "=dx")
(not:SI (match_operand:SI 1 "register_operand" "0")))]
""
"not %0"
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
+ (zero_extract:SI (match_operand:SI 0 "register_operand" "dx")
(match_operand 1 "const_int_operand" "")
(match_operand 2 "const_int_operand" "")))]
""
(define_insn ""
[(set (cc0)
- (zero_extract:SI (match_operand:QI 0 "general_operand" "R,d")
+ (zero_extract:SI (match_operand:QI 0 "general_operand" "R,dx")
(match_operand 1 "const_int_operand" "")
(match_operand 2 "const_int_operand" "")))]
"mask_ok_for_mem_btst (INTVAL (operands[1]), INTVAL (operands[2]))"
[(set_attr "cc" "set_znv")])
(define_insn ""
- [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "d")
+ [(set (cc0) (and:SI (match_operand:SI 0 "register_operand" "dx")
(match_operand:SI 1 "const_int_operand" "")))]
""
"btst %1,%0"
(define_insn ""
[(set (cc0)
(and:SI
- (subreg:SI (match_operand:QI 0 "general_operand" "R,d") 0)
+ (subreg:SI (match_operand:QI 0 "general_operand" "R,dx") 0)
(match_operand:SI 1 "const_8bit_operand" "")))]
""
"@
}")
(define_insn "call_value_internal"
- [(set (match_operand 0 "" "=da")
+ [(set (match_operand 0 "" "=dax")
(call (mem:QI (match_operand:SI 1 "call_address_operand" "aS"))
(match_operand:SI 2 "general_operand" "g")))]
""
;; ----------------------------------------------------------------------
(define_insn "zero_extendqisi2"
- [(set (match_operand:SI 0 "general_operand" "=d,d,d")
+ [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
(zero_extend:SI
(match_operand:QI 1 "general_operand" "0,d,m")))]
""
[(set_attr "cc" "none_0hit")])
(define_insn "zero_extendhisi2"
- [(set (match_operand:SI 0 "general_operand" "=d,d,d")
+ [(set (match_operand:SI 0 "general_operand" "=dx,dx,dx")
(zero_extend:SI
- (match_operand:HI 1 "general_operand" "0,d,m")))]
+ (match_operand:HI 1 "general_operand" "0,dx,m")))]
""
"@
exthu %0
;;- sign extension instructions
(define_insn "extendqisi2"
- [(set (match_operand:SI 0 "general_operand" "=d,d")
+ [(set (match_operand:SI 0 "general_operand" "=dx,dx")
(sign_extend:SI
- (match_operand:QI 1 "general_operand" "0,d")))]
+ (match_operand:QI 1 "general_operand" "0,dx")))]
""
"@
extb %0
[(set_attr "cc" "none_0hit")])
(define_insn "extendhisi2"
- [(set (match_operand:SI 0 "general_operand" "=d,d")
+ [(set (match_operand:SI 0 "general_operand" "=dx,dx")
(sign_extend:SI
- (match_operand:HI 1 "general_operand" "0,d")))]
+ (match_operand:HI 1 "general_operand" "0,dx")))]
""
"@
exth %0
;; ----------------------------------------------------------------------
(define_insn "ashlsi3"
- [(set (match_operand:SI 0 "register_operand" "=da,d,d,d,d")
+ [(set (match_operand:SI 0 "register_operand" "=dax,dx,dx,dx,dx")
(ashift:SI
(match_operand:SI 1 "register_operand" "0,0,0,0,0")
- (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,di")))]
+ (match_operand:QI 2 "nonmemory_operand" "J,K,M,L,dxi")))]
""
"@
add %0,%0
[(set_attr "cc" "set_zn")])
(define_insn "lshrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand" "=dx")
(lshiftrt:SI
(match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "di")))]
+ (match_operand:QI 2 "nonmemory_operand" "dxi")))]
""
"lsr %S2,%0"
[(set_attr "cc" "set_zn")])
(define_insn "ashrsi3"
- [(set (match_operand:SI 0 "register_operand" "=d")
+ [(set (match_operand:SI 0 "register_operand" "=dx")
(ashiftrt:SI
(match_operand:SI 1 "register_operand" "0")
- (match_operand:QI 2 "nonmemory_operand" "di")))]
+ (match_operand:QI 2 "nonmemory_operand" "dxi")))]
""
"asr %S2,%0"
[(set_attr "cc" "set_zn")])
(match_operand:SI 0 "const_int_operand" "i")
(return)]
""
- "ret [d2,d3,a2,a3],%0"
+ "*
+{
+ return \"ret [d2,d3,a2,a3],%0\";
+}"
[(set_attr "cc" "clobber")])
(define_insn "store_movm"
[(const_int 1)]
""
- "movm [d2,d3,a2,a3],(sp)"
+ "*
+{
+ return \"movm [d2,d3,a2,a3],(sp)\";
+}"
[(set_attr "cc" "clobber")])
(define_insn "return"
;; Try to combine consecutive updates of the stack pointer (or any
;; other register for that matter).
(define_peephole
- [(set (match_operand:SI 0 "register_operand" "=dax")
+ [(set (match_operand:SI 0 "register_operand" "=dxay")
(plus:SI (match_dup 0)
(match_operand 1 "const_int_operand" "")))
(set (match_dup 0)
;; This will work on the mn10200 because we can check the ZX flag
;; if the comparison is in HImode.
(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" "d"))
+ [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
(set (pc) (if_then_else (ge (cc0) (const_int 0))
(match_operand 1 "" "")
(pc)))]
[(set_attr "cc" "clobber")])
(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" "d"))
+ [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
(set (pc) (if_then_else (lt (cc0) (const_int 0))
(match_operand 1 "" "")
(pc)))]
[(set_attr "cc" "clobber")])
(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" "d"))
+ [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
(set (pc) (if_then_else (ge (cc0) (const_int 0))
(pc)
(match_operand 1 "" "")))]
[(set_attr "cc" "clobber")])
(define_peephole
- [(set (cc0) (match_operand:SI 0 "register_operand" "d"))
+ [(set (cc0) (match_operand:SI 0 "register_operand" "dx"))
(set (pc) (if_then_else (lt (cc0) (const_int 0))
(pc)
(match_operand 1 "" "")))]