1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
44 #include "target-def.h"
46 /* This is used by GOTaddr2picreg to uniquely identify
48 int mn10300_unspec_int_label_counter;
50 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
51 names are not prefixed by underscores, to tell whether to prefix a
52 label with a plus sign or not, so that the assembler can tell
53 symbol names from register names. */
54 int mn10300_protect_label;
56 /* The selected processor. */
57 enum processor_type mn10300_processor = PROCESSOR_DEFAULT;
59 /* The size of the callee register save area. Right now we save everything
60 on entry since it costs us nothing in code size. It does cost us from a
61 speed standpoint, so we want to optimize this sooner or later. */
62 #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \
63 + 4 * df_regs_ever_live_p (3) \
64 + 4 * df_regs_ever_live_p (6) \
65 + 4 * df_regs_ever_live_p (7) \
66 + 16 * (df_regs_ever_live_p (14) || df_regs_ever_live_p (15) \
67 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)))
70 static bool mn10300_handle_option (size_t, const char *, int);
71 static bool mn10300_legitimate_address_p (enum machine_mode, rtx, bool);
72 static int mn10300_address_cost_1 (rtx, int *);
73 static int mn10300_address_cost (rtx, bool);
74 static bool mn10300_rtx_costs (rtx, int, int, int *, bool);
75 static void mn10300_file_start (void);
76 static bool mn10300_return_in_memory (const_tree, const_tree);
77 static rtx mn10300_builtin_saveregs (void);
78 static void mn10300_va_start (tree, rtx);
79 static rtx mn10300_legitimize_address (rtx, rtx, enum machine_mode);
80 static bool mn10300_pass_by_reference (CUMULATIVE_ARGS *, enum machine_mode,
82 static int mn10300_arg_partial_bytes (CUMULATIVE_ARGS *, enum machine_mode,
84 static unsigned int mn10300_case_values_threshold (void);
85 static void mn10300_encode_section_info (tree, rtx, int);
86 static void mn10300_asm_trampoline_template (FILE *);
87 static void mn10300_trampoline_init (rtx, tree, rtx);
88 static rtx mn10300_function_value (const_tree, const_tree, bool);
89 static rtx mn10300_libcall_value (enum machine_mode, const_rtx);
90 static void mn10300_asm_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, HOST_WIDE_INT, tree);
91 static bool mn10300_can_output_mi_thunk (const_tree, HOST_WIDE_INT, HOST_WIDE_INT, const_tree);
93 /* Initialize the GCC target structure. */
94 #undef TARGET_ASM_ALIGNED_HI_OP
95 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
97 #undef TARGET_LEGITIMIZE_ADDRESS
98 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
100 #undef TARGET_RTX_COSTS
101 #define TARGET_RTX_COSTS mn10300_rtx_costs
102 #undef TARGET_ADDRESS_COST
103 #define TARGET_ADDRESS_COST mn10300_address_cost
105 #undef TARGET_ASM_FILE_START
106 #define TARGET_ASM_FILE_START mn10300_file_start
107 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
108 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
110 #undef TARGET_DEFAULT_TARGET_FLAGS
111 #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0
112 #undef TARGET_HANDLE_OPTION
113 #define TARGET_HANDLE_OPTION mn10300_handle_option
115 #undef TARGET_ENCODE_SECTION_INFO
116 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
118 #undef TARGET_PROMOTE_PROTOTYPES
119 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
120 #undef TARGET_RETURN_IN_MEMORY
121 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
122 #undef TARGET_PASS_BY_REFERENCE
123 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
124 #undef TARGET_CALLEE_COPIES
125 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
126 #undef TARGET_ARG_PARTIAL_BYTES
127 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
129 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
130 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
131 #undef TARGET_EXPAND_BUILTIN_VA_START
132 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
134 #undef TARGET_CASE_VALUES_THRESHOLD
135 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
137 #undef TARGET_LEGITIMATE_ADDRESS_P
138 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
140 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
141 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template
142 #undef TARGET_TRAMPOLINE_INIT
143 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
145 #undef TARGET_FUNCTION_VALUE
146 #define TARGET_FUNCTION_VALUE mn10300_function_value
147 #undef TARGET_LIBCALL_VALUE
148 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
150 #undef TARGET_ASM_OUTPUT_MI_THUNK
151 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
152 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
153 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
155 struct gcc_target targetm = TARGET_INITIALIZER;
157 /* Implement TARGET_HANDLE_OPTION. */
160 mn10300_handle_option (size_t code,
161 const char *arg ATTRIBUTE_UNUSED,
167 mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300;
170 mn10300_processor = (value
172 : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT));
179 /* Implement OVERRIDE_OPTIONS. */
182 mn10300_override_options (void)
185 target_flags &= ~MASK_MULT_BUG;
189 mn10300_file_start (void)
191 default_file_start ();
194 fprintf (asm_out_file, "\t.am33_2\n");
195 else if (TARGET_AM33)
196 fprintf (asm_out_file, "\t.am33\n");
200 /* Print operand X using operand code CODE to assembly language output file
204 print_operand (FILE *file, rtx x, int code)
210 if (cc_status.mdep.fpCC)
212 switch (code == 'b' ? GET_CODE (x)
213 : reverse_condition_maybe_unordered (GET_CODE (x)))
216 fprintf (file, "ne");
219 fprintf (file, "eq");
222 fprintf (file, "ge");
225 fprintf (file, "gt");
228 fprintf (file, "le");
231 fprintf (file, "lt");
234 fprintf (file, "lge");
237 fprintf (file, "uo");
240 fprintf (file, "lg");
243 fprintf (file, "ue");
246 fprintf (file, "uge");
249 fprintf (file, "ug");
252 fprintf (file, "ule");
255 fprintf (file, "ul");
262 /* These are normal and reversed branches. */
263 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
266 fprintf (file, "ne");
269 fprintf (file, "eq");
272 fprintf (file, "ge");
275 fprintf (file, "gt");
278 fprintf (file, "le");
281 fprintf (file, "lt");
284 fprintf (file, "cc");
287 fprintf (file, "hi");
290 fprintf (file, "ls");
293 fprintf (file, "cs");
300 /* This is used for the operand to a call instruction;
301 if it's a REG, enclose it in parens, else output
302 the operand normally. */
303 if (GET_CODE (x) == REG)
306 print_operand (file, x, 0);
310 print_operand (file, x, 0);
314 switch (GET_CODE (x))
318 output_address (XEXP (x, 0));
323 fprintf (file, "fd%d", REGNO (x) - 18);
331 /* These are the least significant word in a 64bit value. */
333 switch (GET_CODE (x))
337 output_address (XEXP (x, 0));
342 fprintf (file, "%s", reg_names[REGNO (x)]);
346 fprintf (file, "%s", reg_names[subreg_regno (x)]);
354 switch (GET_MODE (x))
357 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
358 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
359 fprintf (file, "0x%lx", val[0]);
362 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
363 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
364 fprintf (file, "0x%lx", val[0]);
368 print_operand_address (file,
369 GEN_INT (CONST_DOUBLE_LOW (x)));
380 split_double (x, &low, &high);
381 fprintf (file, "%ld", (long)INTVAL (low));
390 /* Similarly, but for the most significant word. */
392 switch (GET_CODE (x))
396 x = adjust_address (x, SImode, 4);
397 output_address (XEXP (x, 0));
402 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
406 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
414 switch (GET_MODE (x))
417 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
418 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
419 fprintf (file, "0x%lx", val[1]);
425 print_operand_address (file,
426 GEN_INT (CONST_DOUBLE_HIGH (x)));
437 split_double (x, &low, &high);
438 fprintf (file, "%ld", (long)INTVAL (high));
449 if (GET_CODE (XEXP (x, 0)) == REG)
450 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
452 output_address (XEXP (x, 0));
457 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
458 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
462 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
463 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
466 /* For shift counts. The hardware ignores the upper bits of
467 any immediate, but the assembler will flag an out of range
468 shift count as an error. So we mask off the high bits
469 of the immediate here. */
471 if (GET_CODE (x) == CONST_INT)
473 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
479 switch (GET_CODE (x))
483 output_address (XEXP (x, 0));
492 fprintf (file, "%s", reg_names[REGNO (x)]);
496 fprintf (file, "%s", reg_names[subreg_regno (x)]);
499 /* This will only be single precision.... */
505 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
506 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
507 fprintf (file, "0x%lx", val);
517 print_operand_address (file, x);
526 /* Output assembly language output for the address ADDR to FILE. */
529 print_operand_address (FILE *file, rtx addr)
531 switch (GET_CODE (addr))
534 print_operand_address (file, XEXP (addr, 0));
538 print_operand (file, addr, 0);
543 if (REG_P (XEXP (addr, 0))
544 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
545 base = XEXP (addr, 0), index = XEXP (addr, 1);
546 else if (REG_P (XEXP (addr, 1))
547 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
548 base = XEXP (addr, 1), index = XEXP (addr, 0);
551 print_operand (file, index, 0);
553 print_operand (file, base, 0);;
557 output_addr_const (file, addr);
560 output_addr_const (file, addr);
565 /* Count the number of FP registers that have to be saved. */
567 fp_regs_to_save (void)
574 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
575 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
581 /* Print a set of registers in the format required by "movm" and "ret".
582 Register K is saved if bit K of MASK is set. The data and address
583 registers can be stored individually, but the extended registers cannot.
584 We assume that the mask already takes that into account. For instance,
585 bits 14 to 17 must have the same value. */
588 mn10300_print_reg_list (FILE *file, int mask)
596 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
597 if ((mask & (1 << i)) != 0)
601 fputs (reg_names [i], file);
605 if ((mask & 0x3c000) != 0)
607 gcc_assert ((mask & 0x3c000) == 0x3c000);
610 fputs ("exreg1", file);
618 can_use_return_insn (void)
620 /* size includes the fixed stack space needed for function calls. */
621 int size = get_frame_size () + crtl->outgoing_args_size;
623 /* And space for the return pointer. */
624 size += crtl->outgoing_args_size ? 4 : 0;
626 return (reload_completed
628 && !df_regs_ever_live_p (2)
629 && !df_regs_ever_live_p (3)
630 && !df_regs_ever_live_p (6)
631 && !df_regs_ever_live_p (7)
632 && !df_regs_ever_live_p (14)
633 && !df_regs_ever_live_p (15)
634 && !df_regs_ever_live_p (16)
635 && !df_regs_ever_live_p (17)
636 && fp_regs_to_save () == 0
637 && !frame_pointer_needed);
640 /* Returns the set of live, callee-saved registers as a bitmask. The
641 callee-saved extended registers cannot be stored individually, so
642 all of them will be included in the mask if any one of them is used. */
645 mn10300_get_live_callee_saved_regs (void)
651 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
652 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
654 if ((mask & 0x3c000) != 0)
660 /* Generate an instruction that pushes several registers onto the stack.
661 Register K will be saved if bit K in MASK is set. The function does
662 nothing if MASK is zero.
664 To be compatible with the "movm" instruction, the lowest-numbered
665 register must be stored in the lowest slot. If MASK is the set
666 { R1,...,RN }, where R1...RN are ordered least first, the generated
667 instruction will have the form:
670 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
671 (set (mem:SI (plus:SI (reg:SI 9)
675 (set (mem:SI (plus:SI (reg:SI 9)
680 mn10300_gen_multiple_store (int mask)
689 /* Count how many registers need to be saved. */
691 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
692 if ((mask & (1 << i)) != 0)
695 /* We need one PARALLEL element to update the stack pointer and
696 an additional element for each register that is stored. */
697 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
699 /* Create the instruction that updates the stack pointer. */
701 = gen_rtx_SET (SImode,
703 gen_rtx_PLUS (SImode,
705 GEN_INT (-count * 4)));
707 /* Create each store. */
709 for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
710 if ((mask & (1 << i)) != 0)
712 rtx address = gen_rtx_PLUS (SImode,
714 GEN_INT (-pari * 4));
715 XVECEXP(par, 0, pari)
716 = gen_rtx_SET (VOIDmode,
717 gen_rtx_MEM (SImode, address),
718 gen_rtx_REG (SImode, i));
722 par = emit_insn (par);
723 RTX_FRAME_RELATED_P (par) = 1;
728 expand_prologue (void)
732 /* SIZE includes the fixed stack space needed for function calls. */
733 size = get_frame_size () + crtl->outgoing_args_size;
734 size += (crtl->outgoing_args_size ? 4 : 0);
736 /* If we use any of the callee-saved registers, save them now. */
737 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
739 if (TARGET_AM33_2 && fp_regs_to_save ())
741 int num_regs_to_save = fp_regs_to_save (), i;
743 enum { save_sp_merge,
745 save_sp_partial_merge,
747 save_a0_no_merge } strategy;
748 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
752 /* We have several different strategies to save FP registers.
753 We can store them using SP offsets, which is beneficial if
754 there are just a few registers to save, or we can use `a0' in
755 post-increment mode (`a0' is the only call-clobbered address
756 register that is never used to pass information to a
757 function). Furthermore, if we don't need a frame pointer, we
758 can merge the two SP adds into a single one, but this isn't
759 always beneficial; sometimes we can just split the two adds
760 so that we don't exceed a 16-bit constant size. The code
761 below will select which strategy to use, so as to generate
762 smallest code. Ties are broken in favor or shorter sequences
763 (in terms of number of instructions). */
765 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
766 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
767 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
768 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
769 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
770 (((S) >= (L)) ? (SIZE1) * (N) \
771 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
772 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
774 #define SIZE_FMOV_SP_(S,N) \
775 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
776 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
777 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
778 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
780 /* Consider alternative save_sp_merge only if we don't need the
781 frame pointer and size is nonzero. */
782 if (! frame_pointer_needed && size)
784 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
785 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
786 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
787 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
789 if (this_strategy_size < strategy_size)
791 strategy = save_sp_merge;
792 strategy_size = this_strategy_size;
796 /* Consider alternative save_sp_no_merge unconditionally. */
797 /* Insn: add -4 * num_regs_to_save, sp. */
798 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
799 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
800 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
803 /* Insn: add -size, sp. */
804 this_strategy_size += SIZE_ADD_SP (-size);
807 if (this_strategy_size < strategy_size)
809 strategy = save_sp_no_merge;
810 strategy_size = this_strategy_size;
813 /* Consider alternative save_sp_partial_merge only if we don't
814 need a frame pointer and size is reasonably large. */
815 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
817 /* Insn: add -128, sp. */
818 this_strategy_size = SIZE_ADD_SP (-128);
819 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
820 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
824 /* Insn: add 128-size, sp. */
825 this_strategy_size += SIZE_ADD_SP (128 - size);
828 if (this_strategy_size < strategy_size)
830 strategy = save_sp_partial_merge;
831 strategy_size = this_strategy_size;
835 /* Consider alternative save_a0_merge only if we don't need a
836 frame pointer, size is nonzero and the user hasn't
837 changed the calling conventions of a0. */
838 if (! frame_pointer_needed && size
839 && call_really_used_regs [FIRST_ADDRESS_REGNUM]
840 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
842 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
843 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
844 /* Insn: mov sp, a0. */
845 this_strategy_size++;
848 /* Insn: add size, a0. */
849 this_strategy_size += SIZE_ADD_AX (size);
851 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
852 this_strategy_size += 3 * num_regs_to_save;
854 if (this_strategy_size < strategy_size)
856 strategy = save_a0_merge;
857 strategy_size = this_strategy_size;
861 /* Consider alternative save_a0_no_merge if the user hasn't
862 changed the calling conventions of a0. */
863 if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
864 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
866 /* Insn: add -4 * num_regs_to_save, sp. */
867 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
868 /* Insn: mov sp, a0. */
869 this_strategy_size++;
870 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
871 this_strategy_size += 3 * num_regs_to_save;
874 /* Insn: add -size, sp. */
875 this_strategy_size += SIZE_ADD_SP (-size);
878 if (this_strategy_size < strategy_size)
880 strategy = save_a0_no_merge;
881 strategy_size = this_strategy_size;
885 /* Emit the initial SP add, common to all strategies. */
888 case save_sp_no_merge:
889 case save_a0_no_merge:
890 emit_insn (gen_addsi3 (stack_pointer_rtx,
892 GEN_INT (-4 * num_regs_to_save)));
896 case save_sp_partial_merge:
897 emit_insn (gen_addsi3 (stack_pointer_rtx,
900 xsize = 128 - 4 * num_regs_to_save;
906 emit_insn (gen_addsi3 (stack_pointer_rtx,
908 GEN_INT (-(size + 4 * num_regs_to_save))));
909 /* We'll have to adjust FP register saves according to the
912 /* Since we've already created the stack frame, don't do it
913 again at the end of the function. */
921 /* Now prepare register a0, if we have decided to use it. */
925 case save_sp_no_merge:
926 case save_sp_partial_merge:
931 case save_a0_no_merge:
932 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
933 emit_insn (gen_movsi (reg, stack_pointer_rtx));
935 emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize)));
936 reg = gen_rtx_POST_INC (SImode, reg);
943 /* Now actually save the FP registers. */
944 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
945 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
953 /* If we aren't using `a0', use an SP offset. */
956 addr = gen_rtx_PLUS (SImode,
961 addr = stack_pointer_rtx;
966 insn = emit_insn (gen_movsi (gen_rtx_MEM (SImode, addr),
967 gen_rtx_REG (SImode, i)));
969 RTX_FRAME_RELATED_P (insn) = 1;
973 /* Now put the frame pointer into the frame pointer register. */
974 if (frame_pointer_needed)
975 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
977 /* Allocate stack for this frame. */
979 emit_insn (gen_addsi3 (stack_pointer_rtx,
982 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
983 emit_insn (gen_GOTaddr2picreg ());
987 expand_epilogue (void)
991 /* SIZE includes the fixed stack space needed for function calls. */
992 size = get_frame_size () + crtl->outgoing_args_size;
993 size += (crtl->outgoing_args_size ? 4 : 0);
995 if (TARGET_AM33_2 && fp_regs_to_save ())
997 int num_regs_to_save = fp_regs_to_save (), i;
1000 /* We have several options to restore FP registers. We could
1001 load them from SP offsets, but, if there are enough FP
1002 registers to restore, we win if we use a post-increment
1005 /* If we have a frame pointer, it's the best option, because we
1006 already know it has the value we want. */
1007 if (frame_pointer_needed)
1008 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
1009 /* Otherwise, we may use `a1', since it's call-clobbered and
1010 it's never used for return values. But only do so if it's
1011 smaller than using SP offsets. */
1014 enum { restore_sp_post_adjust,
1015 restore_sp_pre_adjust,
1016 restore_sp_partial_adjust,
1017 restore_a1 } strategy;
1018 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
1020 /* Consider using sp offsets before adjusting sp. */
1021 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1022 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
1023 /* If size is too large, we'll have to adjust SP with an
1025 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1027 /* Insn: add size + 4 * num_regs_to_save, sp. */
1028 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
1030 /* If we don't have to restore any non-FP registers,
1031 we'll be able to save one byte by using rets. */
1032 if (! REG_SAVE_BYTES)
1033 this_strategy_size--;
1035 if (this_strategy_size < strategy_size)
1037 strategy = restore_sp_post_adjust;
1038 strategy_size = this_strategy_size;
1041 /* Consider using sp offsets after adjusting sp. */
1042 /* Insn: add size, sp. */
1043 this_strategy_size = SIZE_ADD_SP (size);
1044 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
1045 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
1046 /* We're going to use ret to release the FP registers
1047 save area, so, no savings. */
1049 if (this_strategy_size < strategy_size)
1051 strategy = restore_sp_pre_adjust;
1052 strategy_size = this_strategy_size;
1055 /* Consider using sp offsets after partially adjusting sp.
1056 When size is close to 32Kb, we may be able to adjust SP
1057 with an imm16 add instruction while still using fmov
1059 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1061 /* Insn: add size + 4 * num_regs_to_save
1062 + REG_SAVE_BYTES - 252,sp. */
1063 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
1064 + REG_SAVE_BYTES - 252);
1065 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
1066 this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
1067 - 4 * num_regs_to_save,
1069 /* We're going to use ret to release the FP registers
1070 save area, so, no savings. */
1072 if (this_strategy_size < strategy_size)
1074 strategy = restore_sp_partial_adjust;
1075 strategy_size = this_strategy_size;
1079 /* Consider using a1 in post-increment mode, as long as the
1080 user hasn't changed the calling conventions of a1. */
1081 if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
1082 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1084 /* Insn: mov sp,a1. */
1085 this_strategy_size = 1;
1088 /* Insn: add size,a1. */
1089 this_strategy_size += SIZE_ADD_AX (size);
1091 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1092 this_strategy_size += 3 * num_regs_to_save;
1093 /* If size is large enough, we may be able to save a
1095 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1097 /* Insn: mov a1,sp. */
1098 this_strategy_size += 2;
1100 /* If we don't have to restore any non-FP registers,
1101 we'll be able to save one byte by using rets. */
1102 if (! REG_SAVE_BYTES)
1103 this_strategy_size--;
1105 if (this_strategy_size < strategy_size)
1107 strategy = restore_a1;
1108 strategy_size = this_strategy_size;
1114 case restore_sp_post_adjust:
1117 case restore_sp_pre_adjust:
1118 emit_insn (gen_addsi3 (stack_pointer_rtx,
1124 case restore_sp_partial_adjust:
1125 emit_insn (gen_addsi3 (stack_pointer_rtx,
1127 GEN_INT (size + 4 * num_regs_to_save
1128 + REG_SAVE_BYTES - 252)));
1129 size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1133 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1134 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1136 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1144 /* Adjust the selected register, if any, for post-increment. */
1146 reg = gen_rtx_POST_INC (SImode, reg);
1148 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1149 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
1157 /* If we aren't using a post-increment register, use an
1159 addr = gen_rtx_PLUS (SImode,
1164 addr = stack_pointer_rtx;
1168 emit_insn (gen_movsi (gen_rtx_REG (SImode, i),
1169 gen_rtx_MEM (SImode, addr)));
1172 /* If we were using the restore_a1 strategy and the number of
1173 bytes to be released won't fit in the `ret' byte, copy `a1'
1174 to `sp', to avoid having to use `add' to adjust it. */
1175 if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1177 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1182 /* Maybe cut back the stack, except for the register save area.
1184 If the frame pointer exists, then use the frame pointer to
1187 If the stack size + register save area is more than 255 bytes,
1188 then the stack must be cut back here since the size + register
1189 save size is too big for a ret/retf instruction.
1191 Else leave it alone, it will be cut back as part of the
1192 ret/retf instruction, or there wasn't any stack to begin with.
1194 Under no circumstances should the register save area be
1195 deallocated here, that would leave a window where an interrupt
1196 could occur and trash the register save area. */
1197 if (frame_pointer_needed)
1199 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1202 else if (size + REG_SAVE_BYTES > 255)
1204 emit_insn (gen_addsi3 (stack_pointer_rtx,
1210 /* Adjust the stack and restore callee-saved registers, if any. */
1211 if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1212 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1213 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1214 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1215 || frame_pointer_needed)
1216 emit_jump_insn (gen_return_internal_regs
1217 (GEN_INT (size + REG_SAVE_BYTES)));
1219 emit_jump_insn (gen_return_internal ());
1222 /* Update the condition code from the insn. */
1225 notice_update_cc (rtx body, rtx insn)
1227 switch (get_attr_cc (insn))
1230 /* Insn does not affect CC at all. */
1234 /* Insn does not change CC, but the 0'th operand has been changed. */
1235 if (cc_status.value1 != 0
1236 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
1237 cc_status.value1 = 0;
1241 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
1242 V,C are unusable. */
1244 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
1245 cc_status.value1 = recog_data.operand[0];
1249 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
1252 cc_status.flags |= CC_NO_CARRY;
1253 cc_status.value1 = recog_data.operand[0];
1257 /* The insn is a compare instruction. */
1259 cc_status.value1 = SET_SRC (body);
1260 if (GET_CODE (cc_status.value1) == COMPARE
1261 && GET_MODE (XEXP (cc_status.value1, 0)) == SFmode)
1262 cc_status.mdep.fpCC = 1;
1266 /* Insn doesn't leave CC in a usable state. */
1275 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1276 This function is for MATCH_PARALLEL and so assumes OP is known to be
1277 parallel. If OP is a multiple store, return a mask indicating which
1278 registers it saves. Return 0 otherwise. */
1281 store_multiple_operation (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1289 count = XVECLEN (op, 0);
1293 /* Check that first instruction has the form (set (sp) (plus A B)) */
1294 elt = XVECEXP (op, 0, 0);
1295 if (GET_CODE (elt) != SET
1296 || GET_CODE (SET_DEST (elt)) != REG
1297 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1298 || GET_CODE (SET_SRC (elt)) != PLUS)
1301 /* Check that A is the stack pointer and B is the expected stack size.
1302 For OP to match, each subsequent instruction should push a word onto
1303 the stack. We therefore expect the first instruction to create
1304 COUNT-1 stack slots. */
1305 elt = SET_SRC (elt);
1306 if (GET_CODE (XEXP (elt, 0)) != REG
1307 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1308 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1309 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1312 /* Now go through the rest of the vector elements. They must be
1313 ordered so that the first instruction stores the highest-numbered
1314 register to the highest stack slot and that subsequent instructions
1315 store a lower-numbered register to the slot below.
1317 LAST keeps track of the smallest-numbered register stored so far.
1318 MASK is the set of stored registers. */
1319 last = LAST_EXTENDED_REGNUM + 1;
1321 for (i = 1; i < count; i++)
1323 /* Check that element i is a (set (mem M) R) and that R is valid. */
1324 elt = XVECEXP (op, 0, i);
1325 if (GET_CODE (elt) != SET
1326 || GET_CODE (SET_DEST (elt)) != MEM
1327 || GET_CODE (SET_SRC (elt)) != REG
1328 || REGNO (SET_SRC (elt)) >= last)
1331 /* R was OK, so provisionally add it to MASK. We return 0 in any
1332 case if the rest of the instruction has a flaw. */
1333 last = REGNO (SET_SRC (elt));
1334 mask |= (1 << last);
1336 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1337 elt = XEXP (SET_DEST (elt), 0);
1338 if (GET_CODE (elt) != PLUS
1339 || GET_CODE (XEXP (elt, 0)) != REG
1340 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1341 || GET_CODE (XEXP (elt, 1)) != CONST_INT
1342 || INTVAL (XEXP (elt, 1)) != -i * 4)
1346 /* All or none of the callee-saved extended registers must be in the set. */
1347 if ((mask & 0x3c000) != 0
1348 && (mask & 0x3c000) != 0x3c000)
1354 /* What (if any) secondary registers are needed to move IN with mode
1355 MODE into a register in register class RCLASS.
1357 We might be able to simplify this. */
1359 mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
1364 /* Strip off any SUBREG expressions from IN. Basically we want
1365 to know if IN is a pseudo or (subreg (pseudo)) as those can
1366 turn into MEMs during reload. */
1367 while (GET_CODE (inner) == SUBREG)
1368 inner = SUBREG_REG (inner);
1370 /* Memory loads less than a full word wide can't have an
1371 address or stack pointer destination. They must use
1372 a data register as an intermediate register. */
1373 if ((GET_CODE (in) == MEM
1374 || (GET_CODE (inner) == REG
1375 && REGNO (inner) >= FIRST_PSEUDO_REGISTER))
1376 && (mode == QImode || mode == HImode)
1377 && (rclass == ADDRESS_REGS || rclass == SP_REGS
1378 || rclass == SP_OR_ADDRESS_REGS))
1381 return DATA_OR_EXTENDED_REGS;
1385 /* We can't directly load sp + const_int into a data register;
1386 we must use an address register as an intermediate. */
1387 if (rclass != SP_REGS
1388 && rclass != ADDRESS_REGS
1389 && rclass != SP_OR_ADDRESS_REGS
1390 && rclass != SP_OR_EXTENDED_REGS
1391 && rclass != ADDRESS_OR_EXTENDED_REGS
1392 && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS
1393 && (in == stack_pointer_rtx
1394 || (GET_CODE (in) == PLUS
1395 && (XEXP (in, 0) == stack_pointer_rtx
1396 || XEXP (in, 1) == stack_pointer_rtx))))
1397 return ADDRESS_REGS;
1399 if (GET_CODE (in) == PLUS
1400 && (XEXP (in, 0) == stack_pointer_rtx
1401 || XEXP (in, 1) == stack_pointer_rtx))
1402 return GENERAL_REGS;
1405 && rclass == FP_REGS)
1407 /* We can't load directly into an FP register from a
1408 constant address. */
1409 if (GET_CODE (in) == MEM
1410 && CONSTANT_ADDRESS_P (XEXP (in, 0)))
1411 return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS);
1413 /* Handle case were a pseudo may not get a hard register
1414 but has an equivalent memory location defined. */
1415 if (GET_CODE (inner) == REG
1416 && REGNO (inner) >= FIRST_PSEUDO_REGISTER
1417 && reg_equiv_mem [REGNO (inner)]
1418 && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0)))
1419 return (TARGET_AM33 ? DATA_OR_EXTENDED_REGS : DATA_REGS);
1422 /* Otherwise assume no secondary reloads are needed. */
1427 initial_offset (int from, int to)
1429 /* The difference between the argument pointer and the frame pointer
1430 is the size of the callee register save area. */
1431 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1433 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1434 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1435 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1436 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1437 || fp_regs_to_save ()
1438 || frame_pointer_needed)
1439 return REG_SAVE_BYTES
1440 + 4 * fp_regs_to_save ();
1445 /* The difference between the argument pointer and the stack pointer is
1446 the sum of the size of this function's frame, the callee register save
1447 area, and the fixed stack space needed for function calls (if any). */
1448 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1450 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1451 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1452 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1453 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1454 || fp_regs_to_save ()
1455 || frame_pointer_needed)
1456 return (get_frame_size () + REG_SAVE_BYTES
1457 + 4 * fp_regs_to_save ()
1458 + (crtl->outgoing_args_size
1459 ? crtl->outgoing_args_size + 4 : 0));
1461 return (get_frame_size ()
1462 + (crtl->outgoing_args_size
1463 ? crtl->outgoing_args_size + 4 : 0));
1466 /* The difference between the frame pointer and stack pointer is the sum
1467 of the size of this function's frame and the fixed stack space needed
1468 for function calls (if any). */
1469 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1470 return (get_frame_size ()
1471 + (crtl->outgoing_args_size
1472 ? crtl->outgoing_args_size + 4 : 0));
1477 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1480 mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1482 /* Return values > 8 bytes in length in memory. */
1483 return (int_size_in_bytes (type) > 8
1484 || int_size_in_bytes (type) == 0
1485 || TYPE_MODE (type) == BLKmode);
1488 /* Flush the argument registers to the stack for a stdarg function;
1489 return the new argument pointer. */
1491 mn10300_builtin_saveregs (void)
1494 tree fntype = TREE_TYPE (current_function_decl);
1495 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
1496 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
1497 != void_type_node)))
1498 ? UNITS_PER_WORD : 0);
1499 alias_set_type set = get_varargs_alias_set ();
1502 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
1504 offset = crtl->args.arg_offset_rtx;
1506 mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
1507 set_mem_alias_set (mem, set);
1508 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1510 mem = gen_rtx_MEM (SImode,
1511 plus_constant (crtl->args.internal_arg_pointer, 4));
1512 set_mem_alias_set (mem, set);
1513 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1515 return copy_to_reg (expand_binop (Pmode, add_optab,
1516 crtl->args.internal_arg_pointer,
1517 offset, 0, 0, OPTAB_LIB_WIDEN));
1521 mn10300_va_start (tree valist, rtx nextarg)
1523 nextarg = expand_builtin_saveregs ();
1524 std_expand_builtin_va_start (valist, nextarg);
1527 /* Return true when a parameter should be passed by reference. */
1530 mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1531 enum machine_mode mode, const_tree type,
1532 bool named ATTRIBUTE_UNUSED)
1534 unsigned HOST_WIDE_INT size;
1537 size = int_size_in_bytes (type);
1539 size = GET_MODE_SIZE (mode);
1541 return (size > 8 || size == 0);
1544 /* Return an RTX to represent where a value with mode MODE will be returned
1545 from a function. If the result is NULL_RTX, the argument is pushed. */
1548 function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1549 tree type, int named ATTRIBUTE_UNUSED)
1551 rtx result = NULL_RTX;
1554 /* We only support using 2 data registers as argument registers. */
1557 /* Figure out the size of the object to be passed. */
1558 if (mode == BLKmode)
1559 size = int_size_in_bytes (type);
1561 size = GET_MODE_SIZE (mode);
1563 /* Figure out the alignment of the object to be passed. */
1566 cum->nbytes = (cum->nbytes + 3) & ~3;
1568 /* Don't pass this arg via a register if all the argument registers
1570 if (cum->nbytes > nregs * UNITS_PER_WORD)
1573 /* Don't pass this arg via a register if it would be split between
1574 registers and memory. */
1575 if (type == NULL_TREE
1576 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1579 switch (cum->nbytes / UNITS_PER_WORD)
1582 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM);
1585 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1);
1594 /* Return the number of bytes of registers to use for an argument passed
1595 partially in registers and partially in memory. */
1598 mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1599 tree type, bool named ATTRIBUTE_UNUSED)
1603 /* We only support using 2 data registers as argument registers. */
1606 /* Figure out the size of the object to be passed. */
1607 if (mode == BLKmode)
1608 size = int_size_in_bytes (type);
1610 size = GET_MODE_SIZE (mode);
1612 /* Figure out the alignment of the object to be passed. */
1615 cum->nbytes = (cum->nbytes + 3) & ~3;
1617 /* Don't pass this arg via a register if all the argument registers
1619 if (cum->nbytes > nregs * UNITS_PER_WORD)
1622 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1625 /* Don't pass this arg via a register if it would be split between
1626 registers and memory. */
1627 if (type == NULL_TREE
1628 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1631 return nregs * UNITS_PER_WORD - cum->nbytes;
1634 /* Return the location of the function's value. This will be either
1635 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1636 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1637 we only return the PARALLEL for outgoing values; we do not want
1638 callers relying on this extra copy. */
1641 mn10300_function_value (const_tree valtype,
1642 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1646 enum machine_mode mode = TYPE_MODE (valtype);
1648 if (! POINTER_TYPE_P (valtype))
1649 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1650 else if (! TARGET_PTR_A0D0 || ! outgoing
1651 || cfun->returns_struct)
1652 return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1654 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1656 = gen_rtx_EXPR_LIST (VOIDmode,
1657 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1661 = gen_rtx_EXPR_LIST (VOIDmode,
1662 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1667 /* Implements TARGET_LIBCALL_VALUE. */
1670 mn10300_libcall_value (enum machine_mode mode,
1671 const_rtx fun ATTRIBUTE_UNUSED)
1673 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1676 /* Implements FUNCTION_VALUE_REGNO_P. */
1679 mn10300_function_value_regno_p (const unsigned int regno)
1681 return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
1684 /* Output a tst insn. */
1686 output_tst (rtx operand, rtx insn)
1691 /* We can save a byte if we can find a register which has the value
1693 temp = PREV_INSN (insn);
1694 while (optimize && temp)
1698 /* We allow the search to go through call insns. We record
1699 the fact that we've past a CALL_INSN and reject matches which
1700 use call clobbered registers. */
1701 if (GET_CODE (temp) == CODE_LABEL
1702 || GET_CODE (temp) == JUMP_INSN
1703 || GET_CODE (temp) == BARRIER)
1706 if (GET_CODE (temp) == CALL_INSN)
1709 if (GET_CODE (temp) == NOTE)
1711 temp = PREV_INSN (temp);
1715 /* It must be an insn, see if it is a simple set. */
1716 set = single_set (temp);
1719 temp = PREV_INSN (temp);
1723 /* Are we setting a data register to zero (this does not win for
1726 If it's a call clobbered register, have we past a call?
1728 Make sure the register we find isn't the same as ourself;
1729 the mn10300 can't encode that.
1731 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1732 so the code to detect calls here isn't doing anything useful. */
1733 if (REG_P (SET_DEST (set))
1734 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1735 && !reg_set_between_p (SET_DEST (set), temp, insn)
1736 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1737 == REGNO_REG_CLASS (REGNO (operand)))
1738 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1739 && REGNO (SET_DEST (set)) != REGNO (operand)
1741 || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1744 xoperands[0] = operand;
1745 xoperands[1] = SET_DEST (set);
1747 output_asm_insn ("cmp %1,%0", xoperands);
1751 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1752 && REG_P (SET_DEST (set))
1753 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1754 && !reg_set_between_p (SET_DEST (set), temp, insn)
1755 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1756 != REGNO_REG_CLASS (REGNO (operand)))
1757 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1758 && REGNO (SET_DEST (set)) != REGNO (operand)
1760 || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1763 xoperands[0] = operand;
1764 xoperands[1] = SET_DEST (set);
1766 output_asm_insn ("cmp %1,%0", xoperands);
1769 temp = PREV_INSN (temp);
1775 impossible_plus_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1777 if (GET_CODE (op) != PLUS)
1780 if (XEXP (op, 0) == stack_pointer_rtx
1781 || XEXP (op, 1) == stack_pointer_rtx)
1787 /* Similarly, but when using a zero_extract pattern for a btst where
1788 the source operand might end up in memory. */
1790 mask_ok_for_mem_btst (int len, int bit)
1792 unsigned int mask = 0;
1801 /* MASK must bit into an 8bit value. */
1802 return (((mask & 0xff) == mask)
1803 || ((mask & 0xff00) == mask)
1804 || ((mask & 0xff0000) == mask)
1805 || ((mask & 0xff000000) == mask));
1808 /* Return 1 if X contains a symbolic expression. We know these
1809 expressions will have one of a few well defined forms, so
1810 we need only check those forms. */
1812 symbolic_operand (register rtx op, enum machine_mode mode ATTRIBUTE_UNUSED)
1814 switch (GET_CODE (op))
1821 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1822 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1823 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1829 /* Try machine dependent ways of modifying an illegitimate address
1830 to be legitimate. If we find one, return the new valid address.
1831 This macro is used in only one place: `memory_address' in explow.c.
1833 OLDX is the address as it was before break_out_memory_refs was called.
1834 In some cases it is useful to look at this to decide what needs to be done.
1836 Normally it is always safe for this macro to do nothing. It exists to
1837 recognize opportunities to optimize the output.
1839 But on a few ports with segmented architectures and indexed addressing
1840 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1842 mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1843 enum machine_mode mode ATTRIBUTE_UNUSED)
1845 if (flag_pic && ! legitimate_pic_operand_p (x))
1846 x = legitimize_pic_address (oldx, NULL_RTX);
1848 /* Uh-oh. We might have an address for x[n-100000]. This needs
1849 special handling to avoid creating an indexed memory address
1850 with x-100000 as the base. */
1851 if (GET_CODE (x) == PLUS
1852 && symbolic_operand (XEXP (x, 1), VOIDmode))
1854 /* Ugly. We modify things here so that the address offset specified
1855 by the index expression is computed first, then added to x to form
1856 the entire address. */
1858 rtx regx1, regy1, regy2, y;
1860 /* Strip off any CONST. */
1862 if (GET_CODE (y) == CONST)
1865 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1867 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1868 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1869 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1870 regx1 = force_reg (Pmode,
1871 gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1, regy2));
1872 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1878 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1879 @GOTOFF in `reg'. */
1881 legitimize_pic_address (rtx orig, rtx reg)
1883 if (GET_CODE (orig) == LABEL_REF
1884 || (GET_CODE (orig) == SYMBOL_REF
1885 && (CONSTANT_POOL_ADDRESS_P (orig)
1886 || ! MN10300_GLOBAL_P (orig))))
1889 reg = gen_reg_rtx (Pmode);
1891 emit_insn (gen_symGOTOFF2reg (reg, orig));
1894 else if (GET_CODE (orig) == SYMBOL_REF)
1897 reg = gen_reg_rtx (Pmode);
1899 emit_insn (gen_symGOT2reg (reg, orig));
1905 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1906 isn't protected by a PIC unspec; nonzero otherwise. */
1908 legitimate_pic_operand_p (rtx x)
1910 register const char *fmt;
1913 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1916 if (GET_CODE (x) == UNSPEC
1917 && (XINT (x, 1) == UNSPEC_PIC
1918 || XINT (x, 1) == UNSPEC_GOT
1919 || XINT (x, 1) == UNSPEC_GOTOFF
1920 || XINT (x, 1) == UNSPEC_PLT
1921 || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
1924 fmt = GET_RTX_FORMAT (GET_CODE (x));
1925 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1931 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1932 if (! legitimate_pic_operand_p (XVECEXP (x, i, j)))
1935 else if (fmt[i] == 'e' && ! legitimate_pic_operand_p (XEXP (x, i)))
1942 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1943 legitimate, and FALSE otherwise.
1945 On the mn10300, the value in the address register must be
1946 in the same memory space/segment as the effective address.
1948 This is problematical for reload since it does not understand
1949 that base+index != index+base in a memory reference.
1951 Note it is still possible to use reg+reg addressing modes,
1952 it's just much more difficult. For a discussion of a possible
1953 workaround and solution, see the comments in pa.c before the
1954 function record_unscaled_index_insn_codes. */
1957 mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1959 if (CONSTANT_ADDRESS_P (x)
1960 && (! flag_pic || legitimate_pic_operand_p (x)))
1963 if (RTX_OK_FOR_BASE_P (x, strict))
1967 && GET_CODE (x) == POST_INC
1968 && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1969 && (mode == SImode || mode == SFmode || mode == HImode))
1972 if (GET_CODE (x) == PLUS)
1974 rtx base = 0, index = 0;
1976 if (REG_P (XEXP (x, 0))
1977 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict))
1980 index = XEXP (x, 1);
1983 if (REG_P (XEXP (x, 1))
1984 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict))
1987 index = XEXP (x, 0);
1990 if (base != 0 && index != 0)
1992 if (GET_CODE (index) == CONST_INT)
1994 if (GET_CODE (index) == CONST
1995 && GET_CODE (XEXP (index, 0)) != PLUS
1997 || legitimate_pic_operand_p (index)))
2006 mn10300_address_cost_1 (rtx x, int *unsig)
2008 switch (GET_CODE (x))
2011 switch (REGNO_REG_CLASS (REGNO (x)))
2037 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
2038 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
2043 return mn10300_address_cost (XEXP (x, 0), !optimize_size);
2047 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
2050 if (INTVAL (x) == 0)
2052 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
2054 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
2056 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
2072 mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
2075 return mn10300_address_cost_1 (x, &s);
2079 mn10300_rtx_costs (rtx x, int code, int outer_code, int *total, bool speed ATTRIBUTE_UNUSED)
2084 /* Zeros are extremely cheap. */
2085 if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE))
2087 /* If it fits in 8 bits, then it's still relatively cheap. */
2088 else if (INT_8_BITS (INTVAL (x)))
2090 /* This is the "base" cost, includes constants where either the
2091 upper or lower 16bits are all zeros. */
2092 else if (INT_16_BITS (INTVAL (x))
2093 || (INTVAL (x) & 0xffff) == 0
2094 || (INTVAL (x) & 0xffff0000) == 0)
2103 /* These are more costly than a CONST_INT, but we can relax them,
2104 so they're less costly than a CONST_DOUBLE. */
2109 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
2110 so their cost is very high. */
2115 /* This is cheap, we can use btst. */
2116 if (outer_code == COMPARE)
2120 /* ??? This probably needs more work. */
2132 /* Check whether a constant used to initialize a DImode or DFmode can
2133 use a clr instruction. The code here must be kept in sync with
2137 mn10300_wide_const_load_uses_clr (rtx operands[2])
2141 if (GET_CODE (operands[0]) != REG
2142 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
2145 switch (GET_CODE (operands[1]))
2150 split_double (operands[1], &low, &high);
2151 val[0] = INTVAL (low);
2152 val[1] = INTVAL (high);
2157 if (GET_MODE (operands[1]) == DFmode)
2161 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
2162 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
2164 else if (GET_MODE (operands[1]) == VOIDmode
2165 || GET_MODE (operands[1]) == DImode)
2167 val[0] = CONST_DOUBLE_LOW (operands[1]);
2168 val[1] = CONST_DOUBLE_HIGH (operands[1]);
2176 return val[0] == 0 || val[1] == 0;
2178 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2179 may access it using GOTOFF instead of GOT. */
2182 mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
2186 if (GET_CODE (rtl) != MEM)
2188 symbol = XEXP (rtl, 0);
2189 if (GET_CODE (symbol) != SYMBOL_REF)
2193 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
2196 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2197 and readonly data size. So we crank up the case threshold value to
2198 encourage a series of if/else comparisons to implement many small switch
2199 statements. In theory, this value could be increased much more if we
2200 were solely optimizing for space, but we keep it "reasonable" to avoid
2201 serious code efficiency lossage. */
2203 unsigned int mn10300_case_values_threshold (void)
2208 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. */
2211 mn10300_asm_trampoline_template (FILE *f)
2213 fprintf (f, "\tadd -4,sp\n");
2214 fprintf (f, "\t.long 0x0004fffa\n");
2215 fprintf (f, "\tmov (0,sp),a0\n");
2216 fprintf (f, "\tadd 4,sp\n");
2217 fprintf (f, "\tmov (13,a0),a1\n");
2218 fprintf (f, "\tmov (17,a0),a0\n");
2219 fprintf (f, "\tjmp (a0)\n");
2220 fprintf (f, "\t.long 0\n");
2221 fprintf (f, "\t.long 0\n");
2224 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2227 mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2229 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2232 emit_block_move (m_tramp, assemble_trampoline_template (),
2233 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2235 mem = adjust_address (m_tramp, SImode, 0x14);
2236 emit_move_insn (mem, chain_value);
2237 mem = adjust_address (m_tramp, SImode, 0x18);
2238 emit_move_insn (mem, fnaddr);
2241 /* Output the assembler code for a C++ thunk function.
2242 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2243 is the decl for the target function. DELTA is an immediate constant
2244 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2245 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2246 additionally added to THIS. Finally jump to the entry point of
2250 mn10300_asm_output_mi_thunk (FILE * file,
2251 tree thunk_fndecl ATTRIBUTE_UNUSED,
2252 HOST_WIDE_INT delta,
2253 HOST_WIDE_INT vcall_offset,
2258 /* Get the register holding the THIS parameter. Handle the case
2259 where there is a hidden first argument for a returned structure. */
2260 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
2261 _this = reg_names [FIRST_ARGUMENT_REGNUM + 1];
2263 _this = reg_names [FIRST_ARGUMENT_REGNUM];
2265 fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START);
2268 fprintf (file, "\tadd %d, %s\n", (int) delta, _this);
2272 const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1];
2274 fprintf (file, "\tmov %s, %s\n", _this, scratch);
2275 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2276 fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch);
2277 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2278 fprintf (file, "\tadd %s, %s\n", scratch, _this);
2281 fputs ("\tjmp ", file);
2282 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2286 /* Return true if mn10300_output_mi_thunk would be able to output the
2287 assembler code for the thunk function specified by the arguments
2288 it is passed, and false otherwise. */
2291 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
2292 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
2293 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2294 const_tree function ATTRIBUTE_UNUSED)