1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004,
3 2005, 2006, 2007, 2008, 2009, 2010 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3, or (at your option)
13 GCC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
29 #include "hard-reg-set.h"
30 #include "insn-config.h"
31 #include "conditions.h"
33 #include "insn-attr.h"
41 #include "diagnostic-core.h"
45 #include "target-def.h"
48 /* This is used by GOTaddr2picreg to uniquely identify
50 int mn10300_unspec_int_label_counter;
52 /* This is used in the am33_2.0-linux-gnu port, in which global symbol
53 names are not prefixed by underscores, to tell whether to prefix a
54 label with a plus sign or not, so that the assembler can tell
55 symbol names from register names. */
56 int mn10300_protect_label;
58 /* The selected processor. */
59 enum processor_type mn10300_processor = PROCESSOR_DEFAULT;
61 /* The size of the callee register save area. Right now we save everything
62 on entry since it costs us nothing in code size. It does cost us from a
63 speed standpoint, so we want to optimize this sooner or later. */
64 #define REG_SAVE_BYTES (4 * df_regs_ever_live_p (2) \
65 + 4 * df_regs_ever_live_p (3) \
66 + 4 * df_regs_ever_live_p (6) \
67 + 4 * df_regs_ever_live_p (7) \
68 + 16 * (df_regs_ever_live_p (14) \
69 || df_regs_ever_live_p (15) \
70 || df_regs_ever_live_p (16) \
71 || df_regs_ever_live_p (17)))
73 static int mn10300_address_cost (rtx, bool);
75 /* Implement TARGET_OPTION_OPTIMIZATION_TABLE. */
76 static const struct default_options mn10300_option_optimization_table[] =
78 { OPT_LEVELS_1_PLUS, OPT_fomit_frame_pointer, NULL, 1 },
79 { OPT_LEVELS_NONE, 0, NULL, 0 }
82 /* Implement TARGET_HANDLE_OPTION. */
85 mn10300_handle_option (size_t code,
86 const char *arg ATTRIBUTE_UNUSED,
92 mn10300_processor = value ? PROCESSOR_AM33 : PROCESSOR_MN10300;
95 mn10300_processor = (value
97 : MIN (PROCESSOR_AM33, PROCESSOR_DEFAULT));
104 /* Implement TARGET_OPTION_OVERRIDE. */
107 mn10300_option_override (void)
110 target_flags &= ~MASK_MULT_BUG;
114 mn10300_file_start (void)
116 default_file_start ();
119 fprintf (asm_out_file, "\t.am33_2\n");
120 else if (TARGET_AM33)
121 fprintf (asm_out_file, "\t.am33\n");
124 /* Print operand X using operand code CODE to assembly language output file
128 mn10300_print_operand (FILE *file, rtx x, int code)
134 if (GET_MODE (XEXP (x, 0)) == CC_FLOATmode)
136 switch (code == 'b' ? GET_CODE (x)
137 : reverse_condition_maybe_unordered (GET_CODE (x)))
140 fprintf (file, "ne");
143 fprintf (file, "eq");
146 fprintf (file, "ge");
149 fprintf (file, "gt");
152 fprintf (file, "le");
155 fprintf (file, "lt");
158 fprintf (file, "lge");
161 fprintf (file, "uo");
164 fprintf (file, "lg");
167 fprintf (file, "ue");
170 fprintf (file, "uge");
173 fprintf (file, "ug");
176 fprintf (file, "ule");
179 fprintf (file, "ul");
186 /* These are normal and reversed branches. */
187 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
190 fprintf (file, "ne");
193 fprintf (file, "eq");
196 fprintf (file, "ge");
199 fprintf (file, "gt");
202 fprintf (file, "le");
205 fprintf (file, "lt");
208 fprintf (file, "cc");
211 fprintf (file, "hi");
214 fprintf (file, "ls");
217 fprintf (file, "cs");
224 /* This is used for the operand to a call instruction;
225 if it's a REG, enclose it in parens, else output
226 the operand normally. */
230 mn10300_print_operand (file, x, 0);
234 mn10300_print_operand (file, x, 0);
238 switch (GET_CODE (x))
242 output_address (XEXP (x, 0));
247 fprintf (file, "fd%d", REGNO (x) - 18);
255 /* These are the least significant word in a 64bit value. */
257 switch (GET_CODE (x))
261 output_address (XEXP (x, 0));
266 fprintf (file, "%s", reg_names[REGNO (x)]);
270 fprintf (file, "%s", reg_names[subreg_regno (x)]);
278 switch (GET_MODE (x))
281 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
282 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
283 fprintf (file, "0x%lx", val[0]);
286 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
287 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
288 fprintf (file, "0x%lx", val[0]);
292 mn10300_print_operand_address (file,
293 GEN_INT (CONST_DOUBLE_LOW (x)));
304 split_double (x, &low, &high);
305 fprintf (file, "%ld", (long)INTVAL (low));
314 /* Similarly, but for the most significant word. */
316 switch (GET_CODE (x))
320 x = adjust_address (x, SImode, 4);
321 output_address (XEXP (x, 0));
326 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
330 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
338 switch (GET_MODE (x))
341 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
342 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
343 fprintf (file, "0x%lx", val[1]);
349 mn10300_print_operand_address (file,
350 GEN_INT (CONST_DOUBLE_HIGH (x)));
361 split_double (x, &low, &high);
362 fprintf (file, "%ld", (long)INTVAL (high));
373 if (REG_P ((XEXP (x, 0))))
374 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), const0_rtx));
376 output_address (XEXP (x, 0));
381 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
382 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
386 gcc_assert (INTVAL (x) >= -128 && INTVAL (x) <= 255);
387 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
390 /* For shift counts. The hardware ignores the upper bits of
391 any immediate, but the assembler will flag an out of range
392 shift count as an error. So we mask off the high bits
393 of the immediate here. */
395 if (CONST_INT_P ((x)))
397 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
403 switch (GET_CODE (x))
407 output_address (XEXP (x, 0));
416 fprintf (file, "%s", reg_names[REGNO (x)]);
420 fprintf (file, "%s", reg_names[subreg_regno (x)]);
423 /* This will only be single precision.... */
429 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
430 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
431 fprintf (file, "0x%lx", val);
441 mn10300_print_operand_address (file, x);
450 /* Output assembly language output for the address ADDR to FILE. */
453 mn10300_print_operand_address (FILE *file, rtx addr)
455 switch (GET_CODE (addr))
458 mn10300_print_operand_address (file, XEXP (addr, 0));
462 mn10300_print_operand (file, addr, 0);
467 if (REG_P (XEXP (addr, 0))
468 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
469 base = XEXP (addr, 0), index = XEXP (addr, 1);
470 else if (REG_P (XEXP (addr, 1))
471 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
472 base = XEXP (addr, 1), index = XEXP (addr, 0);
475 mn10300_print_operand (file, index, 0);
477 mn10300_print_operand (file, base, 0);;
481 output_addr_const (file, addr);
484 output_addr_const (file, addr);
489 /* Count the number of FP registers that have to be saved. */
491 fp_regs_to_save (void)
498 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
499 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
505 /* Print a set of registers in the format required by "movm" and "ret".
506 Register K is saved if bit K of MASK is set. The data and address
507 registers can be stored individually, but the extended registers cannot.
508 We assume that the mask already takes that into account. For instance,
509 bits 14 to 17 must have the same value. */
512 mn10300_print_reg_list (FILE *file, int mask)
520 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
521 if ((mask & (1 << i)) != 0)
525 fputs (reg_names [i], file);
529 if ((mask & 0x3c000) != 0)
531 gcc_assert ((mask & 0x3c000) == 0x3c000);
534 fputs ("exreg1", file);
542 mn10300_can_use_return_insn (void)
544 /* size includes the fixed stack space needed for function calls. */
545 int size = get_frame_size () + crtl->outgoing_args_size;
547 /* And space for the return pointer. */
548 size += crtl->outgoing_args_size ? 4 : 0;
550 return (reload_completed
552 && !df_regs_ever_live_p (2)
553 && !df_regs_ever_live_p (3)
554 && !df_regs_ever_live_p (6)
555 && !df_regs_ever_live_p (7)
556 && !df_regs_ever_live_p (14)
557 && !df_regs_ever_live_p (15)
558 && !df_regs_ever_live_p (16)
559 && !df_regs_ever_live_p (17)
560 && fp_regs_to_save () == 0
561 && !frame_pointer_needed);
564 /* Returns the set of live, callee-saved registers as a bitmask. The
565 callee-saved extended registers cannot be stored individually, so
566 all of them will be included in the mask if any one of them is used. */
569 mn10300_get_live_callee_saved_regs (void)
575 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
576 if (df_regs_ever_live_p (i) && ! call_really_used_regs[i])
578 if ((mask & 0x3c000) != 0)
587 RTX_FRAME_RELATED_P (r) = 1;
591 /* Generate an instruction that pushes several registers onto the stack.
592 Register K will be saved if bit K in MASK is set. The function does
593 nothing if MASK is zero.
595 To be compatible with the "movm" instruction, the lowest-numbered
596 register must be stored in the lowest slot. If MASK is the set
597 { R1,...,RN }, where R1...RN are ordered least first, the generated
598 instruction will have the form:
601 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
602 (set (mem:SI (plus:SI (reg:SI 9)
606 (set (mem:SI (plus:SI (reg:SI 9)
611 mn10300_gen_multiple_store (int mask)
620 /* Count how many registers need to be saved. */
622 for (i = 0; i <= LAST_EXTENDED_REGNUM; i++)
623 if ((mask & (1 << i)) != 0)
626 /* We need one PARALLEL element to update the stack pointer and
627 an additional element for each register that is stored. */
628 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
630 /* Create the instruction that updates the stack pointer. */
632 = F (gen_rtx_SET (SImode,
634 gen_rtx_PLUS (SImode,
636 GEN_INT (-count * 4))));
638 /* Create each store. */
640 for (i = LAST_EXTENDED_REGNUM; i >= 0; i--)
641 if ((mask & (1 << i)) != 0)
643 rtx address = gen_rtx_PLUS (SImode,
645 GEN_INT (-pari * 4));
646 XVECEXP(par, 0, pari)
647 = F (gen_rtx_SET (VOIDmode,
648 gen_rtx_MEM (SImode, address),
649 gen_rtx_REG (SImode, i)));
658 mn10300_expand_prologue (void)
662 /* SIZE includes the fixed stack space needed for function calls. */
663 size = get_frame_size () + crtl->outgoing_args_size;
664 size += (crtl->outgoing_args_size ? 4 : 0);
666 /* If we use any of the callee-saved registers, save them now. */
667 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
669 if (TARGET_AM33_2 && fp_regs_to_save ())
671 int num_regs_to_save = fp_regs_to_save (), i;
677 save_sp_partial_merge,
681 unsigned int strategy_size = (unsigned)-1, this_strategy_size;
684 /* We have several different strategies to save FP registers.
685 We can store them using SP offsets, which is beneficial if
686 there are just a few registers to save, or we can use `a0' in
687 post-increment mode (`a0' is the only call-clobbered address
688 register that is never used to pass information to a
689 function). Furthermore, if we don't need a frame pointer, we
690 can merge the two SP adds into a single one, but this isn't
691 always beneficial; sometimes we can just split the two adds
692 so that we don't exceed a 16-bit constant size. The code
693 below will select which strategy to use, so as to generate
694 smallest code. Ties are broken in favor or shorter sequences
695 (in terms of number of instructions). */
697 #define SIZE_ADD_AX(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
698 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 2)
699 #define SIZE_ADD_SP(S) ((((S) >= (1 << 15)) || ((S) < -(1 << 15))) ? 6 \
700 : (((S) >= (1 << 7)) || ((S) < -(1 << 7))) ? 4 : 3)
701 #define SIZE_FMOV_LIMIT(S,N,L,SIZE1,SIZE2,ELSE) \
702 (((S) >= (L)) ? (SIZE1) * (N) \
703 : ((S) + 4 * (N) >= (L)) ? (((L) - (S)) / 4 * (SIZE2) \
704 + ((S) + 4 * (N) - (L)) / 4 * (SIZE1)) \
706 #define SIZE_FMOV_SP_(S,N) \
707 (SIZE_FMOV_LIMIT ((S), (N), (1 << 24), 7, 6, \
708 SIZE_FMOV_LIMIT ((S), (N), (1 << 8), 6, 4, \
709 (S) ? 4 * (N) : 3 + 4 * ((N) - 1))))
710 #define SIZE_FMOV_SP(S,N) (SIZE_FMOV_SP_ ((unsigned HOST_WIDE_INT)(S), (N)))
712 /* Consider alternative save_sp_merge only if we don't need the
713 frame pointer and size is nonzero. */
714 if (! frame_pointer_needed && size)
716 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
717 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
718 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
719 this_strategy_size += SIZE_FMOV_SP (size, num_regs_to_save);
721 if (this_strategy_size < strategy_size)
723 strategy = save_sp_merge;
724 strategy_size = this_strategy_size;
728 /* Consider alternative save_sp_no_merge unconditionally. */
729 /* Insn: add -4 * num_regs_to_save, sp. */
730 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
731 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
732 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
735 /* Insn: add -size, sp. */
736 this_strategy_size += SIZE_ADD_SP (-size);
739 if (this_strategy_size < strategy_size)
741 strategy = save_sp_no_merge;
742 strategy_size = this_strategy_size;
745 /* Consider alternative save_sp_partial_merge only if we don't
746 need a frame pointer and size is reasonably large. */
747 if (! frame_pointer_needed && size + 4 * num_regs_to_save > 128)
749 /* Insn: add -128, sp. */
750 this_strategy_size = SIZE_ADD_SP (-128);
751 /* Insn: fmov fs#, (##, sp), for each fs# to be saved. */
752 this_strategy_size += SIZE_FMOV_SP (128 - 4 * num_regs_to_save,
756 /* Insn: add 128-size, sp. */
757 this_strategy_size += SIZE_ADD_SP (128 - size);
760 if (this_strategy_size < strategy_size)
762 strategy = save_sp_partial_merge;
763 strategy_size = this_strategy_size;
767 /* Consider alternative save_a0_merge only if we don't need a
768 frame pointer, size is nonzero and the user hasn't
769 changed the calling conventions of a0. */
770 if (! frame_pointer_needed && size
771 && call_really_used_regs [FIRST_ADDRESS_REGNUM]
772 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
774 /* Insn: add -(size + 4 * num_regs_to_save), sp. */
775 this_strategy_size = SIZE_ADD_SP (-(size + 4 * num_regs_to_save));
776 /* Insn: mov sp, a0. */
777 this_strategy_size++;
780 /* Insn: add size, a0. */
781 this_strategy_size += SIZE_ADD_AX (size);
783 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
784 this_strategy_size += 3 * num_regs_to_save;
786 if (this_strategy_size < strategy_size)
788 strategy = save_a0_merge;
789 strategy_size = this_strategy_size;
793 /* Consider alternative save_a0_no_merge if the user hasn't
794 changed the calling conventions of a0. */
795 if (call_really_used_regs [FIRST_ADDRESS_REGNUM]
796 && ! fixed_regs[FIRST_ADDRESS_REGNUM])
798 /* Insn: add -4 * num_regs_to_save, sp. */
799 this_strategy_size = SIZE_ADD_SP (-4 * num_regs_to_save);
800 /* Insn: mov sp, a0. */
801 this_strategy_size++;
802 /* Insn: fmov fs#, (a0+), for each fs# to be saved. */
803 this_strategy_size += 3 * num_regs_to_save;
806 /* Insn: add -size, sp. */
807 this_strategy_size += SIZE_ADD_SP (-size);
810 if (this_strategy_size < strategy_size)
812 strategy = save_a0_no_merge;
813 strategy_size = this_strategy_size;
817 /* Emit the initial SP add, common to all strategies. */
820 case save_sp_no_merge:
821 case save_a0_no_merge:
822 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
824 GEN_INT (-4 * num_regs_to_save))));
828 case save_sp_partial_merge:
829 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
832 xsize = 128 - 4 * num_regs_to_save;
838 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
840 GEN_INT (-(size + 4 * num_regs_to_save)))));
841 /* We'll have to adjust FP register saves according to the
844 /* Since we've already created the stack frame, don't do it
845 again at the end of the function. */
853 /* Now prepare register a0, if we have decided to use it. */
857 case save_sp_no_merge:
858 case save_sp_partial_merge:
863 case save_a0_no_merge:
864 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM);
865 F (emit_insn (gen_movsi (reg, stack_pointer_rtx)));
867 F (emit_insn (gen_addsi3 (reg, reg, GEN_INT (xsize))));
868 reg = gen_rtx_POST_INC (SImode, reg);
875 /* Now actually save the FP registers. */
876 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
877 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
885 /* If we aren't using `a0', use an SP offset. */
888 addr = gen_rtx_PLUS (SImode,
893 addr = stack_pointer_rtx;
898 F (emit_insn (gen_movsf (gen_rtx_MEM (SFmode, addr),
899 gen_rtx_REG (SFmode, i))));
903 /* Now put the frame pointer into the frame pointer register. */
904 if (frame_pointer_needed)
905 F (emit_move_insn (frame_pointer_rtx, stack_pointer_rtx));
907 /* Allocate stack for this frame. */
909 F (emit_insn (gen_addsi3 (stack_pointer_rtx,
913 if (flag_pic && df_regs_ever_live_p (PIC_OFFSET_TABLE_REGNUM))
914 emit_insn (gen_GOTaddr2picreg ());
918 mn10300_expand_epilogue (void)
922 /* SIZE includes the fixed stack space needed for function calls. */
923 size = get_frame_size () + crtl->outgoing_args_size;
924 size += (crtl->outgoing_args_size ? 4 : 0);
926 if (TARGET_AM33_2 && fp_regs_to_save ())
928 int num_regs_to_save = fp_regs_to_save (), i;
931 /* We have several options to restore FP registers. We could
932 load them from SP offsets, but, if there are enough FP
933 registers to restore, we win if we use a post-increment
936 /* If we have a frame pointer, it's the best option, because we
937 already know it has the value we want. */
938 if (frame_pointer_needed)
939 reg = gen_rtx_REG (SImode, FRAME_POINTER_REGNUM);
940 /* Otherwise, we may use `a1', since it's call-clobbered and
941 it's never used for return values. But only do so if it's
942 smaller than using SP offsets. */
945 enum { restore_sp_post_adjust,
946 restore_sp_pre_adjust,
947 restore_sp_partial_adjust,
948 restore_a1 } strategy;
949 unsigned int this_strategy_size, strategy_size = (unsigned)-1;
951 /* Consider using sp offsets before adjusting sp. */
952 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
953 this_strategy_size = SIZE_FMOV_SP (size, num_regs_to_save);
954 /* If size is too large, we'll have to adjust SP with an
956 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
958 /* Insn: add size + 4 * num_regs_to_save, sp. */
959 this_strategy_size += SIZE_ADD_SP (size + 4 * num_regs_to_save);
961 /* If we don't have to restore any non-FP registers,
962 we'll be able to save one byte by using rets. */
963 if (! REG_SAVE_BYTES)
964 this_strategy_size--;
966 if (this_strategy_size < strategy_size)
968 strategy = restore_sp_post_adjust;
969 strategy_size = this_strategy_size;
972 /* Consider using sp offsets after adjusting sp. */
973 /* Insn: add size, sp. */
974 this_strategy_size = SIZE_ADD_SP (size);
975 /* Insn: fmov (##,sp),fs#, for each fs# to be restored. */
976 this_strategy_size += SIZE_FMOV_SP (0, num_regs_to_save);
977 /* We're going to use ret to release the FP registers
978 save area, so, no savings. */
980 if (this_strategy_size < strategy_size)
982 strategy = restore_sp_pre_adjust;
983 strategy_size = this_strategy_size;
986 /* Consider using sp offsets after partially adjusting sp.
987 When size is close to 32Kb, we may be able to adjust SP
988 with an imm16 add instruction while still using fmov
990 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
992 /* Insn: add size + 4 * num_regs_to_save
993 + REG_SAVE_BYTES - 252,sp. */
994 this_strategy_size = SIZE_ADD_SP (size + 4 * num_regs_to_save
995 + REG_SAVE_BYTES - 252);
996 /* Insn: fmov (##,sp),fs#, fo each fs# to be restored. */
997 this_strategy_size += SIZE_FMOV_SP (252 - REG_SAVE_BYTES
998 - 4 * num_regs_to_save,
1000 /* We're going to use ret to release the FP registers
1001 save area, so, no savings. */
1003 if (this_strategy_size < strategy_size)
1005 strategy = restore_sp_partial_adjust;
1006 strategy_size = this_strategy_size;
1010 /* Consider using a1 in post-increment mode, as long as the
1011 user hasn't changed the calling conventions of a1. */
1012 if (call_really_used_regs [FIRST_ADDRESS_REGNUM + 1]
1013 && ! fixed_regs[FIRST_ADDRESS_REGNUM+1])
1015 /* Insn: mov sp,a1. */
1016 this_strategy_size = 1;
1019 /* Insn: add size,a1. */
1020 this_strategy_size += SIZE_ADD_AX (size);
1022 /* Insn: fmov (a1+),fs#, for each fs# to be restored. */
1023 this_strategy_size += 3 * num_regs_to_save;
1024 /* If size is large enough, we may be able to save a
1026 if (size + 4 * num_regs_to_save + REG_SAVE_BYTES > 255)
1028 /* Insn: mov a1,sp. */
1029 this_strategy_size += 2;
1031 /* If we don't have to restore any non-FP registers,
1032 we'll be able to save one byte by using rets. */
1033 if (! REG_SAVE_BYTES)
1034 this_strategy_size--;
1036 if (this_strategy_size < strategy_size)
1038 strategy = restore_a1;
1039 strategy_size = this_strategy_size;
1045 case restore_sp_post_adjust:
1048 case restore_sp_pre_adjust:
1049 emit_insn (gen_addsi3 (stack_pointer_rtx,
1055 case restore_sp_partial_adjust:
1056 emit_insn (gen_addsi3 (stack_pointer_rtx,
1058 GEN_INT (size + 4 * num_regs_to_save
1059 + REG_SAVE_BYTES - 252)));
1060 size = 252 - REG_SAVE_BYTES - 4 * num_regs_to_save;
1064 reg = gen_rtx_REG (SImode, FIRST_ADDRESS_REGNUM + 1);
1065 emit_insn (gen_movsi (reg, stack_pointer_rtx));
1067 emit_insn (gen_addsi3 (reg, reg, GEN_INT (size)));
1075 /* Adjust the selected register, if any, for post-increment. */
1077 reg = gen_rtx_POST_INC (SImode, reg);
1079 for (i = FIRST_FP_REGNUM; i <= LAST_FP_REGNUM; ++i)
1080 if (df_regs_ever_live_p (i) && ! call_really_used_regs [i])
1088 /* If we aren't using a post-increment register, use an
1090 addr = gen_rtx_PLUS (SImode,
1095 addr = stack_pointer_rtx;
1099 emit_insn (gen_movsf (gen_rtx_REG (SFmode, i),
1100 gen_rtx_MEM (SFmode, addr)));
1103 /* If we were using the restore_a1 strategy and the number of
1104 bytes to be released won't fit in the `ret' byte, copy `a1'
1105 to `sp', to avoid having to use `add' to adjust it. */
1106 if (! frame_pointer_needed && reg && size + REG_SAVE_BYTES > 255)
1108 emit_move_insn (stack_pointer_rtx, XEXP (reg, 0));
1113 /* Maybe cut back the stack, except for the register save area.
1115 If the frame pointer exists, then use the frame pointer to
1118 If the stack size + register save area is more than 255 bytes,
1119 then the stack must be cut back here since the size + register
1120 save size is too big for a ret/retf instruction.
1122 Else leave it alone, it will be cut back as part of the
1123 ret/retf instruction, or there wasn't any stack to begin with.
1125 Under no circumstances should the register save area be
1126 deallocated here, that would leave a window where an interrupt
1127 could occur and trash the register save area. */
1128 if (frame_pointer_needed)
1130 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
1133 else if (size + REG_SAVE_BYTES > 255)
1135 emit_insn (gen_addsi3 (stack_pointer_rtx,
1141 /* Adjust the stack and restore callee-saved registers, if any. */
1142 if (size || df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1143 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1144 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1145 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1146 || frame_pointer_needed)
1147 emit_jump_insn (gen_return_internal_regs
1148 (GEN_INT (size + REG_SAVE_BYTES)));
1150 emit_jump_insn (gen_return_internal ());
1153 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
1154 This function is for MATCH_PARALLEL and so assumes OP is known to be
1155 parallel. If OP is a multiple store, return a mask indicating which
1156 registers it saves. Return 0 otherwise. */
1159 mn10300_store_multiple_operation (rtx op,
1160 enum machine_mode mode ATTRIBUTE_UNUSED)
1168 count = XVECLEN (op, 0);
1172 /* Check that first instruction has the form (set (sp) (plus A B)) */
1173 elt = XVECEXP (op, 0, 0);
1174 if (GET_CODE (elt) != SET
1175 || (! REG_P (SET_DEST (elt)))
1176 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
1177 || GET_CODE (SET_SRC (elt)) != PLUS)
1180 /* Check that A is the stack pointer and B is the expected stack size.
1181 For OP to match, each subsequent instruction should push a word onto
1182 the stack. We therefore expect the first instruction to create
1183 COUNT-1 stack slots. */
1184 elt = SET_SRC (elt);
1185 if ((! REG_P (XEXP (elt, 0)))
1186 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1187 || (! CONST_INT_P (XEXP (elt, 1)))
1188 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
1191 /* Now go through the rest of the vector elements. They must be
1192 ordered so that the first instruction stores the highest-numbered
1193 register to the highest stack slot and that subsequent instructions
1194 store a lower-numbered register to the slot below.
1196 LAST keeps track of the smallest-numbered register stored so far.
1197 MASK is the set of stored registers. */
1198 last = LAST_EXTENDED_REGNUM + 1;
1200 for (i = 1; i < count; i++)
1202 /* Check that element i is a (set (mem M) R) and that R is valid. */
1203 elt = XVECEXP (op, 0, i);
1204 if (GET_CODE (elt) != SET
1205 || (! MEM_P (SET_DEST (elt)))
1206 || (! REG_P (SET_SRC (elt)))
1207 || REGNO (SET_SRC (elt)) >= last)
1210 /* R was OK, so provisionally add it to MASK. We return 0 in any
1211 case if the rest of the instruction has a flaw. */
1212 last = REGNO (SET_SRC (elt));
1213 mask |= (1 << last);
1215 /* Check that M has the form (plus (sp) (const_int -I*4)) */
1216 elt = XEXP (SET_DEST (elt), 0);
1217 if (GET_CODE (elt) != PLUS
1218 || (! REG_P (XEXP (elt, 0)))
1219 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
1220 || (! CONST_INT_P (XEXP (elt, 1)))
1221 || INTVAL (XEXP (elt, 1)) != -i * 4)
1225 /* All or none of the callee-saved extended registers must be in the set. */
1226 if ((mask & 0x3c000) != 0
1227 && (mask & 0x3c000) != 0x3c000)
1233 /* What (if any) secondary registers are needed to move IN with mode
1234 MODE into a register in register class RCLASS.
1236 We might be able to simplify this. */
1239 mn10300_secondary_reload_class (enum reg_class rclass, enum machine_mode mode,
1244 /* Strip off any SUBREG expressions from IN. Basically we want
1245 to know if IN is a pseudo or (subreg (pseudo)) as those can
1246 turn into MEMs during reload. */
1247 while (GET_CODE (inner) == SUBREG)
1248 inner = SUBREG_REG (inner);
1250 /* Memory loads less than a full word wide can't have an
1251 address or stack pointer destination. They must use
1252 a data register as an intermediate register. */
1255 && REGNO (inner) >= FIRST_PSEUDO_REGISTER))
1256 && (mode == QImode || mode == HImode)
1257 && (rclass == ADDRESS_REGS || rclass == SP_REGS
1258 || rclass == SP_OR_ADDRESS_REGS))
1261 return DATA_OR_EXTENDED_REGS;
1265 /* We can't directly load sp + const_int into a data register;
1266 we must use an address register as an intermediate. */
1267 if (rclass != SP_REGS
1268 && rclass != ADDRESS_REGS
1269 && rclass != SP_OR_ADDRESS_REGS
1270 && rclass != SP_OR_EXTENDED_REGS
1271 && rclass != ADDRESS_OR_EXTENDED_REGS
1272 && rclass != SP_OR_ADDRESS_OR_EXTENDED_REGS
1273 && (in == stack_pointer_rtx
1274 || (GET_CODE (in) == PLUS
1275 && (XEXP (in, 0) == stack_pointer_rtx
1276 || XEXP (in, 1) == stack_pointer_rtx))))
1277 return ADDRESS_REGS;
1280 && rclass == FP_REGS)
1282 /* We can't load directly into an FP register from a
1283 constant address. */
1285 && CONSTANT_ADDRESS_P (XEXP (in, 0)))
1286 return DATA_OR_EXTENDED_REGS;
1288 /* Handle case were a pseudo may not get a hard register
1289 but has an equivalent memory location defined. */
1291 && REGNO (inner) >= FIRST_PSEUDO_REGISTER
1292 && reg_equiv_mem [REGNO (inner)]
1293 && CONSTANT_ADDRESS_P (XEXP (reg_equiv_mem [REGNO (inner)], 0)))
1294 return DATA_OR_EXTENDED_REGS;
1297 /* Otherwise assume no secondary reloads are needed. */
1302 mn10300_initial_offset (int from, int to)
1304 /* The difference between the argument pointer and the frame pointer
1305 is the size of the callee register save area. */
1306 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
1308 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1309 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1310 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1311 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1312 || fp_regs_to_save ()
1313 || frame_pointer_needed)
1314 return REG_SAVE_BYTES
1315 + 4 * fp_regs_to_save ();
1320 /* The difference between the argument pointer and the stack pointer is
1321 the sum of the size of this function's frame, the callee register save
1322 area, and the fixed stack space needed for function calls (if any). */
1323 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1325 if (df_regs_ever_live_p (2) || df_regs_ever_live_p (3)
1326 || df_regs_ever_live_p (6) || df_regs_ever_live_p (7)
1327 || df_regs_ever_live_p (14) || df_regs_ever_live_p (15)
1328 || df_regs_ever_live_p (16) || df_regs_ever_live_p (17)
1329 || fp_regs_to_save ()
1330 || frame_pointer_needed)
1331 return (get_frame_size () + REG_SAVE_BYTES
1332 + 4 * fp_regs_to_save ()
1333 + (crtl->outgoing_args_size
1334 ? crtl->outgoing_args_size + 4 : 0));
1336 return (get_frame_size ()
1337 + (crtl->outgoing_args_size
1338 ? crtl->outgoing_args_size + 4 : 0));
1341 /* The difference between the frame pointer and stack pointer is the sum
1342 of the size of this function's frame and the fixed stack space needed
1343 for function calls (if any). */
1344 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
1345 return (get_frame_size ()
1346 + (crtl->outgoing_args_size
1347 ? crtl->outgoing_args_size + 4 : 0));
1352 /* Worker function for TARGET_RETURN_IN_MEMORY. */
1355 mn10300_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED)
1357 /* Return values > 8 bytes in length in memory. */
1358 return (int_size_in_bytes (type) > 8
1359 || int_size_in_bytes (type) == 0
1360 || TYPE_MODE (type) == BLKmode);
1363 /* Flush the argument registers to the stack for a stdarg function;
1364 return the new argument pointer. */
1366 mn10300_builtin_saveregs (void)
1369 tree fntype = TREE_TYPE (current_function_decl);
1370 int argadj = ((!stdarg_p (fntype))
1371 ? UNITS_PER_WORD : 0);
1372 alias_set_type set = get_varargs_alias_set ();
1375 offset = plus_constant (crtl->args.arg_offset_rtx, argadj);
1377 offset = crtl->args.arg_offset_rtx;
1379 mem = gen_rtx_MEM (SImode, crtl->args.internal_arg_pointer);
1380 set_mem_alias_set (mem, set);
1381 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
1383 mem = gen_rtx_MEM (SImode,
1384 plus_constant (crtl->args.internal_arg_pointer, 4));
1385 set_mem_alias_set (mem, set);
1386 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
1388 return copy_to_reg (expand_binop (Pmode, add_optab,
1389 crtl->args.internal_arg_pointer,
1390 offset, 0, 0, OPTAB_LIB_WIDEN));
1394 mn10300_va_start (tree valist, rtx nextarg)
1396 nextarg = expand_builtin_saveregs ();
1397 std_expand_builtin_va_start (valist, nextarg);
1400 /* Return true when a parameter should be passed by reference. */
1403 mn10300_pass_by_reference (CUMULATIVE_ARGS *cum ATTRIBUTE_UNUSED,
1404 enum machine_mode mode, const_tree type,
1405 bool named ATTRIBUTE_UNUSED)
1407 unsigned HOST_WIDE_INT size;
1410 size = int_size_in_bytes (type);
1412 size = GET_MODE_SIZE (mode);
1414 return (size > 8 || size == 0);
1417 /* Return an RTX to represent where a value with mode MODE will be returned
1418 from a function. If the result is NULL_RTX, the argument is pushed. */
1421 mn10300_function_arg (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1422 tree type, int named ATTRIBUTE_UNUSED)
1424 rtx result = NULL_RTX;
1427 /* We only support using 2 data registers as argument registers. */
1430 /* Figure out the size of the object to be passed. */
1431 if (mode == BLKmode)
1432 size = int_size_in_bytes (type);
1434 size = GET_MODE_SIZE (mode);
1436 /* Figure out the alignment of the object to be passed. */
1439 cum->nbytes = (cum->nbytes + 3) & ~3;
1441 /* Don't pass this arg via a register if all the argument registers
1443 if (cum->nbytes > nregs * UNITS_PER_WORD)
1446 /* Don't pass this arg via a register if it would be split between
1447 registers and memory. */
1448 if (type == NULL_TREE
1449 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1452 switch (cum->nbytes / UNITS_PER_WORD)
1455 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM);
1458 result = gen_rtx_REG (mode, FIRST_ARGUMENT_REGNUM + 1);
1467 /* Return the number of bytes of registers to use for an argument passed
1468 partially in registers and partially in memory. */
1471 mn10300_arg_partial_bytes (CUMULATIVE_ARGS *cum, enum machine_mode mode,
1472 tree type, bool named ATTRIBUTE_UNUSED)
1476 /* We only support using 2 data registers as argument registers. */
1479 /* Figure out the size of the object to be passed. */
1480 if (mode == BLKmode)
1481 size = int_size_in_bytes (type);
1483 size = GET_MODE_SIZE (mode);
1485 /* Figure out the alignment of the object to be passed. */
1488 cum->nbytes = (cum->nbytes + 3) & ~3;
1490 /* Don't pass this arg via a register if all the argument registers
1492 if (cum->nbytes > nregs * UNITS_PER_WORD)
1495 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1498 /* Don't pass this arg via a register if it would be split between
1499 registers and memory. */
1500 if (type == NULL_TREE
1501 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1504 return nregs * UNITS_PER_WORD - cum->nbytes;
1507 /* Return the location of the function's value. This will be either
1508 $d0 for integer functions, $a0 for pointers, or a PARALLEL of both
1509 $d0 and $a0 if the -mreturn-pointer-on-do flag is set. Note that
1510 we only return the PARALLEL for outgoing values; we do not want
1511 callers relying on this extra copy. */
1514 mn10300_function_value (const_tree valtype,
1515 const_tree fn_decl_or_type ATTRIBUTE_UNUSED,
1519 enum machine_mode mode = TYPE_MODE (valtype);
1521 if (! POINTER_TYPE_P (valtype))
1522 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1523 else if (! TARGET_PTR_A0D0 || ! outgoing
1524 || cfun->returns_struct)
1525 return gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM);
1527 rv = gen_rtx_PARALLEL (mode, rtvec_alloc (2));
1529 = gen_rtx_EXPR_LIST (VOIDmode,
1530 gen_rtx_REG (mode, FIRST_ADDRESS_REGNUM),
1534 = gen_rtx_EXPR_LIST (VOIDmode,
1535 gen_rtx_REG (mode, FIRST_DATA_REGNUM),
1540 /* Implements TARGET_LIBCALL_VALUE. */
1543 mn10300_libcall_value (enum machine_mode mode,
1544 const_rtx fun ATTRIBUTE_UNUSED)
1546 return gen_rtx_REG (mode, FIRST_DATA_REGNUM);
1549 /* Implements FUNCTION_VALUE_REGNO_P. */
1552 mn10300_function_value_regno_p (const unsigned int regno)
1554 return (regno == FIRST_DATA_REGNUM || regno == FIRST_ADDRESS_REGNUM);
1557 /* Output a compare insn. */
1560 mn10300_output_cmp (rtx operand, rtx insn)
1565 /* We can save a byte if we can find a register which has the value
1567 temp = PREV_INSN (insn);
1568 while (optimize && temp)
1572 /* We allow the search to go through call insns. We record
1573 the fact that we've past a CALL_INSN and reject matches which
1574 use call clobbered registers. */
1577 || GET_CODE (temp) == BARRIER)
1583 if (GET_CODE (temp) == NOTE)
1585 temp = PREV_INSN (temp);
1589 /* It must be an insn, see if it is a simple set. */
1590 set = single_set (temp);
1593 temp = PREV_INSN (temp);
1597 /* Are we setting a data register to zero (this does not win for
1600 If it's a call clobbered register, have we past a call?
1602 Make sure the register we find isn't the same as ourself;
1603 the mn10300 can't encode that.
1605 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1606 so the code to detect calls here isn't doing anything useful. */
1607 if (REG_P (SET_DEST (set))
1608 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1609 && !reg_set_between_p (SET_DEST (set), temp, insn)
1610 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1611 == REGNO_REG_CLASS (REGNO (operand)))
1612 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1613 && REGNO (SET_DEST (set)) != REGNO (operand)
1615 || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1618 xoperands[0] = operand;
1619 xoperands[1] = SET_DEST (set);
1621 output_asm_insn ("cmp %1,%0", xoperands);
1625 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1626 && REG_P (SET_DEST (set))
1627 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1628 && !reg_set_between_p (SET_DEST (set), temp, insn)
1629 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1630 != REGNO_REG_CLASS (REGNO (operand)))
1631 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1632 && REGNO (SET_DEST (set)) != REGNO (operand)
1634 || ! call_really_used_regs [REGNO (SET_DEST (set))]))
1637 xoperands[0] = operand;
1638 xoperands[1] = SET_DEST (set);
1640 output_asm_insn ("cmp %1,%0", xoperands);
1643 temp = PREV_INSN (temp);
1648 /* Similarly, but when using a zero_extract pattern for a btst where
1649 the source operand might end up in memory. */
1651 mn10300_mask_ok_for_mem_btst (int len, int bit)
1653 unsigned int mask = 0;
1662 /* MASK must bit into an 8bit value. */
1663 return (((mask & 0xff) == mask)
1664 || ((mask & 0xff00) == mask)
1665 || ((mask & 0xff0000) == mask)
1666 || ((mask & 0xff000000) == mask));
1669 /* Return 1 if X contains a symbolic expression. We know these
1670 expressions will have one of a few well defined forms, so
1671 we need only check those forms. */
1674 mn10300_symbolic_operand (rtx op,
1675 enum machine_mode mode ATTRIBUTE_UNUSED)
1677 switch (GET_CODE (op))
1684 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1685 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1686 && CONST_INT_P ((XEXP (op, 1))));
1692 /* Try machine dependent ways of modifying an illegitimate address
1693 to be legitimate. If we find one, return the new valid address.
1694 This macro is used in only one place: `memory_address' in explow.c.
1696 OLDX is the address as it was before break_out_memory_refs was called.
1697 In some cases it is useful to look at this to decide what needs to be done.
1699 Normally it is always safe for this macro to do nothing. It exists to
1700 recognize opportunities to optimize the output.
1702 But on a few ports with segmented architectures and indexed addressing
1703 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1706 mn10300_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED,
1707 enum machine_mode mode ATTRIBUTE_UNUSED)
1709 if (flag_pic && ! mn10300_legitimate_pic_operand_p (x))
1710 x = mn10300_legitimize_pic_address (oldx, NULL_RTX);
1712 /* Uh-oh. We might have an address for x[n-100000]. This needs
1713 special handling to avoid creating an indexed memory address
1714 with x-100000 as the base. */
1715 if (GET_CODE (x) == PLUS
1716 && mn10300_symbolic_operand (XEXP (x, 1), VOIDmode))
1718 /* Ugly. We modify things here so that the address offset specified
1719 by the index expression is computed first, then added to x to form
1720 the entire address. */
1722 rtx regx1, regy1, regy2, y;
1724 /* Strip off any CONST. */
1726 if (GET_CODE (y) == CONST)
1729 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1731 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1732 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1733 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1734 regx1 = force_reg (Pmode,
1735 gen_rtx_fmt_ee (GET_CODE (y), Pmode, regx1,
1737 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1743 /* Convert a non-PIC address in `orig' to a PIC address using @GOT or
1744 @GOTOFF in `reg'. */
1747 mn10300_legitimize_pic_address (rtx orig, rtx reg)
1749 if (GET_CODE (orig) == LABEL_REF
1750 || (GET_CODE (orig) == SYMBOL_REF
1751 && (CONSTANT_POOL_ADDRESS_P (orig)
1752 || ! MN10300_GLOBAL_P (orig))))
1755 reg = gen_reg_rtx (Pmode);
1757 emit_insn (gen_symGOTOFF2reg (reg, orig));
1760 else if (GET_CODE (orig) == SYMBOL_REF)
1763 reg = gen_reg_rtx (Pmode);
1765 emit_insn (gen_symGOT2reg (reg, orig));
1771 /* Return zero if X references a SYMBOL_REF or LABEL_REF whose symbol
1772 isn't protected by a PIC unspec; nonzero otherwise. */
1775 mn10300_legitimate_pic_operand_p (rtx x)
1780 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF)
1783 if (GET_CODE (x) == UNSPEC
1784 && (XINT (x, 1) == UNSPEC_PIC
1785 || XINT (x, 1) == UNSPEC_GOT
1786 || XINT (x, 1) == UNSPEC_GOTOFF
1787 || XINT (x, 1) == UNSPEC_PLT
1788 || XINT (x, 1) == UNSPEC_GOTSYM_OFF))
1791 fmt = GET_RTX_FORMAT (GET_CODE (x));
1792 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--)
1798 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
1799 if (! mn10300_legitimate_pic_operand_p (XVECEXP (x, i, j)))
1802 else if (fmt[i] == 'e'
1803 && ! mn10300_legitimate_pic_operand_p (XEXP (x, i)))
1810 /* Return TRUE if the address X, taken from a (MEM:MODE X) rtx, is
1811 legitimate, and FALSE otherwise.
1813 On the mn10300, the value in the address register must be
1814 in the same memory space/segment as the effective address.
1816 This is problematical for reload since it does not understand
1817 that base+index != index+base in a memory reference.
1819 Note it is still possible to use reg+reg addressing modes,
1820 it's just much more difficult. For a discussion of a possible
1821 workaround and solution, see the comments in pa.c before the
1822 function record_unscaled_index_insn_codes. */
1825 mn10300_legitimate_address_p (enum machine_mode mode, rtx x, bool strict)
1827 if (CONSTANT_ADDRESS_P (x)
1828 && (! flag_pic || mn10300_legitimate_pic_operand_p (x)))
1831 if (RTX_OK_FOR_BASE_P (x, strict))
1835 && GET_CODE (x) == POST_INC
1836 && RTX_OK_FOR_BASE_P (XEXP (x, 0), strict)
1837 && (mode == SImode || mode == SFmode || mode == HImode))
1840 if (GET_CODE (x) == PLUS)
1842 rtx base = 0, index = 0;
1844 if (REG_P (XEXP (x, 0))
1845 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 0)), strict))
1848 index = XEXP (x, 1);
1851 if (REG_P (XEXP (x, 1))
1852 && REGNO_STRICT_OK_FOR_BASE_P (REGNO (XEXP (x, 1)), strict))
1855 index = XEXP (x, 0);
1858 if (base != 0 && index != 0)
1860 if (CONST_INT_P ((index)))
1862 if (GET_CODE (index) == CONST
1863 && GET_CODE (XEXP (index, 0)) != PLUS
1865 || (mn10300_legitimate_pic_operand_p (index)
1866 && GET_MODE_SIZE (mode) == 4)))
1874 /* Used by LEGITIMATE_CONSTANT_P(). Returns TRUE if X is a valid
1875 constant. Note that some "constants" aren't valid, such as TLS
1876 symbols and unconverted GOT-based references, so we eliminate
1880 mn10300_legitimate_constant_p (rtx x)
1882 switch (GET_CODE (x))
1887 if (GET_CODE (x) == PLUS)
1889 if (! CONST_INT_P (XEXP (x, 1)))
1894 /* Only some unspecs are valid as "constants". */
1895 if (GET_CODE (x) == UNSPEC)
1897 rtx sym = XVECEXP (x, 0, 0);
1898 switch (XINT (x, 1))
1900 case UNSPEC_INT_LABEL:
1911 /* We must have drilled down to a symbol. */
1912 if (! mn10300_symbolic_operand (x, Pmode))
1924 mn10300_address_cost_1 (rtx x, int *unsig)
1926 switch (GET_CODE (x))
1929 switch (REGNO_REG_CLASS (REGNO (x)))
1955 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
1956 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
1961 return mn10300_address_cost (XEXP (x, 0), !optimize_size);
1965 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
1968 if (INTVAL (x) == 0)
1970 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1972 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1974 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1990 mn10300_address_cost (rtx x, bool speed ATTRIBUTE_UNUSED)
1993 return mn10300_address_cost_1 (x, &s);
1997 mn10300_rtx_costs (rtx x, int code, int outer_code, int *total,
1998 bool speed ATTRIBUTE_UNUSED)
2003 /* Zeros are extremely cheap. */
2004 if (INTVAL (x) == 0 && (outer_code == SET || outer_code == COMPARE))
2006 /* If it fits in 8 bits, then it's still relatively cheap. */
2007 else if (INT_8_BITS (INTVAL (x)))
2009 /* This is the "base" cost, includes constants where either the
2010 upper or lower 16bits are all zeros. */
2011 else if (INT_16_BITS (INTVAL (x))
2012 || (INTVAL (x) & 0xffff) == 0
2013 || (INTVAL (x) & 0xffff0000) == 0)
2022 /* These are more costly than a CONST_INT, but we can relax them,
2023 so they're less costly than a CONST_DOUBLE. */
2028 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
2029 so their cost is very high. */
2034 /* This is cheap, we can use btst. */
2035 if (outer_code == COMPARE)
2039 /* ??? This probably needs more work. */
2051 /* Check whether a constant used to initialize a DImode or DFmode can
2052 use a clr instruction. The code here must be kept in sync with
2056 mn10300_wide_const_load_uses_clr (rtx operands[2])
2058 long val[2] = {0, 0};
2060 if (! REG_P (operands[0])
2061 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
2064 switch (GET_CODE (operands[1]))
2069 split_double (operands[1], &low, &high);
2070 val[0] = INTVAL (low);
2071 val[1] = INTVAL (high);
2076 if (GET_MODE (operands[1]) == DFmode)
2080 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
2081 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
2083 else if (GET_MODE (operands[1]) == VOIDmode
2084 || GET_MODE (operands[1]) == DImode)
2086 val[0] = CONST_DOUBLE_LOW (operands[1]);
2087 val[1] = CONST_DOUBLE_HIGH (operands[1]);
2095 return val[0] == 0 || val[1] == 0;
2097 /* If using PIC, mark a SYMBOL_REF for a non-global symbol so that we
2098 may access it using GOTOFF instead of GOT. */
2101 mn10300_encode_section_info (tree decl, rtx rtl, int first ATTRIBUTE_UNUSED)
2107 symbol = XEXP (rtl, 0);
2108 if (GET_CODE (symbol) != SYMBOL_REF)
2112 SYMBOL_REF_FLAG (symbol) = (*targetm.binds_local_p) (decl);
2115 /* Dispatch tables on the mn10300 are extremely expensive in terms of code
2116 and readonly data size. So we crank up the case threshold value to
2117 encourage a series of if/else comparisons to implement many small switch
2118 statements. In theory, this value could be increased much more if we
2119 were solely optimizing for space, but we keep it "reasonable" to avoid
2120 serious code efficiency lossage. */
2123 mn10300_case_values_threshold (void)
2128 /* Worker function for TARGET_ASM_TRAMPOLINE_TEMPLATE. */
2131 mn10300_asm_trampoline_template (FILE *f)
2133 fprintf (f, "\tadd -4,sp\n");
2134 fprintf (f, "\t.long 0x0004fffa\n");
2135 fprintf (f, "\tmov (0,sp),a0\n");
2136 fprintf (f, "\tadd 4,sp\n");
2137 fprintf (f, "\tmov (13,a0),a1\n");
2138 fprintf (f, "\tmov (17,a0),a0\n");
2139 fprintf (f, "\tjmp (a0)\n");
2140 fprintf (f, "\t.long 0\n");
2141 fprintf (f, "\t.long 0\n");
2144 /* Worker function for TARGET_TRAMPOLINE_INIT. */
2147 mn10300_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value)
2149 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0);
2152 emit_block_move (m_tramp, assemble_trampoline_template (),
2153 GEN_INT (TRAMPOLINE_SIZE), BLOCK_OP_NORMAL);
2155 mem = adjust_address (m_tramp, SImode, 0x14);
2156 emit_move_insn (mem, chain_value);
2157 mem = adjust_address (m_tramp, SImode, 0x18);
2158 emit_move_insn (mem, fnaddr);
2161 /* Output the assembler code for a C++ thunk function.
2162 THUNK_DECL is the declaration for the thunk function itself, FUNCTION
2163 is the decl for the target function. DELTA is an immediate constant
2164 offset to be added to the THIS parameter. If VCALL_OFFSET is nonzero
2165 the word at the adjusted address *(*THIS' + VCALL_OFFSET) should be
2166 additionally added to THIS. Finally jump to the entry point of
2170 mn10300_asm_output_mi_thunk (FILE * file,
2171 tree thunk_fndecl ATTRIBUTE_UNUSED,
2172 HOST_WIDE_INT delta,
2173 HOST_WIDE_INT vcall_offset,
2178 /* Get the register holding the THIS parameter. Handle the case
2179 where there is a hidden first argument for a returned structure. */
2180 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function))
2181 _this = reg_names [FIRST_ARGUMENT_REGNUM + 1];
2183 _this = reg_names [FIRST_ARGUMENT_REGNUM];
2185 fprintf (file, "\t%s Thunk Entry Point:\n", ASM_COMMENT_START);
2188 fprintf (file, "\tadd %d, %s\n", (int) delta, _this);
2192 const char * scratch = reg_names [FIRST_ADDRESS_REGNUM + 1];
2194 fprintf (file, "\tmov %s, %s\n", _this, scratch);
2195 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2196 fprintf (file, "\tadd %d, %s\n", (int) vcall_offset, scratch);
2197 fprintf (file, "\tmov (%s), %s\n", scratch, scratch);
2198 fprintf (file, "\tadd %s, %s\n", scratch, _this);
2201 fputs ("\tjmp ", file);
2202 assemble_name (file, XSTR (XEXP (DECL_RTL (function), 0), 0));
2206 /* Return true if mn10300_output_mi_thunk would be able to output the
2207 assembler code for the thunk function specified by the arguments
2208 it is passed, and false otherwise. */
2211 mn10300_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED,
2212 HOST_WIDE_INT delta ATTRIBUTE_UNUSED,
2213 HOST_WIDE_INT vcall_offset ATTRIBUTE_UNUSED,
2214 const_tree function ATTRIBUTE_UNUSED)
2220 mn10300_hard_regno_mode_ok (unsigned int regno, enum machine_mode mode)
2222 if (REGNO_REG_CLASS (regno) == FP_REGS
2223 || REGNO_REG_CLASS (regno) == FP_ACC_REGS)
2224 /* Do not store integer values in FP registers. */
2225 return GET_MODE_CLASS (mode) == MODE_FLOAT && ((regno & 1) == 0);
2227 if (((regno) & 1) == 0 || GET_MODE_SIZE (mode) == 4)
2230 if (REGNO_REG_CLASS (regno) == DATA_REGS
2231 || (TARGET_AM33 && REGNO_REG_CLASS (regno) == ADDRESS_REGS)
2232 || REGNO_REG_CLASS (regno) == EXTENDED_REGS)
2233 return GET_MODE_SIZE (mode) <= 4;
2239 mn10300_modes_tieable (enum machine_mode mode1, enum machine_mode mode2)
2241 if (GET_MODE_CLASS (mode1) == MODE_FLOAT
2242 && GET_MODE_CLASS (mode2) != MODE_FLOAT)
2245 if (GET_MODE_CLASS (mode2) == MODE_FLOAT
2246 && GET_MODE_CLASS (mode1) != MODE_FLOAT)
2251 || (GET_MODE_SIZE (mode1) <= 4 && GET_MODE_SIZE (mode2) <= 4))
2258 mn10300_select_cc_mode (rtx x)
2260 return (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) ? CC_FLOATmode : CCmode;
2263 /* Initialize the GCC target structure. */
2265 #undef TARGET_EXCEPT_UNWIND_INFO
2266 #define TARGET_EXCEPT_UNWIND_INFO sjlj_except_unwind_info
2268 #undef TARGET_ASM_ALIGNED_HI_OP
2269 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
2271 #undef TARGET_LEGITIMIZE_ADDRESS
2272 #define TARGET_LEGITIMIZE_ADDRESS mn10300_legitimize_address
2274 #undef TARGET_RTX_COSTS
2275 #define TARGET_RTX_COSTS mn10300_rtx_costs
2276 #undef TARGET_ADDRESS_COST
2277 #define TARGET_ADDRESS_COST mn10300_address_cost
2279 #undef TARGET_ASM_FILE_START
2280 #define TARGET_ASM_FILE_START mn10300_file_start
2281 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
2282 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
2284 #undef TARGET_DEFAULT_TARGET_FLAGS
2285 #define TARGET_DEFAULT_TARGET_FLAGS MASK_MULT_BUG | MASK_PTR_A0D0
2286 #undef TARGET_HANDLE_OPTION
2287 #define TARGET_HANDLE_OPTION mn10300_handle_option
2288 #undef TARGET_OPTION_OVERRIDE
2289 #define TARGET_OPTION_OVERRIDE mn10300_option_override
2290 #undef TARGET_OPTION_OPTIMIZATION_TABLE
2291 #define TARGET_OPTION_OPTIMIZATION_TABLE mn10300_option_optimization_table
2293 #undef TARGET_ENCODE_SECTION_INFO
2294 #define TARGET_ENCODE_SECTION_INFO mn10300_encode_section_info
2296 #undef TARGET_PROMOTE_PROTOTYPES
2297 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true
2298 #undef TARGET_RETURN_IN_MEMORY
2299 #define TARGET_RETURN_IN_MEMORY mn10300_return_in_memory
2300 #undef TARGET_PASS_BY_REFERENCE
2301 #define TARGET_PASS_BY_REFERENCE mn10300_pass_by_reference
2302 #undef TARGET_CALLEE_COPIES
2303 #define TARGET_CALLEE_COPIES hook_bool_CUMULATIVE_ARGS_mode_tree_bool_true
2304 #undef TARGET_ARG_PARTIAL_BYTES
2305 #define TARGET_ARG_PARTIAL_BYTES mn10300_arg_partial_bytes
2307 #undef TARGET_EXPAND_BUILTIN_SAVEREGS
2308 #define TARGET_EXPAND_BUILTIN_SAVEREGS mn10300_builtin_saveregs
2309 #undef TARGET_EXPAND_BUILTIN_VA_START
2310 #define TARGET_EXPAND_BUILTIN_VA_START mn10300_va_start
2312 #undef TARGET_CASE_VALUES_THRESHOLD
2313 #define TARGET_CASE_VALUES_THRESHOLD mn10300_case_values_threshold
2315 #undef TARGET_LEGITIMATE_ADDRESS_P
2316 #define TARGET_LEGITIMATE_ADDRESS_P mn10300_legitimate_address_p
2318 #undef TARGET_ASM_TRAMPOLINE_TEMPLATE
2319 #define TARGET_ASM_TRAMPOLINE_TEMPLATE mn10300_asm_trampoline_template
2320 #undef TARGET_TRAMPOLINE_INIT
2321 #define TARGET_TRAMPOLINE_INIT mn10300_trampoline_init
2323 #undef TARGET_FUNCTION_VALUE
2324 #define TARGET_FUNCTION_VALUE mn10300_function_value
2325 #undef TARGET_LIBCALL_VALUE
2326 #define TARGET_LIBCALL_VALUE mn10300_libcall_value
2328 #undef TARGET_ASM_OUTPUT_MI_THUNK
2329 #define TARGET_ASM_OUTPUT_MI_THUNK mn10300_asm_output_mi_thunk
2330 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK
2331 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK mn10300_can_output_mi_thunk
2333 struct gcc_target targetm = TARGET_INITIALIZER;