1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
3 Free Software Foundation, Inc.
4 Contributed by Jeff Law (law@cygnus.com).
6 This file is part of GNU CC.
8 GNU CC is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GNU CC is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GNU CC; see the file COPYING. If not, write to
20 the Free Software Foundation, 59 Temple Place - Suite 330,
21 Boston, MA 02111-1307, USA. */
25 #include "coretypes.h"
30 #include "hard-reg-set.h"
32 #include "insn-config.h"
33 #include "conditions.h"
35 #include "insn-attr.h"
45 #include "target-def.h"
47 /* The size of the callee register save area. Right now we save everything
48 on entry since it costs us nothing in code size. It does cost us from a
49 speed standpoint, so we want to optimize this sooner or later. */
50 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
51 + 4 * regs_ever_live[3] \
52 + 4 * regs_ever_live[6] \
53 + 4 * regs_ever_live[7] \
54 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
55 || regs_ever_live[16] || regs_ever_live[17]))
58 static int mn10300_address_cost_1 PARAMS ((rtx, int *));
59 static int mn10300_address_cost PARAMS ((rtx));
60 static bool mn10300_rtx_costs PARAMS ((rtx, int, int, int *));
61 static void mn10300_file_start PARAMS ((void));
64 /* Initialize the GCC target structure. */
65 #undef TARGET_ASM_ALIGNED_HI_OP
66 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t"
68 #undef TARGET_RTX_COSTS
69 #define TARGET_RTX_COSTS mn10300_rtx_costs
70 #undef TARGET_ADDRESS_COST
71 #define TARGET_ADDRESS_COST mn10300_address_cost
73 #undef TARGET_ASM_FILE_START
74 #define TARGET_ASM_FILE_START mn10300_file_start
75 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE
76 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true
78 struct gcc_target targetm = TARGET_INITIALIZER;
83 default_file_start ();
86 fprintf (asm_out_file, "\t.am33\n");
90 /* Print operand X using operand code CODE to assembly language output file
94 print_operand (file, x, code)
103 /* These are normal and reversed branches. */
104 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
107 fprintf (file, "ne");
110 fprintf (file, "eq");
113 fprintf (file, "ge");
116 fprintf (file, "gt");
119 fprintf (file, "le");
122 fprintf (file, "lt");
125 fprintf (file, "cc");
128 fprintf (file, "hi");
131 fprintf (file, "ls");
134 fprintf (file, "cs");
141 /* This is used for the operand to a call instruction;
142 if it's a REG, enclose it in parens, else output
143 the operand normally. */
144 if (GET_CODE (x) == REG)
147 print_operand (file, x, 0);
151 print_operand (file, x, 0);
154 /* These are the least significant word in a 64bit value. */
156 switch (GET_CODE (x))
160 output_address (XEXP (x, 0));
165 fprintf (file, "%s", reg_names[REGNO (x)]);
169 fprintf (file, "%s", reg_names[subreg_regno (x)]);
177 switch (GET_MODE (x))
180 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
181 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
182 fprintf (file, "0x%lx", val[0]);
185 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
186 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
187 fprintf (file, "0x%lx", val[0]);
191 print_operand_address (file,
192 GEN_INT (CONST_DOUBLE_LOW (x)));
203 split_double (x, &low, &high);
204 fprintf (file, "%ld", (long)INTVAL (low));
213 /* Similarly, but for the most significant word. */
215 switch (GET_CODE (x))
219 x = adjust_address (x, SImode, 4);
220 output_address (XEXP (x, 0));
225 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
229 fprintf (file, "%s", reg_names[subreg_regno (x) + 1]);
237 switch (GET_MODE (x))
240 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
241 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
242 fprintf (file, "0x%lx", val[1]);
248 print_operand_address (file,
249 GEN_INT (CONST_DOUBLE_HIGH (x)));
260 split_double (x, &low, &high);
261 fprintf (file, "%ld", (long)INTVAL (high));
272 if (GET_CODE (XEXP (x, 0)) == REG)
273 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
275 output_address (XEXP (x, 0));
280 if (INTVAL (x) < -128 || INTVAL (x) > 255)
282 fprintf (file, "%d", (int)((~INTVAL (x)) & 0xff));
286 if (INTVAL (x) < -128 || INTVAL (x) > 255)
288 fprintf (file, "%d", (int)(INTVAL (x) & 0xff));
291 /* For shift counts. The hardware ignores the upper bits of
292 any immediate, but the assembler will flag an out of range
293 shift count as an error. So we mask off the high bits
294 of the immediate here. */
296 if (GET_CODE (x) == CONST_INT)
298 fprintf (file, "%d", (int)(INTVAL (x) & 0x1f));
304 switch (GET_CODE (x))
308 output_address (XEXP (x, 0));
317 fprintf (file, "%s", reg_names[REGNO (x)]);
321 fprintf (file, "%s", reg_names[subreg_regno (x)]);
324 /* This will only be single precision.... */
330 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
331 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
332 fprintf (file, "0x%lx", val);
341 print_operand_address (file, x);
350 /* Output assembly language output for the address ADDR to FILE. */
353 print_operand_address (file, addr)
357 switch (GET_CODE (addr))
360 print_operand_address (file, XEXP (addr, 0));
364 print_operand (file, addr, 0);
369 if (REG_P (XEXP (addr, 0))
370 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
371 base = XEXP (addr, 0), index = XEXP (addr, 1);
372 else if (REG_P (XEXP (addr, 1))
373 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
374 base = XEXP (addr, 1), index = XEXP (addr, 0);
377 print_operand (file, index, 0);
379 print_operand (file, base, 0);;
383 output_addr_const (file, addr);
386 output_addr_const (file, addr);
391 /* Print a set of registers in the format required by "movm" and "ret".
392 Register K is saved if bit K of MASK is set. The data and address
393 registers can be stored individually, but the extended registers cannot.
394 We assume that the mask alread takes that into account. For instance,
395 bits 14 to 17 must have the same value. */
398 mn10300_print_reg_list (file, mask)
408 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
409 if ((mask & (1 << i)) != 0)
413 fputs (reg_names [i], file);
417 if ((mask & 0x3c000) != 0)
419 if ((mask & 0x3c000) != 0x3c000)
423 fputs ("exreg1", file);
431 can_use_return_insn ()
433 /* size includes the fixed stack space needed for function calls. */
434 int size = get_frame_size () + current_function_outgoing_args_size;
436 /* And space for the return pointer. */
437 size += current_function_outgoing_args_size ? 4 : 0;
439 return (reload_completed
441 && !regs_ever_live[2]
442 && !regs_ever_live[3]
443 && !regs_ever_live[6]
444 && !regs_ever_live[7]
445 && !regs_ever_live[14]
446 && !regs_ever_live[15]
447 && !regs_ever_live[16]
448 && !regs_ever_live[17]
449 && !frame_pointer_needed);
452 /* Returns the set of live, callee-saved registers as a bitmask. The
453 callee-saved extended registers cannot be stored individually, so
454 all of them will be included in the mask if any one of them is used. */
457 mn10300_get_live_callee_saved_regs ()
463 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
464 if (regs_ever_live[i] && ! call_used_regs[i])
466 if ((mask & 0x3c000) != 0)
472 /* Generate an instruction that pushes several registers onto the stack.
473 Register K will be saved if bit K in MASK is set. The function does
474 nothing if MASK is zero.
476 To be compatible with the "movm" instruction, the lowest-numbered
477 register must be stored in the lowest slot. If MASK is the set
478 { R1,...,RN }, where R1...RN are ordered least first, the generated
479 instruction will have the form:
482 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
483 (set (mem:SI (plus:SI (reg:SI 9)
487 (set (mem:SI (plus:SI (reg:SI 9)
492 mn10300_gen_multiple_store (mask)
502 /* Count how many registers need to be saved. */
504 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
505 if ((mask & (1 << i)) != 0)
508 /* We need one PARALLEL element to update the stack pointer and
509 an additional element for each register that is stored. */
510 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
512 /* Create the instruction that updates the stack pointer. */
514 = gen_rtx_SET (SImode,
516 gen_rtx_PLUS (SImode,
518 GEN_INT (-count * 4)));
520 /* Create each store. */
522 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
523 if ((mask & (1 << i)) != 0)
525 rtx address = gen_rtx_PLUS (SImode,
527 GEN_INT (-pari * 4));
528 XVECEXP(par, 0, pari)
529 = gen_rtx_SET (VOIDmode,
530 gen_rtx_MEM (SImode, address),
531 gen_rtx_REG (SImode, i));
535 par = emit_insn (par);
536 RTX_FRAME_RELATED_P (par) = 1;
545 /* SIZE includes the fixed stack space needed for function calls. */
546 size = get_frame_size () + current_function_outgoing_args_size;
547 size += (current_function_outgoing_args_size ? 4 : 0);
549 /* If we use any of the callee-saved registers, save them now. */
550 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
552 /* Now put the frame pointer into the frame pointer register. */
553 if (frame_pointer_needed)
554 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
556 /* Allocate stack for this frame. */
558 emit_insn (gen_addsi3 (stack_pointer_rtx,
568 /* SIZE includes the fixed stack space needed for function calls. */
569 size = get_frame_size () + current_function_outgoing_args_size;
570 size += (current_function_outgoing_args_size ? 4 : 0);
572 /* Maybe cut back the stack, except for the register save area.
574 If the frame pointer exists, then use the frame pointer to
577 If the stack size + register save area is more than 255 bytes,
578 then the stack must be cut back here since the size + register
579 save size is too big for a ret/retf instruction.
581 Else leave it alone, it will be cut back as part of the
582 ret/retf instruction, or there wasn't any stack to begin with.
584 Under no circumstanes should the register save area be
585 deallocated here, that would leave a window where an interrupt
586 could occur and trash the register save area. */
587 if (frame_pointer_needed)
589 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
592 else if (size + REG_SAVE_BYTES > 255)
594 emit_insn (gen_addsi3 (stack_pointer_rtx,
600 /* Adjust the stack and restore callee-saved registers, if any. */
601 if (size || regs_ever_live[2] || regs_ever_live[3]
602 || regs_ever_live[6] || regs_ever_live[7]
603 || regs_ever_live[14] || regs_ever_live[15]
604 || regs_ever_live[16] || regs_ever_live[17]
605 || frame_pointer_needed)
606 emit_jump_insn (gen_return_internal_regs
607 (GEN_INT (size + REG_SAVE_BYTES)));
609 emit_jump_insn (gen_return_internal ());
612 /* Update the condition code from the insn. */
615 notice_update_cc (body, insn)
619 switch (get_attr_cc (insn))
622 /* Insn does not affect CC at all. */
626 /* Insn does not change CC, but the 0'th operand has been changed. */
627 if (cc_status.value1 != 0
628 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
629 cc_status.value1 = 0;
633 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
636 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
637 cc_status.value1 = recog_data.operand[0];
641 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
644 cc_status.flags |= CC_NO_CARRY;
645 cc_status.value1 = recog_data.operand[0];
649 /* The insn is a compare instruction. */
651 cc_status.value1 = SET_SRC (body);
655 /* The insn is a compare instruction. */
657 cc_status.value1 = SET_SRC (body);
658 cc_status.flags |= CC_INVERTED;
662 /* Insn doesn't leave CC in a usable state. */
671 /* Recognize the PARALLEL rtx generated by mn10300_gen_multiple_store().
672 This function is for MATCH_PARALLEL and so assumes OP is known to be
673 parallel. If OP is a multiple store, return a mask indicating which
674 registers it saves. Return 0 otherwise. */
677 store_multiple_operation (op, mode)
679 enum machine_mode mode ATTRIBUTE_UNUSED;
687 count = XVECLEN (op, 0);
691 /* Check that first instruction has the form (set (sp) (plus A B)) */
692 elt = XVECEXP (op, 0, 0);
693 if (GET_CODE (elt) != SET
694 || GET_CODE (SET_DEST (elt)) != REG
695 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
696 || GET_CODE (SET_SRC (elt)) != PLUS)
699 /* Check that A is the stack pointer and B is the expected stack size.
700 For OP to match, each subsequent instruction should push a word onto
701 the stack. We therefore expect the first instruction to create
702 COUNT-1 stack slots. */
704 if (GET_CODE (XEXP (elt, 0)) != REG
705 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
706 || GET_CODE (XEXP (elt, 1)) != CONST_INT
707 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
710 /* Now go through the rest of the vector elements. They must be
711 ordered so that the first instruction stores the highest-numbered
712 register to the highest stack slot and that subsequent instructions
713 store a lower-numbered register to the slot below.
715 LAST keeps track of the smallest-numbered register stored so far.
716 MASK is the set of stored registers. */
717 last = FIRST_PSEUDO_REGISTER;
719 for (i = 1; i < count; i++)
721 /* Check that element i is a (set (mem M) R) and that R is valid. */
722 elt = XVECEXP (op, 0, i);
723 if (GET_CODE (elt) != SET
724 || GET_CODE (SET_DEST (elt)) != MEM
725 || GET_CODE (SET_SRC (elt)) != REG
726 || REGNO (SET_SRC (elt)) >= last)
729 /* R was OK, so provisionally add it to MASK. We return 0 in any
730 case if the rest of the instruction has a flaw. */
731 last = REGNO (SET_SRC (elt));
734 /* Check that M has the form (plus (sp) (const_int -I*4)) */
735 elt = XEXP (SET_DEST (elt), 0);
736 if (GET_CODE (elt) != PLUS
737 || GET_CODE (XEXP (elt, 0)) != REG
738 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
739 || GET_CODE (XEXP (elt, 1)) != CONST_INT
740 || INTVAL (XEXP (elt, 1)) != -i * 4)
744 /* All or none of the callee-saved extended registers must be in the set. */
745 if ((mask & 0x3c000) != 0
746 && (mask & 0x3c000) != 0x3c000)
752 /* Return true if OP is a valid call operand. */
755 call_address_operand (op, mode)
757 enum machine_mode mode ATTRIBUTE_UNUSED;
759 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
762 /* What (if any) secondary registers are needed to move IN with mode
763 MODE into a register in register class CLASS.
765 We might be able to simplify this. */
767 secondary_reload_class (class, mode, in)
768 enum reg_class class;
769 enum machine_mode mode;
772 /* Memory loads less than a full word wide can't have an
773 address or stack pointer destination. They must use
774 a data register as an intermediate register. */
775 if ((GET_CODE (in) == MEM
776 || (GET_CODE (in) == REG
777 && REGNO (in) >= FIRST_PSEUDO_REGISTER)
778 || (GET_CODE (in) == SUBREG
779 && GET_CODE (SUBREG_REG (in)) == REG
780 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
781 && (mode == QImode || mode == HImode)
782 && (class == ADDRESS_REGS || class == SP_REGS
783 || class == SP_OR_ADDRESS_REGS))
786 return DATA_OR_EXTENDED_REGS;
790 /* We can't directly load sp + const_int into a data register;
791 we must use an address register as an intermediate. */
793 && class != ADDRESS_REGS
794 && class != SP_OR_ADDRESS_REGS
795 && class != SP_OR_EXTENDED_REGS
796 && class != ADDRESS_OR_EXTENDED_REGS
797 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
798 && (in == stack_pointer_rtx
799 || (GET_CODE (in) == PLUS
800 && (XEXP (in, 0) == stack_pointer_rtx
801 || XEXP (in, 1) == stack_pointer_rtx))))
804 if (GET_CODE (in) == PLUS
805 && (XEXP (in, 0) == stack_pointer_rtx
806 || XEXP (in, 1) == stack_pointer_rtx))
809 return DATA_OR_EXTENDED_REGS;
813 /* Otherwise assume no secondary reloads are needed. */
818 initial_offset (from, to)
821 /* The difference between the argument pointer and the frame pointer
822 is the size of the callee register save area. */
823 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
825 if (regs_ever_live[2] || regs_ever_live[3]
826 || regs_ever_live[6] || regs_ever_live[7]
827 || regs_ever_live[14] || regs_ever_live[15]
828 || regs_ever_live[16] || regs_ever_live[17]
829 || frame_pointer_needed)
830 return REG_SAVE_BYTES;
835 /* The difference between the argument pointer and the stack pointer is
836 the sum of the size of this function's frame, the callee register save
837 area, and the fixed stack space needed for function calls (if any). */
838 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
840 if (regs_ever_live[2] || regs_ever_live[3]
841 || regs_ever_live[6] || regs_ever_live[7]
842 || regs_ever_live[14] || regs_ever_live[15]
843 || regs_ever_live[16] || regs_ever_live[17]
844 || frame_pointer_needed)
845 return (get_frame_size () + REG_SAVE_BYTES
846 + (current_function_outgoing_args_size
847 ? current_function_outgoing_args_size + 4 : 0));
849 return (get_frame_size ()
850 + (current_function_outgoing_args_size
851 ? current_function_outgoing_args_size + 4 : 0));
854 /* The difference between the frame pointer and stack pointer is the sum
855 of the size of this function's frame and the fixed stack space needed
856 for function calls (if any). */
857 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
858 return (get_frame_size ()
859 + (current_function_outgoing_args_size
860 ? current_function_outgoing_args_size + 4 : 0));
865 /* Flush the argument registers to the stack for a stdarg function;
866 return the new argument pointer. */
868 mn10300_builtin_saveregs ()
871 tree fntype = TREE_TYPE (current_function_decl);
872 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
873 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
875 ? UNITS_PER_WORD : 0);
876 int set = get_varargs_alias_set ();
879 offset = plus_constant (current_function_arg_offset_rtx, argadj);
881 offset = current_function_arg_offset_rtx;
883 mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
884 set_mem_alias_set (mem, set);
885 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
887 mem = gen_rtx_MEM (SImode,
888 plus_constant (current_function_internal_arg_pointer, 4));
889 set_mem_alias_set (mem, set);
890 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
892 return copy_to_reg (expand_binop (Pmode, add_optab,
893 current_function_internal_arg_pointer,
894 offset, 0, 0, OPTAB_LIB_WIDEN));
898 mn10300_va_start (valist, nextarg)
902 nextarg = expand_builtin_saveregs ();
903 std_expand_builtin_va_start (valist, nextarg);
907 mn10300_va_arg (valist, type)
910 HOST_WIDE_INT align, rsize;
913 /* Compute the rounded size of the type. */
914 align = PARM_BOUNDARY / BITS_PER_UNIT;
915 rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
917 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
918 build_int_2 ((rsize > 8 ? 4 : rsize), 0));
919 TREE_SIDE_EFFECTS (t) = 1;
921 ptr = build_pointer_type (type);
923 /* "Large" types are passed by reference. */
926 pptr = build_pointer_type (ptr);
927 t = build1 (NOP_EXPR, pptr, t);
928 TREE_SIDE_EFFECTS (t) = 1;
930 t = build1 (INDIRECT_REF, ptr, t);
931 TREE_SIDE_EFFECTS (t) = 1;
935 t = build1 (NOP_EXPR, ptr, t);
936 TREE_SIDE_EFFECTS (t) = 1;
940 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
943 /* Return an RTX to represent where a value with mode MODE will be returned
944 from a function. If the result is 0, the argument is pushed. */
947 function_arg (cum, mode, type, named)
948 CUMULATIVE_ARGS *cum;
949 enum machine_mode mode;
951 int named ATTRIBUTE_UNUSED;
956 /* We only support using 2 data registers as argument registers. */
959 /* Figure out the size of the object to be passed. */
961 size = int_size_in_bytes (type);
963 size = GET_MODE_SIZE (mode);
965 /* Figure out the alignment of the object to be passed. */
968 cum->nbytes = (cum->nbytes + 3) & ~3;
970 /* Don't pass this arg via a register if all the argument registers
972 if (cum->nbytes > nregs * UNITS_PER_WORD)
975 /* Don't pass this arg via a register if it would be split between
976 registers and memory. */
977 if (type == NULL_TREE
978 && cum->nbytes + size > nregs * UNITS_PER_WORD)
981 switch (cum->nbytes / UNITS_PER_WORD)
984 result = gen_rtx_REG (mode, 0);
987 result = gen_rtx_REG (mode, 1);
996 /* Return the number of registers to use for an argument passed partially
997 in registers and partially in memory. */
1000 function_arg_partial_nregs (cum, mode, type, named)
1001 CUMULATIVE_ARGS *cum;
1002 enum machine_mode mode;
1004 int named ATTRIBUTE_UNUSED;
1008 /* We only support using 2 data registers as argument registers. */
1011 /* Figure out the size of the object to be passed. */
1012 if (mode == BLKmode)
1013 size = int_size_in_bytes (type);
1015 size = GET_MODE_SIZE (mode);
1017 /* Figure out the alignment of the object to be passed. */
1020 cum->nbytes = (cum->nbytes + 3) & ~3;
1022 /* Don't pass this arg via a register if all the argument registers
1024 if (cum->nbytes > nregs * UNITS_PER_WORD)
1027 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1030 /* Don't pass this arg via a register if it would be split between
1031 registers and memory. */
1032 if (type == NULL_TREE
1033 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1036 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1039 /* Output a tst insn. */
1041 output_tst (operand, insn)
1047 /* We can save a byte if we can find a register which has the value
1049 temp = PREV_INSN (insn);
1050 while (optimize && temp)
1054 /* We allow the search to go through call insns. We record
1055 the fact that we've past a CALL_INSN and reject matches which
1056 use call clobbered registers. */
1057 if (GET_CODE (temp) == CODE_LABEL
1058 || GET_CODE (temp) == JUMP_INSN
1059 || GET_CODE (temp) == BARRIER)
1062 if (GET_CODE (temp) == CALL_INSN)
1065 if (GET_CODE (temp) == NOTE)
1067 temp = PREV_INSN (temp);
1071 /* It must be an insn, see if it is a simple set. */
1072 set = single_set (temp);
1075 temp = PREV_INSN (temp);
1079 /* Are we setting a data register to zero (this does not win for
1082 If it's a call clobbered register, have we past a call?
1084 Make sure the register we find isn't the same as ourself;
1085 the mn10300 can't encode that.
1087 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1088 so the code to detect calls here isn't doing anything useful. */
1089 if (REG_P (SET_DEST (set))
1090 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1091 && !reg_set_between_p (SET_DEST (set), temp, insn)
1092 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1093 == REGNO_REG_CLASS (REGNO (operand)))
1094 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1095 && REGNO (SET_DEST (set)) != REGNO (operand)
1097 || !call_used_regs[REGNO (SET_DEST (set))]))
1100 xoperands[0] = operand;
1101 xoperands[1] = SET_DEST (set);
1103 output_asm_insn ("cmp %1,%0", xoperands);
1107 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1108 && REG_P (SET_DEST (set))
1109 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1110 && !reg_set_between_p (SET_DEST (set), temp, insn)
1111 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1112 != REGNO_REG_CLASS (REGNO (operand)))
1113 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1114 && REGNO (SET_DEST (set)) != REGNO (operand)
1116 || !call_used_regs[REGNO (SET_DEST (set))]))
1119 xoperands[0] = operand;
1120 xoperands[1] = SET_DEST (set);
1122 output_asm_insn ("cmp %1,%0", xoperands);
1125 temp = PREV_INSN (temp);
1131 impossible_plus_operand (op, mode)
1133 enum machine_mode mode ATTRIBUTE_UNUSED;
1135 if (GET_CODE (op) != PLUS)
1138 if (XEXP (op, 0) == stack_pointer_rtx
1139 || XEXP (op, 1) == stack_pointer_rtx)
1145 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1146 for the btst insn which may examine memory or a register (the memory
1147 variant only allows an unsigned 8 bit integer). */
1149 const_8bit_operand (op, mode)
1151 enum machine_mode mode ATTRIBUTE_UNUSED;
1153 return (GET_CODE (op) == CONST_INT
1155 && INTVAL (op) < 256);
1158 /* Similarly, but when using a zero_extract pattern for a btst where
1159 the source operand might end up in memory. */
1161 mask_ok_for_mem_btst (len, bit)
1165 unsigned int mask = 0;
1174 /* MASK must bit into an 8bit value. */
1175 return (((mask & 0xff) == mask)
1176 || ((mask & 0xff00) == mask)
1177 || ((mask & 0xff0000) == mask)
1178 || ((mask & 0xff000000) == mask));
1181 /* Return 1 if X contains a symbolic expression. We know these
1182 expressions will have one of a few well defined forms, so
1183 we need only check those forms. */
1185 symbolic_operand (op, mode)
1187 enum machine_mode mode ATTRIBUTE_UNUSED;
1189 switch (GET_CODE (op))
1196 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1197 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1198 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1204 /* Try machine dependent ways of modifying an illegitimate address
1205 to be legitimate. If we find one, return the new valid address.
1206 This macro is used in only one place: `memory_address' in explow.c.
1208 OLDX is the address as it was before break_out_memory_refs was called.
1209 In some cases it is useful to look at this to decide what needs to be done.
1211 MODE and WIN are passed so that this macro can use
1212 GO_IF_LEGITIMATE_ADDRESS.
1214 Normally it is always safe for this macro to do nothing. It exists to
1215 recognize opportunities to optimize the output.
1217 But on a few ports with segmented architectures and indexed addressing
1218 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1220 legitimize_address (x, oldx, mode)
1222 rtx oldx ATTRIBUTE_UNUSED;
1223 enum machine_mode mode ATTRIBUTE_UNUSED;
1225 /* Uh-oh. We might have an address for x[n-100000]. This needs
1226 special handling to avoid creating an indexed memory address
1227 with x-100000 as the base. */
1228 if (GET_CODE (x) == PLUS
1229 && symbolic_operand (XEXP (x, 1), VOIDmode))
1231 /* Ugly. We modify things here so that the address offset specified
1232 by the index expression is computed first, then added to x to form
1233 the entire address. */
1235 rtx regx1, regy1, regy2, y;
1237 /* Strip off any CONST. */
1239 if (GET_CODE (y) == CONST)
1242 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1244 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1245 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1246 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1247 regx1 = force_reg (Pmode,
1248 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1249 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1256 mn10300_address_cost_1 (x, unsig)
1260 switch (GET_CODE (x))
1263 switch (REGNO_REG_CLASS (REGNO (x)))
1288 return (mn10300_address_cost_1 (XEXP (x, 0), unsig)
1289 + mn10300_address_cost_1 (XEXP (x, 1), unsig));
1294 return mn10300_address_cost (XEXP (x, 0));
1298 return mn10300_address_cost_1 (XEXP (x, 0), unsig);
1301 if (INTVAL (x) == 0)
1303 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1305 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1307 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1317 switch (GET_CODE (XEXP (x, 0)))
1320 return mn10300_address_cost (XEXP (x, 0));
1336 mn10300_address_cost (x)
1340 return mn10300_address_cost_1 (x, &s);
1344 mn10300_rtx_costs (x, code, outer_code, total)
1346 int code, outer_code;
1352 /* Zeros are extremely cheap. */
1353 if (INTVAL (x) == 0 && outer_code == SET)
1355 /* If it fits in 8 bits, then it's still relatively cheap. */
1356 else if (INT_8_BITS (INTVAL (x)))
1358 /* This is the "base" cost, includes constants where either the
1359 upper or lower 16bits are all zeros. */
1360 else if (INT_16_BITS (INTVAL (x))
1361 || (INTVAL (x) & 0xffff) == 0
1362 || (INTVAL (x) & 0xffff0000) == 0)
1371 /* These are more costly than a CONST_INT, but we can relax them,
1372 so they're less costly than a CONST_DOUBLE. */
1377 /* We don't optimize CONST_DOUBLEs well nor do we relax them well,
1378 so their cost is very high. */
1382 /* ??? This probably needs more work. */
1394 /* Check whether a constant used to initialize a DImode or DFmode can
1395 use a clr instruction. The code here must be kept in sync with
1399 mn10300_wide_const_load_uses_clr (operands)
1404 if (GET_CODE (operands[0]) != REG
1405 || REGNO_REG_CLASS (REGNO (operands[0])) != DATA_REGS)
1408 switch (GET_CODE (operands[1]))
1413 split_double (operands[1], &low, &high);
1414 val[0] = INTVAL (low);
1415 val[1] = INTVAL (high);
1420 if (GET_MODE (operands[1]) == DFmode)
1424 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]);
1425 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
1427 else if (GET_MODE (operands[1]) == VOIDmode
1428 || GET_MODE (operands[1]) == DImode)
1430 val[0] = CONST_DOUBLE_LOW (operands[1]);
1431 val[1] = CONST_DOUBLE_HIGH (operands[1]);
1439 return val[0] == 0 || val[1] == 0;