1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996, 1997, 1998, 1999, 2000 Free Software Foundation, Inc.
3 Contributed by Jeff Law (law@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
29 #include "insn-config.h"
30 #include "conditions.h"
32 #include "insn-attr.h"
41 /* The size of the callee register save area. Right now we save everything
42 on entry since it costs us nothing in code size. It does cost us from a
43 speed standpoint, so we want to optimize this sooner or later. */
44 #define REG_SAVE_BYTES (4 * regs_ever_live[2] \
45 + 4 * regs_ever_live[3] \
46 + 4 * regs_ever_live[6] \
47 + 4 * regs_ever_live[7] \
48 + 16 * (regs_ever_live[14] || regs_ever_live[15] \
49 || regs_ever_live[16] || regs_ever_live[17]))
55 fprintf (file, "#\tGCC For the Matsushita MN10300\n");
57 fprintf (file, "# -O%d\n", optimize);
59 fprintf (file, "\n\n");
62 fprintf (file, "\t.am33\n");
63 output_file_directive (file, main_input_filename);
67 /* Print operand X using operand code CODE to assembly language output file
71 print_operand (file, x, code)
80 /* These are normal and reversed branches. */
81 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
102 fprintf (file, "cc");
105 fprintf (file, "hi");
108 fprintf (file, "ls");
111 fprintf (file, "cs");
118 /* This is used for the operand to a call instruction;
119 if it's a REG, enclose it in parens, else output
120 the operand normally. */
121 if (GET_CODE (x) == REG)
124 print_operand (file, x, 0);
128 print_operand (file, x, 0);
131 /* These are the least significant word in a 64bit value. */
133 switch (GET_CODE (x))
137 output_address (XEXP (x, 0));
142 fprintf (file, "%s", reg_names[REGNO (x)]);
147 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
155 switch (GET_MODE (x))
158 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
159 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
160 fprintf (file, "0x%lx", val[0]);
163 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
164 REAL_VALUE_TO_TARGET_SINGLE (rv, val[0]);
165 fprintf (file, "0x%lx", val[0]);
169 print_operand_address (file,
170 GEN_INT (CONST_DOUBLE_LOW (x)));
181 split_double (x, &low, &high);
182 fprintf (file, "%ld", (long)INTVAL (low));
191 /* Similarly, but for the most significant word. */
193 switch (GET_CODE (x))
197 x = adj_offsettable_operand (x, 4);
198 output_address (XEXP (x, 0));
203 fprintf (file, "%s", reg_names[REGNO (x) + 1]);
208 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)] + 1);
216 switch (GET_MODE (x))
219 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
220 REAL_VALUE_TO_TARGET_DOUBLE (rv, val);
221 fprintf (file, "0x%lx", val[1]);
227 print_operand_address (file,
228 GEN_INT (CONST_DOUBLE_HIGH (x)));
239 split_double (x, &low, &high);
240 fprintf (file, "%ld", (long)INTVAL (high));
251 if (GET_CODE (XEXP (x, 0)) == REG)
252 output_address (gen_rtx_PLUS (SImode, XEXP (x, 0), GEN_INT (0)));
254 output_address (XEXP (x, 0));
259 output_address (GEN_INT ((~INTVAL (x)) & 0xff));
262 /* For shift counts. The hardware ignores the upper bits of
263 any immediate, but the assembler will flag an out of range
264 shift count as an error. So we mask off the high bits
265 of the immediate here. */
267 if (GET_CODE (x) == CONST_INT)
269 fprintf (file, "%d", INTVAL (x) & 0x1f);
275 switch (GET_CODE (x))
279 output_address (XEXP (x, 0));
288 fprintf (file, "%s", reg_names[REGNO (x)]);
293 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
296 /* This will only be single precision.... */
302 REAL_VALUE_FROM_CONST_DOUBLE (rv, x);
303 REAL_VALUE_TO_TARGET_SINGLE (rv, val);
304 fprintf (file, "0x%lx", val);
313 print_operand_address (file, x);
322 /* Output assembly language output for the address ADDR to FILE. */
325 print_operand_address (file, addr)
329 switch (GET_CODE (addr))
332 print_operand_address (file, XEXP (addr, 0));
336 print_operand (file, addr, 0);
341 if (REG_P (XEXP (addr, 0))
342 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
343 base = XEXP (addr, 0), index = XEXP (addr, 1);
344 else if (REG_P (XEXP (addr, 1))
345 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
346 base = XEXP (addr, 1), index = XEXP (addr, 0);
349 print_operand (file, index, 0);
351 print_operand (file, base, 0);;
355 output_addr_const (file, addr);
358 output_addr_const (file, addr);
363 /* Print a set of registers in the format required by "movm" and "ret".
364 Register K is saved if bit K of MASK is set. The data and address
365 registers can be stored individually, but the extended registers cannot.
366 We assume that the mask alread takes that into account. For instance,
367 bits 14 to 17 must have the same value. */
370 mn10300_print_reg_list (file, mask)
380 for (i = 0; i < FIRST_EXTENDED_REGNUM; i++)
381 if ((mask & (1 << i)) != 0)
385 fputs (reg_names [i], file);
389 if ((mask & 0x3c000) != 0)
391 if ((mask & 0x3c000) != 0x3c000)
395 fputs ("exreg1", file);
403 can_use_return_insn ()
405 /* size includes the fixed stack space needed for function calls. */
406 int size = get_frame_size () + current_function_outgoing_args_size;
408 /* And space for the return pointer. */
409 size += current_function_outgoing_args_size ? 4 : 0;
411 return (reload_completed
413 && !regs_ever_live[2]
414 && !regs_ever_live[3]
415 && !regs_ever_live[6]
416 && !regs_ever_live[7]
417 && !regs_ever_live[14]
418 && !regs_ever_live[15]
419 && !regs_ever_live[16]
420 && !regs_ever_live[17]
421 && !frame_pointer_needed);
424 /* Returns the set of live, callee-saved registers as a bitmask. The
425 callee-saved extended registers cannot be stored individually, so
426 all of them will be included in the mask if any one of them is used. */
429 mn10300_get_live_callee_saved_regs ()
435 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
436 if (regs_ever_live[i] && ! call_used_regs[i])
438 if ((mask & 0x3c000) != 0)
444 /* Generate an instruction that pushes several registers onto the stack.
445 Register K will be saved if bit K in MASK is set. The function does
446 nothing if MASK is zero.
448 To be compatible with the "movm" instruction, the lowest-numbered
449 register must be stored in the lowest slot. If MASK is the set
450 { R1,...,RN }, where R1...RN are ordered least first, the generated
451 instruction will have the form:
454 (set (reg:SI 9) (plus:SI (reg:SI 9) (const_int -N*4)))
455 (set (mem:SI (plus:SI (reg:SI 9)
459 (set (mem:SI (plus:SI (reg:SI 9)
464 mn10300_gen_multiple_store (mask)
474 /* Count how many registers need to be saved. */
476 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
477 if ((mask & (1 << i)) != 0)
480 /* We need one PARALLEL element to update the stack pointer and
481 an additional element for each register that is stored. */
482 par = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1));
484 /* Create the instruction that updates the stack pointer. */
486 = gen_rtx_SET (SImode,
488 gen_rtx_PLUS (SImode,
490 GEN_INT (-count * 4)));
492 /* Create each store. */
494 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
495 if ((mask & (1 << i)) != 0)
497 rtx address = gen_rtx_PLUS (SImode,
499 GEN_INT (-pari * 4));
500 XVECEXP(par, 0, pari)
501 = gen_rtx_SET (VOIDmode,
502 gen_rtx_MEM (SImode, address),
503 gen_rtx_REG (SImode, i));
507 par = emit_insn (par);
508 RTX_FRAME_RELATED_P (par) = 1;
517 /* SIZE includes the fixed stack space needed for function calls. */
518 size = get_frame_size () + current_function_outgoing_args_size;
519 size += (current_function_outgoing_args_size ? 4 : 0);
521 /* If this is an old-style varargs function, then its arguments
522 need to be flushed back to the stack. */
523 if (current_function_varargs)
525 emit_move_insn (gen_rtx_MEM (SImode,
526 plus_constant (stack_pointer_rtx, 4)),
527 gen_rtx_REG (SImode, 0));
528 emit_move_insn (gen_rtx_MEM (SImode,
529 plus_constant (stack_pointer_rtx, 8)),
530 gen_rtx_REG (SImode, 1));
533 /* If we use any of the callee-saved registers, save them now. */
534 mn10300_gen_multiple_store (mn10300_get_live_callee_saved_regs ());
536 /* Now put the frame pointer into the frame pointer register. */
537 if (frame_pointer_needed)
538 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
540 /* Allocate stack for this frame. */
542 emit_insn (gen_addsi3 (stack_pointer_rtx,
552 /* SIZE includes the fixed stack space needed for function calls. */
553 size = get_frame_size () + current_function_outgoing_args_size;
554 size += (current_function_outgoing_args_size ? 4 : 0);
556 /* Maybe cut back the stack, except for the register save area.
558 If the frame pointer exists, then use the frame pointer to
561 If the stack size + register save area is more than 255 bytes,
562 then the stack must be cut back here since the size + register
563 save size is too big for a ret/retf instruction.
565 Else leave it alone, it will be cut back as part of the
566 ret/retf instruction, or there wasn't any stack to begin with.
568 Under no circumstanes should the register save area be
569 deallocated here, that would leave a window where an interrupt
570 could occur and trash the register save area. */
571 if (frame_pointer_needed)
573 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
576 else if (size + REG_SAVE_BYTES > 255)
578 emit_insn (gen_addsi3 (stack_pointer_rtx,
584 /* Adjust the stack and restore callee-saved registers, if any. */
585 if (size || regs_ever_live[2] || regs_ever_live[3]
586 || regs_ever_live[6] || regs_ever_live[7]
587 || regs_ever_live[14] || regs_ever_live[15]
588 || regs_ever_live[16] || regs_ever_live[17]
589 || frame_pointer_needed)
590 emit_jump_insn (gen_return_internal_regs
591 (GEN_INT (size + REG_SAVE_BYTES)));
593 emit_jump_insn (gen_return_internal ());
596 /* Update the condition code from the insn. */
599 notice_update_cc (body, insn)
603 switch (get_attr_cc (insn))
606 /* Insn does not affect CC at all. */
610 /* Insn does not change CC, but the 0'th operand has been changed. */
611 if (cc_status.value1 != 0
612 && reg_overlap_mentioned_p (recog_data.operand[0], cc_status.value1))
613 cc_status.value1 = 0;
617 /* Insn sets the Z,N flags of CC to recog_data.operand[0].
620 cc_status.flags |= CC_NO_CARRY | CC_OVERFLOW_UNUSABLE;
621 cc_status.value1 = recog_data.operand[0];
625 /* Insn sets the Z,N,V flags of CC to recog_data.operand[0].
628 cc_status.flags |= CC_NO_CARRY;
629 cc_status.value1 = recog_data.operand[0];
633 /* The insn is a compare instruction. */
635 cc_status.value1 = SET_SRC (body);
639 /* The insn is a compare instruction. */
641 cc_status.value1 = SET_SRC (body);
642 cc_status.flags |= CC_INVERTED;
646 /* Insn doesn't leave CC in a usable state. */
655 /* Recognise the PARALLEL rtx generated by mn10300_gen_multiple_store().
656 This function is for MATCH_PARALLEL and so assumes OP is known to be
657 parallel. If OP is a multiple store, return a mask indicating which
658 registers it saves. Return 0 otherwise. */
661 store_multiple_operation (op, mode)
663 enum machine_mode mode ATTRIBUTE_UNUSED;
671 count = XVECLEN (op, 0);
675 /* Check that first instruction has the form (set (sp) (plus A B)) */
676 elt = XVECEXP (op, 0, 0);
677 if (GET_CODE (elt) != SET
678 || GET_CODE (SET_DEST (elt)) != REG
679 || REGNO (SET_DEST (elt)) != STACK_POINTER_REGNUM
680 || GET_CODE (SET_SRC (elt)) != PLUS)
683 /* Check that A is the stack pointer and B is the expected stack size.
684 For OP to match, each subsequent instruction should push a word onto
685 the stack. We therefore expect the first instruction to create
686 COUNT-1 stack slots. */
688 if (GET_CODE (XEXP (elt, 0)) != REG
689 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
690 || GET_CODE (XEXP (elt, 1)) != CONST_INT
691 || INTVAL (XEXP (elt, 1)) != -(count - 1) * 4)
694 /* Now go through the rest of the vector elements. They must be
695 ordered so that the first instruction stores the highest-numbered
696 register to the highest stack slot and that subsequent instructions
697 store a lower-numbered register to the slot below.
699 LAST keeps track of the smallest-numbered register stored so far.
700 MASK is the set of stored registers. */
701 last = FIRST_PSEUDO_REGISTER;
703 for (i = 1; i < count; i++)
705 /* Check that element i is a (set (mem M) R) and that R is valid. */
706 elt = XVECEXP (op, 0, i);
707 if (GET_CODE (elt) != SET
708 || GET_CODE (SET_DEST (elt)) != MEM
709 || GET_CODE (SET_SRC (elt)) != REG
710 || REGNO (SET_SRC (elt)) >= last)
713 /* R was OK, so provisionally add it to MASK. We return 0 in any
714 case if the rest of the instruction has a flaw. */
715 last = REGNO (SET_SRC (elt));
718 /* Check that M has the form (plus (sp) (const_int -I*4)) */
719 elt = XEXP (SET_DEST (elt), 0);
720 if (GET_CODE (elt) != PLUS
721 || GET_CODE (XEXP (elt, 0)) != REG
722 || REGNO (XEXP (elt, 0)) != STACK_POINTER_REGNUM
723 || GET_CODE (XEXP (elt, 1)) != CONST_INT
724 || INTVAL (XEXP (elt, 1)) != -i * 4)
728 /* All or none of the callee-saved extended registers must be in the set. */
729 if ((mask & 0x3c000) != 0
730 && (mask & 0x3c000) != 0x3c000)
736 /* Return true if OP is a valid call operand. */
739 call_address_operand (op, mode)
741 enum machine_mode mode ATTRIBUTE_UNUSED;
743 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
746 /* What (if any) secondary registers are needed to move IN with mode
747 MODE into a register in register class CLASS.
749 We might be able to simplify this. */
751 secondary_reload_class (class, mode, in)
752 enum reg_class class;
753 enum machine_mode mode;
756 /* Memory loads less than a full word wide can't have an
757 address or stack pointer destination. They must use
758 a data register as an intermediate register. */
759 if ((GET_CODE (in) == MEM
760 || (GET_CODE (in) == REG
761 && REGNO (in) >= FIRST_PSEUDO_REGISTER)
762 || (GET_CODE (in) == SUBREG
763 && GET_CODE (SUBREG_REG (in)) == REG
764 && REGNO (SUBREG_REG (in)) >= FIRST_PSEUDO_REGISTER))
765 && (mode == QImode || mode == HImode)
766 && (class == ADDRESS_REGS || class == SP_REGS
767 || class == SP_OR_ADDRESS_REGS))
770 return DATA_OR_EXTENDED_REGS;
774 /* We can't directly load sp + const_int into a data register;
775 we must use an address register as an intermediate. */
777 && class != ADDRESS_REGS
778 && class != SP_OR_ADDRESS_REGS
779 && class != SP_OR_EXTENDED_REGS
780 && class != ADDRESS_OR_EXTENDED_REGS
781 && class != SP_OR_ADDRESS_OR_EXTENDED_REGS
782 && (in == stack_pointer_rtx
783 || (GET_CODE (in) == PLUS
784 && (XEXP (in, 0) == stack_pointer_rtx
785 || XEXP (in, 1) == stack_pointer_rtx))))
788 if (GET_CODE (in) == PLUS
789 && (XEXP (in, 0) == stack_pointer_rtx
790 || XEXP (in, 1) == stack_pointer_rtx))
793 return DATA_OR_EXTENDED_REGS;
797 /* Otherwise assume no secondary reloads are needed. */
802 initial_offset (from, to)
805 /* The difference between the argument pointer and the frame pointer
806 is the size of the callee register save area. */
807 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM)
809 if (regs_ever_live[2] || regs_ever_live[3]
810 || regs_ever_live[6] || regs_ever_live[7]
811 || regs_ever_live[14] || regs_ever_live[15]
812 || regs_ever_live[16] || regs_ever_live[17]
813 || frame_pointer_needed)
814 return REG_SAVE_BYTES;
819 /* The difference between the argument pointer and the stack pointer is
820 the sum of the size of this function's frame, the callee register save
821 area, and the fixed stack space needed for function calls (if any). */
822 if (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
824 if (regs_ever_live[2] || regs_ever_live[3]
825 || regs_ever_live[6] || regs_ever_live[7]
826 || regs_ever_live[14] || regs_ever_live[15]
827 || regs_ever_live[16] || regs_ever_live[17]
828 || frame_pointer_needed)
829 return (get_frame_size () + REG_SAVE_BYTES
830 + (current_function_outgoing_args_size
831 ? current_function_outgoing_args_size + 4 : 0));
833 return (get_frame_size ()
834 + (current_function_outgoing_args_size
835 ? current_function_outgoing_args_size + 4 : 0));
838 /* The difference between the frame pointer and stack pointer is the sum
839 of the size of this function's frame and the fixed stack space needed
840 for function calls (if any). */
841 if (from == FRAME_POINTER_REGNUM && to == STACK_POINTER_REGNUM)
842 return (get_frame_size ()
843 + (current_function_outgoing_args_size
844 ? current_function_outgoing_args_size + 4 : 0));
849 /* Flush the argument registers to the stack for a stdarg function;
850 return the new argument pointer. */
852 mn10300_builtin_saveregs ()
855 tree fntype = TREE_TYPE (current_function_decl);
856 int argadj = ((!(TYPE_ARG_TYPES (fntype) != 0
857 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype)))
859 ? UNITS_PER_WORD : 0);
860 int set = get_varargs_alias_set ();
863 offset = plus_constant (current_function_arg_offset_rtx, argadj);
865 offset = current_function_arg_offset_rtx;
867 mem = gen_rtx_MEM (SImode, current_function_internal_arg_pointer);
868 MEM_ALIAS_SET (mem) = set;
869 emit_move_insn (mem, gen_rtx_REG (SImode, 0));
871 mem = gen_rtx_MEM (SImode,
872 plus_constant (current_function_internal_arg_pointer, 4));
873 MEM_ALIAS_SET (mem) = set;
874 emit_move_insn (mem, gen_rtx_REG (SImode, 1));
876 return copy_to_reg (expand_binop (Pmode, add_optab,
877 current_function_internal_arg_pointer,
878 offset, 0, 0, OPTAB_LIB_WIDEN));
882 mn10300_va_start (stdarg_p, valist, nextarg)
888 nextarg = expand_builtin_saveregs ();
890 std_expand_builtin_va_start (stdarg_p, valist, nextarg);
894 mn10300_va_arg (valist, type)
897 HOST_WIDE_INT align, rsize;
900 /* Compute the rounded size of the type. */
901 align = PARM_BOUNDARY / BITS_PER_UNIT;
902 rsize = (((int_size_in_bytes (type) + align - 1) / align) * align);
904 t = build (POSTINCREMENT_EXPR, TREE_TYPE (valist), valist,
905 build_int_2 ((rsize > 8 ? 4 : rsize), 0));
906 TREE_SIDE_EFFECTS (t) = 1;
908 ptr = build_pointer_type (type);
910 /* "Large" types are passed by reference. */
913 pptr = build_pointer_type (ptr);
914 t = build1 (NOP_EXPR, pptr, t);
915 TREE_SIDE_EFFECTS (t) = 1;
917 t = build1 (INDIRECT_REF, ptr, t);
918 TREE_SIDE_EFFECTS (t) = 1;
922 t = build1 (NOP_EXPR, ptr, t);
923 TREE_SIDE_EFFECTS (t) = 1;
927 return expand_expr (t, NULL_RTX, Pmode, EXPAND_NORMAL);
930 /* Return an RTX to represent where a value with mode MODE will be returned
931 from a function. If the result is 0, the argument is pushed. */
934 function_arg (cum, mode, type, named)
935 CUMULATIVE_ARGS *cum;
936 enum machine_mode mode;
938 int named ATTRIBUTE_UNUSED;
943 /* We only support using 2 data registers as argument registers. */
946 /* Figure out the size of the object to be passed. */
948 size = int_size_in_bytes (type);
950 size = GET_MODE_SIZE (mode);
952 /* Figure out the alignment of the object to be passed. */
955 cum->nbytes = (cum->nbytes + 3) & ~3;
957 /* Don't pass this arg via a register if all the argument registers
959 if (cum->nbytes > nregs * UNITS_PER_WORD)
962 /* Don't pass this arg via a register if it would be split between
963 registers and memory. */
964 if (type == NULL_TREE
965 && cum->nbytes + size > nregs * UNITS_PER_WORD)
968 switch (cum->nbytes / UNITS_PER_WORD)
971 result = gen_rtx_REG (mode, 0);
974 result = gen_rtx_REG (mode, 1);
983 /* Return the number of registers to use for an argument passed partially
984 in registers and partially in memory. */
987 function_arg_partial_nregs (cum, mode, type, named)
988 CUMULATIVE_ARGS *cum;
989 enum machine_mode mode;
991 int named ATTRIBUTE_UNUSED;
995 /* We only support using 2 data registers as argument registers. */
998 /* Figure out the size of the object to be passed. */
1000 size = int_size_in_bytes (type);
1002 size = GET_MODE_SIZE (mode);
1004 /* Figure out the alignment of the object to be passed. */
1007 cum->nbytes = (cum->nbytes + 3) & ~3;
1009 /* Don't pass this arg via a register if all the argument registers
1011 if (cum->nbytes > nregs * UNITS_PER_WORD)
1014 if (cum->nbytes + size <= nregs * UNITS_PER_WORD)
1017 /* Don't pass this arg via a register if it would be split between
1018 registers and memory. */
1019 if (type == NULL_TREE
1020 && cum->nbytes + size > nregs * UNITS_PER_WORD)
1023 return (nregs * UNITS_PER_WORD - cum->nbytes) / UNITS_PER_WORD;
1026 /* Output a tst insn. */
1028 output_tst (operand, insn)
1034 /* We can save a byte if we can find a register which has the value
1036 temp = PREV_INSN (insn);
1037 while (optimize && temp)
1041 /* We allow the search to go through call insns. We record
1042 the fact that we've past a CALL_INSN and reject matches which
1043 use call clobbered registers. */
1044 if (GET_CODE (temp) == CODE_LABEL
1045 || GET_CODE (temp) == JUMP_INSN
1046 || GET_CODE (temp) == BARRIER)
1049 if (GET_CODE (temp) == CALL_INSN)
1052 if (GET_CODE (temp) == NOTE)
1054 temp = PREV_INSN (temp);
1058 /* It must be an insn, see if it is a simple set. */
1059 set = single_set (temp);
1062 temp = PREV_INSN (temp);
1066 /* Are we setting a data register to zero (this does not win for
1069 If it's a call clobbered register, have we past a call?
1071 Make sure the register we find isn't the same as ourself;
1072 the mn10300 can't encode that.
1074 ??? reg_set_between_p return nonzero anytime we pass a CALL_INSN
1075 so the code to detect calls here isn't doing anything useful. */
1076 if (REG_P (SET_DEST (set))
1077 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1078 && !reg_set_between_p (SET_DEST (set), temp, insn)
1079 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1080 == REGNO_REG_CLASS (REGNO (operand)))
1081 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) != EXTENDED_REGS
1082 && REGNO (SET_DEST (set)) != REGNO (operand)
1084 || !call_used_regs[REGNO (SET_DEST (set))]))
1087 xoperands[0] = operand;
1088 xoperands[1] = SET_DEST (set);
1090 output_asm_insn ("cmp %1,%0", xoperands);
1094 if (REGNO_REG_CLASS (REGNO (operand)) == EXTENDED_REGS
1095 && REG_P (SET_DEST (set))
1096 && SET_SRC (set) == CONST0_RTX (GET_MODE (SET_DEST (set)))
1097 && !reg_set_between_p (SET_DEST (set), temp, insn)
1098 && (REGNO_REG_CLASS (REGNO (SET_DEST (set)))
1099 != REGNO_REG_CLASS (REGNO (operand)))
1100 && REGNO_REG_CLASS (REGNO (SET_DEST (set))) == EXTENDED_REGS
1101 && REGNO (SET_DEST (set)) != REGNO (operand)
1103 || !call_used_regs[REGNO (SET_DEST (set))]))
1106 xoperands[0] = operand;
1107 xoperands[1] = SET_DEST (set);
1109 output_asm_insn ("cmp %1,%0", xoperands);
1112 temp = PREV_INSN (temp);
1118 impossible_plus_operand (op, mode)
1120 enum machine_mode mode ATTRIBUTE_UNUSED;
1122 if (GET_CODE (op) != PLUS)
1125 if (XEXP (op, 0) == stack_pointer_rtx
1126 || XEXP (op, 1) == stack_pointer_rtx)
1132 /* Return 1 if X is a CONST_INT that is only 8 bits wide. This is used
1133 for the btst insn which may examine memory or a register (the memory
1134 variant only allows an unsigned 8 bit integer). */
1136 const_8bit_operand (op, mode)
1138 enum machine_mode mode ATTRIBUTE_UNUSED;
1140 return (GET_CODE (op) == CONST_INT
1142 && INTVAL (op) < 256);
1145 /* Similarly, but when using a zero_extract pattern for a btst where
1146 the source operand might end up in memory. */
1148 mask_ok_for_mem_btst (len, bit)
1161 /* MASK must bit into an 8bit value. */
1162 return (((mask & 0xff) == mask)
1163 || ((mask & 0xff00) == mask)
1164 || ((mask & 0xff0000) == mask)
1165 || ((mask & 0xff000000) == mask));
1168 /* Return 1 if X contains a symbolic expression. We know these
1169 expressions will have one of a few well defined forms, so
1170 we need only check those forms. */
1172 symbolic_operand (op, mode)
1174 enum machine_mode mode ATTRIBUTE_UNUSED;
1176 switch (GET_CODE (op))
1183 return ((GET_CODE (XEXP (op, 0)) == SYMBOL_REF
1184 || GET_CODE (XEXP (op, 0)) == LABEL_REF)
1185 && GET_CODE (XEXP (op, 1)) == CONST_INT);
1191 /* Try machine dependent ways of modifying an illegitimate address
1192 to be legitimate. If we find one, return the new valid address.
1193 This macro is used in only one place: `memory_address' in explow.c.
1195 OLDX is the address as it was before break_out_memory_refs was called.
1196 In some cases it is useful to look at this to decide what needs to be done.
1198 MODE and WIN are passed so that this macro can use
1199 GO_IF_LEGITIMATE_ADDRESS.
1201 Normally it is always safe for this macro to do nothing. It exists to
1202 recognize opportunities to optimize the output.
1204 But on a few ports with segmented architectures and indexed addressing
1205 (mn10300, hppa) it is used to rewrite certain problematical addresses. */
1207 legitimize_address (x, oldx, mode)
1209 rtx oldx ATTRIBUTE_UNUSED;
1210 enum machine_mode mode ATTRIBUTE_UNUSED;
1212 /* Uh-oh. We might have an address for x[n-100000]. This needs
1213 special handling to avoid creating an indexed memory address
1214 with x-100000 as the base. */
1215 if (GET_CODE (x) == PLUS
1216 && symbolic_operand (XEXP (x, 1), VOIDmode))
1218 /* Ugly. We modify things here so that the address offset specified
1219 by the index expression is computed first, then added to x to form
1220 the entire address. */
1222 rtx regx1, regy1, regy2, y;
1224 /* Strip off any CONST. */
1226 if (GET_CODE (y) == CONST)
1229 if (GET_CODE (y) == PLUS || GET_CODE (y) == MINUS)
1231 regx1 = force_reg (Pmode, force_operand (XEXP (x, 0), 0));
1232 regy1 = force_reg (Pmode, force_operand (XEXP (y, 0), 0));
1233 regy2 = force_reg (Pmode, force_operand (XEXP (y, 1), 0));
1234 regx1 = force_reg (Pmode,
1235 gen_rtx (GET_CODE (y), Pmode, regx1, regy2));
1236 return force_reg (Pmode, gen_rtx_PLUS (Pmode, regx1, regy1));
1243 mn10300_address_cost (x, unsig)
1251 switch (GET_CODE (x))
1254 switch (REGNO_REG_CLASS (REGNO (x)))
1279 return (mn10300_address_cost (XEXP (x, 0), unsig)
1280 + mn10300_address_cost (XEXP (x, 1), unsig));
1285 return ADDRESS_COST (XEXP (x, 0));
1289 return mn10300_address_cost (XEXP (x, 0), unsig);
1292 if (INTVAL (x) == 0)
1294 if (INTVAL (x) + (*unsig ? 0 : 0x80) < 0x100)
1296 if (INTVAL (x) + (*unsig ? 0 : 0x8000) < 0x10000)
1298 if (INTVAL (x) + (*unsig ? 0 : 0x800000) < 0x1000000)
1308 switch (GET_CODE (XEXP (x, 0)))
1311 return ADDRESS_COST (XEXP (x, 0));