1 /* Subroutines for insn-output.c for Matsushita MN10300 series
2 Copyright (C) 1996 Free Software Foundation, Inc.
3 Contributed by Jeff Law (law@cygnus.com).
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
28 #include "insn-config.h"
29 #include "conditions.h"
30 #include "insn-flags.h"
32 #include "insn-attr.h"
43 fprintf (file, "#\tGCC For the Matsushita MN10300\n");
45 fprintf (file, "# -O%d\n", optimize);
47 fprintf (file, "\n\n");
48 output_file_directive (file, main_input_filename);
60 if (INT_8_BITS (INTVAL (r)))
62 else if (INT_16_BITS (INTVAL (r)))
73 /* Print operand X using operand code CODE to assembly language output file
77 print_operand (file, x, code)
86 /* These are normal and reversed branches. */
87 switch (code == 'b' ? GET_CODE (x) : reverse_condition (GET_CODE (x)))
102 fprintf (file, "le");
105 fprintf (file, "lt");
108 fprintf (file, "cc");
111 fprintf (file, "hi");
114 fprintf (file, "ls");
117 fprintf (file, "cs");
124 /* This is used for the operand to a call instruction;
125 if it's a REG, enclose it in parens, else output
126 the operand normally. */
127 if (GET_CODE (x) == REG)
130 print_operand (file, x, 0);
134 print_operand (file, x, 0);
138 switch (GET_CODE (x))
142 output_address (XEXP (x, 0));
147 fprintf (file, "%s", reg_names[REGNO (x)]);
152 reg_names[REGNO (SUBREG_REG (x)) + SUBREG_WORD (x)]);
160 print_operand_address (file, x);
169 /* Output assembly language output for the address ADDR to FILE. */
172 print_operand_address (file, addr)
176 switch (GET_CODE (addr))
179 if (addr == stack_pointer_rtx)
180 print_operand_address (file, gen_rtx (PLUS, SImode,
184 print_operand (file, addr, 0);
189 if (REG_P (XEXP (addr, 0))
190 && REG_OK_FOR_BASE_P (XEXP (addr, 0)))
191 base = XEXP (addr, 0), index = XEXP (addr, 1);
192 else if (REG_P (XEXP (addr, 1))
193 && REG_OK_FOR_BASE_P (XEXP (addr, 1)))
194 base = XEXP (addr, 1), index = XEXP (addr, 0);
197 print_operand (file, index, 0);
199 print_operand (file, base, 0);;
203 output_addr_const (file, addr);
206 output_addr_const (file, addr);
214 unsigned int size = get_frame_size ();
216 /* For simplicity, we just movm all the callee saved registers to
217 the stack with one instruction, then set up the frame pointer
218 (if needed), and finally allocate the new stack. */
219 emit_insn (gen_store_movm ());
221 if (frame_pointer_needed)
223 emit_move_insn (frame_pointer_rtx, stack_pointer_rtx);
224 emit_insn (gen_addsi3 (frame_pointer_rtx,
230 emit_insn (gen_addsi3 (stack_pointer_rtx,
238 unsigned int size = get_frame_size ();
240 /* Cut back the stack. */
241 if (frame_pointer_needed)
243 emit_insn (gen_addsi3 (frame_pointer_rtx,
246 emit_move_insn (stack_pointer_rtx, frame_pointer_rtx);
251 emit_insn (gen_addsi3 (stack_pointer_rtx,
257 /* Deallocate remaining stack, restore registers and return. And return. */
258 emit_jump_insn (gen_return_internal (GEN_INT (size)));
261 /* Update the condition code from the insn. */
264 notice_update_cc (body, insn)
269 switch (get_attr_cc (insn))
272 /* Insn does not affect CC at all. */
276 /* Insn does not change CC, but the 0'th operand has been changed. */
277 if (cc_status.value1 != 0
278 && reg_overlap_mentioned_p (recog_operand[0], cc_status.value1))
279 cc_status.value1 = 0;
283 /* Insn sets the Z,N flags of CC to recog_operand[0].
284 V is always set to 0. C may or may not be set to 0 but that's ok
285 because alter_cond will change tests to use EQ/NE. */
287 cc_status.flags |= CC_NO_OVERFLOW;
288 cc_status.value1 = recog_operand[0];
293 /* The insn is a compare instruction. */
295 cc_status.value1 = SET_SRC (body);
299 /* Insn doesn't leave CC in a usable state. */
307 /* Return true if OP is a valid call operand. */
310 call_address_operand (op, mode)
312 enum machine_mode mode;
314 return (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == REG);
317 /* What (if any) secondary registers are needed to move IN with mode
318 MODE into a register from in register class CLASS.
320 We might be able to simplify this. */
322 secondary_reload_class (class, mode, in)
323 enum reg_class class;
324 enum machine_mode mode;
329 /* Memory loads less than a full word wide can't have an
330 address or stack pointer destination. They must use
331 a data register as an intermediate register. */
332 if (GET_CODE (in) == MEM
333 && (mode == QImode || mode == HImode)
334 && (class == ADDRESS_REGS || class == SP_REGS))
337 /* We can't directly load sp + const_int into a data register;
338 we must use an address register as an intermediate. */
339 if (class == DATA_REGS
340 && (in == stack_pointer_rtx
341 || (GET_CODE (in) == PLUS
342 && XEXP (in, 0) == stack_pointer_rtx)))
345 /* Get the true register. */
346 if (GET_CODE (in) == REG)
349 if (regno >= FIRST_PSEUDO_REGISTER)
350 regno = true_regnum (in);
353 /* We can't copy directly from a data register into the stack
356 && GET_CODE (in) == REG
360 /* Otherwise assume no secondary reloads are needed. */