1 /* Subroutines for insn-output.c for MIPS
2 Copyright (C) 1989, 90, 91, 93-97, 1998 Free Software Foundation, Inc.
3 Contributed by A. Lichnewsky, lich@inria.inria.fr.
4 Changes by Michael Meissner, meissner@osf.org.
5 64 bit r4000 support by Ian Lance Taylor, ian@cygnus.com, and
6 Brendan Eich, brendan@microunity.com.
8 This file is part of GNU CC.
10 GNU CC is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 2, or (at your option)
15 GNU CC is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with GNU CC; see the file COPYING. If not, write to
22 the Free Software Foundation, 59 Temple Place - Suite 330,
23 Boston, MA 02111-1307, USA. */
25 /* ??? The TARGET_FP_CALL_32 macros are intended to simulate a 32 bit
26 calling convention in 64 bit mode. It doesn't work though, and should
27 be replaced with something better designed. */
41 #include "hard-reg-set.h"
43 #include "insn-config.h"
44 #include "conditions.h"
45 #include "insn-flags.h"
46 #include "insn-attr.h"
47 #include "insn-codes.h"
51 #undef MAX /* sys/param.h may also define these */
55 #include <sys/types.h>
69 #if defined(USG) || defined(NO_STAB_H)
70 #include "gstab.h" /* If doing DBX on sysV, use our own stab.h. */
72 #include <stab.h> /* On BSD, use the system's stab.h. */
76 #define STAB_CODE_TYPE enum __stab_debug_code
78 #define STAB_CODE_TYPE int
83 extern char *getenv ();
84 extern char *mktemp ();
86 extern rtx adj_offsettable_operand ();
87 extern rtx copy_to_reg ();
89 extern tree lookup_name ();
90 extern void pfatal_with_name ();
91 extern void warning ();
93 extern FILE *asm_out_file;
95 static void mips16_output_gp_offset ();
96 static void build_mips16_function_stub ();
98 /* Enumeration for all of the relational tests, so that we can build
99 arrays indexed by the test type, and not worry about the order
116 /* Global variables for machine-dependent things. */
118 /* Threshold for data being put into the small data/bss area, instead
119 of the normal data area (references to the small data/bss area take
120 1 instruction, and use the global pointer, references to the normal
121 data area takes 2 instructions). */
122 int mips_section_threshold = -1;
124 /* Count the number of .file directives, so that .loc is up to date. */
125 int num_source_filenames = 0;
127 /* Count the number of sdb related labels are generated (to find block
128 start and end boundaries). */
129 int sdb_label_count = 0;
131 /* Next label # for each statement for Silicon Graphics IRIS systems. */
134 /* Non-zero if inside of a function, because the stupid MIPS asm can't
135 handle .files inside of functions. */
136 int inside_function = 0;
138 /* Files to separate the text and the data output, so that all of the data
139 can be emitted before the text, which will mean that the assembler will
140 generate smaller code, based on the global pointer. */
141 FILE *asm_out_data_file;
142 FILE *asm_out_text_file;
144 /* Linked list of all externals that are to be emitted when optimizing
145 for the global pointer if they haven't been declared by the end of
146 the program with an appropriate .comm or initialization. */
149 struct extern_list *next; /* next external */
150 char *name; /* name of the external */
151 int size; /* size in bytes */
154 /* Name of the file containing the current function. */
155 char *current_function_file = "";
157 /* Warning given that Mips ECOFF can't support changing files
158 within a function. */
159 int file_in_function_warning = FALSE;
161 /* Whether to suppress issuing .loc's because the user attempted
162 to change the filename within a function. */
163 int ignore_line_number = FALSE;
165 /* Number of nested .set noreorder, noat, nomacro, and volatile requests. */
171 /* The next branch instruction is a branch likely, not branch normal. */
172 int mips_branch_likely;
174 /* Count of delay slots and how many are filled. */
175 int dslots_load_total;
176 int dslots_load_filled;
177 int dslots_jump_total;
178 int dslots_jump_filled;
180 /* # of nops needed by previous insn */
181 int dslots_number_nops;
183 /* Number of 1/2/3 word references to data items (ie, not jal's). */
186 /* registers to check for load delay */
187 rtx mips_load_reg, mips_load_reg2, mips_load_reg3, mips_load_reg4;
189 /* Cached operands, and operator to compare for use in set/branch on
193 /* what type of branch to use */
194 enum cmp_type branch_type;
196 /* Number of previously seen half-pic pointers and references. */
197 static int prev_half_pic_ptrs = 0;
198 static int prev_half_pic_refs = 0;
200 /* which cpu are we scheduling for */
201 enum processor_type mips_cpu;
203 /* which instruction set architecture to use. */
206 #ifdef MIPS_ABI_DEFAULT
207 /* Which ABI to use. This is defined to a constant in mips.h if the target
208 doesn't support multiple ABIs. */
212 /* Strings to hold which cpu and instruction set architecture to use. */
213 char *mips_cpu_string; /* for -mcpu=<xxx> */
214 char *mips_isa_string; /* for -mips{1,2,3,4} */
215 char *mips_abi_string; /* for -mabi={o32,32,n32,n64,64,eabi} */
217 /* Whether we are generating mips16 code. This is a synonym for
218 TARGET_MIPS16, and exists for use as an attribute. */
221 /* This variable is set by -mno-mips16. We only care whether
222 -mno-mips16 appears or not, and using a string in this fashion is
223 just a way to avoid using up another bit in target_flags. */
224 char *mips_no_mips16_string;
226 /* Whether we are generating mips16 hard float code. In mips16 mode
227 we always set TARGET_SOFT_FLOAT; this variable is nonzero if
228 -msoft-float was not specified by the user, which means that we
229 should arrange to call mips32 hard floating point code. */
230 int mips16_hard_float;
232 /* This variable is set by -mentry. We only care whether -mentry
233 appears or not, and using a string in this fashion is just a way to
234 avoid using up another bit in target_flags. */
235 char *mips_entry_string;
237 /* Whether we should entry and exit pseudo-ops in mips16 mode. */
240 /* If TRUE, we split addresses into their high and low parts in the RTL. */
241 int mips_split_addresses;
243 /* Generating calls to position independent functions? */
244 enum mips_abicalls_type mips_abicalls;
246 /* High and low marks for floating point values which we will accept
247 as legitimate constants for LEGITIMATE_CONSTANT_P. These are
248 initialized in override_options. */
249 REAL_VALUE_TYPE dfhigh, dflow, sfhigh, sflow;
251 /* Array giving truth value on whether or not a given hard register
252 can support a given mode. */
253 char mips_hard_regno_mode_ok[(int)MAX_MACHINE_MODE][FIRST_PSEUDO_REGISTER];
255 /* Current frame information calculated by compute_frame_size. */
256 struct mips_frame_info current_frame_info;
258 /* Zero structure to initialize current_frame_info. */
259 struct mips_frame_info zero_frame_info;
261 /* Temporary filename used to buffer .text until end of program
263 static char *temp_filename;
265 /* Pseudo-reg holding the address of the current function when
266 generating embedded PIC code. Created by LEGITIMIZE_ADDRESS, used
267 by mips_finalize_pic if it was created. */
268 rtx embedded_pic_fnaddr_rtx;
270 /* The length of all strings seen when compiling for the mips16. This
271 is used to tell how many strings are in the constant pool, so that
272 we can see if we may have an overflow. This is reset each time the
273 constant pool is output. */
274 int mips_string_length;
276 /* Pseudo-reg holding the value of $28 in a mips16 function which
277 refers to GP relative global variables. */
278 rtx mips16_gp_pseudo_rtx;
280 /* In mips16 mode, we build a list of all the string constants we see
281 in a particular function. */
283 struct string_constant
285 struct string_constant *next;
289 static struct string_constant *string_constants;
291 /* List of all MIPS punctuation characters used by print_operand. */
292 char mips_print_operand_punct[256];
294 /* Map GCC register number to debugger register number. */
295 int mips_dbx_regno[FIRST_PSEUDO_REGISTER];
297 /* Buffer to use to enclose a load/store operation with %{ %} to
298 turn on .set volatile. */
299 static char volatile_buffer[60];
301 /* Hardware names for the registers. If -mrnames is used, this
302 will be overwritten with mips_sw_reg_names. */
304 char mips_reg_names[][8] =
306 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
307 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
308 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
309 "$24", "$25", "$26", "$27", "$28", "$sp", "$fp", "$31",
310 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
311 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
312 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
313 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
314 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
315 "$fcc5","$fcc6","$fcc7","$rap"
318 /* Mips software names for the registers, used to overwrite the
319 mips_reg_names array. */
321 char mips_sw_reg_names[][8] =
323 "$zero","$at", "$v0", "$v1", "$a0", "$a1", "$a2", "$a3",
324 "$t0", "$t1", "$t2", "$t3", "$t4", "$t5", "$t6", "$t7",
325 "$s0", "$s1", "$s2", "$s3", "$s4", "$s5", "$s6", "$s7",
326 "$t8", "$t9", "$k0", "$k1", "$gp", "$sp", "$fp", "$ra",
327 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
328 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
329 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
330 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31",
331 "hi", "lo", "accum","$fcc0","$fcc1","$fcc2","$fcc3","$fcc4",
332 "$fcc5","$fcc6","$fcc7","$rap"
335 /* Map hard register number to register class */
336 enum reg_class mips_regno_to_class[] =
338 GR_REGS, GR_REGS, M16_NA_REGS, M16_NA_REGS,
339 M16_REGS, M16_REGS, M16_REGS, M16_REGS,
340 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
341 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
342 M16_NA_REGS, M16_NA_REGS, GR_REGS, GR_REGS,
343 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
344 T_REG, GR_REGS, GR_REGS, GR_REGS,
345 GR_REGS, GR_REGS, GR_REGS, GR_REGS,
346 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
347 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
348 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
349 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
350 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
351 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
352 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
353 FP_REGS, FP_REGS, FP_REGS, FP_REGS,
354 HI_REG, LO_REG, HILO_REG, ST_REGS,
355 ST_REGS, ST_REGS, ST_REGS, ST_REGS,
356 ST_REGS, ST_REGS, ST_REGS, GR_REGS
359 /* Map register constraint character to register class. */
360 enum reg_class mips_char_to_class[256] =
362 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
363 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
364 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
365 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
366 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
367 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
368 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
369 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
370 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
371 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
372 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
373 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
374 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
375 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
376 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
377 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
378 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
379 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
380 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
381 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
382 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
383 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
384 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
385 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
386 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
387 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
388 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
389 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
390 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
391 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
392 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
393 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
394 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
395 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
396 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
397 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
398 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
399 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
400 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
401 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
402 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
403 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
404 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
405 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
406 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
407 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
408 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
409 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
410 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
411 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
412 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
413 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
414 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
415 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
416 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
417 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
418 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
419 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
420 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
421 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
422 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
423 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
424 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
425 NO_REGS, NO_REGS, NO_REGS, NO_REGS,
429 /* Return truth value of whether OP can be used as an operands
430 where a register or 16 bit unsigned integer is needed. */
433 uns_arith_operand (op, mode)
435 enum machine_mode mode;
437 if (GET_CODE (op) == CONST_INT && SMALL_INT_UNSIGNED (op))
440 return register_operand (op, mode);
443 /* Return truth value of whether OP can be used as an operands
444 where a 16 bit integer is needed */
447 arith_operand (op, mode)
449 enum machine_mode mode;
451 if (GET_CODE (op) == CONST_INT && SMALL_INT (op))
454 /* On the mips16, a GP relative value is a signed 16 bit offset. */
455 if (TARGET_MIPS16 && GET_CODE (op) == CONST && mips16_gp_offset_p (op))
458 return register_operand (op, mode);
461 /* Return truth value of whether OP can be used as an operand in a two
462 address arithmetic insn (such as set 123456,%o4) of mode MODE. */
465 arith32_operand (op, mode)
467 enum machine_mode mode;
469 if (GET_CODE (op) == CONST_INT)
472 return register_operand (op, mode);
475 /* Return truth value of whether OP is a integer which fits in 16 bits */
480 enum machine_mode mode;
482 return (GET_CODE (op) == CONST_INT && SMALL_INT (op));
485 /* Return truth value of whether OP is a 32 bit integer which is too big to
486 be loaded with one instruction. */
491 enum machine_mode mode;
495 if (GET_CODE (op) != CONST_INT)
499 if ((value & ~0x0000ffff) == 0) /* ior reg,$r0,value */
502 if (((unsigned long)(value + 32768)) <= 32767) /* subu reg,$r0,value */
505 if ((value & 0x0000ffff) == 0) /* lui reg,value>>16 */
511 /* Return truth value of whether OP is a register or the constant 0.
512 In mips16 mode, we only accept a register, since the mips16 does
516 reg_or_0_operand (op, mode)
518 enum machine_mode mode;
520 switch (GET_CODE (op))
528 return (INTVAL (op) == 0);
531 if (TARGET_MIPS16 || op != CONST0_RTX (mode))
538 return register_operand (op, mode);
544 /* Return truth value if a CONST_DOUBLE is ok to be a legitimate constant. */
547 mips_const_double_ok (op, mode)
549 enum machine_mode mode;
553 if (GET_CODE (op) != CONST_DOUBLE)
556 if (mode == VOIDmode)
559 if (mode != SFmode && mode != DFmode)
562 if (op == CONST0_RTX (mode))
565 /* ??? li.s does not work right with SGI's Irix 6 assembler. */
566 if (mips_abi != ABI_32 && mips_abi != ABI_EABI)
569 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
571 if (REAL_VALUE_ISNAN (d))
574 if (REAL_VALUE_NEGATIVE (d))
575 d = REAL_VALUE_NEGATE (d);
579 if (REAL_VALUES_LESS (d, dfhigh)
580 && REAL_VALUES_LESS (dflow, d))
585 if (REAL_VALUES_LESS (d, sfhigh)
586 && REAL_VALUES_LESS (sflow, d))
593 /* Accept the floating point constant 1 in the appropriate mode. */
596 const_float_1_operand (op, mode)
598 enum machine_mode mode;
601 static REAL_VALUE_TYPE onedf;
602 static REAL_VALUE_TYPE onesf;
603 static int one_initialized;
605 if (GET_CODE (op) != CONST_DOUBLE
606 || mode != GET_MODE (op)
607 || (mode != DFmode && mode != SFmode))
610 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
612 /* We only initialize these values if we need them, since we will
613 never get called unless mips_isa >= 4. */
614 if (! one_initialized)
616 onedf = REAL_VALUE_ATOF ("1.0", DFmode);
617 onesf = REAL_VALUE_ATOF ("1.0", SFmode);
618 one_initialized = TRUE;
622 return REAL_VALUES_EQUAL (d, onedf);
624 return REAL_VALUES_EQUAL (d, onesf);
627 /* Return true if a memory load or store of REG plus OFFSET in MODE
628 can be represented in a single word on the mips16. */
631 mips16_simple_memory_operand (reg, offset, mode)
634 enum machine_mode mode;
640 /* We can't tell, because we don't know how the value will
641 eventually be accessed. Returning FALSE here does no great
642 harm; it just prevents some possible instruction scheduling. */
646 size = GET_MODE_SIZE (mode);
648 if (INTVAL (offset) % size != 0)
650 if (REGNO (reg) == STACK_POINTER_REGNUM && GET_MODE_SIZE (mode) == 4)
654 if (INTVAL (offset) >= 0 && INTVAL (offset) < off * size)
659 /* Return truth value if a memory operand fits in a single instruction
660 (ie, register + small offset). */
663 simple_memory_operand (op, mode)
665 enum machine_mode mode;
667 rtx addr, plus0, plus1;
669 /* Eliminate non-memory operations */
670 if (GET_CODE (op) != MEM)
673 /* dword operations really put out 2 instructions, so eliminate them. */
674 /* ??? This isn't strictly correct. It is OK to accept multiword modes
675 here, since the length attributes are being set correctly, but only
676 if the address is offsettable. LO_SUM is not offsettable. */
677 if (GET_MODE_SIZE (GET_MODE (op)) > UNITS_PER_WORD)
680 /* Decode the address now. */
682 switch (GET_CODE (addr))
694 return SMALL_INT (op);
697 plus0 = XEXP (addr, 0);
698 plus1 = XEXP (addr, 1);
699 if (GET_CODE (plus0) == REG
700 && GET_CODE (plus1) == CONST_INT
703 || mips16_simple_memory_operand (plus0, plus1, mode)))
706 else if (GET_CODE (plus1) == REG
707 && GET_CODE (plus0) == CONST_INT
710 || mips16_simple_memory_operand (plus1, plus0, mode)))
717 /* We used to allow small symbol refs here (ie, stuff in .sdata
718 or .sbss), but this causes some bugs in G++. Also, it won't
719 interfere if the MIPS linker rewrites the store instruction
720 because the function is PIC. */
722 case LABEL_REF: /* never gp relative */
726 /* If -G 0, we can never have a GP relative memory operation.
727 Also, save some time if not optimizing. */
732 rtx offset = const0_rtx;
733 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
734 if (GET_CODE (op) != SYMBOL_REF)
737 /* let's be paranoid.... */
738 if (! SMALL_INT (offset))
744 return SYMBOL_REF_FLAG (addr);
747 /* This SYMBOL_REF case is for the mips16. If the above case is
748 reenabled, this one should be merged in. */
750 /* References to the constant pool on the mips16 use a small
751 offset if the function is small. The only time we care about
752 getting this right is during delayed branch scheduling, so
753 don't need to check until then. The machine_dependent_reorg
754 function will set the total length of the instructions used
755 in the function in current_frame_info. If that is small
756 enough, we know for sure that this is a small offset. It
757 would be better if we could take into account the location of
758 the instruction within the function, but we can't, because we
759 don't know where we are. */
761 && CONSTANT_POOL_ADDRESS_P (addr)
762 && current_frame_info.insns_len > 0)
766 size = current_frame_info.insns_len + get_pool_size ();
767 if (GET_MODE_SIZE (mode) == 4)
768 return size < 4 * 0x100;
769 else if (GET_MODE_SIZE (mode) == 8)
770 return size < 8 * 0x20;
781 /* Return true for a memory address that can be used to load or store
785 double_memory_operand (op, mode)
787 enum machine_mode mode;
791 if (GET_CODE (op) != MEM
792 || ! memory_operand (op, mode))
794 /* During reload, we accept a pseudo register if it has an
795 appropriate memory address. If we don't do this, we will
796 wind up reloading into a register, and then reloading that
797 register from memory, when we could just reload directly from
799 if (reload_in_progress
800 && GET_CODE (op) == REG
801 && REGNO (op) >= FIRST_PSEUDO_REGISTER
802 && reg_renumber[REGNO (op)] < 0
803 && reg_equiv_mem[REGNO (op)] != 0
804 && double_memory_operand (reg_equiv_mem[REGNO (op)], mode))
807 if (reload_in_progress
809 && GET_CODE (op) == MEM)
815 /* During reload on the mips16, we accept a large offset
816 from the frame pointer or the stack pointer. This large
817 address will get reloaded anyhow. */
818 if (GET_CODE (addr) == PLUS
819 && GET_CODE (XEXP (addr, 0)) == REG
820 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
821 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
822 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
823 && ! SMALL_INT (XEXP (addr, 1)))
824 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
825 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
828 /* Similarly, we accept a case where the memory address is
829 itself on the stack, and will be reloaded. */
830 if (GET_CODE (addr) == MEM)
834 maddr = XEXP (addr, 0);
835 if (GET_CODE (maddr) == PLUS
836 && GET_CODE (XEXP (maddr, 0)) == REG
837 && (REGNO (XEXP (maddr, 0)) == HARD_FRAME_POINTER_REGNUM
838 || REGNO (XEXP (maddr, 0)) == STACK_POINTER_REGNUM)
839 && ((GET_CODE (XEXP (maddr, 1)) == CONST_INT
840 && ! SMALL_INT (XEXP (maddr, 1)))
841 || (GET_CODE (XEXP (maddr, 1)) == SYMBOL_REF
842 && CONSTANT_POOL_ADDRESS_P (XEXP (maddr, 1)))))
846 /* We also accept the same case when we have a 16 bit signed
847 offset mixed in as well. The large address will get
848 reloaded, and the 16 bit offset will be OK. */
849 if (GET_CODE (addr) == PLUS
850 && GET_CODE (XEXP (addr, 0)) == MEM
851 && GET_CODE (XEXP (addr, 1)) == CONST_INT
852 && SMALL_INT (XEXP (addr, 1)))
854 addr = XEXP (XEXP (addr, 0), 0);
855 if (GET_CODE (addr) == PLUS
856 && GET_CODE (XEXP (addr, 0)) == REG
857 && (REGNO (XEXP (addr, 0)) == HARD_FRAME_POINTER_REGNUM
858 || REGNO (XEXP (addr, 0)) == STACK_POINTER_REGNUM)
859 && ((GET_CODE (XEXP (addr, 1)) == CONST_INT
860 && ! SMALL_INT (XEXP (addr, 1)))
861 || (GET_CODE (XEXP (addr, 1)) == SYMBOL_REF
862 && CONSTANT_POOL_ADDRESS_P (XEXP (addr, 1)))))
872 /* In this case we can use an instruction like sd. */
876 /* Make sure that 4 added to the address is a valid memory address.
877 This essentially just checks for overflow in an added constant. */
881 if (CONSTANT_ADDRESS_P (addr))
884 return memory_address_p ((GET_MODE_CLASS (mode) == MODE_INT
887 plus_constant_for_output (addr, 4));
890 /* Return true if the code of this rtx pattern is EQ or NE. */
893 equality_op (op, mode)
895 enum machine_mode mode;
897 if (mode != GET_MODE (op))
900 return (GET_CODE (op) == EQ || GET_CODE (op) == NE);
903 /* Return true if the code is a relational operations (EQ, LE, etc.) */
908 enum machine_mode mode;
910 if (mode != GET_MODE (op))
913 return (GET_RTX_CLASS (GET_CODE (op)) == '<');
916 /* Return true if the operand is either the PC or a label_ref. */
919 pc_or_label_operand (op, mode)
921 enum machine_mode mode;
926 if (GET_CODE (op) == LABEL_REF)
932 /* Test for a valid operand for a call instruction.
933 Don't allow the arg pointer register or virtual regs
934 since they may change into reg + const, which the patterns
938 call_insn_operand (op, mode)
940 enum machine_mode mode;
942 if (CONSTANT_ADDRESS_P (op)
943 || (GET_CODE (op) == REG && op != arg_pointer_rtx
944 && ! (REGNO (op) >= FIRST_PSEUDO_REGISTER
945 && REGNO (op) <= LAST_VIRTUAL_REGISTER)))
950 /* Return true if OPERAND is valid as a source operand for a move
954 move_operand (op, mode)
956 enum machine_mode mode;
958 /* Accept any general operand after reload has started; doing so
959 avoids losing if reload does an in-place replacement of a register
960 with a SYMBOL_REF or CONST. */
961 return (general_operand (op, mode)
962 && (! (mips_split_addresses && mips_check_split (op, mode))
963 || reload_in_progress
966 && GET_CODE (op) == SYMBOL_REF
967 && ! mips16_constant (op, mode, 1, 0)));
972 /* Return true if OPERAND is valid as a source operand for movdi.
973 This accepts not only general_operand, but also sign extended
974 constants and registers. We need to accept sign extended constants
975 in case a sign extended register which is used in an expression,
976 and is equivalent to a constant, is spilled. */
979 movdi_operand (op, mode)
981 enum machine_mode mode;
985 && GET_CODE (op) == SIGN_EXTEND
986 && GET_MODE (op) == DImode
987 && (GET_MODE (XEXP (op, 0)) == SImode
988 || (GET_CODE (XEXP (op, 0)) == CONST_INT
989 && GET_MODE (XEXP (op, 0)) == VOIDmode))
990 && (register_operand (XEXP (op, 0), SImode)
991 || immediate_operand (XEXP (op, 0), SImode)))
994 return (general_operand (op, mode)
996 && GET_CODE (op) == SYMBOL_REF
997 && ! mips16_constant (op, mode, 1, 0)));
1000 /* Like register_operand, but when in 64 bit mode also accept a sign
1001 extend of a 32 bit register, since the value is known to be already
1005 se_register_operand (op, mode)
1007 enum machine_mode mode;
1011 && GET_CODE (op) == SIGN_EXTEND
1012 && GET_MODE (op) == DImode
1013 && GET_MODE (XEXP (op, 0)) == SImode
1014 && register_operand (XEXP (op, 0), SImode))
1017 return register_operand (op, mode);
1020 /* Like reg_or_0_operand, but when in 64 bit mode also accept a sign
1021 extend of a 32 bit register, since the value is known to be already
1025 se_reg_or_0_operand (op, mode)
1027 enum machine_mode mode;
1031 && GET_CODE (op) == SIGN_EXTEND
1032 && GET_MODE (op) == DImode
1033 && GET_MODE (XEXP (op, 0)) == SImode
1034 && register_operand (XEXP (op, 0), SImode))
1037 return reg_or_0_operand (op, mode);
1040 /* Like uns_arith_operand, but when in 64 bit mode also accept a sign
1041 extend of a 32 bit register, since the value is known to be already
1045 se_uns_arith_operand (op, mode)
1047 enum machine_mode mode;
1051 && GET_CODE (op) == SIGN_EXTEND
1052 && GET_MODE (op) == DImode
1053 && GET_MODE (XEXP (op, 0)) == SImode
1054 && register_operand (XEXP (op, 0), SImode))
1057 return uns_arith_operand (op, mode);
1060 /* Like arith_operand, but when in 64 bit mode also accept a sign
1061 extend of a 32 bit register, since the value is known to be already
1065 se_arith_operand (op, mode)
1067 enum machine_mode mode;
1071 && GET_CODE (op) == SIGN_EXTEND
1072 && GET_MODE (op) == DImode
1073 && GET_MODE (XEXP (op, 0)) == SImode
1074 && register_operand (XEXP (op, 0), SImode))
1077 return arith_operand (op, mode);
1080 /* Like nonmemory_operand, but when in 64 bit mode also accept a sign
1081 extend of a 32 bit register, since the value is known to be already
1085 se_nonmemory_operand (op, mode)
1087 enum machine_mode mode;
1091 && GET_CODE (op) == SIGN_EXTEND
1092 && GET_MODE (op) == DImode
1093 && GET_MODE (XEXP (op, 0)) == SImode
1094 && register_operand (XEXP (op, 0), SImode))
1097 return nonmemory_operand (op, mode);
1100 /* Like nonimmediate_operand, but when in 64 bit mode also accept a
1101 sign extend of a 32 bit register, since the value is known to be
1102 already sign extended. */
1105 se_nonimmediate_operand (op, mode)
1107 enum machine_mode mode;
1111 && GET_CODE (op) == SIGN_EXTEND
1112 && GET_MODE (op) == DImode
1113 && GET_MODE (XEXP (op, 0)) == SImode
1114 && register_operand (XEXP (op, 0), SImode))
1117 return nonimmediate_operand (op, mode);
1120 /* Accept any operand that can appear in a mips16 constant table
1121 instruction. We can't use any of the standard operand functions
1122 because for these instructions we accept values that are not
1123 accepted by LEGITIMATE_CONSTANT, such as arbitrary SYMBOL_REFs. */
1126 consttable_operand (op, mode)
1128 enum machine_mode mode;
1130 return CONSTANT_P (op);
1133 /* Return true if we split the address into high and low parts. */
1135 /* ??? We should also handle reg+array somewhere. We get four
1136 instructions currently, lui %hi/addui %lo/addui reg/lw. Better is
1137 lui %hi/addui reg/lw %lo. Fixing GO_IF_LEGITIMATE_ADDRESS to accept
1138 (plus (reg) (symbol_ref)) doesn't work because the SYMBOL_REF is broken
1139 out of the address, then we have 4 instructions to combine. Perhaps
1140 add a 3->2 define_split for combine. */
1142 /* ??? We could also split a CONST_INT here if it is a large_int().
1143 However, it doesn't seem to be very useful to have %hi(constant).
1144 We would be better off by doing the masking ourselves and then putting
1145 the explicit high part of the constant in the RTL. This will give better
1146 optimization. Also, %hi(constant) needs assembler changes to work.
1147 There is already a define_split that does this. */
1150 mips_check_split (address, mode)
1152 enum machine_mode mode;
1154 /* ??? This is the same check used in simple_memory_operand.
1155 We use it here because LO_SUM is not offsettable. */
1156 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD)
1159 if ((GET_CODE (address) == SYMBOL_REF && ! SYMBOL_REF_FLAG (address))
1160 || (GET_CODE (address) == CONST
1161 && GET_CODE (XEXP (XEXP (address, 0), 0)) == SYMBOL_REF
1162 && ! SYMBOL_REF_FLAG (XEXP (XEXP (address, 0), 0)))
1163 || GET_CODE (address) == LABEL_REF)
1169 /* We need a lot of little routines to check constant values on the
1170 mips16. These are used to figure out how long the instruction will
1171 be. It would be much better to do this using constraints, but
1172 there aren't nearly enough letters available. */
1175 m16_check_op (op, low, high, mask)
1181 return (GET_CODE (op) == CONST_INT
1182 && INTVAL (op) >= low
1183 && INTVAL (op) <= high
1184 && (INTVAL (op) & mask) == 0);
1188 m16_uimm3_b (op, mode)
1190 enum machine_mode mode;
1192 return m16_check_op (op, 0x1, 0x8, 0);
1196 m16_simm4_1 (op, mode)
1198 enum machine_mode mode;
1200 return m16_check_op (op, - 0x8, 0x7, 0);
1204 m16_nsimm4_1 (op, mode)
1206 enum machine_mode mode;
1208 return m16_check_op (op, - 0x7, 0x8, 0);
1212 m16_simm5_1 (op, mode)
1214 enum machine_mode mode;
1216 return m16_check_op (op, - 0x10, 0xf, 0);
1220 m16_nsimm5_1 (op, mode)
1222 enum machine_mode mode;
1224 return m16_check_op (op, - 0xf, 0x10, 0);
1228 m16_uimm5_4 (op, mode)
1230 enum machine_mode mode;
1232 return m16_check_op (op, (- 0x10) << 2, 0xf << 2, 3);
1236 m16_nuimm5_4 (op, mode)
1238 enum machine_mode mode;
1240 return m16_check_op (op, (- 0xf) << 2, 0x10 << 2, 3);
1244 m16_simm8_1 (op, mode)
1246 enum machine_mode mode;
1248 return m16_check_op (op, - 0x80, 0x7f, 0);
1252 m16_nsimm8_1 (op, mode)
1254 enum machine_mode mode;
1256 return m16_check_op (op, - 0x7f, 0x80, 0);
1260 m16_uimm8_1 (op, mode)
1262 enum machine_mode mode;
1264 return m16_check_op (op, 0x0, 0xff, 0);
1268 m16_nuimm8_1 (op, mode)
1270 enum machine_mode mode;
1272 return m16_check_op (op, - 0xff, 0x0, 0);
1276 m16_uimm8_m1_1 (op, mode)
1278 enum machine_mode mode;
1280 return m16_check_op (op, - 0x1, 0xfe, 0);
1284 m16_uimm8_4 (op, mode)
1286 enum machine_mode mode;
1288 return m16_check_op (op, 0x0, 0xff << 2, 3);
1292 m16_nuimm8_4 (op, mode)
1294 enum machine_mode mode;
1296 return m16_check_op (op, (- 0xff) << 2, 0x0, 3);
1300 m16_simm8_8 (op, mode)
1302 enum machine_mode mode;
1304 return m16_check_op (op, (- 0x80) << 3, 0x7f << 3, 7);
1308 m16_nsimm8_8 (op, mode)
1310 enum machine_mode mode;
1312 return m16_check_op (op, (- 0x7f) << 3, 0x80 << 3, 7);
1315 /* References to the string table on the mips16 only use a small
1316 offset if the function is small. See the comment in the SYMBOL_REF
1317 case in simple_memory_operand. We can't check for LABEL_REF here,
1318 because the offset is always large if the label is before the
1319 referencing instruction. */
1322 m16_usym8_4 (op, mode)
1324 enum machine_mode mode;
1326 if (GET_CODE (op) == SYMBOL_REF
1327 && SYMBOL_REF_FLAG (op)
1328 && current_frame_info.insns_len > 0
1329 && XSTR (op, 0)[0] == '*'
1330 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1331 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1332 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1335 struct string_constant *l;
1337 /* Make sure this symbol is on thelist of string constants to be
1338 output for this function. It is possible that it has already
1339 been output, in which case this requires a large offset. */
1340 for (l = string_constants; l != NULL; l = l->next)
1341 if (strcmp (l->label, XSTR (op, 0)) == 0)
1349 m16_usym5_4 (op, mode)
1351 enum machine_mode mode;
1353 if (GET_CODE (op) == SYMBOL_REF
1354 && SYMBOL_REF_FLAG (op)
1355 && current_frame_info.insns_len > 0
1356 && XSTR (op, 0)[0] == '*'
1357 && strncmp (XSTR (op, 0) + 1, LOCAL_LABEL_PREFIX,
1358 sizeof LOCAL_LABEL_PREFIX - 1) == 0
1359 && (current_frame_info.insns_len + get_pool_size () + mips_string_length
1362 struct string_constant *l;
1364 /* Make sure this symbol is on thelist of string constants to be
1365 output for this function. It is possible that it has already
1366 been output, in which case this requires a large offset. */
1367 for (l = string_constants; l != NULL; l = l->next)
1368 if (strcmp (l->label, XSTR (op, 0)) == 0)
1375 /* Returns an operand string for the given instruction's delay slot,
1376 after updating filled delay slot statistics.
1378 We assume that operands[0] is the target register that is set.
1380 In order to check the next insn, most of this functionality is moved
1381 to FINAL_PRESCAN_INSN, and we just set the global variables that
1384 /* ??? This function no longer does anything useful, because final_prescan_insn
1385 now will never emit a nop. */
1388 mips_fill_delay_slot (ret, type, operands, cur_insn)
1389 char *ret; /* normal string to return */
1390 enum delay_type type; /* type of delay */
1391 rtx operands[]; /* operands to use */
1392 rtx cur_insn; /* current insn */
1394 register rtx set_reg;
1395 register enum machine_mode mode;
1396 register rtx next_insn = (cur_insn) ? NEXT_INSN (cur_insn) : (rtx)0;
1397 register int num_nops;
1399 if (type == DELAY_LOAD || type == DELAY_FCMP)
1402 else if (type == DELAY_HILO)
1408 /* Make sure that we don't put nop's after labels. */
1409 next_insn = NEXT_INSN (cur_insn);
1410 while (next_insn != (rtx)0 && GET_CODE (next_insn) == NOTE)
1411 next_insn = NEXT_INSN (next_insn);
1413 dslots_load_total += num_nops;
1414 if (TARGET_DEBUG_F_MODE
1416 || type == DELAY_NONE
1417 || operands == (rtx *)0
1418 || cur_insn == (rtx)0
1419 || next_insn == (rtx)0
1420 || GET_CODE (next_insn) == CODE_LABEL
1421 || (set_reg = operands[0]) == (rtx)0)
1423 dslots_number_nops = 0;
1424 mips_load_reg = (rtx)0;
1425 mips_load_reg2 = (rtx)0;
1426 mips_load_reg3 = (rtx)0;
1427 mips_load_reg4 = (rtx)0;
1431 set_reg = operands[0];
1432 if (set_reg == (rtx)0)
1435 while (GET_CODE (set_reg) == SUBREG)
1436 set_reg = SUBREG_REG (set_reg);
1438 mode = GET_MODE (set_reg);
1439 dslots_number_nops = num_nops;
1440 mips_load_reg = set_reg;
1441 if (GET_MODE_SIZE (mode)
1442 > (FP_REG_P (REGNO (set_reg)) ? UNITS_PER_FPREG : UNITS_PER_WORD))
1443 mips_load_reg2 = gen_rtx (REG, SImode, REGNO (set_reg) + 1);
1447 if (type == DELAY_HILO)
1449 mips_load_reg3 = gen_rtx (REG, SImode, MD_REG_FIRST);
1450 mips_load_reg4 = gen_rtx (REG, SImode, MD_REG_FIRST+1);
1462 /* Determine whether a memory reference takes one (based off of the GP pointer),
1463 two (normal), or three (label + reg) instructions, and bump the appropriate
1464 counter for -mstats. */
1467 mips_count_memory_refs (op, num)
1473 rtx addr, plus0, plus1;
1474 enum rtx_code code0, code1;
1477 if (TARGET_DEBUG_B_MODE)
1479 fprintf (stderr, "\n========== mips_count_memory_refs:\n");
1483 /* Skip MEM if passed, otherwise handle movsi of address. */
1484 addr = (GET_CODE (op) != MEM) ? op : XEXP (op, 0);
1486 /* Loop, going through the address RTL */
1490 switch (GET_CODE (addr))
1501 plus0 = XEXP (addr, 0);
1502 plus1 = XEXP (addr, 1);
1503 code0 = GET_CODE (plus0);
1504 code1 = GET_CODE (plus1);
1514 if (code0 == CONST_INT)
1529 if (code1 == CONST_INT)
1536 if (code0 == SYMBOL_REF || code0 == LABEL_REF || code0 == CONST)
1543 if (code1 == SYMBOL_REF || code1 == LABEL_REF || code1 == CONST)
1553 n_words = 2; /* always 2 words */
1557 addr = XEXP (addr, 0);
1562 n_words = SYMBOL_REF_FLAG (addr) ? 1 : 2;
1571 n_words += additional;
1575 num_refs[n_words-1] += num;
1579 /* Return RTL for the offset from the current function to the
1583 embedded_pic_offset (x)
1586 if (embedded_pic_fnaddr_rtx == NULL)
1590 embedded_pic_fnaddr_rtx = gen_reg_rtx (Pmode);
1592 /* Output code at function start to initialize the pseudo-reg. */
1593 /* ??? We used to do this in FINALIZE_PIC, but that does not work for
1594 inline functions, because it is called after RTL for the function
1595 has been copied. The pseudo-reg in embedded_pic_fnaddr_rtx however
1596 does not get copied, and ends up not matching the rest of the RTL.
1597 This solution works, but means that we get unnecessary code to
1598 initialize this value every time a function is inlined into another
1601 emit_insn (gen_get_fnaddr (embedded_pic_fnaddr_rtx,
1602 XEXP (DECL_RTL (current_function_decl), 0)));
1603 seq = gen_sequence ();
1605 push_topmost_sequence ();
1606 emit_insn_after (seq, get_insns ());
1607 pop_topmost_sequence ();
1610 return gen_rtx (CONST, Pmode,
1611 gen_rtx (MINUS, Pmode, x,
1612 XEXP (DECL_RTL (current_function_decl), 0)));
1615 /* Return the appropriate instructions to move one operand to another. */
1618 mips_move_1word (operands, insn, unsignedp)
1624 rtx op0 = operands[0];
1625 rtx op1 = operands[1];
1626 enum rtx_code code0 = GET_CODE (op0);
1627 enum rtx_code code1 = GET_CODE (op1);
1628 enum machine_mode mode = GET_MODE (op0);
1629 int subreg_word0 = 0;
1630 int subreg_word1 = 0;
1631 enum delay_type delay = DELAY_NONE;
1633 while (code0 == SUBREG)
1635 subreg_word0 += SUBREG_WORD (op0);
1636 op0 = SUBREG_REG (op0);
1637 code0 = GET_CODE (op0);
1640 while (code1 == SUBREG)
1642 subreg_word1 += SUBREG_WORD (op1);
1643 op1 = SUBREG_REG (op1);
1644 code1 = GET_CODE (op1);
1647 /* For our purposes, a condition code mode is the same as SImode. */
1653 int regno0 = REGNO (op0) + subreg_word0;
1657 int regno1 = REGNO (op1) + subreg_word1;
1659 /* Just in case, don't do anything for assigning a register
1660 to itself, unless we are filling a delay slot. */
1661 if (regno0 == regno1 && set_nomacro == 0)
1664 else if (GP_REG_P (regno0))
1666 if (GP_REG_P (regno1))
1667 ret = "move\t%0,%1";
1669 else if (MD_REG_P (regno1))
1672 if (regno1 != HILO_REGNUM)
1678 else if (ST_REG_P (regno1) && mips_isa >= 4)
1679 ret = "li\t%0,1\n\tmovf\t%0,%.,%1";
1684 if (FP_REG_P (regno1))
1685 ret = "mfc1\t%0,%1";
1687 else if (regno1 == FPSW_REGNUM && mips_isa < 4)
1688 ret = "cfc1\t%0,$31";
1692 else if (FP_REG_P (regno0))
1694 if (GP_REG_P (regno1))
1697 ret = "mtc1\t%1,%0";
1700 if (FP_REG_P (regno1))
1701 ret = "mov.s\t%0,%1";
1704 else if (MD_REG_P (regno0))
1706 if (GP_REG_P (regno1))
1709 if (regno0 != HILO_REGNUM && ! TARGET_MIPS16)
1714 else if (regno0 == FPSW_REGNUM && mips_isa < 4)
1716 if (GP_REG_P (regno1))
1719 ret = "ctc1\t%0,$31";
1724 else if (code1 == MEM)
1729 mips_count_memory_refs (op1, 1);
1731 if (GP_REG_P (regno0))
1733 /* For loads, use the mode of the memory item, instead of the
1734 target, so zero/sign extend can use this code as well. */
1735 switch (GET_MODE (op1))
1744 ret = ((unsignedp && TARGET_64BIT)
1749 ret = (unsignedp) ? "lhu\t%0,%1" : "lh\t%0,%1";
1752 ret = (unsignedp) ? "lbu\t%0,%1" : "lb\t%0,%1";
1757 else if (FP_REG_P (regno0) && (mode == SImode || mode == SFmode))
1760 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
1762 int i = strlen (ret);
1763 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1766 sprintf (volatile_buffer, "%%{%s%%}", ret);
1767 ret = volatile_buffer;
1771 else if (code1 == CONST_INT
1772 || (code1 == CONST_DOUBLE
1773 && GET_MODE (op1) == VOIDmode))
1775 if (code1 == CONST_DOUBLE)
1777 /* This can happen when storing constants into long long
1778 bitfields. Just store the least significant word of
1780 operands[1] = op1 = GEN_INT (CONST_DOUBLE_LOW (op1));
1783 if (INTVAL (op1) == 0 && ! TARGET_MIPS16)
1785 if (GP_REG_P (regno0))
1786 ret = "move\t%0,%z1";
1788 else if (FP_REG_P (regno0))
1791 ret = "mtc1\t%z1,%0";
1794 else if (MD_REG_P (regno0))
1801 else if (GP_REG_P (regno0))
1803 /* Don't use X format, because that will give out of
1804 range numbers for 64 bit host and 32 bit target. */
1805 if (! TARGET_MIPS16)
1806 ret = "li\t%0,%1\t\t\t# %X1";
1809 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
1811 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
1812 ret = "li\t%0,%n1\n\tneg\t%0";
1817 else if (code1 == CONST_DOUBLE && mode == SFmode)
1819 if (op1 == CONST0_RTX (SFmode))
1821 if (GP_REG_P (regno0))
1822 ret = "move\t%0,%.";
1824 else if (FP_REG_P (regno0))
1827 ret = "mtc1\t%.,%0";
1834 ret = "li.s\t%0,%1";
1838 else if (code1 == LABEL_REF)
1841 mips_count_memory_refs (op1, 1);
1846 else if (code1 == SYMBOL_REF || code1 == CONST)
1848 if (HALF_PIC_P () && CONSTANT_P (op1) && HALF_PIC_ADDRESS_P (op1))
1850 rtx offset = const0_rtx;
1852 if (GET_CODE (op1) == CONST)
1853 op1 = eliminate_constant_term (XEXP (op1, 0), &offset);
1855 if (GET_CODE (op1) == SYMBOL_REF)
1857 operands[2] = HALF_PIC_PTR (op1);
1860 mips_count_memory_refs (operands[2], 1);
1862 if (INTVAL (offset) == 0)
1865 ret = (unsignedp && TARGET_64BIT
1871 dslots_load_total++;
1872 operands[3] = offset;
1873 if (unsignedp && TARGET_64BIT)
1874 ret = (SMALL_INT (offset))
1875 ? "lwu\t%0,%2%#\n\tadd\t%0,%0,%3"
1876 : "lwu\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1878 ret = (SMALL_INT (offset))
1879 ? "lw\t%0,%2%#\n\tadd\t%0,%0,%3"
1880 : "lw\t%0,%2%#\n\t%[li\t%@,%3\n\tadd\t%0,%0,%@%]";
1884 else if (TARGET_MIPS16
1886 && GET_CODE (XEXP (op1, 0)) == REG
1887 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
1889 /* This case arises on the mips16; see
1890 mips16_gp_pseudo_reg. */
1891 ret = "move\t%0,%+";
1893 else if (TARGET_MIPS16
1894 && code1 == SYMBOL_REF
1895 && SYMBOL_REF_FLAG (op1)
1896 && (XSTR (op1, 0)[0] != '*'
1897 || strncmp (XSTR (op1, 0) + 1,
1899 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
1901 /* This can occur when reloading the address of a GP
1902 relative symbol on the mips16. */
1903 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
1908 mips_count_memory_refs (op1, 1);
1914 else if (code1 == PLUS)
1916 rtx add_op0 = XEXP (op1, 0);
1917 rtx add_op1 = XEXP (op1, 1);
1919 if (GET_CODE (XEXP (op1, 1)) == REG && GET_CODE (XEXP (op1, 0)) == CONST_INT)
1921 add_op0 = XEXP (op1, 1); /* reverse operands */
1922 add_op1 = XEXP (op1, 0);
1925 operands[2] = add_op0;
1926 operands[3] = add_op1;
1927 ret = "add%:\t%0,%2,%3";
1930 else if (code1 == HIGH)
1932 operands[1] = XEXP (op1, 0);
1933 ret = "lui\t%0,%%hi(%1)";
1937 else if (code0 == MEM)
1940 mips_count_memory_refs (op0, 1);
1944 int regno1 = REGNO (op1) + subreg_word1;
1946 if (GP_REG_P (regno1))
1951 case SFmode: ret = "sw\t%1,%0"; break;
1952 case SImode: ret = "sw\t%1,%0"; break;
1953 case HImode: ret = "sh\t%1,%0"; break;
1954 case QImode: ret = "sb\t%1,%0"; break;
1958 else if (FP_REG_P (regno1) && (mode == SImode || mode == SFmode))
1962 else if (code1 == CONST_INT && INTVAL (op1) == 0)
1967 case SFmode: ret = "sw\t%z1,%0"; break;
1968 case SImode: ret = "sw\t%z1,%0"; break;
1969 case HImode: ret = "sh\t%z1,%0"; break;
1970 case QImode: ret = "sb\t%z1,%0"; break;
1974 else if (code1 == CONST_DOUBLE && op1 == CONST0_RTX (mode))
1979 case SFmode: ret = "sw\t%.,%0"; break;
1980 case SImode: ret = "sw\t%.,%0"; break;
1981 case HImode: ret = "sh\t%.,%0"; break;
1982 case QImode: ret = "sb\t%.,%0"; break;
1986 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
1988 int i = strlen (ret);
1989 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
1992 sprintf (volatile_buffer, "%%{%s%%}", ret);
1993 ret = volatile_buffer;
1997 if (ret == (char *)0)
1999 abort_with_insn (insn, "Bad move");
2003 if (delay != DELAY_NONE)
2004 return mips_fill_delay_slot (ret, delay, operands, insn);
2010 /* Return the appropriate instructions to move 2 words */
2013 mips_move_2words (operands, insn)
2018 rtx op0 = operands[0];
2019 rtx op1 = operands[1];
2020 enum rtx_code code0 = GET_CODE (operands[0]);
2021 enum rtx_code code1 = GET_CODE (operands[1]);
2022 int subreg_word0 = 0;
2023 int subreg_word1 = 0;
2024 enum delay_type delay = DELAY_NONE;
2026 while (code0 == SUBREG)
2028 subreg_word0 += SUBREG_WORD (op0);
2029 op0 = SUBREG_REG (op0);
2030 code0 = GET_CODE (op0);
2033 if (code1 == SIGN_EXTEND)
2035 op1 = XEXP (op1, 0);
2036 code1 = GET_CODE (op1);
2039 while (code1 == SUBREG)
2041 subreg_word1 += SUBREG_WORD (op1);
2042 op1 = SUBREG_REG (op1);
2043 code1 = GET_CODE (op1);
2047 if (GET_CODE (operands[1]) == SIGN_EXTEND
2049 && code1 != CONST_INT
2050 /* The following three can happen as the result of a questionable
2052 && code1 != LABEL_REF
2053 && code1 != SYMBOL_REF
2059 int regno0 = REGNO (op0) + subreg_word0;
2063 int regno1 = REGNO (op1) + subreg_word1;
2065 /* Just in case, don't do anything for assigning a register
2066 to itself, unless we are filling a delay slot. */
2067 if (regno0 == regno1 && set_nomacro == 0)
2070 else if (FP_REG_P (regno0))
2072 if (FP_REG_P (regno1))
2073 ret = "mov.d\t%0,%1";
2081 abort_with_insn (insn, "Bad move");
2082 #ifdef TARGET_FP_CALL_32
2083 if (FP_CALL_GP_REG_P (regno1))
2084 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tdmtc1\t%1,%0";
2087 ret = "dmtc1\t%1,%0";
2090 ret = "mtc1\t%L1,%0\n\tmtc1\t%M1,%D0";
2094 else if (FP_REG_P (regno1))
2100 abort_with_insn (insn, "Bad move");
2101 #ifdef TARGET_FP_CALL_32
2102 if (FP_CALL_GP_REG_P (regno0))
2103 ret = "dmfc1\t%0,%1\n\tmfc1\t%D0,%1\n\tdsrl\t%0,32";
2106 ret = "dmfc1\t%0,%1";
2109 ret = "mfc1\t%L0,%1\n\tmfc1\t%M0,%D1";
2112 else if (MD_REG_P (regno0) && GP_REG_P (regno1) && !TARGET_MIPS16)
2117 if (regno0 != HILO_REGNUM)
2119 else if (regno1 == 0)
2120 ret = "mtlo\t%.\n\tmthi\t%.";
2123 ret = "mthi\t%M1\n\tmtlo\t%L1";
2126 else if (GP_REG_P (regno0) && MD_REG_P (regno1))
2131 if (regno1 != HILO_REGNUM)
2135 ret = "mfhi\t%M0\n\tmflo\t%L0";
2138 else if (TARGET_64BIT)
2139 ret = "move\t%0,%1";
2141 else if (regno0 != (regno1+1))
2142 ret = "move\t%0,%1\n\tmove\t%D0,%D1";
2145 ret = "move\t%D0,%D1\n\tmove\t%0,%1";
2148 else if (code1 == CONST_DOUBLE)
2150 /* Move zero from $0 unless !TARGET_64BIT and recipient
2151 is 64-bit fp reg, in which case generate a constant. */
2152 if (op1 != CONST0_RTX (GET_MODE (op1))
2153 || (TARGET_FLOAT64 && !TARGET_64BIT && FP_REG_P (regno0)))
2155 if (GET_MODE (op1) == DFmode)
2158 #ifdef TARGET_FP_CALL_32
2159 if (FP_CALL_GP_REG_P (regno0))
2161 if (TARGET_FLOAT64 && !TARGET_64BIT)
2163 split_double (op1, operands + 2, operands + 3);
2164 ret = "li\t%0,%2\n\tli\t%D0,%3";
2167 ret = "li.d\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2171 ret = "li.d\t%0,%1";
2174 else if (TARGET_64BIT)
2176 if (! TARGET_MIPS16)
2182 split_double (op1, operands + 2, operands + 3);
2183 ret = "li\t%0,%2\n\tli\t%D0,%3";
2189 if (GP_REG_P (regno0))
2191 #ifdef TARGET_FP_CALL_32
2192 && ! FP_CALL_GP_REG_P (regno0)
2196 : "move\t%0,%.\n\tmove\t%D0,%.";
2198 else if (FP_REG_P (regno0))
2201 ret = (TARGET_64BIT)
2203 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0";
2208 else if (code1 == CONST_INT && INTVAL (op1) == 0 && ! TARGET_MIPS16)
2210 if (GP_REG_P (regno0))
2211 ret = (TARGET_64BIT)
2213 : "move\t%0,%.\n\tmove\t%D0,%.";
2215 else if (FP_REG_P (regno0))
2218 ret = (TARGET_64BIT)
2222 : "mtc1\t%.,%0\n\tmtc1\t%.,%D0");
2224 else if (MD_REG_P (regno0))
2227 if (regno0 != HILO_REGNUM)
2230 ret = "mtlo\t%.\n\tmthi\t%.";
2234 else if (code1 == CONST_INT && GET_MODE (op0) == DImode && GP_REG_P (regno0))
2240 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2242 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2243 ret = "li\t%0,%n1\n\tneg\t%0";
2245 else if (GET_CODE (operands[1]) == SIGN_EXTEND)
2246 ret = "li\t%0,%1\t\t# %X1";
2247 else if (HOST_BITS_PER_WIDE_INT < 64)
2248 /* We can't use 'X' for negative numbers, because then we won't
2249 get the right value for the upper 32 bits. */
2250 ret = ((INTVAL (op1) < 0) ? "dli\t%0,%1\t\t\t# %X1"
2251 : "dli\t%0,%X1\t\t# %1");
2253 /* We must use 'X', because otherwise LONG_MIN will print as
2254 a number that the assembler won't accept. */
2255 ret = "dli\t%0,%X1\t\t# %1";
2257 else if (HOST_BITS_PER_WIDE_INT < 64)
2259 operands[2] = GEN_INT (INTVAL (operands[1]) >= 0 ? 0 : -1);
2262 if (INTVAL (op1) >= 0 && INTVAL (op1) <= 0xffff)
2263 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2264 else if (INTVAL (op1) < 0 && INTVAL (op1) >= -0xffff)
2266 operands[2] = GEN_INT (1);
2267 ret = "li\t%M0,%2\n\tneg\t%M0\n\tli\t%L0,%n1\n\tneg\t%L0";
2271 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2275 /* We use multiple shifts here, to avoid warnings about out
2276 of range shifts on 32 bit hosts. */
2277 operands[2] = GEN_INT (INTVAL (operands[1]) >> 16 >> 16);
2278 operands[1] = GEN_INT (INTVAL (operands[1]) << 16 << 16 >> 16 >> 16);
2279 ret = "li\t%M0,%2\n\tli\t%L0,%1";
2283 else if (code1 == MEM)
2288 mips_count_memory_refs (op1, 2);
2290 if (FP_REG_P (regno0))
2293 else if (TARGET_64BIT)
2295 #ifdef TARGET_FP_CALL_32
2296 if (FP_CALL_GP_REG_P (regno0))
2298 if (double_memory_operand (op1, GET_MODE (op1)))
2299 ret = "lwu\t%0,%1\n\tlwu\t%D0,4+%1";
2301 ret = "ld\t%0,%1\n\tdsll\t%D0,%0,32\n\tdsrl\t%D0,32\n\tdsrl\t%0,32";
2308 else if (double_memory_operand (op1, GET_MODE (op1)))
2310 operands[2] = adj_offsettable_operand (op1, 4);
2311 if (reg_mentioned_p (op0, op1))
2312 ret = "lw\t%D0,%2\n\tlw\t%0,%1";
2314 ret = "lw\t%0,%1\n\tlw\t%D0,%2";
2317 if (ret != (char *)0 && MEM_VOLATILE_P (op1))
2319 int i = strlen (ret);
2320 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2323 sprintf (volatile_buffer, "%%{%s%%}", ret);
2324 ret = volatile_buffer;
2328 else if (code1 == LABEL_REF)
2331 mips_count_memory_refs (op1, 2);
2333 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2334 /* We deliberately remove the 'a' from '%1', so that we don't
2335 have to add SIGN_EXTEND support to print_operand_address.
2336 print_operand will just call print_operand_address in this
2337 case, so there is no problem. */
2340 ret = "dla\t%0,%a1";
2342 else if (code1 == SYMBOL_REF
2347 && GET_CODE (XEXP (op1, 0)) == REG
2348 && REGNO (XEXP (op1, 0)) == GP_REG_FIRST + 28)
2350 /* This case arises on the mips16; see
2351 mips16_gp_pseudo_reg. */
2352 ret = "move\t%0,%+";
2354 else if (TARGET_MIPS16
2355 && code1 == SYMBOL_REF
2356 && SYMBOL_REF_FLAG (op1)
2357 && (XSTR (op1, 0)[0] != '*'
2358 || strncmp (XSTR (op1, 0) + 1,
2360 sizeof LOCAL_LABEL_PREFIX - 1) != 0))
2362 /* This can occur when reloading the address of a GP
2363 relative symbol on the mips16. */
2364 ret = "move\t%0,%+\n\taddu\t%0,%%gprel(%a1)";
2369 mips_count_memory_refs (op1, 2);
2371 if (GET_CODE (operands[1]) == SIGN_EXTEND)
2372 /* We deliberately remove the 'a' from '%1', so that we don't
2373 have to add SIGN_EXTEND support to print_operand_address.
2374 print_operand will just call print_operand_address in this
2375 case, so there is no problem. */
2378 ret = "dla\t%0,%a1";
2383 else if (code0 == MEM)
2387 int regno1 = REGNO (op1) + subreg_word1;
2389 if (FP_REG_P (regno1))
2392 else if (TARGET_64BIT)
2394 #ifdef TARGET_FP_CALL_32
2395 if (FP_CALL_GP_REG_P (regno1))
2396 ret = "dsll\t%1,32\n\tor\t%1,%D1\n\tsd\t%1,%0";
2402 else if (double_memory_operand (op0, GET_MODE (op0)))
2404 operands[2] = adj_offsettable_operand (op0, 4);
2405 ret = "sw\t%1,%0\n\tsw\t%D1,%2";
2409 else if (((code1 == CONST_INT && INTVAL (op1) == 0)
2410 || (code1 == CONST_DOUBLE
2411 && op1 == CONST0_RTX (GET_MODE (op1))))
2413 || double_memory_operand (op0, GET_MODE (op0))))
2419 operands[2] = adj_offsettable_operand (op0, 4);
2420 ret = "sw\t%.,%0\n\tsw\t%.,%2";
2425 mips_count_memory_refs (op0, 2);
2427 if (ret != (char *)0 && MEM_VOLATILE_P (op0))
2429 int i = strlen (ret);
2430 if (i > sizeof (volatile_buffer) - sizeof ("%{%}"))
2433 sprintf (volatile_buffer, "%%{%s%%}", ret);
2434 ret = volatile_buffer;
2438 if (ret == (char *)0)
2440 abort_with_insn (insn, "Bad move");
2444 if (delay != DELAY_NONE)
2445 return mips_fill_delay_slot (ret, delay, operands, insn);
2451 /* Provide the costs of an addressing mode that contains ADDR.
2452 If ADDR is not a valid address, its cost is irrelevant. */
2455 mips_address_cost (addr)
2458 switch (GET_CODE (addr))
2471 rtx offset = const0_rtx;
2472 addr = eliminate_constant_term (XEXP (addr, 0), &offset);
2473 if (GET_CODE (addr) == LABEL_REF)
2476 if (GET_CODE (addr) != SYMBOL_REF)
2479 if (! SMALL_INT (offset))
2485 return SYMBOL_REF_FLAG (addr) ? 1 : 2;
2489 register rtx plus0 = XEXP (addr, 0);
2490 register rtx plus1 = XEXP (addr, 1);
2492 if (GET_CODE (plus0) != REG && GET_CODE (plus1) == REG)
2494 plus0 = XEXP (addr, 1);
2495 plus1 = XEXP (addr, 0);
2498 if (GET_CODE (plus0) != REG)
2501 switch (GET_CODE (plus1))
2507 return (SMALL_INT (plus1) ? 1 : 2);
2514 return mips_address_cost (plus1) + 1;
2522 /* Return true if X is an address which needs a temporary register when
2523 reloaded while generating PIC code. */
2526 pic_address_needs_scratch (x)
2529 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */
2530 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS
2531 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF
2532 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
2533 && ! SMALL_INT (XEXP (XEXP (x, 0), 1)))
2539 /* Make normal rtx_code into something we can index from an array */
2541 static enum internal_test
2542 map_test_to_internal_test (test_code)
2543 enum rtx_code test_code;
2545 enum internal_test test = ITEST_MAX;
2550 case EQ: test = ITEST_EQ; break;
2551 case NE: test = ITEST_NE; break;
2552 case GT: test = ITEST_GT; break;
2553 case GE: test = ITEST_GE; break;
2554 case LT: test = ITEST_LT; break;
2555 case LE: test = ITEST_LE; break;
2556 case GTU: test = ITEST_GTU; break;
2557 case GEU: test = ITEST_GEU; break;
2558 case LTU: test = ITEST_LTU; break;
2559 case LEU: test = ITEST_LEU; break;
2566 /* Generate the code to compare two integer values. The return value is:
2567 (reg:SI xx) The pseudo register the comparison is in
2568 (rtx)0 No register, generate a simple branch.
2570 ??? This is called with result nonzero by the Scond patterns in
2571 mips.md. These patterns are called with a target in the mode of
2572 the Scond instruction pattern. Since this must be a constant, we
2573 must use SImode. This means that if RESULT is non-zero, it will
2574 always be an SImode register, even if TARGET_64BIT is true. We
2575 cope with this by calling convert_move rather than emit_move_insn.
2576 This will sometimes lead to an unnecessary extension of the result;
2588 gen_int_relational (test_code, result, cmp0, cmp1, p_invert)
2589 enum rtx_code test_code; /* relational test (EQ, etc) */
2590 rtx result; /* result to store comp. or 0 if branch */
2591 rtx cmp0; /* first operand to compare */
2592 rtx cmp1; /* second operand to compare */
2593 int *p_invert; /* NULL or ptr to hold whether branch needs */
2594 /* to reverse its test */
2597 enum rtx_code test_code; /* code to use in instruction (LT vs. LTU) */
2598 int const_low; /* low bound of constant we can accept */
2599 int const_high; /* high bound of constant we can accept */
2600 int const_add; /* constant to add (convert LE -> LT) */
2601 int reverse_regs; /* reverse registers in test */
2602 int invert_const; /* != 0 if invert value if cmp1 is constant */
2603 int invert_reg; /* != 0 if invert value if cmp1 is register */
2604 int unsignedp; /* != 0 for unsigned comparisons. */
2607 static struct cmp_info info[ (int)ITEST_MAX ] = {
2609 { XOR, 0, 65535, 0, 0, 0, 0, 0 }, /* EQ */
2610 { XOR, 0, 65535, 0, 0, 1, 1, 0 }, /* NE */
2611 { LT, -32769, 32766, 1, 1, 1, 0, 0 }, /* GT */
2612 { LT, -32768, 32767, 0, 0, 1, 1, 0 }, /* GE */
2613 { LT, -32768, 32767, 0, 0, 0, 0, 0 }, /* LT */
2614 { LT, -32769, 32766, 1, 1, 0, 1, 0 }, /* LE */
2615 { LTU, -32769, 32766, 1, 1, 1, 0, 1 }, /* GTU */
2616 { LTU, -32768, 32767, 0, 0, 1, 1, 1 }, /* GEU */
2617 { LTU, -32768, 32767, 0, 0, 0, 0, 1 }, /* LTU */
2618 { LTU, -32769, 32766, 1, 1, 0, 1, 1 }, /* LEU */
2621 enum internal_test test;
2622 enum machine_mode mode;
2623 struct cmp_info *p_info;
2630 test = map_test_to_internal_test (test_code);
2631 if (test == ITEST_MAX)
2634 p_info = &info[ (int)test ];
2635 eqne_p = (p_info->test_code == XOR);
2637 mode = GET_MODE (cmp0);
2638 if (mode == VOIDmode)
2639 mode = GET_MODE (cmp1);
2641 /* Eliminate simple branches */
2642 branch_p = (result == (rtx)0);
2645 if (GET_CODE (cmp0) == REG || GET_CODE (cmp0) == SUBREG)
2647 /* Comparisons against zero are simple branches */
2648 if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0
2649 && (! TARGET_MIPS16 || eqne_p))
2652 /* Test for beq/bne. */
2653 if (eqne_p && ! TARGET_MIPS16)
2657 /* allocate a pseudo to calculate the value in. */
2658 result = gen_reg_rtx (mode);
2661 /* Make sure we can handle any constants given to us. */
2662 if (GET_CODE (cmp0) == CONST_INT)
2663 cmp0 = force_reg (mode, cmp0);
2665 if (GET_CODE (cmp1) == CONST_INT)
2667 HOST_WIDE_INT value = INTVAL (cmp1);
2668 if (value < p_info->const_low
2669 || value > p_info->const_high
2670 /* ??? Why? And why wasn't the similar code below modified too? */
2672 && HOST_BITS_PER_WIDE_INT < 64
2673 && p_info->const_add != 0
2674 && ((p_info->unsignedp
2675 ? ((unsigned HOST_WIDE_INT) (value + p_info->const_add)
2677 : (value + p_info->const_add) > INTVAL (cmp1))
2678 != (p_info->const_add > 0))))
2679 cmp1 = force_reg (mode, cmp1);
2682 /* See if we need to invert the result. */
2683 invert = (GET_CODE (cmp1) == CONST_INT)
2684 ? p_info->invert_const
2685 : p_info->invert_reg;
2687 if (p_invert != (int *)0)
2693 /* Comparison to constants, may involve adding 1 to change a LT into LE.
2694 Comparison between two registers, may involve switching operands. */
2695 if (GET_CODE (cmp1) == CONST_INT)
2697 if (p_info->const_add != 0)
2699 HOST_WIDE_INT new = INTVAL (cmp1) + p_info->const_add;
2700 /* If modification of cmp1 caused overflow,
2701 we would get the wrong answer if we follow the usual path;
2702 thus, x > 0xffffffffU would turn into x > 0U. */
2703 if ((p_info->unsignedp
2704 ? (unsigned HOST_WIDE_INT) new > INTVAL (cmp1)
2705 : new > INTVAL (cmp1))
2706 != (p_info->const_add > 0))
2708 /* This test is always true, but if INVERT is true then
2709 the result of the test needs to be inverted so 0 should
2710 be returned instead. */
2711 emit_move_insn (result, invert ? const0_rtx : const_true_rtx);
2715 cmp1 = GEN_INT (new);
2718 else if (p_info->reverse_regs)
2725 if (test == ITEST_NE && GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) == 0)
2729 reg = (invert || eqne_p) ? gen_reg_rtx (mode) : result;
2730 convert_move (reg, gen_rtx (p_info->test_code, mode, cmp0, cmp1), 0);
2733 if (test == ITEST_NE)
2735 if (! TARGET_MIPS16)
2737 convert_move (result, gen_rtx (GTU, mode, reg, const0_rtx), 0);
2742 reg2 = invert ? gen_reg_rtx (mode) : result;
2743 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2748 else if (test == ITEST_EQ)
2750 reg2 = (invert) ? gen_reg_rtx (mode) : result;
2751 convert_move (reg2, gen_rtx (LTU, mode, reg, const1_rtx), 0);
2759 if (! TARGET_MIPS16)
2763 /* The value is in $24. Copy it to another register, so
2764 that reload doesn't think it needs to store the $24 and
2765 the input to the XOR in the same location. */
2766 reg2 = gen_reg_rtx (mode);
2767 emit_move_insn (reg2, reg);
2769 one = force_reg (mode, const1_rtx);
2771 convert_move (result, gen_rtx (XOR, mode, reg, one), 0);
2778 /* Emit the common code for doing conditional branches.
2779 operand[0] is the label to jump to.
2780 The comparison operands are saved away by cmp{si,di,sf,df}. */
2783 gen_conditional_branch (operands, test_code)
2785 enum rtx_code test_code;
2787 enum cmp_type type = branch_type;
2788 rtx cmp0 = branch_cmp[0];
2789 rtx cmp1 = branch_cmp[1];
2790 enum machine_mode mode;
2798 abort_with_insn (gen_rtx (test_code, VOIDmode, cmp0, cmp1), "bad test");
2802 mode = type == CMP_SI ? SImode : DImode;
2804 reg = gen_int_relational (test_code, NULL_RTX, cmp0, cmp1, &invert);
2811 else if (GET_CODE (cmp1) == CONST_INT && INTVAL (cmp1) != 0)
2813 /* We don't want to build a comparison against a non-zero
2815 cmp1 = force_reg (mode, cmp1);
2822 reg = gen_rtx (REG, CCmode, FPSW_REGNUM);
2824 reg = gen_reg_rtx (CCmode);
2826 /* For cmp0 != cmp1, build cmp0 == cmp1, and test for result ==
2827 0 in the instruction built below. The MIPS FPU handles
2828 inequality testing by testing for equality and looking for a
2830 emit_insn (gen_rtx (SET, VOIDmode,
2832 gen_rtx (test_code == NE ? EQ : test_code,
2833 CCmode, cmp0, cmp1)));
2835 test_code = test_code == NE ? EQ : NE;
2843 /* Generate the branch. */
2845 label1 = gen_rtx (LABEL_REF, VOIDmode, operands[0]);
2854 emit_jump_insn (gen_rtx (SET, VOIDmode,
2856 gen_rtx (IF_THEN_ELSE, VOIDmode,
2857 gen_rtx (test_code, mode, cmp0, cmp1),
2862 /* Emit the common code for conditional moves. OPERANDS is the array
2863 of operands passed to the conditional move defined_expand. */
2866 gen_conditional_move (operands)
2869 rtx op0 = branch_cmp[0];
2870 rtx op1 = branch_cmp[1];
2871 enum machine_mode mode = GET_MODE (branch_cmp[0]);
2872 enum rtx_code cmp_code = GET_CODE (operands[1]);
2873 enum rtx_code move_code = NE;
2874 enum machine_mode op_mode = GET_MODE (operands[0]);
2875 enum machine_mode cmp_mode;
2878 if (GET_MODE_CLASS (mode) != MODE_FLOAT)
2897 op0 = force_reg (mode, branch_cmp[1]);
2898 op1 = branch_cmp[0];
2902 op0 = force_reg (mode, branch_cmp[1]);
2903 op1 = branch_cmp[0];
2914 op0 = force_reg (mode, branch_cmp[1]);
2915 op1 = branch_cmp[0];
2919 op0 = force_reg (mode, branch_cmp[1]);
2920 op1 = branch_cmp[0];
2936 if (mode == SImode || mode == DImode)
2938 else if (mode == SFmode || mode == DFmode)
2943 cmp_reg = gen_reg_rtx (cmp_mode);
2944 emit_insn (gen_rtx (SET, cmp_mode,
2946 gen_rtx (cmp_code, cmp_mode, op0, op1)));
2947 emit_insn (gen_rtx (SET, op_mode,
2949 gen_rtx (IF_THEN_ELSE, op_mode,
2950 gen_rtx (move_code, VOIDmode,
2952 CONST0_RTX (SImode)),
2957 /* Write a loop to move a constant number of bytes. Generate load/stores as follows:
2963 temp<last> = src[MAX_MOVE_REGS-1];
2967 dest[MAX_MOVE_REGS-1] = temp<last>;
2968 src += MAX_MOVE_REGS;
2969 dest += MAX_MOVE_REGS;
2970 } while (src != final);
2972 This way, no NOP's are needed, and only MAX_MOVE_REGS+3 temp
2973 registers are needed.
2975 Aligned moves move MAX_MOVE_REGS*4 bytes every (2*MAX_MOVE_REGS)+3
2976 cycles, unaligned moves move MAX_MOVE_REGS*4 bytes every
2977 (4*MAX_MOVE_REGS)+3 cycles, assuming no cache misses. */
2979 #define MAX_MOVE_REGS 4
2980 #define MAX_MOVE_BYTES (MAX_MOVE_REGS * UNITS_PER_WORD)
2983 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src)
2984 rtx dest_reg; /* register holding destination address */
2985 rtx src_reg; /* register holding source address */
2986 int bytes; /* # bytes to move */
2987 int align; /* alignment */
2988 rtx orig_dest; /* original dest for change_address */
2989 rtx orig_src; /* original source for making a reg note */
2991 rtx dest_mem = change_address (orig_dest, BLKmode, dest_reg);
2992 rtx src_mem = change_address (orig_src, BLKmode, src_reg);
2993 rtx align_rtx = GEN_INT (align);
2999 if (bytes < 2*MAX_MOVE_BYTES)
3002 leftover = bytes % MAX_MOVE_BYTES;
3005 label = gen_label_rtx ();
3006 final_src = gen_reg_rtx (Pmode);
3007 bytes_rtx = GEN_INT (bytes);
3011 if (Pmode == DImode)
3013 emit_insn (gen_movdi (final_src, bytes_rtx));
3014 emit_insn (gen_adddi3 (final_src, final_src, src_reg));
3018 emit_insn (gen_movsi (final_src, bytes_rtx));
3019 emit_insn (gen_addsi3 (final_src, final_src, src_reg));
3024 if (Pmode == DImode)
3025 emit_insn (gen_adddi3 (final_src, src_reg, bytes_rtx));
3027 emit_insn (gen_addsi3 (final_src, src_reg, bytes_rtx));
3032 bytes_rtx = GEN_INT (MAX_MOVE_BYTES);
3033 emit_insn (gen_movstrsi_internal (dest_mem, src_mem, bytes_rtx, align_rtx));
3034 if (Pmode == DImode)
3036 emit_insn (gen_adddi3 (src_reg, src_reg, bytes_rtx));
3037 emit_insn (gen_adddi3 (dest_reg, dest_reg, bytes_rtx));
3038 emit_insn (gen_cmpdi (src_reg, final_src));
3042 emit_insn (gen_addsi3 (src_reg, src_reg, bytes_rtx));
3043 emit_insn (gen_addsi3 (dest_reg, dest_reg, bytes_rtx));
3044 emit_insn (gen_cmpsi (src_reg, final_src));
3046 emit_jump_insn (gen_bne (label));
3049 emit_insn (gen_movstrsi_internal (dest_mem, src_mem,
3054 /* Use a library function to move some bytes. */
3057 block_move_call (dest_reg, src_reg, bytes_rtx)
3062 /* We want to pass the size as Pmode, which will normally be SImode
3063 but will be DImode if we are using 64 bit longs and pointers. */
3064 if (GET_MODE (bytes_rtx) != VOIDmode
3065 && GET_MODE (bytes_rtx) != Pmode)
3066 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, TRUE);
3068 #ifdef TARGET_MEM_FUNCTIONS
3069 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "memcpy"), 0,
3073 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx,
3074 TREE_UNSIGNED (sizetype)),
3075 TYPE_MODE (sizetype));
3077 emit_library_call (gen_rtx (SYMBOL_REF, Pmode, "bcopy"), 0,
3081 convert_to_mode (TYPE_MODE (integer_type_node),
3083 TREE_UNSIGNED (integer_type_node)),
3084 TYPE_MODE (integer_type_node));
3089 /* Expand string/block move operations.
3091 operands[0] is the pointer to the destination.
3092 operands[1] is the pointer to the source.
3093 operands[2] is the number of bytes to move.
3094 operands[3] is the alignment. */
3097 expand_block_move (operands)
3100 rtx bytes_rtx = operands[2];
3101 rtx align_rtx = operands[3];
3102 int constp = (GET_CODE (bytes_rtx) == CONST_INT);
3103 int bytes = (constp ? INTVAL (bytes_rtx) : 0);
3104 int align = INTVAL (align_rtx);
3105 rtx orig_src = operands[1];
3106 rtx orig_dest = operands[0];
3110 if (constp && bytes <= 0)
3113 if (align > UNITS_PER_WORD)
3114 align = UNITS_PER_WORD;
3116 /* Move the address into scratch registers. */
3117 dest_reg = copy_addr_to_reg (XEXP (orig_dest, 0));
3118 src_reg = copy_addr_to_reg (XEXP (orig_src, 0));
3121 block_move_call (dest_reg, src_reg, bytes_rtx);
3123 else if (constp && bytes <= 2*MAX_MOVE_BYTES)
3124 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3126 change_address (orig_src, BLKmode,
3128 bytes_rtx, align_rtx));
3130 else if (constp && align >= UNITS_PER_WORD && optimize)
3131 block_move_loop (dest_reg, src_reg, bytes, align, orig_dest, orig_src);
3133 else if (constp && optimize)
3135 /* If the alignment is not word aligned, generate a test at
3136 runtime, to see whether things wound up aligned, and we
3137 can use the faster lw/sw instead ulw/usw. */
3139 rtx temp = gen_reg_rtx (Pmode);
3140 rtx aligned_label = gen_label_rtx ();
3141 rtx join_label = gen_label_rtx ();
3142 int leftover = bytes % MAX_MOVE_BYTES;
3146 if (Pmode == DImode)
3148 emit_insn (gen_iordi3 (temp, src_reg, dest_reg));
3149 emit_insn (gen_anddi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
3150 emit_insn (gen_cmpdi (temp, const0_rtx));
3154 emit_insn (gen_iorsi3 (temp, src_reg, dest_reg));
3155 emit_insn (gen_andsi3 (temp, temp, GEN_INT (UNITS_PER_WORD-1)));
3156 emit_insn (gen_cmpsi (temp, const0_rtx));
3158 emit_jump_insn (gen_beq (aligned_label));
3160 /* Unaligned loop. */
3161 block_move_loop (dest_reg, src_reg, bytes, 1, orig_dest, orig_src);
3162 emit_jump_insn (gen_jump (join_label));
3166 emit_label (aligned_label);
3167 block_move_loop (dest_reg, src_reg, bytes, UNITS_PER_WORD, orig_dest,
3169 emit_label (join_label);
3171 /* Bytes at the end of the loop. */
3173 emit_insn (gen_movstrsi_internal (change_address (orig_dest, BLKmode,
3175 change_address (orig_src, BLKmode,
3182 block_move_call (dest_reg, src_reg, bytes_rtx);
3186 /* Emit load/stores for a small constant block_move.
3188 operands[0] is the memory address of the destination.
3189 operands[1] is the memory address of the source.
3190 operands[2] is the number of bytes to move.
3191 operands[3] is the alignment.
3192 operands[4] is a temp register.
3193 operands[5] is a temp register.
3195 operands[3+num_regs] is the last temp register.
3197 The block move type can be one of the following:
3198 BLOCK_MOVE_NORMAL Do all of the block move.
3199 BLOCK_MOVE_NOT_LAST Do all but the last store.
3200 BLOCK_MOVE_LAST Do just the last store. */
3203 output_block_move (insn, operands, num_regs, move_type)
3207 enum block_move_type move_type;
3209 rtx dest_reg = XEXP (operands[0], 0);
3210 rtx src_reg = XEXP (operands[1], 0);
3211 int bytes = INTVAL (operands[2]);
3212 int align = INTVAL (operands[3]);
3215 int use_lwl_lwr = FALSE;
3216 int last_operand = num_regs+4;
3222 char *load; /* load insn without nop */
3223 char *load_nop; /* load insn with trailing nop */
3224 char *store; /* store insn */
3225 char *final; /* if last_store used: NULL or swr */
3226 char *last_store; /* last store instruction */
3227 int offset; /* current offset */
3228 enum machine_mode mode; /* mode to use on (MEM) */
3231 /* Detect a bug in GCC, where it can give us a register
3232 the same as one of the addressing registers and reduce
3233 the number of registers available. */
3235 i < last_operand && safe_regs < (sizeof(xoperands) / sizeof(xoperands[0]));
3238 if (!reg_mentioned_p (operands[i], operands[0])
3239 && !reg_mentioned_p (operands[i], operands[1]))
3241 xoperands[safe_regs++] = operands[i];
3244 if (safe_regs < last_operand)
3246 xoperands[0] = operands[0];
3247 xoperands[1] = operands[1];
3248 xoperands[2] = operands[2];
3249 xoperands[3] = operands[3];
3250 return output_block_move (insn, xoperands, safe_regs-4, move_type);
3253 /* If we are given global or static addresses, and we would be
3254 emitting a few instructions, try to save time by using a
3255 temporary register for the pointer. */
3256 /* ??? The SGI Irix6 assembler fails when a SYMBOL_REF is used in
3257 an ldl/ldr instruction pair. We play it safe, and always move
3258 constant addresses into registers when generating N32/N64 code, just
3259 in case we might emit an unaligned load instruction. */
3260 if (num_regs > 2 && (bytes > 2*align || move_type != BLOCK_MOVE_NORMAL
3261 || mips_abi == ABI_N32 || mips_abi == ABI_64))
3263 if (CONSTANT_P (src_reg))
3266 mips_count_memory_refs (operands[1], 1);
3268 src_reg = operands[ 3 + num_regs-- ];
3269 if (move_type != BLOCK_MOVE_LAST)
3271 xoperands[1] = operands[1];
3272 xoperands[0] = src_reg;
3273 if (Pmode == DImode)
3274 output_asm_insn ("dla\t%0,%1", xoperands);
3276 output_asm_insn ("la\t%0,%1", xoperands);
3280 if (CONSTANT_P (dest_reg))
3283 mips_count_memory_refs (operands[0], 1);
3285 dest_reg = operands[ 3 + num_regs-- ];
3286 if (move_type != BLOCK_MOVE_LAST)
3288 xoperands[1] = operands[0];
3289 xoperands[0] = dest_reg;
3290 if (Pmode == DImode)
3291 output_asm_insn ("dla\t%0,%1", xoperands);
3293 output_asm_insn ("la\t%0,%1", xoperands);
3298 /* ??? We really shouldn't get any LO_SUM addresses here, because they
3299 are not offsettable, however, offsettable_address_p says they are
3300 offsettable. I think this is a bug in offsettable_address_p.
3301 For expediency, we fix this by just loading the address into a register
3302 if we happen to get one. */
3304 if (GET_CODE (src_reg) == LO_SUM)
3306 src_reg = operands[ 3 + num_regs-- ];
3307 if (move_type != BLOCK_MOVE_LAST)
3309 xoperands[2] = XEXP (XEXP (operands[1], 0), 1);
3310 xoperands[1] = XEXP (XEXP (operands[1], 0), 0);
3311 xoperands[0] = src_reg;
3312 if (Pmode == DImode)
3313 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3315 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3319 if (GET_CODE (dest_reg) == LO_SUM)
3321 dest_reg = operands[ 3 + num_regs-- ];
3322 if (move_type != BLOCK_MOVE_LAST)
3324 xoperands[2] = XEXP (XEXP (operands[0], 0), 1);
3325 xoperands[1] = XEXP (XEXP (operands[0], 0), 0);
3326 xoperands[0] = dest_reg;
3327 if (Pmode == DImode)
3328 output_asm_insn ("daddiu\t%0,%1,%%lo(%2)", xoperands);
3330 output_asm_insn ("addiu\t%0,%1,%%lo(%2)", xoperands);
3334 if (num_regs > (sizeof (load_store) / sizeof (load_store[0])))
3335 num_regs = (sizeof (load_store) / sizeof (load_store[0]));
3337 else if (num_regs < 1)
3338 abort_with_insn (insn, "Cannot do block move, not enough scratch registers");
3342 load_store[num].offset = offset;
3344 if (TARGET_64BIT && bytes >= 8 && align >= 8)
3346 load_store[num].load = "ld\t%0,%1";
3347 load_store[num].load_nop = "ld\t%0,%1%#";
3348 load_store[num].store = "sd\t%0,%1";
3349 load_store[num].last_store = "sd\t%0,%1";
3350 load_store[num].final = (char *)0;
3351 load_store[num].mode = DImode;
3356 /* ??? Fails because of a MIPS assembler bug? */
3357 else if (TARGET_64BIT && bytes >= 8 && ! TARGET_MIPS16)
3359 if (BYTES_BIG_ENDIAN)
3361 load_store[num].load = "ldl\t%0,%1\n\tldr\t%0,%2";
3362 load_store[num].load_nop = "ldl\t%0,%1\n\tldr\t%0,%2%#";
3363 load_store[num].store = "sdl\t%0,%1\n\tsdr\t%0,%2";
3364 load_store[num].last_store = "sdr\t%0,%2";
3365 load_store[num].final = "sdl\t%0,%1";
3369 load_store[num].load = "ldl\t%0,%2\n\tldr\t%0,%1";
3370 load_store[num].load_nop = "ldl\t%0,%2\n\tldr\t%0,%1%#";
3371 load_store[num].store = "sdl\t%0,%2\n\tsdr\t%0,%1";
3372 load_store[num].last_store = "sdr\t%0,%1";
3373 load_store[num].final = "sdl\t%0,%2";
3375 load_store[num].mode = DImode;
3381 else if (bytes >= 4 && align >= 4)
3383 load_store[num].load = "lw\t%0,%1";
3384 load_store[num].load_nop = "lw\t%0,%1%#";
3385 load_store[num].store = "sw\t%0,%1";
3386 load_store[num].last_store = "sw\t%0,%1";
3387 load_store[num].final = (char *)0;
3388 load_store[num].mode = SImode;
3393 else if (bytes >= 4 && ! TARGET_MIPS16)
3395 if (BYTES_BIG_ENDIAN)
3397 load_store[num].load = "lwl\t%0,%1\n\tlwr\t%0,%2";
3398 load_store[num].load_nop = "lwl\t%0,%1\n\tlwr\t%0,%2%#";
3399 load_store[num].store = "swl\t%0,%1\n\tswr\t%0,%2";
3400 load_store[num].last_store = "swr\t%0,%2";
3401 load_store[num].final = "swl\t%0,%1";
3405 load_store[num].load = "lwl\t%0,%2\n\tlwr\t%0,%1";
3406 load_store[num].load_nop = "lwl\t%0,%2\n\tlwr\t%0,%1%#";
3407 load_store[num].store = "swl\t%0,%2\n\tswr\t%0,%1";
3408 load_store[num].last_store = "swr\t%0,%1";
3409 load_store[num].final = "swl\t%0,%2";
3411 load_store[num].mode = SImode;
3417 else if (bytes >= 2 && align >= 2)
3419 load_store[num].load = "lh\t%0,%1";
3420 load_store[num].load_nop = "lh\t%0,%1%#";
3421 load_store[num].store = "sh\t%0,%1";
3422 load_store[num].last_store = "sh\t%0,%1";
3423 load_store[num].final = (char *)0;
3424 load_store[num].mode = HImode;
3431 load_store[num].load = "lb\t%0,%1";
3432 load_store[num].load_nop = "lb\t%0,%1%#";
3433 load_store[num].store = "sb\t%0,%1";
3434 load_store[num].last_store = "sb\t%0,%1";
3435 load_store[num].final = (char *)0;
3436 load_store[num].mode = QImode;
3441 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3443 dslots_load_total++;
3444 dslots_load_filled++;
3446 if (CONSTANT_P (src_reg))
3447 mips_count_memory_refs (src_reg, 1);
3449 if (CONSTANT_P (dest_reg))
3450 mips_count_memory_refs (dest_reg, 1);
3453 /* Emit load/stores now if we have run out of registers or are
3454 at the end of the move. */
3456 if (++num == num_regs || bytes == 0)
3458 /* If only load/store, we need a NOP after the load. */
3461 load_store[0].load = load_store[0].load_nop;
3462 if (TARGET_STATS && move_type != BLOCK_MOVE_LAST)
3463 dslots_load_filled--;
3466 if (move_type != BLOCK_MOVE_LAST)
3468 for (i = 0; i < num; i++)
3475 if (GET_MODE (operands[i+4]) != load_store[i].mode)
3476 operands[i+4] = gen_rtx (REG, load_store[i].mode, REGNO (operands[i+4]));
3478 offset = load_store[i].offset;
3479 xoperands[0] = operands[i+4];
3480 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
3481 plus_constant (src_reg, offset));
3486 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3487 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
3488 plus_constant (src_reg,
3493 output_asm_insn (load_store[i].load, xoperands);
3497 for (i = 0; i < num; i++)
3499 int last_p = (i == num-1 && bytes == 0);
3500 int offset = load_store[i].offset;
3502 xoperands[0] = operands[i+4];
3503 xoperands[1] = gen_rtx (MEM, load_store[i].mode,
3504 plus_constant (dest_reg, offset));
3510 extra_offset = GET_MODE_SIZE (load_store[i].mode) - 1;
3511 xoperands[2] = gen_rtx (MEM, load_store[i].mode,
3512 plus_constant (dest_reg,
3517 if (move_type == BLOCK_MOVE_NORMAL)
3518 output_asm_insn (load_store[i].store, xoperands);
3520 else if (move_type == BLOCK_MOVE_NOT_LAST)
3523 output_asm_insn (load_store[i].store, xoperands);
3525 else if (load_store[i].final != (char *)0)
3526 output_asm_insn (load_store[i].final, xoperands);
3530 output_asm_insn (load_store[i].last_store, xoperands);
3533 num = 0; /* reset load_store */
3534 use_lwl_lwr = FALSE;
3542 /* Argument support functions. */
3544 /* Initialize CUMULATIVE_ARGS for a function. */
3547 init_cumulative_args (cum, fntype, libname)
3548 CUMULATIVE_ARGS *cum; /* argument info to initialize */
3549 tree fntype; /* tree ptr for function decl */
3550 rtx libname; /* SYMBOL_REF of library name or 0 */
3552 static CUMULATIVE_ARGS zero_cum;
3553 tree param, next_param;
3555 if (TARGET_DEBUG_E_MODE)
3557 fprintf (stderr, "\ninit_cumulative_args, fntype = 0x%.8lx", (long)fntype);
3559 fputc ('\n', stderr);
3563 tree ret_type = TREE_TYPE (fntype);
3564 fprintf (stderr, ", fntype code = %s, ret code = %s\n",
3565 tree_code_name[ (int)TREE_CODE (fntype) ],
3566 tree_code_name[ (int)TREE_CODE (ret_type) ]);
3572 /* Determine if this function has variable arguments. This is
3573 indicated by the last argument being 'void_type_mode' if there
3574 are no variable arguments. The standard MIPS calling sequence
3575 passes all arguments in the general purpose registers in this
3578 for (param = (fntype) ? TYPE_ARG_TYPES (fntype) : 0;
3582 next_param = TREE_CHAIN (param);
3583 if (next_param == (tree)0 && TREE_VALUE (param) != void_type_node)
3584 cum->gp_reg_found = 1;
3588 /* Advance the argument to the next argument position. */
3591 function_arg_advance (cum, mode, type, named)
3592 CUMULATIVE_ARGS *cum; /* current arg information */
3593 enum machine_mode mode; /* current arg mode */
3594 tree type; /* type of the argument or 0 if lib support */
3595 int named; /* whether or not the argument was named */
3597 if (TARGET_DEBUG_E_MODE)
3599 "function_adv( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d )\n\n",
3600 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
3610 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3611 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3613 cum->gp_reg_found = 1;
3614 cum->arg_words += ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1)
3619 cum->gp_reg_found = 1;
3620 cum->arg_words += ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3625 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3626 cum->fp_arg_words++;
3629 if (! cum->gp_reg_found && cum->arg_number <= 2)
3630 cum->fp_code += 1 << ((cum->arg_number - 1) * 2);
3634 if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT && ! TARGET_SINGLE_FLOAT)
3635 cum->fp_arg_words += (TARGET_64BIT ? 1 : 2);
3637 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3638 if (! cum->gp_reg_found && ! TARGET_SINGLE_FLOAT && cum->arg_number <= 2)
3639 cum->fp_code += 2 << ((cum->arg_number - 1) * 2);
3643 cum->gp_reg_found = 1;
3644 cum->arg_words += (TARGET_64BIT ? 1 : 2);
3650 cum->gp_reg_found = 1;
3656 /* Return an RTL expression containing the register for the given mode,
3657 or 0 if the argument is to be passed on the stack. */
3660 function_arg (cum, mode, type, named)
3661 CUMULATIVE_ARGS *cum; /* current arg information */
3662 enum machine_mode mode; /* current arg mode */
3663 tree type; /* type of the argument or 0 if lib support */
3664 int named; /* != 0 for normal args, == 0 for ... args */
3669 int *arg_words = &cum->arg_words;
3670 int struct_p = ((type != (tree)0)
3671 && (TREE_CODE (type) == RECORD_TYPE
3672 || TREE_CODE (type) == UNION_TYPE));
3674 if (TARGET_DEBUG_E_MODE)
3676 "function_arg( {gp reg found = %d, arg # = %2d, words = %2d}, %4s, 0x%.8x, %d ) = ",
3677 cum->gp_reg_found, cum->arg_number, cum->arg_words, GET_MODE_NAME (mode),
3680 cum->last_arg_fp = 0;
3684 if (mips_abi == ABI_32)
3686 if (cum->gp_reg_found || cum->arg_number >= 2 || TARGET_SOFT_FLOAT)
3687 regbase = GP_ARG_FIRST;
3690 regbase = FP_ARG_FIRST;
3691 /* If the first arg was a float in a floating point register,
3692 then set bias to align this float arg properly. */
3693 if (cum->arg_words == 1)
3697 else if (mips_abi == ABI_EABI && ! TARGET_SOFT_FLOAT)
3700 cum->fp_arg_words += cum->fp_arg_words & 1;
3701 cum->last_arg_fp = 1;
3702 arg_words = &cum->fp_arg_words;
3703 regbase = FP_ARG_FIRST;
3706 regbase = (TARGET_SOFT_FLOAT || ! named ? GP_ARG_FIRST : FP_ARG_FIRST);
3712 if (mips_abi == ABI_EABI
3713 && ! TARGET_SOFT_FLOAT
3714 && ! TARGET_SINGLE_FLOAT)
3715 cum->fp_arg_words += cum->fp_arg_words & 1;
3717 cum->arg_words += cum->arg_words & 1;
3719 if (mips_abi == ABI_32)
3720 regbase = ((cum->gp_reg_found
3721 || TARGET_SOFT_FLOAT
3722 || TARGET_SINGLE_FLOAT
3723 || cum->arg_number >= 2)
3726 else if (mips_abi == ABI_EABI
3727 && ! TARGET_SOFT_FLOAT
3728 && ! TARGET_SINGLE_FLOAT)
3730 cum->last_arg_fp = 1;
3731 arg_words = &cum->fp_arg_words;
3732 regbase = FP_ARG_FIRST;
3735 regbase = (TARGET_SOFT_FLOAT || TARGET_SINGLE_FLOAT || ! named
3736 ? GP_ARG_FIRST : FP_ARG_FIRST);
3740 if (GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3741 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3744 /* Drops through. */
3746 if (type != (tree)0 && TYPE_ALIGN (type) > BITS_PER_WORD
3747 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3748 cum->arg_words += (cum->arg_words & 1);
3749 regbase = GP_ARG_FIRST;
3756 regbase = GP_ARG_FIRST;
3761 cum->arg_words += (cum->arg_words & 1);
3762 regbase = GP_ARG_FIRST;
3765 if (*arg_words >= MAX_ARGS_IN_REGISTERS)
3767 if (TARGET_DEBUG_E_MODE)
3768 fprintf (stderr, "<stack>%s\n", struct_p ? ", [struct]" : "");
3777 if (! type || TREE_CODE (type) != RECORD_TYPE || mips_abi == ABI_32
3778 || mips_abi == ABI_EABI || ! named)
3779 ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
3782 /* The Irix 6 n32/n64 ABIs say that if any 64 bit chunk of the
3783 structure contains a double in its entirety, then that 64 bit
3784 chunk is passed in a floating point register. */
3787 /* First check to see if there is any such field. */
3788 for (field = TYPE_FIELDS (type); field; field = TREE_CHAIN (field))
3789 if (TREE_CODE (field) == FIELD_DECL
3790 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3791 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD
3792 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3793 % BITS_PER_WORD == 0))
3796 /* If the whole struct fits a DFmode register,
3797 we don't need the PARALLEL. */
3798 if (! field || mode == DFmode)
3799 ret = gen_rtx (REG, mode, regbase + *arg_words + bias);
3802 /* Now handle the special case by returning a PARALLEL
3803 indicating where each 64 bit chunk goes. */
3809 /* ??? If this is a packed structure, then the last hunk won't
3812 chunks = TREE_INT_CST_LOW (TYPE_SIZE (type)) / BITS_PER_WORD;
3813 if (chunks + *arg_words + bias > MAX_ARGS_IN_REGISTERS)
3814 chunks = MAX_ARGS_IN_REGISTERS - *arg_words - bias;
3816 /* assign_parms checks the mode of ENTRY_PARM, so we must
3817 use the actual mode here. */
3818 ret = gen_rtx (PARALLEL, mode, rtvec_alloc (chunks));
3821 regno = regbase + *arg_words + bias;
3822 field = TYPE_FIELDS (type);
3823 for (i = 0; i < chunks; i++)
3827 for (; field; field = TREE_CHAIN (field))
3828 if (TREE_CODE (field) == FIELD_DECL
3829 && (TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field))
3834 && TREE_INT_CST_LOW (DECL_FIELD_BITPOS (field)) == bitpos
3835 && TREE_CODE (TREE_TYPE (field)) == REAL_TYPE
3836 && TYPE_PRECISION (TREE_TYPE (field)) == BITS_PER_WORD)
3837 reg = gen_rtx (REG, DFmode,
3838 regno + FP_ARG_FIRST - GP_ARG_FIRST);
3840 reg = gen_rtx (REG, word_mode, regno);
3842 XVECEXP (ret, 0, i) = gen_rtx (EXPR_LIST, VOIDmode, reg,
3843 GEN_INT (bitpos / BITS_PER_UNIT));
3851 if (TARGET_DEBUG_E_MODE)
3852 fprintf (stderr, "%s%s\n", reg_names[regbase + *arg_words + bias],
3853 struct_p ? ", [struct]" : "");
3855 /* The following is a hack in order to pass 1 byte structures
3856 the same way that the MIPS compiler does (namely by passing
3857 the structure in the high byte or half word of the register).
3858 This also makes varargs work. If we have such a structure,
3859 we save the adjustment RTL, and the call define expands will
3860 emit them. For the VOIDmode argument (argument after the
3861 last real argument), pass back a parallel vector holding each
3862 of the adjustments. */
3864 /* ??? function_arg can be called more than once for each argument.
3865 As a result, we compute more adjustments than we need here.
3866 See the CUMULATIVE_ARGS definition in mips.h. */
3868 /* ??? This scheme requires everything smaller than the word size to
3869 shifted to the left, but when TARGET_64BIT and ! TARGET_INT64,
3870 that would mean every int needs to be shifted left, which is very
3871 inefficient. Let's not carry this compatibility to the 64 bit
3872 calling convention for now. */
3874 if (struct_p && int_size_in_bytes (type) < UNITS_PER_WORD
3875 && ! TARGET_64BIT && mips_abi != ABI_EABI)
3877 rtx amount = GEN_INT (BITS_PER_WORD
3878 - int_size_in_bytes (type) * BITS_PER_UNIT);
3879 rtx reg = gen_rtx (REG, word_mode, regbase + *arg_words + bias);
3881 cum->adjust[ cum->num_adjusts++ ] = gen_ashldi3 (reg, reg, amount);
3883 cum->adjust[ cum->num_adjusts++ ] = gen_ashlsi3 (reg, reg, amount);
3887 /* We will be called with a mode of VOIDmode after the last argument
3888 has been seen. Whatever we return will be passed to the call
3889 insn. If we need any shifts for small structures, return them in
3890 a PARALLEL; in that case, stuff the mips16 fp_code in as the
3891 mode. Otherwise, if we have need a mips16 fp_code, return a REG
3892 with the code stored as the mode. */
3893 if (mode == VOIDmode)
3895 if (cum->num_adjusts > 0)
3896 ret = gen_rtx (PARALLEL, (enum machine_mode) cum->fp_code,
3897 gen_rtvec_v (cum->num_adjusts, cum->adjust));
3898 else if (TARGET_MIPS16 && cum->fp_code != 0)
3899 ret = gen_rtx (REG, (enum machine_mode) cum->fp_code, 0);
3907 function_arg_partial_nregs (cum, mode, type, named)
3908 CUMULATIVE_ARGS *cum; /* current arg information */
3909 enum machine_mode mode; /* current arg mode */
3910 tree type; /* type of the argument or 0 if lib support */
3911 int named; /* != 0 for normal args, == 0 for ... args */
3913 if ((mode == BLKmode
3914 || GET_MODE_CLASS (mode) != MODE_COMPLEX_INT
3915 || GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT)
3916 && cum->arg_words < MAX_ARGS_IN_REGISTERS
3917 && mips_abi != ABI_EABI)
3920 if (mode == BLKmode)
3921 words = ((int_size_in_bytes (type) + UNITS_PER_WORD - 1)
3924 words = (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD;
3926 if (words + cum->arg_words <= MAX_ARGS_IN_REGISTERS)
3927 return 0; /* structure fits in registers */
3929 if (TARGET_DEBUG_E_MODE)
3930 fprintf (stderr, "function_arg_partial_nregs = %d\n",
3931 MAX_ARGS_IN_REGISTERS - cum->arg_words);
3933 return MAX_ARGS_IN_REGISTERS - cum->arg_words;
3936 else if (mode == DImode && cum->arg_words == MAX_ARGS_IN_REGISTERS-1
3938 && mips_abi != ABI_EABI)
3940 if (TARGET_DEBUG_E_MODE)
3941 fprintf (stderr, "function_arg_partial_nregs = 1\n");
3949 /* Abort after printing out a specific insn. */
3952 abort_with_insn (insn, reason)
3961 /* Write a message to stderr (for use in macros expanded in files that do not
3962 include stdio.h). */
3968 fprintf (stderr, s, s1, s2);
3972 /* Set up the threshold for data to go into the small data area, instead
3973 of the normal data area, and detect any conflicts in the switches. */
3978 register int i, start;
3980 register enum machine_mode mode;
3982 mips_section_threshold = (g_switch_set) ? g_switch_value : MIPS_DEFAULT_GVALUE;
3984 if (mips_section_threshold <= 0)
3985 target_flags &= ~MASK_GPOPT;
3987 target_flags |= MASK_GPOPT;
3989 #ifndef MIPS_ISA_DEFAULT
3990 #define MIPS_ISA_DEFAULT 1
3993 /* If both single-float and soft-float are set, then clear the one that
3994 was set by TARGET_DEFAULT, leaving the one that was set by the
3995 user. We assume here that the specs prevent both being set by the
3997 #ifdef TARGET_DEFAULT
3998 if (TARGET_SINGLE_FLOAT && TARGET_SOFT_FLOAT)
3999 target_flags &= ~(TARGET_DEFAULT&(MASK_SOFT_FLOAT|MASK_SINGLE_FLOAT));
4002 /* Get the architectural level. */
4003 if (mips_isa_string == (char *)0)
4004 mips_isa = MIPS_ISA_DEFAULT;
4006 else if (isdigit (*mips_isa_string))
4008 mips_isa = atoi (mips_isa_string);
4011 /* -mno-mips16 overrides -mips16. */
4012 if (mips_no_mips16_string == NULL)
4014 target_flags |= MASK_MIPS16;
4018 mips_isa = MIPS_ISA_DEFAULT;
4022 mips_isa = MIPS_ISA_DEFAULT;
4025 else if (mips_isa < 1 || mips_isa > 4)
4027 error ("-mips%d not supported", mips_isa);
4034 error ("bad value (%s) for -mips switch", mips_isa_string);
4038 #ifdef MIPS_ABI_DEFAULT
4039 /* Get the ABI to use. Currently this code is only used for Irix 6. */
4040 if (mips_abi_string == (char *) 0)
4041 mips_abi = MIPS_ABI_DEFAULT;
4042 else if (! strcmp (mips_abi_string, "32")
4043 || ! strcmp (mips_abi_string, "o32"))
4045 else if (! strcmp (mips_abi_string, "n32"))
4047 else if (! strcmp (mips_abi_string, "64")
4048 || ! strcmp (mips_abi_string, "n64"))
4050 else if (! strcmp (mips_abi_string, "eabi"))
4051 mips_abi = ABI_EABI;
4053 error ("bad value (%s) for -mabi= switch", mips_abi_string);
4055 /* A specified ISA defaults the ABI if it was not specified. */
4056 if (mips_abi_string == 0 && mips_isa_string && mips_abi != ABI_EABI)
4063 /* A specified ABI defaults the ISA if it was not specified. */
4064 else if (mips_isa_string == 0 && mips_abi_string && mips_abi != ABI_EABI)
4066 if (mips_abi == ABI_32)
4068 else if (mips_abi == ABI_N32)
4073 /* If both ABI and ISA were specified, check for conflicts. */
4074 else if (mips_isa_string && mips_abi_string)
4076 if ((mips_isa <= 2 && (mips_abi == ABI_N32 || mips_abi == ABI_64))
4077 || (mips_isa >= 3 && mips_abi == ABI_32))
4078 error ("-mabi=%s does not support -mips%d", mips_abi_string, mips_isa);
4081 /* Override TARGET_DEFAULT if necessary. */
4082 if (mips_abi == ABI_32)
4083 target_flags &= ~ (MASK_FLOAT64|MASK_64BIT);
4085 /* In the EABI in 64 bit mode, longs and pointers are 64 bits. Likewise
4086 for the SGI Irix6 N64 ABI. */
4087 if ((mips_abi == ABI_EABI && TARGET_64BIT)
4088 || mips_abi == ABI_64)
4089 target_flags |= MASK_LONG64;
4091 /* ??? This doesn't work yet, so don't let people try to use it. */
4092 if (mips_abi == ABI_32)
4093 error ("The -mabi=32 support does not work yet.");
4095 if (mips_abi_string)
4096 error ("This target does not support the -mabi switch.");
4099 #ifdef MIPS_CPU_STRING_DEFAULT
4100 /* ??? There is a minor inconsistency here. If the user specifies an ISA
4101 greater than that supported by the default processor, then the user gets
4102 an error. Normally, the compiler will just default to the base level cpu
4103 for the indicated isa. */
4104 if (mips_cpu_string == (char *)0)
4105 mips_cpu_string = MIPS_CPU_STRING_DEFAULT;
4108 /* Identify the processor type */
4109 if (mips_cpu_string == (char *)0
4110 || !strcmp (mips_cpu_string, "default")
4111 || !strcmp (mips_cpu_string, "DEFAULT"))
4116 mips_cpu_string = "3000";
4117 mips_cpu = PROCESSOR_R3000;
4120 mips_cpu_string = "6000";
4121 mips_cpu = PROCESSOR_R6000;
4124 mips_cpu_string = "4000";
4125 mips_cpu = PROCESSOR_R4000;
4128 mips_cpu_string = "8000";
4129 mips_cpu = PROCESSOR_R8000;
4136 char *p = mips_cpu_string;
4139 /* We need to cope with the various "vr" prefixes for the NEC 4300
4140 and 4100 processors. */
4141 if (*p == 'v' || *p == 'V')
4146 if (*p == 'r' || *p == 'R')
4149 /* Since there is no difference between a R2000 and R3000 in
4150 terms of the scheduler, we collapse them into just an R3000. */
4152 mips_cpu = PROCESSOR_DEFAULT;
4155 /* start-sanitize-tx19 */
4157 if (!strcmp (p, "1900"))
4158 mips_cpu = PROCESSOR_R3900;
4160 /* end-sanitize-tx19 */
4163 if (!strcmp (p, "2000") || !strcmp (p, "2k") || !strcmp (p, "2K"))
4164 mips_cpu = PROCESSOR_R3000;
4168 if (!strcmp (p, "3000") || !strcmp (p, "3k") || !strcmp (p, "3K"))
4169 mips_cpu = PROCESSOR_R3000;
4170 else if (!strcmp (p, "3900"))
4171 mips_cpu = PROCESSOR_R3900;
4175 if (!strcmp (p, "4000") || !strcmp (p, "4k") || !strcmp (p, "4K"))
4176 mips_cpu = PROCESSOR_R4000;
4177 /* The vr4100 is a non-FP ISA III processor with some extra
4179 else if (!strcmp (p, "4100")) {
4180 mips_cpu = PROCESSOR_R4100;
4181 target_flags |= MASK_SOFT_FLOAT ;
4183 /* The vr4300 is a standard ISA III processor, but with a different
4185 else if (!strcmp (p, "4300"))
4186 mips_cpu = PROCESSOR_R4300;
4187 /* The r4400 is exactly the same as the r4000 from the compiler's
4189 else if (!strcmp (p, "4400"))
4190 mips_cpu = PROCESSOR_R4000;
4191 else if (!strcmp (p, "4600"))
4192 mips_cpu = PROCESSOR_R4600;
4193 else if (!strcmp (p, "4650"))
4194 mips_cpu = PROCESSOR_R4650;
4198 if (!strcmp (p, "5000") || !strcmp (p, "5k") || !strcmp (p, "5K"))
4199 mips_cpu = PROCESSOR_R5000;
4203 if (!strcmp (p, "6000") || !strcmp (p, "6k") || !strcmp (p, "6K"))
4204 mips_cpu = PROCESSOR_R6000;
4208 if (!strcmp (p, "8000"))
4209 mips_cpu = PROCESSOR_R8000;
4213 if (!strcmp (p, "orion"))
4214 mips_cpu = PROCESSOR_R4600;
4219 && mips_cpu != PROCESSOR_R4300
4220 && mips_cpu != PROCESSOR_R4100
4221 && mips_cpu != PROCESSOR_R5000)
4222 mips_cpu = PROCESSOR_DEFAULT;
4224 if (mips_cpu == PROCESSOR_DEFAULT)
4226 error ("bad value (%s) for -mcpu= switch", mips_cpu_string);
4227 mips_cpu_string = "default";
4231 if ((mips_cpu == PROCESSOR_R3000 && mips_isa > 1)
4232 || (mips_cpu == PROCESSOR_R6000 && mips_isa > 2)
4233 || ((mips_cpu == PROCESSOR_R4000
4234 || mips_cpu == PROCESSOR_R4100
4235 || mips_cpu == PROCESSOR_R4300
4236 || mips_cpu == PROCESSOR_R4600
4237 || mips_cpu == PROCESSOR_R4650)
4239 error ("-mcpu=%s does not support -mips%d", mips_cpu_string, mips_isa);
4241 /* make sure sizes of ints/longs/etc. are ok */
4245 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit ints");
4247 else if (TARGET_LONG64)
4248 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit longs");
4250 else if (TARGET_FLOAT64)
4251 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit fp registers");
4253 else if (TARGET_64BIT)
4254 fatal ("Only MIPS-III or MIPS-IV CPUs can support 64 bit gp registers");
4257 if (mips_abi != ABI_32)
4258 flag_pcc_struct_return = 0;
4260 /* Tell halfpic.c that we have half-pic code if we do. */
4261 if (TARGET_HALF_PIC)
4264 /* -fpic (-KPIC) is the default when TARGET_ABICALLS is defined. We need
4265 to set flag_pic so that the LEGITIMATE_PIC_OPERAND_P macro will work. */
4266 /* ??? -non_shared turns off pic code generation, but this is not
4268 if (TARGET_ABICALLS)
4270 mips_abicalls = MIPS_ABICALLS_YES;
4272 if (mips_section_threshold > 0)
4273 warning ("-G is incompatible with PIC code which is the default");
4276 mips_abicalls = MIPS_ABICALLS_NO;
4278 /* -membedded-pic is a form of PIC code suitable for embedded
4279 systems. All calls are made using PC relative addressing, and
4280 all data is addressed using the $gp register. This requires gas,
4281 which does most of the work, and GNU ld, which automatically
4282 expands PC relative calls which are out of range into a longer
4283 instruction sequence. All gcc really does differently is
4284 generate a different sequence for a switch. */
4285 if (TARGET_EMBEDDED_PIC)
4288 if (TARGET_ABICALLS)
4289 warning ("-membedded-pic and -mabicalls are incompatible");
4291 warning ("-G and -membedded-pic are incompatible");
4292 /* Setting mips_section_threshold is not required, because gas
4293 will force everything to be GP addressable anyhow, but
4294 setting it will cause gcc to make better estimates of the
4295 number of instructions required to access a particular data
4297 mips_section_threshold = 0x7fffffff;
4300 /* This optimization requires a linker that can support a R_MIPS_LO16
4301 relocation which is not immediately preceeded by a R_MIPS_HI16 relocation.
4302 GNU ld has this support, but not all other MIPS linkers do, so we enable
4303 this optimization only if the user requests it, or if GNU ld is the
4304 standard linker for this configuration. */
4305 /* ??? This does not work when target addresses are DImode.
4306 This is because we are missing DImode high/lo_sum patterns. */
4307 if (TARGET_GAS && ! TARGET_MIPS16 && TARGET_SPLIT_ADDRESSES && optimize && ! flag_pic
4309 mips_split_addresses = 1;
4311 mips_split_addresses = 0;
4313 /* -mrnames says to use the MIPS software convention for register
4314 names instead of the hardware names (ie, $a0 instead of $4).
4315 We do this by switching the names in mips_reg_names, which the
4316 reg_names points into via the REGISTER_NAMES macro. */
4318 if (TARGET_NAME_REGS)
4319 bcopy ((char *) mips_sw_reg_names, (char *) mips_reg_names, sizeof (mips_reg_names));
4321 /* When compiling for the mips16, we can not use floating point. We
4322 record the original hard float value in mips16_hard_float. */
4325 if (TARGET_SOFT_FLOAT)
4326 mips16_hard_float = 0;
4328 mips16_hard_float = 1;
4329 target_flags |= MASK_SOFT_FLOAT;
4331 /* Don't run the scheduler before reload, since it tends to
4332 increase register pressure. */
4333 flag_schedule_insns = 0;
4336 /* We put -mentry in TARGET_OPTIONS rather than TARGET_SWITCHES only
4337 to avoid using up another bit in target_flags. */
4338 if (mips_entry_string != NULL)
4340 if (*mips_entry_string != '\0')
4341 error ("Invalid option `entry%s'", mips_entry_string);
4343 if (! TARGET_MIPS16)
4344 warning ("-mentry is only meaningful with -mips-16");
4349 /* We copy TARGET_MIPS16 into the mips16 global variable, so that
4350 attributes can access it. */
4357 #if defined(ultrix) || defined(__ultrix) || defined(__OSF1__) || defined(__osf__) || defined(osf)
4358 /* If -mstats and -quiet, make stderr line buffered. */
4359 if (quiet_flag && TARGET_STATS)
4360 setvbuf (stderr, (char *)0, _IOLBF, BUFSIZ);
4364 /* Initialize the high and low values for legitimate floating point
4365 constants. Rather than trying to get the accuracy down to the
4366 last bit, just use approximate ranges. */
4367 dfhigh = REAL_VALUE_ATOF ("1.0e300", DFmode);
4368 dflow = REAL_VALUE_ATOF ("1.0e-300", DFmode);
4369 sfhigh = REAL_VALUE_ATOF ("1.0e38", SFmode);
4370 sflow = REAL_VALUE_ATOF ("1.0e-38", SFmode);
4372 mips_print_operand_punct['?'] = TRUE;
4373 mips_print_operand_punct['#'] = TRUE;
4374 mips_print_operand_punct['&'] = TRUE;
4375 mips_print_operand_punct['!'] = TRUE;
4376 mips_print_operand_punct['*'] = TRUE;
4377 mips_print_operand_punct['@'] = TRUE;
4378 mips_print_operand_punct['.'] = TRUE;
4379 mips_print_operand_punct['('] = TRUE;
4380 mips_print_operand_punct[')'] = TRUE;
4381 mips_print_operand_punct['['] = TRUE;
4382 mips_print_operand_punct[']'] = TRUE;
4383 mips_print_operand_punct['<'] = TRUE;
4384 mips_print_operand_punct['>'] = TRUE;
4385 mips_print_operand_punct['{'] = TRUE;
4386 mips_print_operand_punct['}'] = TRUE;
4387 mips_print_operand_punct['^'] = TRUE;
4388 mips_print_operand_punct['$'] = TRUE;
4389 mips_print_operand_punct['+'] = TRUE;
4391 mips_char_to_class['d'] = TARGET_MIPS16 ? M16_REGS : GR_REGS;
4392 mips_char_to_class['e'] = M16_NA_REGS;
4393 mips_char_to_class['t'] = T_REG;
4394 mips_char_to_class['f'] = ((TARGET_HARD_FLOAT) ? FP_REGS : NO_REGS);
4395 mips_char_to_class['h'] = HI_REG;
4396 mips_char_to_class['l'] = LO_REG;
4397 mips_char_to_class['a'] = HILO_REG;
4398 mips_char_to_class['x'] = MD_REGS;
4399 mips_char_to_class['b'] = ALL_REGS;
4400 mips_char_to_class['y'] = GR_REGS;
4401 mips_char_to_class['z'] = ST_REGS;
4403 /* Set up array to map GCC register number to debug register number.
4404 Ignore the special purpose register numbers. */
4406 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4407 mips_dbx_regno[i] = -1;
4409 start = GP_DBX_FIRST - GP_REG_FIRST;
4410 for (i = GP_REG_FIRST; i <= GP_REG_LAST; i++)
4411 mips_dbx_regno[i] = i + start;
4413 start = FP_DBX_FIRST - FP_REG_FIRST;
4414 for (i = FP_REG_FIRST; i <= FP_REG_LAST; i++)
4415 mips_dbx_regno[i] = i + start;
4417 /* Set up array giving whether a given register can hold a given mode.
4418 At present, restrict ints from being in FP registers, because reload
4419 is a little enthusiastic about storing extra values in FP registers,
4420 and this is not good for things like OS kernels. Also, due to the
4421 mandatory delay, it is as fast to load from cached memory as to move
4422 from the FP register. */
4424 for (mode = VOIDmode;
4425 mode != MAX_MACHINE_MODE;
4426 mode = (enum machine_mode)((int)mode + 1))
4428 register int size = GET_MODE_SIZE (mode);
4429 register enum mode_class class = GET_MODE_CLASS (mode);
4431 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
4438 temp = (regno == FPSW_REGNUM);
4440 temp = (ST_REG_P (regno)
4442 || FP_REG_P (regno));
4445 else if (GP_REG_P (regno))
4446 temp = ((regno & 1) == 0 || (size <= UNITS_PER_WORD));
4448 else if (FP_REG_P (regno))
4449 temp = ((TARGET_FLOAT64 || ((regno & 1) == 0))
4450 && (class == MODE_FLOAT
4451 || class == MODE_COMPLEX_FLOAT
4452 || (TARGET_DEBUG_H_MODE && class == MODE_INT))
4453 && (! TARGET_SINGLE_FLOAT || size <= 4));
4455 else if (MD_REG_P (regno))
4456 temp = (class == MODE_INT
4457 && (size <= UNITS_PER_WORD
4458 || (regno == MD_REG_FIRST && size == 2 * UNITS_PER_WORD)));
4463 mips_hard_regno_mode_ok[(int)mode][regno] = temp;
4468 /* On the mips16, we want to allocate $24 (T_REG) before other
4469 registers for instructions for which it is possible. This helps
4470 avoid shuffling registers around in order to set up for an xor,
4471 encouraging the compiler to use a cmp instead. */
4474 mips_order_regs_for_local_alloc ()
4478 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
4479 reg_alloc_order[i] = i;
4483 /* It really doesn't matter where we put register 0, since it is
4484 a fixed register anyhow. */
4485 reg_alloc_order[0] = 24;
4486 reg_alloc_order[24] = 0;
4492 * The MIPS debug format wants all automatic variables and arguments
4493 * to be in terms of the virtual frame pointer (stack pointer before
4494 * any adjustment in the function), while the MIPS 3.0 linker wants
4495 * the frame pointer to be the stack pointer after the initial
4496 * adjustment. So, we do the adjustment here. The arg pointer (which
4497 * is eliminated) points to the virtual frame pointer, while the frame
4498 * pointer (which may be eliminated) points to the stack pointer after
4499 * the initial adjustments.
4503 mips_debugger_offset (addr, offset)
4507 rtx offset2 = const0_rtx;
4508 rtx reg = eliminate_constant_term (addr, &offset2);
4511 offset = INTVAL (offset2);
4513 if (reg == stack_pointer_rtx || reg == frame_pointer_rtx
4514 || reg == hard_frame_pointer_rtx)
4516 int frame_size = (!current_frame_info.initialized)
4517 ? compute_frame_size (get_frame_size ())
4518 : current_frame_info.total_size;
4520 offset = offset - frame_size;
4522 /* sdbout_parms does not want this to crash for unrecognized cases. */
4524 else if (reg != arg_pointer_rtx)
4525 abort_with_insn (addr, "mips_debugger_offset called with non stack/frame/arg pointer.");
4532 /* A C compound statement to output to stdio stream STREAM the
4533 assembler syntax for an instruction operand X. X is an RTL
4536 CODE is a value that can be used to specify one of several ways
4537 of printing the operand. It is used when identical operands
4538 must be printed differently depending on the context. CODE
4539 comes from the `%' specification that was used to request
4540 printing of the operand. If the specification was just `%DIGIT'
4541 then CODE is 0; if the specification was `%LTR DIGIT' then CODE
4542 is the ASCII code for LTR.
4544 If X is a register, this macro should print the register's name.
4545 The names can be found in an array `reg_names' whose type is
4546 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'.
4548 When the machine description has a specification `%PUNCT' (a `%'
4549 followed by a punctuation character), this macro is called with
4550 a null pointer for X and the punctuation character for CODE.
4552 The MIPS specific codes are:
4554 'X' X is CONST_INT, prints 32 bits in hexadecimal format = "0x%08x",
4555 'x' X is CONST_INT, prints 16 bits in hexadecimal format = "0x%04x",
4556 'd' output integer constant in decimal,
4557 'z' if the operand is 0, use $0 instead of normal operand.
4558 'D' print second register of double-word register operand.
4559 'L' print low-order register of double-word register operand.
4560 'M' print high-order register of double-word register operand.
4561 'C' print part of opcode for a branch condition.
4562 'N' print part of opcode for a branch condition, inverted.
4563 'S' X is CODE_LABEL, print with prefix of "LS" (for embedded switch).
4564 'B' print 'z' for EQ, 'n' for NE
4565 'b' print 'n' for EQ, 'z' for NE
4566 'T' print 'f' for EQ, 't' for NE
4567 't' print 't' for EQ, 'f' for NE
4568 'Z' print register and a comma, but print nothing for $fcc0
4569 '(' Turn on .set noreorder
4570 ')' Turn on .set reorder
4571 '[' Turn on .set noat
4573 '<' Turn on .set nomacro
4574 '>' Turn on .set macro
4575 '{' Turn on .set volatile (not GAS)
4576 '}' Turn on .set novolatile (not GAS)
4577 '&' Turn on .set noreorder if filling delay slots
4578 '*' Turn on both .set noreorder and .set nomacro if filling delay slots
4579 '!' Turn on .set nomacro if filling delay slots
4580 '#' Print nop if in a .set noreorder section.
4581 '?' Print 'l' if we are to use a branch likely instead of normal branch.
4582 '@' Print the name of the assembler temporary register (at or $1).
4583 '.' Print the name of the register with a hard-wired zero (zero or $0).
4584 '^' Print the name of the pic call-through register (t9 or $25).
4585 '$' Print the name of the stack pointer register (sp or $29).
4586 '+' Print the name of the gp register (gp or $28). */
4589 print_operand (file, op, letter)
4590 FILE *file; /* file to write to */
4591 rtx op; /* operand to print */
4592 int letter; /* %<letter> or 0 */
4594 register enum rtx_code code;
4596 if (PRINT_OPERAND_PUNCT_VALID_P (letter))
4601 error ("PRINT_OPERAND: Unknown punctuation '%c'", letter);
4605 if (mips_branch_likely)
4610 fputs (reg_names [GP_REG_FIRST + 1], file);
4614 fputs (reg_names [PIC_FUNCTION_ADDR_REGNUM], file);
4618 fputs (reg_names [GP_REG_FIRST + 0], file);
4622 fputs (reg_names[STACK_POINTER_REGNUM], file);
4626 fputs (reg_names[GP_REG_FIRST + 28], file);
4630 if (final_sequence != 0 && set_noreorder++ == 0)
4631 fputs (".set\tnoreorder\n\t", file);
4635 if (final_sequence != 0)
4637 if (set_noreorder++ == 0)
4638 fputs (".set\tnoreorder\n\t", file);
4640 if (set_nomacro++ == 0)
4641 fputs (".set\tnomacro\n\t", file);
4646 if (final_sequence != 0 && set_nomacro++ == 0)
4647 fputs ("\n\t.set\tnomacro", file);
4651 if (set_noreorder != 0)
4652 fputs ("\n\tnop", file);
4654 else if (TARGET_STATS)
4655 fputs ("\n\t#nop", file);
4660 if (set_noreorder++ == 0)
4661 fputs (".set\tnoreorder\n\t", file);
4665 if (set_noreorder == 0)
4666 error ("internal error: %%) found without a %%( in assembler pattern");
4668 else if (--set_noreorder == 0)
4669 fputs ("\n\t.set\treorder", file);
4674 if (set_noat++ == 0)
4675 fputs (".set\tnoat\n\t", file);
4680 error ("internal error: %%] found without a %%[ in assembler pattern");
4682 else if (--set_noat == 0)
4683 fputs ("\n\t.set\tat", file);
4688 if (set_nomacro++ == 0)
4689 fputs (".set\tnomacro\n\t", file);
4693 if (set_nomacro == 0)
4694 error ("internal error: %%> found without a %%< in assembler pattern");
4696 else if (--set_nomacro == 0)
4697 fputs ("\n\t.set\tmacro", file);
4702 if (set_volatile++ == 0)
4703 fprintf (file, "%s.set\tvolatile\n\t", (TARGET_MIPS_AS) ? "" : "#");
4707 if (set_volatile == 0)
4708 error ("internal error: %%} found without a %%{ in assembler pattern");
4710 else if (--set_volatile == 0)
4711 fprintf (file, "\n\t%s.set\tnovolatile", (TARGET_MIPS_AS) ? "" : "#");
4720 error ("PRINT_OPERAND null pointer");
4724 code = GET_CODE (op);
4726 if (code == SIGN_EXTEND)
4729 code = GET_CODE (op);
4735 case EQ: fputs ("eq", file); break;
4736 case NE: fputs ("ne", file); break;
4737 case GT: fputs ("gt", file); break;
4738 case GE: fputs ("ge", file); break;
4739 case LT: fputs ("lt", file); break;
4740 case LE: fputs ("le", file); break;
4741 case GTU: fputs ("gtu", file); break;
4742 case GEU: fputs ("geu", file); break;
4743 case LTU: fputs ("ltu", file); break;
4744 case LEU: fputs ("leu", file); break;
4747 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%C");
4750 else if (letter == 'N')
4753 case EQ: fputs ("ne", file); break;
4754 case NE: fputs ("eq", file); break;
4755 case GT: fputs ("le", file); break;
4756 case GE: fputs ("lt", file); break;
4757 case LT: fputs ("ge", file); break;
4758 case LE: fputs ("gt", file); break;
4759 case GTU: fputs ("leu", file); break;
4760 case GEU: fputs ("ltu", file); break;
4761 case LTU: fputs ("geu", file); break;
4762 case LEU: fputs ("gtu", file); break;
4765 abort_with_insn (op, "PRINT_OPERAND, invalid insn for %%N");
4768 else if (letter == 'S')
4772 ASM_GENERATE_INTERNAL_LABEL (buffer, "LS", CODE_LABEL_NUMBER (op));
4773 assemble_name (file, buffer);
4776 else if (letter == 'Z')
4778 register int regnum;
4782 regnum = REGNO (op);
4783 if (! ST_REG_P (regnum))
4785 if (regnum != ST_REG_FIRST)
4786 fprintf (file, "%s,", reg_names[regnum]);
4789 else if (code == REG || code == SUBREG)
4791 register int regnum;
4794 regnum = REGNO (op);
4796 regnum = true_regnum (op);
4798 if ((letter == 'M' && ! WORDS_BIG_ENDIAN)
4799 || (letter == 'L' && WORDS_BIG_ENDIAN)
4803 fprintf (file, "%s", reg_names[regnum]);
4806 else if (code == MEM)
4807 output_address (XEXP (op, 0));
4809 else if (code == CONST_DOUBLE
4810 && GET_MODE_CLASS (GET_MODE (op)) == MODE_FLOAT)
4815 REAL_VALUE_FROM_CONST_DOUBLE (d, op);
4816 REAL_VALUE_TO_DECIMAL (d, "%.20e", s);
4820 else if ((letter == 'x') && (GET_CODE(op) == CONST_INT))
4821 fprintf (file, "0x%04x", 0xffff & ((int) INTVAL(op)));
4822 #if HOST_BITS_PER_WIDE_INT <= HOST_BITS_PER_LONG
4823 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT))
4824 fprintf (file, "0x%08lx", (unsigned long) INTVAL(op));
4826 else if ((letter == 'X') && (GET_CODE(op) == CONST_INT))
4827 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL(op));
4829 else if ((letter == 'd') && (GET_CODE(op) == CONST_INT))
4830 fprintf (file, "%ld", ((long) INTVAL(op)));
4832 else if (letter == 'z'
4833 && (GET_CODE (op) == CONST_INT)
4834 && INTVAL (op) == 0)
4835 fputs (reg_names[GP_REG_FIRST], file);
4837 else if (letter == 'd' || letter == 'x' || letter == 'X')
4838 fatal ("PRINT_OPERAND: letter %c was found & insn was not CONST_INT", letter);
4840 else if (letter == 'B')
4841 fputs (code == EQ ? "z" : "n", file);
4842 else if (letter == 'b')
4843 fputs (code == EQ ? "n" : "z", file);
4844 else if (letter == 'T')
4845 fputs (code == EQ ? "f" : "t", file);
4846 else if (letter == 't')
4847 fputs (code == EQ ? "t" : "f", file);
4849 else if (code == CONST && GET_CODE (XEXP (op, 0)) == REG)
4851 /* This case arises on the mips16; see mips16_gp_pseudo_reg. */
4852 print_operand (file, XEXP (op, 0), letter);
4855 else if (TARGET_MIPS16 && code == CONST && mips16_gp_offset_p (op))
4857 fputs ("%gprel(", file);
4858 mips16_output_gp_offset (file, op);
4863 output_addr_const (file, op);
4867 /* A C compound statement to output to stdio stream STREAM the
4868 assembler syntax for an instruction operand that is a memory
4869 reference whose address is ADDR. ADDR is an RTL expression.
4871 On some machines, the syntax for a symbolic address depends on
4872 the section that the address refers to. On these machines,
4873 define the macro `ENCODE_SECTION_INFO' to store the information
4874 into the `symbol_ref', and then check for it here. */
4877 print_operand_address (file, addr)
4882 error ("PRINT_OPERAND_ADDRESS, null pointer");
4885 switch (GET_CODE (addr))
4888 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #1");
4892 if (! TARGET_MIPS16 && REGNO (addr) == ARG_POINTER_REGNUM)
4893 abort_with_insn (addr, "Arg pointer not eliminated.");
4895 fprintf (file, "0(%s)", reg_names [REGNO (addr)]);
4900 register rtx arg0 = XEXP (addr, 0);
4901 register rtx arg1 = XEXP (addr, 1);
4903 if (! mips_split_addresses)
4904 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, Spurious LO_SUM.");
4906 if (GET_CODE (arg0) != REG)
4907 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, LO_SUM with #1 not REG.");
4909 fprintf (file, "%%lo(");
4910 print_operand_address (file, arg1);
4911 fprintf (file, ")(%s)", reg_names [REGNO (arg0)]);
4917 register rtx reg = (rtx)0;
4918 register rtx offset = (rtx)0;
4919 register rtx arg0 = XEXP (addr, 0);
4920 register rtx arg1 = XEXP (addr, 1);
4922 if (GET_CODE (arg0) == REG)
4926 if (GET_CODE (offset) == REG)
4927 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, 2 regs");
4929 else if (GET_CODE (arg1) == REG)
4934 else if (CONSTANT_P (arg0) && CONSTANT_P (arg1))
4936 output_addr_const (file, addr);
4940 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, no regs");
4942 if (!CONSTANT_P (offset))
4943 abort_with_insn (addr, "PRINT_OPERAND_ADDRESS, invalid insn #2");
4945 if (REGNO (reg) == ARG_POINTER_REGNUM)
4946 abort_with_insn (addr, "Arg pointer not eliminated.");
4949 && GET_CODE (offset) == CONST
4950 && mips16_gp_offset_p (offset))
4952 fputs ("%gprel(", file);
4953 mips16_output_gp_offset (file, offset);
4957 output_addr_const (file, offset);
4958 fprintf (file, "(%s)", reg_names [REGNO (reg)]);
4966 output_addr_const (file, addr);
4972 /* If optimizing for the global pointer, keep track of all of
4973 the externs, so that at the end of the file, we can emit
4974 the appropriate .extern declaration for them, before writing
4975 out the text section. We assume that all names passed to
4976 us are in the permanent obstack, so that they will be valid
4977 at the end of the compilation.
4979 If we have -G 0, or the extern size is unknown, or the object is in
4980 a user specified section that is not .sbss/.sdata, don't bother
4981 emitting the .externs. In the case of user specified sections this
4982 behaviour is required as otherwise GAS will think the object lives in
4986 mips_output_external (file, decl, name)
4991 register struct extern_list *p;
4996 && ((TREE_CODE (decl)) != FUNCTION_DECL)
4997 && ((len = int_size_in_bytes (TREE_TYPE (decl))) > 0)
4998 && (((section_name = DECL_SECTION_NAME (decl)) == NULL)
4999 || strcmp (TREE_STRING_POINTER (section_name), ".sbss") == 0
5000 || strcmp (TREE_STRING_POINTER (section_name), ".sdata") == 0))
5002 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
5003 p->next = extern_head;
5009 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5010 if (TREE_CODE (decl) == FUNCTION_DECL
5011 /* ??? Don't include alloca, since gcc will always expand it
5012 inline. If we don't do this, the C++ library fails to build. */
5013 && strcmp (name, "alloca")
5014 /* ??? Don't include __builtin_next_arg, because then gcc will not
5015 bootstrap under Irix 5.1. */
5016 && strcmp (name, "__builtin_next_arg"))
5018 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
5019 p->next = extern_head;
5029 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5031 mips_output_external_libcall (file, name)
5035 register struct extern_list *p;
5037 p = (struct extern_list *)permalloc ((long) sizeof (struct extern_list));
5038 p->next = extern_head;
5048 /* Compute a string to use as a temporary file name. */
5050 /* On MSDOS, write temp files in current dir
5051 because there's no place else we can expect to use. */
5054 #define P_tmpdir "./"
5062 char *base = getenv ("TMPDIR");
5065 if (base == (char *)0)
5068 if (access (P_tmpdir, R_OK | W_OK) == 0)
5072 if (access ("/usr/tmp", R_OK | W_OK) == 0)
5078 len = strlen (base);
5079 /* temp_filename is global, so we must use malloc, not alloca. */
5080 temp_filename = (char *) xmalloc (len + sizeof("/ctXXXXXX"));
5081 strcpy (temp_filename, base);
5082 if (len > 0 && temp_filename[len-1] != '/')
5083 temp_filename[len++] = '/';
5085 strcpy (temp_filename + len, "ctXXXXXX");
5086 mktemp (temp_filename);
5088 stream = fopen (temp_filename, "w+");
5090 pfatal_with_name (temp_filename);
5093 /* In MSDOS, we cannot unlink the temporary file until we are finished using
5094 it. Otherwise, we delete it now, so that it will be gone even if the
5095 compiler happens to crash. */
5096 unlink (temp_filename);
5102 /* Emit a new filename to a stream. If this is MIPS ECOFF, watch out
5103 for .file's that start within a function. If we are smuggling stabs, try to
5104 put out a MIPS ECOFF file and a stab. */
5107 mips_output_filename (stream, name)
5111 static int first_time = TRUE;
5112 char ltext_label_name[100];
5118 current_function_file = name;
5119 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5120 /* This tells mips-tfile that stabs will follow. */
5121 if (!TARGET_GAS && write_symbols == DBX_DEBUG)
5122 fprintf (stream, "\t#@stabs\n");
5125 else if (write_symbols == DBX_DEBUG)
5127 ASM_GENERATE_INTERNAL_LABEL (ltext_label_name, "Ltext", 0);
5128 fprintf (stream, "%s ", ASM_STABS_OP);
5129 output_quoted_string (stream, name);
5130 fprintf (stream, ",%d,0,0,%s\n", N_SOL, <ext_label_name[1]);
5133 else if (name != current_function_file
5134 && strcmp (name, current_function_file) != 0)
5136 if (inside_function && !TARGET_GAS)
5138 if (!file_in_function_warning)
5140 file_in_function_warning = TRUE;
5141 ignore_line_number = TRUE;
5142 warning ("MIPS ECOFF format does not allow changing filenames within functions with #line");
5148 current_function_file = name;
5149 ASM_OUTPUT_FILENAME (stream, num_source_filenames, name);
5155 /* Emit a linenumber. For encapsulated stabs, we need to put out a stab
5156 as well as a .loc, since it is possible that MIPS ECOFF might not be
5157 able to represent the location for inlines that come from a different
5161 mips_output_lineno (stream, line)
5165 if (write_symbols == DBX_DEBUG)
5168 fprintf (stream, "%sLM%d:\n\t%s %d,0,%d,%sLM%d\n",
5169 LOCAL_LABEL_PREFIX, sym_lineno, ASM_STABN_OP, N_SLINE, line,
5170 LOCAL_LABEL_PREFIX, sym_lineno);
5175 fprintf (stream, "\n\t%s.loc\t%d %d\n",
5176 (ignore_line_number) ? "#" : "",
5177 num_source_filenames, line);
5179 LABEL_AFTER_LOC (stream);
5184 /* If defined, a C statement to be executed just prior to the
5185 output of assembler code for INSN, to modify the extracted
5186 operands so they will be output differently.
5188 Here the argument OPVEC is the vector containing the operands
5189 extracted from INSN, and NOPERANDS is the number of elements of
5190 the vector which contain meaningful data for this insn. The
5191 contents of this vector are what will be used to convert the
5192 insn template into assembler code, so you can change the
5193 assembler output by changing the contents of the vector.
5195 We use it to check if the current insn needs a nop in front of it
5196 because of load delays, and also to update the delay slot
5199 /* ??? There is no real need for this function, because it never actually
5200 emits a NOP anymore. */
5203 final_prescan_insn (insn, opvec, noperands)
5208 if (dslots_number_nops > 0)
5210 rtx pattern = PATTERN (insn);
5211 int length = get_attr_length (insn);
5213 /* Do we need to emit a NOP? */
5215 || (mips_load_reg != (rtx)0 && reg_mentioned_p (mips_load_reg, pattern))
5216 || (mips_load_reg2 != (rtx)0 && reg_mentioned_p (mips_load_reg2, pattern))
5217 || (mips_load_reg3 != (rtx)0 && reg_mentioned_p (mips_load_reg3, pattern))
5218 || (mips_load_reg4 != (rtx)0 && reg_mentioned_p (mips_load_reg4, pattern)))
5219 fputs ("\t#nop\n", asm_out_file);
5222 dslots_load_filled++;
5224 while (--dslots_number_nops > 0)
5225 fputs ("\t#nop\n", asm_out_file);
5227 mips_load_reg = (rtx)0;
5228 mips_load_reg2 = (rtx)0;
5229 mips_load_reg3 = (rtx)0;
5230 mips_load_reg4 = (rtx)0;
5235 enum rtx_code code = GET_CODE (insn);
5236 if (code == JUMP_INSN || code == CALL_INSN)
5237 dslots_jump_total++;
5242 /* Output at beginning of assembler file.
5243 If we are optimizing to use the global pointer, create a temporary
5244 file to hold all of the text stuff, and write it out to the end.
5245 This is needed because the MIPS assembler is evidently one pass,
5246 and if it hasn't seen the relevant .comm/.lcomm/.extern/.sdata
5247 declaration when the code is processed, it generates a two
5248 instruction sequence. */
5251 mips_asm_file_start (stream)
5254 ASM_OUTPUT_SOURCE_FILENAME (stream, main_input_filename);
5256 /* Versions of the MIPS assembler before 2.20 generate errors
5257 if a branch inside of a .set noreorder section jumps to a
5258 label outside of the .set noreorder section. Revision 2.20
5259 just set nobopt silently rather than fixing the bug. */
5261 if (TARGET_MIPS_AS && optimize && flag_delayed_branch)
5262 fprintf (stream, "\t.set\tnobopt\n");
5264 /* Generate the pseudo ops that System V.4 wants. */
5265 #ifndef ABICALLS_ASM_OP
5266 #define ABICALLS_ASM_OP ".abicalls"
5268 if (TARGET_ABICALLS)
5269 /* ??? but do not want this (or want pic0) if -non-shared? */
5270 fprintf (stream, "\t%s\n", ABICALLS_ASM_OP);
5273 fprintf (stream, "\t.set\tmips16\n");
5275 /* Start a section, so that the first .popsection directive is guaranteed
5276 to have a previously defined section to pop back to. */
5277 if (mips_abi != ABI_32 && mips_abi != ABI_EABI)
5278 fprintf (stream, "\t.section\t.text\n");
5280 /* This code exists so that we can put all externs before all symbol
5281 references. This is necessary for the MIPS assembler's global pointer
5282 optimizations to work. */
5283 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5285 asm_out_data_file = stream;
5286 asm_out_text_file = make_temp_file ();
5289 asm_out_data_file = asm_out_text_file = stream;
5291 if (flag_verbose_asm)
5292 fprintf (stream, "\n%s -G value = %d, Cpu = %s, ISA = %d\n",
5294 mips_section_threshold, mips_cpu_string, mips_isa);
5298 /* If we are optimizing the global pointer, emit the text section now
5299 and any small externs which did not have .comm, etc that are
5300 needed. Also, give a warning if the data area is more than 32K and
5301 -pic because 3 instructions are needed to reference the data
5305 mips_asm_file_end (file)
5310 struct extern_list *p;
5315 HALF_PIC_FINISH (file);
5322 for (p = extern_head; p != 0; p = p->next)
5324 name_tree = get_identifier (p->name);
5326 /* Positively ensure only one .extern for any given symbol. */
5327 if (! TREE_ASM_WRITTEN (name_tree))
5329 TREE_ASM_WRITTEN (name_tree) = 1;
5330 #ifdef ASM_OUTPUT_UNDEF_FUNCTION
5332 ASM_OUTPUT_UNDEF_FUNCTION (file, p->name);
5336 fputs ("\t.extern\t", file);
5337 assemble_name (file, p->name);
5338 fprintf (file, ", %d\n", p->size);
5344 if (TARGET_FILE_SWITCHING && ! TARGET_MIPS16)
5346 fprintf (file, "\n\t.text\n");
5347 rewind (asm_out_text_file);
5348 if (ferror (asm_out_text_file))
5349 fatal_io_error (temp_filename);
5351 while ((len = fread (buffer, 1, sizeof (buffer), asm_out_text_file)) > 0)
5352 if (fwrite (buffer, 1, len, file) != len)
5353 pfatal_with_name (asm_file_name);
5356 pfatal_with_name (temp_filename);
5358 if (fclose (asm_out_text_file) != 0)
5359 pfatal_with_name (temp_filename);
5362 unlink (temp_filename);
5368 /* Emit either a label, .comm, or .lcomm directive, and mark
5369 that the symbol is used, so that we don't emit an .extern
5370 for it in mips_asm_file_end. */
5373 mips_declare_object (stream, name, init_string, final_string, size)
5380 fputs (init_string, stream); /* "", "\t.comm\t", or "\t.lcomm\t" */
5381 assemble_name (stream, name);
5382 fprintf (stream, final_string, size); /* ":\n", ",%u\n", ",%u\n" */
5386 tree name_tree = get_identifier (name);
5387 TREE_ASM_WRITTEN (name_tree) = 1;
5392 /* Output a double precision value to the assembler. If both the
5393 host and target are IEEE, emit the values in hex. */
5396 mips_output_double (stream, value)
5398 REAL_VALUE_TYPE value;
5400 #ifdef REAL_VALUE_TO_TARGET_DOUBLE
5402 REAL_VALUE_TO_TARGET_DOUBLE (value, value_long);
5404 fprintf (stream, "\t.word\t0x%08lx\t\t# %.20g\n\t.word\t0x%08lx\n",
5405 value_long[0], value, value_long[1]);
5407 fprintf (stream, "\t.double\t%.20g\n", value);
5412 /* Output a single precision value to the assembler. If both the
5413 host and target are IEEE, emit the values in hex. */
5416 mips_output_float (stream, value)
5418 REAL_VALUE_TYPE value;
5420 #ifdef REAL_VALUE_TO_TARGET_SINGLE
5422 REAL_VALUE_TO_TARGET_SINGLE (value, value_long);
5424 fprintf (stream, "\t.word\t0x%08lx\t\t# %.12g (float)\n", value_long, value);
5426 fprintf (stream, "\t.float\t%.12g\n", value);
5431 /* Return the bytes needed to compute the frame pointer from the current
5434 Mips stack frames look like:
5436 Before call After call
5437 +-----------------------+ +-----------------------+
5440 | caller's temps. | | caller's temps. |
5442 +-----------------------+ +-----------------------+
5444 | arguments on stack. | | arguments on stack. |
5446 +-----------------------+ +-----------------------+
5447 | 4 words to save | | 4 words to save |
5448 | arguments passed | | arguments passed |
5449 | in registers, even | | in registers, even |
5450 SP->| if not passed. | VFP->| if not passed. |
5451 +-----------------------+ +-----------------------+
5453 | fp register save |
5455 +-----------------------+
5457 | gp register save |
5459 +-----------------------+
5463 +-----------------------+
5465 | alloca allocations |
5467 +-----------------------+
5469 | GP save for V.4 abi |
5471 +-----------------------+
5473 | arguments on stack |
5475 +-----------------------+
5477 | arguments passed |
5478 | in registers, even |
5479 low SP->| if not passed. |
5480 memory +-----------------------+
5485 compute_frame_size (size)
5486 int size; /* # of var. bytes allocated */
5489 long total_size; /* # bytes that the entire frame takes up */
5490 long var_size; /* # bytes that variables take up */
5491 long args_size; /* # bytes that outgoing arguments take up */
5492 long extra_size; /* # extra bytes */
5493 long gp_reg_rounded; /* # bytes needed to store gp after rounding */
5494 long gp_reg_size; /* # bytes needed to store gp regs */
5495 long fp_reg_size; /* # bytes needed to store fp regs */
5496 long mask; /* mask of saved gp registers */
5497 long fmask; /* mask of saved fp registers */
5498 int fp_inc; /* 1 or 2 depending on the size of fp regs */
5499 long fp_bits; /* bitmask to use for each fp register */
5505 extra_size = MIPS_STACK_ALIGN (((TARGET_ABICALLS) ? UNITS_PER_WORD : 0));
5506 var_size = MIPS_STACK_ALIGN (size);
5507 args_size = MIPS_STACK_ALIGN (current_function_outgoing_args_size);
5509 /* The MIPS 3.0 linker does not like functions that dynamically
5510 allocate the stack and have 0 for STACK_DYNAMIC_OFFSET, since it
5511 looks like we are trying to create a second frame pointer to the
5512 function, so allocate some stack space to make it happy. */
5514 if (args_size == 0 && current_function_calls_alloca)
5515 args_size = 4*UNITS_PER_WORD;
5517 total_size = var_size + args_size + extra_size;
5519 /* Calculate space needed for gp registers. */
5520 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++)
5522 /* $18 is a special case on the mips16. It may be used to call
5523 a function which returns a floating point value, but it is
5524 marked in call_used_regs. $31 is also a special case. When
5525 not using -mentry, it will be used to copy a return value
5526 into the floating point registers if the return value is
5528 if (MUST_SAVE_REGISTER (regno)
5530 && regno == GP_REG_FIRST + 18
5531 && regs_ever_live[regno])
5533 && regno == GP_REG_FIRST + 31
5534 && mips16_hard_float
5536 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
5537 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
5539 && (! TARGET_SINGLE_FLOAT
5540 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
5543 gp_reg_size += UNITS_PER_WORD;
5544 mask |= 1L << (regno - GP_REG_FIRST);
5546 /* The entry and exit pseudo instructions can not save $17
5547 without also saving $16. */
5549 && regno == GP_REG_FIRST + 17
5550 && ! MUST_SAVE_REGISTER (GP_REG_FIRST + 16))
5552 gp_reg_size += UNITS_PER_WORD;
5558 /* Calculate space needed for fp registers. */
5559 if (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT)
5570 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno += fp_inc)
5572 if (regs_ever_live[regno] && !call_used_regs[regno])
5574 fp_reg_size += fp_inc * UNITS_PER_FPREG;
5575 fmask |= fp_bits << (regno - FP_REG_FIRST);
5579 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5580 total_size += gp_reg_rounded + MIPS_STACK_ALIGN (fp_reg_size);
5582 /* The gp reg is caller saved in the 32 bit ABI, so there is no need
5583 for leaf routines (total_size == extra_size) to save the gp reg.
5584 The gp reg is callee saved in the 64 bit ABI, so all routines must
5585 save the gp reg. This is not a leaf routine if -p, because of the
5587 if (total_size == extra_size && (mips_abi == ABI_32 || mips_abi == ABI_EABI)
5589 total_size = extra_size = 0;
5590 else if (TARGET_ABICALLS)
5592 /* Add the context-pointer to the saved registers. */
5593 gp_reg_size += UNITS_PER_WORD;
5594 mask |= 1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST);
5595 total_size -= gp_reg_rounded;
5596 gp_reg_rounded = MIPS_STACK_ALIGN (gp_reg_size);
5597 total_size += gp_reg_rounded;
5600 /* Add in space reserved on the stack by the callee for storing arguments
5601 passed in registers. */
5602 if (mips_abi != ABI_32)
5603 total_size += MIPS_STACK_ALIGN (current_function_pretend_args_size);
5605 /* The entry pseudo instruction will allocate 32 bytes on the stack. */
5606 if (mips_entry && total_size > 0 && total_size < 32)
5609 /* Save other computed information. */
5610 current_frame_info.total_size = total_size;
5611 current_frame_info.var_size = var_size;
5612 current_frame_info.args_size = args_size;
5613 current_frame_info.extra_size = extra_size;
5614 current_frame_info.gp_reg_size = gp_reg_size;
5615 current_frame_info.fp_reg_size = fp_reg_size;
5616 current_frame_info.mask = mask;
5617 current_frame_info.fmask = fmask;
5618 current_frame_info.initialized = reload_completed;
5619 current_frame_info.num_gp = gp_reg_size / UNITS_PER_WORD;
5620 current_frame_info.num_fp = fp_reg_size / (fp_inc * UNITS_PER_FPREG);
5624 unsigned long offset;
5626 /* When using mips_entry, the registers are always saved at the
5627 top of the stack. */
5629 offset = (args_size + extra_size + var_size
5630 + gp_reg_size - UNITS_PER_WORD);
5632 offset = total_size - UNITS_PER_WORD;
5633 current_frame_info.gp_sp_offset = offset;
5634 current_frame_info.gp_save_offset = offset - total_size;
5638 current_frame_info.gp_sp_offset = 0;
5639 current_frame_info.gp_save_offset = 0;
5645 unsigned long offset = (args_size + extra_size + var_size
5646 + gp_reg_rounded + fp_reg_size
5647 - fp_inc * UNITS_PER_FPREG);
5648 current_frame_info.fp_sp_offset = offset;
5649 current_frame_info.fp_save_offset = offset - total_size;
5653 current_frame_info.fp_sp_offset = 0;
5654 current_frame_info.fp_save_offset = 0;
5657 /* Ok, we're done. */
5662 /* Common code to emit the insns (or to write the instructions to a file)
5663 to save/restore registers.
5665 Other parts of the code assume that MIPS_TEMP1_REGNUM (aka large_reg)
5666 is not modified within save_restore_insns. */
5668 #define BITSET_P(value,bit) (((value) & (1L << (bit))) != 0)
5671 save_restore_insns (store_p, large_reg, large_offset, file)
5672 int store_p; /* true if this is prologue */
5673 rtx large_reg; /* register holding large offset constant or NULL */
5674 long large_offset; /* large constant offset value */
5675 FILE *file; /* file to write instructions to instead of making RTL */
5677 long mask = current_frame_info.mask;
5678 long fmask = current_frame_info.fmask;
5687 if (frame_pointer_needed && !BITSET_P (mask, HARD_FRAME_POINTER_REGNUM - GP_REG_FIRST))
5690 if (mask == 0 && fmask == 0)
5693 /* Save registers starting from high to low. The debuggers prefer
5694 at least the return register be stored at func+4, and also it
5695 allows us not to need a nop in the epilog if at least one
5696 register is reloaded in addition to return address. */
5698 /* Save GP registers if needed. */
5701 /* Pick which pointer to use as a base register. For small
5702 frames, just use the stack pointer. Otherwise, use a
5703 temporary register. Save 2 cycles if the save area is near
5704 the end of a large frame, by reusing the constant created in
5705 the prologue/epilogue to adjust the stack frame. */
5707 gp_offset = current_frame_info.gp_sp_offset;
5708 end_offset = gp_offset - (current_frame_info.gp_reg_size - UNITS_PER_WORD);
5710 if (gp_offset < 0 || end_offset < 0)
5711 fatal ("gp_offset (%ld) or end_offset (%ld) is less than zero.",
5712 gp_offset, end_offset);
5714 /* If we see a large frame in mips16 mode, we save the registers
5715 before adjusting the stack pointer, and load them afterward. */
5716 else if (TARGET_MIPS16 && large_offset > 32767)
5718 base_reg_rtx = stack_pointer_rtx;
5719 base_offset = large_offset;
5722 else if (gp_offset < 32768)
5724 base_reg_rtx = stack_pointer_rtx;
5728 else if (large_reg != (rtx)0
5729 && (((unsigned long)(large_offset - gp_offset)) < 32768)
5730 && (((unsigned long)(large_offset - end_offset)) < 32768))
5732 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5733 base_offset = large_offset;
5734 if (file == (FILE *)0)
5736 if (Pmode == DImode)
5737 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
5739 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
5741 RTX_FRAME_RELATED_P (insn) = 1;
5744 fprintf (file, "\t%s\t%s,%s,%s\n",
5745 Pmode == DImode ? "daddu" : "addu",
5746 reg_names[MIPS_TEMP2_REGNUM],
5747 reg_names[REGNO (large_reg)],
5748 reg_names[STACK_POINTER_REGNUM]);
5753 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5754 base_offset = gp_offset;
5755 if (file == (FILE *)0)
5757 rtx gp_offset_rtx = GEN_INT (gp_offset);
5759 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5760 bit, so make sure that we don't emit anything that can be
5762 /* ??? There is no DImode ori immediate pattern, so we can only
5763 do this for 32 bit code. */
5764 if (large_int (gp_offset_rtx)
5765 && GET_MODE (base_reg_rtx) == SImode)
5767 insn = emit_move_insn (base_reg_rtx,
5768 GEN_INT (gp_offset & 0xffff0000));
5770 RTX_FRAME_RELATED_P (insn) = 1;
5771 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
5772 GEN_INT (gp_offset & 0x0000ffff)));
5774 RTX_FRAME_RELATED_P (insn) = 1;
5778 insn = emit_move_insn (base_reg_rtx, gp_offset_rtx);
5780 RTX_FRAME_RELATED_P (insn) = 1;
5783 if (Pmode == DImode)
5784 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
5786 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
5788 RTX_FRAME_RELATED_P (insn) = 1;
5791 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
5792 reg_names[MIPS_TEMP2_REGNUM],
5795 Pmode == DImode ? "daddu" : "addu",
5796 reg_names[MIPS_TEMP2_REGNUM],
5797 reg_names[MIPS_TEMP2_REGNUM],
5798 reg_names[STACK_POINTER_REGNUM]);
5801 /* When we restore the registers in MIPS16 mode, then if we are
5802 using a frame pointer, and this is not a large frame, the
5803 current stack pointer will be offset by
5804 current_function_outgoing_args_size. Doing it this way lets
5805 us avoid offsetting the frame pointer before copying it into
5806 the stack pointer; there is no instruction to set the stack
5807 pointer to the sum of a register and a constant. */
5810 && frame_pointer_needed
5811 && large_offset <= 32767)
5812 base_offset += current_function_outgoing_args_size;
5814 for (regno = GP_REG_LAST; regno >= GP_REG_FIRST; regno--)
5816 if (BITSET_P (mask, regno - GP_REG_FIRST))
5818 if (file == (FILE *)0)
5821 rtx mem_rtx = gen_rtx (MEM, word_mode,
5822 gen_rtx (PLUS, Pmode, base_reg_rtx,
5823 GEN_INT (gp_offset - base_offset)));
5824 RTX_UNCHANGING_P (mem_rtx) = 1;
5826 /* The mips16 does not have an instruction to load
5827 $31, so we load $7 instead, and work things out
5829 if (TARGET_MIPS16 && ! store_p && regno == GP_REG_FIRST + 31)
5830 reg_rtx = gen_rtx (REG, word_mode, GP_REG_FIRST + 7);
5831 /* The mips16 sometimes needs to save $18. */
5832 else if (TARGET_MIPS16
5833 && regno != GP_REG_FIRST + 31
5834 && ! M16_REG_P (regno))
5837 reg_rtx = gen_rtx (REG, word_mode, 6);
5840 reg_rtx = gen_rtx (REG, word_mode, 3);
5841 emit_move_insn (reg_rtx,
5842 gen_rtx (REG, word_mode, regno));
5846 reg_rtx = gen_rtx (REG, word_mode, regno);
5849 insn = emit_move_insn (mem_rtx, reg_rtx);
5850 RTX_FRAME_RELATED_P (insn) = 1;
5852 else if (!TARGET_ABICALLS || mips_abi != ABI_32
5853 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5855 emit_move_insn (reg_rtx, mem_rtx);
5857 && regno != GP_REG_FIRST + 31
5858 && ! M16_REG_P (regno))
5859 emit_move_insn (gen_rtx (REG, word_mode, regno),
5865 if (store_p || !TARGET_ABICALLS || mips_abi != ABI_32
5866 || regno != (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
5870 /* The mips16 does not have an instruction to
5871 load $31, so we load $7 instead, and work
5872 things out in the caller. */
5873 if (TARGET_MIPS16 && ! store_p && r == GP_REG_FIRST + 31)
5874 r = GP_REG_FIRST + 7;
5875 /* The mips16 sometimes needs to save $18. */
5877 && regno != GP_REG_FIRST + 31
5878 && ! M16_REG_P (regno))
5881 r = GP_REG_FIRST + 6;
5884 r = GP_REG_FIRST + 3;
5885 fprintf (file, "\tmove\t%s,%s\n",
5886 reg_names[r], reg_names[regno]);
5889 fprintf (file, "\t%s\t%s,%ld(%s)\n",
5891 ? (store_p) ? "sd" : "ld"
5892 : (store_p) ? "sw" : "lw"),
5894 gp_offset - base_offset,
5895 reg_names[REGNO(base_reg_rtx)]);
5898 && regno != GP_REG_FIRST + 31
5899 && ! M16_REG_P (regno))
5900 fprintf (file, "\tmove\t%s,%s\n",
5901 reg_names[regno], reg_names[r]);
5905 gp_offset -= UNITS_PER_WORD;
5911 base_reg_rtx = (rtx)0; /* Make sure these are initialized */
5915 /* Save floating point registers if needed. */
5918 int fp_inc = (TARGET_FLOAT64 || TARGET_SINGLE_FLOAT) ? 1 : 2;
5919 int fp_size = fp_inc * UNITS_PER_FPREG;
5921 /* Pick which pointer to use as a base register. */
5922 fp_offset = current_frame_info.fp_sp_offset;
5923 end_offset = fp_offset - (current_frame_info.fp_reg_size - fp_size);
5925 if (fp_offset < 0 || end_offset < 0)
5926 fatal ("fp_offset (%ld) or end_offset (%ld) is less than zero.",
5927 fp_offset, end_offset);
5929 else if (fp_offset < 32768)
5931 base_reg_rtx = stack_pointer_rtx;
5935 else if (base_reg_rtx != (rtx)0
5936 && (((unsigned long)(base_offset - fp_offset)) < 32768)
5937 && (((unsigned long)(base_offset - end_offset)) < 32768))
5939 ; /* already set up for gp registers above */
5942 else if (large_reg != (rtx)0
5943 && (((unsigned long)(large_offset - fp_offset)) < 32768)
5944 && (((unsigned long)(large_offset - end_offset)) < 32768))
5946 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5947 base_offset = large_offset;
5948 if (file == (FILE *)0)
5950 if (Pmode == DImode)
5951 insn = emit_insn (gen_adddi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
5953 insn = emit_insn (gen_addsi3 (base_reg_rtx, large_reg, stack_pointer_rtx));
5955 RTX_FRAME_RELATED_P (insn) = 1;
5958 fprintf (file, "\t%s\t%s,%s,%s\n",
5959 Pmode == DImode ? "daddu" : "addu",
5960 reg_names[MIPS_TEMP2_REGNUM],
5961 reg_names[REGNO (large_reg)],
5962 reg_names[STACK_POINTER_REGNUM]);
5967 base_reg_rtx = gen_rtx (REG, Pmode, MIPS_TEMP2_REGNUM);
5968 base_offset = fp_offset;
5969 if (file == (FILE *)0)
5971 rtx fp_offset_rtx = GEN_INT (fp_offset);
5973 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
5974 bit, so make sure that we don't emit anything that can be
5976 /* ??? There is no DImode ori immediate pattern, so we can only
5977 do this for 32 bit code. */
5978 if (large_int (fp_offset_rtx)
5979 && GET_MODE (base_reg_rtx) == SImode)
5981 insn = emit_move_insn (base_reg_rtx,
5982 GEN_INT (fp_offset & 0xffff0000));
5984 RTX_FRAME_RELATED_P (insn) = 1;
5985 insn = emit_insn (gen_iorsi3 (base_reg_rtx, base_reg_rtx,
5986 GEN_INT (fp_offset & 0x0000ffff)));
5988 RTX_FRAME_RELATED_P (insn) = 1;
5992 insn = emit_move_insn (base_reg_rtx, fp_offset_rtx);
5994 RTX_FRAME_RELATED_P (insn) = 1;
5998 RTX_FRAME_RELATED_P (insn) = 1;
5999 if (Pmode == DImode)
6000 insn = emit_insn (gen_adddi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
6002 insn = emit_insn (gen_addsi3 (base_reg_rtx, base_reg_rtx, stack_pointer_rtx));
6004 RTX_FRAME_RELATED_P (insn) = 1;
6007 fprintf (file, "\tli\t%s,0x%.08lx\t# %ld\n\t%s\t%s,%s,%s\n",
6008 reg_names[MIPS_TEMP2_REGNUM],
6011 Pmode == DImode ? "daddu" : "addu",
6012 reg_names[MIPS_TEMP2_REGNUM],
6013 reg_names[MIPS_TEMP2_REGNUM],
6014 reg_names[STACK_POINTER_REGNUM]);
6017 for (regno = FP_REG_LAST-1; regno >= FP_REG_FIRST; regno -= fp_inc)
6019 if (BITSET_P (fmask, regno - FP_REG_FIRST))
6021 if (file == (FILE *)0)
6023 enum machine_mode sz =
6024 TARGET_SINGLE_FLOAT ? SFmode : DFmode;
6025 rtx reg_rtx = gen_rtx (REG, sz, regno);
6026 rtx mem_rtx = gen_rtx (MEM, sz,
6027 gen_rtx (PLUS, Pmode, base_reg_rtx,
6028 GEN_INT (fp_offset - base_offset)));
6029 RTX_UNCHANGING_P (mem_rtx) = 1;
6033 insn = emit_move_insn (mem_rtx, reg_rtx);
6034 RTX_FRAME_RELATED_P (insn) = 1;
6037 emit_move_insn (reg_rtx, mem_rtx);
6040 fprintf (file, "\t%s\t%s,%ld(%s)\n",
6041 (TARGET_SINGLE_FLOAT
6042 ? ((store_p) ? "s.s" : "l.s")
6043 : ((store_p) ? "s.d" : "l.d")),
6045 fp_offset - base_offset,
6046 reg_names[REGNO(base_reg_rtx)]);
6049 fp_offset -= fp_size;
6056 /* Set up the stack and frame (if desired) for the function. */
6059 function_prologue (file, size)
6063 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6066 long tsize = current_frame_info.total_size;
6068 ASM_OUTPUT_SOURCE_FILENAME (file, DECL_SOURCE_FILE (current_function_decl));
6070 #ifdef SDB_DEBUGGING_INFO
6071 if (debug_info_level != DINFO_LEVEL_TERSE && write_symbols == SDB_DEBUG)
6072 ASM_OUTPUT_SOURCE_LINE (file, DECL_SOURCE_LINE (current_function_decl));
6075 /* In mips16 mode, we may need to generate a 32 bit to handle
6076 floating point arguments. The linker will arrange for any 32 bit
6077 functions to call this stub, which will then jump to the 16 bit
6079 if (TARGET_MIPS16 && !TARGET_SOFT_FLOAT
6080 && current_function_args_info.fp_code != 0)
6081 build_mips16_function_stub (file);
6083 inside_function = 1;
6085 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6086 /* Get the function name the same way that toplev.c does before calling
6087 assemble_start_function. This is needed so that the name used here
6088 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6089 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6091 if (!flag_inhibit_size_directive)
6093 fputs ("\t.ent\t", file);
6094 assemble_name (file, fnname);
6098 assemble_name (file, fnname);
6099 fputs (":\n", file);
6102 if (!flag_inhibit_size_directive)
6104 fprintf (file, "\t.frame\t%s,%ld,%s\t\t# vars= %ld, regs= %d/%d, args= %d, extra= %ld\n",
6105 reg_names[ (frame_pointer_needed) ? HARD_FRAME_POINTER_REGNUM : STACK_POINTER_REGNUM ],
6107 reg_names[31 + GP_REG_FIRST],
6108 current_frame_info.var_size,
6109 current_frame_info.num_gp,
6110 current_frame_info.num_fp,
6111 current_function_outgoing_args_size,
6112 current_frame_info.extra_size);
6114 fprintf (file, "\t.mask\t0x%08lx,%ld\n\t.fmask\t0x%08lx,%ld\n",
6115 current_frame_info.mask,
6116 current_frame_info.gp_save_offset,
6117 current_frame_info.fmask,
6118 current_frame_info.fp_save_offset);
6121 if (mips_entry && ! mips_can_use_return_insn ())
6123 int save16 = BITSET_P (current_frame_info.mask, 16);
6124 int save17 = BITSET_P (current_frame_info.mask, 17);
6125 int save31 = BITSET_P (current_frame_info.mask, 31);
6129 /* Look through the initial insns to see if any of them store
6130 the function parameters into the incoming parameter storage
6131 area. If they do, we delete the insn, and save the register
6132 using the entry pseudo-instruction instead. We don't try to
6133 look past a label, jump, or call. */
6134 for (insn = get_insns (); insn != NULL_RTX; insn = NEXT_INSN (insn))
6136 rtx note, set, src, dest, base, offset;
6139 if (GET_CODE (insn) == CODE_LABEL
6140 || GET_CODE (insn) == JUMP_INSN
6141 || GET_CODE (insn) == CALL_INSN)
6143 if (GET_CODE (insn) != INSN)
6145 set = PATTERN (insn);
6146 if (GET_CODE (set) != SET)
6149 /* An insn storing a function parameter will still have a
6150 REG_EQUIV note on it mentioning the argument pointer. */
6151 note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
6152 if (note == NULL_RTX)
6154 if (! reg_mentioned_p (arg_pointer_rtx, XEXP (note, 0)))
6157 src = SET_SRC (set);
6158 if (GET_CODE (src) != REG
6159 || REGNO (src) < GP_REG_FIRST + 4
6160 || REGNO (src) > GP_REG_FIRST + 7)
6163 dest = SET_DEST (set);
6164 if (GET_CODE (dest) != MEM)
6166 if (GET_MODE_SIZE (GET_MODE (dest)) == UNITS_PER_WORD)
6168 else if (GET_MODE_SIZE (GET_MODE (dest)) == 2 * UNITS_PER_WORD
6169 && REGNO (src) < GP_REG_FIRST + 7)
6173 offset = const0_rtx;
6174 base = eliminate_constant_term (XEXP (dest, 0), &offset);
6175 if (GET_CODE (base) != REG
6176 || GET_CODE (offset) != CONST_INT)
6178 if (REGNO (base) == STACK_POINTER_REGNUM
6179 && INTVAL (offset) == tsize + (REGNO (src) - 4) * UNITS_PER_WORD)
6181 else if (REGNO (base) == HARD_FRAME_POINTER_REGNUM
6184 + (REGNO (src) - 4) * UNITS_PER_WORD
6185 - current_function_outgoing_args_size)))
6190 /* This insn stores a parameter onto the stack, in the same
6191 location where the entry pseudo-instruction will put it.
6192 Delete the insn, and arrange to tell the entry
6193 instruction to save the register. */
6194 PUT_CODE (insn, NOTE);
6195 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
6196 NOTE_SOURCE_FILE (insn) = 0;
6198 hireg = (REGNO (src)
6199 + HARD_REGNO_NREGS (REGNO (src), GET_MODE (dest))
6201 if (hireg > savearg)
6205 /* If this is a varargs function, we need to save all the
6206 registers onto the stack anyhow. */
6207 if (current_function_stdarg || current_function_varargs)
6208 savearg = GP_REG_FIRST + 7;
6210 fprintf (file, "\tentry\t");
6213 if (savearg == GP_REG_FIRST + 4)
6214 fprintf (file, "%s", reg_names[savearg]);
6216 fprintf (file, "%s-%s", reg_names[GP_REG_FIRST + 4],
6217 reg_names[savearg]);
6219 if (save16 || save17)
6222 fprintf (file, ",");
6223 fprintf (file, "%s", reg_names[GP_REG_FIRST + 16]);
6225 fprintf (file, "-%s", reg_names[GP_REG_FIRST + 17]);
6229 if (savearg > 0 || save16 || save17)
6230 fprintf (file, ",");
6231 fprintf (file, "%s", reg_names[GP_REG_FIRST + 31]);
6233 fprintf (file, "\n");
6236 if (TARGET_ABICALLS && mips_abi == ABI_32)
6238 char *sp_str = reg_names[STACK_POINTER_REGNUM];
6240 fprintf (file, "\t.set\tnoreorder\n\t.cpload\t%s\n\t.set\treorder\n",
6241 reg_names[PIC_FUNCTION_ADDR_REGNUM]);
6244 fprintf (file, "\t%s\t%s,%s,%ld\n",
6245 (Pmode == DImode ? "dsubu" : "subu"),
6246 sp_str, sp_str, tsize);
6247 fprintf (file, "\t.cprestore %ld\n", current_frame_info.args_size);
6250 if (dwarf2out_do_frame ())
6251 dwarf2out_def_cfa ("", STACK_POINTER_REGNUM, tsize);
6256 /* Expand the prologue into a bunch of separate insns. */
6259 mips_expand_prologue ()
6263 rtx tmp_rtx = (rtx)0;
6264 char *arg_name = (char *)0;
6265 tree fndecl = current_function_decl;
6266 tree fntype = TREE_TYPE (fndecl);
6267 tree fnargs = DECL_ARGUMENTS (fndecl);
6272 CUMULATIVE_ARGS args_so_far;
6273 rtx reg_18_save = NULL_RTX;
6275 /* If struct value address is treated as the first argument, make it so. */
6276 if (aggregate_value_p (DECL_RESULT (fndecl))
6277 && ! current_function_returns_pcc_struct
6278 && struct_value_incoming_rtx == 0)
6280 tree type = build_pointer_type (fntype);
6281 tree function_result_decl = build_decl (PARM_DECL, NULL_TREE, type);
6282 DECL_ARG_TYPE (function_result_decl) = type;
6283 TREE_CHAIN (function_result_decl) = fnargs;
6284 fnargs = function_result_decl;
6287 /* Determine the last argument, and get its name. */
6289 INIT_CUMULATIVE_ARGS (args_so_far, fntype, (rtx)0, 0);
6290 regno = GP_ARG_FIRST;
6292 for (cur_arg = fnargs; cur_arg != (tree)0; cur_arg = next_arg)
6294 tree passed_type = DECL_ARG_TYPE (cur_arg);
6295 enum machine_mode passed_mode = TYPE_MODE (passed_type);
6298 if (TREE_ADDRESSABLE (passed_type))
6300 passed_type = build_pointer_type (passed_type);
6301 passed_mode = Pmode;
6304 entry_parm = FUNCTION_ARG (args_so_far, passed_mode, passed_type, 1);
6310 /* passed in a register, so will get homed automatically */
6311 if (GET_MODE (entry_parm) == BLKmode)
6312 words = (int_size_in_bytes (passed_type) + 3) / 4;
6314 words = (GET_MODE_SIZE (GET_MODE (entry_parm)) + 3) / 4;
6316 regno = REGNO (entry_parm) + words - 1;
6320 regno = GP_ARG_LAST+1;
6324 FUNCTION_ARG_ADVANCE (args_so_far, passed_mode, passed_type, 1);
6326 next_arg = TREE_CHAIN (cur_arg);
6327 if (next_arg == (tree)0)
6329 if (DECL_NAME (cur_arg))
6330 arg_name = IDENTIFIER_POINTER (DECL_NAME (cur_arg));
6336 /* In order to pass small structures by value in registers
6337 compatibly with the MIPS compiler, we need to shift the value
6338 into the high part of the register. Function_arg has encoded a
6339 PARALLEL rtx, holding a vector of adjustments to be made as the
6340 next_arg_reg variable, so we split up the insns, and emit them
6343 next_arg_reg = FUNCTION_ARG (args_so_far, VOIDmode, void_type_node, 1);
6344 if (next_arg_reg != (rtx)0 && GET_CODE (next_arg_reg) == PARALLEL)
6346 rtvec adjust = XVEC (next_arg_reg, 0);
6347 int num = GET_NUM_ELEM (adjust);
6349 for (i = 0; i < num; i++)
6351 rtx pattern = RTVEC_ELT (adjust, i);
6352 if (GET_CODE (pattern) != SET
6353 || GET_CODE (SET_SRC (pattern)) != ASHIFT)
6354 abort_with_insn (pattern, "Insn is not a shift");
6356 PUT_CODE (SET_SRC (pattern), ASHIFTRT);
6357 emit_insn (pattern);
6361 tsize = compute_frame_size (get_frame_size ());
6363 /* If this function is a varargs function, store any registers that
6364 would normally hold arguments ($4 - $7) on the stack. */
6365 if (mips_abi == ABI_32
6366 && (! mips_entry || mips_can_use_return_insn ())
6367 && ((TYPE_ARG_TYPES (fntype) != 0
6368 && (TREE_VALUE (tree_last (TYPE_ARG_TYPES (fntype))) != void_type_node))
6369 || (arg_name != (char *)0
6370 && ((arg_name[0] == '_' && strcmp (arg_name, "__builtin_va_alist") == 0)
6371 || (arg_name[0] == 'v' && strcmp (arg_name, "va_alist") == 0)))))
6373 int offset = (regno - GP_ARG_FIRST) * UNITS_PER_WORD;
6374 rtx ptr = stack_pointer_rtx;
6376 /* If we are doing svr4-abi, sp has already been decremented by tsize. */
6377 if (TARGET_ABICALLS)
6380 for (; regno <= GP_ARG_LAST; regno++)
6383 ptr = gen_rtx (PLUS, Pmode, stack_pointer_rtx, GEN_INT (offset));
6384 emit_move_insn (gen_rtx (MEM, word_mode, ptr),
6385 gen_rtx (REG, word_mode, regno));
6386 offset += UNITS_PER_WORD;
6390 /* If we are using the entry pseudo instruction, it will
6391 automatically subtract 32 from the stack pointer, so we don't
6392 need to. The entry pseudo instruction is emitted by
6393 function_prologue. */
6394 if (mips_entry && ! mips_can_use_return_insn ())
6396 if (tsize > 0 && tsize <= 32 && frame_pointer_needed)
6400 /* If we are using a frame pointer with a small stack frame,
6401 we need to initialize it here since it won't be done
6403 if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6405 rtx incr = GEN_INT (current_function_outgoing_args_size);
6406 if (Pmode == DImode)
6407 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6411 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6415 else if (Pmode == DImode)
6416 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx, stack_pointer_rtx));
6418 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
6420 RTX_FRAME_RELATED_P (insn) = 1;
6423 /* We may need to save $18, if it is used to call a function
6424 which may return a floating point value. Set up a sequence
6425 of instructions to do so. Later on we emit them at the right
6427 if (TARGET_MIPS16 && BITSET_P (current_frame_info.mask, 18))
6429 rtx reg_rtx = gen_rtx (REG, word_mode, GP_REG_FIRST + 3);
6430 long gp_offset, base_offset;
6432 gp_offset = current_frame_info.gp_sp_offset;
6433 if (BITSET_P (current_frame_info.mask, 16))
6434 gp_offset -= UNITS_PER_WORD;
6435 if (BITSET_P (current_frame_info.mask, 17))
6436 gp_offset -= UNITS_PER_WORD;
6437 if (BITSET_P (current_frame_info.mask, 31))
6438 gp_offset -= UNITS_PER_WORD;
6440 base_offset = tsize;
6444 emit_move_insn (reg_rtx,
6445 gen_rtx (REG, word_mode, GP_REG_FIRST + 18));
6446 emit_move_insn (gen_rtx (MEM, word_mode,
6447 gen_rtx (PLUS, Pmode, stack_pointer_rtx,
6451 reg_18_save = gen_sequence ();
6460 if (reg_18_save != NULL_RTX)
6461 emit_insn (reg_18_save);
6467 rtx tsize_rtx = GEN_INT (tsize);
6469 /* If we are doing svr4-abi, sp move is done by
6470 function_prologue. In mips16 mode with a large frame, we
6471 save the registers before adjusting the stack. */
6472 if ((!TARGET_ABICALLS || mips_abi != ABI_32)
6473 && (!TARGET_MIPS16 || tsize <= 32767))
6479 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
6481 /* Instruction splitting doesn't preserve the RTX_FRAME_RELATED_P
6482 bit, so make sure that we don't emit anything that can be
6484 /* ??? There is no DImode ori immediate pattern, so we can only
6485 do this for 32 bit code. */
6486 if (large_int (tsize_rtx) && GET_MODE (tmp_rtx) == SImode)
6488 insn = emit_move_insn (tmp_rtx,
6489 GEN_INT (tsize & 0xffff0000));
6490 RTX_FRAME_RELATED_P (insn) = 1;
6491 insn = emit_insn (gen_iorsi3 (tmp_rtx, tmp_rtx,
6492 GEN_INT (tsize & 0x0000ffff)));
6493 RTX_FRAME_RELATED_P (insn) = 1;
6497 insn = emit_move_insn (tmp_rtx, tsize_rtx);
6498 RTX_FRAME_RELATED_P (insn) = 1;
6501 tsize_rtx = tmp_rtx;
6504 if (Pmode == DImode)
6505 insn = emit_insn (gen_subdi3 (stack_pointer_rtx, stack_pointer_rtx,
6508 insn = emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx,
6511 RTX_FRAME_RELATED_P (insn) = 1;
6515 save_restore_insns (TRUE, tmp_rtx, tsize, (FILE *)0);
6516 else if (reg_18_save != NULL_RTX)
6517 emit_insn (reg_18_save);
6519 if ((!TARGET_ABICALLS || mips_abi != ABI_32)
6525 if (!frame_pointer_needed)
6528 reg_rtx = gen_rtx (REG, Pmode, 3);
6529 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx);
6530 emit_move_insn (reg_rtx, tsize_rtx);
6531 if (Pmode == DImode)
6532 emit_insn (gen_subdi3 (hard_frame_pointer_rtx,
6533 hard_frame_pointer_rtx,
6536 emit_insn (gen_subsi3 (hard_frame_pointer_rtx,
6537 hard_frame_pointer_rtx,
6539 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx);
6542 if (frame_pointer_needed)
6546 /* On the mips16, we encourage the use of unextended
6547 instructions when using the frame pointer by pointing the
6548 frame pointer ahead of the argument space allocated on
6550 if ((! TARGET_ABICALLS || mips_abi != ABI_32)
6554 /* In this case, we have already copied the stack
6555 pointer into the frame pointer, above. We need only
6556 adjust for the outgoing argument size. */
6557 if (current_function_outgoing_args_size != 0)
6559 rtx incr = GEN_INT (current_function_outgoing_args_size);
6560 if (Pmode == DImode)
6561 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6562 hard_frame_pointer_rtx,
6565 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6566 hard_frame_pointer_rtx,
6570 else if (TARGET_MIPS16 && current_function_outgoing_args_size != 0)
6572 rtx incr = GEN_INT (current_function_outgoing_args_size);
6573 if (Pmode == DImode)
6574 insn = emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6578 insn = emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6582 else if (Pmode == DImode)
6583 insn = emit_insn (gen_movdi (hard_frame_pointer_rtx, stack_pointer_rtx));
6585 insn = emit_insn (gen_movsi (hard_frame_pointer_rtx, stack_pointer_rtx));
6588 RTX_FRAME_RELATED_P (insn) = 1;
6591 if (TARGET_ABICALLS && mips_abi != ABI_32)
6592 emit_insn (gen_loadgp (XEXP (DECL_RTL (current_function_decl), 0),
6593 gen_rtx (REG, DImode, 25)));
6596 /* If we are profiling, make sure no instructions are scheduled before
6597 the call to mcount. */
6599 if (profile_flag || profile_block_flag)
6600 emit_insn (gen_blockage ());
6604 /* Do any necessary cleanup after a function to restore stack, frame, and regs. */
6606 #define RA_MASK ((long) 0x80000000) /* 1 << 31 */
6607 #define PIC_OFFSET_TABLE_MASK (1 << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))
6610 function_epilogue (file, size)
6616 #ifndef FUNCTION_NAME_ALREADY_DECLARED
6617 /* Get the function name the same way that toplev.c does before calling
6618 assemble_start_function. This is needed so that the name used here
6619 exactly matches the name used in ASM_DECLARE_FUNCTION_NAME. */
6620 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
6622 if (!flag_inhibit_size_directive)
6624 fputs ("\t.end\t", file);
6625 assemble_name (file, fnname);
6632 int num_gp_regs = current_frame_info.gp_reg_size / 4;
6633 int num_fp_regs = current_frame_info.fp_reg_size / 8;
6634 int num_regs = num_gp_regs + num_fp_regs;
6635 char *name = fnname;
6640 dslots_load_total += num_regs;
6643 "%-20s fp=%c leaf=%c alloca=%c setjmp=%c stack=%4ld arg=%3ld reg=%2d/%d delay=%3d/%3dL %3d/%3dJ refs=%3d/%3d/%3d",
6645 (frame_pointer_needed) ? 'y' : 'n',
6646 ((current_frame_info.mask & RA_MASK) != 0) ? 'n' : 'y',
6647 (current_function_calls_alloca) ? 'y' : 'n',
6648 (current_function_calls_setjmp) ? 'y' : 'n',
6649 (long)current_frame_info.total_size,
6650 (long)current_function_outgoing_args_size,
6651 num_gp_regs, num_fp_regs,
6652 dslots_load_total, dslots_load_filled,
6653 dslots_jump_total, dslots_jump_filled,
6654 num_refs[0], num_refs[1], num_refs[2]);
6656 if (HALF_PIC_NUMBER_PTRS > prev_half_pic_ptrs)
6658 fprintf (stderr, " half-pic=%3d", HALF_PIC_NUMBER_PTRS - prev_half_pic_ptrs);
6659 prev_half_pic_ptrs = HALF_PIC_NUMBER_PTRS;
6662 if (HALF_PIC_NUMBER_REFS > prev_half_pic_refs)
6664 fprintf (stderr, " pic-ref=%3d", HALF_PIC_NUMBER_REFS - prev_half_pic_refs);
6665 prev_half_pic_refs = HALF_PIC_NUMBER_REFS;
6668 fputc ('\n', stderr);
6671 /* Reset state info for each function. */
6672 inside_function = FALSE;
6673 ignore_line_number = FALSE;
6674 dslots_load_total = 0;
6675 dslots_jump_total = 0;
6676 dslots_load_filled = 0;
6677 dslots_jump_filled = 0;
6681 mips_load_reg = (rtx)0;
6682 mips_load_reg2 = (rtx)0;
6683 current_frame_info = zero_frame_info;
6685 while (string_constants != NULL)
6687 struct string_constant *next;
6689 next = string_constants->next;
6690 free (string_constants);
6691 string_constants = next;
6694 /* Restore the output file if optimizing the GP (optimizing the GP causes
6695 the text to be diverted to a tempfile, so that data decls come before
6696 references to the data). */
6698 if (TARGET_GP_OPT && ! TARGET_MIPS16 && ! TARGET_GAS)
6699 asm_out_file = asm_out_data_file;
6703 /* Expand the epilogue into a bunch of separate insns. */
6706 mips_expand_epilogue ()
6708 long tsize = current_frame_info.total_size;
6709 rtx tsize_rtx = GEN_INT (tsize);
6710 rtx tmp_rtx = (rtx)0;
6712 if (mips_can_use_return_insn ())
6714 emit_insn (gen_return ());
6718 if (mips_entry && ! mips_can_use_return_insn ())
6721 if (tsize > 32767 && ! TARGET_MIPS16)
6723 tmp_rtx = gen_rtx (REG, Pmode, MIPS_TEMP1_REGNUM);
6724 emit_move_insn (tmp_rtx, tsize_rtx);
6725 tsize_rtx = tmp_rtx;
6730 long orig_tsize = tsize;
6732 if (frame_pointer_needed)
6734 emit_insn (gen_blockage ());
6736 /* On the mips16, the frame pointer is offset from the stack
6737 pointer by current_function_outgoing_args_size. We
6738 account for that by changing tsize. Note that this can
6739 actually make tsize negative. */
6742 tsize -= current_function_outgoing_args_size;
6744 /* If we have a large frame, it's easier to add to $17
6745 than to $sp, since the mips16 has no instruction to
6746 add a register to $sp. */
6747 if (orig_tsize > 32767)
6749 rtx g6_rtx = gen_rtx (REG, Pmode, GP_REG_FIRST + 6);
6751 emit_move_insn (g6_rtx, GEN_INT (tsize));
6752 if (Pmode == DImode)
6753 emit_insn (gen_adddi3 (hard_frame_pointer_rtx,
6754 hard_frame_pointer_rtx,
6757 emit_insn (gen_addsi3 (hard_frame_pointer_rtx,
6758 hard_frame_pointer_rtx,
6763 if (tsize && tsize != orig_tsize)
6764 tsize_rtx = GEN_INT (tsize);
6767 if (Pmode == DImode)
6768 emit_insn (gen_movdi (stack_pointer_rtx, hard_frame_pointer_rtx));
6770 emit_insn (gen_movsi (stack_pointer_rtx, hard_frame_pointer_rtx));
6772 /* The GP/PIC register is implicitly used by all SYMBOL_REFs, so if we
6773 are going to restore it, then we must emit a blockage insn to
6774 prevent the scheduler from moving the restore out of the epilogue. */
6775 else if (TARGET_ABICALLS && mips_abi != ABI_32
6776 && (current_frame_info.mask
6777 & (1L << (PIC_OFFSET_TABLE_REGNUM - GP_REG_FIRST))))
6778 emit_insn (gen_blockage ());
6780 save_restore_insns (FALSE, tmp_rtx, orig_tsize, (FILE *)0);
6782 /* In mips16 mode with a large frame, we adjust the stack
6783 pointer before restoring the registers. In this case, we
6784 should always be using a frame pointer, so everything should
6785 have been handled above. */
6786 if (tsize > 32767 && TARGET_MIPS16)
6789 emit_insn (gen_blockage ());
6790 if (Pmode == DImode && tsize != 0)
6791 emit_insn (gen_adddi3 (stack_pointer_rtx, stack_pointer_rtx,
6793 else if (tsize != 0)
6794 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx,
6798 /* The mips16 loads the return address into $7, not $31. */
6799 if (TARGET_MIPS16 && (current_frame_info.mask & RA_MASK) != 0)
6800 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6801 GP_REG_FIRST + 7)));
6803 emit_jump_insn (gen_return_internal (gen_rtx (REG, Pmode,
6804 GP_REG_FIRST + 31)));
6808 /* Return true if this function is known to have a null epilogue.
6809 This allows the optimizer to omit jumps to jumps if no stack
6813 mips_can_use_return_insn ()
6815 if (!reload_completed)
6818 if (regs_ever_live[31] || profile_flag)
6821 /* In mips16 mode, a function which returns a floating point value
6822 needs to arrange to copy the return value into the floating point
6825 && mips16_hard_float
6826 && ! aggregate_value_p (DECL_RESULT (current_function_decl))
6827 && (GET_MODE_CLASS (DECL_MODE (DECL_RESULT (current_function_decl)))
6829 && (! TARGET_SINGLE_FLOAT
6830 || (GET_MODE_SIZE (DECL_MODE (DECL_RESULT (current_function_decl)))
6834 if (current_frame_info.initialized)
6835 return current_frame_info.total_size == 0;
6837 return (compute_frame_size (get_frame_size ())) == 0;
6840 /* Choose the section to use for the constant rtx expression X that has
6844 mips_select_rtx_section (mode, x)
6845 enum machine_mode mode;
6850 /* In mips16 mode, the constant table always goes in the .text
6851 section, so that constants can be loaded using PC relative
6855 else if (TARGET_EMBEDDED_DATA)
6857 /* For embedded applications, always put constants in read-only data,
6858 in order to reduce RAM usage. */
6859 READONLY_DATA_SECTION ();
6863 /* For hosted applications, always put constants in small data if
6864 possible, as this gives the best performance. */
6866 if (GET_MODE_SIZE (mode) <= mips_section_threshold
6867 && mips_section_threshold > 0)
6868 SMALL_DATA_SECTION ();
6870 READONLY_DATA_SECTION ();
6874 /* Choose the section to use for DECL. RELOC is true if its value contains
6875 any relocatable expression. */
6878 mips_select_section (decl, reloc)
6882 int size = int_size_in_bytes (TREE_TYPE (decl));
6884 if ((TARGET_EMBEDDED_PIC || TARGET_MIPS16)
6885 && TREE_CODE (decl) == STRING_CST
6886 && !flag_writable_strings)
6888 /* For embedded position independent code, put constant strings
6889 in the text section, because the data section is limited to
6890 64K in size. For mips16 code, put strings in the text
6891 section so that a PC relative load instruction can be used to
6892 get their address. */
6896 else if (TARGET_EMBEDDED_DATA)
6898 /* For embedded applications, always put an object in read-only data
6899 if possible, in order to reduce RAM usage. */
6901 if (((TREE_CODE (decl) == VAR_DECL
6902 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
6903 && DECL_INITIAL (decl)
6904 && (DECL_INITIAL (decl) == error_mark_node
6905 || TREE_CONSTANT (DECL_INITIAL (decl))))
6906 /* Deal with calls from output_constant_def_contents. */
6907 || (TREE_CODE (decl) != VAR_DECL
6908 && (TREE_CODE (decl) != STRING_CST
6909 || !flag_writable_strings)))
6910 && ! (flag_pic && reloc))
6911 READONLY_DATA_SECTION ();
6912 else if (size > 0 && size <= mips_section_threshold)
6913 SMALL_DATA_SECTION ();
6919 /* For hosted applications, always put an object in small data if
6920 possible, as this gives the best performance. */
6922 if (size > 0 && size <= mips_section_threshold)
6923 SMALL_DATA_SECTION ();
6924 else if (((TREE_CODE (decl) == VAR_DECL
6925 && TREE_READONLY (decl) && !TREE_SIDE_EFFECTS (decl)
6926 && DECL_INITIAL (decl)
6927 && (DECL_INITIAL (decl) == error_mark_node
6928 || TREE_CONSTANT (DECL_INITIAL (decl))))
6929 /* Deal with calls from output_constant_def_contents. */
6930 || (TREE_CODE (decl) != VAR_DECL
6931 && (TREE_CODE (decl) != STRING_CST
6932 || !flag_writable_strings)))
6933 && ! (flag_pic && reloc))
6934 READONLY_DATA_SECTION ();
6940 #ifdef MIPS_ABI_DEFAULT
6941 /* Support functions for the 64 bit ABI. */
6943 /* Return register to use for a function return value with VALTYPE for function
6947 mips_function_value (valtype, func)
6951 int reg = GP_RETURN;
6952 enum machine_mode mode = TYPE_MODE (valtype);
6953 enum mode_class mclass = GET_MODE_CLASS (mode);
6954 int unsignedp = TREE_UNSIGNED (valtype);
6956 /* Since we define PROMOTE_FUNCTION_RETURN, we must promote the mode
6957 just as PROMOTE_MODE does. */
6958 mode = promote_mode (valtype, mode, &unsignedp, 1);
6960 /* ??? How should we return complex float? */
6961 if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT)
6963 if (TARGET_SINGLE_FLOAT
6964 && (mclass == MODE_FLOAT
6965 ? GET_MODE_SIZE (mode) > 4
6966 : GET_MODE_SIZE (mode) / 2 > 4))
6971 else if (TREE_CODE (valtype) == RECORD_TYPE
6972 && mips_abi != ABI_32 && mips_abi != ABI_EABI)
6974 /* A struct with only one or two floating point fields is returned in
6975 the floating point registers. */
6976 tree field, fields[2];
6979 for (i = 0, field = TYPE_FIELDS (valtype); field;
6980 field = TREE_CHAIN (field))
6982 if (TREE_CODE (field) != FIELD_DECL)
6984 if (TREE_CODE (TREE_TYPE (field)) != REAL_TYPE || i >= 2)
6987 fields[i++] = field;
6990 /* Must check i, so that we reject structures with no elements. */
6995 /* The structure has DImode, but we don't allow DImode values
6996 in FP registers, so we use a PARALLEL even though it isn't
6997 strictly necessary. */
6998 enum machine_mode field_mode = TYPE_MODE (TREE_TYPE (fields[0]));
7000 return gen_rtx (PARALLEL, mode,
7002 gen_rtx (EXPR_LIST, VOIDmode,
7003 gen_rtx (REG, field_mode, FP_RETURN),
7008 enum machine_mode first_mode
7009 = TYPE_MODE (TREE_TYPE (fields[0]));
7010 enum machine_mode second_mode
7011 = TYPE_MODE (TREE_TYPE (fields[1]));
7013 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[0]));
7015 = TREE_INT_CST_LOW (DECL_FIELD_BITPOS (fields[1]));
7017 return gen_rtx (PARALLEL, mode,
7019 gen_rtx (EXPR_LIST, VOIDmode,
7020 gen_rtx (REG, first_mode, FP_RETURN),
7021 GEN_INT (first_offset / BITS_PER_UNIT)),
7022 gen_rtx (EXPR_LIST, VOIDmode,
7023 gen_rtx (REG, second_mode, FP_RETURN + 2),
7024 GEN_INT (second_offset / BITS_PER_UNIT))));
7029 return gen_rtx (REG, mode, reg);
7032 /* The implementation of FUNCTION_ARG_PASS_BY_REFERENCE. Return
7033 nonzero when an argument must be passed by reference. */
7036 function_arg_pass_by_reference (cum, mode, type, named)
7037 CUMULATIVE_ARGS *cum;
7038 enum machine_mode mode;
7044 if (mips_abi != ABI_EABI)
7047 /* ??? How should SCmode be handled? */
7048 if (type == NULL_TREE || mode == DImode || mode == DFmode)
7051 size = int_size_in_bytes (type);
7052 return size == -1 || size > UNITS_PER_WORD;
7057 /* This function returns the register class required for a secondary
7058 register when copying between one of the registers in CLASS, and X,
7059 using MODE. If IN_P is nonzero, the copy is going from X to the
7060 register, otherwise the register is the source. A return value of
7061 NO_REGS means that no secondary register is required. */
7064 mips_secondary_reload_class (class, mode, x, in_p)
7065 enum reg_class class;
7066 enum machine_mode mode;
7070 enum reg_class gr_regs = TARGET_MIPS16 ? M16_REGS : GR_REGS;
7074 if (GET_CODE (x) == SIGN_EXTEND)
7080 /* We may be called with reg_renumber NULL from regclass.
7081 ??? This is probably a bug. */
7083 regno = true_regnum (x);
7086 while (GET_CODE (x) == SUBREG)
7088 off += SUBREG_WORD (x);
7091 if (GET_CODE (x) == REG)
7092 regno = REGNO (x) + off;
7095 else if (GET_CODE (x) == REG || GET_CODE (x) == SUBREG)
7096 regno = true_regnum (x);
7098 gp_reg_p = TARGET_MIPS16 ? M16_REG_P (regno) : GP_REG_P (regno);
7100 /* We always require a general register when copying anything to
7101 HILO_REGNUM, except when copying an SImode value from HILO_REGNUM
7102 to a general register, or when copying from register 0. */
7103 if (class == HILO_REG && regno != GP_REG_FIRST + 0)
7107 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7111 if (regno == HILO_REGNUM)
7115 && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (SImode))
7120 /* Copying from HI or LO to anywhere other than a general register
7121 requires a general register. */
7122 if (class == HI_REG || class == LO_REG || class == MD_REGS)
7124 if (TARGET_MIPS16 && in_p)
7126 /* We can't really copy to HI or LO at all in mips16 mode. */
7133 if (MD_REG_P (regno))
7135 if (TARGET_MIPS16 && ! in_p)
7137 /* We can't really copy to HI or LO at all in mips16 mode. */
7140 if (class == gr_regs)
7145 /* We can only copy a value to a condition code register from a
7146 floating point register, and even then we require a scratch
7147 floating point register. We can only copy a value out of a
7148 condition code register into a general register. */
7149 if (class == ST_REGS)
7153 if (GP_REG_P (regno))
7157 if (ST_REG_P (regno))
7161 if (class == GR_REGS)
7166 /* In mips16 mode, going between memory and anything but M16_REGS
7167 requires an M16_REG. */
7170 if (class != M16_REGS && class != M16_NA_REGS)
7178 if (class == M16_REGS || class == M16_NA_REGS)
7187 /* For each mips16 function which refers to GP relative symbols, we
7188 use a pseudo register, initialized at the start of the function, to
7189 hold the $gp value. */
7192 mips16_gp_pseudo_reg ()
7194 if (mips16_gp_pseudo_rtx == NULL_RTX)
7199 mips16_gp_pseudo_rtx = gen_reg_rtx (Pmode);
7200 RTX_UNCHANGING_P (mips16_gp_pseudo_rtx) = 1;
7202 /* We want to initialize this to a value which gcc will believe
7204 const_gp = gen_rtx (CONST, Pmode,
7205 gen_rtx (REG, Pmode, GP_REG_FIRST + 28));
7208 emit_move_insn (mips16_gp_pseudo_rtx, const_gp);
7209 insn = gen_sequence ();
7212 push_topmost_sequence ();
7213 /* We need to emit the initialization after the FUNCTION_BEG
7214 note, so that it will be integrated. */
7215 for (scan = get_insns (); scan != NULL_RTX; scan = NEXT_INSN (scan))
7216 if (GET_CODE (scan) == NOTE
7217 && NOTE_LINE_NUMBER (scan) == NOTE_INSN_FUNCTION_BEG)
7219 if (scan == NULL_RTX)
7220 scan = get_insns ();
7221 insn = emit_insn_after (insn, scan);
7222 pop_topmost_sequence ();
7225 return mips16_gp_pseudo_rtx;
7228 /* Return an RTX which represents the signed 16 bit offset from the
7229 $gp register for the given symbol. This is only used on the
7233 mips16_gp_offset (sym)
7238 if (GET_CODE (sym) != SYMBOL_REF
7239 || ! SYMBOL_REF_FLAG (sym))
7242 /* We use a special identifier to represent the value of the gp
7244 gp = get_identifier ("__mips16_gp_value");
7246 return gen_rtx (CONST, Pmode,
7247 gen_rtx (MINUS, Pmode, sym,
7248 gen_rtx (SYMBOL_REF, Pmode,
7249 IDENTIFIER_POINTER (gp))));
7252 /* Return nonzero if the given RTX represents a signed 16 bit offset
7253 from the $gp register. */
7256 mips16_gp_offset_p (x)
7259 if (GET_CODE (x) == CONST)
7262 /* It's OK to add a small integer value to a gp offset. */
7263 if (GET_CODE (x) == PLUS)
7265 if (GET_CODE (XEXP (x, 1)) == CONST_INT
7266 && SMALL_INT (XEXP (x, 1)))
7267 return mips16_gp_offset_p (XEXP (x, 0));
7268 if (GET_CODE (XEXP (x, 0)) == CONST_INT
7269 && SMALL_INT (XEXP (x, 0)))
7270 return mips16_gp_offset_p (XEXP (x, 1));
7274 /* Make sure it is in the form SYM - __mips16_gp_value. */
7275 return (GET_CODE (x) == MINUS
7276 && GET_CODE (XEXP (x, 0)) == SYMBOL_REF
7277 && SYMBOL_REF_FLAG (XEXP (x, 0))
7278 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7279 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0);
7282 /* Output a GP offset. We don't want to print the subtraction of
7283 __mips16_gp_value; it is implicitly represented by the %gprel which
7284 should have been printed by the caller. */
7287 mips16_output_gp_offset (file, x)
7291 if (GET_CODE (x) == CONST)
7294 if (GET_CODE (x) == PLUS)
7296 mips16_output_gp_offset (file, XEXP (x, 0));
7298 mips16_output_gp_offset (file, XEXP (x, 1));
7302 if (GET_CODE (x) == MINUS
7303 && GET_CODE (XEXP (x, 1)) == SYMBOL_REF
7304 && strcmp (XSTR (XEXP (x, 1), 0), "__mips16_gp_value") == 0)
7306 mips16_output_gp_offset (file, XEXP (x, 0));
7310 output_addr_const (file, x);
7313 /* Return nonzero if a constant should not be output until after the
7314 function. This is true of most string constants, so that we can
7315 use a more efficient PC relative reference. However, a static
7316 inline function may never call assemble_function_end to write out
7317 the constant pool, so don't try to postpone the constant in that
7320 ??? It's really a bug that a static inline function can put stuff
7321 in the constant pool even if the function itself is not output.
7323 We record which string constants we've seen, so that we know which
7324 ones might use the more efficient reference. */
7327 mips16_constant_after_function_p (x)
7330 if (TREE_CODE (x) == STRING_CST
7331 && ! flag_writable_strings
7332 && current_function_decl != 0
7333 && ! DECL_DEFER_OUTPUT (current_function_decl)
7334 && ! (DECL_INLINE (current_function_decl)
7335 && ((! TREE_PUBLIC (current_function_decl)
7336 && ! TREE_ADDRESSABLE (current_function_decl)
7337 && ! flag_keep_inline_functions)
7338 || DECL_EXTERNAL (current_function_decl))))
7340 struct string_constant *n;
7342 n = (struct string_constant *) xmalloc (sizeof *n);
7343 n->label = XSTR (XEXP (TREE_CST_RTL (x), 0), 0);
7344 n->next = string_constants;
7345 string_constants = n;
7353 /* Validate a constant for the mips16. This rejects general symbolic
7354 addresses, which must be loaded from memory. If ADDR is nonzero,
7355 this should reject anything which is not a legal address. If
7356 ADDEND is nonzero, this is being added to something else. */
7359 mips16_constant (x, mode, addr, addend)
7361 enum machine_mode mode;
7365 while (GET_CODE (x) == CONST)
7368 switch (GET_CODE (x))
7374 return (mips16_constant (XEXP (x, 0), mode, addr, 1)
7375 && mips16_constant (XEXP (x, 1), mode, addr, 1));
7378 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7380 if (CONSTANT_POOL_ADDRESS_P (x))
7383 /* If we aren't looking for a memory address, we can accept a GP
7384 relative symbol, which will have SYMBOL_REF_FLAG set; movsi
7385 knows how to handle this. We can always accept a string
7386 constant, which is the other case in which SYMBOL_REF_FLAG
7388 if (! addr && ! addend && SYMBOL_REF_FLAG (x) && mode == Pmode)
7391 /* We can accept a string constant, which will have
7392 SYMBOL_REF_FLAG set but must be recognized by name to
7393 distinguish from a GP accessible symbol. The name of a
7394 string constant will have been generated by
7395 ASM_GENERATE_INTERNAL_LABEL as called by output_constant_def. */
7396 if (SYMBOL_REF_FLAG (x))
7398 char *name = XSTR (x, 0);
7400 return (name[0] == '*'
7401 && strncmp (name + 1, LOCAL_LABEL_PREFIX,
7402 sizeof LOCAL_LABEL_PREFIX - 1) == 0);
7408 if (addr && GET_MODE_SIZE (mode) != 4 && GET_MODE_SIZE (mode) != 8)
7413 if (addr && ! addend)
7415 return INTVAL (x) > - 0x10000 && INTVAL (x) <= 0xffff;
7418 /* We need to treat $gp as a legitimate constant, because
7419 mips16_gp_pseudo_reg assumes that. */
7420 return REGNO (x) == GP_REG_FIRST + 28;
7424 /* Write out code to move floating point arguments in or out of
7425 general registers. Output the instructions to FILE. FP_CODE is
7426 the code describing which arguments are present (see the comment at
7427 the definition of CUMULATIVE_ARGS in mips.h). FROM_FP_P is non-zero if
7428 we are copying from the floating point registers. */
7431 mips16_fp_args (file, fp_code, from_fp_p)
7440 /* This code only works for the original 32 bit ABI. */
7441 if (mips_abi != ABI_32)
7448 gparg = GP_ARG_FIRST;
7449 fparg = FP_ARG_FIRST;
7450 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7454 if ((fparg & 1) != 0)
7456 fprintf (file, "\t%s\t%s,%s\n", s,
7457 reg_names[gparg], reg_names[fparg]);
7459 else if ((f & 3) == 2)
7462 fprintf (file, "\td%s\t%s,%s\n", s,
7463 reg_names[gparg], reg_names[fparg]);
7466 if ((fparg & 1) != 0)
7468 fprintf (file, "\t%s\t%s,%s\n\t%s\t%s,%s\n", s,
7469 reg_names[gparg], reg_names[fparg + 1], s,
7470 reg_names[gparg + 1], reg_names[fparg]);
7483 /* Build a mips16 function stub. This is used for functions which
7484 take aruments in the floating point registers. It is 32 bit code
7485 that moves the floating point args into the general registers, and
7486 then jumps to the 16 bit code. */
7489 build_mips16_function_stub (file)
7493 char *secname, *stubname;
7494 tree stubid, stubdecl;
7498 fnname = XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0);
7499 secname = (char *) alloca (strlen (fnname) + 20);
7500 sprintf (secname, ".mips16.fn.%s", fnname);
7501 stubname = (char *) alloca (strlen (fnname) + 20);
7502 sprintf (stubname, "__fn_stub_%s", fnname);
7503 stubid = get_identifier (stubname);
7504 stubdecl = build_decl (FUNCTION_DECL, stubid,
7505 build_function_type (void_type_node, NULL_TREE));
7506 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7508 fprintf (file, "\t# Stub function for %s (", current_function_name);
7510 for (f = (unsigned int) current_function_args_info.fp_code; f != 0; f >>= 2)
7512 fprintf (file, "%s%s",
7513 need_comma ? ", " : "",
7514 (f & 3) == 1 ? "float" : "double");
7517 fprintf (file, ")\n");
7519 fprintf (file, "\t.set\tnomips16\n");
7520 function_section (stubdecl);
7521 ASM_OUTPUT_ALIGN (file, floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT));
7523 /* ??? If FUNCTION_NAME_ALREADY_DECLARED is defined, then we are
7524 within a .ent, and we can not emit another .ent. */
7525 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7526 fputs ("\t.ent\t", file);
7527 assemble_name (file, stubname);
7531 assemble_name (file, stubname);
7532 fputs (":\n", file);
7534 /* We don't want the assembler to insert any nops here. */
7535 fprintf (file, "\t.set\tnoreorder\n");
7537 mips16_fp_args (file, current_function_args_info.fp_code, 1);
7539 fprintf (asm_out_file, "\t.set\tnoat\n");
7540 fprintf (asm_out_file, "\tla\t%s,", reg_names[GP_REG_FIRST + 1]);
7541 assemble_name (file, fnname);
7542 fprintf (file, "\n");
7543 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7544 fprintf (asm_out_file, "\t.set\tat\n");
7546 /* Unfortunately, we can't fill the jump delay slot. We can't fill
7547 with one of the mfc1 instructions, because the result is not
7548 available for one instruction, so if the very first instruction
7549 in the function refers to the register, it will see the wrong
7551 fprintf (file, "\tnop\n");
7553 fprintf (file, "\t.set\treorder\n");
7555 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7556 fputs ("\t.end\t", file);
7557 assemble_name (file, stubname);
7561 fprintf (file, "\t.set\tmips16\n");
7563 function_section (current_function_decl);
7566 /* We keep a list of functions for which we have already built stubs
7567 in build_mips16_call_stub. */
7571 struct mips16_stub *next;
7576 static struct mips16_stub *mips16_stubs;
7578 /* Build a call stub for a mips16 call. A stub is needed if we are
7579 passing any floating point values which should go into the floating
7580 point registers. If we are, and the call turns out to be to a 32
7581 bit function, the stub will be used to move the values into the
7582 floating point registers before calling the 32 bit function. The
7583 linker will magically adjust the function call to either the 16 bit
7584 function or the 32 bit stub, depending upon where the function call
7585 is actually defined.
7587 Similarly, we need a stub if the return value might come back in a
7588 floating point register.
7590 RETVAL, FNMEM, and ARG_SIZE are the values passed to the call insn
7591 (RETVAL is NULL if this is call rather than call_value). FP_CODE
7592 is the code built by function_arg. This function returns a nonzero
7593 value if it builds the call instruction itself. */
7596 build_mips16_call_stub (retval, fnmem, arg_size, fp_code)
7604 char *fnname, *secname, *stubname;
7605 struct mips16_stub *l;
7606 tree stubid, stubdecl;
7610 /* We don't need to do anything if we aren't in mips16 mode, or if
7611 we were invoked with the -msoft-float option. */
7612 if (! TARGET_MIPS16 || ! mips16_hard_float)
7615 /* Figure out whether the value might come back in a floating point
7617 fpret = (retval != 0
7618 && GET_MODE_CLASS (GET_MODE (retval)) == MODE_FLOAT
7619 && (! TARGET_SINGLE_FLOAT
7620 || GET_MODE_SIZE (GET_MODE (retval)) <= 4));
7622 /* We don't need to do anything if there were no floating point
7623 arguments and the value will not be returned in a floating point
7625 if (fp_code == 0 && ! fpret)
7628 if (GET_CODE (fnmem) != MEM)
7630 fn = XEXP (fnmem, 0);
7632 /* We don't need to do anything if this is a call to a special
7633 mips16 support function. */
7634 if (GET_CODE (fn) == SYMBOL_REF
7635 && strncmp (XSTR (fn, 0), "__mips16_", 9) == 0)
7638 /* This code will only work for the standard ABI. The other ABI's
7639 require more sophisticated support. */
7640 if (mips_abi != ABI_32)
7643 /* We can only handle SFmode and DFmode floating point return
7645 if (fpret && GET_MODE (retval) != SFmode && GET_MODE (retval) != DFmode)
7648 /* If we're calling via a function pointer, then we must always call
7649 via a stub. There are magic stubs provided in libgcc.a for each
7650 of the required cases. Each of them expects the function address
7651 to arrive in register $2. */
7653 if (GET_CODE (fn) != SYMBOL_REF)
7657 rtx stub_fn, stub_mem, insn;
7659 /* ??? If this code is modified to support other ABI's, we need
7660 to handle PARALLEL return values here. */
7662 sprintf (buf, "__mips16_call_stub_%s%d",
7664 ? (GET_MODE (retval) == SFmode ? "sf_" : "df_")
7667 id = get_identifier (buf);
7668 stub_fn = gen_rtx (SYMBOL_REF, Pmode, IDENTIFIER_POINTER (id));
7669 stub_mem = gen_rtx (MEM, Pmode, stub_fn);
7671 emit_move_insn (gen_rtx (REG, Pmode, 2), fn);
7673 if (retval == NULL_RTX)
7674 insn = gen_call_internal0 (stub_mem, arg_size,
7675 gen_rtx (REG, SImode,
7676 GP_REG_FIRST + 31));
7678 insn = gen_call_value_internal0 (retval, stub_mem, arg_size,
7679 gen_rtx (REG, SImode,
7680 GP_REG_FIRST + 31));
7681 insn = emit_call_insn (insn);
7683 /* Put the register usage information on the CALL. */
7684 if (GET_CODE (insn) != CALL_INSN)
7686 CALL_INSN_FUNCTION_USAGE (insn) =
7687 gen_rtx (EXPR_LIST, VOIDmode,
7688 gen_rtx (USE, VOIDmode, gen_rtx (REG, Pmode, 2)),
7689 CALL_INSN_FUNCTION_USAGE (insn));
7691 /* If we are handling a floating point return value, we need to
7692 save $18 in the function prologue. Putting a note on the
7693 call will mean that regs_ever_live[$18] will be true if the
7694 call is not eliminated, and we can check that in the prologue
7697 CALL_INSN_FUNCTION_USAGE (insn) =
7698 gen_rtx (EXPR_LIST, VOIDmode,
7699 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7700 CALL_INSN_FUNCTION_USAGE (insn));
7702 /* Return 1 to tell the caller that we've generated the call
7707 /* We know the function we are going to call. If we have already
7708 built a stub, we don't need to do anything further. */
7710 fnname = XSTR (fn, 0);
7711 for (l = mips16_stubs; l != NULL; l = l->next)
7712 if (strcmp (l->name, fnname) == 0)
7717 /* Build a special purpose stub. When the linker sees a
7718 function call in mips16 code, it will check where the target
7719 is defined. If the target is a 32 bit call, the linker will
7720 search for the section defined here. It can tell which
7721 symbol this section is associated with by looking at the
7722 relocation information (the name is unreliable, since this
7723 might be a static function). If such a section is found, the
7724 linker will redirect the call to the start of the magic
7727 If the function does not return a floating point value, the
7728 special stub section is named
7731 If the function does return a floating point value, the stub
7733 .mips16.call.fp.FNNAME
7736 secname = (char *) alloca (strlen (fnname) + 40);
7737 sprintf (secname, ".mips16.call.%s%s",
7740 stubname = (char *) alloca (strlen (fnname) + 20);
7741 sprintf (stubname, "__call_stub_%s%s",
7744 stubid = get_identifier (stubname);
7745 stubdecl = build_decl (FUNCTION_DECL, stubid,
7746 build_function_type (void_type_node, NULL_TREE));
7747 DECL_SECTION_NAME (stubdecl) = build_string (strlen (secname), secname);
7749 fprintf (asm_out_file, "\t# Stub function to call %s%s (",
7751 ? (GET_MODE (retval) == SFmode ? "float " : "double ")
7755 for (f = (unsigned int) fp_code; f != 0; f >>= 2)
7757 fprintf (asm_out_file, "%s%s",
7758 need_comma ? ", " : "",
7759 (f & 3) == 1 ? "float" : "double");
7762 fprintf (asm_out_file, ")\n");
7764 fprintf (asm_out_file, "\t.set\tnomips16\n");
7765 assemble_start_function (stubdecl, stubname);
7767 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7768 fputs ("\t.ent\t", asm_out_file);
7769 assemble_name (asm_out_file, stubname);
7770 fputs ("\n", asm_out_file);
7772 assemble_name (asm_out_file, stubname);
7773 fputs (":\n", asm_out_file);
7776 /* We build the stub code by hand. That's the only way we can
7777 do it, since we can't generate 32 bit code during a 16 bit
7780 /* We don't want the assembler to insert any nops here. */
7781 fprintf (asm_out_file, "\t.set\tnoreorder\n");
7783 mips16_fp_args (asm_out_file, fp_code, 0);
7787 fprintf (asm_out_file, "\t.set\tnoat\n");
7788 fprintf (asm_out_file, "\tla\t%s,%s\n", reg_names[GP_REG_FIRST + 1],
7790 fprintf (asm_out_file, "\tjr\t%s\n", reg_names[GP_REG_FIRST + 1]);
7791 fprintf (asm_out_file, "\t.set\tat\n");
7792 /* Unfortunately, we can't fill the jump delay slot. We
7793 can't fill with one of the mtc1 instructions, because the
7794 result is not available for one instruction, so if the
7795 very first instruction in the function refers to the
7796 register, it will see the wrong value. */
7797 fprintf (asm_out_file, "\tnop\n");
7801 fprintf (asm_out_file, "\tmove\t%s,%s\n",
7802 reg_names[GP_REG_FIRST + 18], reg_names[GP_REG_FIRST + 31]);
7803 fprintf (asm_out_file, "\tjal\t%s\n", fnname);
7804 /* As above, we can't fill the delay slot. */
7805 fprintf (asm_out_file, "\tnop\n");
7806 if (GET_MODE (retval) == SFmode)
7807 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7808 reg_names[GP_REG_FIRST + 2], reg_names[FP_REG_FIRST + 0]);
7811 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7812 reg_names[GP_REG_FIRST + 2],
7813 reg_names[FP_REG_FIRST + 1]);
7814 fprintf (asm_out_file, "\tmfc1\t%s,%s\n",
7815 reg_names[GP_REG_FIRST + 3],
7816 reg_names[FP_REG_FIRST + 0]);
7818 fprintf (asm_out_file, "\tj\t%s\n", reg_names[GP_REG_FIRST + 18]);
7819 /* As above, we can't fill the delay slot. */
7820 fprintf (asm_out_file, "\tnop\n");
7823 fprintf (asm_out_file, "\t.set\treorder\n");
7825 #ifdef ASM_DECLARE_FUNCTION_SIZE
7826 ASM_DECLARE_FUNCTION_SIZE (asm_out_file, stubname, stubdecl);
7829 #ifndef FUNCTION_NAME_ALREADY_DECLARED
7830 fputs ("\t.end\t", asm_out_file);
7831 assemble_name (asm_out_file, stubname);
7832 fputs ("\n", asm_out_file);
7835 fprintf (asm_out_file, "\t.set\tmips16\n");
7837 /* Record this stub. */
7838 l = (struct mips16_stub *) xmalloc (sizeof *l);
7839 l->name = (char *) xmalloc (strlen (fnname) + 1);
7840 strcpy (l->name, fnname);
7842 l->next = mips16_stubs;
7846 /* If we expect a floating point return value, but we've built a
7847 stub which does not expect one, then we're in trouble. We can't
7848 use the existing stub, because it won't handle the floating point
7849 value. We can't build a new stub, because the linker won't know
7850 which stub to use for the various calls in this object file.
7851 Fortunately, this case is illegal, since it means that a function
7852 was declared in two different ways in a single compilation. */
7853 if (fpret && ! l->fpret)
7854 error ("can not handle inconsistent calls to `%s'", fnname);
7856 /* If we are calling a stub which handles a floating point return
7857 value, we need to arrange to save $18 in the prologue. We do
7858 this by marking the function call as using the register. The
7859 prologue will later see that it is used, and emit code to save
7866 if (retval == NULL_RTX)
7867 insn = gen_call_internal0 (fnmem, arg_size,
7868 gen_rtx (REG, SImode,
7869 GP_REG_FIRST + 31));
7871 insn = gen_call_value_internal0 (retval, fnmem, arg_size,
7872 gen_rtx (REG, SImode,
7873 GP_REG_FIRST + 31));
7874 insn = emit_call_insn (insn);
7876 if (GET_CODE (insn) != CALL_INSN)
7879 CALL_INSN_FUNCTION_USAGE (insn) =
7880 gen_rtx (EXPR_LIST, VOIDmode,
7881 gen_rtx (USE, VOIDmode, gen_rtx (REG, word_mode, 18)),
7882 CALL_INSN_FUNCTION_USAGE (insn));
7884 /* Return 1 to tell the caller that we've generated the call
7889 /* Return 0 to let the caller generate the call insn. */
7893 /* This function looks through the code for a function, and tries to
7894 optimize the usage of the $gp register. We arrange to copy $gp
7895 into a pseudo-register, and then let gcc's normal reload handling
7896 deal with the pseudo-register. Unfortunately, if reload choose to
7897 put the pseudo-register into a call-clobbered register, it will
7898 emit saves and restores for that register around any function
7899 calls. We don't need the saves, and it's faster to copy $gp than
7900 to do an actual restore. ??? This still means that we waste a
7903 This is an optimization, and the code which gcc has actually
7904 generated is correct, so we do not need to catch all cases. */
7907 mips16_optimize_gp (first)
7910 rtx gpcopy, slot, insn;
7912 /* Look through the instructions. Set GPCOPY to the register which
7913 holds a copy of $gp. Set SLOT to the stack slot where it is
7914 saved. If we find an instruction which sets GPCOPY to anything
7915 other than $gp or SLOT, then we can't use it. If we find an
7916 instruction which sets SLOT to anything other than GPCOPY, we
7921 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
7925 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
7928 set = PATTERN (insn);
7930 /* We know that all references to memory will be inside a SET,
7931 because there is no other way to access memory on the mips16.
7932 We don't have to worry about a PARALLEL here, because the
7933 mips.md file will never generate them for memory references. */
7934 if (GET_CODE (set) != SET)
7937 if (gpcopy == NULL_RTX
7938 && GET_CODE (SET_SRC (set)) == CONST
7939 && GET_CODE (XEXP (SET_SRC (set), 0)) == REG
7940 && REGNO (XEXP (SET_SRC (set), 0)) == GP_REG_FIRST + 28
7941 && GET_CODE (SET_DEST (set)) == REG
7942 && GET_MODE (SET_DEST (set)) == Pmode)
7943 gpcopy = SET_DEST (set);
7944 else if (slot == NULL_RTX
7945 && gpcopy != NULL_RTX
7946 && GET_CODE (SET_DEST (set)) == MEM
7947 && GET_CODE (SET_SRC (set)) == REG
7948 && REGNO (SET_SRC (set)) == REGNO (gpcopy)
7949 && GET_MODE (SET_DEST (set)) == Pmode)
7953 offset = const0_rtx;
7954 base = eliminate_constant_term (XEXP (SET_DEST (set), 0), &offset);
7955 if (GET_CODE (base) == REG
7956 && (REGNO (base) == STACK_POINTER_REGNUM
7957 || REGNO (base) == FRAME_POINTER_REGNUM))
7958 slot = SET_DEST (set);
7960 else if (gpcopy != NULL_RTX
7961 && (GET_CODE (SET_DEST (set)) == REG
7962 || GET_CODE (SET_DEST (set)) == SUBREG)
7963 && reg_overlap_mentioned_p (SET_DEST (set), gpcopy)
7964 && (GET_CODE (SET_DEST (set)) != REG
7965 || REGNO (SET_DEST (set)) != REGNO (gpcopy)
7966 || GET_MODE (SET_DEST (set)) != Pmode
7967 || ((GET_CODE (SET_SRC (set)) != CONST
7968 || GET_CODE (XEXP (SET_SRC (set), 0)) != REG
7969 || (REGNO (XEXP (SET_SRC (set), 0))
7970 != GP_REG_FIRST + 28))
7971 && ! rtx_equal_p (SET_SRC (set), slot))))
7973 else if (slot != NULL_RTX
7974 && GET_CODE (SET_DEST (set)) == MEM
7975 && rtx_equal_p (SET_DEST (set), slot)
7976 && (GET_CODE (SET_SRC (set)) != REG
7977 || REGNO (SET_SRC (set)) != REGNO (gpcopy)))
7981 /* If we couldn't find a unique value for GPCOPY or SLOT, then try a
7982 different optimization. Any time we find a copy of $28 into a
7983 register, followed by an add of a symbol_ref to that register, we
7984 convert it to load the value from the constant table instead.
7985 The copy and add will take six bytes, just as the load and
7986 constant table entry will take six bytes. However, it is
7987 possible that the constant table entry will be shared.
7989 This could be a peephole optimization, but I don't know if the
7990 peephole code can call force_const_mem.
7992 Using the same register for the copy of $28 and the add of the
7993 symbol_ref is actually pretty likely, since the add instruction
7994 requires the destination and the first addend to be the same
7997 if (insn != NULL_RTX || gpcopy == NULL_RTX || slot == NULL_RTX)
8001 /* This optimization is only reasonable if the constant table
8002 entries are only 4 bytes. */
8003 if (Pmode != SImode)
8006 for (insn = first; insn != NULL_RTX; insn = next)
8013 next = NEXT_INSN (next);
8015 while (next != NULL_RTX
8016 && (GET_CODE (next) == NOTE
8017 || (GET_CODE (next) == INSN
8018 && (GET_CODE (PATTERN (next)) == USE
8019 || GET_CODE (PATTERN (next)) == CLOBBER))));
8021 if (next == NULL_RTX)
8024 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8027 if (GET_RTX_CLASS (GET_CODE (next)) != 'i')
8030 set1 = PATTERN (insn);
8031 if (GET_CODE (set1) != SET)
8033 set2 = PATTERN (next);
8034 if (GET_CODE (set2) != SET)
8037 if (GET_CODE (SET_DEST (set1)) == REG
8038 && GET_CODE (SET_SRC (set1)) == CONST
8039 && GET_CODE (XEXP (SET_SRC (set1), 0)) == REG
8040 && REGNO (XEXP (SET_SRC (set1), 0)) == GP_REG_FIRST + 28
8041 && rtx_equal_p (SET_DEST (set1), SET_DEST (set2))
8042 && GET_CODE (SET_SRC (set2)) == PLUS
8043 && rtx_equal_p (SET_DEST (set1), XEXP (SET_SRC (set2), 0))
8044 && mips16_gp_offset_p (XEXP (SET_SRC (set2), 1))
8045 && GET_CODE (XEXP (XEXP (SET_SRC (set2), 1), 0)) == MINUS)
8049 /* We've found a case we can change to load from the
8052 sym = XEXP (XEXP (XEXP (SET_SRC (set2), 1), 0), 0);
8053 if (GET_CODE (sym) != SYMBOL_REF)
8055 emit_insn_after (gen_rtx (SET, VOIDmode, SET_DEST (set1),
8056 force_const_mem (Pmode, sym)),
8059 PUT_CODE (insn, NOTE);
8060 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8061 NOTE_SOURCE_FILE (insn) = 0;
8063 PUT_CODE (next, NOTE);
8064 NOTE_LINE_NUMBER (next) = NOTE_INSN_DELETED;
8065 NOTE_SOURCE_FILE (next) = 0;
8072 /* We can safely remove all assignments to SLOT from GPCOPY, and
8073 replace all assignments from SLOT to GPCOPY with assignments from
8076 for (insn = first; insn != NULL_RTX; insn = next_active_insn (insn))
8080 if (GET_RTX_CLASS (GET_CODE (insn)) != 'i')
8083 set = PATTERN (insn);
8084 if (GET_CODE (set) != SET
8085 || GET_MODE (SET_DEST (set)) != Pmode)
8088 if (GET_CODE (SET_DEST (set)) == MEM
8089 && rtx_equal_p (SET_DEST (set), slot)
8090 && GET_CODE (SET_SRC (set)) == REG
8091 && REGNO (SET_SRC (set)) == REGNO (gpcopy))
8093 PUT_CODE (insn, NOTE);
8094 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8095 NOTE_SOURCE_FILE (insn) = 0;
8097 else if (GET_CODE (SET_DEST (set)) == REG
8098 && REGNO (SET_DEST (set)) == REGNO (gpcopy)
8099 && GET_CODE (SET_SRC (set)) == MEM
8100 && rtx_equal_p (SET_SRC (set), slot))
8102 emit_insn_after (gen_rtx (SET, Pmode, SET_DEST (set),
8103 gen_rtx (CONST, Pmode,
8104 gen_rtx (REG, Pmode,
8105 GP_REG_FIRST + 28))),
8107 PUT_CODE (insn, NOTE);
8108 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8109 NOTE_SOURCE_FILE (insn) = 0;
8114 /* We keep a list of constants we which we have to add to internal
8115 constant tables in the middle of large functions. */
8119 struct constant *next;
8122 enum machine_mode mode;
8125 /* Add a constant to the list in *PCONSTANTS. */
8128 add_constant (pconstants, val, mode)
8129 struct constant **pconstants;
8131 enum machine_mode mode;
8135 for (c = *pconstants; c != NULL; c = c->next)
8136 if (mode == c->mode && rtx_equal_p (val, c->value))
8139 c = (struct constant *) xmalloc (sizeof *c);
8142 c->label = gen_label_rtx ();
8143 c->next = *pconstants;
8148 /* Dump out the constants in CONSTANTS after INSN. */
8151 dump_constants (constants, insn)
8152 struct constant *constants;
8163 struct constant *next;
8165 switch (GET_MODE_SIZE (c->mode))
8172 insn = emit_insn_after (gen_align_2 (), insn);
8177 insn = emit_insn_after (gen_align_4 (), insn);
8182 insn = emit_insn_after (gen_align_8 (), insn);
8187 insn = emit_label_after (c->label, insn);
8192 r = gen_consttable_qi (c->value);
8195 r = gen_consttable_hi (c->value);
8198 r = gen_consttable_si (c->value);
8201 r = gen_consttable_sf (c->value);
8204 r = gen_consttable_di (c->value);
8207 r = gen_consttable_df (c->value);
8213 insn = emit_insn_after (r, insn);
8220 emit_barrier_after (insn);
8223 /* Find the symbol in an address expression. */
8226 mips_find_symbol (addr)
8229 if (GET_CODE (addr) == MEM)
8230 addr = XEXP (addr, 0);
8231 while (GET_CODE (addr) == CONST)
8232 addr = XEXP (addr, 0);
8233 if (GET_CODE (addr) == SYMBOL_REF || GET_CODE (addr) == LABEL_REF)
8235 if (GET_CODE (addr) == PLUS)
8239 l1 = mips_find_symbol (XEXP (addr, 0));
8240 l2 = mips_find_symbol (XEXP (addr, 1));
8241 if (l1 != NULL_RTX && l2 == NULL_RTX)
8243 else if (l1 == NULL_RTX && l2 != NULL_RTX)
8249 /* Exported to toplev.c.
8251 Do a final pass over the function, just before delayed branch
8255 machine_dependent_reorg (first)
8258 int insns_len, max_internal_pool_size, pool_size, addr;
8260 struct constant *constants;
8262 if (! TARGET_MIPS16)
8265 /* If $gp is used, try to remove stores, and replace loads with
8268 mips16_optimize_gp (first);
8270 /* Scan the function looking for PC relative loads which may be out
8271 of range. All such loads will either be from the constant table,
8272 or be getting the address of a constant string. If the size of
8273 the function plus the size of the constant table is less than
8274 0x8000, then all loads are in range. */
8277 for (insn = first; insn; insn = NEXT_INSN (insn))
8279 insns_len += get_attr_length (insn) * 2;
8281 /* ??? We put switch tables in .text, but we don't define
8282 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8283 compute their lengths correctly. */
8284 if (GET_CODE (insn) == JUMP_INSN)
8288 body = PATTERN (insn);
8289 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8290 insns_len += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8291 * GET_MODE_SIZE (GET_MODE (body)));
8292 insns_len += GET_MODE_SIZE (GET_MODE (body)) - 1;
8296 /* Store the original value of insns_len in current_frame_info, so
8297 that simple_memory_operand can look at it. */
8298 current_frame_info.insns_len = insns_len;
8300 pool_size = get_pool_size ();
8301 if (insns_len + pool_size + mips_string_length < 0x8000)
8304 /* Loop over the insns and figure out what the maximum internal pool
8306 max_internal_pool_size = 0;
8307 for (insn = first; insn; insn = NEXT_INSN (insn))
8309 if (GET_CODE (insn) == INSN
8310 && GET_CODE (PATTERN (insn)) == SET)
8314 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8315 if (src == NULL_RTX)
8317 if (CONSTANT_POOL_ADDRESS_P (src))
8318 max_internal_pool_size += GET_MODE_SIZE (get_pool_mode (src));
8319 else if (SYMBOL_REF_FLAG (src))
8320 max_internal_pool_size += GET_MODE_SIZE (Pmode);
8327 for (insn = first; insn; insn = NEXT_INSN (insn))
8329 if (GET_CODE (insn) == INSN
8330 && GET_CODE (PATTERN (insn)) == SET)
8333 enum machine_mode mode;
8336 src = mips_find_symbol (SET_SRC (PATTERN (insn)));
8337 if (src != NULL_RTX && CONSTANT_POOL_ADDRESS_P (src))
8339 /* ??? This is very conservative, which means that we
8340 will generate too many copies of the constant table.
8341 The only solution would seem to be some form of
8343 if (((insns_len - addr)
8344 + max_internal_pool_size
8345 + get_pool_offset (src))
8348 val = get_pool_constant (src);
8349 mode = get_pool_mode (src);
8351 max_internal_pool_size -= GET_MODE_SIZE (get_pool_mode (src));
8353 else if (src != NULL_RTX && SYMBOL_REF_FLAG (src))
8355 /* Including all of mips_string_length is conservative,
8356 and so is including all of max_internal_pool_size. */
8357 if (((insns_len - addr)
8358 + max_internal_pool_size
8360 + mips_string_length)
8364 max_internal_pool_size -= Pmode;
8367 if (val != NULL_RTX)
8371 /* This PC relative load is out of range. ??? In the
8372 case of a string constant, we are only guessing that
8373 it is range, since we don't know the offset of a
8374 particular string constant. */
8376 lab = add_constant (&constants, val, mode);
8377 newsrc = gen_rtx (MEM, mode,
8378 gen_rtx (LABEL_REF, VOIDmode, lab));
8379 RTX_UNCHANGING_P (newsrc) = 1;
8380 PATTERN (insn) = gen_rtx (SET, VOIDmode,
8381 SET_DEST (PATTERN (insn)),
8383 INSN_CODE (insn) = -1;
8387 addr += get_attr_length (insn) * 2;
8389 /* ??? We put switch tables in .text, but we don't define
8390 JUMP_TABLES_IN_TEXT_SECTION, so get_attr_length will not
8391 compute their lengths correctly. */
8392 if (GET_CODE (insn) == JUMP_INSN)
8396 body = PATTERN (insn);
8397 if (GET_CODE (body) == ADDR_VEC || GET_CODE (body) == ADDR_DIFF_VEC)
8398 addr += (XVECLEN (body, GET_CODE (body) == ADDR_DIFF_VEC)
8399 * GET_MODE_SIZE (GET_MODE (body)));
8400 addr += GET_MODE_SIZE (GET_MODE (body)) - 1;
8403 if (GET_CODE (insn) == BARRIER)
8405 /* Output any constants we have accumulated. Note that we
8406 don't need to change ADDR, since its only use is
8407 subtraction from INSNS_LEN, and both would be changed by
8409 ??? If the instructions up to the next barrier reuse a
8410 constant, it would often be better to continue
8412 if (constants != NULL)
8413 dump_constants (constants, insn);
8417 /* ??? If we don't find a barrier within 0x8000 bytes of
8418 instructions and constants in CONSTANTS, we need to invent
8419 one. This seems sufficiently unlikely that I am not going to
8423 if (constants != NULL)
8425 rtx label, jump, barrier;
8427 label = gen_label_rtx ();
8428 jump = emit_jump_insn_after (gen_jump (label), get_last_insn ());
8429 JUMP_LABEL (jump) = label;
8430 LABEL_NUSES (label) = 1;
8431 barrier = emit_barrier_after (jump);
8432 emit_label_after (label, barrier);
8433 dump_constants (constants, barrier);
8437 /* ??? If we output all references to a constant in internal
8438 constants table, we don't need to output the constant in the real
8439 constant table, but we have no way to prevent that. */