1 ;;- Machine description for GNU compiler, Motorola 68000 Version
2 ;; Copyright (C) 1987, 88, 93-97, 1998 Free Software Foundation, Inc.
4 ;; This file is part of GNU CC.
6 ;; GNU CC is free software; you can redistribute it and/or modify
7 ;; it under the terms of the GNU General Public License as published by
8 ;; the Free Software Foundation; either version 2, or (at your option)
11 ;; GNU CC is distributed in the hope that it will be useful,
12 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
13 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 ;; GNU General Public License for more details.
16 ;; You should have received a copy of the GNU General Public License
17 ;; along with GNU CC; see the file COPYING. If not, write to
18 ;; the Free Software Foundation, 59 Temple Place - Suite 330,
19 ;; Boston, MA 02111-1307, USA.
21 ;;- Information about MCF5200 port.
23 ;;- The MCF5200 "ColdFire" architecture is a reduced version of the
24 ;;- 68k ISA. Differences include reduced support for byte and word
25 ;;- operands and the removal of BCD, bitfield, rotate, and integer
26 ;;- divide instructions. The TARGET_5200 flag turns the use of the
27 ;;- removed opcodes and addressing modes off.
31 ;;- instruction definitions
33 ;;- @@The original PO technology requires these to be ordered by speed,
34 ;;- @@ so that assigner will pick the fastest.
36 ;;- See file "rtl.def" for documentation on define_insn, match_*, et. al.
38 ;;- When naming insn's (operand 0 of define_insn) be careful about using
39 ;;- names from other targets machine descriptions.
41 ;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code
42 ;;- updates for most instructions.
44 ;;- Operand classes for the register allocator:
45 ;;- 'a' one of the address registers can be used.
46 ;;- 'd' one of the data registers can be used.
47 ;;- 'f' one of the m68881 registers can be used
48 ;;- 'r' either a data or an address register can be used.
49 ;;- 'x' if one of the Sun FPA registers
50 ;;- 'y' if one of the Low Sun FPA registers (fpa0-fpa15).
52 ;;- Immediate Floating point operator constraints
53 ;;- 'G' a floating point constant that is *NOT* one of the standard
54 ;; 68881 constant values (to force calling output_move_const_double
55 ;; to get it from rom if it is a 68881 constant).
56 ;;- 'H' one of the standard FPA constant values
58 ;; See the functions standard_XXX_constant_p in output-m68k.c for more
61 ;;- Immediate integer operand constraints:
63 ;;- 'J' -32768 .. 32767
64 ;;- 'K' all integers EXCEPT -128 .. 127
66 ;;- 'M' all integers EXCEPT -256 .. 255
72 ;;- "%." size separator ("." or "") move%.l d0,d1
73 ;;- "%#" immediate separator ("#" or "") move%.l %#0,d0
74 ;;- "%-" push operand "sp@-" move%.l d0,%-
75 ;;- "%+" pop operand "sp@+" move%.l d0,%+
76 ;;- "%@" top of stack "sp@" move%.l d0,%@
77 ;;- "%!" fpcr register
78 ;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1
79 ;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1
82 ;; 1 This is a `sin' operation. The mode of the UNSPEC is MODE_FLOAT.
83 ;; operand 1 is the argument for `sin'.
84 ;; 2 This is a `cos' operation. The mode of the UNSPEC is MODE_FLOAT.
85 ;; operand 1 is the argument for `cos'.
87 ;;- Information about 68040 port.
89 ;;- The 68040 executes all 68030 and 68881/2 instructions, but some must
90 ;;- be emulated in software by the OS. It is faster to avoid these
91 ;;- instructions and issue a library call rather than trapping into
92 ;;- the kernel. The affected instructions are fintrz and fscale. The
93 ;;- TARGET_68040 flag turns the use of the opcodes off.
95 ;;- The '040 also implements a set of new floating-point instructions
96 ;;- which specify the rounding precision in the opcode. This finally
97 ;;- permit the 68k series to be truly IEEE compliant, and solves all
98 ;;- issues of excess precision accumulating in the extended registers.
99 ;;- By default, GCC does not use these instructions, since such code will
100 ;;- not run on an '030. To use these instructions, use the -m68040-only
101 ;;- switch. By changing TARGET_DEFAULT to include TARGET_68040_ONLY,
102 ;;- you can make these instructions the default.
104 ;;- These new instructions aren't directly in the md. They are brought
105 ;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather
108 ;;- Information about 68060 port.
110 ;;- The 68060 executes all 68030 and 68881/2 instructions, but some must
111 ;;- be emulated in software by the OS. It is faster to avoid these
112 ;;- instructions and issue a library call rather than trapping into
113 ;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq;
114 ;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and
115 ;;- fscale. The TARGET_68060 flag turns the use of the opcodes off.
117 ;;- FPA port explanation:
119 ;;- Usage of the Sun FPA and the 68881 together
121 ;;- The current port of gcc to the sun fpa disallows use of the m68881
122 ;;- instructions completely if code is targeted for the fpa. This is
123 ;;- for the following reasons:
125 ;;- 1) Expressing the preference hierarchy (ie. use the fpa if you
126 ;;- can, the 68881 otherwise, and data registers only if you are
127 ;;- forced to it) is a bitch with the current constraint scheme,
128 ;;- especially since it would have to work for any combination of
131 ;;- 2) There are no instructions to move between the two types of
132 ;;- registers; the stack must be used as an intermediary.
134 ;;- It could indeed be done; I think the best way would be to have
135 ;;- separate patterns for TARGET_FPA (which implies a 68881),
136 ;;- TARGET_68881, and no floating point co-processor. Use
137 ;;- define_expands for all of the named instruction patterns, and
138 ;;- include code in the FPA instruction to deal with the 68881 with
139 ;;- preferences specifically set to favor the fpa. Some of this has
140 ;;- already been done:
142 ;;- 1) Separation of most of the patterns out into a TARGET_FPA
143 ;;- case and a TARGET_68881 case (the exceptions are the patterns
144 ;;- which would need one define_expand and three define_insn's under
145 ;;- it (with a lot of duplicate code between them) to replace the
146 ;;- current single define_insn. These are mov{[ds]f,[ds]i} and the
147 ;;- first two patterns in the md.
149 ;;- Some would still have to be done:
151 ;;- 1) Add code to the fpa patterns which correspond to 68881
152 ;;- patterns to deal with the 68881 case (including preferences!).
153 ;;- What you might actually do here is combine the fpa and 68881 code
154 ;;- back together into one pattern for those instructions where it's
155 ;;- absolutely necessary and save yourself some duplicate code. I'm
156 ;;- not completely sure as to whether you could get away with doing
157 ;;- this only for the mov* insns, or if you'd have to do it for all
159 ;;- 2) Add code to the mov{[ds]f,[ds]i} instructions to handle
160 ;;- moving between fpa regs and 68881 regs.
162 ;;- Since the fpa is more powerful than the 68881 and also has more
163 ;;- registers, and since I think the resultant md would be medium ugly
164 ;;- (lot's of duplicate code, ugly constraint strings), I elected not
165 ;;- to do this change.
167 ;;- Another reason why someone *might* want to do the change is to
168 ;;- control which register classes are accessed in a slightly cleaner
169 ;;- way than I have. See the blurb on CONDITIONAL_REGISTER_USAGE in
170 ;;- the internals manual.
172 ;;- Yet another reason why someone might want to do this change is to
173 ;;- allow use of some of the 68881 insns which have no equivalent on
174 ;;- the fpa. The sqrt instruction comes fairly quickly to mind.
176 ;;- If this is ever done, don't forget to change sun3.h so that
177 ;;- it *will* define __HAVE_68881__ when the FPA is in use.
179 ;;- Condition code hack
181 ;;- When a floating point compare is done in the fpa, the resulting
182 ;;- condition codes are left in the fpastatus register. The values in
183 ;;- this register must be moved into the 68000 cc register before any
184 ;;- jump is executed. Once this has been done, regular jump
185 ;;- instructions are fine (ie. floating point jumps are not necessary.
186 ;;- They are only done if the cc is in the 68881).
188 ;;- The instructions that move the fpastatus register to the 68000
189 ;;- register clobber a data register (the move cannot be done direct).
190 ;;- These instructions might be bundled either with the compare
191 ;;- instruction, or the branch instruction. If we were using both the
192 ;;- fpa and the 68881 together, we would wish to only mark the
193 ;;- register clobbered if we were doing the compare in the fpa, but I
194 ;;- think that that decision (whether to clobber the register or not)
195 ;;- must be done before register allocation (makes sense) and hence we
196 ;;- can't know if the floating point compare will be done in the fpa
197 ;;- or the fp. So whenever we are asked for code that uses the fpa,
198 ;;- we will mark a data register as clobbered. This is reasonable, as
199 ;;- almost all floating point compare operations done with fpa code
200 ;;- enabled will be done in the fpa. It's even more reasonable since
201 ;;- we decided to make the 68881 and the fpa mutually exclusive.
203 ;;- We place to code to move the fpastatus register inside of a
204 ;;- define_expand so that we can do it conditionally based on whether
205 ;;- we are targeting an fpa or not.
207 ;;- This still leaves us with the question of where we wish to put the
208 ;;- code to move the fpastatus reg. If we put it in the compare
209 ;;- instruction, we can restrict the clobbering of the register to
210 ;;- floating point compares, but we can't take advantage of floating
211 ;;- point subtracts & etc. that alter the fpastatus register. If we
212 ;;- put it in the branch instruction, all branches compiled with fpa
213 ;;- code enabled will clobber a data register, but we will be able to
214 ;;- take advantage of fpa subtracts. This balance favors putting the
215 ;;- code in with the compare instruction.
217 ;;- Note that if some enterprising hacker should decide to switch
218 ;;- this, he'll need to modify the code in NOTICE_UPDATE_CC.
220 ;;- Usage of the top 16 fpa registers
222 ;;- The only locations which we may transfer fpa registers 16-31 from
223 ;;- or to are the fpa registers 0-15. (68000 registers and memory
224 ;;- locations are impossible). This causes problems in gcc, which
225 ;;- assumes that mov?? instructions require no additional registers
226 ;;- (see section 11.7) and since floating point moves *must* be
227 ;;- supported into general registers (see section 12.3 under
228 ;;- HARD_REGNO_OK_FOR_MODE_P) from anywhere.
230 ;;- My solution was to reserve fpa0 for moves into or out of these top
231 ;;- 16 registers and to disparage the choice to reload into or out of
232 ;;- these registers as much as I could. That alternative is always
233 ;;- last in the list, so it will not be used unless all else fails. I
234 ;;- will note that according to my current information, sun's compiler
235 ;;- doesn't use these top 16 registers at all.
237 ;;- There is another possible way to do it. I *believe* that if you
238 ;;- make absolutely sure that the code will not be executed in the
239 ;;- reload pass, you can support the mov?? names with define_expands
240 ;;- which require new registers. This may be possible by the
241 ;;- appropriate juggling of constraints. I may come back to this later.
243 ;;- Usage of constant RAM
245 ;;- This has been handled correctly (I believe) but the way I've done
246 ;;- it could use a little explanation. The constant RAM can only be
247 ;;- accessed when the instruction is in "command register" mode.
248 ;;- "command register" mode means that no accessing of memory or the
249 ;;- 68000 registers is being done. This can be expressed easily in
250 ;;- constraints, so generally the mode of the instruction is
251 ;;- determined by a branch off of which_alternative. In outputting
252 ;;- instructions, a 'w' means to output an access to the constant ram
253 ;;- (if the arg is CONST_DOUBLE and is one of the available
254 ;;- constants), and 'x' means to output a register pair (if the arg is
255 ;;- a 68000 register) and a 'y' is the combination of the above two
256 ;;- processes. You use a 'y' in two operand DF instructions where you
257 ;;- *know* the other operand is an fpa register, you use an 'x' in DF
258 ;;- instructions where the arg might be a 68000 register and the
259 ;;- instruction is *not* in "command register" mode, and you use a 'w'
260 ;;- in two situations: 1) The instruction *is* in command register
261 ;;- mode (and hence won't be accessing 68000 registers), or 2) The
262 ;;- instruction is a two operand SF instruction where you know the
263 ;;- other operand is an fpa register.
265 ;;- Optimization issues
267 ;;- I actually think that I've included all of the fpa instructions
268 ;;- that should be included. Note that if someone is interested in
269 ;;- doing serious floating point work on the sun fpa, I would advise
270 ;;- the use of the "asm" instruction in gcc to allow you to use the
271 ;;- sin, cos, and exponential functions on the fpa board.
273 ;;- END FPA Explanation Section.
276 ;;- Some of these insn's are composites of several m68000 op codes.
277 ;;- The assembler (or final @@??) insures that the appropriate one is
281 [(set (match_operand:DF 0 "push_operand" "=m")
282 (match_operand:DF 1 "general_operand" "ro<>fyE"))]
286 if (FP_REG_P (operands[1]))
287 return \"fmove%.d %f1,%0\";
288 if (FPA_REG_P (operands[1]))
289 return \"fpmove%.d %1, %x0\";
290 return output_move_double (operands);
293 (define_insn "pushdi"
294 [(set (match_operand:DI 0 "push_operand" "=m")
295 (match_operand:DI 1 "general_operand" "ro<>Fyi"))]
299 return output_move_double (operands);
302 ;; We don't want to allow a constant operand for test insns because
303 ;; (set (cc0) (const_int foo)) has no mode information. Such insns will
304 ;; be folded while optimizing anyway.
306 (define_expand "tstdi"
307 [(parallel [(set (cc0)
308 (match_operand:DI 0 "nonimmediate_operand" ""))
309 (clobber (match_scratch:SI 1 ""))
310 (clobber (match_scratch:DI 2 ""))])]
312 "m68k_last_compare_had_fp_operands = 0;")
316 (match_operand:DI 0 "nonimmediate_operand" "am,d"))
317 (clobber (match_scratch:SI 1 "=X,d"))
318 (clobber (match_scratch:DI 2 "=d,X"))]
322 if (which_alternative == 0)
326 xoperands[0] = operands[2];
327 xoperands[1] = operands[0];
328 output_move_double (xoperands);
329 cc_status.flags |= CC_REVERSED;
330 return \"neg%.l %R2\;negx%.l %2\";
332 if (find_reg_note (insn, REG_DEAD, operands[0]))
334 cc_status.flags |= CC_REVERSED;
335 return \"neg%.l %R0\;negx%.l %0\";
339 ** 'sub' clears %1, and also clears the X cc bit
340 ** 'tst' sets the Z cc bit according to the low part of the DImode operand
341 ** 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part
343 return \"sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0\";
346 (define_expand "tstsi"
348 (match_operand:SI 0 "nonimmediate_operand" ""))]
350 "m68k_last_compare_had_fp_operands = 0;")
354 (match_operand:SI 0 "nonimmediate_operand" "rm"))]
359 /* ISI's assembler fails to handle tstl a0. */
360 if (! ADDRESS_REG_P (operands[0]))
362 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
364 return \"tst%.l %0\";
365 /* If you think that the 68020 does not support tstl a0,
366 reread page B-167 of the 68020 manual more carefully. */
367 /* On an address reg, cmpw may replace cmpl. */
369 return \"cmp%.w %0,%#0\";
371 return \"cmp%.w %#0,%0\";
375 ;; This can't use an address register, because comparisons
376 ;; with address registers as second operand always test the whole word.
377 (define_expand "tsthi"
379 (match_operand:HI 0 "nonimmediate_operand" ""))]
381 "m68k_last_compare_had_fp_operands = 0;")
385 (match_operand:HI 0 "nonimmediate_operand" "dm"))]
389 (define_expand "tstqi"
391 (match_operand:QI 0 "nonimmediate_operand" ""))]
393 "m68k_last_compare_had_fp_operands = 0;")
397 (match_operand:QI 0 "nonimmediate_operand" "dm"))]
401 (define_expand "tstsf"
403 (match_operand:SF 0 "general_operand" ""))]
404 "TARGET_68881 || TARGET_FPA"
407 m68k_last_compare_had_fp_operands = 1;
410 emit_insn (gen_tstsf_fpa (operands[0]));
415 (define_insn "tstsf_fpa"
417 (match_operand:SF 0 "general_operand" "xmdF"))
418 (clobber (match_scratch:SI 1 "=d"))]
420 "fptst%.s %x0\;fpmove fpastatus,%1\;movw %1,cc")
424 (match_operand:SF 0 "general_operand" "fdm"))]
428 cc_status.flags = CC_IN_68881;
429 if (FP_REG_P (operands[0]))
430 return \"ftst%.x %0\";
431 return \"ftst%.s %0\";
434 (define_expand "tstdf"
436 (match_operand:DF 0 "general_operand" ""))]
437 "TARGET_68881 || TARGET_FPA"
440 m68k_last_compare_had_fp_operands = 1;
443 emit_insn (gen_tstsf_fpa (operands[0]));
448 (define_insn "tstdf_fpa"
450 (match_operand:DF 0 "general_operand" "xrmF"))
451 (clobber (match_scratch:SI 1 "=d"))]
453 "fptst%.d %x0\;fpmove fpastatus,%1\;movw %1,cc")
457 (match_operand:DF 0 "general_operand" "fm"))]
461 cc_status.flags = CC_IN_68881;
462 if (FP_REG_P (operands[0]))
463 return \"ftst%.x %0\";
464 return \"ftst%.d %0\";
467 ;; compare instructions.
469 (define_expand "cmpdi"
472 (compare (match_operand:DI 0 "nonimmediate_operand" "")
473 (match_operand:DI 1 "general_operand" "")))
474 (clobber (match_dup 2))])]
476 "m68k_last_compare_had_fp_operands = 0; operands[2] = gen_reg_rtx (DImode);")
480 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d")
481 (match_operand:DI 2 "general_operand" "d,0")))
482 (clobber (match_operand:DI 0 "register_operand" "=d,d"))]
486 if (rtx_equal_p (operands[0], operands[1]))
487 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
490 cc_status.flags |= CC_REVERSED;
491 return \"sub%.l %R1,%R0\;subx%.l %1,%0\";
495 ;; This is the second "hook" for PIC code (in addition to movsi). See
496 ;; comment of movsi for a description of PIC handling.
497 (define_expand "cmpsi"
499 (compare (match_operand:SI 0 "nonimmediate_operand" "")
500 (match_operand:SI 1 "general_operand" "")))]
504 m68k_last_compare_had_fp_operands = 0;
505 if (flag_pic && symbolic_operand (operands[1], SImode))
507 /* The source is an address which requires PIC relocation.
508 Call legitimize_pic_address with the source, mode, and a relocation
509 register (a new pseudo, or the final destination if reload_in_progress
510 is set). Then fall through normally */
511 extern rtx legitimize_pic_address();
512 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
513 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
517 ;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes.
520 (compare (match_operand:SI 0 "nonimmediate_operand" "rKs,mr,>")
521 (match_operand:SI 1 "general_operand" "mr,rKs,>")))]
525 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
527 return \"cmpm%.l %0,%1\";
529 return \"cmpm%.l %1,%0\";
531 if (REG_P (operands[1])
532 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
533 { cc_status.flags |= CC_REVERSED;
535 return \"cmp%.l %d1,%d0\";
537 return \"cmp%.l %d0,%d1\";
541 return \"cmp%.l %d0,%d1\";
543 return \"cmp%.l %d1,%d0\";
549 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r")
550 (match_operand:SI 1 "general_operand" "r,mrKs")))]
554 if (REG_P (operands[1])
555 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
556 { cc_status.flags |= CC_REVERSED;
558 return \"cmp%.l %d1,%d0\";
560 return \"cmp%.l %d0,%d1\";
564 return \"cmp%.l %d0,%d1\";
566 return \"cmp%.l %d1,%d0\";
570 (define_expand "cmphi"
572 (compare (match_operand:HI 0 "nonimmediate_operand" "")
573 (match_operand:HI 1 "general_operand" "")))]
575 "m68k_last_compare_had_fp_operands = 0;")
579 (compare (match_operand:HI 0 "nonimmediate_operand" "rnm,d,n,m,>")
580 (match_operand:HI 1 "general_operand" "d,rnm,m,n,>")))]
584 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
586 return \"cmpm%.w %0,%1\";
588 return \"cmpm%.w %1,%0\";
590 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1]))
591 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
592 { cc_status.flags |= CC_REVERSED;
594 return \"cmp%.w %d1,%d0\";
596 return \"cmp%.w %d0,%d1\";
600 return \"cmp%.w %d0,%d1\";
602 return \"cmp%.w %d1,%d0\";
606 (define_expand "cmpqi"
608 (compare (match_operand:QI 0 "nonimmediate_operand" "")
609 (match_operand:QI 1 "general_operand" "")))]
611 "m68k_last_compare_had_fp_operands = 0;")
615 (compare (match_operand:QI 0 "nonimmediate_operand" "dn,md,>")
616 (match_operand:QI 1 "general_operand" "dm,nd,>")))]
620 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM)
622 return \"cmpm%.b %0,%1\";
624 return \"cmpm%.b %1,%0\";
626 if (REG_P (operands[1])
627 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM))
628 { cc_status.flags |= CC_REVERSED;
630 return \"cmp%.b %d1,%d0\";
632 return \"cmp%.b %d0,%d1\";
636 return \"cmp%.b %d0,%d1\";
638 return \"cmp%.b %d1,%d0\";
642 (define_expand "cmpdf"
644 (compare (match_operand:DF 0 "general_operand" "")
645 (match_operand:DF 1 "general_operand" "")))]
646 "TARGET_68881 || TARGET_FPA"
649 m68k_last_compare_had_fp_operands = 1;
652 emit_insn (gen_cmpdf_fpa (operands[0], operands[1]));
657 (define_insn "cmpdf_fpa"
659 (compare (match_operand:DF 0 "general_operand" "x,y")
660 (match_operand:DF 1 "general_operand" "xH,rmF")))
661 (clobber (match_scratch:SI 2 "=d,d"))]
663 "fpcmp%.d %y1,%0\;fpmove fpastatus,%2\;movw %2,cc")
667 (compare (match_operand:DF 0 "general_operand" "f,mG")
668 (match_operand:DF 1 "general_operand" "fmG,f")))]
672 cc_status.flags = CC_IN_68881;
674 if (REG_P (operands[0]))
676 if (REG_P (operands[1]))
677 return \"fcmp%.x %0,%1\";
679 return \"fcmp%.d %0,%f1\";
681 cc_status.flags |= CC_REVERSED;
682 return \"fcmp%.d %1,%f0\";
684 if (REG_P (operands[0]))
686 if (REG_P (operands[1]))
687 return \"fcmp%.x %1,%0\";
689 return \"fcmp%.d %f1,%0\";
691 cc_status.flags |= CC_REVERSED;
692 return \"fcmp%.d %f0,%1\";
696 (define_expand "cmpsf"
698 (compare (match_operand:SF 0 "general_operand" "")
699 (match_operand:SF 1 "general_operand" "")))]
700 "TARGET_68881 || TARGET_FPA"
703 m68k_last_compare_had_fp_operands = 1;
706 emit_insn (gen_cmpsf_fpa (operands[0], operands[1]));
711 (define_insn "cmpsf_fpa"
713 (compare (match_operand:SF 0 "general_operand" "x,y")
714 (match_operand:SF 1 "general_operand" "xH,rmF")))
715 (clobber (match_scratch:SI 2 "=d,d"))]
717 "fpcmp%.s %w1,%x0\;fpmove fpastatus,%2\;movw %2,cc")
721 (compare (match_operand:SF 0 "general_operand" "f,mdG")
722 (match_operand:SF 1 "general_operand" "fmdG,f")))]
726 cc_status.flags = CC_IN_68881;
728 if (FP_REG_P (operands[0]))
730 if (FP_REG_P (operands[1]))
731 return \"fcmp%.x %0,%1\";
733 return \"fcmp%.s %0,%f1\";
735 cc_status.flags |= CC_REVERSED;
736 return \"fcmp%.s %1,%f0\";
738 if (FP_REG_P (operands[0]))
740 if (FP_REG_P (operands[1]))
741 return \"fcmp%.x %1,%0\";
743 return \"fcmp%.s %f1,%0\";
745 cc_status.flags |= CC_REVERSED;
746 return \"fcmp%.s %f0,%1\";
750 ;; Recognizers for btst instructions.
752 ;; Coldfire/5200 only allows "<Q>" type addresses when the bit position is
753 ;; specified as a constant, so we must disable all patterns that may extract
754 ;; from a MEM at a constant bit position if we can't use this as a constraint.
757 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
759 (minus:SI (const_int 7)
760 (match_operand:SI 1 "general_operand" "di"))))]
762 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
764 ;; This is the same as the above pattern except for the constraints. The 'i'
768 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
770 (minus:SI (const_int 7)
771 (match_operand:SI 1 "general_operand" "d"))))]
773 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
776 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
778 (minus:SI (const_int 31)
779 (match_operand:SI 1 "general_operand" "di"))))]
781 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
783 ;; The following two patterns are like the previous two
784 ;; except that they use the fact that bit-number operands
785 ;; are automatically masked to 3 or 5 bits.
788 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "o")
790 (minus:SI (const_int 7)
792 (match_operand:SI 1 "register_operand" "d")
795 "* { return output_btst (operands, operands[1], operands[0], insn, 7); }")
798 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "d")
800 (minus:SI (const_int 31)
802 (match_operand:SI 1 "register_operand" "d")
805 "* { return output_btst (operands, operands[1], operands[0], insn, 31); }")
807 ;; Nonoffsettable mem refs are ok in this one pattern
808 ;; since we don't try to adjust them.
810 [(set (cc0) (zero_extract (match_operand:QI 0 "memory_operand" "m")
812 (match_operand:SI 1 "const_int_operand" "n")))]
813 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_5200"
816 operands[1] = GEN_INT (7 - INTVAL (operands[1]));
817 return output_btst (operands, operands[1], operands[0], insn, 7);
821 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "do")
823 (match_operand:SI 1 "const_int_operand" "n")))]
827 if (GET_CODE (operands[0]) == MEM)
829 operands[0] = adj_offsettable_operand (operands[0],
830 INTVAL (operands[1]) / 8);
831 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
832 return output_btst (operands, operands[1], operands[0], insn, 7);
834 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
835 return output_btst (operands, operands[1], operands[0], insn, 31);
838 ;; This is the same as the above pattern except for the constraints.
839 ;; The 'o' has been replaced with 'Q'.
842 [(set (cc0) (zero_extract (match_operand:SI 0 "register_operand" "dQ")
844 (match_operand:SI 1 "const_int_operand" "n")))]
848 if (GET_CODE (operands[0]) == MEM)
850 operands[0] = adj_offsettable_operand (operands[0],
851 INTVAL (operands[1]) / 8);
852 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8);
853 return output_btst (operands, operands[1], operands[0], insn, 7);
855 operands[1] = GEN_INT (31 - INTVAL (operands[1]));
856 return output_btst (operands, operands[1], operands[0], insn, 31);
862 ;; A special case in which it is not desirable
863 ;; to reload the constant into a data register.
864 (define_insn "pushexthisi_const"
865 [(set (match_operand:SI 0 "push_operand" "=m")
866 (match_operand:SI 1 "const_int_operand" "J"))]
867 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000"
870 if (operands[1] == const0_rtx)
871 return \"clr%.l %0\";
876 ;(define_insn "swapsi"
877 ; [(set (match_operand:SI 0 "general_operand" "+r")
878 ; (match_operand:SI 1 "general_operand" "+r"))
879 ; (set (match_dup 1) (match_dup 0))]
883 ;; Special case of fullword move when source is zero.
884 ;; The reason this is special is to avoid loading a zero
885 ;; into a data reg with moveq in order to store it elsewhere.
887 (define_insn "movsi_const0"
888 [(set (match_operand:SI 0 "general_operand" "=g")
890 ;; clr insns on 68000 read before writing.
891 ;; This isn't so on the 68010, but we have no TARGET_68010.
892 "((TARGET_68020 || TARGET_5200)
893 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))"
896 if (ADDRESS_REG_P (operands[0]))
898 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
899 if (!TARGET_68040 && !TARGET_68060)
900 return \"sub%.l %0,%0\";
905 /* Many SGS assemblers croak on size specifiers for constants. */
908 return \"lea 0.w,%0\";
911 return \"lea 0:w,%0\";
915 /* moveq is faster on the 68000. */
916 if (DATA_REG_P (operands[0]) && (!TARGET_68020 && !TARGET_5200))
917 #if defined(MOTOROLA) && !defined(CRDS)
918 return \"moveq%.l %#0,%0\";
920 return \"moveq %#0,%0\";
922 return \"clr%.l %0\";
925 ;; General case of fullword move.
927 ;; This is the main "hook" for PIC code. When generating
928 ;; PIC, movsi is responsible for determining when the source address
929 ;; needs PIC relocation and appropriately calling legitimize_pic_address
930 ;; to perform the actual relocation.
932 ;; In both the PIC and non-PIC cases the patterns generated will
933 ;; matched by the next define_insn.
934 (define_expand "movsi"
935 [(set (match_operand:SI 0 "general_operand" "")
936 (match_operand:SI 1 "general_operand" ""))]
940 if (flag_pic && symbolic_operand (operands[1], SImode))
942 /* The source is an address which requires PIC relocation.
943 Call legitimize_pic_address with the source, mode, and a relocation
944 register (a new pseudo, or the final destination if reload_in_progress
945 is set). Then fall through normally */
946 extern rtx legitimize_pic_address();
947 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
948 operands[1] = legitimize_pic_address (operands[1], SImode, temp);
952 ;; General case of fullword move. The register constraints
953 ;; force integer constants in range for a moveq to be reloaded
954 ;; if they are headed for memory.
956 ;; Notes: make sure no alternative allows g vs g.
957 ;; We don't allow f-regs since fixed point cannot go in them.
958 ;; We do allow y and x regs since fixed point is allowed in them.
959 [(set (match_operand:SI 0 "general_operand" "=g,da,y,!*x*r*m")
960 (match_operand:SI 1 "general_operand" "daymKs,i,g,*x*r*m"))]
964 if (which_alternative == 3)
965 return \"fpmove%.l %x1,fpa0\;fpmove%.l fpa0,%x0\";
966 if (FPA_REG_P (operands[1]) || FPA_REG_P (operands[0]))
967 return \"fpmove%.l %x1,%x0\";
968 return output_move_simode (operands);
972 [(set (match_operand:SI 0 "general_operand" "=r<Q>,g")
973 (match_operand:SI 1 "general_operand" "g,r<Q>"))]
975 "* return output_move_simode (operands);")
977 (define_expand "movhi"
978 [(set (match_operand:HI 0 "general_operand" "")
979 (match_operand:HI 1 "general_operand" ""))]
984 [(set (match_operand:HI 0 "general_operand" "=g")
985 (match_operand:HI 1 "general_operand" "g"))]
987 "* return output_move_himode (operands);")
990 [(set (match_operand:HI 0 "general_operand" "=r<Q>,g")
991 (match_operand:HI 1 "general_operand" "g,r<Q>"))]
993 "* return output_move_himode (operands);")
995 (define_expand "movstricthi"
996 [(set (strict_low_part (match_operand:HI 0 "general_operand" ""))
997 (match_operand:HI 1 "general_operand" ""))]
1002 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
1003 (match_operand:HI 1 "general_operand" "rmn"))]
1005 "* return output_move_stricthi (operands);")
1008 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+d,m"))
1009 (match_operand:HI 1 "general_operand" "rmn,r"))]
1011 "* return output_move_stricthi (operands);")
1013 (define_expand "movqi"
1014 [(set (match_operand:QI 0 "general_operand" "")
1015 (match_operand:QI 1 "general_operand" ""))]
1020 [(set (match_operand:QI 0 "general_operand" "=d,*a,m")
1021 (match_operand:QI 1 "general_operand" "dmi*a,di*a,dmi"))]
1023 "* return output_move_qimode (operands);")
1026 [(set (match_operand:QI 0 "general_operand" "=d*a<Q>,d*am")
1027 (match_operand:QI 1 "general_operand" "d*ami,d*a<Q>"))]
1029 "* return output_move_qimode (operands);")
1031 (define_expand "movstrictqi"
1032 [(set (strict_low_part (match_operand:QI 0 "general_operand" ""))
1033 (match_operand:QI 1 "general_operand" ""))]
1038 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
1039 (match_operand:QI 1 "general_operand" "dmn"))]
1041 "* return output_move_strictqi (operands);")
1044 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+d,m"))
1045 (match_operand:QI 1 "general_operand" "dmn,d"))]
1047 "* return output_move_strictqi (operands);")
1049 (define_expand "movsf"
1050 [(set (match_operand:SF 0 "general_operand" "")
1051 (match_operand:SF 1 "general_operand" ""))]
1056 [(set (match_operand:SF 0 "general_operand" "=rmf,x,y,rm,!x,!rm")
1057 (match_operand:SF 1 "general_operand" "rmfF,xH,rmF,y,rm,x"))]
1058 ; [(set (match_operand:SF 0 "general_operand" "=rmf")
1059 ; (match_operand:SF 1 "general_operand" "rmfF"))]
1063 if (which_alternative >= 4)
1064 return \"fpmove%.s %1,fpa0\;fpmove%.s fpa0,%0\";
1065 if (FPA_REG_P (operands[0]))
1067 if (FPA_REG_P (operands[1]))
1068 return \"fpmove%.s %x1,%x0\";
1069 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1070 return output_move_const_single (operands);
1071 else if (FP_REG_P (operands[1]))
1072 return \"fmove%.s %1,sp@-\;fpmove%.d sp@+, %0\";
1073 return \"fpmove%.s %x1,%x0\";
1075 if (FPA_REG_P (operands[1]))
1077 if (FP_REG_P (operands[0]))
1078 return \"fpmove%.s %x1,sp@-\;fmove%.s sp@+,%0\";
1080 return \"fpmove%.s %x1,%x0\";
1082 if (FP_REG_P (operands[0]))
1084 if (FP_REG_P (operands[1]))
1085 return \"f%$move%.x %1,%0\";
1086 else if (ADDRESS_REG_P (operands[1]))
1087 return \"move%.l %1,%-\;f%$move%.s %+,%0\";
1088 else if (GET_CODE (operands[1]) == CONST_DOUBLE)
1089 return output_move_const_single (operands);
1090 return \"f%$move%.s %f1,%0\";
1092 if (FP_REG_P (operands[1]))
1094 if (ADDRESS_REG_P (operands[0]))
1095 return \"fmove%.s %1,%-\;move%.l %+,%0\";
1096 return \"fmove%.s %f1,%0\";
1098 if (operands[1] == CONST0_RTX (SFmode)
1099 /* clr insns on 68000 read before writing.
1100 This isn't so on the 68010, but we have no TARGET_68010. */
1101 && ((TARGET_68020 || TARGET_5200)
1102 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0]))))
1104 if (ADDRESS_REG_P (operands[0]))
1106 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */
1107 if (!TARGET_68040 && !TARGET_68060)
1108 return \"sub%.l %0,%0\";
1113 /* Many SGS assemblers croak on size specifiers for constants. */
1114 return \"lea 0,%0\";
1116 return \"lea 0.w,%0\";
1119 return \"lea 0:w,%0\";
1123 /* moveq is faster on the 68000. */
1124 if (DATA_REG_P (operands[0]) && !(TARGET_68020 || TARGET_5200))
1126 #if defined(MOTOROLA) && !defined(CRDS)
1127 return \"moveq%.l %#0,%0\";
1129 return \"moveq %#0,%0\";
1132 return \"clr%.l %0\";
1134 return \"move%.l %1,%0\";
1138 [(set (match_operand:SF 0 "general_operand" "=r,g")
1139 (match_operand:SF 1 "general_operand" "g,r"))]
1141 "* return \"move%.l %1,%0\";")
1143 (define_expand "movdf"
1144 [(set (match_operand:DF 0 "general_operand" "")
1145 (match_operand:DF 1 "general_operand" ""))]
1150 [(set (match_operand:DF 0 "general_operand" "=rm,rf,rf,&rof<>,y,rm,x,!x,!rm")
1151 (match_operand:DF 1 "general_operand" "rf,m,0,rofE<>,rmE,y,xH,rm,x"))]
1152 ; [(set (match_operand:DF 0 "general_operand" "=rm,&rf,&rof<>")
1153 ; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))]
1157 if (which_alternative == 7)
1158 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1159 if (FPA_REG_P (operands[0]))
1161 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1162 return output_move_const_double (operands);
1163 if (FP_REG_P (operands[1]))
1164 return \"fmove%.d %1,sp@-\;fpmove%.d sp@+,%x0\";
1165 return \"fpmove%.d %x1,%x0\";
1167 else if (FPA_REG_P (operands[1]))
1169 if (FP_REG_P(operands[0]))
1170 return \"fpmove%.d %x1,sp@-\;fmoved sp@+,%0\";
1172 return \"fpmove%.d %x1,%x0\";
1174 if (FP_REG_P (operands[0]))
1176 if (FP_REG_P (operands[1]))
1177 return \"f%&move%.x %1,%0\";
1178 if (REG_P (operands[1]))
1181 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1182 output_asm_insn (\"move%.l %1,%-\", xoperands);
1183 output_asm_insn (\"move%.l %1,%-\", operands);
1184 return \"f%&move%.d %+,%0\";
1186 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1187 return output_move_const_double (operands);
1188 return \"f%&move%.d %f1,%0\";
1190 else if (FP_REG_P (operands[1]))
1192 if (REG_P (operands[0]))
1194 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1195 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1196 return \"move%.l %+,%0\";
1199 return \"fmove%.d %f1,%0\";
1201 return output_move_double (operands);
1205 [(set (match_operand:DF 0 "general_operand" "=r,g")
1206 (match_operand:DF 1 "general_operand" "g,r"))]
1208 "* return output_move_double (operands);")
1210 (define_expand "movxf"
1211 [(set (match_operand:XF 0 "nonimmediate_operand" "")
1212 (match_operand:XF 1 "general_operand" ""))]
1216 if (CONSTANT_P (operands[1]))
1218 operands[1] = force_const_mem (XFmode, operands[1]);
1219 if (! memory_address_p (XFmode, XEXP (operands[1], 0))
1220 && ! reload_in_progress)
1221 operands[1] = change_address (operands[1], XFmode,
1222 XEXP (operands[1], 0));
1227 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f")
1228 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r"))]
1232 if (FP_REG_P (operands[0]))
1234 if (FP_REG_P (operands[1]))
1235 return \"fmove%.x %1,%0\";
1236 if (REG_P (operands[1]))
1239 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1240 output_asm_insn (\"move%.l %1,%-\", xoperands);
1241 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1242 output_asm_insn (\"move%.l %1,%-\", xoperands);
1243 output_asm_insn (\"move%.l %1,%-\", operands);
1244 return \"fmove%.x %+,%0\";
1246 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1247 return \"fmove%.x %1,%0\";
1248 return \"fmove%.x %f1,%0\";
1250 if (REG_P (operands[0]))
1252 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1253 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1254 output_asm_insn (\"move%.l %+,%0\", operands);
1255 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1256 return \"move%.l %+,%0\";
1258 return \"fmove%.x %f1,%0\";
1263 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
1264 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
1265 "! TARGET_68881 && ! TARGET_5200"
1268 if (FP_REG_P (operands[0]))
1270 if (FP_REG_P (operands[1]))
1271 return \"fmove%.x %1,%0\";
1272 if (REG_P (operands[1]))
1275 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2);
1276 output_asm_insn (\"move%.l %1,%-\", xoperands);
1277 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1278 output_asm_insn (\"move%.l %1,%-\", xoperands);
1279 output_asm_insn (\"move%.l %1,%-\", operands);
1280 return \"fmove%.x %+,%0\";
1282 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1283 return \"fmove%.x %1,%0\";
1284 return \"fmove%.x %f1,%0\";
1286 if (FP_REG_P (operands[1]))
1288 if (REG_P (operands[0]))
1290 output_asm_insn (\"fmove%.x %f1,%-\;move%.l %+,%0\", operands);
1291 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1292 output_asm_insn (\"move%.l %+,%0\", operands);
1293 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1294 return \"move%.l %+,%0\";
1297 return \"fmove%.x %f1,%0\";
1299 return output_move_double (operands);
1304 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
1305 (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
1306 "! TARGET_68881 && TARGET_5200"
1307 "* return output_move_double (operands);")
1309 (define_expand "movdi"
1310 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1311 [(set (match_operand:DI 0 "general_operand" "")
1312 (match_operand:DI 1 "general_operand" ""))]
1316 ;; movdi can apply to fp regs in some cases
1318 ;; Let's see if it really still needs to handle fp regs, and, if so, why.
1319 [(set (match_operand:DI 0 "general_operand" "=rm,r,&ro<>,y,rm,!*x,!rm")
1320 (match_operand:DI 1 "general_operand" "rF,m,roi<>F,rmiF,y,rmF,*x"))]
1321 ; [(set (match_operand:DI 0 "general_operand" "=rm,&r,&ro<>,!&rm,!&f,y,rm,x,!x,!rm")
1322 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfmF,rmi,y,rm,x"))]
1323 ; [(set (match_operand:DI 0 "general_operand" "=rm,&rf,&ro<>,!&rm,!&f")
1324 ; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))]
1328 if (which_alternative == 8)
1329 return \"fpmove%.d %x1,fpa0\;fpmove%.d fpa0,%x0\";
1330 if (FPA_REG_P (operands[0]) || FPA_REG_P (operands[1]))
1331 return \"fpmove%.d %x1,%x0\";
1332 if (FP_REG_P (operands[0]))
1334 if (FP_REG_P (operands[1]))
1335 return \"fmove%.x %1,%0\";
1336 if (REG_P (operands[1]))
1339 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
1340 output_asm_insn (\"move%.l %1,%-\", xoperands);
1341 output_asm_insn (\"move%.l %1,%-\", operands);
1342 return \"fmove%.d %+,%0\";
1344 if (GET_CODE (operands[1]) == CONST_DOUBLE)
1345 return output_move_const_double (operands);
1346 return \"fmove%.d %f1,%0\";
1348 else if (FP_REG_P (operands[1]))
1350 if (REG_P (operands[0]))
1352 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1353 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1354 return \"move%.l %+,%0\";
1357 return \"fmove%.d %f1,%0\";
1359 return output_move_double (operands);
1363 [(set (match_operand:DI 0 "general_operand" "=r,g")
1364 (match_operand:DI 1 "general_operand" "g,r"))]
1366 "* return output_move_double (operands);")
1368 ;; Thus goes after the move instructions
1369 ;; because the move instructions are better (require no spilling)
1370 ;; when they can apply. It goes before the add/sub insns
1371 ;; so we will prefer it to them.
1373 (define_insn "pushasi"
1374 [(set (match_operand:SI 0 "push_operand" "=m")
1375 (match_operand:SI 1 "address_operand" "p"))]
1379 ;; truncation instructions
1380 (define_insn "truncsiqi2"
1381 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1383 (match_operand:SI 1 "general_operand" "doJ,i")))]
1387 if (GET_CODE (operands[0]) == REG)
1389 /* Must clear condition codes, since the move.l bases them on
1390 the entire 32 bits, not just the desired 8 bits. */
1392 return \"move%.l %1,%0\";
1394 if (GET_CODE (operands[1]) == MEM)
1395 operands[1] = adj_offsettable_operand (operands[1], 3);
1396 return \"move%.b %1,%0\";
1399 (define_insn "trunchiqi2"
1400 [(set (match_operand:QI 0 "general_operand" "=dm,d")
1402 (match_operand:HI 1 "general_operand" "doJ,i")))]
1406 if (GET_CODE (operands[0]) == REG
1407 && (GET_CODE (operands[1]) == MEM
1408 || GET_CODE (operands[1]) == CONST_INT))
1410 /* Must clear condition codes, since the move.w bases them on
1411 the entire 16 bits, not just the desired 8 bits. */
1413 return \"move%.w %1,%0\";
1415 if (GET_CODE (operands[0]) == REG)
1417 /* Must clear condition codes, since the move.l bases them on
1418 the entire 32 bits, not just the desired 8 bits. */
1420 return \"move%.l %1,%0\";
1422 if (GET_CODE (operands[1]) == MEM)
1423 operands[1] = adj_offsettable_operand (operands[1], 1);
1424 return \"move%.b %1,%0\";
1427 (define_insn "truncsihi2"
1428 [(set (match_operand:HI 0 "general_operand" "=dm,d")
1430 (match_operand:SI 1 "general_operand" "roJ,i")))]
1434 if (GET_CODE (operands[0]) == REG)
1436 /* Must clear condition codes, since the move.l bases them on
1437 the entire 32 bits, not just the desired 8 bits. */
1439 return \"move%.l %1,%0\";
1441 if (GET_CODE (operands[1]) == MEM)
1442 operands[1] = adj_offsettable_operand (operands[1], 2);
1443 return \"move%.w %1,%0\";
1446 ;; zero extension instructions
1448 (define_insn "zero_extendqidi2"
1449 [(set (match_operand:DI 0 "general_operand" "=&d")
1450 (zero_extend:DI (match_operand:QI 1 "general_operand" "dm")))]
1455 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1456 return \"moveq %#0,%0\;moveq %#0,%2\;move%.b %1,%2\";
1459 (define_insn "zero_extendhidi2"
1460 [(set (match_operand:DI 0 "general_operand" "=&d")
1461 (zero_extend:DI (match_operand:HI 1 "general_operand" "rm")))]
1466 operands[2] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
1467 return \"moveq %#0,%0\;moveq %#0,%2\;move%.w %1,%2\";
1470 ;; this is the canonical form for (lshiftrt:DI x 32)
1471 (define_insn "zero_extendsidi2"
1472 [(set (match_operand:DI 0 "general_operand" "rm")
1473 (zero_extend:DI (match_operand:SI 1 "general_operand" "rm")))]
1478 if (GET_CODE (operands[0]) == REG)
1479 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1480 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1481 return \"move%.l %1,%0\;clr%.l %0\";
1482 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1483 return \"clr%.l %0\;move%.l %1,%0\";
1485 operands[2] = adj_offsettable_operand (operands[0], 4);
1486 if (GET_CODE (operands[1]) != REG || GET_CODE (operands[1]) != REG
1487 || REGNO (operands[1]) != REGNO (operands[2]))
1488 output_asm_insn (\"move%.l %1,%2\", operands);
1489 if (ADDRESS_REG_P (operands[0]))
1490 return \"sub%.l %0,%0\";
1492 return \"clr%.l %0\";
1495 (define_expand "zero_extendhisi2"
1496 [(set (match_operand:SI 0 "register_operand" "")
1498 (set (strict_low_part (match_dup 2))
1499 (match_operand:HI 1 "general_operand" ""))]
1503 operands[1] = make_safe_from (operands[1], operands[0]);
1504 if (GET_CODE (operands[0]) == SUBREG)
1505 operands[2] = gen_rtx_SUBREG (HImode, SUBREG_REG (operands[0]),
1506 SUBREG_WORD (operands[0]));
1508 operands[2] = gen_rtx_SUBREG (HImode, operands[0], 0);
1511 (define_expand "zero_extendqihi2"
1512 [(set (match_operand:HI 0 "register_operand" "")
1514 (set (strict_low_part (match_dup 2))
1515 (match_operand:QI 1 "general_operand" ""))]
1519 operands[1] = make_safe_from (operands[1], operands[0]);
1520 if (GET_CODE (operands[0]) == SUBREG)
1521 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1522 SUBREG_WORD (operands[0]));
1524 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1527 (define_expand "zero_extendqisi2"
1528 [(set (match_operand:SI 0 "register_operand" "")
1530 (set (strict_low_part (match_dup 2))
1531 (match_operand:QI 1 "general_operand" ""))]
1535 operands[1] = make_safe_from (operands[1], operands[0]);
1536 if (GET_CODE (operands[0]) == SUBREG)
1537 operands[2] = gen_rtx_SUBREG (QImode, SUBREG_REG (operands[0]),
1538 SUBREG_WORD (operands[0]));
1540 operands[2] = gen_rtx_SUBREG (QImode, operands[0], 0);
1543 ;; Patterns to recognize zero-extend insns produced by the combiner.
1544 ;; We don't allow both operands in memory, because of aliasing problems.
1545 ;; Explicitly disallow two memory operands via the condition since reloading
1546 ;; of this case will result in worse code than the uncombined patterns.
1549 [(set (match_operand:SI 0 "general_operand" "=do<>,d<")
1550 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "r,m")))]
1551 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1554 if (DATA_REG_P (operands[0]))
1556 if (GET_CODE (operands[1]) == REG
1557 && REGNO (operands[0]) == REGNO (operands[1]))
1558 return \"and%.l %#0xFFFF,%0\";
1559 if (reg_mentioned_p (operands[0], operands[1]))
1560 return \"move%.w %1,%0\;and%.l %#0xFFFF,%0\";
1561 return \"clr%.l %0\;move%.w %1,%0\";
1563 else if (GET_CODE (operands[0]) == MEM
1564 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1565 return \"move%.w %1,%0\;clr%.w %0\";
1566 else if (GET_CODE (operands[0]) == MEM
1567 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1568 return \"clr%.w %0\;move%.w %1,%0\";
1571 output_asm_insn (\"clr%.w %0\", operands);
1572 operands[0] = adj_offsettable_operand (operands[0], 2);
1573 return \"move%.w %1,%0\";
1578 [(set (match_operand:HI 0 "general_operand" "=do<>,d")
1579 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1580 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1583 if (DATA_REG_P (operands[0]))
1585 if (GET_CODE (operands[1]) == REG
1586 && REGNO (operands[0]) == REGNO (operands[1]))
1587 return \"and%.w %#0xFF,%0\";
1588 if (reg_mentioned_p (operands[0], operands[1]))
1589 return \"move%.b %1,%0\;and%.w %#0xFF,%0\";
1590 return \"clr%.w %0\;move%.b %1,%0\";
1592 else if (GET_CODE (operands[0]) == MEM
1593 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1595 if (REGNO (XEXP (XEXP (operands[0], 0), 0))
1596 == STACK_POINTER_REGNUM)
1598 output_asm_insn (\"clr%.w %-\", operands);
1599 operands[0] = gen_rtx_MEM (GET_MODE (operands[0]),
1600 plus_constant (stack_pointer_rtx, 1));
1601 return \"move%.b %1,%0\";
1604 return \"move%.b %1,%0\;clr%.b %0\";
1606 else if (GET_CODE (operands[0]) == MEM
1607 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1608 return \"clr%.b %0\;move%.b %1,%0\";
1611 output_asm_insn (\"clr%.b %0\", operands);
1612 operands[0] = adj_offsettable_operand (operands[0], 1);
1613 return \"move%.b %1,%0\";
1618 [(set (match_operand:SI 0 "general_operand" "=do<>,d")
1619 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "d,m")))]
1620 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM"
1623 if (DATA_REG_P (operands[0]))
1625 if (GET_CODE (operands[1]) == REG
1626 && REGNO (operands[0]) == REGNO (operands[1]))
1627 return \"and%.l %#0xFF,%0\";
1628 if (reg_mentioned_p (operands[0], operands[1]))
1629 return \"move%.b %1,%0\;and%.l %#0xFF,%0\";
1630 return \"clr%.l %0\;move%.b %1,%0\";
1632 else if (GET_CODE (operands[0]) == MEM
1633 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
1635 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1638 return \"clr%.l -(%0)\;move%.b %1,3(%0)\";
1640 return \"clr%.l -(%0)\;move%.b %1,(3,%0)\";
1643 return \"clrl %0@-\;moveb %1,%0@(3)\";
1646 else if (GET_CODE (operands[0]) == MEM
1647 && GET_CODE (XEXP (operands[0], 0)) == POST_INC)
1649 operands[0] = XEXP (XEXP (operands[0], 0), 0);
1652 return \"clr%.l (%0)+\;move%.b %1,-1(%0)\";
1654 return \"clr%.l (%0)+\;move%.b %1,(-1,%0)\";
1657 return \"clrl %0@+\;moveb %1,%0@(-1)\";
1662 output_asm_insn (\"clr%.l %0\", operands);
1663 operands[0] = adj_offsettable_operand (operands[0], 3);
1664 return \"move%.b %1,%0\";
1668 ;; sign extension instructions
1670 (define_insn "extendqidi2"
1671 [(set (match_operand:DI 0 "general_operand" "=d")
1673 (match_operand:QI 1 "general_operand" "rm")))]
1678 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1679 if (TARGET_68020 || TARGET_5200)
1680 return \"move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0\";
1682 return \"move%.b %1,%2\;ext%.w %0\;ext%.l %2\;move%.l %2,%0\;smi %0\";
1685 (define_insn "extendhidi2"
1686 [(set (match_operand:DI 0 "general_operand" "=d")
1688 (match_operand:HI 1 "general_operand" "rm")))]
1693 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1694 if (TARGET_68020 || TARGET_5200)
1695 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0\";
1697 return \"move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0\";
1700 (define_insn "extendsidi2"
1701 [(set (match_operand:DI 0 "general_operand" "=d")
1703 (match_operand:SI 1 "general_operand" "rm")))]
1708 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1709 if (TARGET_68020 || TARGET_5200)
1710 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
1712 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
1715 ;; Special case when one can avoid register clobbering, copy and test
1716 ;; Maybe there is a way to make that the general case, by forcing the
1717 ;; result of the SI tree to be in the lower register of the DI target
1719 (define_insn "extendplussidi"
1720 [(set (match_operand:DI 0 "register_operand" "=d")
1721 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn")
1722 (match_operand:SI 2 "general_operand" "rmn"))))]
1727 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1728 if (GET_CODE (operands[1]) == CONST_INT
1729 && (unsigned) INTVAL (operands[1]) > 8)
1731 rtx tmp = operands[1];
1733 operands[1] = operands[2];
1736 if (GET_CODE (operands[1]) == REG
1737 && REGNO (operands[1]) == REGNO (operands[3]))
1738 output_asm_insn (\"add%.l %2,%3\", operands);
1740 output_asm_insn (\"move%.l %2,%3\;add%.l %1,%3\", operands);
1741 if (TARGET_68020 || TARGET_5200)
1742 return \"smi %0\;extb%.l %0\";
1744 return \"smi %0\;ext%.w %0\;ext%.l %0\";
1747 (define_insn "extendhisi2"
1748 [(set (match_operand:SI 0 "general_operand" "=*d,a")
1750 (match_operand:HI 1 "nonimmediate_operand" "0,rm")))]
1754 if (ADDRESS_REG_P (operands[0]))
1755 return \"move%.w %1,%0\";
1756 return \"ext%.l %0\";
1759 (define_insn "extendqihi2"
1760 [(set (match_operand:HI 0 "general_operand" "=d")
1761 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1765 (define_insn "extendqisi2"
1766 [(set (match_operand:SI 0 "general_operand" "=d")
1767 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))]
1768 "TARGET_68020 || TARGET_5200"
1771 ;; Conversions between float and double.
1773 (define_expand "extendsfdf2"
1774 [(set (match_operand:DF 0 "general_operand" "")
1776 (match_operand:SF 1 "general_operand" "")))]
1777 "TARGET_68881 || TARGET_FPA"
1781 [(set (match_operand:DF 0 "general_operand" "=x,y")
1783 (match_operand:SF 1 "general_operand" "xH,rmF")))]
1788 [(set (match_operand:DF 0 "general_operand" "=*fdm,f")
1790 (match_operand:SF 1 "general_operand" "f,dmF")))]
1794 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
1796 if (REGNO (operands[0]) == REGNO (operands[1]))
1798 /* Extending float to double in an fp-reg is a no-op.
1799 NOTICE_UPDATE_CC has already assumed that the
1800 cc will be set. So cancel what it did. */
1801 cc_status = cc_prev_status;
1804 return \"f%&move%.x %1,%0\";
1806 if (FP_REG_P (operands[0]))
1807 return \"f%&move%.s %f1,%0\";
1808 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1]))
1810 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
1811 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
1812 return \"move%.l %+,%0\";
1814 return \"fmove%.d %f1,%0\";
1817 ;; This cannot output into an f-reg because there is no way to be
1818 ;; sure of truncating in that case.
1819 ;; But on the Sun FPA, we can be sure.
1820 (define_expand "truncdfsf2"
1821 [(set (match_operand:SF 0 "general_operand" "")
1823 (match_operand:DF 1 "general_operand" "")))]
1824 "TARGET_68881 || TARGET_FPA"
1828 [(set (match_operand:SF 0 "general_operand" "=x,y")
1830 (match_operand:DF 1 "general_operand" "xH,rmF")))]
1834 ;; On the '040 we can truncate in a register accurately and easily.
1836 [(set (match_operand:SF 0 "general_operand" "=f")
1838 (match_operand:DF 1 "general_operand" "fmG")))]
1842 if (FP_REG_P (operands[1]))
1843 return \"f%$move%.x %1,%0\";
1844 return \"f%$move%.d %f1,%0\";
1848 [(set (match_operand:SF 0 "general_operand" "=dm")
1850 (match_operand:DF 1 "general_operand" "f")))]
1854 ;; Conversion between fixed point and floating point.
1855 ;; Note that among the fix-to-float insns
1856 ;; the ones that start with SImode come first.
1857 ;; That is so that an operand that is a CONST_INT
1858 ;; (and therefore lacks a specific machine mode).
1859 ;; will be recognized as SImode (which is always valid)
1860 ;; rather than as QImode or HImode.
1862 (define_expand "floatsisf2"
1863 [(set (match_operand:SF 0 "general_operand" "")
1864 (float:SF (match_operand:SI 1 "general_operand" "")))]
1865 "TARGET_68881 || TARGET_FPA"
1869 [(set (match_operand:SF 0 "general_operand" "=y,x")
1870 (float:SF (match_operand:SI 1 "general_operand" "rmi,x")))]
1875 [(set (match_operand:SF 0 "general_operand" "=f")
1876 (float:SF (match_operand:SI 1 "general_operand" "dmi")))]
1880 (define_expand "floatsidf2"
1881 [(set (match_operand:DF 0 "general_operand" "")
1882 (float:DF (match_operand:SI 1 "general_operand" "")))]
1883 "TARGET_68881 || TARGET_FPA"
1887 [(set (match_operand:DF 0 "general_operand" "=y,x")
1888 (float:DF (match_operand:SI 1 "general_operand" "rmi,x")))]
1893 [(set (match_operand:DF 0 "general_operand" "=f")
1894 (float:DF (match_operand:SI 1 "general_operand" "dmi")))]
1898 (define_insn "floathisf2"
1899 [(set (match_operand:SF 0 "general_operand" "=f")
1900 (float:SF (match_operand:HI 1 "general_operand" "dmn")))]
1904 (define_insn "floathidf2"
1905 [(set (match_operand:DF 0 "general_operand" "=f")
1906 (float:DF (match_operand:HI 1 "general_operand" "dmn")))]
1910 (define_insn "floatqisf2"
1911 [(set (match_operand:SF 0 "general_operand" "=f")
1912 (float:SF (match_operand:QI 1 "general_operand" "dmn")))]
1916 (define_insn "floatqidf2"
1917 [(set (match_operand:DF 0 "general_operand" "=f")
1918 (float:DF (match_operand:QI 1 "general_operand" "dmn")))]
1922 ;; New routines to convert floating-point values to integers
1923 ;; to be used on the '040. These should be faster than trapping
1924 ;; into the kernel to emulate fintrz. They should also be faster
1925 ;; than calling the subroutines fixsfsi or fixdfsi.
1927 (define_insn "fix_truncdfsi2"
1928 [(set (match_operand:SI 0 "general_operand" "=dm")
1929 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1930 (clobber (match_scratch:SI 2 "=d"))
1931 (clobber (match_scratch:SI 3 "=d"))]
1932 "TARGET_68881 && TARGET_68040"
1936 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!\";
1939 (define_insn "fix_truncdfhi2"
1940 [(set (match_operand:HI 0 "general_operand" "=dm")
1941 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1942 (clobber (match_scratch:SI 2 "=d"))
1943 (clobber (match_scratch:SI 3 "=d"))]
1944 "TARGET_68881 && TARGET_68040"
1948 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!\";
1951 (define_insn "fix_truncdfqi2"
1952 [(set (match_operand:QI 0 "general_operand" "=dm")
1953 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f"))))
1954 (clobber (match_scratch:SI 2 "=d"))
1955 (clobber (match_scratch:SI 3 "=d"))]
1956 "TARGET_68881 && TARGET_68040"
1960 return \"fmovem%.l %!,%2\;moveq %#16,%3\;or%.l %2,%3\;and%.w %#-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!\";
1963 ;; Convert a float to a float whose value is an integer.
1964 ;; This is the first stage of converting it to an integer type.
1966 (define_insn "ftruncdf2"
1967 [(set (match_operand:DF 0 "general_operand" "=f")
1968 (fix:DF (match_operand:DF 1 "general_operand" "fFm")))]
1969 "TARGET_68881 && !TARGET_68040"
1972 if (FP_REG_P (operands[1]))
1973 return \"fintrz%.x %f1,%0\";
1974 return \"fintrz%.d %f1,%0\";
1977 (define_insn "ftruncsf2"
1978 [(set (match_operand:SF 0 "general_operand" "=f")
1979 (fix:SF (match_operand:SF 1 "general_operand" "dfFm")))]
1980 "TARGET_68881 && !TARGET_68040"
1983 if (FP_REG_P (operands[1]))
1984 return \"fintrz%.x %f1,%0\";
1985 return \"fintrz%.s %f1,%0\";
1988 ;; Convert a float whose value is an integer
1989 ;; to an actual integer. Second stage of converting float to integer type.
1990 (define_insn "fixsfqi2"
1991 [(set (match_operand:QI 0 "general_operand" "=dm")
1992 (fix:QI (match_operand:SF 1 "general_operand" "f")))]
1996 (define_insn "fixsfhi2"
1997 [(set (match_operand:HI 0 "general_operand" "=dm")
1998 (fix:HI (match_operand:SF 1 "general_operand" "f")))]
2002 (define_insn "fixsfsi2"
2003 [(set (match_operand:SI 0 "general_operand" "=dm")
2004 (fix:SI (match_operand:SF 1 "general_operand" "f")))]
2008 (define_insn "fixdfqi2"
2009 [(set (match_operand:QI 0 "general_operand" "=dm")
2010 (fix:QI (match_operand:DF 1 "general_operand" "f")))]
2014 (define_insn "fixdfhi2"
2015 [(set (match_operand:HI 0 "general_operand" "=dm")
2016 (fix:HI (match_operand:DF 1 "general_operand" "f")))]
2020 (define_insn "fixdfsi2"
2021 [(set (match_operand:SI 0 "general_operand" "=dm")
2022 (fix:SI (match_operand:DF 1 "general_operand" "f")))]
2026 ;; Convert a float to an integer.
2027 ;; On the Sun FPA, this is done in one step.
2030 [(set (match_operand:SI 0 "general_operand" "=x,y")
2031 (fix:SI (fix:SF (match_operand:SF 1 "general_operand" "xH,rmF"))))]
2036 [(set (match_operand:SI 0 "general_operand" "=x,y")
2037 (fix:SI (fix:DF (match_operand:DF 1 "general_operand" "xH,rmF"))))]
2043 (define_insn "adddi_lshrdi_63"
2044 [(set (match_operand:DI 0 "general_operand" "=d")
2045 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm")
2048 (clobber (match_scratch:SI 2 "=d"))]
2052 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2053 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0]))
2055 \"move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0\";
2056 if (GET_CODE (operands[1]) == REG)
2057 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2058 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC
2059 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2060 operands[4] = operands[1];
2062 operands[4] = adj_offsettable_operand (operands[1], 4);
2063 if (GET_CODE (operands[1]) == MEM
2064 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)
2065 output_asm_insn (\"move%.l %4,%3\", operands);
2066 output_asm_insn (\"move%.l %1,%0\;smi %2\", operands);
2067 if (TARGET_68020 || TARGET_5200)
2068 output_asm_insn (\"extb%.l %2\", operands);
2070 output_asm_insn (\"ext%.w %2\;ext%.l %2\", operands);
2071 if (GET_CODE (operands[1]) != MEM
2072 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC)
2073 output_asm_insn (\"move%.l %4,%3\", operands);
2074 return \"sub%.l %2,%3\;subx%.l %2,%0\";
2077 (define_insn "adddi_sexthishl32"
2078 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2079 (plus:DI (ashift:DI (sign_extend:DI
2080 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm"))
2082 (match_operand:DI 2 "general_operand" "0,0,0,0")))
2083 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2088 if (ADDRESS_REG_P (operands[0]))
2089 return \"add%.w %1,%0\";
2090 else if (ADDRESS_REG_P (operands[3]))
2091 return \"move%.w %1,%3\;add%.l %3,%0\";
2093 return \"move%.w %1,%3\;ext%.l %3\;add%.l %3,%0\";
2096 (define_insn "adddi_dilshr32"
2097 [(set (match_operand:DI 0 "general_operand" "=do")
2098 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2099 ;; (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2100 ;; (const_int 32))))]
2101 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
2103 (match_operand:DI 2 "general_operand" "0")))]
2108 if (GET_CODE (operands[0]) == REG)
2109 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
2111 operands[2] = adj_offsettable_operand (operands[0], 4);
2112 return \"add%.l %1,%2\;negx%.l %0\;neg%.l %0\";
2115 (define_insn "adddi_dishl32"
2116 [(set (match_operand:DI 0 "general_operand" "=ro")
2117 ;; (plus:DI (match_operand:DI 2 "general_operand" "%0")
2118 ;; (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2119 ;; (const_int 32))))]
2120 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2122 (match_operand:DI 2 "general_operand" "0")))]
2127 if (GET_CODE (operands[1]) == REG)
2128 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2130 operands[1] = adj_offsettable_operand (operands[1], 4);
2131 return \"add%.l %1,%0\";
2134 (define_insn "adddi3"
2135 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2136 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0,0")
2137 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2138 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2142 if (DATA_REG_P (operands[0]))
2144 if (DATA_REG_P (operands[2]))
2145 return \"add%.l %R2,%R0\;addx%.l %2,%0\";
2146 else if (GET_CODE (operands[2]) == MEM
2147 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2149 return \"move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0\";
2154 if (GET_CODE (operands[2]) == REG)
2155 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2156 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2158 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2159 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2161 else if (GET_CODE (operands[2]) == CONST_INT)
2163 operands[1] = operands[2];
2164 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2167 operands[1] = adj_offsettable_operand (operands[2], 4);
2168 xoperands[0] = operands[3];
2169 xoperands[1] = operands[2];
2170 output_asm_insn (output_move_simode (xoperands), xoperands);
2171 if (GET_CODE (operands[1]) == CONST_INT)
2173 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2176 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2178 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
2181 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2183 operands[1] = GEN_INT (-INTVAL (operands[1]));
2185 return \"sub%.l %1,%R0\;addx%.l %3,%0\";
2187 return \"subq%.l %1,%R0\;addx%.l %3,%0\";
2191 return \"add%.l %1,%R0\;addx%.l %3,%0\";
2194 else if (GET_CODE (operands[0]) == MEM)
2196 if (GET_CODE (operands[2]) == MEM
2197 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2198 return \"add%.l %2,%0\;addx%.l %2,%0\";
2200 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2203 = gen_rtx_MEM (SImode,
2204 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2206 return \"move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1\";
2208 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2210 operands[1] = XEXP(operands[0], 0);
2211 return \"add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1\";
2215 operands[1] = adj_offsettable_operand (operands[0], 4);
2216 return \"add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0\";
2221 (define_insn "addsi_lshrsi_31"
2222 [(set (match_operand:SI 0 "general_operand" "=dm")
2223 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm")
2229 operands[2] = operands[0];
2230 operands[3] = gen_label_rtx();
2231 if (GET_CODE (operands[0]) == MEM)
2233 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2234 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2235 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2236 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0));
2238 output_asm_insn (\"move%.l %1,%0\", operands);
2240 output_asm_insn (\"jbpl %l3\", operands);
2242 output_asm_insn (\"jpl %l3\", operands);
2245 output_asm_insn (\"addq%.l %#1,%2\", operands);
2247 output_asm_insn (\"add%.l %#1,%2\", operands);
2249 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
2250 CODE_LABEL_NUMBER (operands[3]));
2254 (define_expand "addsi3"
2255 [(set (match_operand:SI 0 "general_operand" "")
2256 (plus:SI (match_operand:SI 1 "general_operand" "")
2257 (match_operand:SI 2 "general_operand" "")))]
2261 ;; Note that the middle two alternatives are near-duplicates
2262 ;; in order to handle insns generated by reload.
2263 ;; This is needed since they are not themselves reloaded,
2264 ;; so commutativity won't apply to them.
2265 (define_insn "*addsi3_internal"
2266 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2267 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2268 (match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
2270 "* return output_addsi3 (operands);")
2272 (define_insn "*addsi3_5200"
2273 [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
2274 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
2275 (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
2277 "* return output_addsi3 (operands);")
2280 [(set (match_operand:SI 0 "general_operand" "=a")
2281 (plus:SI (match_operand:SI 1 "general_operand" "0")
2283 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2287 (define_insn "addhi3"
2288 [(set (match_operand:HI 0 "general_operand" "=m,r")
2289 (plus:HI (match_operand:HI 1 "general_operand" "%0,0")
2290 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2294 if (GET_CODE (operands[2]) == CONST_INT)
2297 /* If the constant would be a negative number when interpreted as
2298 HImode, make it negative. This is usually, but not always, done
2299 elsewhere in the compiler. First check for constants out of range,
2300 which could confuse us. */
2302 if (INTVAL (operands[2]) >= 32768)
2303 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536);
2305 if (INTVAL (operands[2]) > 0
2306 && INTVAL (operands[2]) <= 8)
2307 return \"addq%.w %2,%0\";
2308 if (INTVAL (operands[2]) < 0
2309 && INTVAL (operands[2]) >= -8)
2311 operands[2] = GEN_INT (-INTVAL (operands[2]));
2312 return \"subq%.w %2,%0\";
2314 /* On the CPU32 it is faster to use two addqw instructions to
2315 add a small integer (8 < N <= 16) to a register.
2316 Likewise for subqw. */
2317 if (TARGET_CPU32 && REG_P (operands[0]))
2319 if (INTVAL (operands[2]) > 8
2320 && INTVAL (operands[2]) <= 16)
2322 operands[2] = GEN_INT (INTVAL (operands[2]) - 8);
2323 return \"addq%.w %#8,%0\;addq%.w %2,%0\";
2325 if (INTVAL (operands[2]) < -8
2326 && INTVAL (operands[2]) >= -16)
2328 operands[2] = GEN_INT (-INTVAL (operands[2]) - 8);
2329 return \"subq%.w %#8,%0\;subq%.w %2,%0\";
2333 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2335 return \"lea (%c2,%0),%0\";
2337 return \"lea %0@(%c2),%0\";
2340 return \"add%.w %2,%0\";
2343 ;; These insns must use MATCH_DUP instead of the more expected
2344 ;; use of a matching constraint because the "output" here is also
2345 ;; an input, so you can't use the matching constraint. That also means
2346 ;; that you can't use the "%", so you need patterns with the matched
2347 ;; operand in both positions.
2350 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2351 (plus:HI (match_dup 0)
2352 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2356 if (GET_CODE (operands[1]) == CONST_INT)
2359 /* If the constant would be a negative number when interpreted as
2360 HImode, make it negative. This is usually, but not always, done
2361 elsewhere in the compiler. First check for constants out of range,
2362 which could confuse us. */
2364 if (INTVAL (operands[1]) >= 32768)
2365 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2367 if (INTVAL (operands[1]) > 0
2368 && INTVAL (operands[1]) <= 8)
2369 return \"addq%.w %1,%0\";
2370 if (INTVAL (operands[1]) < 0
2371 && INTVAL (operands[1]) >= -8)
2373 operands[1] = GEN_INT (-INTVAL (operands[1]));
2374 return \"subq%.w %1,%0\";
2376 /* On the CPU32 it is faster to use two addqw instructions to
2377 add a small integer (8 < N <= 16) to a register.
2378 Likewise for subqw. */
2379 if (TARGET_CPU32 && REG_P (operands[0]))
2381 if (INTVAL (operands[1]) > 8
2382 && INTVAL (operands[1]) <= 16)
2384 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2385 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2387 if (INTVAL (operands[1]) < -8
2388 && INTVAL (operands[1]) >= -16)
2390 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2391 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2395 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2397 return \"lea (%c1,%0),%0\";
2399 return \"lea %0@(%c1),%0\";
2402 return \"add%.w %1,%0\";
2406 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2407 (plus:HI (match_operand:HI 1 "general_operand" "dn,rmn")
2412 if (GET_CODE (operands[1]) == CONST_INT)
2415 /* If the constant would be a negative number when interpreted as
2416 HImode, make it negative. This is usually, but not always, done
2417 elsewhere in the compiler. First check for constants out of range,
2418 which could confuse us. */
2420 if (INTVAL (operands[1]) >= 32768)
2421 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536);
2423 if (INTVAL (operands[1]) > 0
2424 && INTVAL (operands[1]) <= 8)
2425 return \"addq%.w %1,%0\";
2426 if (INTVAL (operands[1]) < 0
2427 && INTVAL (operands[1]) >= -8)
2429 operands[1] = GEN_INT (-INTVAL (operands[1]));
2430 return \"subq%.w %1,%0\";
2432 /* On the CPU32 it is faster to use two addqw instructions to
2433 add a small integer (8 < N <= 16) to a register.
2434 Likewise for subqw. */
2435 if (TARGET_CPU32 && REG_P (operands[0]))
2437 if (INTVAL (operands[1]) > 8
2438 && INTVAL (operands[1]) <= 16)
2440 operands[1] = GEN_INT (INTVAL (operands[1]) - 8);
2441 return \"addq%.w %#8,%0\;addq%.w %1,%0\";
2443 if (INTVAL (operands[1]) < -8
2444 && INTVAL (operands[1]) >= -16)
2446 operands[1] = GEN_INT (-INTVAL (operands[1]) - 8);
2447 return \"subq%.w %#8,%0\;subq%.w %1,%0\";
2451 if (ADDRESS_REG_P (operands[0]) && !TARGET_68040)
2453 return \"lea (%c1,%0),%0\";
2455 return \"lea %0@(%c1),%0\";
2458 return \"add%.w %1,%0\";
2461 (define_insn "addqi3"
2462 [(set (match_operand:QI 0 "general_operand" "=m,d")
2463 (plus:QI (match_operand:QI 1 "general_operand" "%0,0")
2464 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2469 if (GET_CODE (operands[2]) == CONST_INT)
2471 if (INTVAL (operands[2]) >= 128)
2472 operands[2] = GEN_INT (INTVAL (operands[2]) - 256);
2474 if (INTVAL (operands[2]) > 0
2475 && INTVAL (operands[2]) <= 8)
2476 return \"addq%.b %2,%0\";
2477 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8)
2479 operands[2] = GEN_INT (-INTVAL (operands[2]));
2480 return \"subq%.b %2,%0\";
2484 return \"add%.b %2,%0\";
2488 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2489 (plus:QI (match_dup 0)
2490 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2495 if (GET_CODE (operands[1]) == CONST_INT)
2497 if (INTVAL (operands[1]) >= 128)
2498 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2500 if (INTVAL (operands[1]) > 0
2501 && INTVAL (operands[1]) <= 8)
2502 return \"addq%.b %1,%0\";
2503 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2505 operands[1] = GEN_INT (-INTVAL (operands[1]));
2506 return \"subq%.b %1,%0\";
2510 return \"add%.b %1,%0\";
2514 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2515 (plus:QI (match_operand:QI 1 "general_operand" "dn,dmn")
2521 if (GET_CODE (operands[1]) == CONST_INT)
2523 if (INTVAL (operands[1]) >= 128)
2524 operands[1] = GEN_INT (INTVAL (operands[1]) - 256);
2526 if (INTVAL (operands[1]) > 0
2527 && INTVAL (operands[1]) <= 8)
2528 return \"addq%.b %1,%0\";
2529 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8)
2531 operands[1] = GEN_INT (-INTVAL (operands[1]));
2532 return \"subq%.b %1,%0\";
2536 return \"add%.b %1,%0\";
2539 (define_expand "adddf3"
2540 [(set (match_operand:DF 0 "general_operand" "")
2541 (plus:DF (match_operand:DF 1 "general_operand" "")
2542 (match_operand:DF 2 "general_operand" "")))]
2543 "TARGET_68881 || TARGET_FPA"
2547 [(set (match_operand:DF 0 "general_operand" "=x,y")
2548 (plus:DF (match_operand:DF 1 "general_operand" "%xH,y")
2549 (match_operand:DF 2 "general_operand" "xH,dmF")))]
2553 if (rtx_equal_p (operands[0], operands[1]))
2554 return \"fpadd%.d %y2,%0\";
2555 if (rtx_equal_p (operands[0], operands[2]))
2556 return \"fpadd%.d %y1,%0\";
2557 if (which_alternative == 0)
2558 return \"fpadd3%.d %w2,%w1,%0\";
2559 return \"fpadd3%.d %x2,%x1,%0\";
2563 [(set (match_operand:DF 0 "general_operand" "=f")
2564 (plus:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
2565 (match_operand:DF 1 "general_operand" "0")))]
2570 [(set (match_operand:DF 0 "general_operand" "=f")
2571 (plus:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
2572 (match_operand:DF 1 "general_operand" "0")))]
2577 [(set (match_operand:DF 0 "general_operand" "=f")
2578 (plus:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
2579 (match_operand:DF 1 "general_operand" "0")))]
2584 [(set (match_operand:DF 0 "general_operand" "=f")
2585 (plus:DF (match_operand:DF 1 "general_operand" "%0")
2586 (match_operand:DF 2 "general_operand" "fmG")))]
2590 if (REG_P (operands[2]))
2591 return \"f%&add%.x %2,%0\";
2592 return \"f%&add%.d %f2,%0\";
2595 (define_expand "addsf3"
2596 [(set (match_operand:SF 0 "general_operand" "")
2597 (plus:SF (match_operand:SF 1 "general_operand" "")
2598 (match_operand:SF 2 "general_operand" "")))]
2599 "TARGET_68881 || TARGET_FPA"
2603 [(set (match_operand:SF 0 "general_operand" "=x,y")
2604 (plus:SF (match_operand:SF 1 "general_operand" "%xH,y")
2605 (match_operand:SF 2 "general_operand" "xH,rmF")))]
2609 if (rtx_equal_p (operands[0], operands[1]))
2610 return \"fpadd%.s %w2,%0\";
2611 if (rtx_equal_p (operands[0], operands[2]))
2612 return \"fpadd%.s %w1,%0\";
2613 if (which_alternative == 0)
2614 return \"fpadd3%.s %w2,%w1,%0\";
2615 return \"fpadd3%.s %2,%1,%0\";
2619 [(set (match_operand:SF 0 "general_operand" "=f")
2620 (plus:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
2621 (match_operand:SF 1 "general_operand" "0")))]
2626 [(set (match_operand:SF 0 "general_operand" "=f")
2627 (plus:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
2628 (match_operand:SF 1 "general_operand" "0")))]
2633 [(set (match_operand:SF 0 "general_operand" "=f")
2634 (plus:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
2635 (match_operand:SF 1 "general_operand" "0")))]
2640 [(set (match_operand:SF 0 "general_operand" "=f")
2641 (plus:SF (match_operand:SF 1 "general_operand" "%0")
2642 (match_operand:SF 2 "general_operand" "fdmF")))]
2646 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2647 return \"f%$add%.x %2,%0\";
2648 return \"f%$add%.s %f2,%0\";
2651 ;; subtract instructions
2653 (define_insn "subdi_sexthishl32"
2654 [(set (match_operand:DI 0 "general_operand" "=o,a,*d,*d")
2655 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0")
2656 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm"))
2658 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))]
2663 if (ADDRESS_REG_P (operands[0]))
2664 return \"sub%.w %2,%0\";
2665 else if (ADDRESS_REG_P (operands[3]))
2666 return \"move%.w %2,%3\;sub%.l %3,%0\";
2668 return \"move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0\";
2671 (define_insn "subdi_dishl32"
2672 [(set (match_operand:DI 0 "general_operand" "+ro")
2673 (minus:DI (match_dup 0)
2674 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
2680 if (GET_CODE (operands[1]) == REG)
2681 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
2683 operands[1] = adj_offsettable_operand (operands[1], 4);
2684 return \"sub%.l %1,%0\";
2687 (define_insn "subdi3"
2688 [(set (match_operand:DI 0 "general_operand" "=<,o<>,d,d,d")
2689 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0,0")
2690 (match_operand:DI 2 "general_operand" "<,d,no>,d,a")))
2691 (clobber (match_scratch:SI 3 "=X,&d,&d,X,&d"))]
2695 if (DATA_REG_P (operands[0]))
2697 if (DATA_REG_P (operands[2]))
2698 return \"sub%.l %R2,%R0\;subx%.l %2,%0\";
2699 else if (GET_CODE (operands[2]) == MEM
2700 && GET_CODE (XEXP (operands[2], 0)) == POST_INC)
2702 return \"move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0\";
2707 if (GET_CODE (operands[2]) == REG)
2708 operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
2709 else if (GET_CODE (operands[2]) == CONST_DOUBLE)
2711 operands[1] = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
2712 operands[2] = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
2714 else if (GET_CODE (operands[2]) == CONST_INT)
2716 operands[1] = operands[2];
2717 operands[2] = INTVAL (operands[2]) < 0 ? constm1_rtx : const0_rtx;
2720 operands[1] = adj_offsettable_operand (operands[2], 4);
2721 xoperands[0] = operands[3];
2722 xoperands[1] = operands[2];
2723 output_asm_insn (output_move_simode (xoperands), xoperands);
2724 if (GET_CODE (operands[1]) == CONST_INT)
2726 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
2729 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2731 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
2734 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
2736 operands[1] = GEN_INT (-INTVAL (operands[1]));
2738 return \"add%.l %1,%R0\;subx%.l %3,%0\";
2740 return \"addq%.l %1,%R0\;subx%.l %3,%0\";
2744 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
2747 else if (GET_CODE (operands[0]) == MEM)
2749 if (GET_CODE (operands[2]) == MEM
2750 && GET_CODE (XEXP (operands[2], 0)) == PRE_DEC)
2751 return \"sub%.l %2,%0\;subx%.l %2,%0\";
2753 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
2756 = gen_rtx_MEM (SImode,
2757 gen_rtx_PLUS (VOIDmode, XEXP(operands[0], 0),
2759 return \"move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1\";
2761 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
2763 operands[1] = XEXP(operands[0], 0);
2764 return \"sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1\";
2768 operands[1] = adj_offsettable_operand (operands[0], 4);
2769 return \"sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0\";
2774 (define_insn "subsi3"
2775 [(set (match_operand:SI 0 "general_operand" "=m,r")
2776 (minus:SI (match_operand:SI 1 "general_operand" "0,0")
2777 (match_operand:SI 2 "general_operand" "ds,mrs")))]
2782 [(set (match_operand:SI 0 "general_operand" "=a")
2783 (minus:SI (match_operand:SI 1 "general_operand" "0")
2785 (match_operand:HI 2 "nonimmediate_operand" "rm"))))]
2789 (define_insn "subhi3"
2790 [(set (match_operand:HI 0 "general_operand" "=m,r")
2791 (minus:HI (match_operand:HI 1 "general_operand" "0,0")
2792 (match_operand:HI 2 "general_operand" "dn,rmn")))]
2797 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
2798 (minus:HI (match_dup 0)
2799 (match_operand:HI 1 "general_operand" "dn,rmn")))]
2803 (define_insn "subqi3"
2804 [(set (match_operand:QI 0 "general_operand" "=m,d")
2805 (minus:QI (match_operand:QI 1 "general_operand" "0,0")
2806 (match_operand:QI 2 "general_operand" "dn,dmn")))]
2811 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
2812 (minus:QI (match_dup 0)
2813 (match_operand:QI 1 "general_operand" "dn,dmn")))]
2817 (define_expand "subdf3"
2818 [(set (match_operand:DF 0 "general_operand" "")
2819 (minus:DF (match_operand:DF 1 "general_operand" "")
2820 (match_operand:DF 2 "general_operand" "")))]
2821 "TARGET_68881 || TARGET_FPA"
2825 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
2826 (minus:DF (match_operand:DF 1 "general_operand" "xH,y,dmF")
2827 (match_operand:DF 2 "general_operand" "xH,dmF,0")))]
2831 if (rtx_equal_p (operands[0], operands[2]))
2832 return \"fprsub%.d %y1,%0\";
2833 if (rtx_equal_p (operands[0], operands[1]))
2834 return \"fpsub%.d %y2,%0\";
2835 if (which_alternative == 0)
2836 return \"fpsub3%.d %w2,%w1,%0\";
2837 return \"fpsub3%.d %x2,%x1,%0\";
2841 [(set (match_operand:DF 0 "general_operand" "=f")
2842 (minus:DF (match_operand:DF 1 "general_operand" "0")
2843 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
2848 [(set (match_operand:DF 0 "general_operand" "=f")
2849 (minus:DF (match_operand:DF 1 "general_operand" "0")
2850 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
2855 [(set (match_operand:DF 0 "general_operand" "=f")
2856 (minus:DF (match_operand:DF 1 "general_operand" "0")
2857 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
2862 [(set (match_operand:DF 0 "general_operand" "=f")
2863 (minus:DF (match_operand:DF 1 "general_operand" "0")
2864 (match_operand:DF 2 "general_operand" "fmG")))]
2868 if (REG_P (operands[2]))
2869 return \"f%&sub%.x %2,%0\";
2870 return \"f%&sub%.d %f2,%0\";
2873 (define_expand "subsf3"
2874 [(set (match_operand:SF 0 "general_operand" "")
2875 (minus:SF (match_operand:SF 1 "general_operand" "")
2876 (match_operand:SF 2 "general_operand" "")))]
2877 "TARGET_68881 || TARGET_FPA"
2881 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
2882 (minus:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
2883 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
2887 if (rtx_equal_p (operands[0], operands[2]))
2888 return \"fprsub%.s %w1,%0\";
2889 if (rtx_equal_p (operands[0], operands[1]))
2890 return \"fpsub%.s %w2,%0\";
2891 if (which_alternative == 0)
2892 return \"fpsub3%.s %w2,%w1,%0\";
2893 return \"fpsub3%.s %2,%1,%0\";
2897 [(set (match_operand:SF 0 "general_operand" "=f")
2898 (minus:SF (match_operand:SF 1 "general_operand" "0")
2899 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
2904 [(set (match_operand:SF 0 "general_operand" "=f")
2905 (minus:SF (match_operand:SF 1 "general_operand" "0")
2906 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
2911 [(set (match_operand:SF 0 "general_operand" "=f")
2912 (minus:SF (match_operand:SF 1 "general_operand" "0")
2913 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
2918 [(set (match_operand:SF 0 "general_operand" "=f")
2919 (minus:SF (match_operand:SF 1 "general_operand" "0")
2920 (match_operand:SF 2 "general_operand" "fdmF")))]
2924 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
2925 return \"f%$sub%.x %2,%0\";
2926 return \"f%$sub%.s %f2,%0\";
2929 ;; multiply instructions
2931 (define_insn "mulhi3"
2932 [(set (match_operand:HI 0 "general_operand" "=d")
2933 (mult:HI (match_operand:HI 1 "general_operand" "%0")
2934 (match_operand:HI 2 "general_operand" "dmn")))]
2938 #if defined(MOTOROLA) && !defined(CRDS)
2939 return \"muls%.w %2,%0\";
2941 return \"muls %2,%0\";
2945 (define_insn "mulhisi3"
2946 [(set (match_operand:SI 0 "general_operand" "=d")
2947 (mult:SI (sign_extend:SI
2948 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2950 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
2954 #if defined(MOTOROLA) && !defined(CRDS)
2955 return \"muls%.w %2,%0\";
2957 return \"muls %2,%0\";
2962 [(set (match_operand:SI 0 "general_operand" "=d")
2963 (mult:SI (sign_extend:SI
2964 (match_operand:HI 1 "nonimmediate_operand" "%0"))
2965 (match_operand:SI 2 "const_int_operand" "n")))]
2966 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff"
2969 #if defined(MOTOROLA) && !defined(CRDS)
2970 return \"muls%.w %2,%0\";
2972 return \"muls %2,%0\";
2976 (define_expand "mulsi3"
2977 [(set (match_operand:SI 0 "general_operand" "")
2978 (mult:SI (match_operand:SI 1 "general_operand" "")
2979 (match_operand:SI 2 "general_operand" "")))]
2980 "TARGET_68020 || TARGET_5200"
2984 [(set (match_operand:SI 0 "general_operand" "=d")
2985 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2986 (match_operand:SI 2 "general_operand" "dmsK")))]
2991 [(set (match_operand:SI 0 "general_operand" "=d")
2992 (mult:SI (match_operand:SI 1 "general_operand" "%0")
2993 (match_operand:SI 2 "general_operand" "d<Q>")))]
2997 (define_insn "umulhisi3"
2998 [(set (match_operand:SI 0 "general_operand" "=d")
2999 (mult:SI (zero_extend:SI
3000 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3002 (match_operand:HI 2 "nonimmediate_operand" "dm"))))]
3006 #if defined(MOTOROLA) && !defined(CRDS)
3007 return \"mulu%.w %2,%0\";
3009 return \"mulu %2,%0\";
3014 [(set (match_operand:SI 0 "general_operand" "=d")
3015 (mult:SI (zero_extend:SI
3016 (match_operand:HI 1 "nonimmediate_operand" "%0"))
3017 (match_operand:SI 2 "const_int_operand" "n")))]
3018 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff"
3021 #if defined(MOTOROLA) && !defined(CRDS)
3022 return \"mulu%.w %2,%0\";
3024 return \"mulu %2,%0\";
3028 ;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the
3029 ;; proper matching constraint. This is because the matching is between
3030 ;; the high-numbered word of the DImode operand[0] and operand[1].
3031 (define_expand "umulsidi3"
3033 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3034 (mult:SI (match_operand:SI 1 "register_operand" "")
3035 (match_operand:SI 2 "nonimmediate_operand" "")))
3036 (set (subreg:SI (match_dup 0) 0)
3037 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3038 (zero_extend:DI (match_dup 2)))
3039 (const_int 32))))])]
3040 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3044 [(set (match_operand:SI 0 "register_operand" "=d")
3045 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3046 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3047 (set (match_operand:SI 3 "register_operand" "=d")
3048 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3049 (zero_extend:DI (match_dup 2)))
3051 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3054 ; Match immediate case. For 2.4 only match things < 2^31.
3055 ; It's tricky with larger values in these patterns since we need to match
3056 ; values between the two parallel multiplies, between a CONST_DOUBLE and
3059 [(set (match_operand:SI 0 "register_operand" "=d")
3060 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3061 (match_operand:SI 2 "const_int_operand" "n")))
3062 (set (match_operand:SI 3 "register_operand" "=d")
3063 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1))
3066 "TARGET_68020 && !TARGET_68060 && !TARGET_5200
3067 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff"
3070 (define_expand "mulsidi3"
3072 [(set (subreg:SI (match_operand:DI 0 "register_operand" "") 1)
3073 (mult:SI (match_operand:SI 1 "register_operand" "")
3074 (match_operand:SI 2 "nonimmediate_operand" "")))
3075 (set (subreg:SI (match_dup 0) 0)
3076 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3077 (sign_extend:DI (match_dup 2)))
3078 (const_int 32))))])]
3079 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3083 [(set (match_operand:SI 0 "register_operand" "=d")
3084 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3085 (match_operand:SI 2 "nonimmediate_operand" "dm")))
3086 (set (match_operand:SI 3 "register_operand" "=d")
3087 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3088 (sign_extend:DI (match_dup 2)))
3090 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3094 [(set (match_operand:SI 0 "register_operand" "=d")
3095 (mult:SI (match_operand:SI 1 "register_operand" "%0")
3096 (match_operand:SI 2 "const_sint32_operand" "")))
3097 (set (match_operand:SI 3 "register_operand" "=d")
3098 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1))
3101 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3104 (define_expand "umulsi3_highpart"
3106 [(set (match_operand:SI 0 "register_operand" "")
3109 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" ""))
3110 (zero_extend:DI (match_operand:SI 2 "general_operand" "")))
3112 (clobber (match_dup 3))])]
3113 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3116 operands[3] = gen_reg_rtx (SImode);
3117 if (GET_CODE (operands[2]) == CONST_INT
3118 || GET_CODE (operands[2]) == CONST_DOUBLE)
3120 if (! const_uint32_operand (operands[2], VOIDmode))
3122 /* We have to adjust the operand order for the matching constraints. */
3123 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3],
3124 operands[1], operands[2]));
3130 [(set (match_operand:SI 0 "register_operand" "=d")
3133 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3134 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3136 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3137 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3140 (define_insn "const_umulsi3_highpart"
3141 [(set (match_operand:SI 0 "register_operand" "=d")
3144 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1"))
3145 (match_operand 3 "const_uint32_operand" ""))
3147 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3148 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3151 (define_expand "smulsi3_highpart"
3153 [(set (match_operand:SI 0 "register_operand" "")
3156 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" ""))
3157 (sign_extend:DI (match_operand:SI 2 "general_operand" "")))
3159 (clobber (match_dup 3))])]
3160 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3163 operands[3] = gen_reg_rtx (SImode);
3164 if (GET_CODE (operands[2]) == CONST_INT
3165 || GET_CODE (operands[2]) == CONST_DOUBLE)
3167 if (! const_sint32_operand (operands[2], VOIDmode))
3169 /* We have to adjust the operand order for the matching constraints. */
3170 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3],
3171 operands[1], operands[2]));
3177 [(set (match_operand:SI 0 "register_operand" "=d")
3180 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1"))
3181 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm")))
3183 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3184 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3187 (define_insn "const_smulsi3_highpart"
3188 [(set (match_operand:SI 0 "register_operand" "=d")
3191 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1"))
3192 (match_operand 3 "const_sint32_operand" ""))
3194 (clobber (match_operand:SI 1 "register_operand" "=d"))]
3195 "TARGET_68020 && !TARGET_68060 && !TARGET_5200"
3198 (define_expand "muldf3"
3199 [(set (match_operand:DF 0 "general_operand" "")
3200 (mult:DF (match_operand:DF 1 "general_operand" "")
3201 (match_operand:DF 2 "general_operand" "")))]
3202 "TARGET_68881 || TARGET_FPA"
3206 [(set (match_operand:DF 0 "general_operand" "=x,y")
3207 (mult:DF (match_operand:DF 1 "general_operand" "%xH,y")
3208 (match_operand:DF 2 "general_operand" "xH,rmF")))]
3212 if (rtx_equal_p (operands[1], operands[2]))
3213 return \"fpsqr%.d %y1,%0\";
3214 if (rtx_equal_p (operands[0], operands[1]))
3215 return \"fpmul%.d %y2,%0\";
3216 if (rtx_equal_p (operands[0], operands[2]))
3217 return \"fpmul%.d %y1,%0\";
3218 if (which_alternative == 0)
3219 return \"fpmul3%.d %w2,%w1,%0\";
3220 return \"fpmul3%.d %x2,%x1,%0\";
3224 [(set (match_operand:DF 0 "general_operand" "=f")
3225 (mult:DF (float:DF (match_operand:SI 2 "general_operand" "dmi"))
3226 (match_operand:DF 1 "general_operand" "0")))]
3231 [(set (match_operand:DF 0 "general_operand" "=f")
3232 (mult:DF (float:DF (match_operand:HI 2 "general_operand" "dmn"))
3233 (match_operand:DF 1 "general_operand" "0")))]
3238 [(set (match_operand:DF 0 "general_operand" "=f")
3239 (mult:DF (float:DF (match_operand:QI 2 "general_operand" "dmn"))
3240 (match_operand:DF 1 "general_operand" "0")))]
3245 [(set (match_operand:DF 0 "general_operand" "=f")
3246 (mult:DF (match_operand:DF 1 "general_operand" "%0")
3247 (match_operand:DF 2 "general_operand" "fmG")))]
3251 if (GET_CODE (operands[2]) == CONST_DOUBLE
3252 && floating_exact_log2 (operands[2]) && !TARGET_68040 && !TARGET_68060)
3254 int i = floating_exact_log2 (operands[2]);
3255 operands[2] = GEN_INT (i);
3256 return \"fscale%.l %2,%0\";
3258 if (REG_P (operands[2]))
3259 return \"f%&mul%.x %2,%0\";
3260 return \"f%&mul%.d %f2,%0\";
3263 (define_expand "mulsf3"
3264 [(set (match_operand:SF 0 "general_operand" "")
3265 (mult:SF (match_operand:SF 1 "general_operand" "")
3266 (match_operand:SF 2 "general_operand" "")))]
3267 "TARGET_68881 || TARGET_FPA"
3271 [(set (match_operand:SF 0 "general_operand" "=x,y")
3272 (mult:SF (match_operand:SF 1 "general_operand" "%xH,y")
3273 (match_operand:SF 2 "general_operand" "xH,rmF")))]
3277 if (rtx_equal_p (operands[1], operands[2]))
3278 return \"fpsqr%.s %w1,%0\";
3279 if (rtx_equal_p (operands[0], operands[1]))
3280 return \"fpmul%.s %w2,%0\";
3281 if (rtx_equal_p (operands[0], operands[2]))
3282 return \"fpmul%.s %w1,%0\";
3283 if (which_alternative == 0)
3284 return \"fpmul3%.s %w2,%w1,%0\";
3285 return \"fpmul3%.s %2,%1,%0\";
3289 [(set (match_operand:SF 0 "general_operand" "=f")
3290 (mult:SF (float:SF (match_operand:SI 2 "general_operand" "dmi"))
3291 (match_operand:SF 1 "general_operand" "0")))]
3295 return (TARGET_68040_ONLY
3296 ? \"fsmul%.l %2,%0\"
3297 : \"fsglmul%.l %2,%0\");
3301 [(set (match_operand:SF 0 "general_operand" "=f")
3302 (mult:SF (float:SF (match_operand:HI 2 "general_operand" "dmn"))
3303 (match_operand:SF 1 "general_operand" "0")))]
3307 return (TARGET_68040_ONLY
3308 ? \"fsmul%.w %2,%0\"
3309 : \"fsglmul%.w %2,%0\");
3313 [(set (match_operand:SF 0 "general_operand" "=f")
3314 (mult:SF (float:SF (match_operand:QI 2 "general_operand" "dmn"))
3315 (match_operand:SF 1 "general_operand" "0")))]
3319 return (TARGET_68040_ONLY
3320 ? \"fsmul%.b %2,%0\"
3321 : \"fsglmul%.b %2,%0\");
3325 [(set (match_operand:SF 0 "general_operand" "=f")
3326 (mult:SF (match_operand:SF 1 "general_operand" "%0")
3327 (match_operand:SF 2 "general_operand" "fdmF")))]
3331 #ifdef FSGLMUL_USE_S
3332 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3333 return (TARGET_68040_ONLY
3334 ? \"fsmul%.s %2,%0\"
3335 : \"fsglmul%.s %2,%0\");
3337 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3338 return (TARGET_68040_ONLY
3339 ? \"fsmul%.x %2,%0\"
3340 : \"fsglmul%.x %2,%0\");
3342 return (TARGET_68040_ONLY
3343 ? \"fsmul%.s %f2,%0\"
3344 : \"fsglmul%.s %f2,%0\");
3347 ;; divide instructions
3349 (define_expand "divdf3"
3350 [(set (match_operand:DF 0 "general_operand" "")
3351 (div:DF (match_operand:DF 1 "general_operand" "")
3352 (match_operand:DF 2 "general_operand" "")))]
3353 "TARGET_68881 || TARGET_FPA"
3357 [(set (match_operand:DF 0 "general_operand" "=x,y,y")
3358 (div:DF (match_operand:DF 1 "general_operand" "xH,y,rmF")
3359 (match_operand:DF 2 "general_operand" "xH,rmF,0")))]
3363 if (rtx_equal_p (operands[0], operands[2]))
3364 return \"fprdiv%.d %y1,%0\";
3365 if (rtx_equal_p (operands[0], operands[1]))
3366 return \"fpdiv%.d %y2,%0\";
3367 if (which_alternative == 0)
3368 return \"fpdiv3%.d %w2,%w1,%0\";
3369 return \"fpdiv3%.d %x2,%x1,%x0\";
3373 [(set (match_operand:DF 0 "general_operand" "=f")
3374 (div:DF (match_operand:DF 1 "general_operand" "0")
3375 (float:DF (match_operand:SI 2 "general_operand" "dmi"))))]
3380 [(set (match_operand:DF 0 "general_operand" "=f")
3381 (div:DF (match_operand:DF 1 "general_operand" "0")
3382 (float:DF (match_operand:HI 2 "general_operand" "dmn"))))]
3387 [(set (match_operand:DF 0 "general_operand" "=f")
3388 (div:DF (match_operand:DF 1 "general_operand" "0")
3389 (float:DF (match_operand:QI 2 "general_operand" "dmn"))))]
3394 [(set (match_operand:DF 0 "general_operand" "=f")
3395 (div:DF (match_operand:DF 1 "general_operand" "0")
3396 (match_operand:DF 2 "general_operand" "fmG")))]
3400 if (REG_P (operands[2]))
3401 return \"f%&div%.x %2,%0\";
3402 return \"f%&div%.d %f2,%0\";
3405 (define_expand "divsf3"
3406 [(set (match_operand:SF 0 "general_operand" "")
3407 (div:SF (match_operand:SF 1 "general_operand" "")
3408 (match_operand:SF 2 "general_operand" "")))]
3409 "TARGET_68881 || TARGET_FPA"
3413 [(set (match_operand:SF 0 "general_operand" "=x,y,y")
3414 (div:SF (match_operand:SF 1 "general_operand" "xH,y,rmF")
3415 (match_operand:SF 2 "general_operand" "xH,rmF,0")))]
3419 if (rtx_equal_p (operands[0], operands[1]))
3420 return \"fpdiv%.s %w2,%0\";
3421 if (rtx_equal_p (operands[0], operands[2]))
3422 return \"fprdiv%.s %w1,%0\";
3423 if (which_alternative == 0)
3424 return \"fpdiv3%.s %w2,%w1,%0\";
3425 return \"fpdiv3%.s %2,%1,%0\";
3429 [(set (match_operand:SF 0 "general_operand" "=f")
3430 (div:SF (match_operand:SF 1 "general_operand" "0")
3431 (float:SF (match_operand:SI 2 "general_operand" "dmi"))))]
3435 return (TARGET_68040_ONLY
3436 ? \"fsdiv%.l %2,%0\"
3437 : \"fsgldiv%.l %2,%0\");
3441 [(set (match_operand:SF 0 "general_operand" "=f")
3442 (div:SF (match_operand:SF 1 "general_operand" "0")
3443 (float:SF (match_operand:HI 2 "general_operand" "dmn"))))]
3447 return (TARGET_68040_ONLY
3448 ? \"fsdiv%.w %2,%0\"
3449 : \"fsgldiv%.w %2,%0\");
3453 [(set (match_operand:SF 0 "general_operand" "=f")
3454 (div:SF (match_operand:SF 1 "general_operand" "0")
3455 (float:SF (match_operand:QI 2 "general_operand" "dmn"))))]
3459 return (TARGET_68040_ONLY
3460 ? \"fsdiv%.b %2,%0\"
3461 : \"fsgldiv%.b %2,%0\");
3465 [(set (match_operand:SF 0 "general_operand" "=f")
3466 (div:SF (match_operand:SF 1 "general_operand" "0")
3467 (match_operand:SF 2 "general_operand" "fdmF")))]
3471 #ifdef FSGLDIV_USE_S
3472 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3473 return (TARGET_68040_ONLY
3474 ? \"fsdiv%.s %2,%0\"
3475 : \"fsgldiv%.s %2,%0\");
3477 if (REG_P (operands[2]) && ! DATA_REG_P (operands[2]))
3478 return (TARGET_68040_ONLY
3479 ? \"fsdiv%.x %2,%0\"
3480 : \"fsgldiv%.x %2,%0\");
3482 return (TARGET_68040_ONLY
3483 ? \"fsdiv%.s %f2,%0\"
3484 : \"fsgldiv%.s %f2,%0\");
3487 ;; Remainder instructions.
3489 (define_insn "divmodsi4"
3490 [(set (match_operand:SI 0 "general_operand" "=d")
3491 (div:SI (match_operand:SI 1 "general_operand" "0")
3492 (match_operand:SI 2 "general_operand" "dmsK")))
3493 (set (match_operand:SI 3 "general_operand" "=d")
3494 (mod:SI (match_dup 1) (match_dup 2)))]
3495 "TARGET_68020 && !TARGET_5200"
3498 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3499 return \"divs%.l %2,%0\";
3501 return \"divsl%.l %2,%3:%0\";
3504 (define_insn "udivmodsi4"
3505 [(set (match_operand:SI 0 "general_operand" "=d")
3506 (udiv:SI (match_operand:SI 1 "general_operand" "0")
3507 (match_operand:SI 2 "general_operand" "dmsK")))
3508 (set (match_operand:SI 3 "general_operand" "=d")
3509 (umod:SI (match_dup 1) (match_dup 2)))]
3510 "TARGET_68020 && !TARGET_5200"
3513 if (find_reg_note (insn, REG_UNUSED, operands[3]))
3514 return \"divu%.l %2,%0\";
3516 return \"divul%.l %2,%3:%0\";
3519 (define_insn "divmodhi4"
3520 [(set (match_operand:HI 0 "general_operand" "=d")
3521 (div:HI (match_operand:HI 1 "general_operand" "0")
3522 (match_operand:HI 2 "general_operand" "dmsK")))
3523 (set (match_operand:HI 3 "general_operand" "=d")
3524 (mod:HI (match_dup 1) (match_dup 2)))]
3529 output_asm_insn (\"ext%.l %0\;divs%.w %2,%0\", operands);
3531 output_asm_insn (\"extl %0\;divs %2,%0\", operands);
3533 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3536 return \"move%.l %0,%3\;swap %3\";
3542 (define_insn "udivmodhi4"
3543 [(set (match_operand:HI 0 "general_operand" "=d")
3544 (udiv:HI (match_operand:HI 1 "general_operand" "0")
3545 (match_operand:HI 2 "general_operand" "dmsK")))
3546 (set (match_operand:HI 3 "general_operand" "=d")
3547 (umod:HI (match_dup 1) (match_dup 2)))]
3552 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu%.w %2,%0\", operands);
3554 output_asm_insn (\"and%.l %#0xFFFF,%0\;divu %2,%0\", operands);
3556 if (!find_reg_note(insn, REG_UNUSED, operands[3]))
3559 return \"move%.l %0,%3\;swap %3\";
3565 ;; logical-and instructions
3567 ;; "anddi3" is mainly here to help combine().
3568 (define_insn "anddi3"
3569 [(set (match_operand:DI 0 "general_operand" "=o,d")
3570 (and:DI (match_operand:DI 1 "general_operand" "%0,0")
3571 (match_operand:DI 2 "general_operand" "dn,don")))]
3576 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3577 if (GET_CODE (operands[2]) == CONST_DOUBLE
3578 || GET_CODE (operands[2]) == CONST_INT)
3582 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3584 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3585 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3590 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3592 switch (INTVAL (hi))
3595 output_asm_insn (\"clr%.l %0\", operands);
3603 xoperands[0] = operands[0];
3605 output_asm_insn (output_andsi3 (xoperands), xoperands);
3608 if (GET_CODE (operands[0]) == REG)
3609 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3611 operands[0] = adj_offsettable_operand (operands[0], 4);
3612 switch (INTVAL (lo))
3615 output_asm_insn (\"clr%.l %0\", operands);
3623 xoperands[0] = operands[0];
3625 output_asm_insn (output_andsi3 (xoperands), xoperands);
3630 if (GET_CODE (operands[0]) != REG)
3632 operands[1] = adj_offsettable_operand (operands[0], 4);
3633 return \"and%.l %2,%0\;and%.l %R2,%1\";
3635 if (GET_CODE (operands[2]) != REG)
3637 operands[1] = adj_offsettable_operand (operands[2], 4);
3638 return \"and%.l %2,%0\;and%.l %1,%R0\";
3640 return \"and%.l %2,%0\;and%.l %R2,%R0\";
3643 ;; Prevent AND from being made with sp. This doesn't exist in the machine
3644 ;; and reload will cause inefficient code. Since sp is a FIXED_REG, we
3645 ;; can't allocate pseudos into it.
3647 (define_expand "andsi3"
3648 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3649 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3650 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3654 (define_insn "andsi3_internal"
3655 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3656 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3657 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3661 return output_andsi3 (operands);
3664 (define_insn "andsi3_5200"
3665 [(set (match_operand:SI 0 "not_sp_operand" "=m,d")
3666 (and:SI (match_operand:SI 1 "general_operand" "%0,0")
3667 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3671 (define_insn "andhi3"
3672 [(set (match_operand:HI 0 "general_operand" "=m,d")
3673 (and:HI (match_operand:HI 1 "general_operand" "%0,0")
3674 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3679 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3680 (and:HI (match_dup 0)
3681 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3686 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3687 (and:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3692 (define_insn "andqi3"
3693 [(set (match_operand:QI 0 "general_operand" "=m,d")
3694 (and:QI (match_operand:QI 1 "general_operand" "%0,0")
3695 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3700 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3701 (and:QI (match_dup 0)
3702 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3707 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3708 (and:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3713 ;; inclusive-or instructions
3715 (define_insn "iordi_zext"
3716 [(set (match_operand:DI 0 "general_operand" "=o,d")
3717 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn"))
3718 (match_operand:DI 2 "general_operand" "0,0")))]
3725 if (GET_CODE (operands[0]) == REG)
3726 operands[0] = gen_rtx (REG, SImode, REGNO (operands[0]) + 1);
3728 operands[0] = adj_offsettable_operand (operands[0], 4);
3729 if (GET_MODE (operands[1]) == SImode)
3730 return \"or%.l %1,%0\";
3731 byte_mode = (GET_MODE (operands[1]) == QImode);
3732 if (GET_CODE (operands[0]) == MEM)
3733 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3735 return \"or%.b %1,%0\";
3737 return \"or%.w %1,%0\";
3740 ;; "iordi3" is mainly here to help combine().
3741 (define_insn "iordi3"
3742 [(set (match_operand:DI 0 "general_operand" "=o,d")
3743 (ior:DI (match_operand:DI 1 "general_operand" "%0,0")
3744 (match_operand:DI 2 "general_operand" "dn,don")))]
3749 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3750 if (GET_CODE (operands[2]) == CONST_DOUBLE
3751 || GET_CODE (operands[2]) == CONST_INT)
3755 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3757 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3758 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3763 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3765 switch (INTVAL (hi))
3770 /* FIXME : a scratch register would be welcome here if operand[0]
3771 is not a register */
3772 output_asm_insn (\"move%.l %#-1,%0\", operands);
3778 xoperands[0] = operands[0];
3780 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3783 if (GET_CODE (operands[0]) == REG)
3784 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3786 operands[0] = adj_offsettable_operand (operands[0], 4);
3787 switch (INTVAL (lo))
3792 /* FIXME : a scratch register would be welcome here if operand[0]
3793 is not a register */
3794 output_asm_insn (\"move%.l %#-1,%R0\", operands);
3800 xoperands[0] = operands[0];
3802 output_asm_insn (output_iorsi3 (xoperands), xoperands);
3807 if (GET_CODE (operands[0]) != REG)
3809 operands[1] = adj_offsettable_operand (operands[0], 4);
3810 return \"or%.l %2,%0\;or%.l %R2,%1\";
3812 if (GET_CODE (operands[2]) != REG)
3814 operands[1] = adj_offsettable_operand (operands[2], 4);
3815 return \"or%.l %2,%0\;or%.l %1,%R0\";
3817 return \"or%.l %2,%0\;or%.l %R2,%R0\";
3820 (define_expand "iorsi3"
3821 [(set (match_operand:SI 0 "general_operand" "")
3822 (ior:SI (match_operand:SI 1 "general_operand" "")
3823 (match_operand:SI 2 "general_operand" "")))]
3827 (define_insn "iorsi3_internal"
3828 [(set (match_operand:SI 0 "general_operand" "=m,d")
3829 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3830 (match_operand:SI 2 "general_operand" "dKs,dmMs")))]
3834 return output_iorsi3 (operands);
3837 (define_insn "iorsi3_5200"
3838 [(set (match_operand:SI 0 "general_operand" "=m,d")
3839 (ior:SI (match_operand:SI 1 "general_operand" "%0,0")
3840 (match_operand:SI 2 "general_operand" "d,dmsK")))]
3844 (define_insn "iorhi3"
3845 [(set (match_operand:HI 0 "general_operand" "=m,d")
3846 (ior:HI (match_operand:HI 1 "general_operand" "%0,0")
3847 (match_operand:HI 2 "general_operand" "dn,dmn")))]
3852 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3853 (ior:HI (match_dup 0)
3854 (match_operand:HI 1 "general_operand" "dn,dmn")))]
3859 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+m,d"))
3860 (ior:HI (match_operand:HI 1 "general_operand" "dn,dmn")
3865 (define_insn "iorqi3"
3866 [(set (match_operand:QI 0 "general_operand" "=m,d")
3867 (ior:QI (match_operand:QI 1 "general_operand" "%0,0")
3868 (match_operand:QI 2 "general_operand" "dn,dmn")))]
3873 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3874 (ior:QI (match_dup 0)
3875 (match_operand:QI 1 "general_operand" "dn,dmn")))]
3880 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+m,d"))
3881 (ior:QI (match_operand:QI 1 "general_operand" "dn,dmn")
3886 ;; On all 68k models, this makes faster code in a special case.
3887 ;; See also ashlsi_16, ashrsi_16 and lshrsi_16.
3889 (define_insn "iorsi_zexthi_ashl16"
3890 [(set (match_operand:SI 0 "general_operand" "=&d")
3891 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn"))
3892 (ashift:SI (match_operand:SI 2 "general_operand" "or")
3898 if (GET_CODE (operands[2]) != REG)
3899 operands[2] = adj_offsettable_operand (operands[2], 2);
3900 if (GET_CODE (operands[2]) != REG
3901 || REGNO (operands[2]) != REGNO (operands[0]))
3902 output_asm_insn (\"move%.w %2,%0\", operands);
3903 return \"swap %0\;mov%.w %1,%0\";
3906 (define_insn "iorsi_zext"
3907 [(set (match_operand:SI 0 "general_operand" "=o,d")
3908 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn"))
3909 (match_operand:SI 2 "general_operand" "0,0")))]
3916 byte_mode = (GET_MODE (operands[1]) == QImode);
3917 if (GET_CODE (operands[0]) == MEM)
3918 operands[0] = adj_offsettable_operand (operands[0], byte_mode ? 3 : 2);
3920 return \"or%.b %1,%0\";
3922 return \"or%.w %1,%0\";
3927 ;; "xordi3" is mainly here to help combine().
3928 (define_insn "xordi3"
3929 [(set (match_operand:DI 0 "general_operand" "=od")
3930 (xor:DI (match_operand:DI 1 "general_operand" "%0")
3931 (match_operand:DI 2 "general_operand" "dn")))]
3936 /* We can get CONST_DOUBLE, but also const1_rtx etc. */
3937 if (GET_CODE (operands[2]) == CONST_DOUBLE
3938 || GET_CODE (operands[2]) == CONST_INT)
3942 if (GET_CODE (operands[2]) == CONST_DOUBLE)
3944 hi = GEN_INT (CONST_DOUBLE_HIGH (operands[2]));
3945 lo = GEN_INT (CONST_DOUBLE_LOW (operands[2]));
3950 hi = INTVAL (lo) < 0 ? constm1_rtx : const0_rtx;
3952 switch (INTVAL (hi))
3957 output_asm_insn (\"not%.l %0\", operands);
3960 /* FIXME : a scratch register would be welcome here if
3961 -128 <= INTVAL (hi) < -1 */
3965 xoperands[0] = operands[0];
3967 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3970 if (GET_CODE (operands[0]) == REG)
3971 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
3973 operands[0] = adj_offsettable_operand (operands[0], 4);
3974 switch (INTVAL (lo))
3979 output_asm_insn (\"not%.l %0\", operands);
3982 /* FIXME : a scratch register would be welcome here if
3983 -128 <= INTVAL (lo) < -1 */
3985 /* FIXME : this should be merged with xorsi3 */
3989 xoperands[0] = operands[0];
3991 output_asm_insn (output_xorsi3 (xoperands), xoperands);
3996 if (GET_CODE (operands[0]) != REG)
3998 operands[1] = adj_offsettable_operand (operands[0], 4);
3999 return \"eor%.l %2,%0\;eor%.l %R2,%1\";
4001 if (GET_CODE (operands[2]) != REG)
4003 operands[1] = adj_offsettable_operand (operands[2], 4);
4004 return \"eor%.l %2,%0\;eor%.l %1,%R0\";
4006 return \"eor%.l %2,%0\;eor%.l %R2,%R0\";
4009 (define_expand "xorsi3"
4010 [(set (match_operand:SI 0 "general_operand" "")
4011 (xor:SI (match_operand:SI 1 "general_operand" "")
4012 (match_operand:SI 2 "general_operand" "")))]
4016 (define_insn "xorsi3_internal"
4017 [(set (match_operand:SI 0 "general_operand" "=do,m")
4018 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4019 (match_operand:SI 2 "general_operand" "di,dKs")))]
4023 return output_xorsi3 (operands);
4026 (define_insn "xorsi3_5200"
4027 [(set (match_operand:SI 0 "general_operand" "=dm,d")
4028 (xor:SI (match_operand:SI 1 "general_operand" "%0,0")
4029 (match_operand:SI 2 "general_operand" "d,Ks")))]
4033 (define_insn "xorhi3"
4034 [(set (match_operand:HI 0 "general_operand" "=dm")
4035 (xor:HI (match_operand:HI 1 "general_operand" "%0")
4036 (match_operand:HI 2 "general_operand" "dn")))]
4041 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4042 (xor:HI (match_dup 0)
4043 (match_operand:HI 1 "general_operand" "dn")))]
4048 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4049 (xor:HI (match_operand:HI 1 "general_operand" "dn")
4054 (define_insn "xorqi3"
4055 [(set (match_operand:QI 0 "general_operand" "=dm")
4056 (xor:QI (match_operand:QI 1 "general_operand" "%0")
4057 (match_operand:QI 2 "general_operand" "dn")))]
4062 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4063 (xor:QI (match_dup 0)
4064 (match_operand:QI 1 "general_operand" "dn")))]
4069 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4070 (xor:QI (match_operand:QI 1 "general_operand" "dn")
4075 ;; negation instructions
4077 (define_expand "negdi2"
4078 [(set (match_operand:DI 0 "general_operand" "")
4079 (neg:DI (match_operand:DI 1 "general_operand" "")))]
4084 emit_insn (gen_negdi2_5200 (operands[0], operands[1]));
4086 emit_insn (gen_negdi2_internal (operands[0], operands[1]));
4090 (define_insn "negdi2_internal"
4091 [(set (match_operand:DI 0 "general_operand" "=<,do,!*a")
4092 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))]
4096 if (which_alternative == 0)
4097 return \"neg%.l %0\;negx%.l %0\";
4098 if (GET_CODE (operands[0]) == REG)
4099 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4101 operands[1] = adj_offsettable_operand (operands[0], 4);
4102 if (ADDRESS_REG_P (operands[0]))
4103 return \"exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0\";
4105 return \"neg%.l %1\;negx%.l %0\";
4108 (define_insn "negdi2_5200"
4109 [(set (match_operand:DI 0 "general_operand" "=d")
4110 (neg:DI (match_operand:DI 1 "general_operand" "0")))]
4114 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4115 return \"neg%.l %1\;negx%.l %0\";
4118 (define_expand "negsi2"
4119 [(set (match_operand:SI 0 "general_operand" "")
4120 (neg:SI (match_operand:SI 1 "general_operand" "")))]
4125 emit_insn (gen_negsi2_5200 (operands[0], operands[1]));
4127 emit_insn (gen_negsi2_internal (operands[0], operands[1]));
4131 (define_insn "negsi2_internal"
4132 [(set (match_operand:SI 0 "general_operand" "=dm")
4133 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4137 (define_insn "negsi2_5200"
4138 [(set (match_operand:SI 0 "general_operand" "=d")
4139 (neg:SI (match_operand:SI 1 "general_operand" "0")))]
4143 (define_insn "neghi2"
4144 [(set (match_operand:HI 0 "general_operand" "=dm")
4145 (neg:HI (match_operand:HI 1 "general_operand" "0")))]
4150 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4151 (neg:HI (match_dup 0)))]
4155 (define_insn "negqi2"
4156 [(set (match_operand:QI 0 "general_operand" "=dm")
4157 (neg:QI (match_operand:QI 1 "general_operand" "0")))]
4162 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4163 (neg:QI (match_dup 0)))]
4167 ;; If using software floating point, just flip the sign bit.
4169 (define_expand "negsf2"
4170 [(set (match_operand:SF 0 "general_operand" "")
4171 (neg:SF (match_operand:SF 1 "general_operand" "")))]
4175 if (!TARGET_FPA && !TARGET_68881)
4180 target = operand_subword_force (operands[0], 0, SFmode);
4181 result = expand_binop (SImode, xor_optab,
4182 operand_subword_force (operands[1], 0, SFmode),
4183 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4187 if (result != target)
4188 emit_move_insn (result, target);
4190 /* Make a place for REG_EQUAL. */
4191 emit_move_insn (operands[0], operands[0]);
4197 [(set (match_operand:SF 0 "general_operand" "=x,y")
4198 (neg:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4203 [(set (match_operand:SF 0 "general_operand" "=f,d")
4204 (neg:SF (match_operand:SF 1 "general_operand" "fdmF,0")))]
4208 if (DATA_REG_P (operands[0]))
4210 operands[1] = GEN_INT (31);
4211 return \"bchg %1,%0\";
4213 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4214 return \"f%$neg%.x %1,%0\";
4215 return \"f%$neg%.s %f1,%0\";
4218 (define_expand "negdf2"
4219 [(set (match_operand:DF 0 "general_operand" "")
4220 (neg:DF (match_operand:DF 1 "general_operand" "")))]
4224 if (!TARGET_FPA && !TARGET_68881)
4231 target = operand_subword (operands[0], 0, 1, DFmode);
4232 result = expand_binop (SImode, xor_optab,
4233 operand_subword_force (operands[1], 0, DFmode),
4234 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
4238 if (result != target)
4239 emit_move_insn (result, target);
4241 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4242 operand_subword_force (operands[1], 1, DFmode));
4244 insns = get_insns ();
4247 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4253 [(set (match_operand:DF 0 "general_operand" "=x,y")
4254 (neg:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4259 [(set (match_operand:DF 0 "general_operand" "=f,d")
4260 (neg:DF (match_operand:DF 1 "general_operand" "fmF,0")))]
4264 if (DATA_REG_P (operands[0]))
4266 operands[1] = GEN_INT (31);
4267 return \"bchg %1,%0\";
4269 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4270 return \"f%&neg%.x %1,%0\";
4271 return \"f%&neg%.d %f1,%0\";
4274 ;; Sqrt instruction for the 68881
4276 (define_insn "sqrtsf2"
4277 [(set (match_operand:SF 0 "general_operand" "=f")
4278 (sqrt:SF (match_operand:SF 1 "general_operand" "fm")))]
4282 if (FP_REG_P (operands[1]))
4283 return \"f%$sqrt%.x %1,%0\";
4285 return \"f%$sqrt%.s %1,%0\";
4288 (define_insn "sqrtdf2"
4289 [(set (match_operand:DF 0 "general_operand" "=f")
4290 (sqrt:DF (match_operand:DF 1 "general_operand" "fm")))]
4294 if (FP_REG_P (operands[1]))
4295 return \"f%&sqrt%.x %1,%0\";
4297 return \"f%&sqrt%.d %1,%0\";
4300 ;; Absolute value instructions
4301 ;; If using software floating point, just zero the sign bit.
4303 (define_expand "abssf2"
4304 [(set (match_operand:SF 0 "general_operand" "")
4305 (abs:SF (match_operand:SF 1 "general_operand" "")))]
4309 if (!TARGET_FPA && !TARGET_68881)
4314 target = operand_subword_force (operands[0], 0, SFmode);
4315 result = expand_binop (SImode, and_optab,
4316 operand_subword_force (operands[1], 0, SFmode),
4317 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4321 if (result != target)
4322 emit_move_insn (result, target);
4324 /* Make a place for REG_EQUAL. */
4325 emit_move_insn (operands[0], operands[0]);
4331 [(set (match_operand:SF 0 "general_operand" "=x,y")
4332 (abs:SF (match_operand:SF 1 "general_operand" "xH,rmF")))]
4337 [(set (match_operand:SF 0 "general_operand" "=f")
4338 (abs:SF (match_operand:SF 1 "general_operand" "fdmF")))]
4342 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4343 return \"f%$abs%.x %1,%0\";
4344 return \"f%$abs%.s %f1,%0\";
4347 (define_expand "absdf2"
4348 [(set (match_operand:DF 0 "general_operand" "")
4349 (abs:DF (match_operand:DF 1 "general_operand" "")))]
4353 if (!TARGET_FPA && !TARGET_68881)
4360 target = operand_subword (operands[0], 0, 1, DFmode);
4361 result = expand_binop (SImode, and_optab,
4362 operand_subword_force (operands[1], 0, DFmode),
4363 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
4367 if (result != target)
4368 emit_move_insn (result, target);
4370 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode),
4371 operand_subword_force (operands[1], 1, DFmode));
4373 insns = get_insns ();
4376 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
4382 [(set (match_operand:DF 0 "general_operand" "=x,y")
4383 (abs:DF (match_operand:DF 1 "general_operand" "xH,rmF")))]
4388 [(set (match_operand:DF 0 "general_operand" "=f")
4389 (abs:DF (match_operand:DF 1 "general_operand" "fmF")))]
4393 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
4394 return \"f%&abs%.x %1,%0\";
4395 return \"f%&abs%.d %f1,%0\";
4398 ;; one complement instructions
4400 ;; "one_cmpldi2" is mainly here to help combine().
4401 (define_insn "one_cmpldi2"
4402 [(set (match_operand:DI 0 "general_operand" "=dm")
4403 (not:DI (match_operand:DI 1 "general_operand" "0")))]
4408 if (GET_CODE (operands[0]) == REG)
4409 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4410 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC
4411 || GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4412 operands[1] = operands[0];
4414 operands[1] = adj_offsettable_operand (operands[0], 4);
4415 return \"not%.l %1\;not%.l %0\";
4418 (define_expand "one_cmplsi2"
4419 [(set (match_operand:SI 0 "general_operand" "")
4420 (not:SI (match_operand:SI 1 "general_operand" "")))]
4425 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1]));
4427 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1]));
4431 (define_insn "one_cmplsi2_internal"
4432 [(set (match_operand:SI 0 "general_operand" "=dm")
4433 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4437 (define_insn "one_cmplsi2_5200"
4438 [(set (match_operand:SI 0 "general_operand" "=d")
4439 (not:SI (match_operand:SI 1 "general_operand" "0")))]
4443 (define_insn "one_cmplhi2"
4444 [(set (match_operand:HI 0 "general_operand" "=dm")
4445 (not:HI (match_operand:HI 1 "general_operand" "0")))]
4450 [(set (strict_low_part (match_operand:HI 0 "general_operand" "+dm"))
4451 (not:HI (match_dup 0)))]
4455 (define_insn "one_cmplqi2"
4456 [(set (match_operand:QI 0 "general_operand" "=dm")
4457 (not:QI (match_operand:QI 1 "general_operand" "0")))]
4462 [(set (strict_low_part (match_operand:QI 0 "general_operand" "+dm"))
4463 (not:QI (match_dup 0)))]
4467 ;; arithmetic shift instructions
4468 ;; We don't need the shift memory by 1 bit instruction
4470 (define_insn "ashldi_extsi"
4471 [(set (match_operand:DI 0 "general_operand" "=ro")
4473 (match_operator:DI 2 "extend_operator"
4474 [(match_operand:SI 1 "general_operand" "rm")])
4480 if (GET_CODE (operands[0]) == REG)
4481 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4483 operands[2] = adj_offsettable_operand (operands[0], 4);
4484 if (ADDRESS_REG_P (operands[0]))
4485 return \"move%.l %1,%0\;sub%.l %2,%2\";
4487 return \"move%.l %1,%0\;clr%.l %2\";
4490 (define_insn "ashldi_sexthi"
4491 [(set (match_operand:DI 0 "general_operand" "=m,a*d")
4492 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm"))
4494 (clobber (match_scratch:SI 2 "=a,X"))]
4499 if (GET_CODE (operands[0]) == MEM)
4501 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4502 return \"clr%.l %0\;move%.w %1,%2\;move%.l %2,%0\";
4503 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4504 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %0\";
4507 operands[3] = adj_offsettable_operand (operands[0], 4);
4508 return \"move%.w %1,%2\;move%.l %2,%0\;clr%.l %3\";
4511 else if (DATA_REG_P (operands[0]))
4512 return \"move%.w %1,%0\;ext%.l %0\;clr%.l %R0\";
4514 return \"move%.w %1,%0\;sub%.l %R0,%R0\";
4517 (define_insn "ashldi_const32"
4518 [(set (match_operand:DI 0 "general_operand" "=rm")
4519 (ashift:DI (match_operand:DI 1 "general_operand" "ro")
4525 if (GET_CODE (operands[1]) == REG)
4526 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4528 operands[3] = adj_offsettable_operand (operands[1], 4);
4529 if (GET_CODE (operands[0]) == REG)
4530 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4531 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC)
4532 return \"clr%.l %0\;move%.l %3,%0\";
4533 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC)
4534 return \"move%.l %3,%0\;clr%.l %0\";
4536 operands[2] = adj_offsettable_operand (operands[0], 4);
4537 if (ADDRESS_REG_P (operands[2]))
4538 return \"move%.l %3,%0\;sub%.l %2,%2\";
4540 return \"move%.l %3,%0\;clr%.l %2\";
4543 ;; The predicate below must be general_operand, because ashldi3 allows that
4544 (define_insn "ashldi_const"
4545 [(set (match_operand:DI 0 "general_operand" "=d")
4546 (ashift:DI (match_operand:DI 1 "general_operand" "0")
4547 (match_operand 2 "const_int_operand" "n")))]
4548 "((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4549 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4550 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4553 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4554 if (INTVAL (operands[2]) == 1)
4555 return \"add%.l %1,%1\;addx%.l %0,%0\";
4556 else if (INTVAL (operands[2]) == 8)
4557 return \"rol%.l %#8,%1\;rol%.l %#8,%0\;move%.b %1,%0\;clr%.b %1\";
4558 else if (INTVAL (operands[2]) == 16)
4559 return \"swap %1\;swap %0\;move%.w %1,%0\;clr%.w %1\";
4560 else if (INTVAL (operands[2]) == 48)
4561 return \"mov%.l %1,%0\;swap %0\;clr%.l %1\;clr%.w %0\";
4562 else if (INTVAL (operands[2]) == 2)
4563 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4564 else if (INTVAL (operands[2]) == 3)
4565 return \"add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\;add%.l %1,%1\;addx%.l %0,%0\";
4566 else /* 32 < INTVAL (operands[2]) <= 63 */
4568 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4569 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asl%.l %2,%1\" :
4570 \"moveq %2,%0\;asl%.l %0,%1\", operands);
4571 return \"mov%.l %1,%0\;moveq %#0,%1\";
4575 (define_expand "ashldi3"
4576 [(set (match_operand:DI 0 "general_operand" "")
4577 (ashift:DI (match_operand:DI 1 "general_operand" "")
4578 (match_operand 2 "const_int_operand" "")))]
4582 if (GET_CODE (operands[2]) != CONST_INT
4583 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4584 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4585 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4589 ;; On most 68k models, this makes faster code in a special case.
4591 (define_insn "ashlsi_16"
4592 [(set (match_operand:SI 0 "register_operand" "=d")
4593 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4599 return \"swap %0\;clr%.w %0\";
4602 ;; ashift patterns : use lsl instead of asl, because lsl always clears the
4603 ;; overflow bit, so we must not set CC_NO_OVERFLOW.
4605 ;; On the 68000, this makes faster code in a special case.
4607 (define_insn "ashlsi_17_24"
4608 [(set (match_operand:SI 0 "register_operand" "=d")
4609 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4610 (match_operand:SI 2 "const_int_operand" "n")))]
4611 "(! TARGET_68020 && !TARGET_5200
4612 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4617 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4618 return \"lsl%.w %2,%0\;swap %0\;clr%.w %0\";
4621 (define_insn "ashlsi3"
4622 [(set (match_operand:SI 0 "register_operand" "=d")
4623 (ashift:SI (match_operand:SI 1 "register_operand" "0")
4624 (match_operand:SI 2 "general_operand" "dI")))]
4628 if (operands[2] == const1_rtx)
4630 cc_status.flags = CC_NO_OVERFLOW;
4631 return \"add%.l %0,%0\";
4633 return \"lsl%.l %2,%0\";
4636 (define_insn "ashlhi3"
4637 [(set (match_operand:HI 0 "register_operand" "=d")
4638 (ashift:HI (match_operand:HI 1 "register_operand" "0")
4639 (match_operand:HI 2 "general_operand" "dI")))]
4644 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4645 (ashift:HI (match_dup 0)
4646 (match_operand:HI 1 "general_operand" "dI")))]
4650 (define_insn "ashlqi3"
4651 [(set (match_operand:QI 0 "register_operand" "=d")
4652 (ashift:QI (match_operand:QI 1 "register_operand" "0")
4653 (match_operand:QI 2 "general_operand" "dI")))]
4658 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4659 (ashift:QI (match_dup 0)
4660 (match_operand:QI 1 "general_operand" "dI")))]
4664 ;; On most 68k models, this makes faster code in a special case.
4666 (define_insn "ashrsi_16"
4667 [(set (match_operand:SI 0 "register_operand" "=d")
4668 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4671 "swap %0\;ext%.l %0")
4673 ;; On the 68000, this makes faster code in a special case.
4676 [(set (match_operand:SI 0 "register_operand" "=d")
4677 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4678 (match_operand:SI 2 "const_int_operand" "n")))]
4679 "(! TARGET_68020 && !TARGET_5200
4680 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4683 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
4684 return \"swap %0\;asr%.w %2,%0\;ext%.l %0\";
4687 (define_insn "subreghi1ashrdi_const32"
4688 [(set (match_operand:HI 0 "general_operand" "=rm")
4689 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4690 (const_int 32)) 1))]
4694 if (GET_CODE (operands[1]) != REG)
4695 operands[1] = adj_offsettable_operand (operands[1], 2);
4696 return \"move%.w %1,%0\";
4699 (define_insn "subregsi1ashrdi_const32"
4700 [(set (match_operand:SI 0 "general_operand" "=rm")
4701 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4702 (const_int 32)) 1))]
4706 return \"move%.l %1,%0\";
4709 (define_insn "ashrdi_const32"
4710 [(set (match_operand:DI 0 "register_operand" "=d")
4711 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4717 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4719 return \"move%.l %1,%2\;smi %0\;extb%.l %0\";
4721 return \"move%.l %1,%2\;smi %0\;ext%.w %0\;ext%.l %0\";
4724 (define_insn "ashrdi_const32_mem"
4725 [(set (match_operand:DI 0 "general_operand" "=o,<")
4726 (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro")
4728 (clobber (match_scratch:SI 2 "=d,d"))]
4733 if (which_alternative == 1)
4734 operands[3] = operands[0];
4736 operands[3] = adj_offsettable_operand (operands[0], 4);
4738 return \"move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0\";
4740 return \"move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\";
4743 ;; The predicate below must be general_operand, because ashrdi3 allows that
4744 (define_insn "ashrdi_const"
4745 [(set (match_operand:DI 0 "general_operand" "=d")
4746 (ashiftrt:DI (match_operand:DI 1 "general_operand" "0")
4747 (match_operand 2 "const_int_operand" "n")))]
4749 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4750 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4751 || INTVAL (operands[2]) == 31
4752 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4755 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4756 if (INTVAL (operands[2]) == 63)
4757 return \"add%.l %0,%0\;subx%.l %0,%0\;move%.l %0,%1\";
4759 if (INTVAL (operands[2]) == 1)
4760 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\";
4761 else if (INTVAL (operands[2]) == 8)
4762 return \"move%.b %0,%1\;asr%.l %#8,%0\;ror%.l %#8,%1\";
4763 else if (INTVAL (operands[2]) == 16)
4764 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;ext%.l %0\";
4765 else if (INTVAL (operands[2]) == 48)
4766 return \"swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0\";
4767 else if (INTVAL (operands[2]) == 31)
4768 return \"add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0\";
4769 else if (INTVAL (operands[2]) == 2)
4770 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4771 else if (INTVAL (operands[2]) == 3)
4772 return \"asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\;asr%.l %#1,%0\;roxr%.l %#1,%1\";
4773 else /* 32 < INTVAL (operands[2]) <= 63 */
4775 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4776 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"asr%.l %2,%0\" :
4777 \"moveq %2,%1\;asr%.l %1,%0\", operands);
4778 output_asm_insn (\"mov%.l %0,%1\;smi %0\", operands);
4779 return INTVAL (operands[2]) >= 15 ? \"ext%.w %d0\" :
4780 TARGET_68020 ? \"extb%.l %0\" : \"ext%.w %0\;ext%.l %0\";
4784 (define_expand "ashrdi3"
4785 [(set (match_operand:DI 0 "general_operand" "")
4786 (ashiftrt:DI (match_operand:DI 1 "general_operand" "")
4787 (match_operand 2 "const_int_operand" "")))]
4791 if (GET_CODE (operands[2]) != CONST_INT
4792 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4793 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4794 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63)))
4798 ;; On all 68k models, this makes faster code in a special case.
4800 (define_insn "ashrsi_31"
4801 [(set (match_operand:SI 0 "register_operand" "=d")
4802 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4807 return \"add%.l %0,%0\;subx%.l %0,%0\";
4810 (define_insn "ashrsi3"
4811 [(set (match_operand:SI 0 "register_operand" "=d")
4812 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0")
4813 (match_operand:SI 2 "general_operand" "dI")))]
4817 (define_insn "ashrhi3"
4818 [(set (match_operand:HI 0 "register_operand" "=d")
4819 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0")
4820 (match_operand:HI 2 "general_operand" "dI")))]
4825 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
4826 (ashiftrt:HI (match_dup 0)
4827 (match_operand:HI 1 "general_operand" "dI")))]
4831 (define_insn "ashrqi3"
4832 [(set (match_operand:QI 0 "register_operand" "=d")
4833 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0")
4834 (match_operand:QI 2 "general_operand" "dI")))]
4839 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
4840 (ashiftrt:QI (match_dup 0)
4841 (match_operand:QI 1 "general_operand" "dI")))]
4845 ;; logical shift instructions
4847 ;; commented out because of reload problems in 950612-1.c
4850 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4851 ;; (const_int 32)) 1))
4852 ;; (set (match_operand:SI 1 "general_operand" "=dm")
4853 ;; (subreg:SI (lshiftrt:DI (match_dup 0)
4854 ;; (const_int 32)) 1))]
4858 ;; return \"move%.l %0,%1\";
4863 ;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro")
4864 ;; (const_int 32)) 0))
4865 ;; (set (match_operand:DI 1 "general_operand" "=do")
4866 ;; (lshiftrt:DI (match_dup 0)
4867 ;; (const_int 32)))]
4871 ;; if (GET_CODE (operands[1]) == REG)
4872 ;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4874 ;; operands[2] = adj_offsettable_operand (operands[1], 4);
4875 ;; return \"move%.l %0,%2\;clr%.l %1\";
4878 (define_insn "subreg1lshrdi_const32"
4879 [(set (match_operand:SI 0 "general_operand" "=rm")
4880 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro")
4881 (const_int 32)) 1))]
4885 return \"move%.l %1,%0\";
4888 (define_insn "lshrdi_const32"
4889 [(set (match_operand:DI 0 "general_operand" "=ro,<,>")
4890 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,ro,ro")
4896 if (which_alternative == 1)
4897 return \"move%.l %1,%0\;clr%.l %0\";
4898 if (which_alternative == 2)
4899 return \"clr%.l %0\;move%.l %1,%0\";
4900 if (GET_CODE (operands[0]) == REG)
4901 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4903 operands[2] = adj_offsettable_operand (operands[0], 4);
4904 if (GET_CODE (operands[1]) == REG)
4905 operands[3] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
4907 operands[3] = adj_offsettable_operand (operands[1], 4);
4908 if (ADDRESS_REG_P (operands[0]))
4909 return \"move%.l %1,%2\;sub%.l %0,%0\";
4911 return \"move%.l %1,%2\;clr%.l %0\";
4914 ;; The predicate below must be general_operand, because lshrdi3 allows that
4915 (define_insn "lshrdi_const"
4916 [(set (match_operand:DI 0 "general_operand" "=d")
4917 (lshiftrt:DI (match_operand:DI 1 "general_operand" "0")
4918 (match_operand 2 "const_int_operand" "n")))]
4920 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3)
4921 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16
4922 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))"
4925 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
4926 if (INTVAL (operands[2]) == 63)
4927 return \"add%.l %0,%0\;clr%.l %0\;clr%.l %1\;addx%.l %1,%1\";
4929 if (INTVAL (operands[2]) == 1)
4930 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4931 else if (INTVAL (operands[2]) == 8)
4932 return \"move%.b %0,%1\;lsr%.l %#8,%0\;ror%.l %#8,%1\";
4933 else if (INTVAL (operands[2]) == 16)
4934 return \"move%.w %0,%1\;clr%.w %0\;swap %1\;swap %0\";
4935 else if (INTVAL (operands[2]) == 48)
4936 return \"move%.l %0,%1\;clr%.w %1\;clr%.l %0\;swap %1\";
4937 else if (INTVAL (operands[2]) == 2)
4938 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4939 else if (INTVAL (operands[2]) == 3)
4940 return \"lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\;lsr%.l %#1,%0\;roxr%.l %#1,%1\";
4941 else /* 32 < INTVAL (operands[2]) <= 63 */
4943 operands[2] = GEN_INT (INTVAL (operands[2]) - 32);
4944 output_asm_insn (INTVAL (operands[2]) <= 8 ? \"lsr%.l %2,%0\" :
4945 \"moveq %2,%1\;lsr%.l %1,%0\", operands);
4946 return \"mov%.l %0,%1\;moveq %#0,%0\";
4950 (define_expand "lshrdi3"
4951 [(set (match_operand:DI 0 "general_operand" "")
4952 (lshiftrt:DI (match_operand:DI 1 "general_operand" "")
4953 (match_operand 2 "const_int_operand" "")))]
4957 if (GET_CODE (operands[2]) != CONST_INT
4958 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3)
4959 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16
4960 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63)))
4964 ;; On all 68k models, this makes faster code in a special case.
4966 (define_insn "lshrsi_31"
4967 [(set (match_operand:SI 0 "register_operand" "=d")
4968 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4973 return \"add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0\";
4976 ;; On most 68k models, this makes faster code in a special case.
4978 (define_insn "lshrsi_16"
4979 [(set (match_operand:SI 0 "register_operand" "=d")
4980 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4986 return \"clr%.w %0\;swap %0\";
4989 ;; On the 68000, this makes faster code in a special case.
4991 (define_insn "lshrsi_17_24"
4992 [(set (match_operand:SI 0 "register_operand" "=d")
4993 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
4994 (match_operand:SI 2 "const_int_operand" "n")))]
4995 "(! TARGET_68020 && !TARGET_5200
4996 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 24)"
4999 /* I think lsr%.w sets the CC properly. */
5000 operands[2] = GEN_INT (INTVAL (operands[2]) - 16);
5001 return \"clr%.w %0\;swap %0\;lsr%.w %2,%0\";
5004 (define_insn "lshrsi3"
5005 [(set (match_operand:SI 0 "register_operand" "=d")
5006 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0")
5007 (match_operand:SI 2 "general_operand" "dI")))]
5011 (define_insn "lshrhi3"
5012 [(set (match_operand:HI 0 "register_operand" "=d")
5013 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0")
5014 (match_operand:HI 2 "general_operand" "dI")))]
5019 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5020 (lshiftrt:HI (match_dup 0)
5021 (match_operand:HI 1 "general_operand" "dI")))]
5025 (define_insn "lshrqi3"
5026 [(set (match_operand:QI 0 "register_operand" "=d")
5027 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0")
5028 (match_operand:QI 2 "general_operand" "dI")))]
5033 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5034 (lshiftrt:QI (match_dup 0)
5035 (match_operand:QI 1 "general_operand" "dI")))]
5039 ;; rotate instructions
5041 (define_insn "rotlsi3"
5042 [(set (match_operand:SI 0 "register_operand" "=d")
5043 (rotate:SI (match_operand:SI 1 "register_operand" "0")
5044 (match_operand:SI 2 "general_operand" "dINO")))]
5048 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16)
5050 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16)
5052 operands[2] = GEN_INT (32 - INTVAL (operands[2]));
5053 return \"ror%.l %2,%0\";
5056 return \"rol%.l %2,%0\";
5059 (define_insn "rotlhi3"
5060 [(set (match_operand:HI 0 "register_operand" "=d")
5061 (rotate:HI (match_operand:HI 1 "register_operand" "0")
5062 (match_operand:HI 2 "general_operand" "dIP")))]
5066 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5068 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5069 return \"ror%.w %2,%0\";
5072 return \"rol%.w %2,%0\";
5076 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5077 (rotate:HI (match_dup 0)
5078 (match_operand:HI 1 "general_operand" "dIP")))]
5082 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8)
5084 operands[2] = GEN_INT (16 - INTVAL (operands[2]));
5085 return \"ror%.w %2,%0\";
5088 return \"rol%.w %2,%0\";
5091 (define_insn "rotlqi3"
5092 [(set (match_operand:QI 0 "register_operand" "=d")
5093 (rotate:QI (match_operand:QI 1 "register_operand" "0")
5094 (match_operand:QI 2 "general_operand" "dI")))]
5098 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5100 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5101 return \"ror%.b %2,%0\";
5104 return \"rol%.b %2,%0\";
5108 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5109 (rotate:QI (match_dup 0)
5110 (match_operand:QI 1 "general_operand" "dI")))]
5114 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4)
5116 operands[2] = GEN_INT (8 - INTVAL (operands[2]));
5117 return \"ror%.b %2,%0\";
5120 return \"rol%.b %2,%0\";
5123 (define_insn "rotrsi3"
5124 [(set (match_operand:SI 0 "register_operand" "=d")
5125 (rotatert:SI (match_operand:SI 1 "register_operand" "0")
5126 (match_operand:SI 2 "general_operand" "dI")))]
5130 (define_insn "rotrhi3"
5131 [(set (match_operand:HI 0 "register_operand" "=d")
5132 (rotatert:HI (match_operand:HI 1 "register_operand" "0")
5133 (match_operand:HI 2 "general_operand" "dI")))]
5138 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d"))
5139 (rotatert:HI (match_dup 0)
5140 (match_operand:HI 1 "general_operand" "dI")))]
5144 (define_insn "rotrqi3"
5145 [(set (match_operand:QI 0 "register_operand" "=d")
5146 (rotatert:QI (match_operand:QI 1 "register_operand" "0")
5147 (match_operand:QI 2 "general_operand" "dI")))]
5152 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d"))
5153 (rotatert:QI (match_dup 0)
5154 (match_operand:QI 1 "general_operand" "dI")))]
5159 ;; Bit set/clear in memory byte.
5161 ;; set bit, bit number is int
5162 (define_insn "bsetmemqi"
5163 [(set (match_operand:QI 0 "memory_operand" "+m")
5164 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5165 (match_operand:SI 1 "general_operand" "d")) 0)
5171 return \"bset %1,%0\";
5174 ;; set bit, bit number is (sign/zero)_extended from HImode/QImode
5176 [(set (match_operand:QI 0 "memory_operand" "+m")
5177 (ior:QI (subreg:QI (ashift:SI (const_int 1)
5178 (match_operator:SI 2 "extend_operator"
5179 [(match_operand 1 "general_operand" "d")])) 0)
5185 return \"bset %1,%0\";
5188 ;; clear bit, bit number is int
5189 (define_insn "bclrmemqi"
5190 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5192 (minus:SI (const_int 7)
5193 (match_operand:SI 1 "general_operand" "d")))
5199 return \"bclr %1,%0\";
5202 ;; clear bit, bit number is (sign/zero)_extended from HImode/QImode
5204 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m")
5206 (minus:SI (const_int 7)
5207 (match_operator:SI 2 "extend_operator"
5208 [(match_operand 1 "general_operand" "d")])))
5214 return \"bclr %1,%0\";
5217 ;; Special cases of bit-field insns which we should
5218 ;; recognize in preference to the general case.
5219 ;; These handle aligned 8-bit and 16-bit fields,
5220 ;; which can usually be done with move instructions.
5223 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5224 ; alignment of structure members is specified.
5226 ; The move is allowed to be odd byte aligned, because that's still faster
5227 ; than an odd byte aligned bit field instruction.
5230 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5232 (match_operand:SI 2 "const_int_operand" "n"))
5233 (match_operand:SI 3 "general_operand" "rmi"))]
5234 "TARGET_68020 && TARGET_BITFIELD
5235 && (INTVAL (operands[2]) % 8) == 0
5236 && ! mode_dependent_address_p (XEXP (operands[0], 0))"
5240 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5242 return \"move%.l %3,%0\";
5246 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+do")
5247 (match_operand:SI 1 "const_int_operand" "n")
5248 (match_operand:SI 2 "const_int_operand" "n"))
5249 (match_operand:SI 3 "register_operand" "d"))]
5250 "TARGET_68020 && TARGET_BITFIELD
5251 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16)
5252 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0
5253 && (GET_CODE (operands[0]) == REG
5254 || ! mode_dependent_address_p (XEXP (operands[0], 0)))"
5257 if (REG_P (operands[0]))
5259 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32)
5260 return \"bfins %3,%0{%b2:%b1}\";
5264 = adj_offsettable_operand (operands[0], INTVAL (operands[2]) / 8);
5266 if (GET_CODE (operands[3]) == MEM)
5267 operands[3] = adj_offsettable_operand (operands[3],
5268 (32 - INTVAL (operands[1])) / 8);
5269 if (INTVAL (operands[1]) == 8)
5270 return \"move%.b %3,%0\";
5271 return \"move%.w %3,%0\";
5276 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5277 ; alignment of structure members is specified.
5279 ; The move is allowed to be odd byte aligned, because that's still faster
5280 ; than an odd byte aligned bit field instruction.
5283 [(set (match_operand:SI 0 "general_operand" "=rm")
5284 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o")
5286 (match_operand:SI 3 "const_int_operand" "n")))]
5287 "TARGET_68020 && TARGET_BITFIELD
5288 && (INTVAL (operands[3]) % 8) == 0
5289 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5293 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5295 return \"move%.l %1,%0\";
5299 [(set (match_operand:SI 0 "general_operand" "=&d")
5300 (zero_extract:SI (match_operand:SI 1 "register_operand" "do")
5301 (match_operand:SI 2 "const_int_operand" "n")
5302 (match_operand:SI 3 "const_int_operand" "n")))]
5303 "TARGET_68020 && TARGET_BITFIELD
5304 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5305 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5306 && (GET_CODE (operands[1]) == REG
5307 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5310 cc_status.flags |= CC_NOT_NEGATIVE;
5311 if (REG_P (operands[1]))
5313 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5314 return \"bfextu %1{%b3:%b2},%0\";
5318 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5320 output_asm_insn (\"clr%.l %0\", operands);
5321 if (GET_CODE (operands[0]) == MEM)
5322 operands[0] = adj_offsettable_operand (operands[0],
5323 (32 - INTVAL (operands[1])) / 8);
5324 if (INTVAL (operands[2]) == 8)
5325 return \"move%.b %1,%0\";
5326 return \"move%.w %1,%0\";
5330 ; Special case for 32-bit field in memory. This only occurs when 32-bit
5331 ; alignment of structure members is specified.
5333 ; The move is allowed to be odd byte aligned, because that's still faster
5334 ; than an odd byte aligned bit field instruction.
5337 [(set (match_operand:SI 0 "general_operand" "=rm")
5338 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5340 (match_operand:SI 3 "const_int_operand" "n")))]
5341 "TARGET_68020 && TARGET_BITFIELD
5342 && (INTVAL (operands[3]) % 8) == 0
5343 && ! mode_dependent_address_p (XEXP (operands[1], 0))"
5347 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5349 return \"move%.l %1,%0\";
5353 [(set (match_operand:SI 0 "general_operand" "=d")
5354 (sign_extract:SI (match_operand:SI 1 "register_operand" "do")
5355 (match_operand:SI 2 "const_int_operand" "n")
5356 (match_operand:SI 3 "const_int_operand" "n")))]
5357 "TARGET_68020 && TARGET_BITFIELD
5358 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16)
5359 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0
5360 && (GET_CODE (operands[1]) == REG
5361 || ! mode_dependent_address_p (XEXP (operands[1], 0)))"
5364 if (REG_P (operands[1]))
5366 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32)
5367 return \"bfexts %1{%b3:%b2},%0\";
5371 = adj_offsettable_operand (operands[1], INTVAL (operands[3]) / 8);
5373 if (INTVAL (operands[2]) == 8)
5374 return \"move%.b %1,%0\;extb%.l %0\";
5375 return \"move%.w %1,%0\;ext%.l %0\";
5378 ;; Bit field instructions, general cases.
5379 ;; "o,d" constraint causes a nonoffsettable memref to match the "o"
5380 ;; so that its address is reloaded.
5382 (define_expand "extv"
5383 [(set (match_operand:SI 0 "general_operand" "")
5384 (sign_extract:SI (match_operand:SI 1 "general_operand" "")
5385 (match_operand:SI 2 "general_operand" "")
5386 (match_operand:SI 3 "general_operand" "")))]
5387 "TARGET_68020 && TARGET_BITFIELD"
5391 [(set (match_operand:SI 0 "general_operand" "=d")
5392 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o")
5393 (match_operand:SI 2 "general_operand" "di")
5394 (match_operand:SI 3 "general_operand" "di")))]
5395 "TARGET_68020 && TARGET_BITFIELD"
5396 "bfexts %1{%b3:%b2},%0")
5398 (define_expand "extzv"
5399 [(set (match_operand:SI 0 "general_operand" "")
5400 (zero_extract:SI (match_operand:SI 1 "general_operand" "")
5401 (match_operand:SI 2 "general_operand" "")
5402 (match_operand:SI 3 "general_operand" "")))]
5403 "TARGET_68020 && TARGET_BITFIELD"
5407 [(set (match_operand:SI 0 "general_operand" "=d,d")
5408 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o,d")
5409 (match_operand:SI 2 "general_operand" "di,di")
5410 (match_operand:SI 3 "general_operand" "di,di")))]
5411 "TARGET_68020 && TARGET_BITFIELD"
5414 if (GET_CODE (operands[2]) == CONST_INT)
5416 if (INTVAL (operands[2]) != 32)
5417 cc_status.flags |= CC_NOT_NEGATIVE;
5423 return \"bfextu %1{%b3:%b2},%0\";
5427 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5428 (match_operand:SI 1 "general_operand" "di")
5429 (match_operand:SI 2 "general_operand" "di"))
5430 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2))
5431 (match_operand 3 "const_int_operand" "n")))]
5432 "TARGET_68020 && TARGET_BITFIELD
5433 && (INTVAL (operands[3]) == -1
5434 || (GET_CODE (operands[1]) == CONST_INT
5435 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))"
5439 return \"bfchg %0{%b2:%b1}\";
5443 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5444 (match_operand:SI 1 "general_operand" "di")
5445 (match_operand:SI 2 "general_operand" "di"))
5447 "TARGET_68020 && TARGET_BITFIELD"
5451 return \"bfclr %0{%b2:%b1}\";
5455 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5456 (match_operand:SI 1 "general_operand" "di")
5457 (match_operand:SI 2 "general_operand" "di"))
5459 "TARGET_68020 && TARGET_BITFIELD"
5463 return \"bfset %0{%b2:%b1}\";
5466 (define_expand "insv"
5467 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "")
5468 (match_operand:SI 1 "general_operand" "")
5469 (match_operand:SI 2 "general_operand" ""))
5470 (match_operand:SI 3 "register_operand" ""))]
5471 "TARGET_68020 && TARGET_BITFIELD"
5475 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o")
5476 (match_operand:SI 1 "general_operand" "di")
5477 (match_operand:SI 2 "general_operand" "di"))
5478 (match_operand:SI 3 "register_operand" "d"))]
5479 "TARGET_68020 && TARGET_BITFIELD"
5480 "bfins %3,%0{%b2:%b1}")
5482 ;; Now recognize bit field insns that operate on registers
5483 ;; (or at least were intended to do so).
5486 [(set (match_operand:SI 0 "general_operand" "=d")
5487 (sign_extract:SI (match_operand:SI 1 "register_operand" "d")
5488 (match_operand:SI 2 "general_operand" "di")
5489 (match_operand:SI 3 "general_operand" "di")))]
5490 "TARGET_68020 && TARGET_BITFIELD"
5491 "bfexts %1{%b3:%b2},%0")
5494 [(set (match_operand:SI 0 "general_operand" "=d")
5495 (zero_extract:SI (match_operand:SI 1 "register_operand" "d")
5496 (match_operand:SI 2 "general_operand" "di")
5497 (match_operand:SI 3 "general_operand" "di")))]
5498 "TARGET_68020 && TARGET_BITFIELD"
5501 if (GET_CODE (operands[2]) == CONST_INT)
5503 if (INTVAL (operands[2]) != 32)
5504 cc_status.flags |= CC_NOT_NEGATIVE;
5510 return \"bfextu %1{%b3:%b2},%0\";
5514 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5515 (match_operand:SI 1 "general_operand" "di")
5516 (match_operand:SI 2 "general_operand" "di"))
5518 "TARGET_68020 && TARGET_BITFIELD"
5522 return \"bfclr %0{%b2:%b1}\";
5526 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5527 (match_operand:SI 1 "general_operand" "di")
5528 (match_operand:SI 2 "general_operand" "di"))
5530 "TARGET_68020 && TARGET_BITFIELD"
5534 return \"bfset %0{%b2:%b1}\";
5538 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d")
5539 (match_operand:SI 1 "general_operand" "di")
5540 (match_operand:SI 2 "general_operand" "di"))
5541 (match_operand:SI 3 "register_operand" "d"))]
5542 "TARGET_68020 && TARGET_BITFIELD"
5546 /* These special cases are now recognized by a specific pattern. */
5547 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5548 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16)
5549 return \"move%.w %3,%0\";
5550 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT
5551 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8)
5552 return \"move%.b %3,%0\";
5554 return \"bfins %3,%0{%b2:%b1}\";
5557 ;; Special patterns for optimizing bit-field instructions.
5561 (zero_extract:SI (match_operand:QI 0 "memory_operand" "o")
5562 (match_operand:SI 1 "const_int_operand" "n")
5563 (match_operand:SI 2 "general_operand" "di")))]
5564 "TARGET_68020 && TARGET_BITFIELD"
5567 if (operands[1] == const1_rtx
5568 && GET_CODE (operands[2]) == CONST_INT)
5570 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5571 return output_btst (operands,
5572 GEN_INT (width - INTVAL (operands[2])),
5575 /* Pass 1000 as SIGNPOS argument so that btst will
5576 not think we are testing the sign bit for an `and'
5577 and assume that nonzero implies a negative result. */
5579 if (INTVAL (operands[1]) != 32)
5580 cc_status.flags = CC_NOT_NEGATIVE;
5581 return \"bftst %0{%b2:%b1}\";
5585 ;;; now handle the register cases
5588 (zero_extract:SI (match_operand:SI 0 "register_operand" "d")
5589 (match_operand:SI 1 "const_int_operand" "n")
5590 (match_operand:SI 2 "general_operand" "di")))]
5591 "TARGET_68020 && TARGET_BITFIELD"
5594 if (operands[1] == const1_rtx
5595 && GET_CODE (operands[2]) == CONST_INT)
5597 int width = GET_CODE (operands[0]) == REG ? 31 : 7;
5598 return output_btst (operands,
5599 GEN_INT (width - INTVAL (operands[2])),
5602 /* Pass 1000 as SIGNPOS argument so that btst will
5603 not think we are testing the sign bit for an `and'
5604 and assume that nonzero implies a negative result. */
5606 if (INTVAL (operands[1]) != 32)
5607 cc_status.flags = CC_NOT_NEGATIVE;
5608 return \"bftst %0{%b2:%b1}\";
5611 (define_insn "scc0_di"
5612 [(set (match_operand:QI 0 "general_operand" "=dm")
5613 (match_operator 1 "valid_dbcc_comparison_p"
5614 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5618 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5621 (define_insn "scc0_di_5200"
5622 [(set (match_operand:QI 0 "general_operand" "=d")
5623 (match_operator 1 "valid_dbcc_comparison_p"
5624 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))]
5628 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]);
5631 (define_insn "scc_di"
5632 [(set (match_operand:QI 0 "general_operand" "=dm,dm")
5633 (match_operator 1 "valid_dbcc_comparison_p"
5634 [(match_operand:DI 2 "general_operand" "ro,r")
5635 (match_operand:DI 3 "general_operand" "r,ro")]))]
5639 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5642 (define_insn "scc_di_5200"
5643 [(set (match_operand:QI 0 "general_operand" "=d,d")
5644 (match_operator 1 "valid_dbcc_comparison_p"
5645 [(match_operand:DI 2 "general_operand" "ro,r")
5646 (match_operand:DI 3 "general_operand" "r,ro")]))]
5650 return output_scc_di (operands[1], operands[2], operands[3], operands[0]);
5653 (define_expand "seq"
5654 [(set (match_operand:QI 0 "general_operand" "")
5655 (eq:QI (cc0) (const_int 0)))]
5659 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5661 m68k_last_compare_had_fp_operands = 0;
5667 [(set (match_operand:QI 0 "general_operand" "=dm")
5668 (eq:QI (cc0) (const_int 0)))]
5671 cc_status = cc_prev_status;
5672 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5676 [(set (match_operand:QI 0 "general_operand" "=d")
5677 (eq:QI (cc0) (const_int 0)))]
5680 cc_status = cc_prev_status;
5681 OUTPUT_JUMP (\"seq %0\", \"fseq %0\", \"seq %0\");
5684 (define_expand "sne"
5685 [(set (match_operand:QI 0 "general_operand" "")
5686 (ne:QI (cc0) (const_int 0)))]
5690 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5692 m68k_last_compare_had_fp_operands = 0;
5698 [(set (match_operand:QI 0 "general_operand" "=dm")
5699 (ne:QI (cc0) (const_int 0)))]
5702 cc_status = cc_prev_status;
5703 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5707 [(set (match_operand:QI 0 "general_operand" "=d")
5708 (ne:QI (cc0) (const_int 0)))]
5711 cc_status = cc_prev_status;
5712 OUTPUT_JUMP (\"sne %0\", \"fsne %0\", \"sne %0\");
5715 (define_expand "sgt"
5716 [(set (match_operand:QI 0 "general_operand" "")
5717 (gt:QI (cc0) (const_int 0)))]
5721 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5723 m68k_last_compare_had_fp_operands = 0;
5729 [(set (match_operand:QI 0 "general_operand" "=dm")
5730 (gt:QI (cc0) (const_int 0)))]
5733 cc_status = cc_prev_status;
5734 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5738 [(set (match_operand:QI 0 "general_operand" "=d")
5739 (gt:QI (cc0) (const_int 0)))]
5742 cc_status = cc_prev_status;
5743 OUTPUT_JUMP (\"sgt %0\", \"fsgt %0\", 0);
5746 (define_expand "sgtu"
5747 [(set (match_operand:QI 0 "general_operand" "")
5748 (gtu:QI (cc0) (const_int 0)))]
5753 [(set (match_operand:QI 0 "general_operand" "=dm")
5754 (gtu:QI (cc0) (const_int 0)))]
5756 "* cc_status = cc_prev_status;
5757 return \"shi %0\"; ")
5760 [(set (match_operand:QI 0 "general_operand" "=d")
5761 (gtu:QI (cc0) (const_int 0)))]
5763 "* cc_status = cc_prev_status;
5764 return \"shi %0\"; ")
5766 (define_expand "slt"
5767 [(set (match_operand:QI 0 "general_operand" "")
5768 (lt:QI (cc0) (const_int 0)))]
5772 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5774 m68k_last_compare_had_fp_operands = 0;
5780 [(set (match_operand:QI 0 "general_operand" "=dm")
5781 (lt:QI (cc0) (const_int 0)))]
5783 "* cc_status = cc_prev_status;
5784 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5787 [(set (match_operand:QI 0 "general_operand" "=d")
5788 (lt:QI (cc0) (const_int 0)))]
5790 "* cc_status = cc_prev_status;
5791 OUTPUT_JUMP (\"slt %0\", \"fslt %0\", \"smi %0\"); ")
5793 (define_expand "sltu"
5794 [(set (match_operand:QI 0 "general_operand" "")
5795 (ltu:QI (cc0) (const_int 0)))]
5800 [(set (match_operand:QI 0 "general_operand" "=dm")
5801 (ltu:QI (cc0) (const_int 0)))]
5803 "* cc_status = cc_prev_status;
5804 return \"scs %0\"; ")
5807 [(set (match_operand:QI 0 "general_operand" "=d")
5808 (ltu:QI (cc0) (const_int 0)))]
5810 "* cc_status = cc_prev_status;
5811 return \"scs %0\"; ")
5813 (define_expand "sge"
5814 [(set (match_operand:QI 0 "general_operand" "")
5815 (ge:QI (cc0) (const_int 0)))]
5819 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5821 m68k_last_compare_had_fp_operands = 0;
5827 [(set (match_operand:QI 0 "general_operand" "=dm")
5828 (ge:QI (cc0) (const_int 0)))]
5830 "* cc_status = cc_prev_status;
5831 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5834 [(set (match_operand:QI 0 "general_operand" "=d")
5835 (ge:QI (cc0) (const_int 0)))]
5837 "* cc_status = cc_prev_status;
5838 OUTPUT_JUMP (\"sge %0\", \"fsge %0\", \"spl %0\"); ")
5840 (define_expand "sgeu"
5841 [(set (match_operand:QI 0 "general_operand" "")
5842 (geu:QI (cc0) (const_int 0)))]
5847 [(set (match_operand:QI 0 "general_operand" "=dm")
5848 (geu:QI (cc0) (const_int 0)))]
5850 "* cc_status = cc_prev_status;
5851 return \"scc %0\"; ")
5854 [(set (match_operand:QI 0 "general_operand" "=d")
5855 (geu:QI (cc0) (const_int 0)))]
5857 "* cc_status = cc_prev_status;
5858 return \"scc %0\"; ")
5860 (define_expand "sle"
5861 [(set (match_operand:QI 0 "general_operand" "")
5862 (le:QI (cc0) (const_int 0)))]
5866 if (TARGET_68060 && m68k_last_compare_had_fp_operands)
5868 m68k_last_compare_had_fp_operands = 0;
5874 [(set (match_operand:QI 0 "general_operand" "=dm")
5875 (le:QI (cc0) (const_int 0)))]
5878 cc_status = cc_prev_status;
5879 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5883 [(set (match_operand:QI 0 "general_operand" "=d")
5884 (le:QI (cc0) (const_int 0)))]
5887 cc_status = cc_prev_status;
5888 OUTPUT_JUMP (\"sle %0\", \"fsle %0\", 0);
5891 (define_expand "sleu"
5892 [(set (match_operand:QI 0 "general_operand" "")
5893 (leu:QI (cc0) (const_int 0)))]
5898 [(set (match_operand:QI 0 "general_operand" "=dm")
5899 (leu:QI (cc0) (const_int 0)))]
5901 "* cc_status = cc_prev_status;
5902 return \"sls %0\"; ")
5905 [(set (match_operand:QI 0 "general_operand" "=d")
5906 (leu:QI (cc0) (const_int 0)))]
5908 "* cc_status = cc_prev_status;
5909 return \"sls %0\"; ")
5911 ;; Basic conditional jump instructions.
5913 (define_insn "beq0_di"
5915 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>")
5917 (label_ref (match_operand 1 "" ","))
5919 (clobber (match_scratch:SI 2 "=d,d"))]
5924 if (which_alternative == 1)
5926 return \"move%.l %0,%2\;or%.l %0,%2\;jbeq %l1\";
5928 return \"move%.l %0,%2\;or%.l %0,%2\;jeq %l1\";
5930 if ((cc_prev_status.value1
5931 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5932 || (cc_prev_status.value2
5933 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5935 cc_status = cc_prev_status;
5937 return \"jbeq %l1\";
5942 if (GET_CODE (operands[0]) == REG)
5943 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
5945 operands[3] = adj_offsettable_operand (operands[0], 4);
5946 if (! ADDRESS_REG_P (operands[0]))
5949 return \"move%.l %0,%2\;or%.l %3,%2\;jbeq %l1\";
5951 return \"move%.l %0,%2\;or%.l %3,%2\;jeq %l1\";
5954 operands[4] = gen_label_rtx();
5955 if (TARGET_68020 || TARGET_5200)
5958 output_asm_insn (\"tst%.l %0\;jbne %l4\;tst%.l %3\;jbeq %l1\", operands);
5960 output_asm_insn (\"tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1\", operands);
5966 #ifdef SGS_CMP_ORDER
5967 output_asm_insn (\"cmp%.w %0,%#0\;jbne %l4\;cmp%.w %3,%#0\;jbeq %l1\", operands);
5969 output_asm_insn (\"cmp%.w %#0,%0\;jbne %l4\;cmp%.w %#0,%3\;jbeq %l1\", operands);
5972 output_asm_insn (\"cmp%.w %#0,%0\;jne %l4\;cmp%.w %#0,%3\;jeq %l1\", operands);
5975 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"L\",
5976 CODE_LABEL_NUMBER (operands[4]));
5980 (define_insn "bne0_di"
5982 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a")
5984 (label_ref (match_operand 1 "" ","))
5986 (clobber (match_scratch:SI 2 "=d,X"))]
5990 if ((cc_prev_status.value1
5991 && rtx_equal_p (cc_prev_status.value1, operands[0]))
5992 || (cc_prev_status.value2
5993 && rtx_equal_p (cc_prev_status.value2, operands[0])))
5995 cc_status = cc_prev_status;
5997 return \"jbne %l1\";
6003 if (GET_CODE (operands[0]) == REG)
6004 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
6006 operands[3] = adj_offsettable_operand (operands[0], 4);
6007 if (!ADDRESS_REG_P (operands[0]))
6010 return \"move%.l %0,%2\;or%.l %3,%2\;jbne %l1\";
6012 return \"move%.l %0,%2\;or%.l %3,%2\;jne %l1\";
6015 if (TARGET_68020 || TARGET_5200)
6018 return \"tst%.l %0\;jbne %l1\;tst%.l %3\;jbne %l1\";
6020 return \"tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1\";
6026 #ifdef SGS_CMP_ORDER
6027 return \"cmp%.w %0,%#0\;jbne %l1\;cmp%.w %3,%#0\;jbne %l1\";
6029 return \"cmp%.w %#0,%0\;jbne %l1\;cmp%.w %#0,%3\;jbne %l1\";
6032 return \"cmp%.w %#0,%0\;jne %l1\;cmp%.w %#0,%3\;jne %l1\";
6037 (define_insn "bge0_di"
6039 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro")
6041 (label_ref (match_operand 1 "" ""))
6046 if ((cc_prev_status.value1
6047 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6048 || (cc_prev_status.value2
6049 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6051 cc_status = cc_prev_status;
6052 if (cc_status.flags & CC_REVERSED)
6055 return \"jble %l1\";
6063 return \"jbpl %l1\";
6070 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6071 output_asm_insn(\"tst%.l %0\", operands);
6074 /* On an address reg, cmpw may replace cmpl. */
6075 #ifdef SGS_CMP_ORDER
6076 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6078 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6083 return \"jbpl %l1\";
6089 (define_insn "blt0_di"
6091 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro")
6093 (label_ref (match_operand 1 "" ""))
6098 if ((cc_prev_status.value1
6099 && rtx_equal_p (cc_prev_status.value1, operands[0]))
6100 || (cc_prev_status.value2
6101 && rtx_equal_p (cc_prev_status.value2, operands[0])))
6103 cc_status = cc_prev_status;
6104 if (cc_status.flags & CC_REVERSED)
6107 return \"jbgt %l1\";
6115 return \"jbmi %l1\";
6122 if (TARGET_68020 || TARGET_5200 || ! ADDRESS_REG_P (operands[0]))
6123 output_asm_insn(\"tst%.l %0\", operands);
6126 /* On an address reg, cmpw may replace cmpl. */
6127 #ifdef SGS_CMP_ORDER
6128 output_asm_insn(\"cmp%.w %0,%#0\", operands);
6130 output_asm_insn(\"cmp%.w %#0,%0\", operands);
6135 return \"jbmi %l1\";
6143 (if_then_else (eq (cc0)
6145 (label_ref (match_operand 0 "" ""))
6151 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6153 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6159 (if_then_else (ne (cc0)
6161 (label_ref (match_operand 0 "" ""))
6167 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6169 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6175 (if_then_else (gt (cc0)
6177 (label_ref (match_operand 0 "" ""))
6182 OUTPUT_JUMP (\"jbgt %l0\", \"fbgt %l0\", 0);
6184 OUTPUT_JUMP (\"jgt %l0\", \"fjgt %l0\", 0);
6190 (if_then_else (gtu (cc0)
6192 (label_ref (match_operand 0 "" ""))
6197 return \"jbhi %l0\";
6205 (if_then_else (lt (cc0)
6207 (label_ref (match_operand 0 "" ""))
6212 OUTPUT_JUMP (\"jblt %l0\", \"fblt %l0\", \"jbmi %l0\");
6214 OUTPUT_JUMP (\"jlt %l0\", \"fjlt %l0\", \"jmi %l0\");
6220 (if_then_else (ltu (cc0)
6222 (label_ref (match_operand 0 "" ""))
6227 return \"jbcs %l0\";
6235 (if_then_else (ge (cc0)
6237 (label_ref (match_operand 0 "" ""))
6242 OUTPUT_JUMP (\"jbge %l0\", \"fbge %l0\", \"jbpl %l0\");
6244 OUTPUT_JUMP (\"jge %l0\", \"fjge %l0\", \"jpl %l0\");
6250 (if_then_else (geu (cc0)
6252 (label_ref (match_operand 0 "" ""))
6257 return \"jbcc %l0\";
6265 (if_then_else (le (cc0)
6267 (label_ref (match_operand 0 "" ""))
6272 OUTPUT_JUMP (\"jble %l0\", \"fble %l0\", 0);
6274 OUTPUT_JUMP (\"jle %l0\", \"fjle %l0\", 0);
6280 (if_then_else (leu (cc0)
6282 (label_ref (match_operand 0 "" ""))
6287 return \"jbls %l0\";
6293 ;; Negated conditional jump instructions.
6297 (if_then_else (eq (cc0)
6300 (label_ref (match_operand 0 "" ""))))]
6305 OUTPUT_JUMP (\"jbne %l0\", \"fbne %l0\", \"jbne %l0\");
6307 OUTPUT_JUMP (\"jne %l0\", \"fjne %l0\", \"jne %l0\");
6313 (if_then_else (ne (cc0)
6316 (label_ref (match_operand 0 "" ""))))]
6321 OUTPUT_JUMP (\"jbeq %l0\", \"fbeq %l0\", \"jbeq %l0\");
6323 OUTPUT_JUMP (\"jeq %l0\", \"fjeq %l0\", \"jeq %l0\");
6329 (if_then_else (gt (cc0)
6332 (label_ref (match_operand 0 "" ""))))]
6336 OUTPUT_JUMP (\"jble %l0\", \"fbngt %l0\", 0);
6338 OUTPUT_JUMP (\"jle %l0\", \"fjngt %l0\", 0);
6344 (if_then_else (gtu (cc0)
6347 (label_ref (match_operand 0 "" ""))))]
6351 return \"jbls %l0\";
6359 (if_then_else (lt (cc0)
6362 (label_ref (match_operand 0 "" ""))))]
6366 OUTPUT_JUMP (\"jbge %l0\", \"fbnlt %l0\", \"jbpl %l0\");
6368 OUTPUT_JUMP (\"jge %l0\", \"fjnlt %l0\", \"jpl %l0\");
6374 (if_then_else (ltu (cc0)
6377 (label_ref (match_operand 0 "" ""))))]
6381 return \"jbcc %l0\";
6389 (if_then_else (ge (cc0)
6392 (label_ref (match_operand 0 "" ""))))]
6396 OUTPUT_JUMP (\"jblt %l0\", \"fbnge %l0\", \"jbmi %l0\");
6398 OUTPUT_JUMP (\"jlt %l0\", \"fjnge %l0\", \"jmi %l0\");
6404 (if_then_else (geu (cc0)
6407 (label_ref (match_operand 0 "" ""))))]
6411 return \"jbcs %l0\";
6419 (if_then_else (le (cc0)
6422 (label_ref (match_operand 0 "" ""))))]
6426 OUTPUT_JUMP (\"jbgt %l0\", \"fbnle %l0\", 0);
6428 OUTPUT_JUMP (\"jgt %l0\", \"fjnle %l0\", 0);
6434 (if_then_else (leu (cc0)
6437 (label_ref (match_operand 0 "" ""))))]
6441 return \"jbhi %l0\";
6447 ;; Unconditional and other jump instructions
6450 (label_ref (match_operand 0 "" "")))]
6454 return \"jbra %l0\";
6460 ;; We support two different ways of handling dispatch tables.
6461 ;; The NeXT uses absolute tables, and other machines use relative.
6462 ;; This define_expand can generate either kind.
6463 (define_expand "tablejump"
6464 [(parallel [(set (pc) (match_operand 0 "" ""))
6465 (use (label_ref (match_operand 1 "" "")))])]
6469 #ifdef CASE_VECTOR_PC_RELATIVE
6470 operands[0] = gen_rtx_PLUS (SImode, pc_rtx,
6471 gen_rtx_SIGN_EXTEND (SImode, operands[0]));
6475 ;; Jump to variable address from dispatch table of absolute addresses.
6477 [(set (pc) (match_operand:SI 0 "register_operand" "a"))
6478 (use (label_ref (match_operand 1 "" "")))]
6482 return \"jmp (%0)\";
6488 ;; Jump to variable address from dispatch table of relative addresses.
6492 (sign_extend:SI (match_operand:HI 0 "register_operand" "r"))))
6493 (use (label_ref (match_operand 1 "" "")))]
6496 #ifdef ASM_RETURN_CASE_JUMP
6497 ASM_RETURN_CASE_JUMP;
6500 #ifdef ASM_OUTPUT_CASE_LABEL
6502 return \"ext%.l %0\;jmp 6(%%pc,%0.l)\";
6504 return \"jmp 6(%%pc,%0.w)\";
6509 return \"ext%.l %0\;jmp 2(pc,%0.l)\";
6511 return \"extl %0\;jmp 2(%%pc,%0.l)\";
6512 #endif /* end !CRDS */
6517 return \"jmp 2(pc,%0.w)\";
6519 return \"jmp 2(%%pc,%0.w)\";
6520 #endif /* end !CRDS */
6527 return \"ext%.l %0\;jmp (2,pc,%0.l)\";
6529 return \"extl %0\;jmp pc@(2,%0:l)\";
6535 return \"jmp (2,pc,%0.w)\";
6537 return \"jmp pc@(2,%0:w)\";
6544 ;; Decrement-and-branch insns.
6548 (ne (match_operand:HI 0 "general_operand" "+d*g")
6550 (label_ref (match_operand 1 "" ""))
6553 (plus:HI (match_dup 0)
6559 if (DATA_REG_P (operands[0]))
6560 return \"dbra %0,%l1\";
6561 if (GET_CODE (operands[0]) == MEM)
6565 return \"sub%.w %#1,%0\;jbcc %l1\";
6567 return \"subq%.w %#1,%0\;jbcc %l1\";
6569 #else /* not MOTOROLA */
6570 return \"subqw %#1,%0\;jcc %l1\";
6574 #ifdef SGS_CMP_ORDER
6576 return \"sub%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6578 return \"subq%.w %#1,%0\;cmp%.w %0,%#-1\;jbne %l1\";
6580 #else /* not SGS_CMP_ORDER */
6581 return \"subq%.w %#1,%0\;cmp%.w %#-1,%0\;jbne %l1\";
6583 #else /* not MOTOROLA */
6584 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6591 (ne (match_operand:SI 0 "general_operand" "+d*g")
6593 (label_ref (match_operand 1 "" ""))
6596 (plus:SI (match_dup 0)
6604 if (DATA_REG_P (operands[0]))
6605 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6606 if (GET_CODE (operands[0]) == MEM)
6607 return \"sub%.l %#1,%0\;jbcc %l1\";
6609 if (DATA_REG_P (operands[0]))
6610 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6611 if (GET_CODE (operands[0]) == MEM)
6612 return \"subq%.l %#1,%0\;jbcc %l1\";
6613 #endif /* NO_ADDSUB_Q */
6614 #ifdef SGS_CMP_ORDER
6616 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6618 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6620 #else /* not SGS_CMP_ORDER */
6621 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6622 #endif /* not SGS_CMP_ORDER */
6623 #else /* not MOTOROLA */
6624 if (DATA_REG_P (operands[0]))
6625 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6626 if (GET_CODE (operands[0]) == MEM)
6627 return \"subql %#1,%0\;jcc %l1\";
6628 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6629 #endif /* not MOTOROLA */
6632 ;; Two dbra patterns that use REG_NOTES info generated by strength_reduce.
6637 (ge (plus:HI (match_operand:HI 0 "general_operand" "+d*am")
6640 (label_ref (match_operand 1 "" ""))
6643 (plus:HI (match_dup 0)
6645 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6651 if (DATA_REG_P (operands[0]))
6652 return \"dbra %0,%l1\";
6653 if (GET_CODE (operands[0]) == MEM)
6654 return \"sub%.w %#1,%0\;jbcc %l1\";
6656 if (DATA_REG_P (operands[0]))
6657 return \"dbra %0,%l1\";
6658 if (GET_CODE (operands[0]) == MEM)
6659 return \"subq%.w %#1,%0\;jbcc %l1\";
6661 #ifdef SGS_CMP_ORDER
6663 return \"sub.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6665 return \"subq.w %#1,%0\;cmp.w %0,%#-1\;jbne %l1\";
6667 #else /* not SGS_CMP_ORDER */
6668 return \"subq.w %#1,%0\;cmp.w %#-1,%0\;jbne %l1\";
6669 #endif /* not SGS_CMP_ORDER */
6670 #else /* not MOTOROLA */
6671 if (DATA_REG_P (operands[0]))
6672 return \"dbra %0,%l1\";
6673 if (GET_CODE (operands[0]) == MEM)
6674 return \"subqw %#1,%0\;jcc %l1\";
6675 return \"subqw %#1,%0\;cmpw %#-1,%0\;jne %l1\";
6676 #endif /* not MOTOROLA */
6679 (define_expand "decrement_and_branch_until_zero"
6680 [(parallel [(set (pc)
6682 (ge (plus:SI (match_operand:SI 0 "general_operand" "")
6685 (label_ref (match_operand 1 "" ""))
6688 (plus:SI (match_dup 0)
6696 (ge (plus:SI (match_operand:SI 0 "general_operand" "+d*am")
6699 (label_ref (match_operand 1 "" ""))
6702 (plus:SI (match_dup 0)
6704 "!TARGET_5200 && find_reg_note (insn, REG_NONNEG, 0)"
6710 if (DATA_REG_P (operands[0]))
6711 return \"dbra %0,%l1\;clr%.w %0\;sub%.l %#1,%0\;jbcc %l1\";
6712 if (GET_CODE (operands[0]) == MEM)
6713 return \"sub%.l %#1,%0\;jbcc %l1\";
6715 if (DATA_REG_P (operands[0]))
6716 return \"dbra %0,%l1\;clr%.w %0\;subq%.l %#1,%0\;jbcc %l1\";
6717 if (GET_CODE (operands[0]) == MEM)
6718 return \"subq%.l %#1,%0\;jbcc %l1\";
6720 #ifdef SGS_CMP_ORDER
6722 return \"sub.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6724 return \"subq.l %#1,%0\;cmp.l %0,%#-1\;jbne %l1\";
6726 #else /* not SGS_CMP_ORDER */
6727 return \"subq.l %#1,%0\;cmp.l %#-1,%0\;jbne %l1\";
6728 #endif /* not SGS_CMP_ORDER */
6729 #else /* not MOTOROLA */
6730 if (DATA_REG_P (operands[0]))
6731 return \"dbra %0,%l1\;clr%.w %0\;subql %#1,%0\;jcc %l1\";
6732 if (GET_CODE (operands[0]) == MEM)
6733 return \"subql %#1,%0\;jcc %l1\";
6734 return \"subql %#1,%0\;cmpl %#-1,%0\;jne %l1\";
6735 #endif /* not MOTOROLA */
6739 ;; For PIC calls, in order to be able to support
6740 ;; dynamic linker LAZY BINDING, all the procedure calls need to go
6741 ;; through the PLT (Procedure Linkage Table) section in PIC mode.
6743 ;; PIC calls are handled by loading the address of the function into a
6744 ;; register (via movsi), then emitting a register indirect call using
6745 ;; the "jsr" function call syntax.
6747 ;; When outputting MIT syntax (e.g. on Suns), we add a bogus extra
6748 ;; operand to the jbsr statement to indicate that this call should
6749 ;; go through the PLT (why? because this is the way that Sun does it).
6751 ;; We have different patterns for PIC calls and non-PIC calls. The
6752 ;; different patterns are only used to choose the right syntax.
6754 ;; The svr4 m68k assembler recognizes this syntax: `bsr FUNC@PLTPC' and it
6755 ;; will create the correct relocation entry (R_68K_PLT32) for `FUNC',
6756 ;; that tells the linker editor to create an entry for `FUNC' in PLT
6757 ;; section at link time. However, all global objects reference are still
6758 ;; done by using `OBJ@GOT'. So, the goal here is to output the function
6759 ;; call operand as `FUNC@PLTPC', but output object operand as `OBJ@GOT'.
6760 ;; We need to have a way to differentiate these two different operands.
6762 ;; The strategy I use here is to use SYMBOL_REF_FLAG to differentiate
6763 ;; these two different operands. The macro LEGITIMATE_PIC_OPERAND_P needs
6764 ;; to be changed to recognize function calls symbol_ref operand as a valid
6765 ;; PIC operand (by checking whether SYMBOL_REF_FLAG is set). This will
6766 ;; avoid the compiler to load this symbol_ref operand into a register.
6767 ;; Remember, the operand "foo@PLTPC" cannot be called via jsr directly
6768 ;; since the value is a PC relative offset, not a real address.
6770 ;; All global objects are treated in the similar way as in SUN3. The only
6771 ;; difference is: on m68k svr4, the reference of such global object needs
6772 ;; to end with a suffix "@GOT" so the assembler and linker know to create
6773 ;; an entry for it in GOT (Global Offset Table) section. This is done in
6776 ;; Call subroutine with no return value.
6777 (define_expand "call"
6778 [(call (match_operand:QI 0 "memory_operand" "")
6779 (match_operand:SI 1 "general_operand" ""))]
6780 ;; Operand 1 not really used on the m68000.
6785 if (flag_pic && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6786 SYMBOL_REF_FLAG (XEXP (operands[0], 0)) = 1;
6789 ;; This is a normal call sequence.
6791 [(call (match_operand:QI 0 "memory_operand" "o")
6792 (match_operand:SI 1 "general_operand" "g"))]
6793 ;; Operand 1 not really used on the m68000.
6797 #if defined (MOTOROLA) && !defined (USE_GAS)
6799 if (GET_CODE (operands[0]) == MEM
6800 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6809 ;; This is a PIC call sequence.
6811 [(call (match_operand:QI 0 "memory_operand" "o")
6812 (match_operand:SI 1 "general_operand" "g"))]
6813 ;; Operand 1 not really used on the m68000.
6817 if (GET_CODE (operands[0]) == MEM
6818 && GET_CODE (XEXP (operands[0], 0)) == SYMBOL_REF)
6821 return \"bsr.l %0\";
6824 return \"bsr.l %0@PLTPC\";
6826 return \"bsr %0@PLTPC\";
6830 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC,
6831 GAS just plain ignores it. */
6832 return \"jbsr %0,a1\";
6837 ;; Call subroutine, returning value in operand 0
6838 ;; (which must be a hard register).
6839 ;; See comments before "call" regarding PIC calls.
6840 (define_expand "call_value"
6841 [(set (match_operand 0 "" "")
6842 (call (match_operand:QI 1 "memory_operand" "")
6843 (match_operand:SI 2 "general_operand" "")))]
6844 ;; Operand 2 not really used on the m68000.
6848 if (flag_pic && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6849 SYMBOL_REF_FLAG (XEXP (operands[1], 0)) = 1;
6852 ;; This is a normal call_value
6854 [(set (match_operand 0 "" "=rf")
6855 (call (match_operand:QI 1 "memory_operand" "o")
6856 (match_operand:SI 2 "general_operand" "g")))]
6857 ;; Operand 2 not really used on the m68000.
6860 #if defined (MOTOROLA) && !defined (USE_GAS)
6862 if (GET_CODE (operands[1]) == MEM
6863 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6872 ;; This is a PIC call_value
6874 [(set (match_operand 0 "" "=rf")
6875 (call (match_operand:QI 1 "memory_operand" "o")
6876 (match_operand:SI 2 "general_operand" "g")))]
6877 ;; Operand 2 not really used on the m68000.
6880 if (GET_CODE (operands[1]) == MEM
6881 && GET_CODE (XEXP (operands[1], 0)) == SYMBOL_REF)
6885 return \"bsr.l %1\";
6888 return \"bsr.l %1@PLTPC\";
6890 return \"bsr %1@PLTPC\";
6894 /* The ',a1' is a dummy argument telling the Sun assembler we want PIC
6895 GAS just plain ignores it. */
6896 return \"jbsr %1,a1\";
6902 ;; Call subroutine returning any type.
6904 (define_expand "untyped_call"
6905 [(parallel [(call (match_operand 0 "" "")
6907 (match_operand 1 "" "")
6908 (match_operand 2 "" "")])]
6909 "NEEDS_UNTYPED_CALL"
6914 emit_call_insn (gen_call (operands[0], const0_rtx, NULL, const0_rtx));
6916 for (i = 0; i < XVECLEN (operands[2], 0); i++)
6918 rtx set = XVECEXP (operands[2], 0, i);
6919 emit_move_insn (SET_DEST (set), SET_SRC (set));
6922 /* The optimizer does not know that the call sets the function value
6923 registers we stored in the result block. We avoid problems by
6924 claiming that all hard registers are used and clobbered at this
6926 emit_insn (gen_blockage ());
6931 ;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and
6932 ;; all of memory. This blocks insns from being moved across this point.
6934 (define_insn "blockage"
6935 [(unspec_volatile [(const_int 0)] 0)]
6944 (define_insn "probe"
6949 operands[0] = gen_rtx_PLUS (SImode, stack_pointer_rtx,
6950 GEN_INT (NEED_PROBE));
6951 return \"tstl %a0\";
6954 ;; Used for frameless functions which save no regs and allocate no locals.
6955 (define_insn "return"
6960 if (current_function_pops_args == 0)
6962 operands[0] = GEN_INT (current_function_pops_args);
6966 (define_insn "indirect_jump"
6967 [(set (pc) (match_operand:SI 0 "address_operand" "p"))]
6971 ;; This should not be used unless the add/sub insns can't be.
6974 [(set (match_operand:SI 0 "general_operand" "=a")
6975 (match_operand:QI 1 "address_operand" "p"))]
6980 /* Recognize an insn that refers to a table of offsets. Such an insn will
6981 need to refer to a label on the insn. So output one. Use the
6982 label-number of the table of offsets to generate this label. This code,
6983 and similar code above, assumes that there will be at most one reference
6985 if (GET_CODE (operands[1]) == PLUS
6986 && GET_CODE (XEXP (operands[1], 1)) == LABEL_REF
6987 && GET_CODE (XEXP (operands[1], 0)) != PLUS)
6989 rtx labelref = XEXP (operands[1], 1);
6990 #if defined (MOTOROLA) && !defined (SGS_SWITCH_TABLES)
6992 asm_fprintf (asm_out_file, \"\\tset %LLI%d,.+2\\n\",
6993 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6995 asm_fprintf (asm_out_file, \"\\t.set %LLI%d,.+2\\n\",
6996 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
6997 #endif /* not SGS */
6998 #else /* SGS_SWITCH_TABLES or not MOTOROLA */
6999 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, \"LI\",
7000 CODE_LABEL_NUMBER (XEXP (labelref, 0)));
7001 #ifdef SGS_SWITCH_TABLES
7002 /* Set flag saying we need to define the symbol
7003 LD%n (with value L%n-LI%n) at the end of the switch table. */
7004 switch_table_difference_label_flag = 1;
7005 #endif /* SGS_SWITCH_TABLES */
7006 #endif /* SGS_SWITCH_TABLES or not MOTOROLA */
7008 #endif /* SGS_NO_LI */
7010 return \"lea %a1,%0\";
7013 ;; This is the first machine-dependent peephole optimization.
7014 ;; It is useful when a floating value is returned from a function call
7015 ;; and then is moved into an FP register.
7016 ;; But it is mainly intended to test the support for these optimizations.
7019 [(set (reg:SI 15) (plus:SI (reg:SI 15) (const_int 4)))
7020 (set (match_operand:DF 0 "register_operand" "=f")
7021 (match_operand:DF 1 "register_operand" "ad"))]
7022 "FP_REG_P (operands[0]) && ! FP_REG_P (operands[1])"
7026 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1);
7027 output_asm_insn (\"move%.l %1,%@\", xoperands);
7028 output_asm_insn (\"move%.l %1,%-\", operands);
7029 return \"fmove%.d %+,%0\";
7033 ;; Optimize a stack-adjust followed by a push of an argument.
7034 ;; This is said to happen frequently with -msoft-float
7035 ;; when there are consecutive library calls.
7038 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7039 (match_operand:SI 0 "const_int_operand" "n")))
7040 (set (match_operand:SF 1 "push_operand" "=m")
7041 (match_operand:SF 2 "general_operand" "rmfF"))]
7042 "INTVAL (operands[0]) >= 4
7043 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7046 if (INTVAL (operands[0]) > 4)
7049 xoperands[0] = stack_pointer_rtx;
7050 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7052 if (INTVAL (xoperands[1]) <= 8)
7055 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7057 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7059 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7061 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7062 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7066 if (INTVAL (xoperands[1]) <= 0x7FFF)
7069 output_asm_insn (\"add%.w %1,%0\", xoperands);
7072 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7074 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7078 output_asm_insn (\"add%.l %1,%0\", xoperands);
7080 if (FP_REG_P (operands[2]))
7081 return \"fmove%.s %2,%@\";
7082 return \"move%.l %2,%@\";
7085 ;; Speed up stack adjust followed by a fullword fixedpoint push.
7088 [(set (reg:SI 15) (plus:SI (reg:SI 15)
7089 (match_operand:SI 0 "const_int_operand" "n")))
7090 (set (match_operand:SI 1 "push_operand" "=m")
7091 (match_operand:SI 2 "general_operand" "g"))]
7092 "INTVAL (operands[0]) >= 4
7093 && ! reg_mentioned_p (stack_pointer_rtx, operands[2])"
7096 if (INTVAL (operands[0]) > 4)
7099 xoperands[0] = stack_pointer_rtx;
7100 xoperands[1] = GEN_INT (INTVAL (operands[0]) - 4);
7102 if (INTVAL (xoperands[1]) <= 8)
7105 output_asm_insn (\"addq%.w %1,%0\", xoperands);
7107 output_asm_insn (\"addq%.l %1,%0\", xoperands);
7109 else if (TARGET_CPU32 && INTVAL (xoperands[1]) <= 16)
7111 xoperands[1] = GEN_INT (INTVAL (xoperands[1]) - 8);
7112 output_asm_insn (\"addq%.w %#8,%0\;addq%.w %1,%0\", xoperands);
7116 if (INTVAL (xoperands[1]) <= 0x7FFF)
7119 output_asm_insn (\"add%.w %1,%0\", xoperands);
7123 output_asm_insn (\"lea (%c1,%0),%0\", xoperands);
7125 output_asm_insn (\"lea %0@(%c1),%0\", xoperands);
7130 output_asm_insn (\"add%.l %1,%0\", xoperands);
7132 if (operands[2] == const0_rtx)
7133 return \"clr%.l %@\";
7134 return \"move%.l %2,%@\";
7137 ;; Speed up pushing a single byte but leaving four bytes of space.
7140 [(set (mem:QI (pre_dec:SI (reg:SI 15)))
7141 (match_operand:QI 1 "general_operand" "dami"))
7142 (set (reg:SI 15) (minus:SI (reg:SI 15) (const_int 2)))]
7143 "! reg_mentioned_p (stack_pointer_rtx, operands[1])"
7148 if (GET_CODE (operands[1]) == REG)
7149 return \"move%.l %1,%-\";
7151 xoperands[1] = operands[1];
7153 = gen_rtx_MEM (QImode,
7154 gen_rtx_PLUS (VOIDmode, stack_pointer_rtx,
7156 xoperands[3] = stack_pointer_rtx;
7158 output_asm_insn (\"subq%.w %#4,%3\;move%.b %1,%2\", xoperands);
7160 output_asm_insn (\"subq%.l %#4,%3\;move%.b %1,%2\", xoperands);
7165 [(set (match_operand:SI 0 "register_operand" "=d")
7167 (set (strict_low_part (subreg:HI (match_dup 0) 0))
7168 (match_operand:HI 1 "general_operand" "rmn"))]
7169 "strict_low_part_peephole_ok (HImode, prev_nonnote_insn (insn), operands[0])"
7172 if (GET_CODE (operands[1]) == CONST_INT)
7174 if (operands[1] == const0_rtx
7175 && (DATA_REG_P (operands[0])
7176 || GET_CODE (operands[0]) == MEM)
7177 /* clr insns on 68000 read before writing.
7178 This isn't so on the 68010, but we have no TARGET_68010. */
7179 && ((TARGET_68020 || TARGET_5200)
7180 || !(GET_CODE (operands[0]) == MEM
7181 && MEM_VOLATILE_P (operands[0]))))
7182 return \"clr%.w %0\";
7184 return \"move%.w %1,%0\";
7192 ;; jCC label ; abnormal loop termination
7193 ;; dbra dN, loop ; normal loop termination
7201 ;; Which moves the jCC condition outside the inner loop for free.
7204 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7205 [(cc0) (const_int 0)])
7206 (label_ref (match_operand 2 "" ""))
7211 (ge (plus:HI (match_operand:HI 0 "register_operand" "+d")
7214 (label_ref (match_operand 1 "" ""))
7217 (plus:HI (match_dup 0)
7219 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7223 output_dbcc_and_branch (operands);
7228 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p"
7229 [(cc0) (const_int 0)])
7230 (label_ref (match_operand 2 "" ""))
7235 (ge (plus:SI (match_operand:SI 0 "register_operand" "+d")
7238 (label_ref (match_operand 1 "" ""))
7241 (plus:SI (match_dup 0)
7243 "!TARGET_5200 && DATA_REG_P (operands[0]) && ! flags_in_68881 ()"
7247 output_dbcc_and_branch (operands);
7252 ;; FPA multiply and add.
7254 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7255 (plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%x,dmF,y")
7256 (match_operand:DF 2 "general_operand" "xH,y,y"))
7257 (match_operand:DF 3 "general_operand" "xH,y,dmF")))]
7260 fpma%.d %1,%w2,%w3,%0
7261 fpma%.d %x1,%x2,%x3,%0
7262 fpma%.d %x1,%x2,%x3,%0")
7265 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7266 (plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%x,ydmF,y")
7267 (match_operand:SF 2 "general_operand" "xH,y,ydmF"))
7268 (match_operand:SF 3 "general_operand" "xH,ydmF,ydmF")))]
7271 fpma%.s %1,%w2,%w3,%0
7273 fpma%.s %1,%2,%3,%0")
7275 ;; FPA Multiply and subtract
7277 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7278 (minus:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7279 (mult:DF (match_operand:DF 2 "general_operand" "%xH,y,y")
7280 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7283 fpms%.d %3,%w2,%w1,%0
7284 fpms%.d %x3,%2,%x1,%0
7285 fpms%.d %x3,%2,%x1,%0")
7288 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7289 (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7290 (mult:SF (match_operand:SF 2 "general_operand" "%xH,rmF,y")
7291 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7294 fpms%.s %3,%w2,%w1,%0
7296 fpms%.s %3,%2,%1,%0")
7299 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7300 (minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7301 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7302 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7305 fpmr%.d %2,%w1,%w3,%0
7306 fpmr%.d %x2,%1,%x3,%0
7307 fpmr%.d %x2,%1,%x3,%0")
7310 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7311 (minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7312 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7313 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7316 fpmr%.s %2,%w1,%w3,%0
7317 fpmr%.s %x2,%1,%x3,%0
7318 fpmr%.s %x2,%1,%x3,%0")
7320 ;; FPA Add and multiply
7322 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7323 (mult:DF (plus:DF (match_operand:DF 1 "general_operand" "%xH,y,y")
7324 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7325 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7328 fpam%.d %2,%w1,%w3,%0
7329 fpam%.d %x2,%1,%x3,%0
7330 fpam%.d %x2,%1,%x3,%0")
7333 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7334 (mult:SF (plus:SF (match_operand:SF 1 "general_operand" "%xH,rmF,y")
7335 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7336 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7339 fpam%.s %2,%w1,%w3,%0
7340 fpam%.s %x2,%1,%x3,%0
7341 fpam%.s %x2,%1,%x3,%0")
7343 ;;FPA Subtract and multiply
7345 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7346 (mult:DF (minus:DF (match_operand:DF 1 "general_operand" "xH,y,y")
7347 (match_operand:DF 2 "general_operand" "x,y,rmF"))
7348 (match_operand:DF 3 "general_operand" "xH,rmF,y")))]
7351 fpsm%.d %2,%w1,%w3,%0
7352 fpsm%.d %x2,%1,%x3,%0
7353 fpsm%.d %x2,%1,%x3,%0")
7356 [(set (match_operand:DF 0 "register_operand" "=x,y,y")
7357 (mult:DF (match_operand:DF 1 "general_operand" "xH,rmF,y")
7358 (minus:DF (match_operand:DF 2 "general_operand" "xH,y,y")
7359 (match_operand:DF 3 "general_operand" "x,y,rmF"))))]
7362 fpsm%.d %3,%w2,%w1,%0
7363 fpsm%.d %x3,%2,%x1,%0
7364 fpsm%.d %x3,%2,%x1,%0")
7367 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7368 (mult:SF (minus:SF (match_operand:SF 1 "general_operand" "xH,rmF,y")
7369 (match_operand:SF 2 "general_operand" "x,y,yrmF"))
7370 (match_operand:SF 3 "general_operand" "xH,rmF,yrmF")))]
7373 fpsm%.s %2,%w1,%w3,%0
7374 fpsm%.s %x2,%1,%x3,%0
7375 fpsm%.s %x2,%1,%x3,%0")
7378 [(set (match_operand:SF 0 "register_operand" "=x,y,y")
7379 (mult:SF (match_operand:SF 1 "general_operand" "xH,rmF,yrmF")
7380 (minus:SF (match_operand:SF 2 "general_operand" "xH,rmF,y")
7381 (match_operand:SF 3 "general_operand" "x,y,yrmF"))))]
7384 fpsm%.s %3,%w2,%w1,%0
7385 fpsm%.s %x3,%2,%x1,%0
7386 fpsm%.s %x3,%2,%x1,%0")
7388 (define_expand "tstxf"
7390 (match_operand:XF 0 "nonimmediate_operand" ""))]
7392 "m68k_last_compare_had_fp_operands = 1;")
7396 (match_operand:XF 0 "nonimmediate_operand" "fm"))]
7400 cc_status.flags = CC_IN_68881;
7401 return \"ftst%.x %0\";
7404 (define_expand "cmpxf"
7406 (compare (match_operand:XF 0 "nonimmediate_operand" "")
7407 (match_operand:XF 1 "nonimmediate_operand" "")))]
7409 "m68k_last_compare_had_fp_operands = 1;")
7413 (compare (match_operand:XF 0 "nonimmediate_operand" "f,m")
7414 (match_operand:XF 1 "nonimmediate_operand" "fm,f")))]
7418 cc_status.flags = CC_IN_68881;
7419 #ifdef SGS_CMP_ORDER
7420 if (REG_P (operands[0]))
7422 if (REG_P (operands[1]))
7423 return \"fcmp%.x %0,%1\";
7425 return \"fcmp%.x %0,%f1\";
7427 cc_status.flags |= CC_REVERSED;
7428 return \"fcmp%.x %1,%f0\";
7430 if (REG_P (operands[0]))
7432 if (REG_P (operands[1]))
7433 return \"fcmp%.x %1,%0\";
7435 return \"fcmp%.x %f1,%0\";
7437 cc_status.flags |= CC_REVERSED;
7438 return \"fcmp%.x %f0,%1\";
7442 (define_insn "extendsfxf2"
7443 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7444 (float_extend:XF (match_operand:SF 1 "general_operand" "f,m")))]
7448 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7450 if (REGNO (operands[0]) == REGNO (operands[1]))
7452 /* Extending float to double in an fp-reg is a no-op.
7453 NOTICE_UPDATE_CC has already assumed that the
7454 cc will be set. So cancel what it did. */
7455 cc_status = cc_prev_status;
7458 return \"f%$move%.x %1,%0\";
7460 if (FP_REG_P (operands[0]))
7461 return \"f%$move%.s %f1,%0\";
7462 return \"fmove%.x %f1,%0\";
7466 (define_insn "extenddfxf2"
7467 [(set (match_operand:XF 0 "general_operand" "=fm,f")
7469 (match_operand:DF 1 "general_operand" "f,m")))]
7473 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1]))
7475 if (REGNO (operands[0]) == REGNO (operands[1]))
7477 /* Extending float to double in an fp-reg is a no-op.
7478 NOTICE_UPDATE_CC has already assumed that the
7479 cc will be set. So cancel what it did. */
7480 cc_status = cc_prev_status;
7483 return \"fmove%.x %1,%0\";
7485 if (FP_REG_P (operands[0]))
7486 return \"f%&move%.d %f1,%0\";
7487 return \"fmove%.x %f1,%0\";
7490 (define_insn "truncxfdf2"
7491 [(set (match_operand:DF 0 "general_operand" "=m,!r")
7493 (match_operand:XF 1 "general_operand" "f,f")))]
7497 if (REG_P (operands[0]))
7499 output_asm_insn (\"fmove%.d %f1,%-\;move%.l %+,%0\", operands);
7500 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
7501 return \"move%.l %+,%0\";
7503 return \"fmove%.d %f1,%0\";
7506 (define_insn "truncxfsf2"
7507 [(set (match_operand:SF 0 "general_operand" "=dm")
7509 (match_operand:XF 1 "general_operand" "f")))]
7513 (define_insn "floatsixf2"
7514 [(set (match_operand:XF 0 "general_operand" "=f")
7515 (float:XF (match_operand:SI 1 "general_operand" "dmi")))]
7519 (define_insn "floathixf2"
7520 [(set (match_operand:XF 0 "general_operand" "=f")
7521 (float:XF (match_operand:HI 1 "general_operand" "dmn")))]
7525 (define_insn "floatqixf2"
7526 [(set (match_operand:XF 0 "general_operand" "=f")
7527 (float:XF (match_operand:QI 1 "general_operand" "dmn")))]
7531 (define_insn "ftruncxf2"
7532 [(set (match_operand:XF 0 "general_operand" "=f")
7533 (fix:XF (match_operand:XF 1 "general_operand" "fFm")))]
7537 if (FP_REG_P (operands[1]))
7538 return \"fintrz%.x %f1,%0\";
7539 return \"fintrz%.x %f1,%0\";
7542 (define_insn "fixxfqi2"
7543 [(set (match_operand:QI 0 "general_operand" "=dm")
7544 (fix:QI (match_operand:XF 1 "general_operand" "f")))]
7548 (define_insn "fixxfhi2"
7549 [(set (match_operand:HI 0 "general_operand" "=dm")
7550 (fix:HI (match_operand:XF 1 "general_operand" "f")))]
7554 (define_insn "fixxfsi2"
7555 [(set (match_operand:SI 0 "general_operand" "=dm")
7556 (fix:SI (match_operand:XF 1 "general_operand" "f")))]
7561 [(set (match_operand:XF 0 "general_operand" "=f")
7562 (plus:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7563 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7568 [(set (match_operand:XF 0 "general_operand" "=f")
7569 (plus:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7570 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7575 [(set (match_operand:XF 0 "general_operand" "=f")
7576 (plus:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7577 (match_operand:XF 1 "general_operand" "0")))]
7581 (define_insn "addxf3"
7582 [(set (match_operand:XF 0 "general_operand" "=f")
7583 (plus:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7584 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7588 if (REG_P (operands[2]))
7589 return \"fadd%.x %2,%0\";
7590 return \"fadd%.x %f2,%0\";
7594 [(set (match_operand:XF 0 "general_operand" "=f")
7595 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7596 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7601 [(set (match_operand:XF 0 "general_operand" "=f")
7602 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7603 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7608 [(set (match_operand:XF 0 "general_operand" "=f")
7609 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7610 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7614 (define_insn "subxf3"
7615 [(set (match_operand:XF 0 "general_operand" "=f")
7616 (minus:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7617 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7621 if (REG_P (operands[2]))
7622 return \"fsub%.x %2,%0\";
7623 return \"fsub%.x %f2,%0\";
7627 [(set (match_operand:XF 0 "general_operand" "=f")
7628 (mult:XF (float:XF (match_operand:SI 2 "general_operand" "dmi"))
7629 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7634 [(set (match_operand:XF 0 "general_operand" "=f")
7635 (mult:XF (float:XF (match_operand:HI 2 "general_operand" "dmn"))
7636 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7641 [(set (match_operand:XF 0 "general_operand" "=f")
7642 (mult:XF (float:XF (match_operand:QI 2 "general_operand" "dmn"))
7643 (match_operand:XF 1 "nonimmediate_operand" "0")))]
7647 (define_insn "mulxf3"
7648 [(set (match_operand:XF 0 "general_operand" "=f")
7649 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0")
7650 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7654 if (REG_P (operands[2]))
7655 return \"fmul%.x %2,%0\";
7656 return \"fmul%.x %f2,%0\";
7660 [(set (match_operand:XF 0 "general_operand" "=f")
7661 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7662 (float:XF (match_operand:SI 2 "general_operand" "dmi"))))]
7667 [(set (match_operand:XF 0 "general_operand" "=f")
7668 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7669 (float:XF (match_operand:HI 2 "general_operand" "dmn"))))]
7674 [(set (match_operand:XF 0 "general_operand" "=f")
7675 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7676 (float:XF (match_operand:QI 2 "general_operand" "dmn"))))]
7680 (define_insn "divxf3"
7681 [(set (match_operand:XF 0 "general_operand" "=f")
7682 (div:XF (match_operand:XF 1 "nonimmediate_operand" "0")
7683 (match_operand:XF 2 "nonimmediate_operand" "fm")))]
7687 if (REG_P (operands[2]))
7688 return \"fdiv%.x %2,%0\";
7689 return \"fdiv%.x %f2,%0\";
7692 (define_expand "negxf2"
7693 [(set (match_operand:XF 0 "general_operand" "")
7694 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7698 /* ??? There isn't an FPA define_insn so we could handle it here too.
7699 For now we don't (paranoia). */
7707 target = operand_subword (operands[0], 0, 1, XFmode);
7708 result = expand_binop (SImode, xor_optab,
7709 operand_subword_force (operands[1], 0, XFmode),
7710 GEN_INT(0x80000000), target, 0, OPTAB_WIDEN);
7714 if (result != target)
7715 emit_move_insn (result, target);
7717 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7718 operand_subword_force (operands[1], 1, XFmode));
7719 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7720 operand_subword_force (operands[1], 2, XFmode));
7722 insns = get_insns ();
7725 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7730 (define_insn "negxf2_68881"
7731 [(set (match_operand:XF 0 "general_operand" "=f")
7732 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7736 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7737 return \"fneg%.x %1,%0\";
7738 return \"fneg%.x %f1,%0\";
7741 (define_expand "absxf2"
7742 [(set (match_operand:XF 0 "general_operand" "")
7743 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))]
7747 /* ??? There isn't an FPA define_insn so we could handle it here too.
7748 For now we don't (paranoia). */
7756 target = operand_subword (operands[0], 0, 1, XFmode);
7757 result = expand_binop (SImode, and_optab,
7758 operand_subword_force (operands[1], 0, XFmode),
7759 GEN_INT(0x7fffffff), target, 0, OPTAB_WIDEN);
7763 if (result != target)
7764 emit_move_insn (result, target);
7766 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode),
7767 operand_subword_force (operands[1], 1, XFmode));
7768 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode),
7769 operand_subword_force (operands[1], 2, XFmode));
7771 insns = get_insns ();
7774 emit_no_conflict_block (insns, operands[0], operands[1], 0, 0);
7779 (define_insn "absxf2_68881"
7780 [(set (match_operand:XF 0 "general_operand" "=f")
7781 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7785 if (REG_P (operands[1]) && ! DATA_REG_P (operands[1]))
7786 return \"fabs%.x %1,%0\";
7787 return \"fabs%.x %f1,%0\";
7790 (define_insn "sqrtxf2"
7791 [(set (match_operand:XF 0 "general_operand" "=f")
7792 (sqrt:XF (match_operand:XF 1 "nonimmediate_operand" "fm")))]
7796 (define_insn "sinsf2"
7797 [(set (match_operand:SF 0 "general_operand" "=f")
7798 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 1))]
7799 "TARGET_68881 && flag_fast_math"
7802 if (FP_REG_P (operands[1]))
7803 return \"fsin%.x %1,%0\";
7805 return \"fsin%.s %1,%0\";
7808 (define_insn "sindf2"
7809 [(set (match_operand:DF 0 "general_operand" "=f")
7810 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 1))]
7811 "TARGET_68881 && flag_fast_math"
7814 if (FP_REG_P (operands[1]))
7815 return \"fsin%.x %1,%0\";
7817 return \"fsin%.d %1,%0\";
7820 (define_insn "sinxf2"
7821 [(set (match_operand:XF 0 "general_operand" "=f")
7822 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 1))]
7823 "TARGET_68881 && flag_fast_math"
7826 (define_insn "cossf2"
7827 [(set (match_operand:SF 0 "general_operand" "=f")
7828 (unspec:SF [(match_operand:SF 1 "general_operand" "fm")] 2))]
7829 "TARGET_68881 && flag_fast_math"
7832 if (FP_REG_P (operands[1]))
7833 return \"fcos%.x %1,%0\";
7835 return \"fcos%.s %1,%0\";
7838 (define_insn "cosdf2"
7839 [(set (match_operand:DF 0 "general_operand" "=f")
7840 (unspec:DF [(match_operand:DF 1 "general_operand" "fm")] 2))]
7841 "TARGET_68881 && flag_fast_math"
7844 if (FP_REG_P (operands[1]))
7845 return \"fcos%.x %1,%0\";
7847 return \"fcos%.d %1,%0\";
7850 (define_insn "cosxf2"
7851 [(set (match_operand:XF 0 "general_operand" "=f")
7852 (unspec:XF [(match_operand:XF 1 "nonimmediate_operand" "fm")] 2))]
7853 "TARGET_68881 && flag_fast_math"