* config/m68k/m68k.md (adddi3, subdi3): Optimize for constant

	operand.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@19220 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index ee3738a..6c1a2fe 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,8 @@
+Wed Apr 15 10:47:21 1998  Andreas Schwab  <schwab@issan.informatik.uni-dortmund.de>
+
+       * config/m68k/m68k.md (adddi3, subdi3): Optimize for constant
+       operand.
+
 Wed Apr 15 01:21:21 1998  Jeffrey A Law  (law@cygnus.com)
 
        * emit-rtl.c (operand_subword): Rework slightly to avoid

diff --git a/gcc/config/m68k/m68k.md b/gcc/config/m68k/m68k.md
index 881b288..b1501de 100644 (file)
--- a/gcc/config/m68k/m68k.md
+++ b/gcc/config/m68k/m68k.md
@@ -2150,6 +2150,7 @@
        }
       else
        {
+         rtx xoperands[2];
          if (GET_CODE (operands[2]) == REG)
            operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
          else if (GET_CODE (operands[2]) == CONST_DOUBLE)
@@ -2164,8 +2165,30 @@
            }
          else
            operands[1] = adj_offsettable_operand (operands[2], 4);
-         /* TODO : for consts, optimize move and add */
-         return \"move%.l %2,%3\;add%.l %1,%R0\;addx%.l %3,%0\";
+         xoperands[0] = operands[3];
+         xoperands[1] = operands[2];
+         output_asm_insn (output_move_simode (xoperands), xoperands);
+         if (GET_CODE (operands[1]) == CONST_INT)
+           {
+             if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
+               {
+#ifdef NO_ADDSUB_Q
+                 return \"add%.l %1,%R0\;addx%.l %3,%0\";
+#else
+                 return \"addq%.l %1,%R0\;addx%.l %3,%0\";
+#endif
+               }
+             else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
+               {
+                 operands[1] = GEN_INT (-INTVAL (operands[1]));
+#ifdef NO_ADDSUB_Q
+                 return \"sub%.l %1,%R0\;addx%.l %3,%0\";
+#else
+                 return \"subq%.l %1,%R0\;addx%.l %3,%0\";
+#endif
+               }
+           }
+         return \"add%.l %1,%R0\;addx%.l %3,%0\";
        }
     }
   else if (GET_CODE (operands[0]) == MEM)
@@ -2680,6 +2703,7 @@
        }
       else
        {
+         rtx xoperands[2];
          if (GET_CODE (operands[2]) == REG)
            operands[1] = gen_rtx_REG (SImode, REGNO (operands[2]) + 1);
          else if (GET_CODE (operands[2]) == CONST_DOUBLE)
@@ -2694,8 +2718,30 @@
            }
          else
            operands[1] = adj_offsettable_operand (operands[2], 4);
-         /* TODO : for consts, optimize move and sub */
-         return \"move%.l %2,%3\;sub%.l %1,%R0\;subx%.l %3,%0\";
+         xoperands[0] = operands[3];
+         xoperands[1] = operands[2];
+         output_asm_insn (output_move_simode (xoperands), xoperands);
+         if (GET_CODE (operands[1]) == CONST_INT)
+           {
+             if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8)
+               {
+#ifdef NO_ADDSUB_Q
+                 return \"sub%.l %1,%R0\;subx%.l %3,%0\";
+#else
+                 return \"subq%.l %1,%R0\;subx%.l %3,%0\";
+#endif
+               }
+             else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0)
+               {
+                 operands[1] = GEN_INT (-INTVAL (operands[1]));
+#ifdef NO_ADDSUB_Q
+                 return \"add%.l %1,%R0\;subx%.l %3,%0\";
+#else
+                 return \"addq%.l %1,%R0\;subx%.l %3,%0\";
+#endif
+               }
+           }
+         return \"sub%.l %1,%R0\;subx%.l %3,%0\";
        }
     }
   else if (GET_CODE (operands[0]) == MEM)