1 ;; GCC machine description for SSE instructions
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
22 ;; 16 byte integral modes handled by SSE, minus TImode, which gets
23 ;; special-cased for TARGET_64BIT.
24 (define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI])
26 ;; All 16-byte vector modes handled by SSE
27 (define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
29 ;; 32 byte integral vector modes handled by AVX
30 (define_mode_iterator AVX256MODEI [V32QI V16HI V8SI V4DI])
32 ;; All 32-byte vector modes handled by AVX
33 (define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF])
35 ;; All QI vector modes handled by AVX
36 (define_mode_iterator AVXMODEQI [V32QI V16QI])
38 ;; All DI vector modes handled by AVX
39 (define_mode_iterator AVXMODEDI [V4DI V2DI])
41 ;; All vector modes handled by AVX
42 (define_mode_iterator AVXMODE [V16QI V8HI V4SI V2DI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF])
45 (define_mode_iterator SSEMODE12 [V16QI V8HI])
46 (define_mode_iterator SSEMODE24 [V8HI V4SI])
47 (define_mode_iterator SSEMODE14 [V16QI V4SI])
48 (define_mode_iterator SSEMODE124 [V16QI V8HI V4SI])
49 (define_mode_iterator SSEMODE248 [V8HI V4SI V2DI])
50 (define_mode_iterator SSEMODE1248 [V16QI V8HI V4SI V2DI])
51 (define_mode_iterator SSEMODEF4 [SF DF V4SF V2DF])
52 (define_mode_iterator FMA4MODEF4 [V8SF V4DF])
53 (define_mode_iterator SSEMODEF2P [V4SF V2DF])
55 (define_mode_iterator AVX256MODEF2P [V8SF V4DF])
56 (define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF])
57 (define_mode_iterator AVX256MODE4P [V4DI V4DF])
58 (define_mode_iterator AVX256MODE8P [V8SI V8SF])
59 (define_mode_iterator AVXMODEF2P [V4SF V2DF V8SF V4DF])
60 (define_mode_iterator AVXMODEF4P [V4SF V4DF])
61 (define_mode_iterator AVXMODEFDP [V2DF V4DF])
62 (define_mode_iterator AVXMODEFSP [V4SF V8SF])
63 (define_mode_iterator AVXMODEDCVTDQ2PS [V4SF V8SF])
64 (define_mode_iterator AVXMODEDCVTPS2DQ [V4SI V8SI])
66 ;; Int-float size matches
67 (define_mode_iterator SSEMODE4S [V4SF V4SI])
68 (define_mode_iterator SSEMODE2D [V2DF V2DI])
70 ;; Modes handled by integer vcond pattern
71 (define_mode_iterator SSEMODE124C8 [V16QI V8HI V4SI
72 (V2DI "TARGET_SSE4_2")])
74 ;; Mapping from float mode to required SSE level
75 (define_mode_attr sse [(SF "sse") (DF "sse2") (V4SF "sse") (V2DF "sse2")])
77 ;; Mapping from integer vector mode to mnemonic suffix
78 (define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
80 ;; Mapping of the fma4 suffix
81 (define_mode_attr fma4modesuffixf4 [(V8SF "ps") (V4DF "pd")])
82 (define_mode_attr ssemodesuffixf2s [(SF "ss") (DF "sd")
83 (V4SF "ss") (V2DF "sd")])
85 ;; Mapping of the avx suffix
86 (define_mode_attr ssemodesuffixf4 [(SF "ss") (DF "sd")
87 (V4SF "ps") (V2DF "pd")])
89 (define_mode_attr ssemodesuffixf2c [(V4SF "s") (V2DF "d")])
91 ;; Mapping of the max integer size for xop rotate immediate constraint
92 (define_mode_attr sserotatemax [(V16QI "7") (V8HI "15") (V4SI "31") (V2DI "63")])
94 ;; Mapping of vector modes back to the scalar modes
95 (define_mode_attr ssescalarmode [(V4SF "SF") (V2DF "DF")
96 (V16QI "QI") (V8HI "HI")
97 (V4SI "SI") (V2DI "DI")])
99 ;; Mapping of vector modes to a vector mode of double size
100 (define_mode_attr ssedoublesizemode
101 [(V2DF "V4DF") (V2DI "V4DI") (V4SF "V8SF") (V4SI "V8SI")
102 (V8HI "V16HI") (V16QI "V32QI")
103 (V4DF "V8DF") (V8SF "V16SF")
104 (V4DI "V8DI") (V8SI "V16SI") (V16HI "V32HI") (V32QI "V64QI")])
106 ;; Number of scalar elements in each vector type
107 (define_mode_attr ssescalarnum
108 [(V4SF "4") (V2DF "2") (V16QI "16") (V8HI "8") (V4SI "4") (V2DI "2")
109 (V8SF "8") (V4DF "4") (V32QI "32") (V16HI "16") (V8SI "8") (V4DI "4")])
112 (define_mode_attr avxvecmode
113 [(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V4SF "V4SF")
114 (V2DF "V2DF") (V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")
115 (V8SF "V8SF") (V4DF "V4DF")])
116 (define_mode_attr avxvecpsmode
117 [(V16QI "V4SF") (V8HI "V4SF") (V4SI "V4SF") (V2DI "V4SF")
118 (V32QI "V8SF") (V16HI "V8SF") (V8SI "V8SF") (V4DI "V8SF")])
119 (define_mode_attr avxhalfvecmode
120 [(V4SF "V2SF") (V32QI "V16QI") (V16HI "V8HI") (V8SI "V4SI")
121 (V4DI "V2DI") (V8SF "V4SF") (V4DF "V2DF")])
122 (define_mode_attr avxscalarmode
123 [(V16QI "QI") (V8HI "HI") (V4SI "SI") (V4SF "SF") (V2DF "DF")
124 (V8SF "SF") (V4DF "DF")])
125 (define_mode_attr avxcvtvecmode
126 [(V4SF "V4SI") (V8SF "V8SI") (V4SI "V4SF") (V8SI "V8SF")])
127 (define_mode_attr avxpermvecmode
128 [(V2DF "V2DI") (V4SF "V4SI") (V4DF "V4DI") (V8SF "V8SI")])
129 (define_mode_attr avxmodesuffixf2c
130 [(V4SF "s") (V2DF "d") (V8SF "s") (V4DF "d")])
131 (define_mode_attr avxmodesuffixp
132 [(V2DF "pd") (V4SI "si") (V4SF "ps") (V8SF "ps") (V8SI "si")
134 (define_mode_attr avxmodesuffix
135 [(V16QI "") (V32QI "256") (V4SI "") (V4SF "") (V2DF "")
136 (V8SI "256") (V8SF "256") (V4DF "256")])
138 ;; Mapping of immediate bits for blend instructions
139 (define_mode_attr blendbits
140 [(V8SF "255") (V4SF "15") (V4DF "15") (V2DF "3")])
142 ;; Mapping of immediate bits for pinsr instructions
143 (define_mode_attr pinsrbits [(V16QI "32768") (V8HI "128") (V4SI "8")])
145 ;; Patterns whose name begins with "sse{,2,3}_" are invoked by intrinsics.
147 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
151 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
153 (define_expand "mov<mode>"
154 [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "")
155 (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))]
158 ix86_expand_vector_move (<MODE>mode, operands);
162 (define_insn "*avx_mov<mode>_internal"
163 [(set (match_operand:AVXMODE 0 "nonimmediate_operand" "=x,x ,m")
164 (match_operand:AVXMODE 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
166 && (register_operand (operands[0], <MODE>mode)
167 || register_operand (operands[1], <MODE>mode))"
169 switch (which_alternative)
172 return standard_sse_constant_opcode (insn, operands[1]);
175 switch (get_attr_mode (insn))
179 return "vmovaps\t{%1, %0|%0, %1}";
182 return "vmovapd\t{%1, %0|%0, %1}";
184 return "vmovdqa\t{%1, %0|%0, %1}";
190 [(set_attr "type" "sselog1,ssemov,ssemov")
191 (set_attr "prefix" "vex")
192 (set_attr "mode" "<avxvecmode>")])
194 ;; All of these patterns are enabled for SSE1 as well as SSE2.
195 ;; This is essential for maintaining stable calling conventions.
197 (define_expand "mov<mode>"
198 [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "")
199 (match_operand:SSEMODE 1 "nonimmediate_operand" ""))]
202 ix86_expand_vector_move (<MODE>mode, operands);
206 (define_insn "*mov<mode>_internal"
207 [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "=x,x ,m")
208 (match_operand:SSEMODE 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
210 && (register_operand (operands[0], <MODE>mode)
211 || register_operand (operands[1], <MODE>mode))"
213 switch (which_alternative)
216 return standard_sse_constant_opcode (insn, operands[1]);
219 switch (get_attr_mode (insn))
222 return "movaps\t{%1, %0|%0, %1}";
224 return "movapd\t{%1, %0|%0, %1}";
226 return "movdqa\t{%1, %0|%0, %1}";
232 [(set_attr "type" "sselog1,ssemov,ssemov")
234 (cond [(ior (ior (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
235 (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
236 (and (eq_attr "alternative" "2")
237 (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
239 (const_string "V4SF")
240 (eq (const_string "<MODE>mode") (const_string "V4SFmode"))
241 (const_string "V4SF")
242 (eq (const_string "<MODE>mode") (const_string "V2DFmode"))
243 (const_string "V2DF")
245 (const_string "TI")))])
247 ;; Move a DI from a 32-bit register pair (e.g. %edx:%eax) to an xmm.
248 ;; We'd rather avoid this entirely; if the 32-bit reg pair was loaded
249 ;; from memory, we'd prefer to load the memory directly into the %xmm
250 ;; register. To facilitate this happy circumstance, this pattern won't
251 ;; split until after register allocation. If the 64-bit value didn't
252 ;; come from memory, this is the best we can do. This is much better
253 ;; than storing %edx:%eax into a stack temporary and loading an %xmm
256 (define_insn_and_split "movdi_to_sse"
258 [(set (match_operand:V4SI 0 "register_operand" "=?x,x")
259 (subreg:V4SI (match_operand:DI 1 "nonimmediate_operand" "r,m") 0))
260 (clobber (match_scratch:V4SI 2 "=&x,X"))])]
261 "!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES"
263 "&& reload_completed"
266 if (register_operand (operands[1], DImode))
268 /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
269 Assemble the 64-bit DImode value in an xmm register. */
270 emit_insn (gen_sse2_loadld (operands[0], CONST0_RTX (V4SImode),
271 gen_rtx_SUBREG (SImode, operands[1], 0)));
272 emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode),
273 gen_rtx_SUBREG (SImode, operands[1], 4)));
274 emit_insn (gen_sse2_punpckldq (operands[0], operands[0], operands[2]));
276 else if (memory_operand (operands[1], DImode))
277 emit_insn (gen_vec_concatv2di (gen_lowpart (V2DImode, operands[0]), operands[1], const0_rtx));
283 [(set (match_operand:V4SF 0 "register_operand" "")
284 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
285 "TARGET_SSE && reload_completed"
288 (vec_duplicate:V4SF (match_dup 1))
292 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
293 operands[2] = CONST0_RTX (V4SFmode);
297 [(set (match_operand:V2DF 0 "register_operand" "")
298 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
299 "TARGET_SSE2 && reload_completed"
300 [(set (match_dup 0) (vec_concat:V2DF (match_dup 1) (match_dup 2)))]
302 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
303 operands[2] = CONST0_RTX (DFmode);
306 (define_expand "push<mode>1"
307 [(match_operand:AVX256MODE 0 "register_operand" "")]
310 ix86_expand_push (<MODE>mode, operands[0]);
314 (define_expand "push<mode>1"
315 [(match_operand:SSEMODE 0 "register_operand" "")]
318 ix86_expand_push (<MODE>mode, operands[0]);
322 (define_expand "movmisalign<mode>"
323 [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "")
324 (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))]
327 ix86_expand_vector_move_misalign (<MODE>mode, operands);
331 (define_expand "movmisalign<mode>"
332 [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "")
333 (match_operand:SSEMODE 1 "nonimmediate_operand" ""))]
336 ix86_expand_vector_move_misalign (<MODE>mode, operands);
340 (define_insn "avx_movup<avxmodesuffixf2c><avxmodesuffix>"
341 [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m")
343 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")]
345 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
346 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
347 "vmovup<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
348 [(set_attr "type" "ssemov")
349 (set_attr "movu" "1")
350 (set_attr "prefix" "vex")
351 (set_attr "mode" "<MODE>")])
353 (define_insn "sse2_movq128"
354 [(set (match_operand:V2DI 0 "register_operand" "=x")
357 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
358 (parallel [(const_int 0)]))
361 "%vmovq\t{%1, %0|%0, %1}"
362 [(set_attr "type" "ssemov")
363 (set_attr "prefix" "maybe_vex")
364 (set_attr "mode" "TI")])
366 (define_insn "<sse>_movup<ssemodesuffixf2c>"
367 [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
369 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
371 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
372 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
373 "movup<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
374 [(set_attr "type" "ssemov")
375 (set_attr "movu" "1")
376 (set_attr "mode" "<MODE>")])
378 (define_insn "avx_movdqu<avxmodesuffix>"
379 [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m")
381 [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")]
383 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
384 "vmovdqu\t{%1, %0|%0, %1}"
385 [(set_attr "type" "ssemov")
386 (set_attr "movu" "1")
387 (set_attr "prefix" "vex")
388 (set_attr "mode" "<avxvecmode>")])
390 (define_insn "sse2_movdqu"
391 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
392 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
394 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
395 "movdqu\t{%1, %0|%0, %1}"
396 [(set_attr "type" "ssemov")
397 (set_attr "movu" "1")
398 (set_attr "prefix_data16" "1")
399 (set_attr "mode" "TI")])
401 (define_insn "avx_movnt<mode>"
402 [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
404 [(match_operand:AVXMODEF2P 1 "register_operand" "x")]
406 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
407 "vmovntp<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
408 [(set_attr "type" "ssemov")
409 (set_attr "prefix" "vex")
410 (set_attr "mode" "<MODE>")])
412 (define_insn "<sse>_movnt<mode>"
413 [(set (match_operand:SSEMODEF2P 0 "memory_operand" "=m")
415 [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
417 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
418 "movntp<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
419 [(set_attr "type" "ssemov")
420 (set_attr "mode" "<MODE>")])
422 (define_insn "avx_movnt<mode>"
423 [(set (match_operand:AVXMODEDI 0 "memory_operand" "=m")
425 [(match_operand:AVXMODEDI 1 "register_operand" "x")]
428 "vmovntdq\t{%1, %0|%0, %1}"
429 [(set_attr "type" "ssecvt")
430 (set_attr "prefix" "vex")
431 (set_attr "mode" "<avxvecmode>")])
433 (define_insn "sse2_movntv2di"
434 [(set (match_operand:V2DI 0 "memory_operand" "=m")
435 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
438 "movntdq\t{%1, %0|%0, %1}"
439 [(set_attr "type" "ssemov")
440 (set_attr "prefix_data16" "1")
441 (set_attr "mode" "TI")])
443 (define_insn "sse2_movntsi"
444 [(set (match_operand:SI 0 "memory_operand" "=m")
445 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
448 "movnti\t{%1, %0|%0, %1}"
449 [(set_attr "type" "ssemov")
450 (set_attr "prefix_data16" "0")
451 (set_attr "mode" "V2DF")])
453 (define_insn "avx_lddqu<avxmodesuffix>"
454 [(set (match_operand:AVXMODEQI 0 "register_operand" "=x")
456 [(match_operand:AVXMODEQI 1 "memory_operand" "m")]
459 "vlddqu\t{%1, %0|%0, %1}"
460 [(set_attr "type" "ssecvt")
461 (set_attr "movu" "1")
462 (set_attr "prefix" "vex")
463 (set_attr "mode" "<avxvecmode>")])
465 (define_insn "sse3_lddqu"
466 [(set (match_operand:V16QI 0 "register_operand" "=x")
467 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
470 "lddqu\t{%1, %0|%0, %1}"
471 [(set_attr "type" "ssemov")
472 (set_attr "movu" "1")
473 (set_attr "prefix_data16" "0")
474 (set_attr "prefix_rep" "1")
475 (set_attr "mode" "TI")])
477 ; Expand patterns for non-temporal stores. At the moment, only those
478 ; that directly map to insns are defined; it would be possible to
479 ; define patterns for other modes that would expand to several insns.
481 (define_expand "storent<mode>"
482 [(set (match_operand:SSEMODEF2P 0 "memory_operand" "")
484 [(match_operand:SSEMODEF2P 1 "register_operand" "")]
486 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
489 (define_expand "storent<mode>"
490 [(set (match_operand:MODEF 0 "memory_operand" "")
492 [(match_operand:MODEF 1 "register_operand" "")]
497 (define_expand "storentv2di"
498 [(set (match_operand:V2DI 0 "memory_operand" "")
499 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "")]
504 (define_expand "storentsi"
505 [(set (match_operand:SI 0 "memory_operand" "")
506 (unspec:SI [(match_operand:SI 1 "register_operand" "")]
511 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
513 ;; Parallel floating point arithmetic
515 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
517 (define_expand "<code><mode>2"
518 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
520 (match_operand:SSEMODEF2P 1 "register_operand" "")))]
521 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
522 "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
524 (define_expand "<plusminus_insn><mode>3"
525 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
526 (plusminus:AVX256MODEF2P
527 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
528 (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
529 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
530 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
532 (define_insn "*avx_<plusminus_insn><mode>3"
533 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
534 (plusminus:AVXMODEF2P
535 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "<comm>x")
536 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
537 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
538 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
539 "v<plusminus_mnemonic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
540 [(set_attr "type" "sseadd")
541 (set_attr "prefix" "vex")
542 (set_attr "mode" "<avxvecmode>")])
544 (define_expand "<plusminus_insn><mode>3"
545 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
546 (plusminus:SSEMODEF2P
547 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
548 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
549 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
550 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
552 (define_insn "*<plusminus_insn><mode>3"
553 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
554 (plusminus:SSEMODEF2P
555 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "<comm>0")
556 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
557 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
558 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
559 "<plusminus_mnemonic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
560 [(set_attr "type" "sseadd")
561 (set_attr "mode" "<MODE>")])
563 (define_insn "*avx_vm<plusminus_insn><mode>3"
564 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
565 (vec_merge:SSEMODEF2P
566 (plusminus:SSEMODEF2P
567 (match_operand:SSEMODEF2P 1 "register_operand" "x")
568 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
571 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
572 "v<plusminus_mnemonic>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
573 [(set_attr "type" "sseadd")
574 (set_attr "prefix" "vex")
575 (set_attr "mode" "<ssescalarmode>")])
577 (define_insn "<sse>_vm<plusminus_insn><mode>3"
578 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
579 (vec_merge:SSEMODEF2P
580 (plusminus:SSEMODEF2P
581 (match_operand:SSEMODEF2P 1 "register_operand" "0")
582 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
585 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
586 "<plusminus_mnemonic>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
587 [(set_attr "type" "sseadd")
588 (set_attr "mode" "<ssescalarmode>")])
590 (define_expand "mul<mode>3"
591 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
593 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
594 (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
595 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
596 "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
598 (define_insn "*avx_mul<mode>3"
599 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
601 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
602 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
603 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
604 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
605 "vmulp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
606 [(set_attr "type" "ssemul")
607 (set_attr "prefix" "vex")
608 (set_attr "mode" "<avxvecmode>")])
610 (define_expand "mul<mode>3"
611 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
613 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
614 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
615 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
616 "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
618 (define_insn "*mul<mode>3"
619 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
621 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
622 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
623 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
624 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
625 "mulp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
626 [(set_attr "type" "ssemul")
627 (set_attr "mode" "<MODE>")])
629 (define_insn "*avx_vmmul<mode>3"
630 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
631 (vec_merge:SSEMODEF2P
633 (match_operand:SSEMODEF2P 1 "register_operand" "x")
634 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
637 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
638 "vmuls<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
639 [(set_attr "type" "ssemul")
640 (set_attr "prefix" "vex")
641 (set_attr "mode" "<ssescalarmode>")])
643 (define_insn "<sse>_vmmul<mode>3"
644 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
645 (vec_merge:SSEMODEF2P
647 (match_operand:SSEMODEF2P 1 "register_operand" "0")
648 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
651 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
652 "muls<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
653 [(set_attr "type" "ssemul")
654 (set_attr "mode" "<ssescalarmode>")])
656 (define_expand "divv8sf3"
657 [(set (match_operand:V8SF 0 "register_operand" "")
658 (div:V8SF (match_operand:V8SF 1 "register_operand" "")
659 (match_operand:V8SF 2 "nonimmediate_operand" "")))]
662 ix86_fixup_binary_operands_no_copy (DIV, V8SFmode, operands);
664 if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
665 && flag_finite_math_only && !flag_trapping_math
666 && flag_unsafe_math_optimizations)
668 ix86_emit_swdivsf (operands[0], operands[1],
669 operands[2], V8SFmode);
674 (define_expand "divv4df3"
675 [(set (match_operand:V4DF 0 "register_operand" "")
676 (div:V4DF (match_operand:V4DF 1 "register_operand" "")
677 (match_operand:V4DF 2 "nonimmediate_operand" "")))]
679 "ix86_fixup_binary_operands_no_copy (DIV, V4DFmode, operands);")
681 (define_insn "avx_div<mode>3"
682 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
684 (match_operand:AVXMODEF2P 1 "register_operand" "x")
685 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
686 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
687 "vdivp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
688 [(set_attr "type" "ssediv")
689 (set_attr "prefix" "vex")
690 (set_attr "mode" "<MODE>")])
692 (define_expand "divv4sf3"
693 [(set (match_operand:V4SF 0 "register_operand" "")
694 (div:V4SF (match_operand:V4SF 1 "register_operand" "")
695 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
698 if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
699 && flag_finite_math_only && !flag_trapping_math
700 && flag_unsafe_math_optimizations)
702 ix86_emit_swdivsf (operands[0], operands[1],
703 operands[2], V4SFmode);
708 (define_expand "divv2df3"
709 [(set (match_operand:V2DF 0 "register_operand" "")
710 (div:V2DF (match_operand:V2DF 1 "register_operand" "")
711 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
715 (define_insn "*avx_div<mode>3"
716 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
718 (match_operand:SSEMODEF2P 1 "register_operand" "x")
719 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
720 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
721 "vdivp<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
722 [(set_attr "type" "ssediv")
723 (set_attr "prefix" "vex")
724 (set_attr "mode" "<MODE>")])
726 (define_insn "<sse>_div<mode>3"
727 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
729 (match_operand:SSEMODEF2P 1 "register_operand" "0")
730 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
731 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
732 "divp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
733 [(set_attr "type" "ssediv")
734 (set_attr "mode" "<MODE>")])
736 (define_insn "*avx_vmdiv<mode>3"
737 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
738 (vec_merge:SSEMODEF2P
740 (match_operand:SSEMODEF2P 1 "register_operand" "x")
741 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
744 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
745 "vdivs<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
746 [(set_attr "type" "ssediv")
747 (set_attr "prefix" "vex")
748 (set_attr "mode" "<ssescalarmode>")])
750 (define_insn "<sse>_vmdiv<mode>3"
751 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
752 (vec_merge:SSEMODEF2P
754 (match_operand:SSEMODEF2P 1 "register_operand" "0")
755 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
758 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
759 "divs<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
760 [(set_attr "type" "ssediv")
761 (set_attr "mode" "<ssescalarmode>")])
763 (define_insn "avx_rcpv8sf2"
764 [(set (match_operand:V8SF 0 "register_operand" "=x")
766 [(match_operand:V8SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
768 "vrcpps\t{%1, %0|%0, %1}"
769 [(set_attr "type" "sse")
770 (set_attr "prefix" "vex")
771 (set_attr "mode" "V8SF")])
773 (define_insn "sse_rcpv4sf2"
774 [(set (match_operand:V4SF 0 "register_operand" "=x")
776 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
778 "%vrcpps\t{%1, %0|%0, %1}"
779 [(set_attr "type" "sse")
780 (set_attr "atom_sse_attr" "rcp")
781 (set_attr "prefix" "maybe_vex")
782 (set_attr "mode" "V4SF")])
784 (define_insn "*avx_vmrcpv4sf2"
785 [(set (match_operand:V4SF 0 "register_operand" "=x")
787 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
789 (match_operand:V4SF 2 "register_operand" "x")
792 "vrcpss\t{%1, %2, %0|%0, %2, %1}"
793 [(set_attr "type" "sse")
794 (set_attr "prefix" "vex")
795 (set_attr "mode" "SF")])
797 (define_insn "sse_vmrcpv4sf2"
798 [(set (match_operand:V4SF 0 "register_operand" "=x")
800 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
802 (match_operand:V4SF 2 "register_operand" "0")
805 "rcpss\t{%1, %0|%0, %1}"
806 [(set_attr "type" "sse")
807 (set_attr "atom_sse_attr" "rcp")
808 (set_attr "mode" "SF")])
810 (define_expand "sqrtv8sf2"
811 [(set (match_operand:V8SF 0 "register_operand" "")
812 (sqrt:V8SF (match_operand:V8SF 1 "nonimmediate_operand" "")))]
815 if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
816 && flag_finite_math_only && !flag_trapping_math
817 && flag_unsafe_math_optimizations)
819 ix86_emit_swsqrtsf (operands[0], operands[1], V8SFmode, 0);
824 (define_insn "avx_sqrtv8sf2"
825 [(set (match_operand:V8SF 0 "register_operand" "=x")
826 (sqrt:V8SF (match_operand:V8SF 1 "nonimmediate_operand" "xm")))]
828 "vsqrtps\t{%1, %0|%0, %1}"
829 [(set_attr "type" "sse")
830 (set_attr "prefix" "vex")
831 (set_attr "mode" "V8SF")])
833 (define_expand "sqrtv4sf2"
834 [(set (match_operand:V4SF 0 "register_operand" "")
835 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
838 if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
839 && flag_finite_math_only && !flag_trapping_math
840 && flag_unsafe_math_optimizations)
842 ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 0);
847 (define_insn "sse_sqrtv4sf2"
848 [(set (match_operand:V4SF 0 "register_operand" "=x")
849 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
851 "%vsqrtps\t{%1, %0|%0, %1}"
852 [(set_attr "type" "sse")
853 (set_attr "atom_sse_attr" "sqrt")
854 (set_attr "prefix" "maybe_vex")
855 (set_attr "mode" "V4SF")])
857 (define_insn "sqrtv4df2"
858 [(set (match_operand:V4DF 0 "register_operand" "=x")
859 (sqrt:V4DF (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
861 "vsqrtpd\t{%1, %0|%0, %1}"
862 [(set_attr "type" "sse")
863 (set_attr "prefix" "vex")
864 (set_attr "mode" "V4DF")])
866 (define_insn "sqrtv2df2"
867 [(set (match_operand:V2DF 0 "register_operand" "=x")
868 (sqrt:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
870 "%vsqrtpd\t{%1, %0|%0, %1}"
871 [(set_attr "type" "sse")
872 (set_attr "prefix" "maybe_vex")
873 (set_attr "mode" "V2DF")])
875 (define_insn "*avx_vmsqrt<mode>2"
876 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
877 (vec_merge:SSEMODEF2P
879 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm"))
880 (match_operand:SSEMODEF2P 2 "register_operand" "x")
882 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
883 "vsqrts<ssemodesuffixf2c>\t{%1, %2, %0|%0, %2, %1}"
884 [(set_attr "type" "sse")
885 (set_attr "prefix" "vex")
886 (set_attr "mode" "<ssescalarmode>")])
888 (define_insn "<sse>_vmsqrt<mode>2"
889 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
890 (vec_merge:SSEMODEF2P
892 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm"))
893 (match_operand:SSEMODEF2P 2 "register_operand" "0")
895 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
896 "sqrts<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
897 [(set_attr "type" "sse")
898 (set_attr "atom_sse_attr" "sqrt")
899 (set_attr "mode" "<ssescalarmode>")])
901 (define_expand "rsqrtv8sf2"
902 [(set (match_operand:V8SF 0 "register_operand" "")
904 [(match_operand:V8SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
905 "TARGET_AVX && TARGET_SSE_MATH"
907 ix86_emit_swsqrtsf (operands[0], operands[1], V8SFmode, 1);
911 (define_insn "avx_rsqrtv8sf2"
912 [(set (match_operand:V8SF 0 "register_operand" "=x")
914 [(match_operand:V8SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
916 "vrsqrtps\t{%1, %0|%0, %1}"
917 [(set_attr "type" "sse")
918 (set_attr "prefix" "vex")
919 (set_attr "mode" "V8SF")])
921 (define_expand "rsqrtv4sf2"
922 [(set (match_operand:V4SF 0 "register_operand" "")
924 [(match_operand:V4SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
927 ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 1);
931 (define_insn "sse_rsqrtv4sf2"
932 [(set (match_operand:V4SF 0 "register_operand" "=x")
934 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
936 "%vrsqrtps\t{%1, %0|%0, %1}"
937 [(set_attr "type" "sse")
938 (set_attr "prefix" "maybe_vex")
939 (set_attr "mode" "V4SF")])
941 (define_insn "*avx_vmrsqrtv4sf2"
942 [(set (match_operand:V4SF 0 "register_operand" "=x")
944 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
946 (match_operand:V4SF 2 "register_operand" "x")
949 "vrsqrtss\t{%1, %2, %0|%0, %2, %1}"
950 [(set_attr "type" "sse")
951 (set_attr "prefix" "vex")
952 (set_attr "mode" "SF")])
954 (define_insn "sse_vmrsqrtv4sf2"
955 [(set (match_operand:V4SF 0 "register_operand" "=x")
957 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
959 (match_operand:V4SF 2 "register_operand" "0")
962 "rsqrtss\t{%1, %0|%0, %1}"
963 [(set_attr "type" "sse")
964 (set_attr "mode" "SF")])
966 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
967 ;; isn't really correct, as those rtl operators aren't defined when
968 ;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
970 (define_expand "<code><mode>3"
971 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
972 (smaxmin:AVX256MODEF2P
973 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
974 (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
975 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
977 if (!flag_finite_math_only)
978 operands[1] = force_reg (<MODE>mode, operands[1]);
979 ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
982 (define_expand "<code><mode>3"
983 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
985 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
986 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
987 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
989 if (!flag_finite_math_only)
990 operands[1] = force_reg (<MODE>mode, operands[1]);
991 ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
994 (define_insn "*avx_<code><mode>3_finite"
995 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
997 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
998 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
999 "AVX_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
1000 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1001 "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1002 [(set_attr "type" "sseadd")
1003 (set_attr "prefix" "vex")
1004 (set_attr "mode" "<MODE>")])
1006 (define_insn "*<code><mode>3_finite"
1007 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1009 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
1010 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1011 "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
1012 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1013 "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1014 [(set_attr "type" "sseadd")
1015 (set_attr "mode" "<MODE>")])
1017 (define_insn "*avx_<code><mode>3"
1018 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1020 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
1021 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1022 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1023 "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1024 [(set_attr "type" "sseadd")
1025 (set_attr "prefix" "vex")
1026 (set_attr "mode" "<avxvecmode>")])
1028 (define_insn "*<code><mode>3"
1029 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1031 (match_operand:SSEMODEF2P 1 "register_operand" "0")
1032 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1033 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1034 "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1035 [(set_attr "type" "sseadd")
1036 (set_attr "mode" "<MODE>")])
1038 (define_insn "*avx_vm<code><mode>3"
1039 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1040 (vec_merge:SSEMODEF2P
1042 (match_operand:SSEMODEF2P 1 "register_operand" "x")
1043 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
1046 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
1047 "v<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1048 [(set_attr "type" "sse")
1049 (set_attr "prefix" "vex")
1050 (set_attr "mode" "<ssescalarmode>")])
1052 (define_insn "<sse>_vm<code><mode>3"
1053 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1054 (vec_merge:SSEMODEF2P
1056 (match_operand:SSEMODEF2P 1 "register_operand" "0")
1057 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
1060 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1061 "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1062 [(set_attr "type" "sseadd")
1063 (set_attr "mode" "<ssescalarmode>")])
1065 ;; These versions of the min/max patterns implement exactly the operations
1066 ;; min = (op1 < op2 ? op1 : op2)
1067 ;; max = (!(op1 < op2) ? op1 : op2)
1068 ;; Their operands are not commutative, and thus they may be used in the
1069 ;; presence of -0.0 and NaN.
1071 (define_insn "*avx_ieee_smin<mode>3"
1072 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1074 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
1075 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]
1077 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1078 "vminp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1079 [(set_attr "type" "sseadd")
1080 (set_attr "prefix" "vex")
1081 (set_attr "mode" "<avxvecmode>")])
1083 (define_insn "*avx_ieee_smax<mode>3"
1084 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1086 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
1087 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]
1089 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1090 "vmaxp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1091 [(set_attr "type" "sseadd")
1092 (set_attr "prefix" "vex")
1093 (set_attr "mode" "<avxvecmode>")])
1095 (define_insn "*ieee_smin<mode>3"
1096 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1098 [(match_operand:SSEMODEF2P 1 "register_operand" "0")
1099 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]
1101 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1102 "minp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1103 [(set_attr "type" "sseadd")
1104 (set_attr "mode" "<MODE>")])
1106 (define_insn "*ieee_smax<mode>3"
1107 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1109 [(match_operand:SSEMODEF2P 1 "register_operand" "0")
1110 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]
1112 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1113 "maxp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1114 [(set_attr "type" "sseadd")
1115 (set_attr "mode" "<MODE>")])
1117 (define_insn "avx_addsubv8sf3"
1118 [(set (match_operand:V8SF 0 "register_operand" "=x")
1121 (match_operand:V8SF 1 "register_operand" "x")
1122 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
1123 (minus:V8SF (match_dup 1) (match_dup 2))
1126 "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
1127 [(set_attr "type" "sseadd")
1128 (set_attr "prefix" "vex")
1129 (set_attr "mode" "V8SF")])
1131 (define_insn "avx_addsubv4df3"
1132 [(set (match_operand:V4DF 0 "register_operand" "=x")
1135 (match_operand:V4DF 1 "register_operand" "x")
1136 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
1137 (minus:V4DF (match_dup 1) (match_dup 2))
1140 "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
1141 [(set_attr "type" "sseadd")
1142 (set_attr "prefix" "vex")
1143 (set_attr "mode" "V4DF")])
1145 (define_insn "*avx_addsubv4sf3"
1146 [(set (match_operand:V4SF 0 "register_operand" "=x")
1149 (match_operand:V4SF 1 "register_operand" "x")
1150 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
1151 (minus:V4SF (match_dup 1) (match_dup 2))
1154 "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
1155 [(set_attr "type" "sseadd")
1156 (set_attr "prefix" "vex")
1157 (set_attr "mode" "V4SF")])
1159 (define_insn "sse3_addsubv4sf3"
1160 [(set (match_operand:V4SF 0 "register_operand" "=x")
1163 (match_operand:V4SF 1 "register_operand" "0")
1164 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
1165 (minus:V4SF (match_dup 1) (match_dup 2))
1168 "addsubps\t{%2, %0|%0, %2}"
1169 [(set_attr "type" "sseadd")
1170 (set_attr "prefix_rep" "1")
1171 (set_attr "mode" "V4SF")])
1173 (define_insn "*avx_addsubv2df3"
1174 [(set (match_operand:V2DF 0 "register_operand" "=x")
1177 (match_operand:V2DF 1 "register_operand" "x")
1178 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1179 (minus:V2DF (match_dup 1) (match_dup 2))
1182 "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
1183 [(set_attr "type" "sseadd")
1184 (set_attr "prefix" "vex")
1185 (set_attr "mode" "V2DF")])
1187 (define_insn "sse3_addsubv2df3"
1188 [(set (match_operand:V2DF 0 "register_operand" "=x")
1191 (match_operand:V2DF 1 "register_operand" "0")
1192 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1193 (minus:V2DF (match_dup 1) (match_dup 2))
1196 "addsubpd\t{%2, %0|%0, %2}"
1197 [(set_attr "type" "sseadd")
1198 (set_attr "atom_unit" "complex")
1199 (set_attr "mode" "V2DF")])
1201 (define_insn "avx_h<plusminus_insn>v4df3"
1202 [(set (match_operand:V4DF 0 "register_operand" "=x")
1207 (match_operand:V4DF 1 "register_operand" "x")
1208 (parallel [(const_int 0)]))
1209 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1211 (vec_select:DF (match_dup 1) (parallel [(const_int 2)]))
1212 (vec_select:DF (match_dup 1) (parallel [(const_int 3)]))))
1216 (match_operand:V4DF 2 "nonimmediate_operand" "xm")
1217 (parallel [(const_int 0)]))
1218 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))
1220 (vec_select:DF (match_dup 2) (parallel [(const_int 2)]))
1221 (vec_select:DF (match_dup 2) (parallel [(const_int 3)]))))))]
1223 "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
1224 [(set_attr "type" "sseadd")
1225 (set_attr "prefix" "vex")
1226 (set_attr "mode" "V4DF")])
1228 (define_insn "avx_h<plusminus_insn>v8sf3"
1229 [(set (match_operand:V8SF 0 "register_operand" "=x")
1235 (match_operand:V8SF 1 "register_operand" "x")
1236 (parallel [(const_int 0)]))
1237 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1239 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
1240 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
1244 (match_operand:V8SF 2 "nonimmediate_operand" "xm")
1245 (parallel [(const_int 0)]))
1246 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
1248 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
1249 (vec_select:SF (match_dup 2) (parallel [(const_int 3)])))))
1253 (vec_select:SF (match_dup 1) (parallel [(const_int 4)]))
1254 (vec_select:SF (match_dup 1) (parallel [(const_int 5)])))
1256 (vec_select:SF (match_dup 1) (parallel [(const_int 6)]))
1257 (vec_select:SF (match_dup 1) (parallel [(const_int 7)]))))
1260 (vec_select:SF (match_dup 2) (parallel [(const_int 4)]))
1261 (vec_select:SF (match_dup 2) (parallel [(const_int 5)])))
1263 (vec_select:SF (match_dup 2) (parallel [(const_int 6)]))
1264 (vec_select:SF (match_dup 2) (parallel [(const_int 7)])))))))]
1266 "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
1267 [(set_attr "type" "sseadd")
1268 (set_attr "prefix" "vex")
1269 (set_attr "mode" "V8SF")])
1271 (define_insn "*avx_h<plusminus_insn>v4sf3"
1272 [(set (match_operand:V4SF 0 "register_operand" "=x")
1277 (match_operand:V4SF 1 "register_operand" "x")
1278 (parallel [(const_int 0)]))
1279 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1281 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
1282 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
1286 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
1287 (parallel [(const_int 0)]))
1288 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
1290 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
1291 (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
1293 "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
1294 [(set_attr "type" "sseadd")
1295 (set_attr "prefix" "vex")
1296 (set_attr "mode" "V4SF")])
1298 (define_insn "sse3_h<plusminus_insn>v4sf3"
1299 [(set (match_operand:V4SF 0 "register_operand" "=x")
1304 (match_operand:V4SF 1 "register_operand" "0")
1305 (parallel [(const_int 0)]))
1306 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1308 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
1309 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
1313 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
1314 (parallel [(const_int 0)]))
1315 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
1317 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
1318 (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
1320 "h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}"
1321 [(set_attr "type" "sseadd")
1322 (set_attr "atom_unit" "complex")
1323 (set_attr "prefix_rep" "1")
1324 (set_attr "mode" "V4SF")])
1326 (define_insn "*avx_h<plusminus_insn>v2df3"
1327 [(set (match_operand:V2DF 0 "register_operand" "=x")
1331 (match_operand:V2DF 1 "register_operand" "x")
1332 (parallel [(const_int 0)]))
1333 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1336 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
1337 (parallel [(const_int 0)]))
1338 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
1340 "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
1341 [(set_attr "type" "sseadd")
1342 (set_attr "prefix" "vex")
1343 (set_attr "mode" "V2DF")])
1345 (define_insn "sse3_h<plusminus_insn>v2df3"
1346 [(set (match_operand:V2DF 0 "register_operand" "=x")
1350 (match_operand:V2DF 1 "register_operand" "0")
1351 (parallel [(const_int 0)]))
1352 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1355 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
1356 (parallel [(const_int 0)]))
1357 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
1359 "h<plusminus_mnemonic>pd\t{%2, %0|%0, %2}"
1360 [(set_attr "type" "sseadd")
1361 (set_attr "mode" "V2DF")])
1363 (define_expand "reduc_splus_v4sf"
1364 [(match_operand:V4SF 0 "register_operand" "")
1365 (match_operand:V4SF 1 "register_operand" "")]
1370 rtx tmp = gen_reg_rtx (V4SFmode);
1371 emit_insn (gen_sse3_haddv4sf3 (tmp, operands[1], operands[1]));
1372 emit_insn (gen_sse3_haddv4sf3 (operands[0], tmp, tmp));
1375 ix86_expand_reduc_v4sf (gen_addv4sf3, operands[0], operands[1]);
1379 (define_expand "reduc_splus_v2df"
1380 [(match_operand:V2DF 0 "register_operand" "")
1381 (match_operand:V2DF 1 "register_operand" "")]
1384 emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1]));
1388 (define_expand "reduc_smax_v4sf"
1389 [(match_operand:V4SF 0 "register_operand" "")
1390 (match_operand:V4SF 1 "register_operand" "")]
1393 ix86_expand_reduc_v4sf (gen_smaxv4sf3, operands[0], operands[1]);
1397 (define_expand "reduc_smin_v4sf"
1398 [(match_operand:V4SF 0 "register_operand" "")
1399 (match_operand:V4SF 1 "register_operand" "")]
1402 ix86_expand_reduc_v4sf (gen_sminv4sf3, operands[0], operands[1]);
1406 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1408 ;; Parallel floating point comparisons
1410 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1412 (define_insn "avx_cmpp<avxmodesuffixf2c><mode>3"
1413 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1415 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
1416 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
1417 (match_operand:SI 3 "const_0_to_31_operand" "n")]
1420 "vcmpp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1421 [(set_attr "type" "ssecmp")
1422 (set_attr "length_immediate" "1")
1423 (set_attr "prefix" "vex")
1424 (set_attr "mode" "<MODE>")])
1426 (define_insn "avx_cmps<ssemodesuffixf2c><mode>3"
1427 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
1428 (vec_merge:SSEMODEF2P
1430 [(match_operand:SSEMODEF2P 1 "register_operand" "x")
1431 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
1432 (match_operand:SI 3 "const_0_to_31_operand" "n")]
1437 "vcmps<ssemodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1438 [(set_attr "type" "ssecmp")
1439 (set_attr "length_immediate" "1")
1440 (set_attr "prefix" "vex")
1441 (set_attr "mode" "<ssescalarmode>")])
1443 ;; We don't promote 128bit vector compare intrinsics. But vectorizer
1444 ;; may generate 256bit vector compare instructions.
1445 (define_insn "*avx_maskcmp<mode>3"
1446 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1447 (match_operator:AVXMODEF2P 3 "avx_comparison_float_operator"
1448 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
1449 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]))]
1450 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1451 "vcmp%D3p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1452 [(set_attr "type" "ssecmp")
1453 (set_attr "prefix" "vex")
1454 (set_attr "length_immediate" "1")
1455 (set_attr "mode" "<avxvecmode>")])
1457 (define_insn "<sse>_maskcmp<mode>3"
1458 [(set (match_operand:SSEMODEF4 0 "register_operand" "=x")
1459 (match_operator:SSEMODEF4 3 "sse_comparison_operator"
1460 [(match_operand:SSEMODEF4 1 "register_operand" "0")
1461 (match_operand:SSEMODEF4 2 "nonimmediate_operand" "xm")]))]
1463 && (SSE_FLOAT_MODE_P (<MODE>mode) || SSE_VEC_FLOAT_MODE_P (<MODE>mode))"
1464 "cmp%D3<ssemodesuffixf4>\t{%2, %0|%0, %2}"
1465 [(set_attr "type" "ssecmp")
1466 (set_attr "length_immediate" "1")
1467 (set_attr "mode" "<MODE>")])
1469 (define_insn "<sse>_vmmaskcmp<mode>3"
1470 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1471 (vec_merge:SSEMODEF2P
1472 (match_operator:SSEMODEF2P 3 "sse_comparison_operator"
1473 [(match_operand:SSEMODEF2P 1 "register_operand" "0")
1474 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")])
1477 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1478 "cmp%D3s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1479 [(set_attr "type" "ssecmp")
1480 (set_attr "length_immediate" "1")
1481 (set_attr "mode" "<ssescalarmode>")])
1483 (define_insn "<sse>_comi"
1484 [(set (reg:CCFP FLAGS_REG)
1487 (match_operand:<ssevecmode> 0 "register_operand" "x")
1488 (parallel [(const_int 0)]))
1490 (match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm")
1491 (parallel [(const_int 0)]))))]
1492 "SSE_FLOAT_MODE_P (<MODE>mode)"
1493 "%vcomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
1494 [(set_attr "type" "ssecomi")
1495 (set_attr "prefix" "maybe_vex")
1496 (set_attr "prefix_rep" "0")
1497 (set (attr "prefix_data16")
1498 (if_then_else (eq_attr "mode" "DF")
1500 (const_string "0")))
1501 (set_attr "mode" "<MODE>")])
1503 (define_insn "<sse>_ucomi"
1504 [(set (reg:CCFPU FLAGS_REG)
1507 (match_operand:<ssevecmode> 0 "register_operand" "x")
1508 (parallel [(const_int 0)]))
1510 (match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm")
1511 (parallel [(const_int 0)]))))]
1512 "SSE_FLOAT_MODE_P (<MODE>mode)"
1513 "%vucomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
1514 [(set_attr "type" "ssecomi")
1515 (set_attr "prefix" "maybe_vex")
1516 (set_attr "prefix_rep" "0")
1517 (set (attr "prefix_data16")
1518 (if_then_else (eq_attr "mode" "DF")
1520 (const_string "0")))
1521 (set_attr "mode" "<MODE>")])
1523 (define_expand "vcond<mode>"
1524 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
1525 (if_then_else:SSEMODEF2P
1526 (match_operator 3 ""
1527 [(match_operand:SSEMODEF2P 4 "nonimmediate_operand" "")
1528 (match_operand:SSEMODEF2P 5 "nonimmediate_operand" "")])
1529 (match_operand:SSEMODEF2P 1 "general_operand" "")
1530 (match_operand:SSEMODEF2P 2 "general_operand" "")))]
1531 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1533 bool ok = ix86_expand_fp_vcond (operands);
1538 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1540 ;; Parallel floating point logical operations
1542 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1544 (define_insn "avx_andnot<mode>3"
1545 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1548 (match_operand:AVXMODEF2P 1 "register_operand" "x"))
1549 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1550 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1551 "vandnp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1552 [(set_attr "type" "sselog")
1553 (set_attr "prefix" "vex")
1554 (set_attr "mode" "<avxvecmode>")])
1556 (define_insn "<sse>_andnot<mode>3"
1557 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1560 (match_operand:SSEMODEF2P 1 "register_operand" "0"))
1561 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1562 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1563 "andnp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1564 [(set_attr "type" "sselog")
1565 (set_attr "mode" "<MODE>")])
1567 (define_expand "<code><mode>3"
1568 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
1569 (plogic:AVX256MODEF2P
1570 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
1571 (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
1572 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
1573 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
1575 (define_insn "*avx_<code><mode>3"
1576 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1578 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
1579 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1580 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
1581 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1582 "v<plogicprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1583 [(set_attr "type" "sselog")
1584 (set_attr "prefix" "vex")
1585 (set_attr "mode" "<avxvecmode>")])
1587 (define_expand "<code><mode>3"
1588 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
1590 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
1591 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
1592 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1593 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
1595 (define_insn "*<code><mode>3"
1596 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1598 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
1599 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1600 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
1601 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1602 "<plogicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1603 [(set_attr "type" "sselog")
1604 (set_attr "mode" "<MODE>")])
1606 (define_expand "copysign<mode>3"
1609 (not:SSEMODEF2P (match_dup 3))
1610 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")))
1612 (and:SSEMODEF2P (match_dup 3)
1613 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))
1614 (set (match_operand:SSEMODEF2P 0 "register_operand" "")
1615 (ior:SSEMODEF2P (match_dup 4) (match_dup 5)))]
1616 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1618 operands[3] = ix86_build_signbit_mask (<ssescalarmode>mode, 1, 0);
1620 operands[4] = gen_reg_rtx (<MODE>mode);
1621 operands[5] = gen_reg_rtx (<MODE>mode);
1624 ;; Also define scalar versions. These are used for abs, neg, and
1625 ;; conditional move. Using subregs into vector modes causes register
1626 ;; allocation lossage. These patterns do not allow memory operands
1627 ;; because the native instructions read the full 128-bits.
1629 (define_insn "*avx_andnot<mode>3"
1630 [(set (match_operand:MODEF 0 "register_operand" "=x")
1633 (match_operand:MODEF 1 "register_operand" "x"))
1634 (match_operand:MODEF 2 "register_operand" "x")))]
1635 "AVX_FLOAT_MODE_P (<MODE>mode)"
1636 "vandnp<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
1637 [(set_attr "type" "sselog")
1638 (set_attr "prefix" "vex")
1639 (set_attr "mode" "<ssevecmode>")])
1641 (define_insn "*andnot<mode>3"
1642 [(set (match_operand:MODEF 0 "register_operand" "=x")
1645 (match_operand:MODEF 1 "register_operand" "0"))
1646 (match_operand:MODEF 2 "register_operand" "x")))]
1647 "SSE_FLOAT_MODE_P (<MODE>mode)"
1648 "andnp<ssemodefsuffix>\t{%2, %0|%0, %2}"
1649 [(set_attr "type" "sselog")
1650 (set_attr "mode" "<ssevecmode>")])
1652 (define_insn "*avx_<code><mode>3"
1653 [(set (match_operand:MODEF 0 "register_operand" "=x")
1655 (match_operand:MODEF 1 "register_operand" "x")
1656 (match_operand:MODEF 2 "register_operand" "x")))]
1657 "AVX_FLOAT_MODE_P (<MODE>mode)"
1658 "v<plogicprefix>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
1659 [(set_attr "type" "sselog")
1660 (set_attr "prefix" "vex")
1661 (set_attr "mode" "<ssevecmode>")])
1663 (define_insn "*<code><mode>3"
1664 [(set (match_operand:MODEF 0 "register_operand" "=x")
1666 (match_operand:MODEF 1 "register_operand" "0")
1667 (match_operand:MODEF 2 "register_operand" "x")))]
1668 "SSE_FLOAT_MODE_P (<MODE>mode)"
1669 "<plogicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
1670 [(set_attr "type" "sselog")
1671 (set_attr "mode" "<ssevecmode>")])
1673 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1675 ;; FMA4 floating point multiply/accumulate instructions This includes the
1676 ;; scalar version of the instructions as well as the vector
1678 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1680 ;; In order to match (*a * *b) + *c, particularly when vectorizing, allow
1681 ;; combine to generate a multiply/add with two memory references. We then
1682 ;; split this insn, into loading up the destination register with one of the
1683 ;; memory operations. If we don't manage to split the insn, reload will
1684 ;; generate the appropriate moves. The reason this is needed, is that combine
1685 ;; has already folded one of the memory references into both the multiply and
1686 ;; add insns, and it can't generate a new pseudo. I.e.:
1687 ;; (set (reg1) (mem (addr1)))
1688 ;; (set (reg2) (mult (reg1) (mem (addr2))))
1689 ;; (set (reg3) (plus (reg2) (mem (addr3))))
1691 (define_insn "fma4_fmadd<mode>4256"
1692 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x,x,x")
1695 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "x,x,xm")
1696 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,xm,x"))
1697 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x,x")))]
1699 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
1700 "vfmadd<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1701 [(set_attr "type" "ssemuladd")
1702 (set_attr "mode" "<MODE>")])
1704 ;; Split fmadd with two memory operands into a load and the fmadd.
1706 [(set (match_operand:FMA4MODEF4 0 "register_operand" "")
1709 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "")
1710 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" ""))
1711 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "")))]
1713 && !ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)
1714 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)
1715 && !reg_mentioned_p (operands[0], operands[1])
1716 && !reg_mentioned_p (operands[0], operands[2])
1717 && !reg_mentioned_p (operands[0], operands[3])"
1720 ix86_expand_fma4_multiple_memory (operands, 4, <MODE>mode);
1721 emit_insn (gen_fma4_fmadd<mode>4256 (operands[0], operands[1],
1722 operands[2], operands[3]));
1726 ;; Floating multiply and subtract
1727 ;; Allow two memory operands the same as fmadd
1728 (define_insn "fma4_fmsub<mode>4256"
1729 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x,x,x")
1732 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "x,x,xm")
1733 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,xm,x"))
1734 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x,x")))]
1736 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
1737 "vfmsub<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1738 [(set_attr "type" "ssemuladd")
1739 (set_attr "mode" "<MODE>")])
1741 ;; Split fmsub with two memory operands into a load and the fmsub.
1743 [(set (match_operand:FMA4MODEF4 0 "register_operand" "")
1746 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "")
1747 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" ""))
1748 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "")))]
1750 && !ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)
1751 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)
1752 && !reg_mentioned_p (operands[0], operands[1])
1753 && !reg_mentioned_p (operands[0], operands[2])
1754 && !reg_mentioned_p (operands[0], operands[3])"
1757 ix86_expand_fma4_multiple_memory (operands, 4, <MODE>mode);
1758 emit_insn (gen_fma4_fmsub<mode>4256 (operands[0], operands[1],
1759 operands[2], operands[3]));
1763 ;; Floating point negative multiply and add
1764 ;; Rewrite (- (a * b) + c) into the canonical form: c - (a * b)
1765 ;; Note operands are out of order to simplify call to ix86_fma4_valid_p
1766 ;; Allow two memory operands to help in optimizing.
1767 (define_insn "fma4_fnmadd<mode>4256"
1768 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x,x,x")
1770 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x,x")
1772 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "x,x,xm")
1773 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,xm,x"))))]
1775 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
1776 "vfnmadd<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1777 [(set_attr "type" "ssemuladd")
1778 (set_attr "mode" "<MODE>")])
1780 ;; Split fnmadd with two memory operands into a load and the fnmadd.
1782 [(set (match_operand:FMA4MODEF4 0 "register_operand" "")
1784 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "")
1786 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "")
1787 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" ""))))]
1789 && !ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)
1790 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)
1791 && !reg_mentioned_p (operands[0], operands[1])
1792 && !reg_mentioned_p (operands[0], operands[2])
1793 && !reg_mentioned_p (operands[0], operands[3])"
1796 ix86_expand_fma4_multiple_memory (operands, 4, <MODE>mode);
1797 emit_insn (gen_fma4_fnmadd<mode>4256 (operands[0], operands[1],
1798 operands[2], operands[3]));
1802 ;; Floating point negative multiply and subtract
1803 ;; Rewrite (- (a * b) - c) into the canonical form: ((-a) * b) - c
1804 ;; Allow 2 memory operands to help with optimization
1805 (define_insn "fma4_fnmsub<mode>4256"
1806 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x,x")
1810 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "x,x"))
1811 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,xm"))
1812 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x")))]
1814 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, false)"
1815 "vfnmsub<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1816 [(set_attr "type" "ssemuladd")
1817 (set_attr "mode" "<MODE>")])
1819 ;; Split fnmsub with two memory operands into a load and the fmsub.
1821 [(set (match_operand:FMA4MODEF4 0 "register_operand" "")
1825 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" ""))
1826 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" ""))
1827 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "")))]
1829 && !ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)
1830 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, false)
1831 && !reg_mentioned_p (operands[0], operands[1])
1832 && !reg_mentioned_p (operands[0], operands[2])
1833 && !reg_mentioned_p (operands[0], operands[3])"
1836 ix86_expand_fma4_multiple_memory (operands, 4, <MODE>mode);
1837 emit_insn (gen_fma4_fnmsub<mode>4256 (operands[0], operands[1],
1838 operands[2], operands[3]));
1842 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1843 (define_insn "fma4_fmadd<mode>4"
1844 [(set (match_operand:SSEMODEF4 0 "register_operand" "=x,x,x")
1847 (match_operand:SSEMODEF4 1 "nonimmediate_operand" "x,x,xm")
1848 (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,xm,x"))
1849 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x,x")))]
1851 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
1852 "vfmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1853 [(set_attr "type" "ssemuladd")
1854 (set_attr "mode" "<MODE>")])
1856 ;; Split fmadd with two memory operands into a load and the fmadd.
1858 [(set (match_operand:SSEMODEF4 0 "register_operand" "")
1861 (match_operand:SSEMODEF4 1 "nonimmediate_operand" "")
1862 (match_operand:SSEMODEF4 2 "nonimmediate_operand" ""))
1863 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "")))]
1865 && !ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)
1866 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)
1867 && !reg_mentioned_p (operands[0], operands[1])
1868 && !reg_mentioned_p (operands[0], operands[2])
1869 && !reg_mentioned_p (operands[0], operands[3])"
1872 ix86_expand_fma4_multiple_memory (operands, 4, <MODE>mode);
1873 emit_insn (gen_fma4_fmadd<mode>4 (operands[0], operands[1],
1874 operands[2], operands[3]));
1878 ;; For the scalar operations, use operand1 for the upper words that aren't
1879 ;; modified, so restrict the forms that are generated.
1880 ;; Scalar version of fmadd
1881 (define_insn "fma4_vmfmadd<mode>4"
1882 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
1883 (vec_merge:SSEMODEF2P
1886 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x")
1887 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
1888 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
1892 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
1893 "vfmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1894 [(set_attr "type" "ssemuladd")
1895 (set_attr "mode" "<MODE>")])
1897 ;; Floating multiply and subtract
1898 ;; Allow two memory operands the same as fmadd
1899 (define_insn "fma4_fmsub<mode>4"
1900 [(set (match_operand:SSEMODEF4 0 "register_operand" "=x,x,x")
1903 (match_operand:SSEMODEF4 1 "nonimmediate_operand" "x,x,xm")
1904 (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,xm,x"))
1905 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x,x")))]
1907 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
1908 "vfmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1909 [(set_attr "type" "ssemuladd")
1910 (set_attr "mode" "<MODE>")])
1912 ;; Split fmsub with two memory operands into a load and the fmsub.
1914 [(set (match_operand:SSEMODEF4 0 "register_operand" "")
1917 (match_operand:SSEMODEF4 1 "nonimmediate_operand" "")
1918 (match_operand:SSEMODEF4 2 "nonimmediate_operand" ""))
1919 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "")))]
1921 && !ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)
1922 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)
1923 && !reg_mentioned_p (operands[0], operands[1])
1924 && !reg_mentioned_p (operands[0], operands[2])
1925 && !reg_mentioned_p (operands[0], operands[3])"
1928 ix86_expand_fma4_multiple_memory (operands, 4, <MODE>mode);
1929 emit_insn (gen_fma4_fmsub<mode>4 (operands[0], operands[1],
1930 operands[2], operands[3]));
1934 ;; For the scalar operations, use operand1 for the upper words that aren't
1935 ;; modified, so restrict the forms that are generated.
1936 ;; Scalar version of fmsub
1937 (define_insn "fma4_vmfmsub<mode>4"
1938 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
1939 (vec_merge:SSEMODEF2P
1942 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x")
1943 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
1944 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
1948 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
1949 "vfmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1950 [(set_attr "type" "ssemuladd")
1951 (set_attr "mode" "<MODE>")])
1953 ;; Floating point negative multiply and add
1954 ;; Rewrite (- (a * b) + c) into the canonical form: c - (a * b)
1955 ;; Note operands are out of order to simplify call to ix86_fma4_valid_p
1956 ;; Allow two memory operands to help in optimizing.
1957 (define_insn "fma4_fnmadd<mode>4"
1958 [(set (match_operand:SSEMODEF4 0 "register_operand" "=x,x,x")
1960 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x,x")
1962 (match_operand:SSEMODEF4 1 "nonimmediate_operand" "x,x,xm")
1963 (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,xm,x"))))]
1965 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
1966 "vfnmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1967 [(set_attr "type" "ssemuladd")
1968 (set_attr "mode" "<MODE>")])
1970 ;; Split fnmadd with two memory operands into a load and the fnmadd.
1972 [(set (match_operand:SSEMODEF4 0 "register_operand" "")
1974 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "")
1976 (match_operand:SSEMODEF4 1 "nonimmediate_operand" "")
1977 (match_operand:SSEMODEF4 2 "nonimmediate_operand" ""))))]
1979 && !ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)
1980 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)
1981 && !reg_mentioned_p (operands[0], operands[1])
1982 && !reg_mentioned_p (operands[0], operands[2])
1983 && !reg_mentioned_p (operands[0], operands[3])"
1986 ix86_expand_fma4_multiple_memory (operands, 4, <MODE>mode);
1987 emit_insn (gen_fma4_fnmadd<mode>4 (operands[0], operands[1],
1988 operands[2], operands[3]));
1992 ;; For the scalar operations, use operand1 for the upper words that aren't
1993 ;; modified, so restrict the forms that are generated.
1994 ;; Scalar version of fnmadd
1995 (define_insn "fma4_vmfnmadd<mode>4"
1996 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
1997 (vec_merge:SSEMODEF2P
1999 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")
2001 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x")
2002 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm")))
2006 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
2007 "vfnmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2008 [(set_attr "type" "ssemuladd")
2009 (set_attr "mode" "<MODE>")])
2011 ;; Floating point negative multiply and subtract
2012 ;; Rewrite (- (a * b) - c) into the canonical form: ((-a) * b) - c
2013 ;; Allow 2 memory operands to help with optimization
2014 (define_insn "fma4_fnmsub<mode>4"
2015 [(set (match_operand:SSEMODEF4 0 "register_operand" "=x,x")
2019 (match_operand:SSEMODEF4 1 "nonimmediate_operand" "x,x"))
2020 (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,xm"))
2021 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x")))]
2023 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, false)"
2024 "vfnmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2025 [(set_attr "type" "ssemuladd")
2026 (set_attr "mode" "<MODE>")])
2028 ;; Split fnmsub with two memory operands into a load and the fmsub.
2030 [(set (match_operand:SSEMODEF4 0 "register_operand" "")
2034 (match_operand:SSEMODEF4 1 "nonimmediate_operand" ""))
2035 (match_operand:SSEMODEF4 2 "nonimmediate_operand" ""))
2036 (match_operand:SSEMODEF4 3 "nonimmediate_operand" "")))]
2038 && !ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)
2039 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, false)
2040 && !reg_mentioned_p (operands[0], operands[1])
2041 && !reg_mentioned_p (operands[0], operands[2])
2042 && !reg_mentioned_p (operands[0], operands[3])"
2045 ix86_expand_fma4_multiple_memory (operands, 4, <MODE>mode);
2046 emit_insn (gen_fma4_fnmsub<mode>4 (operands[0], operands[1],
2047 operands[2], operands[3]));
2051 ;; For the scalar operations, use operand1 for the upper words that aren't
2052 ;; modified, so restrict the forms that are generated.
2053 ;; Scalar version of fnmsub
2054 (define_insn "fma4_vmfnmsub<mode>4"
2055 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2056 (vec_merge:SSEMODEF2P
2060 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x"))
2061 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
2062 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
2066 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, false)"
2067 "vfnmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2068 [(set_attr "type" "ssemuladd")
2069 (set_attr "mode" "<MODE>")])
2071 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2073 (define_insn "fma4i_fmadd<mode>4256"
2074 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x,x")
2078 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "x,x")
2079 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,xm"))
2080 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x"))]
2081 UNSPEC_FMA4_INTRINSIC))]
2082 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
2083 "vfmadd<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2084 [(set_attr "type" "ssemuladd")
2085 (set_attr "mode" "<MODE>")])
2087 (define_insn "fma4i_fmsub<mode>4256"
2088 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x,x")
2092 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "x,x")
2093 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,xm"))
2094 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x"))]
2095 UNSPEC_FMA4_INTRINSIC))]
2096 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
2097 "vfmsub<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2098 [(set_attr "type" "ssemuladd")
2099 (set_attr "mode" "<MODE>")])
2101 (define_insn "fma4i_fnmadd<mode>4256"
2102 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x,x")
2105 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x")
2107 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "x,x")
2108 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,xm")))]
2109 UNSPEC_FMA4_INTRINSIC))]
2110 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
2111 "vfnmadd<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2112 [(set_attr "type" "ssemuladd")
2113 (set_attr "mode" "<MODE>")])
2115 (define_insn "fma4i_fnmsub<mode>4256"
2116 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x,x")
2121 (match_operand:FMA4MODEF4 1 "nonimmediate_operand" "x,x"))
2122 (match_operand:FMA4MODEF4 2 "nonimmediate_operand" "x,xm"))
2123 (match_operand:FMA4MODEF4 3 "nonimmediate_operand" "xm,x"))]
2124 UNSPEC_FMA4_INTRINSIC))]
2125 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
2126 "vfnmsub<fma4modesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2127 [(set_attr "type" "ssemuladd")
2128 (set_attr "mode" "<MODE>")])
2129 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2131 (define_insn "fma4i_fmadd<mode>4"
2132 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2136 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x")
2137 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
2138 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))]
2139 UNSPEC_FMA4_INTRINSIC))]
2140 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
2141 "vfmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2142 [(set_attr "type" "ssemuladd")
2143 (set_attr "mode" "<MODE>")])
2145 (define_insn "fma4i_fmsub<mode>4"
2146 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2150 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x")
2151 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
2152 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))]
2153 UNSPEC_FMA4_INTRINSIC))]
2154 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
2155 "vfmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2156 [(set_attr "type" "ssemuladd")
2157 (set_attr "mode" "<MODE>")])
2159 (define_insn "fma4i_fnmadd<mode>4"
2160 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2163 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")
2165 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x")
2166 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm")))]
2167 UNSPEC_FMA4_INTRINSIC))]
2168 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
2169 "vfnmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2170 [(set_attr "type" "ssemuladd")
2171 (set_attr "mode" "<MODE>")])
2173 (define_insn "fma4i_fnmsub<mode>4"
2174 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2179 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x"))
2180 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
2181 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))]
2182 UNSPEC_FMA4_INTRINSIC))]
2183 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
2184 "vfnmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2185 [(set_attr "type" "ssemuladd")
2186 (set_attr "mode" "<MODE>")])
2188 ;; For the scalar operations, use operand1 for the upper words that aren't
2189 ;; modified, so restrict the forms that are accepted.
2190 (define_insn "fma4i_vmfmadd<mode>4"
2191 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2193 [(vec_merge:SSEMODEF2P
2196 (match_operand:SSEMODEF2P 1 "register_operand" "x,x")
2197 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
2198 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
2201 UNSPEC_FMA4_INTRINSIC))]
2202 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
2203 "vfmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2204 [(set_attr "type" "ssemuladd")
2205 (set_attr "mode" "<ssescalarmode>")])
2207 (define_insn "fma4i_vmfmsub<mode>4"
2208 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2210 [(vec_merge:SSEMODEF2P
2213 (match_operand:SSEMODEF2P 1 "register_operand" "x,x")
2214 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
2215 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
2218 UNSPEC_FMA4_INTRINSIC))]
2219 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
2220 "vfmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2221 [(set_attr "type" "ssemuladd")
2222 (set_attr "mode" "<ssescalarmode>")])
2224 (define_insn "fma4i_vmfnmadd<mode>4"
2225 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2227 [(vec_merge:SSEMODEF2P
2229 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")
2231 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "x,x")
2232 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm")))
2235 UNSPEC_FMA4_INTRINSIC))]
2236 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, true)"
2237 "vfnmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2238 [(set_attr "type" "ssemuladd")
2239 (set_attr "mode" "<ssescalarmode>")])
2241 (define_insn "fma4i_vmfnmsub<mode>4"
2242 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
2244 [(vec_merge:SSEMODEF2P
2248 (match_operand:SSEMODEF2P 1 "register_operand" "x,x"))
2249 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
2250 (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
2253 UNSPEC_FMA4_INTRINSIC))]
2254 "TARGET_FMA4 && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
2255 "vfnmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2256 [(set_attr "type" "ssemuladd")
2257 (set_attr "mode" "<ssescalarmode>")])
2259 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2261 ;; FMA4 Parallel floating point multiply addsub and subadd operations
2263 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2265 (define_insn "fma4_fmaddsubv8sf4"
2266 [(set (match_operand:V8SF 0 "register_operand" "=x,x")
2270 (match_operand:V8SF 1 "nonimmediate_operand" "x,x")
2271 (match_operand:V8SF 2 "nonimmediate_operand" "x,xm"))
2272 (match_operand:V8SF 3 "nonimmediate_operand" "xm,x"))
2280 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2281 "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2282 [(set_attr "type" "ssemuladd")
2283 (set_attr "mode" "V8SF")])
2285 (define_insn "fma4_fmaddsubv4df4"
2286 [(set (match_operand:V4DF 0 "register_operand" "=x,x")
2290 (match_operand:V4DF 1 "nonimmediate_operand" "x,x")
2291 (match_operand:V4DF 2 "nonimmediate_operand" "x,xm"))
2292 (match_operand:V4DF 3 "nonimmediate_operand" "xm,x"))
2300 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2301 "vfmaddsubpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2302 [(set_attr "type" "ssemuladd")
2303 (set_attr "mode" "V4DF")])
2305 (define_insn "fma4_fmaddsubv4sf4"
2306 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
2310 (match_operand:V4SF 1 "nonimmediate_operand" "x,x")
2311 (match_operand:V4SF 2 "nonimmediate_operand" "x,xm"))
2312 (match_operand:V4SF 3 "nonimmediate_operand" "xm,x"))
2320 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2321 "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2322 [(set_attr "type" "ssemuladd")
2323 (set_attr "mode" "V4SF")])
2325 (define_insn "fma4_fmaddsubv2df4"
2326 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2330 (match_operand:V2DF 1 "nonimmediate_operand" "x,x")
2331 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm"))
2332 (match_operand:V2DF 3 "nonimmediate_operand" "xm,x"))
2340 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2341 "vfmaddsubpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2342 [(set_attr "type" "ssemuladd")
2343 (set_attr "mode" "V2DF")])
2345 (define_insn "fma4_fmsubaddv8sf4"
2346 [(set (match_operand:V8SF 0 "register_operand" "=x,x")
2350 (match_operand:V8SF 1 "nonimmediate_operand" "x,x")
2351 (match_operand:V8SF 2 "nonimmediate_operand" "x,xm"))
2352 (match_operand:V8SF 3 "nonimmediate_operand" "xm,x"))
2360 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2361 "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2362 [(set_attr "type" "ssemuladd")
2363 (set_attr "mode" "V8SF")])
2365 (define_insn "fma4_fmsubaddv4df4"
2366 [(set (match_operand:V4DF 0 "register_operand" "=x,x")
2370 (match_operand:V4DF 1 "nonimmediate_operand" "x,x")
2371 (match_operand:V4DF 2 "nonimmediate_operand" "x,xm"))
2372 (match_operand:V4DF 3 "nonimmediate_operand" "xm,x"))
2380 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2381 "vfmsubaddpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2382 [(set_attr "type" "ssemuladd")
2383 (set_attr "mode" "V4DF")])
2385 (define_insn "fma4_fmsubaddv4sf4"
2386 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
2390 (match_operand:V4SF 1 "nonimmediate_operand" "x,x")
2391 (match_operand:V4SF 2 "nonimmediate_operand" "x,xm"))
2392 (match_operand:V4SF 3 "nonimmediate_operand" "xm,x"))
2400 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2401 "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2402 [(set_attr "type" "ssemuladd")
2403 (set_attr "mode" "V4SF")])
2405 (define_insn "fma4_fmsubaddv2df4"
2406 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2410 (match_operand:V2DF 1 "nonimmediate_operand" "x,x")
2411 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm"))
2412 (match_operand:V2DF 3 "nonimmediate_operand" "xm,x"))
2420 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2421 "vfmsubaddpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2422 [(set_attr "type" "ssemuladd")
2423 (set_attr "mode" "V2DF")])
2425 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2427 (define_insn "fma4i_fmaddsubv8sf4"
2428 [(set (match_operand:V8SF 0 "register_operand" "=x,x")
2433 (match_operand:V8SF 1 "nonimmediate_operand" "x,x")
2434 (match_operand:V8SF 2 "nonimmediate_operand" "x,xm"))
2435 (match_operand:V8SF 3 "nonimmediate_operand" "xm,x"))
2442 UNSPEC_FMA4_INTRINSIC))]
2444 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2445 "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2446 [(set_attr "type" "ssemuladd")
2447 (set_attr "mode" "V8SF")])
2449 (define_insn "fma4i_fmaddsubv4df4"
2450 [(set (match_operand:V4DF 0 "register_operand" "=x,x")
2455 (match_operand:V4DF 1 "nonimmediate_operand" "x,x")
2456 (match_operand:V4DF 2 "nonimmediate_operand" "x,xm"))
2457 (match_operand:V4DF 3 "nonimmediate_operand" "xm,x"))
2464 UNSPEC_FMA4_INTRINSIC))]
2466 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2467 "vfmaddsubpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2468 [(set_attr "type" "ssemuladd")
2469 (set_attr "mode" "V4DF")])
2471 (define_insn "fma4i_fmaddsubv4sf4"
2472 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
2477 (match_operand:V4SF 1 "nonimmediate_operand" "x,x")
2478 (match_operand:V4SF 2 "nonimmediate_operand" "x,xm"))
2479 (match_operand:V4SF 3 "nonimmediate_operand" "xm,x"))
2486 UNSPEC_FMA4_INTRINSIC))]
2488 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2489 "vfmaddsubps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2490 [(set_attr "type" "ssemuladd")
2491 (set_attr "mode" "V4SF")])
2493 (define_insn "fma4i_fmaddsubv2df4"
2494 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2499 (match_operand:V2DF 1 "nonimmediate_operand" "x,x")
2500 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm"))
2501 (match_operand:V2DF 3 "nonimmediate_operand" "xm,x"))
2508 UNSPEC_FMA4_INTRINSIC))]
2510 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2511 "vfmaddsubpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2512 [(set_attr "type" "ssemuladd")
2513 (set_attr "mode" "V2DF")])
2515 (define_insn "fma4i_fmsubaddv8sf4"
2516 [(set (match_operand:V8SF 0 "register_operand" "=x,x")
2521 (match_operand:V8SF 1 "nonimmediate_operand" "x,x")
2522 (match_operand:V8SF 2 "nonimmediate_operand" "x,xm"))
2523 (match_operand:V8SF 3 "nonimmediate_operand" "xm,x"))
2530 UNSPEC_FMA4_INTRINSIC))]
2532 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2533 "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2534 [(set_attr "type" "ssemuladd")
2535 (set_attr "mode" "V8SF")])
2537 (define_insn "fma4i_fmsubaddv4df4"
2538 [(set (match_operand:V4DF 0 "register_operand" "=x,x")
2543 (match_operand:V4DF 1 "nonimmediate_operand" "x,x")
2544 (match_operand:V4DF 2 "nonimmediate_operand" "x,xm"))
2545 (match_operand:V4DF 3 "nonimmediate_operand" "xm,x"))
2552 UNSPEC_FMA4_INTRINSIC))]
2554 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2555 "vfmsubaddpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2556 [(set_attr "type" "ssemuladd")
2557 (set_attr "mode" "V4DF")])
2559 (define_insn "fma4i_fmsubaddv4sf4"
2560 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
2565 (match_operand:V4SF 1 "nonimmediate_operand" "x,x")
2566 (match_operand:V4SF 2 "nonimmediate_operand" "x,xm"))
2567 (match_operand:V4SF 3 "nonimmediate_operand" "xm,x"))
2574 UNSPEC_FMA4_INTRINSIC))]
2576 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2577 "vfmsubaddps\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2578 [(set_attr "type" "ssemuladd")
2579 (set_attr "mode" "V4SF")])
2581 (define_insn "fma4i_fmsubaddv2df4"
2582 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2587 (match_operand:V2DF 1 "nonimmediate_operand" "x,x")
2588 (match_operand:V2DF 2 "nonimmediate_operand" "x,xm"))
2589 (match_operand:V2DF 3 "nonimmediate_operand" "xm,x"))
2596 UNSPEC_FMA4_INTRINSIC))]
2598 && ix86_fma4_valid_op_p (operands, insn, 4, true, 2, true)"
2599 "vfmsubaddpd\t{%3, %2, %1, %0|%0, %1, %2, %3}"
2600 [(set_attr "type" "ssemuladd")
2601 (set_attr "mode" "V2DF")])
2603 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2605 ;; Parallel single-precision floating point conversion operations
2607 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2609 (define_insn "sse_cvtpi2ps"
2610 [(set (match_operand:V4SF 0 "register_operand" "=x")
2613 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
2614 (match_operand:V4SF 1 "register_operand" "0")
2617 "cvtpi2ps\t{%2, %0|%0, %2}"
2618 [(set_attr "type" "ssecvt")
2619 (set_attr "mode" "V4SF")])
2621 (define_insn "sse_cvtps2pi"
2622 [(set (match_operand:V2SI 0 "register_operand" "=y")
2624 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
2626 (parallel [(const_int 0) (const_int 1)])))]
2628 "cvtps2pi\t{%1, %0|%0, %1}"
2629 [(set_attr "type" "ssecvt")
2630 (set_attr "unit" "mmx")
2631 (set_attr "mode" "DI")])
2633 (define_insn "sse_cvttps2pi"
2634 [(set (match_operand:V2SI 0 "register_operand" "=y")
2636 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
2637 (parallel [(const_int 0) (const_int 1)])))]
2639 "cvttps2pi\t{%1, %0|%0, %1}"
2640 [(set_attr "type" "ssecvt")
2641 (set_attr "unit" "mmx")
2642 (set_attr "prefix_rep" "0")
2643 (set_attr "mode" "SF")])
2645 (define_insn "*avx_cvtsi2ss"
2646 [(set (match_operand:V4SF 0 "register_operand" "=x")
2649 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm")))
2650 (match_operand:V4SF 1 "register_operand" "x")
2653 "vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}"
2654 [(set_attr "type" "sseicvt")
2655 (set_attr "prefix" "vex")
2656 (set_attr "mode" "SF")])
2658 (define_insn "sse_cvtsi2ss"
2659 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
2662 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
2663 (match_operand:V4SF 1 "register_operand" "0,0")
2666 "cvtsi2ss\t{%2, %0|%0, %2}"
2667 [(set_attr "type" "sseicvt")
2668 (set_attr "athlon_decode" "vector,double")
2669 (set_attr "amdfam10_decode" "vector,double")
2670 (set_attr "mode" "SF")])
2672 (define_insn "*avx_cvtsi2ssq"
2673 [(set (match_operand:V4SF 0 "register_operand" "=x")
2676 (float:SF (match_operand:DI 2 "nonimmediate_operand" "rm")))
2677 (match_operand:V4SF 1 "register_operand" "x")
2679 "TARGET_AVX && TARGET_64BIT"
2680 "vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
2681 [(set_attr "type" "sseicvt")
2682 (set_attr "length_vex" "4")
2683 (set_attr "prefix" "vex")
2684 (set_attr "mode" "SF")])
2686 (define_insn "sse_cvtsi2ssq"
2687 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
2690 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
2691 (match_operand:V4SF 1 "register_operand" "0,0")
2693 "TARGET_SSE && TARGET_64BIT"
2694 "cvtsi2ssq\t{%2, %0|%0, %2}"
2695 [(set_attr "type" "sseicvt")
2696 (set_attr "prefix_rex" "1")
2697 (set_attr "athlon_decode" "vector,double")
2698 (set_attr "amdfam10_decode" "vector,double")
2699 (set_attr "mode" "SF")])
2701 (define_insn "sse_cvtss2si"
2702 [(set (match_operand:SI 0 "register_operand" "=r,r")
2705 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2706 (parallel [(const_int 0)]))]
2707 UNSPEC_FIX_NOTRUNC))]
2709 "%vcvtss2si\t{%1, %0|%0, %1}"
2710 [(set_attr "type" "sseicvt")
2711 (set_attr "athlon_decode" "double,vector")
2712 (set_attr "prefix_rep" "1")
2713 (set_attr "prefix" "maybe_vex")
2714 (set_attr "mode" "SI")])
2716 (define_insn "sse_cvtss2si_2"
2717 [(set (match_operand:SI 0 "register_operand" "=r,r")
2718 (unspec:SI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
2719 UNSPEC_FIX_NOTRUNC))]
2721 "%vcvtss2si\t{%1, %0|%0, %1}"
2722 [(set_attr "type" "sseicvt")
2723 (set_attr "athlon_decode" "double,vector")
2724 (set_attr "amdfam10_decode" "double,double")
2725 (set_attr "prefix_rep" "1")
2726 (set_attr "prefix" "maybe_vex")
2727 (set_attr "mode" "SI")])
2729 (define_insn "sse_cvtss2siq"
2730 [(set (match_operand:DI 0 "register_operand" "=r,r")
2733 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2734 (parallel [(const_int 0)]))]
2735 UNSPEC_FIX_NOTRUNC))]
2736 "TARGET_SSE && TARGET_64BIT"
2737 "%vcvtss2si{q}\t{%1, %0|%0, %1}"
2738 [(set_attr "type" "sseicvt")
2739 (set_attr "athlon_decode" "double,vector")
2740 (set_attr "prefix_rep" "1")
2741 (set_attr "prefix" "maybe_vex")
2742 (set_attr "mode" "DI")])
2744 (define_insn "sse_cvtss2siq_2"
2745 [(set (match_operand:DI 0 "register_operand" "=r,r")
2746 (unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
2747 UNSPEC_FIX_NOTRUNC))]
2748 "TARGET_SSE && TARGET_64BIT"
2749 "%vcvtss2si{q}\t{%1, %0|%0, %1}"
2750 [(set_attr "type" "sseicvt")
2751 (set_attr "athlon_decode" "double,vector")
2752 (set_attr "amdfam10_decode" "double,double")
2753 (set_attr "prefix_rep" "1")
2754 (set_attr "prefix" "maybe_vex")
2755 (set_attr "mode" "DI")])
2757 (define_insn "sse_cvttss2si"
2758 [(set (match_operand:SI 0 "register_operand" "=r,r")
2761 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2762 (parallel [(const_int 0)]))))]
2764 "%vcvttss2si\t{%1, %0|%0, %1}"
2765 [(set_attr "type" "sseicvt")
2766 (set_attr "athlon_decode" "double,vector")
2767 (set_attr "amdfam10_decode" "double,double")
2768 (set_attr "prefix_rep" "1")
2769 (set_attr "prefix" "maybe_vex")
2770 (set_attr "mode" "SI")])
2772 (define_insn "sse_cvttss2siq"
2773 [(set (match_operand:DI 0 "register_operand" "=r,r")
2776 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
2777 (parallel [(const_int 0)]))))]
2778 "TARGET_SSE && TARGET_64BIT"
2779 "%vcvttss2si{q}\t{%1, %0|%0, %1}"
2780 [(set_attr "type" "sseicvt")
2781 (set_attr "athlon_decode" "double,vector")
2782 (set_attr "amdfam10_decode" "double,double")
2783 (set_attr "prefix_rep" "1")
2784 (set_attr "prefix" "maybe_vex")
2785 (set_attr "mode" "DI")])
2787 (define_insn "avx_cvtdq2ps<avxmodesuffix>"
2788 [(set (match_operand:AVXMODEDCVTDQ2PS 0 "register_operand" "=x")
2789 (float:AVXMODEDCVTDQ2PS
2790 (match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")))]
2792 "vcvtdq2ps\t{%1, %0|%0, %1}"
2793 [(set_attr "type" "ssecvt")
2794 (set_attr "prefix" "vex")
2795 (set_attr "mode" "<avxvecmode>")])
2797 (define_insn "sse2_cvtdq2ps"
2798 [(set (match_operand:V4SF 0 "register_operand" "=x")
2799 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
2801 "cvtdq2ps\t{%1, %0|%0, %1}"
2802 [(set_attr "type" "ssecvt")
2803 (set_attr "mode" "V4SF")])
2805 (define_expand "sse2_cvtudq2ps"
2807 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "")))
2809 (lt:V4SF (match_dup 5) (match_dup 3)))
2811 (and:V4SF (match_dup 6) (match_dup 4)))
2812 (set (match_operand:V4SF 0 "register_operand" "")
2813 (plus:V4SF (match_dup 5) (match_dup 7)))]
2816 REAL_VALUE_TYPE TWO32r;
2820 real_ldexp (&TWO32r, &dconst1, 32);
2821 x = const_double_from_real_value (TWO32r, SFmode);
2823 operands[3] = force_reg (V4SFmode, CONST0_RTX (V4SFmode));
2824 operands[4] = force_reg (V4SFmode, ix86_build_const_vector (SFmode, 1, x));
2826 for (i = 5; i < 8; i++)
2827 operands[i] = gen_reg_rtx (V4SFmode);
2830 (define_insn "avx_cvtps2dq<avxmodesuffix>"
2831 [(set (match_operand:AVXMODEDCVTPS2DQ 0 "register_operand" "=x")
2832 (unspec:AVXMODEDCVTPS2DQ
2833 [(match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")]
2834 UNSPEC_FIX_NOTRUNC))]
2836 "vcvtps2dq\t{%1, %0|%0, %1}"
2837 [(set_attr "type" "ssecvt")
2838 (set_attr "prefix" "vex")
2839 (set_attr "mode" "<avxvecmode>")])
2841 (define_insn "sse2_cvtps2dq"
2842 [(set (match_operand:V4SI 0 "register_operand" "=x")
2843 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
2844 UNSPEC_FIX_NOTRUNC))]
2846 "cvtps2dq\t{%1, %0|%0, %1}"
2847 [(set_attr "type" "ssecvt")
2848 (set_attr "prefix_data16" "1")
2849 (set_attr "mode" "TI")])
2851 (define_insn "avx_cvttps2dq<avxmodesuffix>"
2852 [(set (match_operand:AVXMODEDCVTPS2DQ 0 "register_operand" "=x")
2853 (fix:AVXMODEDCVTPS2DQ
2854 (match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")))]
2856 "vcvttps2dq\t{%1, %0|%0, %1}"
2857 [(set_attr "type" "ssecvt")
2858 (set_attr "prefix" "vex")
2859 (set_attr "mode" "<avxvecmode>")])
2861 (define_insn "sse2_cvttps2dq"
2862 [(set (match_operand:V4SI 0 "register_operand" "=x")
2863 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
2865 "cvttps2dq\t{%1, %0|%0, %1}"
2866 [(set_attr "type" "ssecvt")
2867 (set_attr "prefix_rep" "1")
2868 (set_attr "prefix_data16" "0")
2869 (set_attr "mode" "TI")])
2871 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2873 ;; Parallel double-precision floating point conversion operations
2875 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2877 (define_insn "sse2_cvtpi2pd"
2878 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2879 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "y,m")))]
2881 "cvtpi2pd\t{%1, %0|%0, %1}"
2882 [(set_attr "type" "ssecvt")
2883 (set_attr "unit" "mmx,*")
2884 (set_attr "prefix_data16" "1,*")
2885 (set_attr "mode" "V2DF")])
2887 (define_insn "sse2_cvtpd2pi"
2888 [(set (match_operand:V2SI 0 "register_operand" "=y")
2889 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
2890 UNSPEC_FIX_NOTRUNC))]
2892 "cvtpd2pi\t{%1, %0|%0, %1}"
2893 [(set_attr "type" "ssecvt")
2894 (set_attr "unit" "mmx")
2895 (set_attr "prefix_data16" "1")
2896 (set_attr "mode" "DI")])
2898 (define_insn "sse2_cvttpd2pi"
2899 [(set (match_operand:V2SI 0 "register_operand" "=y")
2900 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
2902 "cvttpd2pi\t{%1, %0|%0, %1}"
2903 [(set_attr "type" "ssecvt")
2904 (set_attr "unit" "mmx")
2905 (set_attr "prefix_data16" "1")
2906 (set_attr "mode" "TI")])
2908 (define_insn "*avx_cvtsi2sd"
2909 [(set (match_operand:V2DF 0 "register_operand" "=x")
2912 (float:DF (match_operand:SI 2 "nonimmediate_operand" "rm")))
2913 (match_operand:V2DF 1 "register_operand" "x")
2916 "vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}"
2917 [(set_attr "type" "sseicvt")
2918 (set_attr "prefix" "vex")
2919 (set_attr "mode" "DF")])
2921 (define_insn "sse2_cvtsi2sd"
2922 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2925 (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
2926 (match_operand:V2DF 1 "register_operand" "0,0")
2929 "cvtsi2sd\t{%2, %0|%0, %2}"
2930 [(set_attr "type" "sseicvt")
2931 (set_attr "mode" "DF")
2932 (set_attr "athlon_decode" "double,direct")
2933 (set_attr "amdfam10_decode" "vector,double")])
2935 (define_insn "*avx_cvtsi2sdq"
2936 [(set (match_operand:V2DF 0 "register_operand" "=x")
2939 (float:DF (match_operand:DI 2 "nonimmediate_operand" "rm")))
2940 (match_operand:V2DF 1 "register_operand" "x")
2942 "TARGET_AVX && TARGET_64BIT"
2943 "vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
2944 [(set_attr "type" "sseicvt")
2945 (set_attr "length_vex" "4")
2946 (set_attr "prefix" "vex")
2947 (set_attr "mode" "DF")])
2949 (define_insn "sse2_cvtsi2sdq"
2950 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2953 (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m")))
2954 (match_operand:V2DF 1 "register_operand" "0,0")
2956 "TARGET_SSE2 && TARGET_64BIT"
2957 "cvtsi2sdq\t{%2, %0|%0, %2}"
2958 [(set_attr "type" "sseicvt")
2959 (set_attr "prefix_rex" "1")
2960 (set_attr "mode" "DF")
2961 (set_attr "athlon_decode" "double,direct")
2962 (set_attr "amdfam10_decode" "vector,double")])
2964 (define_insn "sse2_cvtsd2si"
2965 [(set (match_operand:SI 0 "register_operand" "=r,r")
2968 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2969 (parallel [(const_int 0)]))]
2970 UNSPEC_FIX_NOTRUNC))]
2972 "%vcvtsd2si\t{%1, %0|%0, %1}"
2973 [(set_attr "type" "sseicvt")
2974 (set_attr "athlon_decode" "double,vector")
2975 (set_attr "prefix_rep" "1")
2976 (set_attr "prefix" "maybe_vex")
2977 (set_attr "mode" "SI")])
2979 (define_insn "sse2_cvtsd2si_2"
2980 [(set (match_operand:SI 0 "register_operand" "=r,r")
2981 (unspec:SI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
2982 UNSPEC_FIX_NOTRUNC))]
2984 "%vcvtsd2si\t{%1, %0|%0, %1}"
2985 [(set_attr "type" "sseicvt")
2986 (set_attr "athlon_decode" "double,vector")
2987 (set_attr "amdfam10_decode" "double,double")
2988 (set_attr "prefix_rep" "1")
2989 (set_attr "prefix" "maybe_vex")
2990 (set_attr "mode" "SI")])
2992 (define_insn "sse2_cvtsd2siq"
2993 [(set (match_operand:DI 0 "register_operand" "=r,r")
2996 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2997 (parallel [(const_int 0)]))]
2998 UNSPEC_FIX_NOTRUNC))]
2999 "TARGET_SSE2 && TARGET_64BIT"
3000 "%vcvtsd2siq\t{%1, %0|%0, %1}"
3001 [(set_attr "type" "sseicvt")
3002 (set_attr "athlon_decode" "double,vector")
3003 (set_attr "prefix_rep" "1")
3004 (set_attr "prefix" "maybe_vex")
3005 (set_attr "mode" "DI")])
3007 (define_insn "sse2_cvtsd2siq_2"
3008 [(set (match_operand:DI 0 "register_operand" "=r,r")
3009 (unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
3010 UNSPEC_FIX_NOTRUNC))]
3011 "TARGET_SSE2 && TARGET_64BIT"
3012 "%vcvtsd2siq\t{%1, %0|%0, %1}"
3013 [(set_attr "type" "sseicvt")
3014 (set_attr "athlon_decode" "double,vector")
3015 (set_attr "amdfam10_decode" "double,double")
3016 (set_attr "prefix_rep" "1")
3017 (set_attr "prefix" "maybe_vex")
3018 (set_attr "mode" "DI")])
3020 (define_insn "sse2_cvttsd2si"
3021 [(set (match_operand:SI 0 "register_operand" "=r,r")
3024 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
3025 (parallel [(const_int 0)]))))]
3027 "%vcvttsd2si\t{%1, %0|%0, %1}"
3028 [(set_attr "type" "sseicvt")
3029 (set_attr "prefix_rep" "1")
3030 (set_attr "prefix" "maybe_vex")
3031 (set_attr "mode" "SI")
3032 (set_attr "athlon_decode" "double,vector")
3033 (set_attr "amdfam10_decode" "double,double")])
3035 (define_insn "sse2_cvttsd2siq"
3036 [(set (match_operand:DI 0 "register_operand" "=r,r")
3039 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
3040 (parallel [(const_int 0)]))))]
3041 "TARGET_SSE2 && TARGET_64BIT"
3042 "%vcvttsd2siq\t{%1, %0|%0, %1}"
3043 [(set_attr "type" "sseicvt")
3044 (set_attr "prefix_rep" "1")
3045 (set_attr "prefix" "maybe_vex")
3046 (set_attr "mode" "DI")
3047 (set_attr "athlon_decode" "double,vector")
3048 (set_attr "amdfam10_decode" "double,double")])
3050 (define_insn "avx_cvtdq2pd256"
3051 [(set (match_operand:V4DF 0 "register_operand" "=x")
3052 (float:V4DF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
3054 "vcvtdq2pd\t{%1, %0|%0, %1}"
3055 [(set_attr "type" "ssecvt")
3056 (set_attr "prefix" "vex")
3057 (set_attr "mode" "V4DF")])
3059 (define_insn "sse2_cvtdq2pd"
3060 [(set (match_operand:V2DF 0 "register_operand" "=x")
3063 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
3064 (parallel [(const_int 0) (const_int 1)]))))]
3066 "%vcvtdq2pd\t{%1, %0|%0, %1}"
3067 [(set_attr "type" "ssecvt")
3068 (set_attr "prefix" "maybe_vex")
3069 (set_attr "mode" "V2DF")])
3071 (define_insn "avx_cvtpd2dq256"
3072 [(set (match_operand:V4SI 0 "register_operand" "=x")
3073 (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")]
3074 UNSPEC_FIX_NOTRUNC))]
3076 "vcvtpd2dq{y}\t{%1, %0|%0, %1}"
3077 [(set_attr "type" "ssecvt")
3078 (set_attr "prefix" "vex")
3079 (set_attr "mode" "OI")])
3081 (define_expand "sse2_cvtpd2dq"
3082 [(set (match_operand:V4SI 0 "register_operand" "")
3084 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "")]
3088 "operands[2] = CONST0_RTX (V2SImode);")
3090 (define_insn "*sse2_cvtpd2dq"
3091 [(set (match_operand:V4SI 0 "register_operand" "=x")
3093 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
3095 (match_operand:V2SI 2 "const0_operand" "")))]
3097 "* return TARGET_AVX ? \"vcvtpd2dq{x}\t{%1, %0|%0, %1}\"
3098 : \"cvtpd2dq\t{%1, %0|%0, %1}\";"
3099 [(set_attr "type" "ssecvt")
3100 (set_attr "prefix_rep" "1")
3101 (set_attr "prefix_data16" "0")
3102 (set_attr "prefix" "maybe_vex")
3103 (set_attr "mode" "TI")
3104 (set_attr "amdfam10_decode" "double")])
3106 (define_insn "avx_cvttpd2dq256"
3107 [(set (match_operand:V4SI 0 "register_operand" "=x")
3108 (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
3110 "vcvttpd2dq{y}\t{%1, %0|%0, %1}"
3111 [(set_attr "type" "ssecvt")
3112 (set_attr "prefix" "vex")
3113 (set_attr "mode" "OI")])
3115 (define_expand "sse2_cvttpd2dq"
3116 [(set (match_operand:V4SI 0 "register_operand" "")
3118 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" ""))
3121 "operands[2] = CONST0_RTX (V2SImode);")
3123 (define_insn "*sse2_cvttpd2dq"
3124 [(set (match_operand:V4SI 0 "register_operand" "=x")
3126 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
3127 (match_operand:V2SI 2 "const0_operand" "")))]
3129 "* return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\"
3130 : \"cvttpd2dq\t{%1, %0|%0, %1}\";"
3131 [(set_attr "type" "ssecvt")
3132 (set_attr "prefix" "maybe_vex")
3133 (set_attr "mode" "TI")
3134 (set_attr "amdfam10_decode" "double")])
3136 (define_insn "*avx_cvtsd2ss"
3137 [(set (match_operand:V4SF 0 "register_operand" "=x")
3140 (float_truncate:V2SF
3141 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))
3142 (match_operand:V4SF 1 "register_operand" "x")
3145 "vcvtsd2ss\t{%2, %1, %0|%0, %1, %2}"
3146 [(set_attr "type" "ssecvt")
3147 (set_attr "prefix" "vex")
3148 (set_attr "mode" "SF")])
3150 (define_insn "sse2_cvtsd2ss"
3151 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
3154 (float_truncate:V2SF
3155 (match_operand:V2DF 2 "nonimmediate_operand" "x,m")))
3156 (match_operand:V4SF 1 "register_operand" "0,0")
3159 "cvtsd2ss\t{%2, %0|%0, %2}"
3160 [(set_attr "type" "ssecvt")
3161 (set_attr "athlon_decode" "vector,double")
3162 (set_attr "amdfam10_decode" "vector,double")
3163 (set_attr "mode" "SF")])
3165 (define_insn "*avx_cvtss2sd"
3166 [(set (match_operand:V2DF 0 "register_operand" "=x")
3170 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
3171 (parallel [(const_int 0) (const_int 1)])))
3172 (match_operand:V2DF 1 "register_operand" "x")
3175 "vcvtss2sd\t{%2, %1, %0|%0, %1, %2}"
3176 [(set_attr "type" "ssecvt")
3177 (set_attr "prefix" "vex")
3178 (set_attr "mode" "DF")])
3180 (define_insn "sse2_cvtss2sd"
3181 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
3185 (match_operand:V4SF 2 "nonimmediate_operand" "x,m")
3186 (parallel [(const_int 0) (const_int 1)])))
3187 (match_operand:V2DF 1 "register_operand" "0,0")
3190 "cvtss2sd\t{%2, %0|%0, %2}"
3191 [(set_attr "type" "ssecvt")
3192 (set_attr "amdfam10_decode" "vector,double")
3193 (set_attr "mode" "DF")])
3195 (define_insn "avx_cvtpd2ps256"
3196 [(set (match_operand:V4SF 0 "register_operand" "=x")
3197 (float_truncate:V4SF
3198 (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
3200 "vcvtpd2ps{y}\t{%1, %0|%0, %1}"
3201 [(set_attr "type" "ssecvt")
3202 (set_attr "prefix" "vex")
3203 (set_attr "mode" "V4SF")])
3205 (define_expand "sse2_cvtpd2ps"
3206 [(set (match_operand:V4SF 0 "register_operand" "")
3208 (float_truncate:V2SF
3209 (match_operand:V2DF 1 "nonimmediate_operand" ""))
3212 "operands[2] = CONST0_RTX (V2SFmode);")
3214 (define_insn "*sse2_cvtpd2ps"
3215 [(set (match_operand:V4SF 0 "register_operand" "=x")
3217 (float_truncate:V2SF
3218 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
3219 (match_operand:V2SF 2 "const0_operand" "")))]
3221 "* return TARGET_AVX ? \"vcvtpd2ps{x}\t{%1, %0|%0, %1}\"
3222 : \"cvtpd2ps\t{%1, %0|%0, %1}\";"
3223 [(set_attr "type" "ssecvt")
3224 (set_attr "prefix_data16" "1")
3225 (set_attr "prefix" "maybe_vex")
3226 (set_attr "mode" "V4SF")
3227 (set_attr "amdfam10_decode" "double")])
3229 (define_insn "avx_cvtps2pd256"
3230 [(set (match_operand:V4DF 0 "register_operand" "=x")
3232 (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
3234 "vcvtps2pd\t{%1, %0|%0, %1}"
3235 [(set_attr "type" "ssecvt")
3236 (set_attr "prefix" "vex")
3237 (set_attr "mode" "V4DF")])
3239 (define_insn "sse2_cvtps2pd"
3240 [(set (match_operand:V2DF 0 "register_operand" "=x")
3243 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
3244 (parallel [(const_int 0) (const_int 1)]))))]
3246 "%vcvtps2pd\t{%1, %0|%0, %1}"
3247 [(set_attr "type" "ssecvt")
3248 (set_attr "prefix" "maybe_vex")
3249 (set_attr "mode" "V2DF")
3250 (set_attr "prefix_data16" "0")
3251 (set_attr "amdfam10_decode" "direct")])
3253 (define_expand "vec_unpacks_hi_v4sf"
3258 (match_operand:V4SF 1 "nonimmediate_operand" ""))
3259 (parallel [(const_int 6)
3263 (set (match_operand:V2DF 0 "register_operand" "")
3267 (parallel [(const_int 0) (const_int 1)]))))]
3270 operands[2] = gen_reg_rtx (V4SFmode);
3273 (define_expand "vec_unpacks_lo_v4sf"
3274 [(set (match_operand:V2DF 0 "register_operand" "")
3277 (match_operand:V4SF 1 "nonimmediate_operand" "")
3278 (parallel [(const_int 0) (const_int 1)]))))]
3281 (define_expand "vec_unpacks_float_hi_v8hi"
3282 [(match_operand:V4SF 0 "register_operand" "")
3283 (match_operand:V8HI 1 "register_operand" "")]
3286 rtx tmp = gen_reg_rtx (V4SImode);
3288 emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
3289 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
3293 (define_expand "vec_unpacks_float_lo_v8hi"
3294 [(match_operand:V4SF 0 "register_operand" "")
3295 (match_operand:V8HI 1 "register_operand" "")]
3298 rtx tmp = gen_reg_rtx (V4SImode);
3300 emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
3301 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
3305 (define_expand "vec_unpacku_float_hi_v8hi"
3306 [(match_operand:V4SF 0 "register_operand" "")
3307 (match_operand:V8HI 1 "register_operand" "")]
3310 rtx tmp = gen_reg_rtx (V4SImode);
3312 emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
3313 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
3317 (define_expand "vec_unpacku_float_lo_v8hi"
3318 [(match_operand:V4SF 0 "register_operand" "")
3319 (match_operand:V8HI 1 "register_operand" "")]
3322 rtx tmp = gen_reg_rtx (V4SImode);
3324 emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
3325 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
3329 (define_expand "vec_unpacks_float_hi_v4si"
3332 (match_operand:V4SI 1 "nonimmediate_operand" "")
3333 (parallel [(const_int 2)
3337 (set (match_operand:V2DF 0 "register_operand" "")
3341 (parallel [(const_int 0) (const_int 1)]))))]
3343 "operands[2] = gen_reg_rtx (V4SImode);")
3345 (define_expand "vec_unpacks_float_lo_v4si"
3346 [(set (match_operand:V2DF 0 "register_operand" "")
3349 (match_operand:V4SI 1 "nonimmediate_operand" "")
3350 (parallel [(const_int 0) (const_int 1)]))))]
3353 (define_expand "vec_unpacku_float_hi_v4si"
3356 (match_operand:V4SI 1 "nonimmediate_operand" "")
3357 (parallel [(const_int 2)
3365 (parallel [(const_int 0) (const_int 1)]))))
3367 (lt:V2DF (match_dup 6) (match_dup 3)))
3369 (and:V2DF (match_dup 7) (match_dup 4)))
3370 (set (match_operand:V2DF 0 "register_operand" "")
3371 (plus:V2DF (match_dup 6) (match_dup 8)))]
3374 REAL_VALUE_TYPE TWO32r;
3378 real_ldexp (&TWO32r, &dconst1, 32);
3379 x = const_double_from_real_value (TWO32r, DFmode);
3381 operands[3] = force_reg (V2DFmode, CONST0_RTX (V2DFmode));
3382 operands[4] = force_reg (V2DFmode, ix86_build_const_vector (DFmode, 1, x));
3384 operands[5] = gen_reg_rtx (V4SImode);
3386 for (i = 6; i < 9; i++)
3387 operands[i] = gen_reg_rtx (V2DFmode);
3390 (define_expand "vec_unpacku_float_lo_v4si"
3394 (match_operand:V4SI 1 "nonimmediate_operand" "")
3395 (parallel [(const_int 0) (const_int 1)]))))
3397 (lt:V2DF (match_dup 5) (match_dup 3)))
3399 (and:V2DF (match_dup 6) (match_dup 4)))
3400 (set (match_operand:V2DF 0 "register_operand" "")
3401 (plus:V2DF (match_dup 5) (match_dup 7)))]
3404 REAL_VALUE_TYPE TWO32r;
3408 real_ldexp (&TWO32r, &dconst1, 32);
3409 x = const_double_from_real_value (TWO32r, DFmode);
3411 operands[3] = force_reg (V2DFmode, CONST0_RTX (V2DFmode));
3412 operands[4] = force_reg (V2DFmode, ix86_build_const_vector (DFmode, 1, x));
3414 for (i = 5; i < 8; i++)
3415 operands[i] = gen_reg_rtx (V2DFmode);
3418 (define_expand "vec_pack_trunc_v2df"
3419 [(match_operand:V4SF 0 "register_operand" "")
3420 (match_operand:V2DF 1 "nonimmediate_operand" "")
3421 (match_operand:V2DF 2 "nonimmediate_operand" "")]
3426 r1 = gen_reg_rtx (V4SFmode);
3427 r2 = gen_reg_rtx (V4SFmode);
3429 emit_insn (gen_sse2_cvtpd2ps (r1, operands[1]));
3430 emit_insn (gen_sse2_cvtpd2ps (r2, operands[2]));
3431 emit_insn (gen_sse_movlhps (operands[0], r1, r2));
3435 (define_expand "vec_pack_sfix_trunc_v2df"
3436 [(match_operand:V4SI 0 "register_operand" "")
3437 (match_operand:V2DF 1 "nonimmediate_operand" "")
3438 (match_operand:V2DF 2 "nonimmediate_operand" "")]
3443 r1 = gen_reg_rtx (V4SImode);
3444 r2 = gen_reg_rtx (V4SImode);
3446 emit_insn (gen_sse2_cvttpd2dq (r1, operands[1]));
3447 emit_insn (gen_sse2_cvttpd2dq (r2, operands[2]));
3448 emit_insn (gen_sse2_punpcklqdq (gen_lowpart (V2DImode, operands[0]),
3449 gen_lowpart (V2DImode, r1),
3450 gen_lowpart (V2DImode, r2)));
3454 (define_expand "vec_pack_sfix_v2df"
3455 [(match_operand:V4SI 0 "register_operand" "")
3456 (match_operand:V2DF 1 "nonimmediate_operand" "")
3457 (match_operand:V2DF 2 "nonimmediate_operand" "")]
3462 r1 = gen_reg_rtx (V4SImode);
3463 r2 = gen_reg_rtx (V4SImode);
3465 emit_insn (gen_sse2_cvtpd2dq (r1, operands[1]));
3466 emit_insn (gen_sse2_cvtpd2dq (r2, operands[2]));
3467 emit_insn (gen_sse2_punpcklqdq (gen_lowpart (V2DImode, operands[0]),
3468 gen_lowpart (V2DImode, r1),
3469 gen_lowpart (V2DImode, r2)));
3473 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3475 ;; Parallel single-precision floating point element swizzling
3477 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3479 (define_expand "sse_movhlps_exp"
3480 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
3483 (match_operand:V4SF 1 "nonimmediate_operand" "")
3484 (match_operand:V4SF 2 "nonimmediate_operand" ""))
3485 (parallel [(const_int 6)
3490 "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
3492 (define_insn "*avx_movhlps"
3493 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
3496 (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0")
3497 (match_operand:V4SF 2 "nonimmediate_operand" " x,o,x"))
3498 (parallel [(const_int 6)
3502 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3504 vmovhlps\t{%2, %1, %0|%0, %1, %2}
3505 vmovlps\t{%H2, %1, %0|%0, %1, %H2}
3506 vmovhps\t{%2, %0|%0, %2}"
3507 [(set_attr "type" "ssemov")
3508 (set_attr "prefix" "vex")
3509 (set_attr "mode" "V4SF,V2SF,V2SF")])
3511 (define_insn "sse_movhlps"
3512 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
3515 (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
3516 (match_operand:V4SF 2 "nonimmediate_operand" " x,o,x"))
3517 (parallel [(const_int 6)
3521 "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3523 movhlps\t{%2, %0|%0, %2}
3524 movlps\t{%H2, %0|%0, %H2}
3525 movhps\t{%2, %0|%0, %2}"
3526 [(set_attr "type" "ssemov")
3527 (set_attr "mode" "V4SF,V2SF,V2SF")])
3529 (define_expand "sse_movlhps_exp"
3530 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
3533 (match_operand:V4SF 1 "nonimmediate_operand" "")
3534 (match_operand:V4SF 2 "nonimmediate_operand" ""))
3535 (parallel [(const_int 0)
3540 "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
3542 (define_insn "*avx_movlhps"
3543 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
3546 (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0")
3547 (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
3548 (parallel [(const_int 0)
3552 "TARGET_AVX && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
3554 vmovlhps\t{%2, %1, %0|%0, %1, %2}
3555 vmovhps\t{%2, %1, %0|%0, %1, %2}
3556 vmovlps\t{%2, %H0|%H0, %2}"
3557 [(set_attr "type" "ssemov")
3558 (set_attr "prefix" "vex")
3559 (set_attr "mode" "V4SF,V2SF,V2SF")])
3561 (define_insn "sse_movlhps"
3562 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
3565 (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
3566 (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
3567 (parallel [(const_int 0)
3571 "TARGET_SSE && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
3573 movlhps\t{%2, %0|%0, %2}
3574 movhps\t{%2, %0|%0, %2}
3575 movlps\t{%2, %H0|%H0, %2}"
3576 [(set_attr "type" "ssemov")
3577 (set_attr "mode" "V4SF,V2SF,V2SF")])
3579 (define_insn "avx_unpckhps256"
3580 [(set (match_operand:V8SF 0 "register_operand" "=x")
3583 (match_operand:V8SF 1 "register_operand" "x")
3584 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
3585 (parallel [(const_int 2) (const_int 10)
3586 (const_int 3) (const_int 11)
3587 (const_int 6) (const_int 14)
3588 (const_int 7) (const_int 15)])))]
3590 "vunpckhps\t{%2, %1, %0|%0, %1, %2}"
3591 [(set_attr "type" "sselog")
3592 (set_attr "prefix" "vex")
3593 (set_attr "mode" "V8SF")])
3595 (define_insn "*avx_unpckhps"
3596 [(set (match_operand:V4SF 0 "register_operand" "=x")
3599 (match_operand:V4SF 1 "register_operand" "x")
3600 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
3601 (parallel [(const_int 2) (const_int 6)
3602 (const_int 3) (const_int 7)])))]
3604 "vunpckhps\t{%2, %1, %0|%0, %1, %2}"
3605 [(set_attr "type" "sselog")
3606 (set_attr "prefix" "vex")
3607 (set_attr "mode" "V4SF")])
3609 (define_insn "sse_unpckhps"
3610 [(set (match_operand:V4SF 0 "register_operand" "=x")
3613 (match_operand:V4SF 1 "register_operand" "0")
3614 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
3615 (parallel [(const_int 2) (const_int 6)
3616 (const_int 3) (const_int 7)])))]
3618 "unpckhps\t{%2, %0|%0, %2}"
3619 [(set_attr "type" "sselog")
3620 (set_attr "mode" "V4SF")])
3622 (define_insn "avx_unpcklps256"
3623 [(set (match_operand:V8SF 0 "register_operand" "=x")
3626 (match_operand:V8SF 1 "register_operand" "x")
3627 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
3628 (parallel [(const_int 0) (const_int 8)
3629 (const_int 1) (const_int 9)
3630 (const_int 4) (const_int 12)
3631 (const_int 5) (const_int 13)])))]
3633 "vunpcklps\t{%2, %1, %0|%0, %1, %2}"
3634 [(set_attr "type" "sselog")
3635 (set_attr "prefix" "vex")
3636 (set_attr "mode" "V8SF")])
3638 (define_insn "*avx_unpcklps"
3639 [(set (match_operand:V4SF 0 "register_operand" "=x")
3642 (match_operand:V4SF 1 "register_operand" "x")
3643 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
3644 (parallel [(const_int 0) (const_int 4)
3645 (const_int 1) (const_int 5)])))]
3647 "vunpcklps\t{%2, %1, %0|%0, %1, %2}"
3648 [(set_attr "type" "sselog")
3649 (set_attr "prefix" "vex")
3650 (set_attr "mode" "V4SF")])
3652 (define_insn "sse_unpcklps"
3653 [(set (match_operand:V4SF 0 "register_operand" "=x")
3656 (match_operand:V4SF 1 "register_operand" "0")
3657 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
3658 (parallel [(const_int 0) (const_int 4)
3659 (const_int 1) (const_int 5)])))]
3661 "unpcklps\t{%2, %0|%0, %2}"
3662 [(set_attr "type" "sselog")
3663 (set_attr "mode" "V4SF")])
3665 ;; These are modeled with the same vec_concat as the others so that we
3666 ;; capture users of shufps that can use the new instructions
3667 (define_insn "avx_movshdup256"
3668 [(set (match_operand:V8SF 0 "register_operand" "=x")
3671 (match_operand:V8SF 1 "nonimmediate_operand" "xm")
3673 (parallel [(const_int 1) (const_int 1)
3674 (const_int 3) (const_int 3)
3675 (const_int 5) (const_int 5)
3676 (const_int 7) (const_int 7)])))]
3678 "vmovshdup\t{%1, %0|%0, %1}"
3679 [(set_attr "type" "sse")
3680 (set_attr "prefix" "vex")
3681 (set_attr "mode" "V8SF")])
3683 (define_insn "sse3_movshdup"
3684 [(set (match_operand:V4SF 0 "register_operand" "=x")
3687 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
3689 (parallel [(const_int 1)
3694 "%vmovshdup\t{%1, %0|%0, %1}"
3695 [(set_attr "type" "sse")
3696 (set_attr "prefix_rep" "1")
3697 (set_attr "prefix" "maybe_vex")
3698 (set_attr "mode" "V4SF")])
3700 (define_insn "avx_movsldup256"
3701 [(set (match_operand:V8SF 0 "register_operand" "=x")
3704 (match_operand:V8SF 1 "nonimmediate_operand" "xm")
3706 (parallel [(const_int 0) (const_int 0)
3707 (const_int 2) (const_int 2)
3708 (const_int 4) (const_int 4)
3709 (const_int 6) (const_int 6)])))]
3711 "vmovsldup\t{%1, %0|%0, %1}"
3712 [(set_attr "type" "sse")
3713 (set_attr "prefix" "vex")
3714 (set_attr "mode" "V8SF")])
3716 (define_insn "sse3_movsldup"
3717 [(set (match_operand:V4SF 0 "register_operand" "=x")
3720 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
3722 (parallel [(const_int 0)
3727 "%vmovsldup\t{%1, %0|%0, %1}"
3728 [(set_attr "type" "sse")
3729 (set_attr "prefix_rep" "1")
3730 (set_attr "prefix" "maybe_vex")
3731 (set_attr "mode" "V4SF")])
3733 (define_expand "avx_shufps256"
3734 [(match_operand:V8SF 0 "register_operand" "")
3735 (match_operand:V8SF 1 "register_operand" "")
3736 (match_operand:V8SF 2 "nonimmediate_operand" "")
3737 (match_operand:SI 3 "const_int_operand" "")]
3740 int mask = INTVAL (operands[3]);
3741 emit_insn (gen_avx_shufps256_1 (operands[0], operands[1], operands[2],
3742 GEN_INT ((mask >> 0) & 3),
3743 GEN_INT ((mask >> 2) & 3),
3744 GEN_INT (((mask >> 4) & 3) + 8),
3745 GEN_INT (((mask >> 6) & 3) + 8),
3746 GEN_INT (((mask >> 0) & 3) + 4),
3747 GEN_INT (((mask >> 2) & 3) + 4),
3748 GEN_INT (((mask >> 4) & 3) + 12),
3749 GEN_INT (((mask >> 6) & 3) + 12)));
3753 ;; One bit in mask selects 2 elements.
3754 (define_insn "avx_shufps256_1"
3755 [(set (match_operand:V8SF 0 "register_operand" "=x")
3758 (match_operand:V8SF 1 "register_operand" "x")
3759 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
3760 (parallel [(match_operand 3 "const_0_to_3_operand" "")
3761 (match_operand 4 "const_0_to_3_operand" "")
3762 (match_operand 5 "const_8_to_11_operand" "")
3763 (match_operand 6 "const_8_to_11_operand" "")
3764 (match_operand 7 "const_4_to_7_operand" "")
3765 (match_operand 8 "const_4_to_7_operand" "")
3766 (match_operand 9 "const_12_to_15_operand" "")
3767 (match_operand 10 "const_12_to_15_operand" "")])))]
3769 && (INTVAL (operands[3]) == (INTVAL (operands[7]) - 4)
3770 && INTVAL (operands[4]) == (INTVAL (operands[8]) - 4)
3771 && INTVAL (operands[5]) == (INTVAL (operands[9]) - 4)
3772 && INTVAL (operands[6]) == (INTVAL (operands[10]) - 4))"
3775 mask = INTVAL (operands[3]);
3776 mask |= INTVAL (operands[4]) << 2;
3777 mask |= (INTVAL (operands[5]) - 8) << 4;
3778 mask |= (INTVAL (operands[6]) - 8) << 6;
3779 operands[3] = GEN_INT (mask);
3781 return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3783 [(set_attr "type" "sselog")
3784 (set_attr "length_immediate" "1")
3785 (set_attr "prefix" "vex")
3786 (set_attr "mode" "V8SF")])
3788 (define_expand "sse_shufps"
3789 [(match_operand:V4SF 0 "register_operand" "")
3790 (match_operand:V4SF 1 "register_operand" "")
3791 (match_operand:V4SF 2 "nonimmediate_operand" "")
3792 (match_operand:SI 3 "const_int_operand" "")]
3795 int mask = INTVAL (operands[3]);
3796 emit_insn (gen_sse_shufps_v4sf (operands[0], operands[1], operands[2],
3797 GEN_INT ((mask >> 0) & 3),
3798 GEN_INT ((mask >> 2) & 3),
3799 GEN_INT (((mask >> 4) & 3) + 4),
3800 GEN_INT (((mask >> 6) & 3) + 4)));
3804 (define_insn "*avx_shufps_<mode>"
3805 [(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
3806 (vec_select:SSEMODE4S
3807 (vec_concat:<ssedoublesizemode>
3808 (match_operand:SSEMODE4S 1 "register_operand" "x")
3809 (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
3810 (parallel [(match_operand 3 "const_0_to_3_operand" "")
3811 (match_operand 4 "const_0_to_3_operand" "")
3812 (match_operand 5 "const_4_to_7_operand" "")
3813 (match_operand 6 "const_4_to_7_operand" "")])))]
3817 mask |= INTVAL (operands[3]) << 0;
3818 mask |= INTVAL (operands[4]) << 2;
3819 mask |= (INTVAL (operands[5]) - 4) << 4;
3820 mask |= (INTVAL (operands[6]) - 4) << 6;
3821 operands[3] = GEN_INT (mask);
3823 return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3825 [(set_attr "type" "sselog")
3826 (set_attr "length_immediate" "1")
3827 (set_attr "prefix" "vex")
3828 (set_attr "mode" "V4SF")])
3830 (define_insn "sse_shufps_<mode>"
3831 [(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
3832 (vec_select:SSEMODE4S
3833 (vec_concat:<ssedoublesizemode>
3834 (match_operand:SSEMODE4S 1 "register_operand" "0")
3835 (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
3836 (parallel [(match_operand 3 "const_0_to_3_operand" "")
3837 (match_operand 4 "const_0_to_3_operand" "")
3838 (match_operand 5 "const_4_to_7_operand" "")
3839 (match_operand 6 "const_4_to_7_operand" "")])))]
3843 mask |= INTVAL (operands[3]) << 0;
3844 mask |= INTVAL (operands[4]) << 2;
3845 mask |= (INTVAL (operands[5]) - 4) << 4;
3846 mask |= (INTVAL (operands[6]) - 4) << 6;
3847 operands[3] = GEN_INT (mask);
3849 return "shufps\t{%3, %2, %0|%0, %2, %3}";
3851 [(set_attr "type" "sselog")
3852 (set_attr "length_immediate" "1")
3853 (set_attr "mode" "V4SF")])
3855 (define_insn "sse_storehps"
3856 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
3858 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,o")
3859 (parallel [(const_int 2) (const_int 3)])))]
3862 %vmovhps\t{%1, %0|%0, %1}
3863 %vmovhlps\t{%1, %d0|%d0, %1}
3864 %vmovlps\t{%H1, %d0|%d0, %H1}"
3865 [(set_attr "type" "ssemov")
3866 (set_attr "prefix" "maybe_vex")
3867 (set_attr "mode" "V2SF,V4SF,V2SF")])
3869 (define_expand "sse_loadhps_exp"
3870 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
3873 (match_operand:V4SF 1 "nonimmediate_operand" "")
3874 (parallel [(const_int 0) (const_int 1)]))
3875 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
3877 "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
3879 (define_insn "*avx_loadhps"
3880 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
3883 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
3884 (parallel [(const_int 0) (const_int 1)]))
3885 (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
3888 vmovhps\t{%2, %1, %0|%0, %1, %2}
3889 vmovlhps\t{%2, %1, %0|%0, %1, %2}
3890 vmovlps\t{%2, %H0|%H0, %2}"
3891 [(set_attr "type" "ssemov")
3892 (set_attr "prefix" "vex")
3893 (set_attr "mode" "V2SF,V4SF,V2SF")])
3895 (define_insn "sse_loadhps"
3896 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
3899 (match_operand:V4SF 1 "nonimmediate_operand" "0,0,0")
3900 (parallel [(const_int 0) (const_int 1)]))
3901 (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
3904 movhps\t{%2, %0|%0, %2}
3905 movlhps\t{%2, %0|%0, %2}
3906 movlps\t{%2, %H0|%H0, %2}"
3907 [(set_attr "type" "ssemov")
3908 (set_attr "mode" "V2SF,V4SF,V2SF")])
3910 (define_insn "*avx_storelps"
3911 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
3913 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
3914 (parallel [(const_int 0) (const_int 1)])))]
3917 vmovlps\t{%1, %0|%0, %1}
3918 vmovaps\t{%1, %0|%0, %1}
3919 vmovlps\t{%1, %0, %0|%0, %0, %1}"
3920 [(set_attr "type" "ssemov")
3921 (set_attr "prefix" "vex")
3922 (set_attr "mode" "V2SF,V2DF,V2SF")])
3924 (define_insn "sse_storelps"
3925 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
3927 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
3928 (parallel [(const_int 0) (const_int 1)])))]
3931 movlps\t{%1, %0|%0, %1}
3932 movaps\t{%1, %0|%0, %1}
3933 movlps\t{%1, %0|%0, %1}"
3934 [(set_attr "type" "ssemov")
3935 (set_attr "mode" "V2SF,V4SF,V2SF")])
3937 (define_expand "sse_loadlps_exp"
3938 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
3940 (match_operand:V2SF 2 "nonimmediate_operand" "")
3942 (match_operand:V4SF 1 "nonimmediate_operand" "")
3943 (parallel [(const_int 2) (const_int 3)]))))]
3945 "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
3947 (define_insn "*avx_loadlps"
3948 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
3950 (match_operand:V2SF 2 "nonimmediate_operand" "x,m,x")
3952 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
3953 (parallel [(const_int 2) (const_int 3)]))))]
3956 shufps\t{$0xe4, %1, %2, %0|%0, %2, %1, 0xe4}
3957 vmovlps\t{%2, %1, %0|%0, %1, %2}
3958 vmovlps\t{%2, %0|%0, %2}"
3959 [(set_attr "type" "sselog,ssemov,ssemov")
3960 (set_attr "length_immediate" "1,*,*")
3961 (set_attr "prefix" "vex")
3962 (set_attr "mode" "V4SF,V2SF,V2SF")])
3964 (define_insn "sse_loadlps"
3965 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
3967 (match_operand:V2SF 2 "nonimmediate_operand" "0,m,x")
3969 (match_operand:V4SF 1 "nonimmediate_operand" "x,0,0")
3970 (parallel [(const_int 2) (const_int 3)]))))]
3973 shufps\t{$0xe4, %1, %0|%0, %1, 0xe4}
3974 movlps\t{%2, %0|%0, %2}
3975 movlps\t{%2, %0|%0, %2}"
3976 [(set_attr "type" "sselog,ssemov,ssemov")
3977 (set_attr "length_immediate" "1,*,*")
3978 (set_attr "mode" "V4SF,V2SF,V2SF")])
3980 (define_insn "*avx_movss"
3981 [(set (match_operand:V4SF 0 "register_operand" "=x")
3983 (match_operand:V4SF 2 "register_operand" "x")
3984 (match_operand:V4SF 1 "register_operand" "x")
3987 "vmovss\t{%2, %1, %0|%0, %1, %2}"
3988 [(set_attr "type" "ssemov")
3989 (set_attr "prefix" "vex")
3990 (set_attr "mode" "SF")])
3992 (define_insn "sse_movss"
3993 [(set (match_operand:V4SF 0 "register_operand" "=x")
3995 (match_operand:V4SF 2 "register_operand" "x")
3996 (match_operand:V4SF 1 "register_operand" "0")
3999 "movss\t{%2, %0|%0, %2}"
4000 [(set_attr "type" "ssemov")
4001 (set_attr "mode" "SF")])
4003 (define_insn "*vec_dupv4sf_avx"
4004 [(set (match_operand:V4SF 0 "register_operand" "=x")
4006 (match_operand:SF 1 "register_operand" "x")))]
4008 "vshufps\t{$0, %1, %1, %0|%0, %1, %1, 0}"
4009 [(set_attr "type" "sselog1")
4010 (set_attr "length_immediate" "1")
4011 (set_attr "prefix" "vex")
4012 (set_attr "mode" "V4SF")])
4014 (define_insn "*vec_dupv4sf"
4015 [(set (match_operand:V4SF 0 "register_operand" "=x")
4017 (match_operand:SF 1 "register_operand" "0")))]
4019 "shufps\t{$0, %0, %0|%0, %0, 0}"
4020 [(set_attr "type" "sselog1")
4021 (set_attr "length_immediate" "1")
4022 (set_attr "mode" "V4SF")])
4024 (define_insn "*vec_concatv2sf_avx"
4025 [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y")
4027 (match_operand:SF 1 "nonimmediate_operand" " x,x,m, x , m")
4028 (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))]
4031 vunpcklps\t{%2, %1, %0|%0, %1, %2}
4032 vinsertps\t{$0x10, %2, %1, %0|%0, %1, %2, 0x10}
4033 vmovss\t{%1, %0|%0, %1}
4034 punpckldq\t{%2, %0|%0, %2}
4035 movd\t{%1, %0|%0, %1}"
4036 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
4037 (set_attr "length_immediate" "*,1,*,*,*")
4038 (set_attr "prefix_extra" "*,1,*,*,*")
4039 (set (attr "prefix")
4040 (if_then_else (eq_attr "alternative" "3,4")
4041 (const_string "orig")
4042 (const_string "vex")))
4043 (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
4045 ;; Although insertps takes register source, we prefer
4046 ;; unpcklps with register source since it is shorter.
4047 (define_insn "*vec_concatv2sf_sse4_1"
4048 [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y")
4050 (match_operand:SF 1 "nonimmediate_operand" " 0,0,m, 0 , m")
4051 (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))]
4054 unpcklps\t{%2, %0|%0, %2}
4055 insertps\t{$0x10, %2, %0|%0, %2, 0x10}
4056 movss\t{%1, %0|%0, %1}
4057 punpckldq\t{%2, %0|%0, %2}
4058 movd\t{%1, %0|%0, %1}"
4059 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
4060 (set_attr "prefix_data16" "*,1,*,*,*")
4061 (set_attr "prefix_extra" "*,1,*,*,*")
4062 (set_attr "length_immediate" "*,1,*,*,*")
4063 (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
4065 ;; ??? In theory we can match memory for the MMX alternative, but allowing
4066 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
4067 ;; alternatives pretty much forces the MMX alternative to be chosen.
4068 (define_insn "*vec_concatv2sf_sse"
4069 [(set (match_operand:V2SF 0 "register_operand" "=x,x,*y,*y")
4071 (match_operand:SF 1 "nonimmediate_operand" " 0,m, 0, m")
4072 (match_operand:SF 2 "reg_or_0_operand" " x,C,*y, C")))]
4075 unpcklps\t{%2, %0|%0, %2}
4076 movss\t{%1, %0|%0, %1}
4077 punpckldq\t{%2, %0|%0, %2}
4078 movd\t{%1, %0|%0, %1}"
4079 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
4080 (set_attr "mode" "V4SF,SF,DI,DI")])
4082 (define_insn "*vec_concatv4sf_avx"
4083 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
4085 (match_operand:V2SF 1 "register_operand" " x,x")
4086 (match_operand:V2SF 2 "nonimmediate_operand" " x,m")))]
4089 vmovlhps\t{%2, %1, %0|%0, %1, %2}
4090 vmovhps\t{%2, %1, %0|%0, %1, %2}"
4091 [(set_attr "type" "ssemov")
4092 (set_attr "prefix" "vex")
4093 (set_attr "mode" "V4SF,V2SF")])
4095 (define_insn "*vec_concatv4sf_sse"
4096 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
4098 (match_operand:V2SF 1 "register_operand" " 0,0")
4099 (match_operand:V2SF 2 "nonimmediate_operand" " x,m")))]
4102 movlhps\t{%2, %0|%0, %2}
4103 movhps\t{%2, %0|%0, %2}"
4104 [(set_attr "type" "ssemov")
4105 (set_attr "mode" "V4SF,V2SF")])
4107 (define_expand "vec_init<mode>"
4108 [(match_operand:SSEMODE 0 "register_operand" "")
4109 (match_operand 1 "" "")]
4112 ix86_expand_vector_init (false, operands[0], operands[1]);
4116 (define_insn "*vec_setv4sf_0_avx"
4117 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,m")
4120 (match_operand:SF 2 "general_operand" " x,m,*r,x*rfF"))
4121 (match_operand:V4SF 1 "vector_move_operand" " x,C,C ,0")
4125 vmovss\t{%2, %1, %0|%0, %1, %2}
4126 vmovss\t{%2, %0|%0, %2}
4127 vmovd\t{%2, %0|%0, %2}
4129 [(set_attr "type" "ssemov")
4130 (set_attr "prefix" "vex")
4131 (set_attr "mode" "SF")])
4133 (define_insn "vec_setv4sf_0"
4134 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,Y2,m")
4137 (match_operand:SF 2 "general_operand" " x,m,*r,x*rfF"))
4138 (match_operand:V4SF 1 "vector_move_operand" " 0,C,C ,0")
4142 movss\t{%2, %0|%0, %2}
4143 movss\t{%2, %0|%0, %2}
4144 movd\t{%2, %0|%0, %2}
4146 [(set_attr "type" "ssemov")
4147 (set_attr "mode" "SF")])
4149 ;; A subset is vec_setv4sf.
4150 (define_insn "*vec_setv4sf_avx"
4151 [(set (match_operand:V4SF 0 "register_operand" "=x")
4154 (match_operand:SF 2 "nonimmediate_operand" "xm"))
4155 (match_operand:V4SF 1 "register_operand" "x")
4156 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
4159 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
4160 return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
4162 [(set_attr "type" "sselog")
4163 (set_attr "prefix_extra" "1")
4164 (set_attr "length_immediate" "1")
4165 (set_attr "prefix" "vex")
4166 (set_attr "mode" "V4SF")])
4168 (define_insn "*vec_setv4sf_sse4_1"
4169 [(set (match_operand:V4SF 0 "register_operand" "=x")
4172 (match_operand:SF 2 "nonimmediate_operand" "xm"))
4173 (match_operand:V4SF 1 "register_operand" "0")
4174 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
4177 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
4178 return "insertps\t{%3, %2, %0|%0, %2, %3}";
4180 [(set_attr "type" "sselog")
4181 (set_attr "prefix_data16" "1")
4182 (set_attr "prefix_extra" "1")
4183 (set_attr "length_immediate" "1")
4184 (set_attr "mode" "V4SF")])
4186 (define_insn "*avx_insertps"
4187 [(set (match_operand:V4SF 0 "register_operand" "=x")
4188 (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "xm")
4189 (match_operand:V4SF 1 "register_operand" "x")
4190 (match_operand:SI 3 "const_0_to_255_operand" "n")]
4193 "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
4194 [(set_attr "type" "sselog")
4195 (set_attr "prefix" "vex")
4196 (set_attr "prefix_extra" "1")
4197 (set_attr "length_immediate" "1")
4198 (set_attr "mode" "V4SF")])
4200 (define_insn "sse4_1_insertps"
4201 [(set (match_operand:V4SF 0 "register_operand" "=x")
4202 (unspec:V4SF [(match_operand:V4SF 2 "register_operand" "x")
4203 (match_operand:V4SF 1 "register_operand" "0")
4204 (match_operand:SI 3 "const_0_to_255_operand" "n")]
4207 "insertps\t{%3, %2, %0|%0, %2, %3}";
4208 [(set_attr "type" "sselog")
4209 (set_attr "prefix_data16" "1")
4210 (set_attr "prefix_extra" "1")
4211 (set_attr "length_immediate" "1")
4212 (set_attr "mode" "V4SF")])
4215 [(set (match_operand:V4SF 0 "memory_operand" "")
4218 (match_operand:SF 1 "nonmemory_operand" ""))
4221 "TARGET_SSE && reload_completed"
4224 emit_move_insn (adjust_address (operands[0], SFmode, 0), operands[1]);
4228 (define_expand "vec_set<mode>"
4229 [(match_operand:SSEMODE 0 "register_operand" "")
4230 (match_operand:<ssescalarmode> 1 "register_operand" "")
4231 (match_operand 2 "const_int_operand" "")]
4234 ix86_expand_vector_set (false, operands[0], operands[1],
4235 INTVAL (operands[2]));
4239 (define_insn_and_split "*vec_extractv4sf_0"
4240 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,m,f,r")
4242 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x,m,m")
4243 (parallel [(const_int 0)])))]
4244 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4246 "&& reload_completed"
4249 rtx op1 = operands[1];
4251 op1 = gen_rtx_REG (SFmode, REGNO (op1));
4253 op1 = gen_lowpart (SFmode, op1);
4254 emit_move_insn (operands[0], op1);
4258 (define_expand "avx_vextractf128<mode>"
4259 [(match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "")
4260 (match_operand:AVX256MODE 1 "register_operand" "")
4261 (match_operand:SI 2 "const_0_to_1_operand" "")]
4264 switch (INTVAL (operands[2]))
4267 emit_insn (gen_vec_extract_lo_<mode> (operands[0], operands[1]));
4270 emit_insn (gen_vec_extract_hi_<mode> (operands[0], operands[1]));
4278 (define_insn "vec_extract_lo_<mode>"
4279 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
4280 (vec_select:<avxhalfvecmode>
4281 (match_operand:AVX256MODE4P 1 "register_operand" "x,x")
4282 (parallel [(const_int 0) (const_int 1)])))]
4284 "vextractf128\t{$0x0, %1, %0|%0, %1, 0x0}"
4285 [(set_attr "type" "sselog")
4286 (set_attr "prefix_extra" "1")
4287 (set_attr "length_immediate" "1")
4288 (set_attr "memory" "none,store")
4289 (set_attr "prefix" "vex")
4290 (set_attr "mode" "V8SF")])
4292 (define_insn "vec_extract_hi_<mode>"
4293 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
4294 (vec_select:<avxhalfvecmode>
4295 (match_operand:AVX256MODE4P 1 "register_operand" "x,x")
4296 (parallel [(const_int 2) (const_int 3)])))]
4298 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
4299 [(set_attr "type" "sselog")
4300 (set_attr "prefix_extra" "1")
4301 (set_attr "length_immediate" "1")
4302 (set_attr "memory" "none,store")
4303 (set_attr "prefix" "vex")
4304 (set_attr "mode" "V8SF")])
4306 (define_insn "vec_extract_lo_<mode>"
4307 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
4308 (vec_select:<avxhalfvecmode>
4309 (match_operand:AVX256MODE8P 1 "register_operand" "x,x")
4310 (parallel [(const_int 0) (const_int 1)
4311 (const_int 2) (const_int 3)])))]
4313 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
4314 [(set_attr "type" "sselog")
4315 (set_attr "prefix_extra" "1")
4316 (set_attr "length_immediate" "1")
4317 (set_attr "memory" "none,store")
4318 (set_attr "prefix" "vex")
4319 (set_attr "mode" "V8SF")])
4321 (define_insn "vec_extract_hi_<mode>"
4322 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
4323 (vec_select:<avxhalfvecmode>
4324 (match_operand:AVX256MODE8P 1 "register_operand" "x,x")
4325 (parallel [(const_int 4) (const_int 5)
4326 (const_int 6) (const_int 7)])))]
4328 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
4329 [(set_attr "type" "sselog")
4330 (set_attr "prefix_extra" "1")
4331 (set_attr "length_immediate" "1")
4332 (set_attr "memory" "none,store")
4333 (set_attr "prefix" "vex")
4334 (set_attr "mode" "V8SF")])
4336 (define_insn "vec_extract_lo_v16hi"
4337 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
4339 (match_operand:V16HI 1 "register_operand" "x,x")
4340 (parallel [(const_int 0) (const_int 1)
4341 (const_int 2) (const_int 3)
4342 (const_int 4) (const_int 5)
4343 (const_int 6) (const_int 7)])))]
4345 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
4346 [(set_attr "type" "sselog")
4347 (set_attr "prefix_extra" "1")
4348 (set_attr "length_immediate" "1")
4349 (set_attr "memory" "none,store")
4350 (set_attr "prefix" "vex")
4351 (set_attr "mode" "V8SF")])
4353 (define_insn "vec_extract_hi_v16hi"
4354 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
4356 (match_operand:V16HI 1 "register_operand" "x,x")
4357 (parallel [(const_int 8) (const_int 9)
4358 (const_int 10) (const_int 11)
4359 (const_int 12) (const_int 13)
4360 (const_int 14) (const_int 15)])))]
4362 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
4363 [(set_attr "type" "sselog")
4364 (set_attr "prefix_extra" "1")
4365 (set_attr "length_immediate" "1")
4366 (set_attr "memory" "none,store")
4367 (set_attr "prefix" "vex")
4368 (set_attr "mode" "V8SF")])
4370 (define_insn "vec_extract_lo_v32qi"
4371 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
4373 (match_operand:V32QI 1 "register_operand" "x,x")
4374 (parallel [(const_int 0) (const_int 1)
4375 (const_int 2) (const_int 3)
4376 (const_int 4) (const_int 5)
4377 (const_int 6) (const_int 7)
4378 (const_int 8) (const_int 9)
4379 (const_int 10) (const_int 11)
4380 (const_int 12) (const_int 13)
4381 (const_int 14) (const_int 15)])))]
4383 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
4384 [(set_attr "type" "sselog")
4385 (set_attr "prefix_extra" "1")
4386 (set_attr "length_immediate" "1")
4387 (set_attr "memory" "none,store")
4388 (set_attr "prefix" "vex")
4389 (set_attr "mode" "V8SF")])
4391 (define_insn "vec_extract_hi_v32qi"
4392 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
4394 (match_operand:V32QI 1 "register_operand" "x,x")
4395 (parallel [(const_int 16) (const_int 17)
4396 (const_int 18) (const_int 19)
4397 (const_int 20) (const_int 21)
4398 (const_int 22) (const_int 23)
4399 (const_int 24) (const_int 25)
4400 (const_int 26) (const_int 27)
4401 (const_int 28) (const_int 29)
4402 (const_int 30) (const_int 31)])))]
4404 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
4405 [(set_attr "type" "sselog")
4406 (set_attr "prefix_extra" "1")
4407 (set_attr "length_immediate" "1")
4408 (set_attr "memory" "none,store")
4409 (set_attr "prefix" "vex")
4410 (set_attr "mode" "V8SF")])
4412 (define_insn "*sse4_1_extractps"
4413 [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
4415 (match_operand:V4SF 1 "register_operand" "x")
4416 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")])))]
4418 "%vextractps\t{%2, %1, %0|%0, %1, %2}"
4419 [(set_attr "type" "sselog")
4420 (set_attr "prefix_data16" "1")
4421 (set_attr "prefix_extra" "1")
4422 (set_attr "length_immediate" "1")
4423 (set_attr "prefix" "maybe_vex")
4424 (set_attr "mode" "V4SF")])
4426 (define_insn_and_split "*vec_extract_v4sf_mem"
4427 [(set (match_operand:SF 0 "register_operand" "=x*rf")
4429 (match_operand:V4SF 1 "memory_operand" "o")
4430 (parallel [(match_operand 2 "const_0_to_3_operand" "n")])))]
4436 int i = INTVAL (operands[2]);
4438 emit_move_insn (operands[0], adjust_address (operands[1], SFmode, i*4));
4442 (define_expand "vec_extract<mode>"
4443 [(match_operand:<ssescalarmode> 0 "register_operand" "")
4444 (match_operand:SSEMODE 1 "register_operand" "")
4445 (match_operand 2 "const_int_operand" "")]
4448 ix86_expand_vector_extract (false, operands[0], operands[1],
4449 INTVAL (operands[2]));
4453 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4455 ;; Parallel double-precision floating point element swizzling
4457 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4459 (define_insn "avx_unpckhpd256"
4460 [(set (match_operand:V4DF 0 "register_operand" "=x")
4463 (match_operand:V4DF 1 "register_operand" "x")
4464 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
4465 (parallel [(const_int 1) (const_int 5)
4466 (const_int 3) (const_int 7)])))]
4468 "vunpckhpd\t{%2, %1, %0|%0, %1, %2}"
4469 [(set_attr "type" "sselog")
4470 (set_attr "prefix" "vex")
4471 (set_attr "mode" "V4DF")])
4473 (define_expand "sse2_unpckhpd_exp"
4474 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
4477 (match_operand:V2DF 1 "nonimmediate_operand" "")
4478 (match_operand:V2DF 2 "nonimmediate_operand" ""))
4479 (parallel [(const_int 1)
4482 "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
4484 (define_insn "*avx_unpckhpd"
4485 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
4488 (match_operand:V2DF 1 "nonimmediate_operand" " x,o,x")
4489 (match_operand:V2DF 2 "nonimmediate_operand" " x,x,0"))
4490 (parallel [(const_int 1)
4492 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4494 vunpckhpd\t{%2, %1, %0|%0, %1, %2}
4495 vmovlpd\t{%H1, %2, %0|%0, %2, %H1}
4496 vmovhpd\t{%1, %0|%0, %1}"
4497 [(set_attr "type" "sselog,ssemov,ssemov")
4498 (set_attr "prefix" "vex")
4499 (set_attr "mode" "V2DF,V1DF,V1DF")])
4501 (define_insn "sse2_unpckhpd"
4502 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
4505 (match_operand:V2DF 1 "nonimmediate_operand" " 0,o,x")
4506 (match_operand:V2DF 2 "nonimmediate_operand" " x,0,0"))
4507 (parallel [(const_int 1)
4509 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4511 unpckhpd\t{%2, %0|%0, %2}
4512 movlpd\t{%H1, %0|%0, %H1}
4513 movhpd\t{%1, %0|%0, %1}"
4514 [(set_attr "type" "sselog,ssemov,ssemov")
4515 (set_attr "prefix_data16" "*,1,1")
4516 (set_attr "mode" "V2DF,V1DF,V1DF")])
4518 (define_insn "avx_movddup256"
4519 [(set (match_operand:V4DF 0 "register_operand" "=x")
4522 (match_operand:V4DF 1 "nonimmediate_operand" "xm")
4524 (parallel [(const_int 0) (const_int 2)
4525 (const_int 4) (const_int 6)])))]
4527 "vmovddup\t{%1, %0|%0, %1}"
4528 [(set_attr "type" "sselog1")
4529 (set_attr "prefix" "vex")
4530 (set_attr "mode" "V4DF")])
4532 (define_insn "*avx_movddup"
4533 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,o")
4536 (match_operand:V2DF 1 "nonimmediate_operand" "xm,x")
4538 (parallel [(const_int 0)
4540 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4542 vmovddup\t{%1, %0|%0, %1}
4544 [(set_attr "type" "sselog1,ssemov")
4545 (set_attr "prefix" "vex")
4546 (set_attr "mode" "V2DF")])
4548 (define_insn "*sse3_movddup"
4549 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,o")
4552 (match_operand:V2DF 1 "nonimmediate_operand" "xm,x")
4554 (parallel [(const_int 0)
4556 "TARGET_SSE3 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4558 movddup\t{%1, %0|%0, %1}
4560 [(set_attr "type" "sselog1,ssemov")
4561 (set_attr "mode" "V2DF")])
4564 [(set (match_operand:V2DF 0 "memory_operand" "")
4567 (match_operand:V2DF 1 "register_operand" "")
4569 (parallel [(const_int 0)
4571 "TARGET_SSE3 && reload_completed"
4574 rtx low = gen_rtx_REG (DFmode, REGNO (operands[1]));
4575 emit_move_insn (adjust_address (operands[0], DFmode, 0), low);
4576 emit_move_insn (adjust_address (operands[0], DFmode, 8), low);
4580 (define_insn "avx_unpcklpd256"
4581 [(set (match_operand:V4DF 0 "register_operand" "=x")
4584 (match_operand:V4DF 1 "register_operand" "x")
4585 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
4586 (parallel [(const_int 0) (const_int 4)
4587 (const_int 2) (const_int 6)])))]
4589 "vunpcklpd\t{%2, %1, %0|%0, %1, %2}"
4590 [(set_attr "type" "sselog")
4591 (set_attr "prefix" "vex")
4592 (set_attr "mode" "V4DF")])
4594 (define_expand "sse2_unpcklpd_exp"
4595 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
4598 (match_operand:V2DF 1 "nonimmediate_operand" "")
4599 (match_operand:V2DF 2 "nonimmediate_operand" ""))
4600 (parallel [(const_int 0)
4603 "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
4605 (define_insn "*avx_unpcklpd"
4606 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o")
4609 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0")
4610 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x"))
4611 (parallel [(const_int 0)
4613 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4615 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
4616 vmovhpd\t{%2, %1, %0|%0, %1, %2}
4617 vmovlpd\t{%2, %H0|%H0, %2}"
4618 [(set_attr "type" "sselog,ssemov,ssemov")
4619 (set_attr "prefix" "vex")
4620 (set_attr "mode" "V2DF,V1DF,V1DF")])
4622 (define_insn "sse2_unpcklpd"
4623 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o")
4626 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0")
4627 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x"))
4628 (parallel [(const_int 0)
4630 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4632 unpcklpd\t{%2, %0|%0, %2}
4633 movhpd\t{%2, %0|%0, %2}
4634 movlpd\t{%2, %H0|%H0, %2}"
4635 [(set_attr "type" "sselog,ssemov,ssemov")
4636 (set_attr "prefix_data16" "*,1,1")
4637 (set_attr "mode" "V2DF,V1DF,V1DF")])
4639 (define_expand "avx_shufpd256"
4640 [(match_operand:V4DF 0 "register_operand" "")
4641 (match_operand:V4DF 1 "register_operand" "")
4642 (match_operand:V4DF 2 "nonimmediate_operand" "")
4643 (match_operand:SI 3 "const_int_operand" "")]
4646 int mask = INTVAL (operands[3]);
4647 emit_insn (gen_avx_shufpd256_1 (operands[0], operands[1], operands[2],
4649 GEN_INT (mask & 2 ? 5 : 4),
4650 GEN_INT (mask & 4 ? 3 : 2),
4651 GEN_INT (mask & 8 ? 7 : 6)));
4655 (define_insn "avx_shufpd256_1"
4656 [(set (match_operand:V4DF 0 "register_operand" "=x")
4659 (match_operand:V4DF 1 "register_operand" "x")
4660 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
4661 (parallel [(match_operand 3 "const_0_to_1_operand" "")
4662 (match_operand 4 "const_4_to_5_operand" "")
4663 (match_operand 5 "const_2_to_3_operand" "")
4664 (match_operand 6 "const_6_to_7_operand" "")])))]
4668 mask = INTVAL (operands[3]);
4669 mask |= (INTVAL (operands[4]) - 4) << 1;
4670 mask |= (INTVAL (operands[5]) - 2) << 2;
4671 mask |= (INTVAL (operands[6]) - 6) << 3;
4672 operands[3] = GEN_INT (mask);
4674 return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
4676 [(set_attr "type" "sselog")
4677 (set_attr "length_immediate" "1")
4678 (set_attr "prefix" "vex")
4679 (set_attr "mode" "V4DF")])
4681 (define_expand "sse2_shufpd"
4682 [(match_operand:V2DF 0 "register_operand" "")
4683 (match_operand:V2DF 1 "register_operand" "")
4684 (match_operand:V2DF 2 "nonimmediate_operand" "")
4685 (match_operand:SI 3 "const_int_operand" "")]
4688 int mask = INTVAL (operands[3]);
4689 emit_insn (gen_sse2_shufpd_v2df (operands[0], operands[1], operands[2],
4691 GEN_INT (mask & 2 ? 3 : 2)));
4695 (define_expand "vec_extract_even<mode>"
4696 [(set (match_operand:SSEMODE4S 0 "register_operand" "")
4697 (vec_select:SSEMODE4S
4698 (vec_concat:<ssedoublesizemode>
4699 (match_operand:SSEMODE4S 1 "register_operand" "")
4700 (match_operand:SSEMODE4S 2 "nonimmediate_operand" ""))
4701 (parallel [(const_int 0)
4707 (define_expand "vec_extract_odd<mode>"
4708 [(set (match_operand:SSEMODE4S 0 "register_operand" "")
4709 (vec_select:SSEMODE4S
4710 (vec_concat:<ssedoublesizemode>
4711 (match_operand:SSEMODE4S 1 "register_operand" "")
4712 (match_operand:SSEMODE4S 2 "nonimmediate_operand" ""))
4713 (parallel [(const_int 1)
4719 (define_expand "vec_extract_even<mode>"
4720 [(set (match_operand:SSEMODE2D 0 "register_operand" "")
4721 (vec_select:SSEMODE2D
4722 (vec_concat:<ssedoublesizemode>
4723 (match_operand:SSEMODE2D 1 "register_operand" "")
4724 (match_operand:SSEMODE2D 2 "nonimmediate_operand" ""))
4725 (parallel [(const_int 0)
4729 (define_expand "vec_extract_odd<mode>"
4730 [(set (match_operand:SSEMODE2D 0 "register_operand" "")
4731 (vec_select:SSEMODE2D
4732 (vec_concat:<ssedoublesizemode>
4733 (match_operand:SSEMODE2D 1 "register_operand" "")
4734 (match_operand:SSEMODE2D 2 "nonimmediate_operand" ""))
4735 (parallel [(const_int 1)
4739 ;; punpcklqdq and punpckhqdq are shorter than shufpd.
4740 (define_insn "*avx_punpckhqdq"
4741 [(set (match_operand:V2DI 0 "register_operand" "=x")
4744 (match_operand:V2DI 1 "register_operand" "x")
4745 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
4746 (parallel [(const_int 1)
4749 "vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}"
4750 [(set_attr "type" "sselog")
4751 (set_attr "prefix" "vex")
4752 (set_attr "mode" "TI")])
4754 (define_insn "sse2_punpckhqdq"
4755 [(set (match_operand:V2DI 0 "register_operand" "=x")
4758 (match_operand:V2DI 1 "register_operand" "0")
4759 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
4760 (parallel [(const_int 1)
4763 "punpckhqdq\t{%2, %0|%0, %2}"
4764 [(set_attr "type" "sselog")
4765 (set_attr "prefix_data16" "1")
4766 (set_attr "mode" "TI")])
4768 (define_insn "*avx_punpcklqdq"
4769 [(set (match_operand:V2DI 0 "register_operand" "=x")
4772 (match_operand:V2DI 1 "register_operand" "x")
4773 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
4774 (parallel [(const_int 0)
4777 "vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}"
4778 [(set_attr "type" "sselog")
4779 (set_attr "prefix" "vex")
4780 (set_attr "mode" "TI")])
4782 (define_insn "sse2_punpcklqdq"
4783 [(set (match_operand:V2DI 0 "register_operand" "=x")
4786 (match_operand:V2DI 1 "register_operand" "0")
4787 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
4788 (parallel [(const_int 0)
4791 "punpcklqdq\t{%2, %0|%0, %2}"
4792 [(set_attr "type" "sselog")
4793 (set_attr "prefix_data16" "1")
4794 (set_attr "mode" "TI")])
4796 (define_insn "*avx_shufpd_<mode>"
4797 [(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
4798 (vec_select:SSEMODE2D
4799 (vec_concat:<ssedoublesizemode>
4800 (match_operand:SSEMODE2D 1 "register_operand" "x")
4801 (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
4802 (parallel [(match_operand 3 "const_0_to_1_operand" "")
4803 (match_operand 4 "const_2_to_3_operand" "")])))]
4807 mask = INTVAL (operands[3]);
4808 mask |= (INTVAL (operands[4]) - 2) << 1;
4809 operands[3] = GEN_INT (mask);
4811 return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
4813 [(set_attr "type" "sselog")
4814 (set_attr "length_immediate" "1")
4815 (set_attr "prefix" "vex")
4816 (set_attr "mode" "V2DF")])
4818 (define_insn "sse2_shufpd_<mode>"
4819 [(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
4820 (vec_select:SSEMODE2D
4821 (vec_concat:<ssedoublesizemode>
4822 (match_operand:SSEMODE2D 1 "register_operand" "0")
4823 (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
4824 (parallel [(match_operand 3 "const_0_to_1_operand" "")
4825 (match_operand 4 "const_2_to_3_operand" "")])))]
4829 mask = INTVAL (operands[3]);
4830 mask |= (INTVAL (operands[4]) - 2) << 1;
4831 operands[3] = GEN_INT (mask);
4833 return "shufpd\t{%3, %2, %0|%0, %2, %3}";
4835 [(set_attr "type" "sselog")
4836 (set_attr "length_immediate" "1")
4837 (set_attr "mode" "V2DF")])
4839 ;; Avoid combining registers from different units in a single alternative,
4840 ;; see comment above inline_secondary_memory_needed function in i386.c
4841 (define_insn "*avx_storehpd"
4842 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
4844 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,o,o,o")
4845 (parallel [(const_int 1)])))]
4846 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4848 vmovhpd\t{%1, %0|%0, %1}
4849 vunpckhpd\t{%1, %1, %0|%0, %1, %1}
4853 [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
4854 (set_attr "prefix" "vex")
4855 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
4857 (define_insn "sse2_storehpd"
4858 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
4860 (match_operand:V2DF 1 "nonimmediate_operand" " x,0,o,o,o")
4861 (parallel [(const_int 1)])))]
4862 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4864 movhpd\t{%1, %0|%0, %1}
4869 [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
4870 (set_attr "prefix_data16" "1,*,*,*,*")
4871 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
4874 [(set (match_operand:DF 0 "register_operand" "")
4876 (match_operand:V2DF 1 "memory_operand" "")
4877 (parallel [(const_int 1)])))]
4878 "TARGET_SSE2 && reload_completed"
4879 [(set (match_dup 0) (match_dup 1))]
4881 operands[1] = adjust_address (operands[1], DFmode, 8);
4884 ;; Avoid combining registers from different units in a single alternative,
4885 ;; see comment above inline_secondary_memory_needed function in i386.c
4886 (define_insn "sse2_storelpd"
4887 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
4889 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,m,m,m")
4890 (parallel [(const_int 0)])))]
4891 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4893 %vmovlpd\t{%1, %0|%0, %1}
4898 [(set_attr "type" "ssemov,ssemov,ssemov,fmov,imov")
4899 (set_attr "prefix_data16" "1,*,*,*,*")
4900 (set_attr "prefix" "maybe_vex")
4901 (set_attr "mode" "V1DF,DF,DF,DF,DF")])
4904 [(set (match_operand:DF 0 "register_operand" "")
4906 (match_operand:V2DF 1 "nonimmediate_operand" "")
4907 (parallel [(const_int 0)])))]
4908 "TARGET_SSE2 && reload_completed"
4911 rtx op1 = operands[1];
4913 op1 = gen_rtx_REG (DFmode, REGNO (op1));
4915 op1 = gen_lowpart (DFmode, op1);
4916 emit_move_insn (operands[0], op1);
4920 (define_expand "sse2_loadhpd_exp"
4921 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
4924 (match_operand:V2DF 1 "nonimmediate_operand" "")
4925 (parallel [(const_int 0)]))
4926 (match_operand:DF 2 "nonimmediate_operand" "")))]
4928 "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
4930 ;; Avoid combining registers from different units in a single alternative,
4931 ;; see comment above inline_secondary_memory_needed function in i386.c
4932 (define_insn "*avx_loadhpd"
4933 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o,o,o")
4936 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,0,0")
4937 (parallel [(const_int 0)]))
4938 (match_operand:DF 2 "nonimmediate_operand" " m,x,x,*f,r")))]
4939 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4941 vmovhpd\t{%2, %1, %0|%0, %1, %2}
4942 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
4946 [(set_attr "type" "ssemov,sselog,ssemov,fmov,imov")
4947 (set_attr "prefix" "vex")
4948 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
4950 (define_insn "sse2_loadhpd"
4951 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o,o,o")
4954 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,x,0,0,0")
4955 (parallel [(const_int 0)]))
4956 (match_operand:DF 2 "nonimmediate_operand" " m,x,0,x,*f,r")))]
4957 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4959 movhpd\t{%2, %0|%0, %2}
4960 unpcklpd\t{%2, %0|%0, %2}
4961 shufpd\t{$1, %1, %0|%0, %1, 1}
4965 [(set_attr "type" "ssemov,sselog,sselog,ssemov,fmov,imov")
4966 (set_attr "prefix_data16" "1,*,*,*,*,*")
4967 (set_attr "length_immediate" "*,*,1,*,*,*")
4968 (set_attr "mode" "V1DF,V2DF,V2DF,DF,DF,DF")])
4971 [(set (match_operand:V2DF 0 "memory_operand" "")
4973 (vec_select:DF (match_dup 0) (parallel [(const_int 0)]))
4974 (match_operand:DF 1 "register_operand" "")))]
4975 "TARGET_SSE2 && reload_completed"
4976 [(set (match_dup 0) (match_dup 1))]
4978 operands[0] = adjust_address (operands[0], DFmode, 8);
4981 (define_expand "sse2_loadlpd_exp"
4982 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
4984 (match_operand:DF 2 "nonimmediate_operand" "")
4986 (match_operand:V2DF 1 "nonimmediate_operand" "")
4987 (parallel [(const_int 1)]))))]
4989 "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
4991 ;; Avoid combining registers from different units in a single alternative,
4992 ;; see comment above inline_secondary_memory_needed function in i386.c
4993 (define_insn "*avx_loadlpd"
4994 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,m,m")
4996 (match_operand:DF 2 "nonimmediate_operand" " m,m,x,x,x,*f,r")
4998 (match_operand:V2DF 1 "vector_move_operand" " C,x,x,o,0,0,0")
4999 (parallel [(const_int 1)]))))]
5000 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
5002 vmovsd\t{%2, %0|%0, %2}
5003 vmovlpd\t{%2, %1, %0|%0, %1, %2}
5004 vmovsd\t{%2, %1, %0|%0, %1, %2}
5005 vmovhpd\t{%H1, %2, %0|%0, %2, %H1}
5009 [(set_attr "type" "ssemov,ssemov,ssemov,ssemov,ssemov,fmov,imov")
5010 (set_attr "prefix" "vex")
5011 (set_attr "mode" "DF,V1DF,V1DF,V1DF,DF,DF,DF")])
5013 (define_insn "sse2_loadlpd"
5014 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,m,m,m")
5016 (match_operand:DF 2 "nonimmediate_operand" " m,m,x,0,0,x,*f,r")
5018 (match_operand:V2DF 1 "vector_move_operand" " C,0,0,x,o,0,0,0")
5019 (parallel [(const_int 1)]))))]
5020 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
5022 movsd\t{%2, %0|%0, %2}
5023 movlpd\t{%2, %0|%0, %2}
5024 movsd\t{%2, %0|%0, %2}
5025 shufpd\t{$2, %2, %0|%0, %2, 2}
5026 movhpd\t{%H1, %0|%0, %H1}
5030 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,fmov,imov")
5031 (set_attr "prefix_data16" "*,1,*,*,1,*,*,*")
5032 (set_attr "length_immediate" "*,*,*,1,*,*,*,*")
5033 (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,DF,DF,DF")])
5036 [(set (match_operand:V2DF 0 "memory_operand" "")
5038 (match_operand:DF 1 "register_operand" "")
5039 (vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))]
5040 "TARGET_SSE2 && reload_completed"
5041 [(set (match_dup 0) (match_dup 1))]
5043 operands[0] = adjust_address (operands[0], DFmode, 8);
5046 ;; Not sure these two are ever used, but it doesn't hurt to have
5048 (define_insn "*vec_extractv2df_1_sse"
5049 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
5051 (match_operand:V2DF 1 "nonimmediate_operand" "x,x,o")
5052 (parallel [(const_int 1)])))]
5053 "!TARGET_SSE2 && TARGET_SSE
5054 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5056 movhps\t{%1, %0|%0, %1}
5057 movhlps\t{%1, %0|%0, %1}
5058 movlps\t{%H1, %0|%0, %H1}"
5059 [(set_attr "type" "ssemov")
5060 (set_attr "mode" "V2SF,V4SF,V2SF")])
5062 (define_insn "*vec_extractv2df_0_sse"
5063 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
5065 (match_operand:V2DF 1 "nonimmediate_operand" "x,x,m")
5066 (parallel [(const_int 0)])))]
5067 "!TARGET_SSE2 && TARGET_SSE
5068 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
5070 movlps\t{%1, %0|%0, %1}
5071 movaps\t{%1, %0|%0, %1}
5072 movlps\t{%1, %0|%0, %1}"
5073 [(set_attr "type" "ssemov")
5074 (set_attr "mode" "V2SF,V4SF,V2SF")])
5076 (define_insn "*avx_movsd"
5077 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,o")
5079 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,x,0")
5080 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,o,x")
5084 vmovsd\t{%2, %1, %0|%0, %1, %2}
5085 vmovlpd\t{%2, %1, %0|%0, %1, %2}
5086 vmovlpd\t{%2, %0|%0, %2}
5087 vmovhps\t{%H1, %2, %0|%0, %2, %H1}
5088 vmovhps\t{%1, %H0|%H0, %1}"
5089 [(set_attr "type" "ssemov,ssemov,ssemov,ssemov,ssemov")
5090 (set_attr "prefix" "vex")
5091 (set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF")])
5093 (define_insn "sse2_movsd"
5094 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,x,o")
5096 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,0,0,0")
5097 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0,x,o,x")
5101 movsd\t{%2, %0|%0, %2}
5102 movlpd\t{%2, %0|%0, %2}
5103 movlpd\t{%2, %0|%0, %2}
5104 shufpd\t{$2, %2, %0|%0, %2, 2}
5105 movhps\t{%H1, %0|%0, %H1}
5106 movhps\t{%1, %H0|%H0, %1}"
5107 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
5108 (set_attr "prefix_data16" "*,1,1,*,*,*")
5109 (set_attr "length_immediate" "*,*,*,1,*,*")
5110 (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,V1DF")])
5112 (define_insn "*vec_dupv2df_sse3"
5113 [(set (match_operand:V2DF 0 "register_operand" "=x")
5115 (match_operand:DF 1 "nonimmediate_operand" "xm")))]
5117 "%vmovddup\t{%1, %0|%0, %1}"
5118 [(set_attr "type" "sselog1")
5119 (set_attr "prefix" "maybe_vex")
5120 (set_attr "mode" "DF")])
5122 (define_insn "vec_dupv2df"
5123 [(set (match_operand:V2DF 0 "register_operand" "=x")
5125 (match_operand:DF 1 "register_operand" "0")))]
5128 [(set_attr "type" "sselog1")
5129 (set_attr "mode" "V2DF")])
5131 (define_insn "*vec_concatv2df_sse3"
5132 [(set (match_operand:V2DF 0 "register_operand" "=x")
5134 (match_operand:DF 1 "nonimmediate_operand" "xm")
5137 "%vmovddup\t{%1, %0|%0, %1}"
5138 [(set_attr "type" "sselog1")
5139 (set_attr "prefix" "maybe_vex")
5140 (set_attr "mode" "DF")])
5142 (define_insn "*vec_concatv2df_avx"
5143 [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
5145 (match_operand:DF 1 "nonimmediate_operand" " x,x,m")
5146 (match_operand:DF 2 "vector_move_operand" " x,m,C")))]
5149 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
5150 vmovhpd\t{%2, %1, %0|%0, %1, %2}
5151 vmovsd\t{%1, %0|%0, %1}"
5152 [(set_attr "type" "ssemov")
5153 (set_attr "prefix" "vex")
5154 (set_attr "mode" "DF,V1DF,DF")])
5156 (define_insn "*vec_concatv2df"
5157 [(set (match_operand:V2DF 0 "register_operand" "=Y2,Y2,Y2,x,x")
5159 (match_operand:DF 1 "nonimmediate_operand" " 0 ,0 ,m ,0,0")
5160 (match_operand:DF 2 "vector_move_operand" " Y2,m ,C ,x,m")))]
5163 unpcklpd\t{%2, %0|%0, %2}
5164 movhpd\t{%2, %0|%0, %2}
5165 movsd\t{%1, %0|%0, %1}
5166 movlhps\t{%2, %0|%0, %2}
5167 movhps\t{%2, %0|%0, %2}"
5168 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
5169 (set_attr "prefix_data16" "*,1,*,*,*")
5170 (set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
5172 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5174 ;; Parallel integral arithmetic
5176 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5178 (define_expand "neg<mode>2"
5179 [(set (match_operand:SSEMODEI 0 "register_operand" "")
5182 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")))]
5184 "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
5186 (define_expand "<plusminus_insn><mode>3"
5187 [(set (match_operand:SSEMODEI 0 "register_operand" "")
5189 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
5190 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
5192 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
5194 (define_insn "*avx_<plusminus_insn><mode>3"
5195 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
5197 (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>x")
5198 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
5199 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5200 "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5201 [(set_attr "type" "sseiadd")
5202 (set_attr "prefix" "vex")
5203 (set_attr "mode" "TI")])
5205 (define_insn "*<plusminus_insn><mode>3"
5206 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
5208 (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>0")
5209 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
5210 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5211 "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
5212 [(set_attr "type" "sseiadd")
5213 (set_attr "prefix_data16" "1")
5214 (set_attr "mode" "TI")])
5216 (define_expand "sse2_<plusminus_insn><mode>3"
5217 [(set (match_operand:SSEMODE12 0 "register_operand" "")
5218 (sat_plusminus:SSEMODE12
5219 (match_operand:SSEMODE12 1 "nonimmediate_operand" "")
5220 (match_operand:SSEMODE12 2 "nonimmediate_operand" "")))]
5222 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
5224 (define_insn "*avx_<plusminus_insn><mode>3"
5225 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
5226 (sat_plusminus:SSEMODE12
5227 (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>x")
5228 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
5229 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5230 "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5231 [(set_attr "type" "sseiadd")
5232 (set_attr "prefix" "vex")
5233 (set_attr "mode" "TI")])
5235 (define_insn "*sse2_<plusminus_insn><mode>3"
5236 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
5237 (sat_plusminus:SSEMODE12
5238 (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>0")
5239 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
5240 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5241 "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
5242 [(set_attr "type" "sseiadd")
5243 (set_attr "prefix_data16" "1")
5244 (set_attr "mode" "TI")])
5246 (define_insn_and_split "mulv16qi3"
5247 [(set (match_operand:V16QI 0 "register_operand" "")
5248 (mult:V16QI (match_operand:V16QI 1 "register_operand" "")
5249 (match_operand:V16QI 2 "register_operand" "")))]
5251 && can_create_pseudo_p ()"
5259 for (i = 0; i < 12; ++i)
5260 t[i] = gen_reg_rtx (V16QImode);
5262 /* Unpack data such that we've got a source byte in each low byte of
5263 each word. We don't care what goes into the high byte of each word.
5264 Rather than trying to get zero in there, most convenient is to let
5265 it be a copy of the low byte. */
5266 emit_insn (gen_sse2_punpckhbw (t[0], operands[1], operands[1]));
5267 emit_insn (gen_sse2_punpckhbw (t[1], operands[2], operands[2]));
5268 emit_insn (gen_sse2_punpcklbw (t[2], operands[1], operands[1]));
5269 emit_insn (gen_sse2_punpcklbw (t[3], operands[2], operands[2]));
5271 /* Multiply words. The end-of-line annotations here give a picture of what
5272 the output of that instruction looks like. Dot means don't care; the
5273 letters are the bytes of the result with A being the most significant. */
5274 emit_insn (gen_mulv8hi3 (gen_lowpart (V8HImode, t[4]), /* .A.B.C.D.E.F.G.H */
5275 gen_lowpart (V8HImode, t[0]),
5276 gen_lowpart (V8HImode, t[1])));
5277 emit_insn (gen_mulv8hi3 (gen_lowpart (V8HImode, t[5]), /* .I.J.K.L.M.N.O.P */
5278 gen_lowpart (V8HImode, t[2]),
5279 gen_lowpart (V8HImode, t[3])));
5281 /* Extract the relevant bytes and merge them back together. */
5282 emit_insn (gen_sse2_punpckhbw (t[6], t[5], t[4])); /* ..AI..BJ..CK..DL */
5283 emit_insn (gen_sse2_punpcklbw (t[7], t[5], t[4])); /* ..EM..FN..GO..HP */
5284 emit_insn (gen_sse2_punpckhbw (t[8], t[7], t[6])); /* ....AEIM....BFJN */
5285 emit_insn (gen_sse2_punpcklbw (t[9], t[7], t[6])); /* ....CGKO....DHLP */
5286 emit_insn (gen_sse2_punpckhbw (t[10], t[9], t[8])); /* ........ACEGIKMO */
5287 emit_insn (gen_sse2_punpcklbw (t[11], t[9], t[8])); /* ........BDFHJLNP */
5289 emit_insn (gen_sse2_punpcklbw (operands[0], t[11], t[10])); /* ABCDEFGHIJKLMNOP */
5293 (define_expand "mulv8hi3"
5294 [(set (match_operand:V8HI 0 "register_operand" "")
5295 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
5296 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
5298 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
5300 (define_insn "*avx_mulv8hi3"
5301 [(set (match_operand:V8HI 0 "register_operand" "=x")
5302 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x")
5303 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
5304 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5305 "vpmullw\t{%2, %1, %0|%0, %1, %2}"
5306 [(set_attr "type" "sseimul")
5307 (set_attr "prefix" "vex")
5308 (set_attr "mode" "TI")])
5310 (define_insn "*mulv8hi3"
5311 [(set (match_operand:V8HI 0 "register_operand" "=x")
5312 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
5313 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
5314 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5315 "pmullw\t{%2, %0|%0, %2}"
5316 [(set_attr "type" "sseimul")
5317 (set_attr "prefix_data16" "1")
5318 (set_attr "mode" "TI")])
5320 (define_expand "smulv8hi3_highpart"
5321 [(set (match_operand:V8HI 0 "register_operand" "")
5326 (match_operand:V8HI 1 "nonimmediate_operand" ""))
5328 (match_operand:V8HI 2 "nonimmediate_operand" "")))
5331 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
5333 (define_insn "*avxv8hi3_highpart"
5334 [(set (match_operand:V8HI 0 "register_operand" "=x")
5339 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
5341 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
5343 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5344 "vpmulhw\t{%2, %1, %0|%0, %1, %2}"
5345 [(set_attr "type" "sseimul")
5346 (set_attr "prefix" "vex")
5347 (set_attr "mode" "TI")])
5349 (define_insn "*smulv8hi3_highpart"
5350 [(set (match_operand:V8HI 0 "register_operand" "=x")
5355 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
5357 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
5359 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5360 "pmulhw\t{%2, %0|%0, %2}"
5361 [(set_attr "type" "sseimul")
5362 (set_attr "prefix_data16" "1")
5363 (set_attr "mode" "TI")])
5365 (define_expand "umulv8hi3_highpart"
5366 [(set (match_operand:V8HI 0 "register_operand" "")
5371 (match_operand:V8HI 1 "nonimmediate_operand" ""))
5373 (match_operand:V8HI 2 "nonimmediate_operand" "")))
5376 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
5378 (define_insn "*avx_umulv8hi3_highpart"
5379 [(set (match_operand:V8HI 0 "register_operand" "=x")
5384 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
5386 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
5388 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5389 "vpmulhuw\t{%2, %1, %0|%0, %1, %2}"
5390 [(set_attr "type" "sseimul")
5391 (set_attr "prefix" "vex")
5392 (set_attr "mode" "TI")])
5394 (define_insn "*umulv8hi3_highpart"
5395 [(set (match_operand:V8HI 0 "register_operand" "=x")
5400 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
5402 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
5404 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5405 "pmulhuw\t{%2, %0|%0, %2}"
5406 [(set_attr "type" "sseimul")
5407 (set_attr "prefix_data16" "1")
5408 (set_attr "mode" "TI")])
5410 (define_expand "sse2_umulv2siv2di3"
5411 [(set (match_operand:V2DI 0 "register_operand" "")
5415 (match_operand:V4SI 1 "nonimmediate_operand" "")
5416 (parallel [(const_int 0) (const_int 2)])))
5419 (match_operand:V4SI 2 "nonimmediate_operand" "")
5420 (parallel [(const_int 0) (const_int 2)])))))]
5422 "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
5424 (define_insn "*avx_umulv2siv2di3"
5425 [(set (match_operand:V2DI 0 "register_operand" "=x")
5429 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
5430 (parallel [(const_int 0) (const_int 2)])))
5433 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
5434 (parallel [(const_int 0) (const_int 2)])))))]
5435 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5436 "vpmuludq\t{%2, %1, %0|%0, %1, %2}"
5437 [(set_attr "type" "sseimul")
5438 (set_attr "prefix" "vex")
5439 (set_attr "mode" "TI")])
5441 (define_insn "*sse2_umulv2siv2di3"
5442 [(set (match_operand:V2DI 0 "register_operand" "=x")
5446 (match_operand:V4SI 1 "nonimmediate_operand" "%0")
5447 (parallel [(const_int 0) (const_int 2)])))
5450 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
5451 (parallel [(const_int 0) (const_int 2)])))))]
5452 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5453 "pmuludq\t{%2, %0|%0, %2}"
5454 [(set_attr "type" "sseimul")
5455 (set_attr "prefix_data16" "1")
5456 (set_attr "mode" "TI")])
5458 (define_expand "sse4_1_mulv2siv2di3"
5459 [(set (match_operand:V2DI 0 "register_operand" "")
5463 (match_operand:V4SI 1 "nonimmediate_operand" "")
5464 (parallel [(const_int 0) (const_int 2)])))
5467 (match_operand:V4SI 2 "nonimmediate_operand" "")
5468 (parallel [(const_int 0) (const_int 2)])))))]
5470 "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
5472 (define_insn "*avx_mulv2siv2di3"
5473 [(set (match_operand:V2DI 0 "register_operand" "=x")
5477 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
5478 (parallel [(const_int 0) (const_int 2)])))
5481 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
5482 (parallel [(const_int 0) (const_int 2)])))))]
5483 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5484 "vpmuldq\t{%2, %1, %0|%0, %1, %2}"
5485 [(set_attr "type" "sseimul")
5486 (set_attr "prefix_extra" "1")
5487 (set_attr "prefix" "vex")
5488 (set_attr "mode" "TI")])
5490 (define_insn "*sse4_1_mulv2siv2di3"
5491 [(set (match_operand:V2DI 0 "register_operand" "=x")
5495 (match_operand:V4SI 1 "nonimmediate_operand" "%0")
5496 (parallel [(const_int 0) (const_int 2)])))
5499 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
5500 (parallel [(const_int 0) (const_int 2)])))))]
5501 "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5502 "pmuldq\t{%2, %0|%0, %2}"
5503 [(set_attr "type" "sseimul")
5504 (set_attr "prefix_extra" "1")
5505 (set_attr "mode" "TI")])
5507 (define_expand "sse2_pmaddwd"
5508 [(set (match_operand:V4SI 0 "register_operand" "")
5513 (match_operand:V8HI 1 "nonimmediate_operand" "")
5514 (parallel [(const_int 0)
5520 (match_operand:V8HI 2 "nonimmediate_operand" "")
5521 (parallel [(const_int 0)
5527 (vec_select:V4HI (match_dup 1)
5528 (parallel [(const_int 1)
5533 (vec_select:V4HI (match_dup 2)
5534 (parallel [(const_int 1)
5537 (const_int 7)]))))))]
5539 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
5541 (define_insn "*avx_pmaddwd"
5542 [(set (match_operand:V4SI 0 "register_operand" "=x")
5547 (match_operand:V8HI 1 "nonimmediate_operand" "%x")
5548 (parallel [(const_int 0)
5554 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
5555 (parallel [(const_int 0)
5561 (vec_select:V4HI (match_dup 1)
5562 (parallel [(const_int 1)
5567 (vec_select:V4HI (match_dup 2)
5568 (parallel [(const_int 1)
5571 (const_int 7)]))))))]
5572 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5573 "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
5574 [(set_attr "type" "sseiadd")
5575 (set_attr "prefix" "vex")
5576 (set_attr "mode" "TI")])
5578 (define_insn "*sse2_pmaddwd"
5579 [(set (match_operand:V4SI 0 "register_operand" "=x")
5584 (match_operand:V8HI 1 "nonimmediate_operand" "%0")
5585 (parallel [(const_int 0)
5591 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
5592 (parallel [(const_int 0)
5598 (vec_select:V4HI (match_dup 1)
5599 (parallel [(const_int 1)
5604 (vec_select:V4HI (match_dup 2)
5605 (parallel [(const_int 1)
5608 (const_int 7)]))))))]
5609 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
5610 "pmaddwd\t{%2, %0|%0, %2}"
5611 [(set_attr "type" "sseiadd")
5612 (set_attr "atom_unit" "simul")
5613 (set_attr "prefix_data16" "1")
5614 (set_attr "mode" "TI")])
5616 (define_expand "mulv4si3"
5617 [(set (match_operand:V4SI 0 "register_operand" "")
5618 (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
5619 (match_operand:V4SI 2 "register_operand" "")))]
5622 if (TARGET_SSE4_1 || TARGET_XOP)
5623 ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);
5626 (define_insn "*avx_mulv4si3"
5627 [(set (match_operand:V4SI 0 "register_operand" "=x")
5628 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x")
5629 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
5630 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5631 "vpmulld\t{%2, %1, %0|%0, %1, %2}"
5632 [(set_attr "type" "sseimul")
5633 (set_attr "prefix_extra" "1")
5634 (set_attr "prefix" "vex")
5635 (set_attr "mode" "TI")])
5637 (define_insn "*sse4_1_mulv4si3"
5638 [(set (match_operand:V4SI 0 "register_operand" "=x")
5639 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%0")
5640 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
5641 "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
5642 "pmulld\t{%2, %0|%0, %2}"
5643 [(set_attr "type" "sseimul")
5644 (set_attr "prefix_extra" "1")
5645 (set_attr "mode" "TI")])
5647 (define_insn_and_split "*sse2_mulv4si3"
5648 [(set (match_operand:V4SI 0 "register_operand" "")
5649 (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
5650 (match_operand:V4SI 2 "register_operand" "")))]
5651 "TARGET_SSE2 && !TARGET_SSE4_1 && !TARGET_XOP
5652 && can_create_pseudo_p ()"
5657 rtx t1, t2, t3, t4, t5, t6, thirtytwo;
5663 t1 = gen_reg_rtx (V4SImode);
5664 t2 = gen_reg_rtx (V4SImode);
5665 t3 = gen_reg_rtx (V4SImode);
5666 t4 = gen_reg_rtx (V4SImode);
5667 t5 = gen_reg_rtx (V4SImode);
5668 t6 = gen_reg_rtx (V4SImode);
5669 thirtytwo = GEN_INT (32);
5671 /* Multiply elements 2 and 0. */
5672 emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t1),
5675 /* Shift both input vectors down one element, so that elements 3
5676 and 1 are now in the slots for elements 2 and 0. For K8, at
5677 least, this is faster than using a shuffle. */
5678 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t2),
5679 gen_lowpart (TImode, op1),
5681 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t3),
5682 gen_lowpart (TImode, op2),
5684 /* Multiply elements 3 and 1. */
5685 emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t4),
5688 /* Move the results in element 2 down to element 1; we don't care
5689 what goes in elements 2 and 3. */
5690 emit_insn (gen_sse2_pshufd_1 (t5, t1, const0_rtx, const2_rtx,
5691 const0_rtx, const0_rtx));
5692 emit_insn (gen_sse2_pshufd_1 (t6, t4, const0_rtx, const2_rtx,
5693 const0_rtx, const0_rtx));
5695 /* Merge the parts back together. */
5696 emit_insn (gen_sse2_punpckldq (op0, t5, t6));
5700 (define_insn_and_split "mulv2di3"
5701 [(set (match_operand:V2DI 0 "register_operand" "")
5702 (mult:V2DI (match_operand:V2DI 1 "register_operand" "")
5703 (match_operand:V2DI 2 "register_operand" "")))]
5705 && can_create_pseudo_p ()"
5710 rtx t1, t2, t3, t4, t5, t6, thirtytwo;
5715 /* op1: A,B,C,D, op2: E,F,G,H */
5717 op1 = gen_lowpart (V4SImode, operands[1]);
5718 op2 = gen_lowpart (V4SImode, operands[2]);
5719 t1 = gen_reg_rtx (V4SImode);
5720 t2 = gen_reg_rtx (V4SImode);
5721 t3 = gen_reg_rtx (V4SImode);
5722 t4 = gen_reg_rtx (V2DImode);
5723 t5 = gen_reg_rtx (V2DImode);
5726 emit_insn (gen_sse2_pshufd_1 (t1, op1,
5733 emit_move_insn (t2, CONST0_RTX (V4SImode));
5735 /* t3: (B*E),(A*F),(D*G),(C*H) */
5736 emit_insn (gen_xop_pmacsdd (t3, t1, op2, t2));
5738 /* t4: (B*E)+(A*F), (D*G)+(C*H) */
5739 emit_insn (gen_xop_phadddq (t4, t3));
5741 /* t5: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
5742 emit_insn (gen_ashlv2di3 (t5, t4, GEN_INT (32)));
5744 /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
5745 emit_insn (gen_xop_pmacsdql (op0, op1, op2, t5));
5752 t1 = gen_reg_rtx (V2DImode);
5753 t2 = gen_reg_rtx (V2DImode);
5754 t3 = gen_reg_rtx (V2DImode);
5755 t4 = gen_reg_rtx (V2DImode);
5756 t5 = gen_reg_rtx (V2DImode);
5757 t6 = gen_reg_rtx (V2DImode);
5758 thirtytwo = GEN_INT (32);
5760 /* Multiply low parts. */
5761 emit_insn (gen_sse2_umulv2siv2di3 (t1, gen_lowpart (V4SImode, op1),
5762 gen_lowpart (V4SImode, op2)));
5764 /* Shift input vectors left 32 bits so we can multiply high parts. */
5765 emit_insn (gen_lshrv2di3 (t2, op1, thirtytwo));
5766 emit_insn (gen_lshrv2di3 (t3, op2, thirtytwo));
5768 /* Multiply high parts by low parts. */
5769 emit_insn (gen_sse2_umulv2siv2di3 (t4, gen_lowpart (V4SImode, op1),
5770 gen_lowpart (V4SImode, t3)));
5771 emit_insn (gen_sse2_umulv2siv2di3 (t5, gen_lowpart (V4SImode, op2),
5772 gen_lowpart (V4SImode, t2)));
5774 /* Shift them back. */
5775 emit_insn (gen_ashlv2di3 (t4, t4, thirtytwo));
5776 emit_insn (gen_ashlv2di3 (t5, t5, thirtytwo));
5778 /* Add the three parts together. */
5779 emit_insn (gen_addv2di3 (t6, t1, t4));
5780 emit_insn (gen_addv2di3 (op0, t6, t5));
5784 (define_expand "vec_widen_smult_hi_v8hi"
5785 [(match_operand:V4SI 0 "register_operand" "")
5786 (match_operand:V8HI 1 "register_operand" "")
5787 (match_operand:V8HI 2 "register_operand" "")]
5790 rtx op1, op2, t1, t2, dest;
5794 t1 = gen_reg_rtx (V8HImode);
5795 t2 = gen_reg_rtx (V8HImode);
5796 dest = gen_lowpart (V8HImode, operands[0]);
5798 emit_insn (gen_mulv8hi3 (t1, op1, op2));
5799 emit_insn (gen_smulv8hi3_highpart (t2, op1, op2));
5800 emit_insn (gen_vec_interleave_highv8hi (dest, t1, t2));
5804 (define_expand "vec_widen_smult_lo_v8hi"
5805 [(match_operand:V4SI 0 "register_operand" "")
5806 (match_operand:V8HI 1 "register_operand" "")
5807 (match_operand:V8HI 2 "register_operand" "")]
5810 rtx op1, op2, t1, t2, dest;
5814 t1 = gen_reg_rtx (V8HImode);
5815 t2 = gen_reg_rtx (V8HImode);
5816 dest = gen_lowpart (V8HImode, operands[0]);
5818 emit_insn (gen_mulv8hi3 (t1, op1, op2));
5819 emit_insn (gen_smulv8hi3_highpart (t2, op1, op2));
5820 emit_insn (gen_vec_interleave_lowv8hi (dest, t1, t2));
5824 (define_expand "vec_widen_umult_hi_v8hi"
5825 [(match_operand:V4SI 0 "register_operand" "")
5826 (match_operand:V8HI 1 "register_operand" "")
5827 (match_operand:V8HI 2 "register_operand" "")]
5830 rtx op1, op2, t1, t2, dest;
5834 t1 = gen_reg_rtx (V8HImode);
5835 t2 = gen_reg_rtx (V8HImode);
5836 dest = gen_lowpart (V8HImode, operands[0]);
5838 emit_insn (gen_mulv8hi3 (t1, op1, op2));
5839 emit_insn (gen_umulv8hi3_highpart (t2, op1, op2));
5840 emit_insn (gen_vec_interleave_highv8hi (dest, t1, t2));
5844 (define_expand "vec_widen_umult_lo_v8hi"
5845 [(match_operand:V4SI 0 "register_operand" "")
5846 (match_operand:V8HI 1 "register_operand" "")
5847 (match_operand:V8HI 2 "register_operand" "")]
5850 rtx op1, op2, t1, t2, dest;
5854 t1 = gen_reg_rtx (V8HImode);
5855 t2 = gen_reg_rtx (V8HImode);
5856 dest = gen_lowpart (V8HImode, operands[0]);
5858 emit_insn (gen_mulv8hi3 (t1, op1, op2));
5859 emit_insn (gen_umulv8hi3_highpart (t2, op1, op2));
5860 emit_insn (gen_vec_interleave_lowv8hi (dest, t1, t2));
5864 (define_expand "vec_widen_smult_hi_v4si"
5865 [(match_operand:V2DI 0 "register_operand" "")
5866 (match_operand:V4SI 1 "register_operand" "")
5867 (match_operand:V4SI 2 "register_operand" "")]
5872 t1 = gen_reg_rtx (V4SImode);
5873 t2 = gen_reg_rtx (V4SImode);
5875 emit_insn (gen_sse2_pshufd_1 (t1, operands[1],
5880 emit_insn (gen_sse2_pshufd_1 (t2, operands[2],
5885 emit_insn (gen_xop_mulv2div2di3_high (operands[0], t1, t2));
5889 (define_expand "vec_widen_smult_lo_v4si"
5890 [(match_operand:V2DI 0 "register_operand" "")
5891 (match_operand:V4SI 1 "register_operand" "")
5892 (match_operand:V4SI 2 "register_operand" "")]
5897 t1 = gen_reg_rtx (V4SImode);
5898 t2 = gen_reg_rtx (V4SImode);
5900 emit_insn (gen_sse2_pshufd_1 (t1, operands[1],
5905 emit_insn (gen_sse2_pshufd_1 (t2, operands[2],
5910 emit_insn (gen_xop_mulv2div2di3_low (operands[0], t1, t2));
5914 (define_expand "vec_widen_umult_hi_v4si"
5915 [(match_operand:V2DI 0 "register_operand" "")
5916 (match_operand:V4SI 1 "register_operand" "")
5917 (match_operand:V4SI 2 "register_operand" "")]
5920 rtx op1, op2, t1, t2;
5924 t1 = gen_reg_rtx (V4SImode);
5925 t2 = gen_reg_rtx (V4SImode);
5927 emit_insn (gen_vec_interleave_highv4si (t1, op1, op1));
5928 emit_insn (gen_vec_interleave_highv4si (t2, op2, op2));
5929 emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2));
5933 (define_expand "vec_widen_umult_lo_v4si"
5934 [(match_operand:V2DI 0 "register_operand" "")
5935 (match_operand:V4SI 1 "register_operand" "")
5936 (match_operand:V4SI 2 "register_operand" "")]
5939 rtx op1, op2, t1, t2;
5943 t1 = gen_reg_rtx (V4SImode);
5944 t2 = gen_reg_rtx (V4SImode);
5946 emit_insn (gen_vec_interleave_lowv4si (t1, op1, op1));
5947 emit_insn (gen_vec_interleave_lowv4si (t2, op2, op2));
5948 emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2));
5952 (define_expand "sdot_prodv8hi"
5953 [(match_operand:V4SI 0 "register_operand" "")
5954 (match_operand:V8HI 1 "register_operand" "")
5955 (match_operand:V8HI 2 "register_operand" "")
5956 (match_operand:V4SI 3 "register_operand" "")]
5959 rtx t = gen_reg_rtx (V4SImode);
5960 emit_insn (gen_sse2_pmaddwd (t, operands[1], operands[2]));
5961 emit_insn (gen_addv4si3 (operands[0], operands[3], t));
5965 (define_expand "udot_prodv4si"
5966 [(match_operand:V2DI 0 "register_operand" "")
5967 (match_operand:V4SI 1 "register_operand" "")
5968 (match_operand:V4SI 2 "register_operand" "")
5969 (match_operand:V2DI 3 "register_operand" "")]
5974 t1 = gen_reg_rtx (V2DImode);
5975 emit_insn (gen_sse2_umulv2siv2di3 (t1, operands[1], operands[2]));
5976 emit_insn (gen_addv2di3 (t1, t1, operands[3]));
5978 t2 = gen_reg_rtx (V4SImode);
5979 t3 = gen_reg_rtx (V4SImode);
5980 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t2),
5981 gen_lowpart (TImode, operands[1]),
5983 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t3),
5984 gen_lowpart (TImode, operands[2]),
5987 t4 = gen_reg_rtx (V2DImode);
5988 emit_insn (gen_sse2_umulv2siv2di3 (t4, t2, t3));
5990 emit_insn (gen_addv2di3 (operands[0], t1, t4));
5994 (define_insn "*avx_ashr<mode>3"
5995 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
5997 (match_operand:SSEMODE24 1 "register_operand" "x")
5998 (match_operand:SI 2 "nonmemory_operand" "xN")))]
6000 "vpsra<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6001 [(set_attr "type" "sseishft")
6002 (set_attr "prefix" "vex")
6003 (set (attr "length_immediate")
6004 (if_then_else (match_operand 2 "const_int_operand" "")
6006 (const_string "0")))
6007 (set_attr "mode" "TI")])
6009 (define_insn "ashr<mode>3"
6010 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
6012 (match_operand:SSEMODE24 1 "register_operand" "0")
6013 (match_operand:SI 2 "nonmemory_operand" "xN")))]
6015 "psra<ssevecsize>\t{%2, %0|%0, %2}"
6016 [(set_attr "type" "sseishft")
6017 (set_attr "prefix_data16" "1")
6018 (set (attr "length_immediate")
6019 (if_then_else (match_operand 2 "const_int_operand" "")
6021 (const_string "0")))
6022 (set_attr "mode" "TI")])
6024 (define_insn "*avx_lshr<mode>3"
6025 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
6026 (lshiftrt:SSEMODE248
6027 (match_operand:SSEMODE248 1 "register_operand" "x")
6028 (match_operand:SI 2 "nonmemory_operand" "xN")))]
6030 "vpsrl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6031 [(set_attr "type" "sseishft")
6032 (set_attr "prefix" "vex")
6033 (set (attr "length_immediate")
6034 (if_then_else (match_operand 2 "const_int_operand" "")
6036 (const_string "0")))
6037 (set_attr "mode" "TI")])
6039 (define_insn "lshr<mode>3"
6040 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
6041 (lshiftrt:SSEMODE248
6042 (match_operand:SSEMODE248 1 "register_operand" "0")
6043 (match_operand:SI 2 "nonmemory_operand" "xN")))]
6045 "psrl<ssevecsize>\t{%2, %0|%0, %2}"
6046 [(set_attr "type" "sseishft")
6047 (set_attr "prefix_data16" "1")
6048 (set (attr "length_immediate")
6049 (if_then_else (match_operand 2 "const_int_operand" "")
6051 (const_string "0")))
6052 (set_attr "mode" "TI")])
6054 (define_insn "*avx_ashl<mode>3"
6055 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
6057 (match_operand:SSEMODE248 1 "register_operand" "x")
6058 (match_operand:SI 2 "nonmemory_operand" "xN")))]
6060 "vpsll<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6061 [(set_attr "type" "sseishft")
6062 (set_attr "prefix" "vex")
6063 (set (attr "length_immediate")
6064 (if_then_else (match_operand 2 "const_int_operand" "")
6066 (const_string "0")))
6067 (set_attr "mode" "TI")])
6069 (define_insn "ashl<mode>3"
6070 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
6072 (match_operand:SSEMODE248 1 "register_operand" "0")
6073 (match_operand:SI 2 "nonmemory_operand" "xN")))]
6075 "psll<ssevecsize>\t{%2, %0|%0, %2}"
6076 [(set_attr "type" "sseishft")
6077 (set_attr "prefix_data16" "1")
6078 (set (attr "length_immediate")
6079 (if_then_else (match_operand 2 "const_int_operand" "")
6081 (const_string "0")))
6082 (set_attr "mode" "TI")])
6084 (define_expand "vec_shl_<mode>"
6085 [(set (match_operand:SSEMODEI 0 "register_operand" "")
6086 (ashift:TI (match_operand:SSEMODEI 1 "register_operand" "")
6087 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
6090 operands[0] = gen_lowpart (TImode, operands[0]);
6091 operands[1] = gen_lowpart (TImode, operands[1]);
6094 (define_expand "vec_shr_<mode>"
6095 [(set (match_operand:SSEMODEI 0 "register_operand" "")
6096 (lshiftrt:TI (match_operand:SSEMODEI 1 "register_operand" "")
6097 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
6100 operands[0] = gen_lowpart (TImode, operands[0]);
6101 operands[1] = gen_lowpart (TImode, operands[1]);
6104 (define_insn "*avx_<code><mode>3"
6105 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
6107 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
6108 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
6109 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6110 "vp<maxminiprefix><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6111 [(set_attr "type" "sseiadd")
6112 (set (attr "prefix_extra")
6114 (ne (symbol_ref "<MODE>mode != ((<CODE> == SMAX || <CODE> == SMIN) ? V8HImode : V16QImode)")
6117 (const_string "0")))
6118 (set_attr "prefix" "vex")
6119 (set_attr "mode" "TI")])
6121 (define_expand "<code>v16qi3"
6122 [(set (match_operand:V16QI 0 "register_operand" "")
6124 (match_operand:V16QI 1 "nonimmediate_operand" "")
6125 (match_operand:V16QI 2 "nonimmediate_operand" "")))]
6127 "ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
6129 (define_insn "*<code>v16qi3"
6130 [(set (match_operand:V16QI 0 "register_operand" "=x")
6132 (match_operand:V16QI 1 "nonimmediate_operand" "%0")
6133 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
6134 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
6135 "p<maxminiprefix>b\t{%2, %0|%0, %2}"
6136 [(set_attr "type" "sseiadd")
6137 (set_attr "prefix_data16" "1")
6138 (set_attr "mode" "TI")])
6140 (define_expand "<code>v8hi3"
6141 [(set (match_operand:V8HI 0 "register_operand" "")
6143 (match_operand:V8HI 1 "nonimmediate_operand" "")
6144 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
6146 "ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
6148 (define_insn "*<code>v8hi3"
6149 [(set (match_operand:V8HI 0 "register_operand" "=x")
6151 (match_operand:V8HI 1 "nonimmediate_operand" "%0")
6152 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
6153 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
6154 "p<maxminiprefix>w\t{%2, %0|%0, %2}"
6155 [(set_attr "type" "sseiadd")
6156 (set_attr "prefix_data16" "1")
6157 (set_attr "mode" "TI")])
6159 (define_expand "umaxv8hi3"
6160 [(set (match_operand:V8HI 0 "register_operand" "")
6161 (umax:V8HI (match_operand:V8HI 1 "register_operand" "")
6162 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
6166 ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands);
6169 rtx op0 = operands[0], op2 = operands[2], op3 = op0;
6170 if (rtx_equal_p (op3, op2))
6171 op3 = gen_reg_rtx (V8HImode);
6172 emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
6173 emit_insn (gen_addv8hi3 (op0, op3, op2));
6178 (define_expand "smax<mode>3"
6179 [(set (match_operand:SSEMODE14 0 "register_operand" "")
6180 (smax:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
6181 (match_operand:SSEMODE14 2 "register_operand" "")))]
6185 ix86_fixup_binary_operands_no_copy (SMAX, <MODE>mode, operands);
6191 xops[0] = operands[0];
6192 xops[1] = operands[1];
6193 xops[2] = operands[2];
6194 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
6195 xops[4] = operands[1];
6196 xops[5] = operands[2];
6197 ok = ix86_expand_int_vcond (xops);
6203 (define_insn "*sse4_1_<code><mode>3"
6204 [(set (match_operand:SSEMODE14 0 "register_operand" "=x")
6206 (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
6207 (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
6208 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6209 "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
6210 [(set_attr "type" "sseiadd")
6211 (set_attr "prefix_extra" "1")
6212 (set_attr "mode" "TI")])
6214 (define_expand "umaxv4si3"
6215 [(set (match_operand:V4SI 0 "register_operand" "")
6216 (umax:V4SI (match_operand:V4SI 1 "register_operand" "")
6217 (match_operand:V4SI 2 "register_operand" "")))]
6221 ix86_fixup_binary_operands_no_copy (UMAX, V4SImode, operands);
6227 xops[0] = operands[0];
6228 xops[1] = operands[1];
6229 xops[2] = operands[2];
6230 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
6231 xops[4] = operands[1];
6232 xops[5] = operands[2];
6233 ok = ix86_expand_int_vcond (xops);
6239 (define_insn "*sse4_1_<code><mode>3"
6240 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
6242 (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
6243 (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
6244 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6245 "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
6246 [(set_attr "type" "sseiadd")
6247 (set_attr "prefix_extra" "1")
6248 (set_attr "mode" "TI")])
6250 (define_expand "smin<mode>3"
6251 [(set (match_operand:SSEMODE14 0 "register_operand" "")
6252 (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
6253 (match_operand:SSEMODE14 2 "register_operand" "")))]
6257 ix86_fixup_binary_operands_no_copy (SMIN, <MODE>mode, operands);
6263 xops[0] = operands[0];
6264 xops[1] = operands[2];
6265 xops[2] = operands[1];
6266 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
6267 xops[4] = operands[1];
6268 xops[5] = operands[2];
6269 ok = ix86_expand_int_vcond (xops);
6275 (define_expand "umin<mode>3"
6276 [(set (match_operand:SSEMODE24 0 "register_operand" "")
6277 (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
6278 (match_operand:SSEMODE24 2 "register_operand" "")))]
6282 ix86_fixup_binary_operands_no_copy (UMIN, <MODE>mode, operands);
6288 xops[0] = operands[0];
6289 xops[1] = operands[2];
6290 xops[2] = operands[1];
6291 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
6292 xops[4] = operands[1];
6293 xops[5] = operands[2];
6294 ok = ix86_expand_int_vcond (xops);
6300 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6302 ;; Parallel integral comparisons
6304 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6306 (define_expand "sse2_eq<mode>3"
6307 [(set (match_operand:SSEMODE124 0 "register_operand" "")
6309 (match_operand:SSEMODE124 1 "nonimmediate_operand" "")
6310 (match_operand:SSEMODE124 2 "nonimmediate_operand" "")))]
6311 "TARGET_SSE2 && !TARGET_XOP "
6312 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
6314 (define_insn "*avx_eq<mode>3"
6315 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
6317 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "%x")
6318 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
6319 "TARGET_AVX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
6320 "vpcmpeq<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6321 [(set_attr "type" "ssecmp")
6322 (set (attr "prefix_extra")
6323 (if_then_else (match_operand:V2DI 0 "" "")
6325 (const_string "*")))
6326 (set_attr "prefix" "vex")
6327 (set_attr "mode" "TI")])
6329 (define_insn "*sse2_eq<mode>3"
6330 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
6332 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%0")
6333 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
6334 "TARGET_SSE2 && !TARGET_XOP
6335 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
6336 "pcmpeq<ssevecsize>\t{%2, %0|%0, %2}"
6337 [(set_attr "type" "ssecmp")
6338 (set_attr "prefix_data16" "1")
6339 (set_attr "mode" "TI")])
6341 (define_expand "sse4_1_eqv2di3"
6342 [(set (match_operand:V2DI 0 "register_operand" "")
6344 (match_operand:V2DI 1 "nonimmediate_operand" "")
6345 (match_operand:V2DI 2 "nonimmediate_operand" "")))]
6347 "ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);")
6349 (define_insn "*sse4_1_eqv2di3"
6350 [(set (match_operand:V2DI 0 "register_operand" "=x")
6352 (match_operand:V2DI 1 "nonimmediate_operand" "%0")
6353 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
6354 "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
6355 "pcmpeqq\t{%2, %0|%0, %2}"
6356 [(set_attr "type" "ssecmp")
6357 (set_attr "prefix_extra" "1")
6358 (set_attr "mode" "TI")])
6360 (define_insn "*avx_gt<mode>3"
6361 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
6363 (match_operand:SSEMODE1248 1 "register_operand" "x")
6364 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
6366 "vpcmpgt<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
6367 [(set_attr "type" "ssecmp")
6368 (set (attr "prefix_extra")
6369 (if_then_else (match_operand:V2DI 0 "" "")
6371 (const_string "*")))
6372 (set_attr "prefix" "vex")
6373 (set_attr "mode" "TI")])
6375 (define_insn "sse2_gt<mode>3"
6376 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
6378 (match_operand:SSEMODE124 1 "register_operand" "0")
6379 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
6380 "TARGET_SSE2 && !TARGET_XOP"
6381 "pcmpgt<ssevecsize>\t{%2, %0|%0, %2}"
6382 [(set_attr "type" "ssecmp")
6383 (set_attr "prefix_data16" "1")
6384 (set_attr "mode" "TI")])
6386 (define_insn "sse4_2_gtv2di3"
6387 [(set (match_operand:V2DI 0 "register_operand" "=x")
6389 (match_operand:V2DI 1 "register_operand" "0")
6390 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
6392 "pcmpgtq\t{%2, %0|%0, %2}"
6393 [(set_attr "type" "ssecmp")
6394 (set_attr "prefix_extra" "1")
6395 (set_attr "mode" "TI")])
6397 (define_expand "vcond<mode>"
6398 [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
6399 (if_then_else:SSEMODE124C8
6400 (match_operator 3 ""
6401 [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
6402 (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
6403 (match_operand:SSEMODE124C8 1 "general_operand" "")
6404 (match_operand:SSEMODE124C8 2 "general_operand" "")))]
6407 bool ok = ix86_expand_int_vcond (operands);
6412 (define_expand "vcondu<mode>"
6413 [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
6414 (if_then_else:SSEMODE124C8
6415 (match_operator 3 ""
6416 [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
6417 (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
6418 (match_operand:SSEMODE124C8 1 "general_operand" "")
6419 (match_operand:SSEMODE124C8 2 "general_operand" "")))]
6422 bool ok = ix86_expand_int_vcond (operands);
6427 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6429 ;; Parallel bitwise logical operations
6431 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6433 (define_expand "one_cmpl<mode>2"
6434 [(set (match_operand:SSEMODEI 0 "register_operand" "")
6435 (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
6439 int i, n = GET_MODE_NUNITS (<MODE>mode);
6440 rtvec v = rtvec_alloc (n);
6442 for (i = 0; i < n; ++i)
6443 RTVEC_ELT (v, i) = constm1_rtx;
6445 operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
6448 (define_insn "*avx_andnot<mode>3"
6449 [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
6451 (not:AVX256MODEI (match_operand:AVX256MODEI 1 "register_operand" "x"))
6452 (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
6454 "vandnps\t{%2, %1, %0|%0, %1, %2}"
6455 [(set_attr "type" "sselog")
6456 (set_attr "prefix" "vex")
6457 (set_attr "mode" "<avxvecpsmode>")])
6459 (define_insn "*sse_andnot<mode>3"
6460 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6462 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
6463 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6464 "(TARGET_SSE && !TARGET_SSE2)"
6465 "andnps\t{%2, %0|%0, %2}"
6466 [(set_attr "type" "sselog")
6467 (set_attr "mode" "V4SF")])
6469 (define_insn "*avx_andnot<mode>3"
6470 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6472 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "x"))
6473 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6475 "vpandn\t{%2, %1, %0|%0, %1, %2}"
6476 [(set_attr "type" "sselog")
6477 (set_attr "prefix" "vex")
6478 (set_attr "mode" "TI")])
6480 (define_insn "sse2_andnot<mode>3"
6481 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6483 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
6484 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6486 "pandn\t{%2, %0|%0, %2}"
6487 [(set_attr "type" "sselog")
6488 (set_attr "prefix_data16" "1")
6489 (set_attr "mode" "TI")])
6491 (define_insn "*andnottf3"
6492 [(set (match_operand:TF 0 "register_operand" "=x")
6494 (not:TF (match_operand:TF 1 "register_operand" "0"))
6495 (match_operand:TF 2 "nonimmediate_operand" "xm")))]
6497 "pandn\t{%2, %0|%0, %2}"
6498 [(set_attr "type" "sselog")
6499 (set_attr "prefix_data16" "1")
6500 (set_attr "mode" "TI")])
6502 (define_expand "<code><mode>3"
6503 [(set (match_operand:SSEMODEI 0 "register_operand" "")
6505 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
6506 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
6508 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
6510 (define_insn "*avx_<code><mode>3"
6511 [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
6513 (match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x")
6514 (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
6516 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6517 "v<plogicprefix>ps\t{%2, %1, %0|%0, %1, %2}"
6518 [(set_attr "type" "sselog")
6519 (set_attr "prefix" "vex")
6520 (set_attr "mode" "<avxvecpsmode>")])
6522 (define_insn "*sse_<code><mode>3"
6523 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6525 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
6526 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6527 "(TARGET_SSE && !TARGET_SSE2)
6528 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6529 "<plogicprefix>ps\t{%2, %0|%0, %2}"
6530 [(set_attr "type" "sselog")
6531 (set_attr "mode" "V4SF")])
6533 (define_insn "*avx_<code><mode>3"
6534 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6536 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%x")
6537 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6539 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6540 "vp<plogicprefix>\t{%2, %1, %0|%0, %1, %2}"
6541 [(set_attr "type" "sselog")
6542 (set_attr "prefix" "vex")
6543 (set_attr "mode" "TI")])
6545 (define_insn "*sse2_<code><mode>3"
6546 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
6548 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
6549 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
6550 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
6551 "p<plogicprefix>\t{%2, %0|%0, %2}"
6552 [(set_attr "type" "sselog")
6553 (set_attr "prefix_data16" "1")
6554 (set_attr "mode" "TI")])
6556 (define_expand "<code>tf3"
6557 [(set (match_operand:TF 0 "register_operand" "")
6559 (match_operand:TF 1 "nonimmediate_operand" "")
6560 (match_operand:TF 2 "nonimmediate_operand" "")))]
6562 "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
6564 (define_insn "*<code>tf3"
6565 [(set (match_operand:TF 0 "register_operand" "=x")
6567 (match_operand:TF 1 "nonimmediate_operand" "%0")
6568 (match_operand:TF 2 "nonimmediate_operand" "xm")))]
6569 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
6570 "p<plogicprefix>\t{%2, %0|%0, %2}"
6571 [(set_attr "type" "sselog")
6572 (set_attr "prefix_data16" "1")
6573 (set_attr "mode" "TI")])
6575 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6577 ;; Parallel integral element swizzling
6579 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6582 ;; op1 = abcdefghijklmnop
6583 ;; op2 = qrstuvwxyz012345
6584 ;; h1 = aqbrcsdteufvgwhx
6585 ;; l1 = iyjzk0l1m2n3o4p5
6586 ;; h2 = aiqybjrzcks0dlt1
6587 ;; l2 = emu2fnv3gow4hpx5
6588 ;; h3 = aeimquy2bfjnrvz3
6589 ;; l3 = cgkosw04dhlptx15
6590 ;; result = bdfhjlnprtvxz135
6591 (define_expand "vec_pack_trunc_v8hi"
6592 [(match_operand:V16QI 0 "register_operand" "")
6593 (match_operand:V8HI 1 "register_operand" "")
6594 (match_operand:V8HI 2 "register_operand" "")]
6597 rtx op1, op2, h1, l1, h2, l2, h3, l3;
6599 op1 = gen_lowpart (V16QImode, operands[1]);
6600 op2 = gen_lowpart (V16QImode, operands[2]);
6601 h1 = gen_reg_rtx (V16QImode);
6602 l1 = gen_reg_rtx (V16QImode);
6603 h2 = gen_reg_rtx (V16QImode);
6604 l2 = gen_reg_rtx (V16QImode);
6605 h3 = gen_reg_rtx (V16QImode);
6606 l3 = gen_reg_rtx (V16QImode);
6608 emit_insn (gen_vec_interleave_highv16qi (h1, op1, op2));
6609 emit_insn (gen_vec_interleave_lowv16qi (l1, op1, op2));
6610 emit_insn (gen_vec_interleave_highv16qi (h2, l1, h1));
6611 emit_insn (gen_vec_interleave_lowv16qi (l2, l1, h1));
6612 emit_insn (gen_vec_interleave_highv16qi (h3, l2, h2));
6613 emit_insn (gen_vec_interleave_lowv16qi (l3, l2, h2));
6614 emit_insn (gen_vec_interleave_lowv16qi (operands[0], l3, h3));
6625 ;; result = bdfhjlnp
6626 (define_expand "vec_pack_trunc_v4si"
6627 [(match_operand:V8HI 0 "register_operand" "")
6628 (match_operand:V4SI 1 "register_operand" "")
6629 (match_operand:V4SI 2 "register_operand" "")]
6632 rtx op1, op2, h1, l1, h2, l2;
6634 op1 = gen_lowpart (V8HImode, operands[1]);
6635 op2 = gen_lowpart (V8HImode, operands[2]);
6636 h1 = gen_reg_rtx (V8HImode);
6637 l1 = gen_reg_rtx (V8HImode);
6638 h2 = gen_reg_rtx (V8HImode);
6639 l2 = gen_reg_rtx (V8HImode);
6641 emit_insn (gen_vec_interleave_highv8hi (h1, op1, op2));
6642 emit_insn (gen_vec_interleave_lowv8hi (l1, op1, op2));
6643 emit_insn (gen_vec_interleave_highv8hi (h2, l1, h1));
6644 emit_insn (gen_vec_interleave_lowv8hi (l2, l1, h1));
6645 emit_insn (gen_vec_interleave_lowv8hi (operands[0], l2, h2));
6655 (define_expand "vec_pack_trunc_v2di"
6656 [(match_operand:V4SI 0 "register_operand" "")
6657 (match_operand:V2DI 1 "register_operand" "")
6658 (match_operand:V2DI 2 "register_operand" "")]
6661 rtx op1, op2, h1, l1;
6663 op1 = gen_lowpart (V4SImode, operands[1]);
6664 op2 = gen_lowpart (V4SImode, operands[2]);
6665 h1 = gen_reg_rtx (V4SImode);
6666 l1 = gen_reg_rtx (V4SImode);
6668 emit_insn (gen_vec_interleave_highv4si (h1, op1, op2));
6669 emit_insn (gen_vec_interleave_lowv4si (l1, op1, op2));
6670 emit_insn (gen_vec_interleave_lowv4si (operands[0], l1, h1));
6674 (define_expand "vec_interleave_highv16qi"
6675 [(set (match_operand:V16QI 0 "register_operand" "")
6678 (match_operand:V16QI 1 "register_operand" "")
6679 (match_operand:V16QI 2 "nonimmediate_operand" ""))
6680 (parallel [(const_int 8) (const_int 24)
6681 (const_int 9) (const_int 25)
6682 (const_int 10) (const_int 26)
6683 (const_int 11) (const_int 27)
6684 (const_int 12) (const_int 28)
6685 (const_int 13) (const_int 29)
6686 (const_int 14) (const_int 30)
6687 (const_int 15) (const_int 31)])))]
6690 emit_insn (gen_sse2_punpckhbw (operands[0], operands[1], operands[2]));
6694 (define_expand "vec_interleave_lowv16qi"
6695 [(set (match_operand:V16QI 0 "register_operand" "")
6698 (match_operand:V16QI 1 "register_operand" "")
6699 (match_operand:V16QI 2 "nonimmediate_operand" ""))
6700 (parallel [(const_int 0) (const_int 16)
6701 (const_int 1) (const_int 17)
6702 (const_int 2) (const_int 18)
6703 (const_int 3) (const_int 19)
6704 (const_int 4) (const_int 20)
6705 (const_int 5) (const_int 21)
6706 (const_int 6) (const_int 22)
6707 (const_int 7) (const_int 23)])))]
6710 emit_insn (gen_sse2_punpcklbw (operands[0], operands[1], operands[2]));
6714 (define_expand "vec_interleave_highv8hi"
6715 [(set (match_operand:V8HI 0 "register_operand" "=")
6718 (match_operand:V8HI 1 "register_operand" "")
6719 (match_operand:V8HI 2 "nonimmediate_operand" ""))
6720 (parallel [(const_int 4) (const_int 12)
6721 (const_int 5) (const_int 13)
6722 (const_int 6) (const_int 14)
6723 (const_int 7) (const_int 15)])))]
6726 emit_insn (gen_sse2_punpckhwd (operands[0], operands[1], operands[2]));
6730 (define_expand "vec_interleave_lowv8hi"
6731 [(set (match_operand:V8HI 0 "register_operand" "")
6734 (match_operand:V8HI 1 "register_operand" "")
6735 (match_operand:V8HI 2 "nonimmediate_operand" ""))
6736 (parallel [(const_int 0) (const_int 8)
6737 (const_int 1) (const_int 9)
6738 (const_int 2) (const_int 10)
6739 (const_int 3) (const_int 11)])))]
6742 emit_insn (gen_sse2_punpcklwd (operands[0], operands[1], operands[2]));
6746 (define_expand "vec_interleave_highv4si"
6747 [(set (match_operand:V4SI 0 "register_operand" "")
6750 (match_operand:V4SI 1 "register_operand" "")
6751 (match_operand:V4SI 2 "nonimmediate_operand" ""))
6752 (parallel [(const_int 2) (const_int 6)
6753 (const_int 3) (const_int 7)])))]
6756 emit_insn (gen_sse2_punpckhdq (operands[0], operands[1], operands[2]));
6760 (define_expand "vec_interleave_lowv4si"
6761 [(set (match_operand:V4SI 0 "register_operand" "")
6764 (match_operand:V4SI 1 "register_operand" "")
6765 (match_operand:V4SI 2 "nonimmediate_operand" ""))
6766 (parallel [(const_int 0) (const_int 4)
6767 (const_int 1) (const_int 5)])))]
6770 emit_insn (gen_sse2_punpckldq (operands[0], operands[1], operands[2]));
6774 (define_expand "vec_interleave_highv2di"
6775 [(set (match_operand:V2DI 0 "register_operand" "")
6778 (match_operand:V2DI 1 "register_operand" "")
6779 (match_operand:V2DI 2 "nonimmediate_operand" ""))
6780 (parallel [(const_int 1)
6784 emit_insn (gen_sse2_punpckhqdq (operands[0], operands[1], operands[2]));
6788 (define_expand "vec_interleave_lowv2di"
6789 [(set (match_operand:V2DI 0 "register_operand" "")
6792 (match_operand:V2DI 1 "register_operand" "")
6793 (match_operand:V2DI 2 "nonimmediate_operand" ""))
6794 (parallel [(const_int 0)
6798 emit_insn (gen_sse2_punpcklqdq (operands[0], operands[1], operands[2]));
6802 (define_expand "vec_interleave_highv4sf"
6803 [(set (match_operand:V4SF 0 "register_operand" "")
6806 (match_operand:V4SF 1 "register_operand" "")
6807 (match_operand:V4SF 2 "nonimmediate_operand" ""))
6808 (parallel [(const_int 2) (const_int 6)
6809 (const_int 3) (const_int 7)])))]
6812 (define_expand "vec_interleave_lowv4sf"
6813 [(set (match_operand:V4SF 0 "register_operand" "")
6816 (match_operand:V4SF 1 "register_operand" "")
6817 (match_operand:V4SF 2 "nonimmediate_operand" ""))
6818 (parallel [(const_int 0) (const_int 4)
6819 (const_int 1) (const_int 5)])))]
6822 (define_expand "vec_interleave_highv2df"
6823 [(set (match_operand:V2DF 0 "register_operand" "")
6826 (match_operand:V2DF 1 "register_operand" "")
6827 (match_operand:V2DF 2 "nonimmediate_operand" ""))
6828 (parallel [(const_int 1)
6832 (define_expand "vec_interleave_lowv2df"
6833 [(set (match_operand:V2DF 0 "register_operand" "")
6836 (match_operand:V2DF 1 "register_operand" "")
6837 (match_operand:V2DF 2 "nonimmediate_operand" ""))
6838 (parallel [(const_int 0)
6842 (define_insn "*avx_packsswb"
6843 [(set (match_operand:V16QI 0 "register_operand" "=x")
6846 (match_operand:V8HI 1 "register_operand" "x"))
6848 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
6850 "vpacksswb\t{%2, %1, %0|%0, %1, %2}"
6851 [(set_attr "type" "sselog")
6852 (set_attr "prefix" "vex")
6853 (set_attr "mode" "TI")])
6855 (define_insn "sse2_packsswb"
6856 [(set (match_operand:V16QI 0 "register_operand" "=x")
6859 (match_operand:V8HI 1 "register_operand" "0"))
6861 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
6863 "packsswb\t{%2, %0|%0, %2}"
6864 [(set_attr "type" "sselog")
6865 (set_attr "prefix_data16" "1")
6866 (set_attr "mode" "TI")])
6868 (define_insn "*avx_packssdw"
6869 [(set (match_operand:V8HI 0 "register_operand" "=x")
6872 (match_operand:V4SI 1 "register_operand" "x"))
6874 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
6876 "vpackssdw\t{%2, %1, %0|%0, %1, %2}"
6877 [(set_attr "type" "sselog")
6878 (set_attr "prefix" "vex")
6879 (set_attr "mode" "TI")])
6881 (define_insn "sse2_packssdw"
6882 [(set (match_operand:V8HI 0 "register_operand" "=x")
6885 (match_operand:V4SI 1 "register_operand" "0"))
6887 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
6889 "packssdw\t{%2, %0|%0, %2}"
6890 [(set_attr "type" "sselog")
6891 (set_attr "prefix_data16" "1")
6892 (set_attr "mode" "TI")])
6894 (define_insn "*avx_packuswb"
6895 [(set (match_operand:V16QI 0 "register_operand" "=x")
6898 (match_operand:V8HI 1 "register_operand" "x"))
6900 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
6902 "vpackuswb\t{%2, %1, %0|%0, %1, %2}"
6903 [(set_attr "type" "sselog")
6904 (set_attr "prefix" "vex")
6905 (set_attr "mode" "TI")])
6907 (define_insn "sse2_packuswb"
6908 [(set (match_operand:V16QI 0 "register_operand" "=x")
6911 (match_operand:V8HI 1 "register_operand" "0"))
6913 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
6915 "packuswb\t{%2, %0|%0, %2}"
6916 [(set_attr "type" "sselog")
6917 (set_attr "prefix_data16" "1")
6918 (set_attr "mode" "TI")])
6920 (define_insn "*avx_punpckhbw"
6921 [(set (match_operand:V16QI 0 "register_operand" "=x")
6924 (match_operand:V16QI 1 "register_operand" "x")
6925 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
6926 (parallel [(const_int 8) (const_int 24)
6927 (const_int 9) (const_int 25)
6928 (const_int 10) (const_int 26)
6929 (const_int 11) (const_int 27)
6930 (const_int 12) (const_int 28)
6931 (const_int 13) (const_int 29)
6932 (const_int 14) (const_int 30)
6933 (const_int 15) (const_int 31)])))]
6935 "vpunpckhbw\t{%2, %1, %0|%0, %1, %2}"
6936 [(set_attr "type" "sselog")
6937 (set_attr "prefix" "vex")
6938 (set_attr "mode" "TI")])
6940 (define_insn "sse2_punpckhbw"
6941 [(set (match_operand:V16QI 0 "register_operand" "=x")
6944 (match_operand:V16QI 1 "register_operand" "0")
6945 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
6946 (parallel [(const_int 8) (const_int 24)
6947 (const_int 9) (const_int 25)
6948 (const_int 10) (const_int 26)
6949 (const_int 11) (const_int 27)
6950 (const_int 12) (const_int 28)
6951 (const_int 13) (const_int 29)
6952 (const_int 14) (const_int 30)
6953 (const_int 15) (const_int 31)])))]
6955 "punpckhbw\t{%2, %0|%0, %2}"
6956 [(set_attr "type" "sselog")
6957 (set_attr "prefix_data16" "1")
6958 (set_attr "mode" "TI")])
6960 (define_insn "*avx_punpcklbw"
6961 [(set (match_operand:V16QI 0 "register_operand" "=x")
6964 (match_operand:V16QI 1 "register_operand" "x")
6965 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
6966 (parallel [(const_int 0) (const_int 16)
6967 (const_int 1) (const_int 17)
6968 (const_int 2) (const_int 18)
6969 (const_int 3) (const_int 19)
6970 (const_int 4) (const_int 20)
6971 (const_int 5) (const_int 21)
6972 (const_int 6) (const_int 22)
6973 (const_int 7) (const_int 23)])))]
6975 "vpunpcklbw\t{%2, %1, %0|%0, %1, %2}"
6976 [(set_attr "type" "sselog")
6977 (set_attr "prefix" "vex")
6978 (set_attr "mode" "TI")])
6980 (define_insn "sse2_punpcklbw"
6981 [(set (match_operand:V16QI 0 "register_operand" "=x")
6984 (match_operand:V16QI 1 "register_operand" "0")
6985 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
6986 (parallel [(const_int 0) (const_int 16)
6987 (const_int 1) (const_int 17)
6988 (const_int 2) (const_int 18)
6989 (const_int 3) (const_int 19)
6990 (const_int 4) (const_int 20)
6991 (const_int 5) (const_int 21)
6992 (const_int 6) (const_int 22)
6993 (const_int 7) (const_int 23)])))]
6995 "punpcklbw\t{%2, %0|%0, %2}"
6996 [(set_attr "type" "sselog")
6997 (set_attr "prefix_data16" "1")
6998 (set_attr "mode" "TI")])
7000 (define_insn "*avx_punpckhwd"
7001 [(set (match_operand:V8HI 0 "register_operand" "=x")
7004 (match_operand:V8HI 1 "register_operand" "x")
7005 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
7006 (parallel [(const_int 4) (const_int 12)
7007 (const_int 5) (const_int 13)
7008 (const_int 6) (const_int 14)
7009 (const_int 7) (const_int 15)])))]
7011 "vpunpckhwd\t{%2, %1, %0|%0, %1, %2}"
7012 [(set_attr "type" "sselog")
7013 (set_attr "prefix" "vex")
7014 (set_attr "mode" "TI")])
7016 (define_insn "sse2_punpckhwd"
7017 [(set (match_operand:V8HI 0 "register_operand" "=x")
7020 (match_operand:V8HI 1 "register_operand" "0")
7021 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
7022 (parallel [(const_int 4) (const_int 12)
7023 (const_int 5) (const_int 13)
7024 (const_int 6) (const_int 14)
7025 (const_int 7) (const_int 15)])))]
7027 "punpckhwd\t{%2, %0|%0, %2}"
7028 [(set_attr "type" "sselog")
7029 (set_attr "prefix_data16" "1")
7030 (set_attr "mode" "TI")])
7032 (define_insn "*avx_punpcklwd"
7033 [(set (match_operand:V8HI 0 "register_operand" "=x")
7036 (match_operand:V8HI 1 "register_operand" "x")
7037 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
7038 (parallel [(const_int 0) (const_int 8)
7039 (const_int 1) (const_int 9)
7040 (const_int 2) (const_int 10)
7041 (const_int 3) (const_int 11)])))]
7043 "vpunpcklwd\t{%2, %1, %0|%0, %1, %2}"
7044 [(set_attr "type" "sselog")
7045 (set_attr "prefix" "vex")
7046 (set_attr "mode" "TI")])
7048 (define_insn "sse2_punpcklwd"
7049 [(set (match_operand:V8HI 0 "register_operand" "=x")
7052 (match_operand:V8HI 1 "register_operand" "0")
7053 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
7054 (parallel [(const_int 0) (const_int 8)
7055 (const_int 1) (const_int 9)
7056 (const_int 2) (const_int 10)
7057 (const_int 3) (const_int 11)])))]
7059 "punpcklwd\t{%2, %0|%0, %2}"
7060 [(set_attr "type" "sselog")
7061 (set_attr "prefix_data16" "1")
7062 (set_attr "mode" "TI")])
7064 (define_insn "*avx_punpckhdq"
7065 [(set (match_operand:V4SI 0 "register_operand" "=x")
7068 (match_operand:V4SI 1 "register_operand" "x")
7069 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
7070 (parallel [(const_int 2) (const_int 6)
7071 (const_int 3) (const_int 7)])))]
7073 "vpunpckhdq\t{%2, %1, %0|%0, %1, %2}"
7074 [(set_attr "type" "sselog")
7075 (set_attr "prefix" "vex")
7076 (set_attr "mode" "TI")])
7078 (define_insn "sse2_punpckhdq"
7079 [(set (match_operand:V4SI 0 "register_operand" "=x")
7082 (match_operand:V4SI 1 "register_operand" "0")
7083 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
7084 (parallel [(const_int 2) (const_int 6)
7085 (const_int 3) (const_int 7)])))]
7087 "punpckhdq\t{%2, %0|%0, %2}"
7088 [(set_attr "type" "sselog")
7089 (set_attr "prefix_data16" "1")
7090 (set_attr "mode" "TI")])
7092 (define_insn "*avx_punpckldq"
7093 [(set (match_operand:V4SI 0 "register_operand" "=x")
7096 (match_operand:V4SI 1 "register_operand" "x")
7097 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
7098 (parallel [(const_int 0) (const_int 4)
7099 (const_int 1) (const_int 5)])))]
7101 "vpunpckldq\t{%2, %1, %0|%0, %1, %2}"
7102 [(set_attr "type" "sselog")
7103 (set_attr "prefix" "vex")
7104 (set_attr "mode" "TI")])
7106 (define_insn "sse2_punpckldq"
7107 [(set (match_operand:V4SI 0 "register_operand" "=x")
7110 (match_operand:V4SI 1 "register_operand" "0")
7111 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
7112 (parallel [(const_int 0) (const_int 4)
7113 (const_int 1) (const_int 5)])))]
7115 "punpckldq\t{%2, %0|%0, %2}"
7116 [(set_attr "type" "sselog")
7117 (set_attr "prefix_data16" "1")
7118 (set_attr "mode" "TI")])
7120 (define_insn "*avx_pinsr<ssevecsize>"
7121 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
7122 (vec_merge:SSEMODE124
7123 (vec_duplicate:SSEMODE124
7124 (match_operand:<avxscalarmode> 2 "nonimmediate_operand" "rm"))
7125 (match_operand:SSEMODE124 1 "register_operand" "x")
7126 (match_operand:SI 3 "const_pow2_1_to_<pinsrbits>_operand" "n")))]
7129 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
7130 if (MEM_P (operands[2]))
7131 return "vpinsr<ssevecsize>\t{%3, %2, %1, %0|%0, %1, %2, %3}";
7133 return "vpinsr<ssevecsize>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
7135 [(set_attr "type" "sselog")
7136 (set (attr "prefix_extra")
7137 (if_then_else (match_operand:V8HI 0 "register_operand" "")
7139 (const_string "1")))
7140 (set_attr "length_immediate" "1")
7141 (set_attr "prefix" "vex")
7142 (set_attr "mode" "TI")])
7144 (define_insn "*sse4_1_pinsrb"
7145 [(set (match_operand:V16QI 0 "register_operand" "=x")
7147 (vec_duplicate:V16QI
7148 (match_operand:QI 2 "nonimmediate_operand" "rm"))
7149 (match_operand:V16QI 1 "register_operand" "0")
7150 (match_operand:SI 3 "const_pow2_1_to_32768_operand" "n")))]
7153 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
7154 if (MEM_P (operands[2]))
7155 return "pinsrb\t{%3, %2, %0|%0, %2, %3}";
7157 return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
7159 [(set_attr "type" "sselog")
7160 (set_attr "prefix_extra" "1")
7161 (set_attr "length_immediate" "1")
7162 (set_attr "mode" "TI")])
7164 (define_insn "*sse2_pinsrw"
7165 [(set (match_operand:V8HI 0 "register_operand" "=x")
7168 (match_operand:HI 2 "nonimmediate_operand" "rm"))
7169 (match_operand:V8HI 1 "register_operand" "0")
7170 (match_operand:SI 3 "const_pow2_1_to_128_operand" "n")))]
7173 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
7174 if (MEM_P (operands[2]))
7175 return "pinsrw\t{%3, %2, %0|%0, %2, %3}";
7177 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
7179 [(set_attr "type" "sselog")
7180 (set_attr "prefix_data16" "1")
7181 (set_attr "length_immediate" "1")
7182 (set_attr "mode" "TI")])
7184 ;; It must come before sse2_loadld since it is preferred.
7185 (define_insn "*sse4_1_pinsrd"
7186 [(set (match_operand:V4SI 0 "register_operand" "=x")
7189 (match_operand:SI 2 "nonimmediate_operand" "rm"))
7190 (match_operand:V4SI 1 "register_operand" "0")
7191 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
7194 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
7195 return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
7197 [(set_attr "type" "sselog")
7198 (set_attr "prefix_extra" "1")
7199 (set_attr "length_immediate" "1")
7200 (set_attr "mode" "TI")])
7202 (define_insn "*avx_pinsrq"
7203 [(set (match_operand:V2DI 0 "register_operand" "=x")
7206 (match_operand:DI 2 "nonimmediate_operand" "rm"))
7207 (match_operand:V2DI 1 "register_operand" "x")
7208 (match_operand:SI 3 "const_pow2_1_to_2_operand" "n")))]
7209 "TARGET_AVX && TARGET_64BIT"
7211 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
7212 return "vpinsrq\t{%3, %2, %1, %0|%0, %1, %2, %3}";
7214 [(set_attr "type" "sselog")
7215 (set_attr "prefix_extra" "1")
7216 (set_attr "length_immediate" "1")
7217 (set_attr "prefix" "vex")
7218 (set_attr "mode" "TI")])
7220 (define_insn "*sse4_1_pinsrq"
7221 [(set (match_operand:V2DI 0 "register_operand" "=x")
7224 (match_operand:DI 2 "nonimmediate_operand" "rm"))
7225 (match_operand:V2DI 1 "register_operand" "0")
7226 (match_operand:SI 3 "const_pow2_1_to_2_operand" "n")))]
7227 "TARGET_SSE4_1 && TARGET_64BIT"
7229 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
7230 return "pinsrq\t{%3, %2, %0|%0, %2, %3}";
7232 [(set_attr "type" "sselog")
7233 (set_attr "prefix_rex" "1")
7234 (set_attr "prefix_extra" "1")
7235 (set_attr "length_immediate" "1")
7236 (set_attr "mode" "TI")])
7238 (define_insn "*sse4_1_pextrb"
7239 [(set (match_operand:SI 0 "register_operand" "=r")
7242 (match_operand:V16QI 1 "register_operand" "x")
7243 (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")]))))]
7245 "%vpextrb\t{%2, %1, %0|%0, %1, %2}"
7246 [(set_attr "type" "sselog")
7247 (set_attr "prefix_extra" "1")
7248 (set_attr "length_immediate" "1")
7249 (set_attr "prefix" "maybe_vex")
7250 (set_attr "mode" "TI")])
7252 (define_insn "*sse4_1_pextrb_memory"
7253 [(set (match_operand:QI 0 "memory_operand" "=m")
7255 (match_operand:V16QI 1 "register_operand" "x")
7256 (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")])))]
7258 "%vpextrb\t{%2, %1, %0|%0, %1, %2}"
7259 [(set_attr "type" "sselog")
7260 (set_attr "prefix_extra" "1")
7261 (set_attr "length_immediate" "1")
7262 (set_attr "prefix" "maybe_vex")
7263 (set_attr "mode" "TI")])
7265 (define_insn "*sse2_pextrw"
7266 [(set (match_operand:SI 0 "register_operand" "=r")
7269 (match_operand:V8HI 1 "register_operand" "x")
7270 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
7272 "%vpextrw\t{%2, %1, %0|%0, %1, %2}"
7273 [(set_attr "type" "sselog")
7274 (set_attr "prefix_data16" "1")
7275 (set_attr "length_immediate" "1")
7276 (set_attr "prefix" "maybe_vex")
7277 (set_attr "mode" "TI")])
7279 (define_insn "*sse4_1_pextrw_memory"
7280 [(set (match_operand:HI 0 "memory_operand" "=m")
7282 (match_operand:V8HI 1 "register_operand" "x")
7283 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")])))]
7285 "%vpextrw\t{%2, %1, %0|%0, %1, %2}"
7286 [(set_attr "type" "sselog")
7287 (set_attr "prefix_extra" "1")
7288 (set_attr "length_immediate" "1")
7289 (set_attr "prefix" "maybe_vex")
7290 (set_attr "mode" "TI")])
7292 (define_insn "*sse4_1_pextrd"
7293 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
7295 (match_operand:V4SI 1 "register_operand" "x")
7296 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")])))]
7298 "%vpextrd\t{%2, %1, %0|%0, %1, %2}"
7299 [(set_attr "type" "sselog")
7300 (set_attr "prefix_extra" "1")
7301 (set_attr "length_immediate" "1")
7302 (set_attr "prefix" "maybe_vex")
7303 (set_attr "mode" "TI")])
7305 ;; It must come before *vec_extractv2di_1_sse since it is preferred.
7306 (define_insn "*sse4_1_pextrq"
7307 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
7309 (match_operand:V2DI 1 "register_operand" "x")
7310 (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n")])))]
7311 "TARGET_SSE4_1 && TARGET_64BIT"
7312 "%vpextrq\t{%2, %1, %0|%0, %1, %2}"
7313 [(set_attr "type" "sselog")
7314 (set_attr "prefix_rex" "1")
7315 (set_attr "prefix_extra" "1")
7316 (set_attr "length_immediate" "1")
7317 (set_attr "prefix" "maybe_vex")
7318 (set_attr "mode" "TI")])
7320 (define_expand "sse2_pshufd"
7321 [(match_operand:V4SI 0 "register_operand" "")
7322 (match_operand:V4SI 1 "nonimmediate_operand" "")
7323 (match_operand:SI 2 "const_int_operand" "")]
7326 int mask = INTVAL (operands[2]);
7327 emit_insn (gen_sse2_pshufd_1 (operands[0], operands[1],
7328 GEN_INT ((mask >> 0) & 3),
7329 GEN_INT ((mask >> 2) & 3),
7330 GEN_INT ((mask >> 4) & 3),
7331 GEN_INT ((mask >> 6) & 3)));
7335 (define_insn "sse2_pshufd_1"
7336 [(set (match_operand:V4SI 0 "register_operand" "=x")
7338 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
7339 (parallel [(match_operand 2 "const_0_to_3_operand" "")
7340 (match_operand 3 "const_0_to_3_operand" "")
7341 (match_operand 4 "const_0_to_3_operand" "")
7342 (match_operand 5 "const_0_to_3_operand" "")])))]
7346 mask |= INTVAL (operands[2]) << 0;
7347 mask |= INTVAL (operands[3]) << 2;
7348 mask |= INTVAL (operands[4]) << 4;
7349 mask |= INTVAL (operands[5]) << 6;
7350 operands[2] = GEN_INT (mask);
7352 return "%vpshufd\t{%2, %1, %0|%0, %1, %2}";
7354 [(set_attr "type" "sselog1")
7355 (set_attr "prefix_data16" "1")
7356 (set_attr "prefix" "maybe_vex")
7357 (set_attr "length_immediate" "1")
7358 (set_attr "mode" "TI")])
7360 (define_expand "sse2_pshuflw"
7361 [(match_operand:V8HI 0 "register_operand" "")
7362 (match_operand:V8HI 1 "nonimmediate_operand" "")
7363 (match_operand:SI 2 "const_int_operand" "")]
7366 int mask = INTVAL (operands[2]);
7367 emit_insn (gen_sse2_pshuflw_1 (operands[0], operands[1],
7368 GEN_INT ((mask >> 0) & 3),
7369 GEN_INT ((mask >> 2) & 3),
7370 GEN_INT ((mask >> 4) & 3),
7371 GEN_INT ((mask >> 6) & 3)));
7375 (define_insn "sse2_pshuflw_1"
7376 [(set (match_operand:V8HI 0 "register_operand" "=x")
7378 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
7379 (parallel [(match_operand 2 "const_0_to_3_operand" "")
7380 (match_operand 3 "const_0_to_3_operand" "")
7381 (match_operand 4 "const_0_to_3_operand" "")
7382 (match_operand 5 "const_0_to_3_operand" "")
7390 mask |= INTVAL (operands[2]) << 0;
7391 mask |= INTVAL (operands[3]) << 2;
7392 mask |= INTVAL (operands[4]) << 4;
7393 mask |= INTVAL (operands[5]) << 6;
7394 operands[2] = GEN_INT (mask);
7396 return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
7398 [(set_attr "type" "sselog")
7399 (set_attr "prefix_data16" "0")
7400 (set_attr "prefix_rep" "1")
7401 (set_attr "prefix" "maybe_vex")
7402 (set_attr "length_immediate" "1")
7403 (set_attr "mode" "TI")])
7405 (define_expand "sse2_pshufhw"
7406 [(match_operand:V8HI 0 "register_operand" "")
7407 (match_operand:V8HI 1 "nonimmediate_operand" "")
7408 (match_operand:SI 2 "const_int_operand" "")]
7411 int mask = INTVAL (operands[2]);
7412 emit_insn (gen_sse2_pshufhw_1 (operands[0], operands[1],
7413 GEN_INT (((mask >> 0) & 3) + 4),
7414 GEN_INT (((mask >> 2) & 3) + 4),
7415 GEN_INT (((mask >> 4) & 3) + 4),
7416 GEN_INT (((mask >> 6) & 3) + 4)));
7420 (define_insn "sse2_pshufhw_1"
7421 [(set (match_operand:V8HI 0 "register_operand" "=x")
7423 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
7424 (parallel [(const_int 0)
7428 (match_operand 2 "const_4_to_7_operand" "")
7429 (match_operand 3 "const_4_to_7_operand" "")
7430 (match_operand 4 "const_4_to_7_operand" "")
7431 (match_operand 5 "const_4_to_7_operand" "")])))]
7435 mask |= (INTVAL (operands[2]) - 4) << 0;
7436 mask |= (INTVAL (operands[3]) - 4) << 2;
7437 mask |= (INTVAL (operands[4]) - 4) << 4;
7438 mask |= (INTVAL (operands[5]) - 4) << 6;
7439 operands[2] = GEN_INT (mask);
7441 return "%vpshufhw\t{%2, %1, %0|%0, %1, %2}";
7443 [(set_attr "type" "sselog")
7444 (set_attr "prefix_rep" "1")
7445 (set_attr "prefix_data16" "0")
7446 (set_attr "prefix" "maybe_vex")
7447 (set_attr "length_immediate" "1")
7448 (set_attr "mode" "TI")])
7450 (define_expand "sse2_loadd"
7451 [(set (match_operand:V4SI 0 "register_operand" "")
7454 (match_operand:SI 1 "nonimmediate_operand" ""))
7458 "operands[2] = CONST0_RTX (V4SImode);")
7460 (define_insn "*avx_loadld"
7461 [(set (match_operand:V4SI 0 "register_operand" "=x,Yi,x")
7464 (match_operand:SI 2 "nonimmediate_operand" "m ,r ,x"))
7465 (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,x")
7469 vmovd\t{%2, %0|%0, %2}
7470 vmovd\t{%2, %0|%0, %2}
7471 vmovss\t{%2, %1, %0|%0, %1, %2}"
7472 [(set_attr "type" "ssemov")
7473 (set_attr "prefix" "vex")
7474 (set_attr "mode" "TI,TI,V4SF")])
7476 (define_insn "sse2_loadld"
7477 [(set (match_operand:V4SI 0 "register_operand" "=Y2,Yi,x,x")
7480 (match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x"))
7481 (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0")
7485 movd\t{%2, %0|%0, %2}
7486 movd\t{%2, %0|%0, %2}
7487 movss\t{%2, %0|%0, %2}
7488 movss\t{%2, %0|%0, %2}"
7489 [(set_attr "type" "ssemov")
7490 (set_attr "mode" "TI,TI,V4SF,SF")])
7492 (define_insn_and_split "sse2_stored"
7493 [(set (match_operand:SI 0 "nonimmediate_operand" "=mx,r")
7495 (match_operand:V4SI 1 "register_operand" "x,Yi")
7496 (parallel [(const_int 0)])))]
7499 "&& reload_completed
7500 && (TARGET_INTER_UNIT_MOVES
7501 || MEM_P (operands [0])
7502 || !GENERAL_REGNO_P (true_regnum (operands [0])))"
7503 [(set (match_dup 0) (match_dup 1))]
7505 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));
7508 (define_insn_and_split "*vec_ext_v4si_mem"
7509 [(set (match_operand:SI 0 "register_operand" "=r")
7511 (match_operand:V4SI 1 "memory_operand" "o")
7512 (parallel [(match_operand 2 "const_0_to_3_operand" "")])))]
7518 int i = INTVAL (operands[2]);
7520 emit_move_insn (operands[0], adjust_address (operands[1], SImode, i*4));
7524 (define_expand "sse_storeq"
7525 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7527 (match_operand:V2DI 1 "register_operand" "")
7528 (parallel [(const_int 0)])))]
7532 (define_insn "*sse2_storeq_rex64"
7533 [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,*r,r")
7535 (match_operand:V2DI 1 "nonimmediate_operand" "x,Yi,o")
7536 (parallel [(const_int 0)])))]
7537 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7541 %vmov{q}\t{%1, %0|%0, %1}"
7542 [(set_attr "type" "*,*,imov")
7543 (set_attr "prefix" "*,*,maybe_vex")
7544 (set_attr "mode" "*,*,DI")])
7546 (define_insn "*sse2_storeq"
7547 [(set (match_operand:DI 0 "nonimmediate_operand" "=mx")
7549 (match_operand:V2DI 1 "register_operand" "x")
7550 (parallel [(const_int 0)])))]
7555 [(set (match_operand:DI 0 "nonimmediate_operand" "")
7557 (match_operand:V2DI 1 "register_operand" "")
7558 (parallel [(const_int 0)])))]
7561 && (TARGET_INTER_UNIT_MOVES
7562 || MEM_P (operands [0])
7563 || !GENERAL_REGNO_P (true_regnum (operands [0])))"
7564 [(set (match_dup 0) (match_dup 1))]
7566 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
7569 (define_insn "*vec_extractv2di_1_rex64_avx"
7570 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
7572 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o,o")
7573 (parallel [(const_int 1)])))]
7576 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7578 vmovhps\t{%1, %0|%0, %1}
7579 vpsrldq\t{$8, %1, %0|%0, %1, 8}
7580 vmovq\t{%H1, %0|%0, %H1}
7581 vmov{q}\t{%H1, %0|%0, %H1}"
7582 [(set_attr "type" "ssemov,sseishft,ssemov,imov")
7583 (set_attr "length_immediate" "*,1,*,*")
7584 (set_attr "memory" "*,none,*,*")
7585 (set_attr "prefix" "vex")
7586 (set_attr "mode" "V2SF,TI,TI,DI")])
7588 (define_insn "*vec_extractv2di_1_rex64"
7589 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
7591 (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o,o")
7592 (parallel [(const_int 1)])))]
7593 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7595 movhps\t{%1, %0|%0, %1}
7596 psrldq\t{$8, %0|%0, 8}
7597 movq\t{%H1, %0|%0, %H1}
7598 mov{q}\t{%H1, %0|%0, %H1}"
7599 [(set_attr "type" "ssemov,sseishft,ssemov,imov")
7600 (set_attr "length_immediate" "*,1,*,*")
7601 (set_attr "atom_unit" "*,sishuf,*,*")
7602 (set_attr "memory" "*,none,*,*")
7603 (set_attr "mode" "V2SF,TI,TI,DI")])
7605 (define_insn "*vec_extractv2di_1_avx"
7606 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
7608 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
7609 (parallel [(const_int 1)])))]
7612 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7614 vmovhps\t{%1, %0|%0, %1}
7615 vpsrldq\t{$8, %1, %0|%0, %1, 8}
7616 vmovq\t{%H1, %0|%0, %H1}"
7617 [(set_attr "type" "ssemov,sseishft,ssemov")
7618 (set_attr "length_immediate" "*,1,*")
7619 (set_attr "memory" "*,none,*")
7620 (set_attr "prefix" "vex")
7621 (set_attr "mode" "V2SF,TI,TI")])
7623 (define_insn "*vec_extractv2di_1_sse2"
7624 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
7626 (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o")
7627 (parallel [(const_int 1)])))]
7629 && TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7631 movhps\t{%1, %0|%0, %1}
7632 psrldq\t{$8, %0|%0, 8}
7633 movq\t{%H1, %0|%0, %H1}"
7634 [(set_attr "type" "ssemov,sseishft,ssemov")
7635 (set_attr "length_immediate" "*,1,*")
7636 (set_attr "atom_unit" "*,sishuf,*")
7637 (set_attr "memory" "*,none,*")
7638 (set_attr "mode" "V2SF,TI,TI")])
7640 ;; Not sure this is ever used, but it doesn't hurt to have it. -aoliva
7641 (define_insn "*vec_extractv2di_1_sse"
7642 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
7644 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
7645 (parallel [(const_int 1)])))]
7646 "!TARGET_SSE2 && TARGET_SSE
7647 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
7649 movhps\t{%1, %0|%0, %1}
7650 movhlps\t{%1, %0|%0, %1}
7651 movlps\t{%H1, %0|%0, %H1}"
7652 [(set_attr "type" "ssemov")
7653 (set_attr "mode" "V2SF,V4SF,V2SF")])
7655 (define_insn "*vec_dupv4si"
7656 [(set (match_operand:V4SI 0 "register_operand" "=Y2,x")
7658 (match_operand:SI 1 "register_operand" " Y2,0")))]
7661 %vpshufd\t{$0, %1, %0|%0, %1, 0}
7662 shufps\t{$0, %0, %0|%0, %0, 0}"
7663 [(set_attr "type" "sselog1")
7664 (set_attr "prefix" "maybe_vex,orig")
7665 (set_attr "length_immediate" "1")
7666 (set_attr "mode" "TI,V4SF")])
7668 (define_insn "*vec_dupv2di_avx"
7669 [(set (match_operand:V2DI 0 "register_operand" "=x")
7671 (match_operand:DI 1 "register_operand" "x")))]
7673 "vpunpcklqdq\t{%1, %1, %0|%0, %1, %1}"
7674 [(set_attr "type" "sselog1")
7675 (set_attr "prefix" "vex")
7676 (set_attr "mode" "TI")])
7678 (define_insn "*vec_dupv2di"
7679 [(set (match_operand:V2DI 0 "register_operand" "=Y2,x")
7681 (match_operand:DI 1 "register_operand" " 0 ,0")))]
7686 [(set_attr "type" "sselog1,ssemov")
7687 (set_attr "mode" "TI,V4SF")])
7689 (define_insn "*vec_concatv2si_avx"
7690 [(set (match_operand:V2SI 0 "register_operand" "=x,x,x ,*y ,*y")
7692 (match_operand:SI 1 "nonimmediate_operand" "x ,x,rm, 0 ,rm")
7693 (match_operand:SI 2 "vector_move_operand" "rm,x,C ,*ym,C")))]
7696 vpinsrd\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
7697 vpunpckldq\t{%2, %1, %0|%0, %1, %2}
7698 vmovd\t{%1, %0|%0, %1}
7699 punpckldq\t{%2, %0|%0, %2}
7700 movd\t{%1, %0|%0, %1}"
7701 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
7702 (set_attr "prefix_extra" "1,*,*,*,*")
7703 (set_attr "length_immediate" "1,*,*,*,*")
7704 (set (attr "prefix")
7705 (if_then_else (eq_attr "alternative" "3,4")
7706 (const_string "orig")
7707 (const_string "vex")))
7708 (set_attr "mode" "TI,TI,TI,DI,DI")])
7710 (define_insn "*vec_concatv2si_sse4_1"
7711 [(set (match_operand:V2SI 0 "register_operand" "=x,x,x ,*y ,*y")
7713 (match_operand:SI 1 "nonimmediate_operand" "0 ,0,rm, 0 ,rm")
7714 (match_operand:SI 2 "vector_move_operand" "rm,x,C ,*ym,C")))]
7717 pinsrd\t{$0x1, %2, %0|%0, %2, 0x1}
7718 punpckldq\t{%2, %0|%0, %2}
7719 movd\t{%1, %0|%0, %1}
7720 punpckldq\t{%2, %0|%0, %2}
7721 movd\t{%1, %0|%0, %1}"
7722 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
7723 (set_attr "prefix_extra" "1,*,*,*,*")
7724 (set_attr "length_immediate" "1,*,*,*,*")
7725 (set_attr "mode" "TI,TI,TI,DI,DI")])
7727 ;; ??? In theory we can match memory for the MMX alternative, but allowing
7728 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
7729 ;; alternatives pretty much forces the MMX alternative to be chosen.
7730 (define_insn "*vec_concatv2si_sse2"
7731 [(set (match_operand:V2SI 0 "register_operand" "=x,x ,*y,*y")
7733 (match_operand:SI 1 "nonimmediate_operand" " 0,rm, 0,rm")
7734 (match_operand:SI 2 "reg_or_0_operand" " x,C ,*y, C")))]
7737 punpckldq\t{%2, %0|%0, %2}
7738 movd\t{%1, %0|%0, %1}
7739 punpckldq\t{%2, %0|%0, %2}
7740 movd\t{%1, %0|%0, %1}"
7741 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
7742 (set_attr "mode" "TI,TI,DI,DI")])
7744 (define_insn "*vec_concatv2si_sse"
7745 [(set (match_operand:V2SI 0 "register_operand" "=x,x,*y,*y")
7747 (match_operand:SI 1 "nonimmediate_operand" " 0,m, 0,*rm")
7748 (match_operand:SI 2 "reg_or_0_operand" " x,C,*y,C")))]
7751 unpcklps\t{%2, %0|%0, %2}
7752 movss\t{%1, %0|%0, %1}
7753 punpckldq\t{%2, %0|%0, %2}
7754 movd\t{%1, %0|%0, %1}"
7755 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
7756 (set_attr "mode" "V4SF,V4SF,DI,DI")])
7758 (define_insn "*vec_concatv4si_1_avx"
7759 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
7761 (match_operand:V2SI 1 "register_operand" " x,x")
7762 (match_operand:V2SI 2 "nonimmediate_operand" " x,m")))]
7765 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
7766 vmovhps\t{%2, %1, %0|%0, %1, %2}"
7767 [(set_attr "type" "sselog,ssemov")
7768 (set_attr "prefix" "vex")
7769 (set_attr "mode" "TI,V2SF")])
7771 (define_insn "*vec_concatv4si_1"
7772 [(set (match_operand:V4SI 0 "register_operand" "=Y2,x,x")
7774 (match_operand:V2SI 1 "register_operand" " 0 ,0,0")
7775 (match_operand:V2SI 2 "nonimmediate_operand" " Y2,x,m")))]
7778 punpcklqdq\t{%2, %0|%0, %2}
7779 movlhps\t{%2, %0|%0, %2}
7780 movhps\t{%2, %0|%0, %2}"
7781 [(set_attr "type" "sselog,ssemov,ssemov")
7782 (set_attr "mode" "TI,V4SF,V2SF")])
7784 (define_insn "*vec_concatv2di_avx"
7785 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,x,x")
7787 (match_operand:DI 1 "nonimmediate_operand" " m,*y,x,x")
7788 (match_operand:DI 2 "vector_move_operand" " C, C,x,m")))]
7789 "!TARGET_64BIT && TARGET_AVX"
7791 vmovq\t{%1, %0|%0, %1}
7792 movq2dq\t{%1, %0|%0, %1}
7793 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
7794 vmovhps\t{%2, %1, %0|%0, %1, %2}"
7795 [(set_attr "type" "ssemov,ssemov,sselog,ssemov")
7796 (set (attr "prefix")
7797 (if_then_else (eq_attr "alternative" "1")
7798 (const_string "orig")
7799 (const_string "vex")))
7800 (set_attr "mode" "TI,TI,TI,V2SF")])
7802 (define_insn "vec_concatv2di"
7803 [(set (match_operand:V2DI 0 "register_operand" "=Y2 ,?Y2,Y2,x,x")
7805 (match_operand:DI 1 "nonimmediate_operand" " mY2,*y ,0 ,0,0")
7806 (match_operand:DI 2 "vector_move_operand" " C , C,Y2,x,m")))]
7807 "!TARGET_64BIT && TARGET_SSE"
7809 movq\t{%1, %0|%0, %1}
7810 movq2dq\t{%1, %0|%0, %1}
7811 punpcklqdq\t{%2, %0|%0, %2}
7812 movlhps\t{%2, %0|%0, %2}
7813 movhps\t{%2, %0|%0, %2}"
7814 [(set_attr "type" "ssemov,ssemov,sselog,ssemov,ssemov")
7815 (set_attr "mode" "TI,TI,TI,V4SF,V2SF")])
7817 (define_insn "*vec_concatv2di_rex64_avx"
7818 [(set (match_operand:V2DI 0 "register_operand" "=x,x,Yi,!x,x,x")
7820 (match_operand:DI 1 "nonimmediate_operand" " x,m,r ,*y,x,x")
7821 (match_operand:DI 2 "vector_move_operand" "rm,C,C ,C ,x,m")))]
7822 "TARGET_64BIT && TARGET_AVX"
7824 vpinsrq\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
7825 vmovq\t{%1, %0|%0, %1}
7826 vmovq\t{%1, %0|%0, %1}
7827 movq2dq\t{%1, %0|%0, %1}
7828 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
7829 vmovhps\t{%2, %1, %0|%0, %1, %2}"
7830 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov")
7831 (set_attr "prefix_extra" "1,*,*,*,*,*")
7832 (set_attr "length_immediate" "1,*,*,*,*,*")
7833 (set (attr "prefix")
7834 (if_then_else (eq_attr "alternative" "3")
7835 (const_string "orig")
7836 (const_string "vex")))
7837 (set_attr "mode" "TI,TI,TI,TI,TI,V2SF")])
7839 (define_insn "*vec_concatv2di_rex64_sse4_1"
7840 [(set (match_operand:V2DI 0 "register_operand" "=x ,x ,Yi,!x,x,x,x")
7842 (match_operand:DI 1 "nonimmediate_operand" " 0 ,mx,r ,*y,0,0,0")
7843 (match_operand:DI 2 "vector_move_operand" " rm,C ,C ,C ,x,x,m")))]
7844 "TARGET_64BIT && TARGET_SSE4_1"
7846 pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
7847 movq\t{%1, %0|%0, %1}
7848 movq\t{%1, %0|%0, %1}
7849 movq2dq\t{%1, %0|%0, %1}
7850 punpcklqdq\t{%2, %0|%0, %2}
7851 movlhps\t{%2, %0|%0, %2}
7852 movhps\t{%2, %0|%0, %2}"
7853 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
7854 (set_attr "prefix_rex" "1,*,1,*,*,*,*")
7855 (set_attr "prefix_extra" "1,*,*,*,*,*,*")
7856 (set_attr "length_immediate" "1,*,*,*,*,*,*")
7857 (set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
7859 (define_insn "*vec_concatv2di_rex64_sse"
7860 [(set (match_operand:V2DI 0 "register_operand" "=Y2 ,Yi,!Y2,Y2,x,x")
7862 (match_operand:DI 1 "nonimmediate_operand" " mY2,r ,*y ,0 ,0,0")
7863 (match_operand:DI 2 "vector_move_operand" " C ,C ,C ,Y2,x,m")))]
7864 "TARGET_64BIT && TARGET_SSE"
7866 movq\t{%1, %0|%0, %1}
7867 movq\t{%1, %0|%0, %1}
7868 movq2dq\t{%1, %0|%0, %1}
7869 punpcklqdq\t{%2, %0|%0, %2}
7870 movlhps\t{%2, %0|%0, %2}
7871 movhps\t{%2, %0|%0, %2}"
7872 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
7873 (set_attr "prefix_rex" "*,1,*,*,*,*")
7874 (set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF")])
7876 (define_expand "vec_unpacku_hi_v16qi"
7877 [(match_operand:V8HI 0 "register_operand" "")
7878 (match_operand:V16QI 1 "register_operand" "")]
7882 ix86_expand_sse4_unpack (operands, true, true);
7884 ix86_expand_sse_unpack (operands, true, true);
7888 (define_expand "vec_unpacks_hi_v16qi"
7889 [(match_operand:V8HI 0 "register_operand" "")
7890 (match_operand:V16QI 1 "register_operand" "")]
7894 ix86_expand_sse4_unpack (operands, false, true);
7896 ix86_expand_sse_unpack (operands, false, true);
7900 (define_expand "vec_unpacku_lo_v16qi"
7901 [(match_operand:V8HI 0 "register_operand" "")
7902 (match_operand:V16QI 1 "register_operand" "")]
7906 ix86_expand_sse4_unpack (operands, true, false);
7908 ix86_expand_sse_unpack (operands, true, false);
7912 (define_expand "vec_unpacks_lo_v16qi"
7913 [(match_operand:V8HI 0 "register_operand" "")
7914 (match_operand:V16QI 1 "register_operand" "")]
7918 ix86_expand_sse4_unpack (operands, false, false);
7920 ix86_expand_sse_unpack (operands, false, false);
7924 (define_expand "vec_unpacku_hi_v8hi"
7925 [(match_operand:V4SI 0 "register_operand" "")
7926 (match_operand:V8HI 1 "register_operand" "")]
7930 ix86_expand_sse4_unpack (operands, true, true);
7932 ix86_expand_sse_unpack (operands, true, true);
7936 (define_expand "vec_unpacks_hi_v8hi"
7937 [(match_operand:V4SI 0 "register_operand" "")
7938 (match_operand:V8HI 1 "register_operand" "")]
7942 ix86_expand_sse4_unpack (operands, false, true);
7944 ix86_expand_sse_unpack (operands, false, true);
7948 (define_expand "vec_unpacku_lo_v8hi"
7949 [(match_operand:V4SI 0 "register_operand" "")
7950 (match_operand:V8HI 1 "register_operand" "")]
7954 ix86_expand_sse4_unpack (operands, true, false);
7956 ix86_expand_sse_unpack (operands, true, false);
7960 (define_expand "vec_unpacks_lo_v8hi"
7961 [(match_operand:V4SI 0 "register_operand" "")
7962 (match_operand:V8HI 1 "register_operand" "")]
7966 ix86_expand_sse4_unpack (operands, false, false);
7968 ix86_expand_sse_unpack (operands, false, false);
7972 (define_expand "vec_unpacku_hi_v4si"
7973 [(match_operand:V2DI 0 "register_operand" "")
7974 (match_operand:V4SI 1 "register_operand" "")]
7978 ix86_expand_sse4_unpack (operands, true, true);
7980 ix86_expand_sse_unpack (operands, true, true);
7984 (define_expand "vec_unpacks_hi_v4si"
7985 [(match_operand:V2DI 0 "register_operand" "")
7986 (match_operand:V4SI 1 "register_operand" "")]
7990 ix86_expand_sse4_unpack (operands, false, true);
7992 ix86_expand_sse_unpack (operands, false, true);
7996 (define_expand "vec_unpacku_lo_v4si"
7997 [(match_operand:V2DI 0 "register_operand" "")
7998 (match_operand:V4SI 1 "register_operand" "")]
8002 ix86_expand_sse4_unpack (operands, true, false);
8004 ix86_expand_sse_unpack (operands, true, false);
8008 (define_expand "vec_unpacks_lo_v4si"
8009 [(match_operand:V2DI 0 "register_operand" "")
8010 (match_operand:V4SI 1 "register_operand" "")]
8014 ix86_expand_sse4_unpack (operands, false, false);
8016 ix86_expand_sse_unpack (operands, false, false);
8020 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8024 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8026 (define_expand "sse2_uavgv16qi3"
8027 [(set (match_operand:V16QI 0 "register_operand" "")
8033 (match_operand:V16QI 1 "nonimmediate_operand" ""))
8035 (match_operand:V16QI 2 "nonimmediate_operand" "")))
8036 (const_vector:V16QI [(const_int 1) (const_int 1)
8037 (const_int 1) (const_int 1)
8038 (const_int 1) (const_int 1)
8039 (const_int 1) (const_int 1)
8040 (const_int 1) (const_int 1)
8041 (const_int 1) (const_int 1)
8042 (const_int 1) (const_int 1)
8043 (const_int 1) (const_int 1)]))
8046 "ix86_fixup_binary_operands_no_copy (PLUS, V16QImode, operands);")
8048 (define_insn "*avx_uavgv16qi3"
8049 [(set (match_operand:V16QI 0 "register_operand" "=x")
8055 (match_operand:V16QI 1 "nonimmediate_operand" "%x"))
8057 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
8058 (const_vector:V16QI [(const_int 1) (const_int 1)
8059 (const_int 1) (const_int 1)
8060 (const_int 1) (const_int 1)
8061 (const_int 1) (const_int 1)
8062 (const_int 1) (const_int 1)
8063 (const_int 1) (const_int 1)
8064 (const_int 1) (const_int 1)
8065 (const_int 1) (const_int 1)]))
8067 "TARGET_AVX && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
8068 "vpavgb\t{%2, %1, %0|%0, %1, %2}"
8069 [(set_attr "type" "sseiadd")
8070 (set_attr "prefix" "vex")
8071 (set_attr "mode" "TI")])
8073 (define_insn "*sse2_uavgv16qi3"
8074 [(set (match_operand:V16QI 0 "register_operand" "=x")
8080 (match_operand:V16QI 1 "nonimmediate_operand" "%0"))
8082 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
8083 (const_vector:V16QI [(const_int 1) (const_int 1)
8084 (const_int 1) (const_int 1)
8085 (const_int 1) (const_int 1)
8086 (const_int 1) (const_int 1)
8087 (const_int 1) (const_int 1)
8088 (const_int 1) (const_int 1)
8089 (const_int 1) (const_int 1)
8090 (const_int 1) (const_int 1)]))
8092 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
8093 "pavgb\t{%2, %0|%0, %2}"
8094 [(set_attr "type" "sseiadd")
8095 (set_attr "prefix_data16" "1")
8096 (set_attr "mode" "TI")])
8098 (define_expand "sse2_uavgv8hi3"
8099 [(set (match_operand:V8HI 0 "register_operand" "")
8105 (match_operand:V8HI 1 "nonimmediate_operand" ""))
8107 (match_operand:V8HI 2 "nonimmediate_operand" "")))
8108 (const_vector:V8HI [(const_int 1) (const_int 1)
8109 (const_int 1) (const_int 1)
8110 (const_int 1) (const_int 1)
8111 (const_int 1) (const_int 1)]))
8114 "ix86_fixup_binary_operands_no_copy (PLUS, V8HImode, operands);")
8116 (define_insn "*avx_uavgv8hi3"
8117 [(set (match_operand:V8HI 0 "register_operand" "=x")
8123 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
8125 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
8126 (const_vector:V8HI [(const_int 1) (const_int 1)
8127 (const_int 1) (const_int 1)
8128 (const_int 1) (const_int 1)
8129 (const_int 1) (const_int 1)]))
8131 "TARGET_AVX && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
8132 "vpavgw\t{%2, %1, %0|%0, %1, %2}"
8133 [(set_attr "type" "sseiadd")
8134 (set_attr "prefix" "vex")
8135 (set_attr "mode" "TI")])
8137 (define_insn "*sse2_uavgv8hi3"
8138 [(set (match_operand:V8HI 0 "register_operand" "=x")
8144 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
8146 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
8147 (const_vector:V8HI [(const_int 1) (const_int 1)
8148 (const_int 1) (const_int 1)
8149 (const_int 1) (const_int 1)
8150 (const_int 1) (const_int 1)]))
8152 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
8153 "pavgw\t{%2, %0|%0, %2}"
8154 [(set_attr "type" "sseiadd")
8155 (set_attr "prefix_data16" "1")
8156 (set_attr "mode" "TI")])
8158 ;; The correct representation for this is absolutely enormous, and
8159 ;; surely not generally useful.
8160 (define_insn "*avx_psadbw"
8161 [(set (match_operand:V2DI 0 "register_operand" "=x")
8162 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "x")
8163 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
8166 "vpsadbw\t{%2, %1, %0|%0, %1, %2}"
8167 [(set_attr "type" "sseiadd")
8168 (set_attr "prefix" "vex")
8169 (set_attr "mode" "TI")])
8171 (define_insn "sse2_psadbw"
8172 [(set (match_operand:V2DI 0 "register_operand" "=x")
8173 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
8174 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
8177 "psadbw\t{%2, %0|%0, %2}"
8178 [(set_attr "type" "sseiadd")
8179 (set_attr "atom_unit" "simul")
8180 (set_attr "prefix_data16" "1")
8181 (set_attr "mode" "TI")])
8183 (define_insn "avx_movmskp<avxmodesuffixf2c>256"
8184 [(set (match_operand:SI 0 "register_operand" "=r")
8186 [(match_operand:AVX256MODEF2P 1 "register_operand" "x")]
8188 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
8189 "vmovmskp<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
8190 [(set_attr "type" "ssecvt")
8191 (set_attr "prefix" "vex")
8192 (set_attr "mode" "<MODE>")])
8194 (define_insn "<sse>_movmskp<ssemodesuffixf2c>"
8195 [(set (match_operand:SI 0 "register_operand" "=r")
8197 [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
8199 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
8200 "%vmovmskp<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
8201 [(set_attr "type" "ssemov")
8202 (set_attr "prefix" "maybe_vex")
8203 (set_attr "mode" "<MODE>")])
8205 (define_insn "sse2_pmovmskb"
8206 [(set (match_operand:SI 0 "register_operand" "=r")
8207 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
8210 "%vpmovmskb\t{%1, %0|%0, %1}"
8211 [(set_attr "type" "ssemov")
8212 (set_attr "prefix_data16" "1")
8213 (set_attr "prefix" "maybe_vex")
8214 (set_attr "mode" "SI")])
8216 (define_expand "sse2_maskmovdqu"
8217 [(set (match_operand:V16QI 0 "memory_operand" "")
8218 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
8219 (match_operand:V16QI 2 "register_operand" "")
8225 (define_insn "*sse2_maskmovdqu"
8226 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
8227 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
8228 (match_operand:V16QI 2 "register_operand" "x")
8229 (mem:V16QI (match_dup 0))]
8231 "TARGET_SSE2 && !TARGET_64BIT"
8232 ;; @@@ check ordering of operands in intel/nonintel syntax
8233 "%vmaskmovdqu\t{%2, %1|%1, %2}"
8234 [(set_attr "type" "ssemov")
8235 (set_attr "prefix_data16" "1")
8236 ;; The implicit %rdi operand confuses default length_vex computation.
8237 (set_attr "length_vex" "3")
8238 (set_attr "prefix" "maybe_vex")
8239 (set_attr "mode" "TI")])
8241 (define_insn "*sse2_maskmovdqu_rex64"
8242 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
8243 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
8244 (match_operand:V16QI 2 "register_operand" "x")
8245 (mem:V16QI (match_dup 0))]
8247 "TARGET_SSE2 && TARGET_64BIT"
8248 ;; @@@ check ordering of operands in intel/nonintel syntax
8249 "%vmaskmovdqu\t{%2, %1|%1, %2}"
8250 [(set_attr "type" "ssemov")
8251 (set_attr "prefix_data16" "1")
8252 ;; The implicit %rdi operand confuses default length_vex computation.
8253 (set (attr "length_vex")
8254 (symbol_ref ("REGNO (operands[2]) >= FIRST_REX_SSE_REG ? 3 + 1 : 2 + 1")))
8255 (set_attr "prefix" "maybe_vex")
8256 (set_attr "mode" "TI")])
8258 (define_insn "sse_ldmxcsr"
8259 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
8263 [(set_attr "type" "sse")
8264 (set_attr "atom_sse_attr" "mxcsr")
8265 (set_attr "prefix" "maybe_vex")
8266 (set_attr "memory" "load")])
8268 (define_insn "sse_stmxcsr"
8269 [(set (match_operand:SI 0 "memory_operand" "=m")
8270 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
8273 [(set_attr "type" "sse")
8274 (set_attr "atom_sse_attr" "mxcsr")
8275 (set_attr "prefix" "maybe_vex")
8276 (set_attr "memory" "store")])
8278 (define_expand "sse_sfence"
8280 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
8281 "TARGET_SSE || TARGET_3DNOW_A"
8283 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8284 MEM_VOLATILE_P (operands[0]) = 1;
8287 (define_insn "*sse_sfence"
8288 [(set (match_operand:BLK 0 "" "")
8289 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
8290 "TARGET_SSE || TARGET_3DNOW_A"
8292 [(set_attr "type" "sse")
8293 (set_attr "length_address" "0")
8294 (set_attr "atom_sse_attr" "fence")
8295 (set_attr "memory" "unknown")])
8297 (define_insn "sse2_clflush"
8298 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
8302 [(set_attr "type" "sse")
8303 (set_attr "atom_sse_attr" "fence")
8304 (set_attr "memory" "unknown")])
8306 (define_expand "sse2_mfence"
8308 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
8311 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8312 MEM_VOLATILE_P (operands[0]) = 1;
8315 (define_insn "*sse2_mfence"
8316 [(set (match_operand:BLK 0 "" "")
8317 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
8318 "TARGET_64BIT || TARGET_SSE2"
8320 [(set_attr "type" "sse")
8321 (set_attr "length_address" "0")
8322 (set_attr "atom_sse_attr" "fence")
8323 (set_attr "memory" "unknown")])
8325 (define_expand "sse2_lfence"
8327 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
8330 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
8331 MEM_VOLATILE_P (operands[0]) = 1;
8334 (define_insn "*sse2_lfence"
8335 [(set (match_operand:BLK 0 "" "")
8336 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
8339 [(set_attr "type" "sse")
8340 (set_attr "length_address" "0")
8341 (set_attr "atom_sse_attr" "lfence")
8342 (set_attr "memory" "unknown")])
8344 (define_insn "sse3_mwait"
8345 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
8346 (match_operand:SI 1 "register_operand" "c")]
8349 ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.
8350 ;; Since 32bit register operands are implicitly zero extended to 64bit,
8351 ;; we only need to set up 32bit registers.
8353 [(set_attr "length" "3")])
8355 (define_insn "sse3_monitor"
8356 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
8357 (match_operand:SI 1 "register_operand" "c")
8358 (match_operand:SI 2 "register_operand" "d")]
8360 "TARGET_SSE3 && !TARGET_64BIT"
8361 "monitor\t%0, %1, %2"
8362 [(set_attr "length" "3")])
8364 (define_insn "sse3_monitor64"
8365 [(unspec_volatile [(match_operand:DI 0 "register_operand" "a")
8366 (match_operand:SI 1 "register_operand" "c")
8367 (match_operand:SI 2 "register_operand" "d")]
8369 "TARGET_SSE3 && TARGET_64BIT"
8370 ;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in
8371 ;; RCX and RDX are used. Since 32bit register operands are implicitly
8372 ;; zero extended to 64bit, we only need to set up 32bit registers.
8374 [(set_attr "length" "3")])
8376 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8378 ;; SSSE3 instructions
8380 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8382 (define_insn "*avx_phaddwv8hi3"
8383 [(set (match_operand:V8HI 0 "register_operand" "=x")
8389 (match_operand:V8HI 1 "register_operand" "x")
8390 (parallel [(const_int 0)]))
8391 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8393 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8394 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8397 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8398 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8400 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8401 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8406 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8407 (parallel [(const_int 0)]))
8408 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8410 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8411 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8414 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8415 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8417 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8418 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8420 "vphaddw\t{%2, %1, %0|%0, %1, %2}"
8421 [(set_attr "type" "sseiadd")
8422 (set_attr "prefix_extra" "1")
8423 (set_attr "prefix" "vex")
8424 (set_attr "mode" "TI")])
8426 (define_insn "ssse3_phaddwv8hi3"
8427 [(set (match_operand:V8HI 0 "register_operand" "=x")
8433 (match_operand:V8HI 1 "register_operand" "0")
8434 (parallel [(const_int 0)]))
8435 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8437 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8438 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8441 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8442 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8444 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8445 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8450 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8451 (parallel [(const_int 0)]))
8452 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8454 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8455 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8458 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8459 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8461 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8462 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8464 "phaddw\t{%2, %0|%0, %2}"
8465 [(set_attr "type" "sseiadd")
8466 (set_attr "atom_unit" "complex")
8467 (set_attr "prefix_data16" "1")
8468 (set_attr "prefix_extra" "1")
8469 (set_attr "mode" "TI")])
8471 (define_insn "ssse3_phaddwv4hi3"
8472 [(set (match_operand:V4HI 0 "register_operand" "=y")
8477 (match_operand:V4HI 1 "register_operand" "0")
8478 (parallel [(const_int 0)]))
8479 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8481 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8482 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8486 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
8487 (parallel [(const_int 0)]))
8488 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8490 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8491 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
8493 "phaddw\t{%2, %0|%0, %2}"
8494 [(set_attr "type" "sseiadd")
8495 (set_attr "atom_unit" "complex")
8496 (set_attr "prefix_extra" "1")
8497 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8498 (set_attr "mode" "DI")])
8500 (define_insn "*avx_phadddv4si3"
8501 [(set (match_operand:V4SI 0 "register_operand" "=x")
8506 (match_operand:V4SI 1 "register_operand" "x")
8507 (parallel [(const_int 0)]))
8508 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8510 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
8511 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
8515 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
8516 (parallel [(const_int 0)]))
8517 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
8519 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
8520 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
8522 "vphaddd\t{%2, %1, %0|%0, %1, %2}"
8523 [(set_attr "type" "sseiadd")
8524 (set_attr "prefix_extra" "1")
8525 (set_attr "prefix" "vex")
8526 (set_attr "mode" "TI")])
8528 (define_insn "ssse3_phadddv4si3"
8529 [(set (match_operand:V4SI 0 "register_operand" "=x")
8534 (match_operand:V4SI 1 "register_operand" "0")
8535 (parallel [(const_int 0)]))
8536 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8538 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
8539 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
8543 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
8544 (parallel [(const_int 0)]))
8545 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
8547 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
8548 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
8550 "phaddd\t{%2, %0|%0, %2}"
8551 [(set_attr "type" "sseiadd")
8552 (set_attr "atom_unit" "complex")
8553 (set_attr "prefix_data16" "1")
8554 (set_attr "prefix_extra" "1")
8555 (set_attr "mode" "TI")])
8557 (define_insn "ssse3_phadddv2si3"
8558 [(set (match_operand:V2SI 0 "register_operand" "=y")
8562 (match_operand:V2SI 1 "register_operand" "0")
8563 (parallel [(const_int 0)]))
8564 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8567 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
8568 (parallel [(const_int 0)]))
8569 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
8571 "phaddd\t{%2, %0|%0, %2}"
8572 [(set_attr "type" "sseiadd")
8573 (set_attr "atom_unit" "complex")
8574 (set_attr "prefix_extra" "1")
8575 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8576 (set_attr "mode" "DI")])
8578 (define_insn "*avx_phaddswv8hi3"
8579 [(set (match_operand:V8HI 0 "register_operand" "=x")
8585 (match_operand:V8HI 1 "register_operand" "x")
8586 (parallel [(const_int 0)]))
8587 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8589 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8590 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8593 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8594 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8596 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8597 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8602 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8603 (parallel [(const_int 0)]))
8604 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8606 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8607 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8610 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8611 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8613 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8614 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8616 "vphaddsw\t{%2, %1, %0|%0, %1, %2}"
8617 [(set_attr "type" "sseiadd")
8618 (set_attr "prefix_extra" "1")
8619 (set_attr "prefix" "vex")
8620 (set_attr "mode" "TI")])
8622 (define_insn "ssse3_phaddswv8hi3"
8623 [(set (match_operand:V8HI 0 "register_operand" "=x")
8629 (match_operand:V8HI 1 "register_operand" "0")
8630 (parallel [(const_int 0)]))
8631 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8633 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8634 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8637 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8638 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8640 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8641 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8646 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8647 (parallel [(const_int 0)]))
8648 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8650 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8651 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8654 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8655 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8657 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8658 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8660 "phaddsw\t{%2, %0|%0, %2}"
8661 [(set_attr "type" "sseiadd")
8662 (set_attr "atom_unit" "complex")
8663 (set_attr "prefix_data16" "1")
8664 (set_attr "prefix_extra" "1")
8665 (set_attr "mode" "TI")])
8667 (define_insn "ssse3_phaddswv4hi3"
8668 [(set (match_operand:V4HI 0 "register_operand" "=y")
8673 (match_operand:V4HI 1 "register_operand" "0")
8674 (parallel [(const_int 0)]))
8675 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8677 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8678 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8682 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
8683 (parallel [(const_int 0)]))
8684 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8686 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8687 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
8689 "phaddsw\t{%2, %0|%0, %2}"
8690 [(set_attr "type" "sseiadd")
8691 (set_attr "atom_unit" "complex")
8692 (set_attr "prefix_extra" "1")
8693 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8694 (set_attr "mode" "DI")])
8696 (define_insn "*avx_phsubwv8hi3"
8697 [(set (match_operand:V8HI 0 "register_operand" "=x")
8703 (match_operand:V8HI 1 "register_operand" "x")
8704 (parallel [(const_int 0)]))
8705 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8707 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8708 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8711 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8712 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8714 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8715 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8720 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8721 (parallel [(const_int 0)]))
8722 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8724 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8725 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8728 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8729 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8731 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8732 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8734 "vphsubw\t{%2, %1, %0|%0, %1, %2}"
8735 [(set_attr "type" "sseiadd")
8736 (set_attr "prefix_extra" "1")
8737 (set_attr "prefix" "vex")
8738 (set_attr "mode" "TI")])
8740 (define_insn "ssse3_phsubwv8hi3"
8741 [(set (match_operand:V8HI 0 "register_operand" "=x")
8747 (match_operand:V8HI 1 "register_operand" "0")
8748 (parallel [(const_int 0)]))
8749 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8751 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8752 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8755 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8756 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8758 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8759 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8764 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8765 (parallel [(const_int 0)]))
8766 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8768 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8769 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8772 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8773 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8775 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8776 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8778 "phsubw\t{%2, %0|%0, %2}"
8779 [(set_attr "type" "sseiadd")
8780 (set_attr "atom_unit" "complex")
8781 (set_attr "prefix_data16" "1")
8782 (set_attr "prefix_extra" "1")
8783 (set_attr "mode" "TI")])
8785 (define_insn "ssse3_phsubwv4hi3"
8786 [(set (match_operand:V4HI 0 "register_operand" "=y")
8791 (match_operand:V4HI 1 "register_operand" "0")
8792 (parallel [(const_int 0)]))
8793 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8795 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8796 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8800 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
8801 (parallel [(const_int 0)]))
8802 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8804 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8805 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
8807 "phsubw\t{%2, %0|%0, %2}"
8808 [(set_attr "type" "sseiadd")
8809 (set_attr "atom_unit" "complex")
8810 (set_attr "prefix_extra" "1")
8811 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8812 (set_attr "mode" "DI")])
8814 (define_insn "*avx_phsubdv4si3"
8815 [(set (match_operand:V4SI 0 "register_operand" "=x")
8820 (match_operand:V4SI 1 "register_operand" "x")
8821 (parallel [(const_int 0)]))
8822 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8824 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
8825 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
8829 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
8830 (parallel [(const_int 0)]))
8831 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
8833 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
8834 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
8836 "vphsubd\t{%2, %1, %0|%0, %1, %2}"
8837 [(set_attr "type" "sseiadd")
8838 (set_attr "prefix_extra" "1")
8839 (set_attr "prefix" "vex")
8840 (set_attr "mode" "TI")])
8842 (define_insn "ssse3_phsubdv4si3"
8843 [(set (match_operand:V4SI 0 "register_operand" "=x")
8848 (match_operand:V4SI 1 "register_operand" "0")
8849 (parallel [(const_int 0)]))
8850 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8852 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
8853 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
8857 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
8858 (parallel [(const_int 0)]))
8859 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
8861 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
8862 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
8864 "phsubd\t{%2, %0|%0, %2}"
8865 [(set_attr "type" "sseiadd")
8866 (set_attr "atom_unit" "complex")
8867 (set_attr "prefix_data16" "1")
8868 (set_attr "prefix_extra" "1")
8869 (set_attr "mode" "TI")])
8871 (define_insn "ssse3_phsubdv2si3"
8872 [(set (match_operand:V2SI 0 "register_operand" "=y")
8876 (match_operand:V2SI 1 "register_operand" "0")
8877 (parallel [(const_int 0)]))
8878 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
8881 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
8882 (parallel [(const_int 0)]))
8883 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
8885 "phsubd\t{%2, %0|%0, %2}"
8886 [(set_attr "type" "sseiadd")
8887 (set_attr "atom_unit" "complex")
8888 (set_attr "prefix_extra" "1")
8889 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8890 (set_attr "mode" "DI")])
8892 (define_insn "*avx_phsubswv8hi3"
8893 [(set (match_operand:V8HI 0 "register_operand" "=x")
8899 (match_operand:V8HI 1 "register_operand" "x")
8900 (parallel [(const_int 0)]))
8901 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8903 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8904 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8907 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8908 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8910 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8911 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8916 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8917 (parallel [(const_int 0)]))
8918 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8920 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8921 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8924 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8925 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8927 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8928 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8930 "vphsubsw\t{%2, %1, %0|%0, %1, %2}"
8931 [(set_attr "type" "sseiadd")
8932 (set_attr "prefix_extra" "1")
8933 (set_attr "prefix" "vex")
8934 (set_attr "mode" "TI")])
8936 (define_insn "ssse3_phsubswv8hi3"
8937 [(set (match_operand:V8HI 0 "register_operand" "=x")
8943 (match_operand:V8HI 1 "register_operand" "0")
8944 (parallel [(const_int 0)]))
8945 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8947 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8948 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8951 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
8952 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
8954 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
8955 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
8960 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8961 (parallel [(const_int 0)]))
8962 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
8964 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
8965 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
8968 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
8969 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
8971 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
8972 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
8974 "phsubsw\t{%2, %0|%0, %2}"
8975 [(set_attr "type" "sseiadd")
8976 (set_attr "atom_unit" "complex")
8977 (set_attr "prefix_data16" "1")
8978 (set_attr "prefix_extra" "1")
8979 (set_attr "mode" "TI")])
8981 (define_insn "ssse3_phsubswv4hi3"
8982 [(set (match_operand:V4HI 0 "register_operand" "=y")
8987 (match_operand:V4HI 1 "register_operand" "0")
8988 (parallel [(const_int 0)]))
8989 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
8991 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
8992 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
8996 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
8997 (parallel [(const_int 0)]))
8998 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
9000 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
9001 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
9003 "phsubsw\t{%2, %0|%0, %2}"
9004 [(set_attr "type" "sseiadd")
9005 (set_attr "atom_unit" "complex")
9006 (set_attr "prefix_extra" "1")
9007 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
9008 (set_attr "mode" "DI")])
9010 (define_insn "*avx_pmaddubsw128"
9011 [(set (match_operand:V8HI 0 "register_operand" "=x")
9016 (match_operand:V16QI 1 "register_operand" "x")
9017 (parallel [(const_int 0)
9027 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9028 (parallel [(const_int 0)
9038 (vec_select:V16QI (match_dup 1)
9039 (parallel [(const_int 1)
9048 (vec_select:V16QI (match_dup 2)
9049 (parallel [(const_int 1)
9056 (const_int 15)]))))))]
9058 "vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
9059 [(set_attr "type" "sseiadd")
9060 (set_attr "prefix_extra" "1")
9061 (set_attr "prefix" "vex")
9062 (set_attr "mode" "TI")])
9064 (define_insn "ssse3_pmaddubsw128"
9065 [(set (match_operand:V8HI 0 "register_operand" "=x")
9070 (match_operand:V16QI 1 "register_operand" "0")
9071 (parallel [(const_int 0)
9081 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9082 (parallel [(const_int 0)
9092 (vec_select:V16QI (match_dup 1)
9093 (parallel [(const_int 1)
9102 (vec_select:V16QI (match_dup 2)
9103 (parallel [(const_int 1)
9110 (const_int 15)]))))))]
9112 "pmaddubsw\t{%2, %0|%0, %2}"
9113 [(set_attr "type" "sseiadd")
9114 (set_attr "atom_unit" "simul")
9115 (set_attr "prefix_data16" "1")
9116 (set_attr "prefix_extra" "1")
9117 (set_attr "mode" "TI")])
9119 (define_insn "ssse3_pmaddubsw"
9120 [(set (match_operand:V4HI 0 "register_operand" "=y")
9125 (match_operand:V8QI 1 "register_operand" "0")
9126 (parallel [(const_int 0)
9132 (match_operand:V8QI 2 "nonimmediate_operand" "ym")
9133 (parallel [(const_int 0)
9139 (vec_select:V8QI (match_dup 1)
9140 (parallel [(const_int 1)
9145 (vec_select:V8QI (match_dup 2)
9146 (parallel [(const_int 1)
9149 (const_int 7)]))))))]
9151 "pmaddubsw\t{%2, %0|%0, %2}"
9152 [(set_attr "type" "sseiadd")
9153 (set_attr "atom_unit" "simul")
9154 (set_attr "prefix_extra" "1")
9155 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
9156 (set_attr "mode" "DI")])
9158 (define_expand "ssse3_pmulhrswv8hi3"
9159 [(set (match_operand:V8HI 0 "register_operand" "")
9166 (match_operand:V8HI 1 "nonimmediate_operand" ""))
9168 (match_operand:V8HI 2 "nonimmediate_operand" "")))
9170 (const_vector:V8HI [(const_int 1) (const_int 1)
9171 (const_int 1) (const_int 1)
9172 (const_int 1) (const_int 1)
9173 (const_int 1) (const_int 1)]))
9176 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
9178 (define_insn "*avx_pmulhrswv8hi3"
9179 [(set (match_operand:V8HI 0 "register_operand" "=x")
9186 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
9188 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
9190 (const_vector:V8HI [(const_int 1) (const_int 1)
9191 (const_int 1) (const_int 1)
9192 (const_int 1) (const_int 1)
9193 (const_int 1) (const_int 1)]))
9195 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
9196 "vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
9197 [(set_attr "type" "sseimul")
9198 (set_attr "prefix_extra" "1")
9199 (set_attr "prefix" "vex")
9200 (set_attr "mode" "TI")])
9202 (define_insn "*ssse3_pmulhrswv8hi3"
9203 [(set (match_operand:V8HI 0 "register_operand" "=x")
9210 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
9212 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
9214 (const_vector:V8HI [(const_int 1) (const_int 1)
9215 (const_int 1) (const_int 1)
9216 (const_int 1) (const_int 1)
9217 (const_int 1) (const_int 1)]))
9219 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
9220 "pmulhrsw\t{%2, %0|%0, %2}"
9221 [(set_attr "type" "sseimul")
9222 (set_attr "prefix_data16" "1")
9223 (set_attr "prefix_extra" "1")
9224 (set_attr "mode" "TI")])
9226 (define_expand "ssse3_pmulhrswv4hi3"
9227 [(set (match_operand:V4HI 0 "register_operand" "")
9234 (match_operand:V4HI 1 "nonimmediate_operand" ""))
9236 (match_operand:V4HI 2 "nonimmediate_operand" "")))
9238 (const_vector:V4HI [(const_int 1) (const_int 1)
9239 (const_int 1) (const_int 1)]))
9242 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
9244 (define_insn "*ssse3_pmulhrswv4hi3"
9245 [(set (match_operand:V4HI 0 "register_operand" "=y")
9252 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
9254 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
9256 (const_vector:V4HI [(const_int 1) (const_int 1)
9257 (const_int 1) (const_int 1)]))
9259 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
9260 "pmulhrsw\t{%2, %0|%0, %2}"
9261 [(set_attr "type" "sseimul")
9262 (set_attr "prefix_extra" "1")
9263 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
9264 (set_attr "mode" "DI")])
9266 (define_insn "*avx_pshufbv16qi3"
9267 [(set (match_operand:V16QI 0 "register_operand" "=x")
9268 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
9269 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
9272 "vpshufb\t{%2, %1, %0|%0, %1, %2}";
9273 [(set_attr "type" "sselog1")
9274 (set_attr "prefix_extra" "1")
9275 (set_attr "prefix" "vex")
9276 (set_attr "mode" "TI")])
9278 (define_insn "ssse3_pshufbv16qi3"
9279 [(set (match_operand:V16QI 0 "register_operand" "=x")
9280 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
9281 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
9284 "pshufb\t{%2, %0|%0, %2}";
9285 [(set_attr "type" "sselog1")
9286 (set_attr "prefix_data16" "1")
9287 (set_attr "prefix_extra" "1")
9288 (set_attr "mode" "TI")])
9290 (define_insn "ssse3_pshufbv8qi3"
9291 [(set (match_operand:V8QI 0 "register_operand" "=y")
9292 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
9293 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
9296 "pshufb\t{%2, %0|%0, %2}";
9297 [(set_attr "type" "sselog1")
9298 (set_attr "prefix_extra" "1")
9299 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
9300 (set_attr "mode" "DI")])
9302 (define_insn "*avx_psign<mode>3"
9303 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
9305 [(match_operand:SSEMODE124 1 "register_operand" "x")
9306 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
9309 "vpsign<ssevecsize>\t{%2, %1, %0|%0, %1, %2}";
9310 [(set_attr "type" "sselog1")
9311 (set_attr "prefix_extra" "1")
9312 (set_attr "prefix" "vex")
9313 (set_attr "mode" "TI")])
9315 (define_insn "ssse3_psign<mode>3"
9316 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
9318 [(match_operand:SSEMODE124 1 "register_operand" "0")
9319 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
9322 "psign<ssevecsize>\t{%2, %0|%0, %2}";
9323 [(set_attr "type" "sselog1")
9324 (set_attr "prefix_data16" "1")
9325 (set_attr "prefix_extra" "1")
9326 (set_attr "mode" "TI")])
9328 (define_insn "ssse3_psign<mode>3"
9329 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
9331 [(match_operand:MMXMODEI 1 "register_operand" "0")
9332 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
9335 "psign<mmxvecsize>\t{%2, %0|%0, %2}";
9336 [(set_attr "type" "sselog1")
9337 (set_attr "prefix_extra" "1")
9338 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
9339 (set_attr "mode" "DI")])
9341 (define_insn "*avx_palignrti"
9342 [(set (match_operand:TI 0 "register_operand" "=x")
9343 (unspec:TI [(match_operand:TI 1 "register_operand" "x")
9344 (match_operand:TI 2 "nonimmediate_operand" "xm")
9345 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
9349 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
9350 return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
9352 [(set_attr "type" "sseishft")
9353 (set_attr "prefix_extra" "1")
9354 (set_attr "length_immediate" "1")
9355 (set_attr "prefix" "vex")
9356 (set_attr "mode" "TI")])
9358 (define_insn "ssse3_palignrti"
9359 [(set (match_operand:TI 0 "register_operand" "=x")
9360 (unspec:TI [(match_operand:TI 1 "register_operand" "0")
9361 (match_operand:TI 2 "nonimmediate_operand" "xm")
9362 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
9366 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
9367 return "palignr\t{%3, %2, %0|%0, %2, %3}";
9369 [(set_attr "type" "sseishft")
9370 (set_attr "atom_unit" "sishuf")
9371 (set_attr "prefix_data16" "1")
9372 (set_attr "prefix_extra" "1")
9373 (set_attr "length_immediate" "1")
9374 (set_attr "mode" "TI")])
9376 (define_insn "ssse3_palignrdi"
9377 [(set (match_operand:DI 0 "register_operand" "=y")
9378 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
9379 (match_operand:DI 2 "nonimmediate_operand" "ym")
9380 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
9384 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
9385 return "palignr\t{%3, %2, %0|%0, %2, %3}";
9387 [(set_attr "type" "sseishft")
9388 (set_attr "atom_unit" "sishuf")
9389 (set_attr "prefix_extra" "1")
9390 (set_attr "length_immediate" "1")
9391 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
9392 (set_attr "mode" "DI")])
9394 (define_insn "abs<mode>2"
9395 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
9396 (abs:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
9398 "%vpabs<ssevecsize>\t{%1, %0|%0, %1}"
9399 [(set_attr "type" "sselog1")
9400 (set_attr "prefix_data16" "1")
9401 (set_attr "prefix_extra" "1")
9402 (set_attr "prefix" "maybe_vex")
9403 (set_attr "mode" "TI")])
9405 (define_insn "abs<mode>2"
9406 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
9407 (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
9409 "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
9410 [(set_attr "type" "sselog1")
9411 (set_attr "prefix_rep" "0")
9412 (set_attr "prefix_extra" "1")
9413 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
9414 (set_attr "mode" "DI")])
9416 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9418 ;; AMD SSE4A instructions
9420 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9422 (define_insn "sse4a_movnt<mode>"
9423 [(set (match_operand:MODEF 0 "memory_operand" "=m")
9425 [(match_operand:MODEF 1 "register_operand" "x")]
9428 "movnts<ssemodefsuffix>\t{%1, %0|%0, %1}"
9429 [(set_attr "type" "ssemov")
9430 (set_attr "mode" "<MODE>")])
9432 (define_insn "sse4a_vmmovnt<mode>"
9433 [(set (match_operand:<ssescalarmode> 0 "memory_operand" "=m")
9434 (unspec:<ssescalarmode>
9435 [(vec_select:<ssescalarmode>
9436 (match_operand:SSEMODEF2P 1 "register_operand" "x")
9437 (parallel [(const_int 0)]))]
9440 "movnts<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
9441 [(set_attr "type" "ssemov")
9442 (set_attr "mode" "<ssescalarmode>")])
9444 (define_insn "sse4a_extrqi"
9445 [(set (match_operand:V2DI 0 "register_operand" "=x")
9446 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9447 (match_operand 2 "const_int_operand" "")
9448 (match_operand 3 "const_int_operand" "")]
9451 "extrq\t{%3, %2, %0|%0, %2, %3}"
9452 [(set_attr "type" "sse")
9453 (set_attr "prefix_data16" "1")
9454 (set_attr "length_immediate" "2")
9455 (set_attr "mode" "TI")])
9457 (define_insn "sse4a_extrq"
9458 [(set (match_operand:V2DI 0 "register_operand" "=x")
9459 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9460 (match_operand:V16QI 2 "register_operand" "x")]
9463 "extrq\t{%2, %0|%0, %2}"
9464 [(set_attr "type" "sse")
9465 (set_attr "prefix_data16" "1")
9466 (set_attr "mode" "TI")])
9468 (define_insn "sse4a_insertqi"
9469 [(set (match_operand:V2DI 0 "register_operand" "=x")
9470 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9471 (match_operand:V2DI 2 "register_operand" "x")
9472 (match_operand 3 "const_int_operand" "")
9473 (match_operand 4 "const_int_operand" "")]
9476 "insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
9477 [(set_attr "type" "sseins")
9478 (set_attr "prefix_data16" "0")
9479 (set_attr "prefix_rep" "1")
9480 (set_attr "length_immediate" "2")
9481 (set_attr "mode" "TI")])
9483 (define_insn "sse4a_insertq"
9484 [(set (match_operand:V2DI 0 "register_operand" "=x")
9485 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9486 (match_operand:V2DI 2 "register_operand" "x")]
9489 "insertq\t{%2, %0|%0, %2}"
9490 [(set_attr "type" "sseins")
9491 (set_attr "prefix_data16" "0")
9492 (set_attr "prefix_rep" "1")
9493 (set_attr "mode" "TI")])
9495 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9497 ;; Intel SSE4.1 instructions
9499 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9501 (define_insn "avx_blendp<avxmodesuffixf2c><avxmodesuffix>"
9502 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9503 (vec_merge:AVXMODEF2P
9504 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
9505 (match_operand:AVXMODEF2P 1 "register_operand" "x")
9506 (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
9508 "vblendp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9509 [(set_attr "type" "ssemov")
9510 (set_attr "prefix_extra" "1")
9511 (set_attr "length_immediate" "1")
9512 (set_attr "prefix" "vex")
9513 (set_attr "mode" "<avxvecmode>")])
9515 (define_insn "avx_blendvp<avxmodesuffixf2c><avxmodesuffix>"
9516 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9518 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
9519 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
9520 (match_operand:AVXMODEF2P 3 "register_operand" "x")]
9523 "vblendvp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9524 [(set_attr "type" "ssemov")
9525 (set_attr "prefix_extra" "1")
9526 (set_attr "length_immediate" "1")
9527 (set_attr "prefix" "vex")
9528 (set_attr "mode" "<avxvecmode>")])
9530 (define_insn "sse4_1_blendp<ssemodesuffixf2c>"
9531 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9532 (vec_merge:SSEMODEF2P
9533 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
9534 (match_operand:SSEMODEF2P 1 "register_operand" "0")
9535 (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
9537 "blendp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
9538 [(set_attr "type" "ssemov")
9539 (set_attr "prefix_data16" "1")
9540 (set_attr "prefix_extra" "1")
9541 (set_attr "length_immediate" "1")
9542 (set_attr "mode" "<MODE>")])
9544 (define_insn "sse4_1_blendvp<ssemodesuffixf2c>"
9545 [(set (match_operand:SSEMODEF2P 0 "reg_not_xmm0_operand" "=x")
9547 [(match_operand:SSEMODEF2P 1 "reg_not_xmm0_operand" "0")
9548 (match_operand:SSEMODEF2P 2 "nonimm_not_xmm0_operand" "xm")
9549 (match_operand:SSEMODEF2P 3 "register_operand" "Yz")]
9552 "blendvp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
9553 [(set_attr "type" "ssemov")
9554 (set_attr "prefix_data16" "1")
9555 (set_attr "prefix_extra" "1")
9556 (set_attr "mode" "<MODE>")])
9558 (define_insn "avx_dpp<avxmodesuffixf2c><avxmodesuffix>"
9559 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9561 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
9562 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
9563 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9566 "vdpp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9567 [(set_attr "type" "ssemul")
9568 (set_attr "prefix" "vex")
9569 (set_attr "prefix_extra" "1")
9570 (set_attr "length_immediate" "1")
9571 (set_attr "mode" "<avxvecmode>")])
9573 (define_insn "sse4_1_dpp<ssemodesuffixf2c>"
9574 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9576 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
9577 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
9578 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9581 "dpp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
9582 [(set_attr "type" "ssemul")
9583 (set_attr "prefix_data16" "1")
9584 (set_attr "prefix_extra" "1")
9585 (set_attr "length_immediate" "1")
9586 (set_attr "mode" "<MODE>")])
9588 (define_insn "sse4_1_movntdqa"
9589 [(set (match_operand:V2DI 0 "register_operand" "=x")
9590 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "m")]
9593 "%vmovntdqa\t{%1, %0|%0, %1}"
9594 [(set_attr "type" "ssemov")
9595 (set_attr "prefix_extra" "1")
9596 (set_attr "prefix" "maybe_vex")
9597 (set_attr "mode" "TI")])
9599 (define_insn "*avx_mpsadbw"
9600 [(set (match_operand:V16QI 0 "register_operand" "=x")
9601 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
9602 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9603 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9606 "vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9607 [(set_attr "type" "sselog1")
9608 (set_attr "prefix" "vex")
9609 (set_attr "prefix_extra" "1")
9610 (set_attr "length_immediate" "1")
9611 (set_attr "mode" "TI")])
9613 (define_insn "sse4_1_mpsadbw"
9614 [(set (match_operand:V16QI 0 "register_operand" "=x")
9615 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
9616 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9617 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9620 "mpsadbw\t{%3, %2, %0|%0, %2, %3}"
9621 [(set_attr "type" "sselog1")
9622 (set_attr "prefix_extra" "1")
9623 (set_attr "length_immediate" "1")
9624 (set_attr "mode" "TI")])
9626 (define_insn "*avx_packusdw"
9627 [(set (match_operand:V8HI 0 "register_operand" "=x")
9630 (match_operand:V4SI 1 "register_operand" "x"))
9632 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
9634 "vpackusdw\t{%2, %1, %0|%0, %1, %2}"
9635 [(set_attr "type" "sselog")
9636 (set_attr "prefix_extra" "1")
9637 (set_attr "prefix" "vex")
9638 (set_attr "mode" "TI")])
9640 (define_insn "sse4_1_packusdw"
9641 [(set (match_operand:V8HI 0 "register_operand" "=x")
9644 (match_operand:V4SI 1 "register_operand" "0"))
9646 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
9648 "packusdw\t{%2, %0|%0, %2}"
9649 [(set_attr "type" "sselog")
9650 (set_attr "prefix_extra" "1")
9651 (set_attr "mode" "TI")])
9653 (define_insn "*avx_pblendvb"
9654 [(set (match_operand:V16QI 0 "register_operand" "=x")
9655 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
9656 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9657 (match_operand:V16QI 3 "register_operand" "x")]
9660 "vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9661 [(set_attr "type" "ssemov")
9662 (set_attr "prefix_extra" "1")
9663 (set_attr "length_immediate" "1")
9664 (set_attr "prefix" "vex")
9665 (set_attr "mode" "TI")])
9667 (define_insn "sse4_1_pblendvb"
9668 [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x")
9669 (unspec:V16QI [(match_operand:V16QI 1 "reg_not_xmm0_operand" "0")
9670 (match_operand:V16QI 2 "nonimm_not_xmm0_operand" "xm")
9671 (match_operand:V16QI 3 "register_operand" "Yz")]
9674 "pblendvb\t{%3, %2, %0|%0, %2, %3}"
9675 [(set_attr "type" "ssemov")
9676 (set_attr "prefix_extra" "1")
9677 (set_attr "mode" "TI")])
9679 (define_insn "*avx_pblendw"
9680 [(set (match_operand:V8HI 0 "register_operand" "=x")
9682 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
9683 (match_operand:V8HI 1 "register_operand" "x")
9684 (match_operand:SI 3 "const_0_to_255_operand" "n")))]
9686 "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9687 [(set_attr "type" "ssemov")
9688 (set_attr "prefix" "vex")
9689 (set_attr "prefix_extra" "1")
9690 (set_attr "length_immediate" "1")
9691 (set_attr "mode" "TI")])
9693 (define_insn "sse4_1_pblendw"
9694 [(set (match_operand:V8HI 0 "register_operand" "=x")
9696 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
9697 (match_operand:V8HI 1 "register_operand" "0")
9698 (match_operand:SI 3 "const_0_to_255_operand" "n")))]
9700 "pblendw\t{%3, %2, %0|%0, %2, %3}"
9701 [(set_attr "type" "ssemov")
9702 (set_attr "prefix_extra" "1")
9703 (set_attr "length_immediate" "1")
9704 (set_attr "mode" "TI")])
9706 (define_insn "sse4_1_phminposuw"
9707 [(set (match_operand:V8HI 0 "register_operand" "=x")
9708 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")]
9709 UNSPEC_PHMINPOSUW))]
9711 "%vphminposuw\t{%1, %0|%0, %1}"
9712 [(set_attr "type" "sselog1")
9713 (set_attr "prefix_extra" "1")
9714 (set_attr "prefix" "maybe_vex")
9715 (set_attr "mode" "TI")])
9717 (define_insn "sse4_1_extendv8qiv8hi2"
9718 [(set (match_operand:V8HI 0 "register_operand" "=x")
9721 (match_operand:V16QI 1 "register_operand" "x")
9722 (parallel [(const_int 0)
9731 "%vpmovsxbw\t{%1, %0|%0, %1}"
9732 [(set_attr "type" "ssemov")
9733 (set_attr "prefix_extra" "1")
9734 (set_attr "prefix" "maybe_vex")
9735 (set_attr "mode" "TI")])
9737 (define_insn "*sse4_1_extendv8qiv8hi2"
9738 [(set (match_operand:V8HI 0 "register_operand" "=x")
9741 (vec_duplicate:V16QI
9742 (match_operand:V8QI 1 "nonimmediate_operand" "xm"))
9743 (parallel [(const_int 0)
9752 "%vpmovsxbw\t{%1, %0|%0, %1}"
9753 [(set_attr "type" "ssemov")
9754 (set_attr "prefix_extra" "1")
9755 (set_attr "prefix" "maybe_vex")
9756 (set_attr "mode" "TI")])
9758 (define_insn "sse4_1_extendv4qiv4si2"
9759 [(set (match_operand:V4SI 0 "register_operand" "=x")
9762 (match_operand:V16QI 1 "register_operand" "x")
9763 (parallel [(const_int 0)
9768 "%vpmovsxbd\t{%1, %0|%0, %1}"
9769 [(set_attr "type" "ssemov")
9770 (set_attr "prefix_extra" "1")
9771 (set_attr "prefix" "maybe_vex")
9772 (set_attr "mode" "TI")])
9774 (define_insn "*sse4_1_extendv4qiv4si2"
9775 [(set (match_operand:V4SI 0 "register_operand" "=x")
9778 (vec_duplicate:V16QI
9779 (match_operand:V4QI 1 "nonimmediate_operand" "xm"))
9780 (parallel [(const_int 0)
9785 "%vpmovsxbd\t{%1, %0|%0, %1}"
9786 [(set_attr "type" "ssemov")
9787 (set_attr "prefix_extra" "1")
9788 (set_attr "prefix" "maybe_vex")
9789 (set_attr "mode" "TI")])
9791 (define_insn "sse4_1_extendv2qiv2di2"
9792 [(set (match_operand:V2DI 0 "register_operand" "=x")
9795 (match_operand:V16QI 1 "register_operand" "x")
9796 (parallel [(const_int 0)
9799 "%vpmovsxbq\t{%1, %0|%0, %1}"
9800 [(set_attr "type" "ssemov")
9801 (set_attr "prefix_extra" "1")
9802 (set_attr "prefix" "maybe_vex")
9803 (set_attr "mode" "TI")])
9805 (define_insn "*sse4_1_extendv2qiv2di2"
9806 [(set (match_operand:V2DI 0 "register_operand" "=x")
9809 (vec_duplicate:V16QI
9810 (match_operand:V2QI 1 "nonimmediate_operand" "xm"))
9811 (parallel [(const_int 0)
9814 "%vpmovsxbq\t{%1, %0|%0, %1}"
9815 [(set_attr "type" "ssemov")
9816 (set_attr "prefix_extra" "1")
9817 (set_attr "prefix" "maybe_vex")
9818 (set_attr "mode" "TI")])
9820 (define_insn "sse4_1_extendv4hiv4si2"
9821 [(set (match_operand:V4SI 0 "register_operand" "=x")
9824 (match_operand:V8HI 1 "register_operand" "x")
9825 (parallel [(const_int 0)
9830 "%vpmovsxwd\t{%1, %0|%0, %1}"
9831 [(set_attr "type" "ssemov")
9832 (set_attr "prefix_extra" "1")
9833 (set_attr "prefix" "maybe_vex")
9834 (set_attr "mode" "TI")])
9836 (define_insn "*sse4_1_extendv4hiv4si2"
9837 [(set (match_operand:V4SI 0 "register_operand" "=x")
9841 (match_operand:V2HI 1 "nonimmediate_operand" "xm"))
9842 (parallel [(const_int 0)
9847 "%vpmovsxwd\t{%1, %0|%0, %1}"
9848 [(set_attr "type" "ssemov")
9849 (set_attr "prefix_extra" "1")
9850 (set_attr "prefix" "maybe_vex")
9851 (set_attr "mode" "TI")])
9853 (define_insn "sse4_1_extendv2hiv2di2"
9854 [(set (match_operand:V2DI 0 "register_operand" "=x")
9857 (match_operand:V8HI 1 "register_operand" "x")
9858 (parallel [(const_int 0)
9861 "%vpmovsxwq\t{%1, %0|%0, %1}"
9862 [(set_attr "type" "ssemov")
9863 (set_attr "prefix_extra" "1")
9864 (set_attr "prefix" "maybe_vex")
9865 (set_attr "mode" "TI")])
9867 (define_insn "*sse4_1_extendv2hiv2di2"
9868 [(set (match_operand:V2DI 0 "register_operand" "=x")
9872 (match_operand:V8HI 1 "nonimmediate_operand" "xm"))
9873 (parallel [(const_int 0)
9876 "%vpmovsxwq\t{%1, %0|%0, %1}"
9877 [(set_attr "type" "ssemov")
9878 (set_attr "prefix_extra" "1")
9879 (set_attr "prefix" "maybe_vex")
9880 (set_attr "mode" "TI")])
9882 (define_insn "sse4_1_extendv2siv2di2"
9883 [(set (match_operand:V2DI 0 "register_operand" "=x")
9886 (match_operand:V4SI 1 "register_operand" "x")
9887 (parallel [(const_int 0)
9890 "%vpmovsxdq\t{%1, %0|%0, %1}"
9891 [(set_attr "type" "ssemov")
9892 (set_attr "prefix_extra" "1")
9893 (set_attr "prefix" "maybe_vex")
9894 (set_attr "mode" "TI")])
9896 (define_insn "*sse4_1_extendv2siv2di2"
9897 [(set (match_operand:V2DI 0 "register_operand" "=x")
9901 (match_operand:V2SI 1 "nonimmediate_operand" "xm"))
9902 (parallel [(const_int 0)
9905 "%vpmovsxdq\t{%1, %0|%0, %1}"
9906 [(set_attr "type" "ssemov")
9907 (set_attr "prefix_extra" "1")
9908 (set_attr "prefix" "maybe_vex")
9909 (set_attr "mode" "TI")])
9911 (define_insn "sse4_1_zero_extendv8qiv8hi2"
9912 [(set (match_operand:V8HI 0 "register_operand" "=x")
9915 (match_operand:V16QI 1 "register_operand" "x")
9916 (parallel [(const_int 0)
9925 "%vpmovzxbw\t{%1, %0|%0, %1}"
9926 [(set_attr "type" "ssemov")
9927 (set_attr "prefix_extra" "1")
9928 (set_attr "prefix" "maybe_vex")
9929 (set_attr "mode" "TI")])
9931 (define_insn "*sse4_1_zero_extendv8qiv8hi2"
9932 [(set (match_operand:V8HI 0 "register_operand" "=x")
9935 (vec_duplicate:V16QI
9936 (match_operand:V8QI 1 "nonimmediate_operand" "xm"))
9937 (parallel [(const_int 0)
9946 "%vpmovzxbw\t{%1, %0|%0, %1}"
9947 [(set_attr "type" "ssemov")
9948 (set_attr "prefix_extra" "1")
9949 (set_attr "prefix" "maybe_vex")
9950 (set_attr "mode" "TI")])
9952 (define_insn "sse4_1_zero_extendv4qiv4si2"
9953 [(set (match_operand:V4SI 0 "register_operand" "=x")
9956 (match_operand:V16QI 1 "register_operand" "x")
9957 (parallel [(const_int 0)
9962 "%vpmovzxbd\t{%1, %0|%0, %1}"
9963 [(set_attr "type" "ssemov")
9964 (set_attr "prefix_extra" "1")
9965 (set_attr "prefix" "maybe_vex")
9966 (set_attr "mode" "TI")])
9968 (define_insn "*sse4_1_zero_extendv4qiv4si2"
9969 [(set (match_operand:V4SI 0 "register_operand" "=x")
9972 (vec_duplicate:V16QI
9973 (match_operand:V4QI 1 "nonimmediate_operand" "xm"))
9974 (parallel [(const_int 0)
9979 "%vpmovzxbd\t{%1, %0|%0, %1}"
9980 [(set_attr "type" "ssemov")
9981 (set_attr "prefix_extra" "1")
9982 (set_attr "prefix" "maybe_vex")
9983 (set_attr "mode" "TI")])
9985 (define_insn "sse4_1_zero_extendv2qiv2di2"
9986 [(set (match_operand:V2DI 0 "register_operand" "=x")
9989 (match_operand:V16QI 1 "register_operand" "x")
9990 (parallel [(const_int 0)
9993 "%vpmovzxbq\t{%1, %0|%0, %1}"
9994 [(set_attr "type" "ssemov")
9995 (set_attr "prefix_extra" "1")
9996 (set_attr "prefix" "maybe_vex")
9997 (set_attr "mode" "TI")])
9999 (define_insn "*sse4_1_zero_extendv2qiv2di2"
10000 [(set (match_operand:V2DI 0 "register_operand" "=x")
10003 (vec_duplicate:V16QI
10004 (match_operand:V2QI 1 "nonimmediate_operand" "xm"))
10005 (parallel [(const_int 0)
10006 (const_int 1)]))))]
10008 "%vpmovzxbq\t{%1, %0|%0, %1}"
10009 [(set_attr "type" "ssemov")
10010 (set_attr "prefix_extra" "1")
10011 (set_attr "prefix" "maybe_vex")
10012 (set_attr "mode" "TI")])
10014 (define_insn "sse4_1_zero_extendv4hiv4si2"
10015 [(set (match_operand:V4SI 0 "register_operand" "=x")
10018 (match_operand:V8HI 1 "register_operand" "x")
10019 (parallel [(const_int 0)
10022 (const_int 3)]))))]
10024 "%vpmovzxwd\t{%1, %0|%0, %1}"
10025 [(set_attr "type" "ssemov")
10026 (set_attr "prefix_extra" "1")
10027 (set_attr "prefix" "maybe_vex")
10028 (set_attr "mode" "TI")])
10030 (define_insn "*sse4_1_zero_extendv4hiv4si2"
10031 [(set (match_operand:V4SI 0 "register_operand" "=x")
10034 (vec_duplicate:V8HI
10035 (match_operand:V4HI 1 "nonimmediate_operand" "xm"))
10036 (parallel [(const_int 0)
10039 (const_int 3)]))))]
10041 "%vpmovzxwd\t{%1, %0|%0, %1}"
10042 [(set_attr "type" "ssemov")
10043 (set_attr "prefix_extra" "1")
10044 (set_attr "prefix" "maybe_vex")
10045 (set_attr "mode" "TI")])
10047 (define_insn "sse4_1_zero_extendv2hiv2di2"
10048 [(set (match_operand:V2DI 0 "register_operand" "=x")
10051 (match_operand:V8HI 1 "register_operand" "x")
10052 (parallel [(const_int 0)
10053 (const_int 1)]))))]
10055 "%vpmovzxwq\t{%1, %0|%0, %1}"
10056 [(set_attr "type" "ssemov")
10057 (set_attr "prefix_extra" "1")
10058 (set_attr "prefix" "maybe_vex")
10059 (set_attr "mode" "TI")])
10061 (define_insn "*sse4_1_zero_extendv2hiv2di2"
10062 [(set (match_operand:V2DI 0 "register_operand" "=x")
10065 (vec_duplicate:V8HI
10066 (match_operand:V2HI 1 "nonimmediate_operand" "xm"))
10067 (parallel [(const_int 0)
10068 (const_int 1)]))))]
10070 "%vpmovzxwq\t{%1, %0|%0, %1}"
10071 [(set_attr "type" "ssemov")
10072 (set_attr "prefix_extra" "1")
10073 (set_attr "prefix" "maybe_vex")
10074 (set_attr "mode" "TI")])
10076 (define_insn "sse4_1_zero_extendv2siv2di2"
10077 [(set (match_operand:V2DI 0 "register_operand" "=x")
10080 (match_operand:V4SI 1 "register_operand" "x")
10081 (parallel [(const_int 0)
10082 (const_int 1)]))))]
10084 "%vpmovzxdq\t{%1, %0|%0, %1}"
10085 [(set_attr "type" "ssemov")
10086 (set_attr "prefix_extra" "1")
10087 (set_attr "prefix" "maybe_vex")
10088 (set_attr "mode" "TI")])
10090 (define_insn "*sse4_1_zero_extendv2siv2di2"
10091 [(set (match_operand:V2DI 0 "register_operand" "=x")
10094 (vec_duplicate:V4SI
10095 (match_operand:V2SI 1 "nonimmediate_operand" "xm"))
10096 (parallel [(const_int 0)
10097 (const_int 1)]))))]
10099 "%vpmovzxdq\t{%1, %0|%0, %1}"
10100 [(set_attr "type" "ssemov")
10101 (set_attr "prefix_extra" "1")
10102 (set_attr "prefix" "maybe_vex")
10103 (set_attr "mode" "TI")])
10105 ;; ptestps/ptestpd are very similar to comiss and ucomiss when
10106 ;; setting FLAGS_REG. But it is not a really compare instruction.
10107 (define_insn "avx_vtestp<avxmodesuffixf2c><avxmodesuffix>"
10108 [(set (reg:CC FLAGS_REG)
10109 (unspec:CC [(match_operand:AVXMODEF2P 0 "register_operand" "x")
10110 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")]
10113 "vtestp<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
10114 [(set_attr "type" "ssecomi")
10115 (set_attr "prefix_extra" "1")
10116 (set_attr "prefix" "vex")
10117 (set_attr "mode" "<MODE>")])
10119 ;; ptest is very similar to comiss and ucomiss when setting FLAGS_REG.
10120 ;; But it is not a really compare instruction.
10121 (define_insn "avx_ptest256"
10122 [(set (reg:CC FLAGS_REG)
10123 (unspec:CC [(match_operand:V4DI 0 "register_operand" "x")
10124 (match_operand:V4DI 1 "nonimmediate_operand" "xm")]
10127 "vptest\t{%1, %0|%0, %1}"
10128 [(set_attr "type" "ssecomi")
10129 (set_attr "prefix_extra" "1")
10130 (set_attr "prefix" "vex")
10131 (set_attr "mode" "OI")])
10133 (define_insn "sse4_1_ptest"
10134 [(set (reg:CC FLAGS_REG)
10135 (unspec:CC [(match_operand:V2DI 0 "register_operand" "x")
10136 (match_operand:V2DI 1 "nonimmediate_operand" "xm")]
10139 "%vptest\t{%1, %0|%0, %1}"
10140 [(set_attr "type" "ssecomi")
10141 (set_attr "prefix_extra" "1")
10142 (set_attr "prefix" "maybe_vex")
10143 (set_attr "mode" "TI")])
10145 (define_insn "avx_roundp<avxmodesuffixf2c>256"
10146 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x")
10147 (unspec:AVX256MODEF2P
10148 [(match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "xm")
10149 (match_operand:SI 2 "const_0_to_15_operand" "n")]
10152 "vroundp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
10153 [(set_attr "type" "ssecvt")
10154 (set_attr "prefix_extra" "1")
10155 (set_attr "length_immediate" "1")
10156 (set_attr "prefix" "vex")
10157 (set_attr "mode" "<MODE>")])
10159 (define_insn "sse4_1_roundp<ssemodesuffixf2c>"
10160 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
10162 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")
10163 (match_operand:SI 2 "const_0_to_15_operand" "n")]
10166 "%vroundp<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
10167 [(set_attr "type" "ssecvt")
10168 (set_attr "prefix_data16" "1")
10169 (set_attr "prefix_extra" "1")
10170 (set_attr "length_immediate" "1")
10171 (set_attr "prefix" "maybe_vex")
10172 (set_attr "mode" "<MODE>")])
10174 (define_insn "*avx_rounds<ssemodesuffixf2c>"
10175 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
10176 (vec_merge:SSEMODEF2P
10178 [(match_operand:SSEMODEF2P 2 "register_operand" "x")
10179 (match_operand:SI 3 "const_0_to_15_operand" "n")]
10181 (match_operand:SSEMODEF2P 1 "register_operand" "x")
10184 "vrounds<ssemodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10185 [(set_attr "type" "ssecvt")
10186 (set_attr "prefix_extra" "1")
10187 (set_attr "length_immediate" "1")
10188 (set_attr "prefix" "vex")
10189 (set_attr "mode" "<MODE>")])
10191 (define_insn "sse4_1_rounds<ssemodesuffixf2c>"
10192 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
10193 (vec_merge:SSEMODEF2P
10195 [(match_operand:SSEMODEF2P 2 "register_operand" "x")
10196 (match_operand:SI 3 "const_0_to_15_operand" "n")]
10198 (match_operand:SSEMODEF2P 1 "register_operand" "0")
10201 "rounds<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
10202 [(set_attr "type" "ssecvt")
10203 (set_attr "prefix_data16" "1")
10204 (set_attr "prefix_extra" "1")
10205 (set_attr "length_immediate" "1")
10206 (set_attr "mode" "<MODE>")])
10208 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10210 ;; Intel SSE4.2 string/text processing instructions
10212 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10214 (define_insn_and_split "sse4_2_pcmpestr"
10215 [(set (match_operand:SI 0 "register_operand" "=c,c")
10217 [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
10218 (match_operand:SI 3 "register_operand" "a,a")
10219 (match_operand:V16QI 4 "nonimm_not_xmm0_operand" "x,m")
10220 (match_operand:SI 5 "register_operand" "d,d")
10221 (match_operand:SI 6 "const_0_to_255_operand" "n,n")]
10223 (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
10231 (set (reg:CC FLAGS_REG)
10240 && can_create_pseudo_p ()"
10245 int ecx = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0]));
10246 int xmm0 = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[1]));
10247 int flags = !find_regno_note (curr_insn, REG_UNUSED, FLAGS_REG);
10250 emit_insn (gen_sse4_2_pcmpestri (operands[0], operands[2],
10251 operands[3], operands[4],
10252 operands[5], operands[6]));
10254 emit_insn (gen_sse4_2_pcmpestrm (operands[1], operands[2],
10255 operands[3], operands[4],
10256 operands[5], operands[6]));
10257 if (flags && !(ecx || xmm0))
10258 emit_insn (gen_sse4_2_pcmpestr_cconly (NULL, NULL,
10259 operands[2], operands[3],
10260 operands[4], operands[5],
10264 [(set_attr "type" "sselog")
10265 (set_attr "prefix_data16" "1")
10266 (set_attr "prefix_extra" "1")
10267 (set_attr "length_immediate" "1")
10268 (set_attr "memory" "none,load")
10269 (set_attr "mode" "TI")])
10271 (define_insn "sse4_2_pcmpestri"
10272 [(set (match_operand:SI 0 "register_operand" "=c,c")
10274 [(match_operand:V16QI 1 "register_operand" "x,x")
10275 (match_operand:SI 2 "register_operand" "a,a")
10276 (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
10277 (match_operand:SI 4 "register_operand" "d,d")
10278 (match_operand:SI 5 "const_0_to_255_operand" "n,n")]
10280 (set (reg:CC FLAGS_REG)
10289 "%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
10290 [(set_attr "type" "sselog")
10291 (set_attr "prefix_data16" "1")
10292 (set_attr "prefix_extra" "1")
10293 (set_attr "prefix" "maybe_vex")
10294 (set_attr "length_immediate" "1")
10295 (set_attr "memory" "none,load")
10296 (set_attr "mode" "TI")])
10298 (define_insn "sse4_2_pcmpestrm"
10299 [(set (match_operand:V16QI 0 "register_operand" "=Yz,Yz")
10301 [(match_operand:V16QI 1 "register_operand" "x,x")
10302 (match_operand:SI 2 "register_operand" "a,a")
10303 (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
10304 (match_operand:SI 4 "register_operand" "d,d")
10305 (match_operand:SI 5 "const_0_to_255_operand" "n,n")]
10307 (set (reg:CC FLAGS_REG)
10316 "%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
10317 [(set_attr "type" "sselog")
10318 (set_attr "prefix_data16" "1")
10319 (set_attr "prefix_extra" "1")
10320 (set_attr "length_immediate" "1")
10321 (set_attr "prefix" "maybe_vex")
10322 (set_attr "memory" "none,load")
10323 (set_attr "mode" "TI")])
10325 (define_insn "sse4_2_pcmpestr_cconly"
10326 [(set (reg:CC FLAGS_REG)
10328 [(match_operand:V16QI 2 "register_operand" "x,x,x,x")
10329 (match_operand:SI 3 "register_operand" "a,a,a,a")
10330 (match_operand:V16QI 4 "nonimmediate_operand" "x,m,x,m")
10331 (match_operand:SI 5 "register_operand" "d,d,d,d")
10332 (match_operand:SI 6 "const_0_to_255_operand" "n,n,n,n")]
10334 (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X"))
10335 (clobber (match_scratch:SI 1 "= X, X,c,c"))]
10338 %vpcmpestrm\t{%6, %4, %2|%2, %4, %6}
10339 %vpcmpestrm\t{%6, %4, %2|%2, %4, %6}
10340 %vpcmpestri\t{%6, %4, %2|%2, %4, %6}
10341 %vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
10342 [(set_attr "type" "sselog")
10343 (set_attr "prefix_data16" "1")
10344 (set_attr "prefix_extra" "1")
10345 (set_attr "length_immediate" "1")
10346 (set_attr "memory" "none,load,none,load")
10347 (set_attr "prefix" "maybe_vex")
10348 (set_attr "mode" "TI")])
10350 (define_insn_and_split "sse4_2_pcmpistr"
10351 [(set (match_operand:SI 0 "register_operand" "=c,c")
10353 [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
10354 (match_operand:V16QI 3 "nonimm_not_xmm0_operand" "x,m")
10355 (match_operand:SI 4 "const_0_to_255_operand" "n,n")]
10357 (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
10363 (set (reg:CC FLAGS_REG)
10370 && can_create_pseudo_p ()"
10375 int ecx = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0]));
10376 int xmm0 = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[1]));
10377 int flags = !find_regno_note (curr_insn, REG_UNUSED, FLAGS_REG);
10380 emit_insn (gen_sse4_2_pcmpistri (operands[0], operands[2],
10381 operands[3], operands[4]));
10383 emit_insn (gen_sse4_2_pcmpistrm (operands[1], operands[2],
10384 operands[3], operands[4]));
10385 if (flags && !(ecx || xmm0))
10386 emit_insn (gen_sse4_2_pcmpistr_cconly (NULL, NULL,
10387 operands[2], operands[3],
10391 [(set_attr "type" "sselog")
10392 (set_attr "prefix_data16" "1")
10393 (set_attr "prefix_extra" "1")
10394 (set_attr "length_immediate" "1")
10395 (set_attr "memory" "none,load")
10396 (set_attr "mode" "TI")])
10398 (define_insn "sse4_2_pcmpistri"
10399 [(set (match_operand:SI 0 "register_operand" "=c,c")
10401 [(match_operand:V16QI 1 "register_operand" "x,x")
10402 (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
10403 (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
10405 (set (reg:CC FLAGS_REG)
10412 "%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
10413 [(set_attr "type" "sselog")
10414 (set_attr "prefix_data16" "1")
10415 (set_attr "prefix_extra" "1")
10416 (set_attr "length_immediate" "1")
10417 (set_attr "prefix" "maybe_vex")
10418 (set_attr "memory" "none,load")
10419 (set_attr "mode" "TI")])
10421 (define_insn "sse4_2_pcmpistrm"
10422 [(set (match_operand:V16QI 0 "register_operand" "=Yz,Yz")
10424 [(match_operand:V16QI 1 "register_operand" "x,x")
10425 (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
10426 (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
10428 (set (reg:CC FLAGS_REG)
10435 "%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
10436 [(set_attr "type" "sselog")
10437 (set_attr "prefix_data16" "1")
10438 (set_attr "prefix_extra" "1")
10439 (set_attr "length_immediate" "1")
10440 (set_attr "prefix" "maybe_vex")
10441 (set_attr "memory" "none,load")
10442 (set_attr "mode" "TI")])
10444 (define_insn "sse4_2_pcmpistr_cconly"
10445 [(set (reg:CC FLAGS_REG)
10447 [(match_operand:V16QI 2 "register_operand" "x,x,x,x")
10448 (match_operand:V16QI 3 "nonimmediate_operand" "x,m,x,m")
10449 (match_operand:SI 4 "const_0_to_255_operand" "n,n,n,n")]
10451 (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X"))
10452 (clobber (match_scratch:SI 1 "= X, X,c,c"))]
10455 %vpcmpistrm\t{%4, %3, %2|%2, %3, %4}
10456 %vpcmpistrm\t{%4, %3, %2|%2, %3, %4}
10457 %vpcmpistri\t{%4, %3, %2|%2, %3, %4}
10458 %vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
10459 [(set_attr "type" "sselog")
10460 (set_attr "prefix_data16" "1")
10461 (set_attr "prefix_extra" "1")
10462 (set_attr "length_immediate" "1")
10463 (set_attr "memory" "none,load,none,load")
10464 (set_attr "prefix" "maybe_vex")
10465 (set_attr "mode" "TI")])
10467 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10469 ;; XOP instructions
10471 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
10473 ;; XOP parallel integer multiply/add instructions.
10474 ;; Note the instruction does not allow the value being added to be a memory
10475 ;; operation. However by pretending via the nonimmediate_operand predicate
10476 ;; that it does and splitting it later allows the following to be recognized:
10477 ;; a[i] = b[i] * c[i] + d[i];
10478 (define_insn "xop_pmacsww"
10479 [(set (match_operand:V8HI 0 "register_operand" "=x,x")
10482 (match_operand:V8HI 1 "nonimmediate_operand" "%x,m")
10483 (match_operand:V8HI 2 "nonimmediate_operand" "xm,x"))
10484 (match_operand:V8HI 3 "register_operand" "x,x")))]
10485 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 2, true)"
10487 vpmacsww\t{%3, %2, %1, %0|%0, %1, %2, %3}
10488 vpmacsww\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10489 [(set_attr "type" "ssemuladd")
10490 (set_attr "mode" "TI")])
10492 ;; Split pmacsww with two memory operands into a load and the pmacsww.
10494 [(set (match_operand:V8HI 0 "register_operand" "")
10496 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
10497 (match_operand:V8HI 2 "nonimmediate_operand" ""))
10498 (match_operand:V8HI 3 "nonimmediate_operand" "")))]
10500 && !ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)
10501 && ix86_fma4_valid_op_p (operands, insn, 4, false, 2, true)
10502 && !reg_mentioned_p (operands[0], operands[1])
10503 && !reg_mentioned_p (operands[0], operands[2])
10504 && !reg_mentioned_p (operands[0], operands[3])"
10507 ix86_expand_fma4_multiple_memory (operands, 4, V8HImode);
10508 emit_insn (gen_xop_pmacsww (operands[0], operands[1], operands[2],
10513 (define_insn "xop_pmacssww"
10514 [(set (match_operand:V8HI 0 "register_operand" "=x,x")
10516 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x,m")
10517 (match_operand:V8HI 2 "nonimmediate_operand" "xm,x"))
10518 (match_operand:V8HI 3 "register_operand" "x,x")))]
10519 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10521 vpmacssww\t{%3, %2, %1, %0|%0, %1, %2, %3}
10522 vpmacssww\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10523 [(set_attr "type" "ssemuladd")
10524 (set_attr "mode" "TI")])
10526 ;; Note the instruction does not allow the value being added to be a memory
10527 ;; operation. However by pretending via the nonimmediate_operand predicate
10528 ;; that it does and splitting it later allows the following to be recognized:
10529 ;; a[i] = b[i] * c[i] + d[i];
10530 (define_insn "xop_pmacsdd"
10531 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
10534 (match_operand:V4SI 1 "nonimmediate_operand" "%x,m")
10535 (match_operand:V4SI 2 "nonimmediate_operand" "xm,x"))
10536 (match_operand:V4SI 3 "register_operand" "x,x")))]
10537 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 2, true)"
10539 vpmacsdd\t{%3, %2, %1, %0|%0, %1, %2, %3}
10540 vpmacsdd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10541 [(set_attr "type" "ssemuladd")
10542 (set_attr "mode" "TI")])
10544 ;; Split pmacsdd with two memory operands into a load and the pmacsdd.
10546 [(set (match_operand:V4SI 0 "register_operand" "")
10548 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "")
10549 (match_operand:V4SI 2 "nonimmediate_operand" ""))
10550 (match_operand:V4SI 3 "nonimmediate_operand" "")))]
10552 && !ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)
10553 && ix86_fma4_valid_op_p (operands, insn, 4, false, 2, true)
10554 && !reg_mentioned_p (operands[0], operands[1])
10555 && !reg_mentioned_p (operands[0], operands[2])
10556 && !reg_mentioned_p (operands[0], operands[3])"
10559 ix86_expand_fma4_multiple_memory (operands, 4, V4SImode);
10560 emit_insn (gen_xop_pmacsdd (operands[0], operands[1], operands[2],
10565 (define_insn "xop_pmacssdd"
10566 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
10568 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x,m")
10569 (match_operand:V4SI 2 "nonimmediate_operand" "xm,x"))
10570 (match_operand:V4SI 3 "register_operand" "x,x")))]
10571 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10573 vpmacssdd\t{%3, %2, %1, %0|%0, %1, %2, %3}
10574 vpmacssdd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10575 [(set_attr "type" "ssemuladd")
10576 (set_attr "mode" "TI")])
10578 (define_insn "xop_pmacssdql"
10579 [(set (match_operand:V2DI 0 "register_operand" "=x,x")
10584 (match_operand:V4SI 1 "nonimmediate_operand" "%x,m")
10585 (parallel [(const_int 1)
10588 (match_operand:V4SI 2 "nonimmediate_operand" "xm,x")
10589 (parallel [(const_int 1)
10591 (match_operand:V2DI 3 "register_operand" "x,x")))]
10592 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10594 vpmacssdql\t{%3, %2, %1, %0|%0, %1, %2, %3}
10595 vpmacssdql\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10596 [(set_attr "type" "ssemuladd")
10597 (set_attr "mode" "TI")])
10599 (define_insn "xop_pmacssdqh"
10600 [(set (match_operand:V2DI 0 "register_operand" "=x,x")
10605 (match_operand:V4SI 1 "nonimmediate_operand" "%x,m")
10606 (parallel [(const_int 0)
10610 (match_operand:V4SI 2 "nonimmediate_operand" "xm,x")
10611 (parallel [(const_int 0)
10613 (match_operand:V2DI 3 "register_operand" "x,x")))]
10614 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10616 vpmacssdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}
10617 vpmacssdqh\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10618 [(set_attr "type" "ssemuladd")
10619 (set_attr "mode" "TI")])
10621 (define_insn "xop_pmacsdql"
10622 [(set (match_operand:V2DI 0 "register_operand" "=x,x")
10627 (match_operand:V4SI 1 "nonimmediate_operand" "%x,m")
10628 (parallel [(const_int 1)
10632 (match_operand:V4SI 2 "nonimmediate_operand" "xm,x")
10633 (parallel [(const_int 1)
10635 (match_operand:V2DI 3 "register_operand" "x,x")))]
10636 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10638 vpmacsdql\t{%3, %2, %1, %0|%0, %1, %2, %3}
10639 vpmacsdql\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10640 [(set_attr "type" "ssemuladd")
10641 (set_attr "mode" "TI")])
10643 (define_insn_and_split "*xop_pmacsdql_mem"
10644 [(set (match_operand:V2DI 0 "register_operand" "=&x,&x")
10649 (match_operand:V4SI 1 "nonimmediate_operand" "%x,m")
10650 (parallel [(const_int 1)
10654 (match_operand:V4SI 2 "nonimmediate_operand" "xm,x")
10655 (parallel [(const_int 1)
10657 (match_operand:V2DI 3 "memory_operand" "m,m")))]
10658 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, -1, true)"
10660 "&& reload_completed"
10661 [(set (match_dup 0)
10669 (parallel [(const_int 1)
10674 (parallel [(const_int 1)
10678 ;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
10679 ;; fake it with a multiply/add. In general, we expect the define_split to
10680 ;; occur before register allocation, so we have to handle the corner case where
10681 ;; the target is the same as operands 1/2
10682 (define_insn_and_split "xop_mulv2div2di3_low"
10683 [(set (match_operand:V2DI 0 "register_operand" "=&x")
10687 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
10688 (parallel [(const_int 1)
10692 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
10693 (parallel [(const_int 1)
10694 (const_int 3)])))))]
10697 "&& reload_completed"
10698 [(set (match_dup 0)
10706 (parallel [(const_int 1)
10711 (parallel [(const_int 1)
10715 operands[3] = CONST0_RTX (V2DImode);
10717 [(set_attr "type" "ssemuladd")
10718 (set_attr "mode" "TI")])
10720 (define_insn "xop_pmacsdqh"
10721 [(set (match_operand:V2DI 0 "register_operand" "=x,x")
10726 (match_operand:V4SI 1 "nonimmediate_operand" "%x,m")
10727 (parallel [(const_int 0)
10731 (match_operand:V4SI 2 "nonimmediate_operand" "xm,x")
10732 (parallel [(const_int 0)
10734 (match_operand:V2DI 3 "register_operand" "x,x")))]
10735 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10737 vpmacsdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}
10738 vpmacsdqh\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10739 [(set_attr "type" "ssemuladd")
10740 (set_attr "mode" "TI")])
10742 (define_insn_and_split "*xop_pmacsdqh_mem"
10743 [(set (match_operand:V2DI 0 "register_operand" "=&x,&x")
10748 (match_operand:V4SI 1 "nonimmediate_operand" "%x,m")
10749 (parallel [(const_int 0)
10753 (match_operand:V4SI 2 "nonimmediate_operand" "xm,x")
10754 (parallel [(const_int 0)
10756 (match_operand:V2DI 3 "memory_operand" "m,m")))]
10757 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, -1, true)"
10759 "&& reload_completed"
10760 [(set (match_dup 0)
10768 (parallel [(const_int 0)
10773 (parallel [(const_int 0)
10777 ;; We don't have a straight 32-bit parallel multiply and extend on XOP, so
10778 ;; fake it with a multiply/add. In general, we expect the define_split to
10779 ;; occur before register allocation, so we have to handle the corner case where
10780 ;; the target is the same as either operands[1] or operands[2]
10781 (define_insn_and_split "xop_mulv2div2di3_high"
10782 [(set (match_operand:V2DI 0 "register_operand" "=&x")
10786 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
10787 (parallel [(const_int 0)
10791 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
10792 (parallel [(const_int 0)
10793 (const_int 2)])))))]
10796 "&& reload_completed"
10797 [(set (match_dup 0)
10805 (parallel [(const_int 0)
10810 (parallel [(const_int 0)
10814 operands[3] = CONST0_RTX (V2DImode);
10816 [(set_attr "type" "ssemuladd")
10817 (set_attr "mode" "TI")])
10819 ;; XOP parallel integer multiply/add instructions for the intrinisics
10820 (define_insn "xop_pmacsswd"
10821 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
10826 (match_operand:V8HI 1 "nonimmediate_operand" "%x,m")
10827 (parallel [(const_int 1)
10833 (match_operand:V8HI 2 "nonimmediate_operand" "xm,x")
10834 (parallel [(const_int 1)
10838 (match_operand:V4SI 3 "register_operand" "x,x")))]
10839 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10841 vpmacsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
10842 vpmacsswd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10843 [(set_attr "type" "ssemuladd")
10844 (set_attr "mode" "TI")])
10846 (define_insn "xop_pmacswd"
10847 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
10852 (match_operand:V8HI 1 "nonimmediate_operand" "%x,m")
10853 (parallel [(const_int 1)
10859 (match_operand:V8HI 2 "nonimmediate_operand" "xm,x")
10860 (parallel [(const_int 1)
10864 (match_operand:V4SI 3 "register_operand" "x,x")))]
10865 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10867 vpmacswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
10868 vpmacswd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10869 [(set_attr "type" "ssemuladd")
10870 (set_attr "mode" "TI")])
10872 (define_insn "xop_pmadcsswd"
10873 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
10879 (match_operand:V8HI 1 "nonimmediate_operand" "%x,m")
10880 (parallel [(const_int 0)
10886 (match_operand:V8HI 2 "nonimmediate_operand" "xm,x")
10887 (parallel [(const_int 0)
10895 (parallel [(const_int 1)
10902 (parallel [(const_int 1)
10905 (const_int 7)])))))
10906 (match_operand:V4SI 3 "register_operand" "x,x")))]
10907 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10909 vpmadcsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
10910 vpmadcsswd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10911 [(set_attr "type" "ssemuladd")
10912 (set_attr "mode" "TI")])
10914 (define_insn "xop_pmadcswd"
10915 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
10921 (match_operand:V8HI 1 "nonimmediate_operand" "%x,m")
10922 (parallel [(const_int 0)
10928 (match_operand:V8HI 2 "nonimmediate_operand" "xm,x")
10929 (parallel [(const_int 0)
10937 (parallel [(const_int 1)
10944 (parallel [(const_int 1)
10947 (const_int 7)])))))
10948 (match_operand:V4SI 3 "register_operand" "x,x")))]
10949 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, false, 1, true)"
10951 vpmadcswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
10952 vpmadcswd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
10953 [(set_attr "type" "ssemuladd")
10954 (set_attr "mode" "TI")])
10956 ;; XOP parallel XMM conditional moves
10957 (define_insn "xop_pcmov_<mode>"
10958 [(set (match_operand:SSEMODE 0 "register_operand" "=x,x,x")
10959 (if_then_else:SSEMODE
10960 (match_operand:SSEMODE 3 "nonimmediate_operand" "x,x,m")
10961 (match_operand:SSEMODE 1 "vector_move_operand" "x,m,x")
10962 (match_operand:SSEMODE 2 "vector_move_operand" "xm,x,x")))]
10963 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
10964 "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10965 [(set_attr "type" "sse4arg")])
10967 (define_insn "xop_pcmov_<mode>256"
10968 [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x,x")
10969 (if_then_else:AVX256MODE
10970 (match_operand:AVX256MODE 3 "nonimmediate_operand" "x,x,m")
10971 (match_operand:AVX256MODE 1 "vector_move_operand" "x,m,x")
10972 (match_operand:AVX256MODE 2 "vector_move_operand" "xm,x,x")))]
10973 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
10974 "vpcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
10975 [(set_attr "type" "sse4arg")])
10977 ;; XOP horizontal add/subtract instructions
10978 (define_insn "xop_phaddbw"
10979 [(set (match_operand:V8HI 0 "register_operand" "=x")
10983 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
10984 (parallel [(const_int 0)
10995 (parallel [(const_int 1)
11002 (const_int 15)])))))]
11004 "vphaddbw\t{%1, %0|%0, %1}"
11005 [(set_attr "type" "sseiadd1")])
11007 (define_insn "xop_phaddbd"
11008 [(set (match_operand:V4SI 0 "register_operand" "=x")
11013 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
11014 (parallel [(const_int 0)
11021 (parallel [(const_int 1)
11024 (const_int 13)]))))
11029 (parallel [(const_int 2)
11036 (parallel [(const_int 3)
11039 (const_int 15)]))))))]
11041 "vphaddbd\t{%1, %0|%0, %1}"
11042 [(set_attr "type" "sseiadd1")])
11044 (define_insn "xop_phaddbq"
11045 [(set (match_operand:V2DI 0 "register_operand" "=x")
11051 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
11052 (parallel [(const_int 0)
11057 (parallel [(const_int 1)
11063 (parallel [(const_int 2)
11068 (parallel [(const_int 3)
11069 (const_int 7)])))))
11075 (parallel [(const_int 8)
11080 (parallel [(const_int 9)
11081 (const_int 13)]))))
11086 (parallel [(const_int 10)
11091 (parallel [(const_int 11)
11092 (const_int 15)])))))))]
11094 "vphaddbq\t{%1, %0|%0, %1}"
11095 [(set_attr "type" "sseiadd1")])
11097 (define_insn "xop_phaddwd"
11098 [(set (match_operand:V4SI 0 "register_operand" "=x")
11102 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
11103 (parallel [(const_int 0)
11110 (parallel [(const_int 1)
11113 (const_int 7)])))))]
11115 "vphaddwd\t{%1, %0|%0, %1}"
11116 [(set_attr "type" "sseiadd1")])
11118 (define_insn "xop_phaddwq"
11119 [(set (match_operand:V2DI 0 "register_operand" "=x")
11124 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
11125 (parallel [(const_int 0)
11130 (parallel [(const_int 1)
11136 (parallel [(const_int 2)
11141 (parallel [(const_int 3)
11142 (const_int 7)]))))))]
11144 "vphaddwq\t{%1, %0|%0, %1}"
11145 [(set_attr "type" "sseiadd1")])
11147 (define_insn "xop_phadddq"
11148 [(set (match_operand:V2DI 0 "register_operand" "=x")
11152 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
11153 (parallel [(const_int 0)
11158 (parallel [(const_int 1)
11159 (const_int 3)])))))]
11161 "vphadddq\t{%1, %0|%0, %1}"
11162 [(set_attr "type" "sseiadd1")])
11164 (define_insn "xop_phaddubw"
11165 [(set (match_operand:V8HI 0 "register_operand" "=x")
11169 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
11170 (parallel [(const_int 0)
11181 (parallel [(const_int 1)
11188 (const_int 15)])))))]
11190 "vphaddubw\t{%1, %0|%0, %1}"
11191 [(set_attr "type" "sseiadd1")])
11193 (define_insn "xop_phaddubd"
11194 [(set (match_operand:V4SI 0 "register_operand" "=x")
11199 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
11200 (parallel [(const_int 0)
11207 (parallel [(const_int 1)
11210 (const_int 13)]))))
11215 (parallel [(const_int 2)
11222 (parallel [(const_int 3)
11225 (const_int 15)]))))))]
11227 "vphaddubd\t{%1, %0|%0, %1}"
11228 [(set_attr "type" "sseiadd1")])
11230 (define_insn "xop_phaddubq"
11231 [(set (match_operand:V2DI 0 "register_operand" "=x")
11237 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
11238 (parallel [(const_int 0)
11243 (parallel [(const_int 1)
11249 (parallel [(const_int 2)
11254 (parallel [(const_int 3)
11255 (const_int 7)])))))
11261 (parallel [(const_int 8)
11266 (parallel [(const_int 9)
11267 (const_int 13)]))))
11272 (parallel [(const_int 10)
11277 (parallel [(const_int 11)
11278 (const_int 15)])))))))]
11280 "vphaddubq\t{%1, %0|%0, %1}"
11281 [(set_attr "type" "sseiadd1")])
11283 (define_insn "xop_phadduwd"
11284 [(set (match_operand:V4SI 0 "register_operand" "=x")
11288 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
11289 (parallel [(const_int 0)
11296 (parallel [(const_int 1)
11299 (const_int 7)])))))]
11301 "vphadduwd\t{%1, %0|%0, %1}"
11302 [(set_attr "type" "sseiadd1")])
11304 (define_insn "xop_phadduwq"
11305 [(set (match_operand:V2DI 0 "register_operand" "=x")
11310 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
11311 (parallel [(const_int 0)
11316 (parallel [(const_int 1)
11322 (parallel [(const_int 2)
11327 (parallel [(const_int 3)
11328 (const_int 7)]))))))]
11330 "vphadduwq\t{%1, %0|%0, %1}"
11331 [(set_attr "type" "sseiadd1")])
11333 (define_insn "xop_phaddudq"
11334 [(set (match_operand:V2DI 0 "register_operand" "=x")
11338 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
11339 (parallel [(const_int 0)
11344 (parallel [(const_int 1)
11345 (const_int 3)])))))]
11347 "vphaddudq\t{%1, %0|%0, %1}"
11348 [(set_attr "type" "sseiadd1")])
11350 (define_insn "xop_phsubbw"
11351 [(set (match_operand:V8HI 0 "register_operand" "=x")
11355 (match_operand:V16QI 1 "nonimmediate_operand" "xm")
11356 (parallel [(const_int 0)
11367 (parallel [(const_int 1)
11374 (const_int 15)])))))]
11376 "vphsubbw\t{%1, %0|%0, %1}"
11377 [(set_attr "type" "sseiadd1")])
11379 (define_insn "xop_phsubwd"
11380 [(set (match_operand:V4SI 0 "register_operand" "=x")
11384 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
11385 (parallel [(const_int 0)
11392 (parallel [(const_int 1)
11395 (const_int 7)])))))]
11397 "vphsubwd\t{%1, %0|%0, %1}"
11398 [(set_attr "type" "sseiadd1")])
11400 (define_insn "xop_phsubdq"
11401 [(set (match_operand:V2DI 0 "register_operand" "=x")
11405 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
11406 (parallel [(const_int 0)
11411 (parallel [(const_int 1)
11412 (const_int 3)])))))]
11414 "vphsubdq\t{%1, %0|%0, %1}"
11415 [(set_attr "type" "sseiadd1")])
11417 ;; XOP permute instructions
11418 (define_insn "xop_pperm"
11419 [(set (match_operand:V16QI 0 "register_operand" "=x,x,x")
11421 [(match_operand:V16QI 1 "nonimmediate_operand" "x,x,m")
11422 (match_operand:V16QI 2 "nonimmediate_operand" "x,m,x")
11423 (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,x")]
11424 UNSPEC_XOP_PERMUTE))]
11425 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
11426 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
11427 [(set_attr "type" "sse4arg")
11428 (set_attr "mode" "TI")])
11430 ;; XOP pack instructions that combine two vectors into a smaller vector
11431 (define_insn "xop_pperm_pack_v2di_v4si"
11432 [(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
11435 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,m"))
11437 (match_operand:V2DI 2 "nonimmediate_operand" "x,m,x"))))
11438 (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,x"))]
11439 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
11440 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
11441 [(set_attr "type" "sse4arg")
11442 (set_attr "mode" "TI")])
11444 (define_insn "xop_pperm_pack_v4si_v8hi"
11445 [(set (match_operand:V8HI 0 "register_operand" "=x,x,x")
11448 (match_operand:V4SI 1 "nonimmediate_operand" "x,x,m"))
11450 (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x"))))
11451 (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,x"))]
11452 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
11453 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
11454 [(set_attr "type" "sse4arg")
11455 (set_attr "mode" "TI")])
11457 (define_insn "xop_pperm_pack_v8hi_v16qi"
11458 [(set (match_operand:V16QI 0 "register_operand" "=x,x,x")
11461 (match_operand:V8HI 1 "nonimmediate_operand" "x,x,m"))
11463 (match_operand:V8HI 2 "nonimmediate_operand" "x,m,x"))))
11464 (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,x"))]
11465 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 4, true, 1, false)"
11466 "vpperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
11467 [(set_attr "type" "sse4arg")
11468 (set_attr "mode" "TI")])
11470 ;; XOP packed rotate instructions
11471 (define_expand "rotl<mode>3"
11472 [(set (match_operand:SSEMODE1248 0 "register_operand" "")
11473 (rotate:SSEMODE1248
11474 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
11475 (match_operand:SI 2 "general_operand")))]
11478 /* If we were given a scalar, convert it to parallel */
11479 if (! const_0_to_<sserotatemax>_operand (operands[2], SImode))
11481 rtvec vs = rtvec_alloc (<ssescalarnum>);
11482 rtx par = gen_rtx_PARALLEL (<MODE>mode, vs);
11483 rtx reg = gen_reg_rtx (<MODE>mode);
11484 rtx op2 = operands[2];
11487 if (GET_MODE (op2) != <ssescalarmode>mode)
11489 op2 = gen_reg_rtx (<ssescalarmode>mode);
11490 convert_move (op2, operands[2], false);
11493 for (i = 0; i < <ssescalarnum>; i++)
11494 RTVEC_ELT (vs, i) = op2;
11496 emit_insn (gen_vec_init<mode> (reg, par));
11497 emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], reg));
11502 (define_expand "rotr<mode>3"
11503 [(set (match_operand:SSEMODE1248 0 "register_operand" "")
11504 (rotatert:SSEMODE1248
11505 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
11506 (match_operand:SI 2 "general_operand")))]
11509 /* If we were given a scalar, convert it to parallel */
11510 if (! const_0_to_<sserotatemax>_operand (operands[2], SImode))
11512 rtvec vs = rtvec_alloc (<ssescalarnum>);
11513 rtx par = gen_rtx_PARALLEL (<MODE>mode, vs);
11514 rtx neg = gen_reg_rtx (<MODE>mode);
11515 rtx reg = gen_reg_rtx (<MODE>mode);
11516 rtx op2 = operands[2];
11519 if (GET_MODE (op2) != <ssescalarmode>mode)
11521 op2 = gen_reg_rtx (<ssescalarmode>mode);
11522 convert_move (op2, operands[2], false);
11525 for (i = 0; i < <ssescalarnum>; i++)
11526 RTVEC_ELT (vs, i) = op2;
11528 emit_insn (gen_vec_init<mode> (reg, par));
11529 emit_insn (gen_neg<mode>2 (neg, reg));
11530 emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], neg));
11535 (define_insn "xop_rotl<mode>3"
11536 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
11537 (rotate:SSEMODE1248
11538 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
11539 (match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
11541 "vprot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
11542 [(set_attr "type" "sseishft")
11543 (set_attr "length_immediate" "1")
11544 (set_attr "mode" "TI")])
11546 (define_insn "xop_rotr<mode>3"
11547 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
11548 (rotatert:SSEMODE1248
11549 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
11550 (match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
11553 operands[3] = GEN_INT ((<ssescalarnum> * 8) - INTVAL (operands[2]));
11554 return \"vprot<ssevecsize>\t{%3, %1, %0|%0, %1, %3}\";
11556 [(set_attr "type" "sseishft")
11557 (set_attr "length_immediate" "1")
11558 (set_attr "mode" "TI")])
11560 (define_expand "vrotr<mode>3"
11561 [(match_operand:SSEMODE1248 0 "register_operand" "")
11562 (match_operand:SSEMODE1248 1 "register_operand" "")
11563 (match_operand:SSEMODE1248 2 "register_operand" "")]
11566 rtx reg = gen_reg_rtx (<MODE>mode);
11567 emit_insn (gen_neg<mode>2 (reg, operands[2]));
11568 emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], reg));
11572 (define_expand "vrotl<mode>3"
11573 [(match_operand:SSEMODE1248 0 "register_operand" "")
11574 (match_operand:SSEMODE1248 1 "register_operand" "")
11575 (match_operand:SSEMODE1248 2 "register_operand" "")]
11578 emit_insn (gen_xop_vrotl<mode>3 (operands[0], operands[1], operands[2]));
11582 (define_insn "xop_vrotl<mode>3"
11583 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
11584 (if_then_else:SSEMODE1248
11586 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
11588 (rotate:SSEMODE1248
11589 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
11591 (rotatert:SSEMODE1248
11593 (neg:SSEMODE1248 (match_dup 2)))))]
11594 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 3, true, 1, false)"
11595 "vprot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
11596 [(set_attr "type" "sseishft")
11597 (set_attr "prefix_data16" "0")
11598 (set_attr "prefix_extra" "2")
11599 (set_attr "mode" "TI")])
11601 ;; XOP packed shift instructions.
11602 ;; FIXME: add V2DI back in
11603 (define_expand "vlshr<mode>3"
11604 [(match_operand:SSEMODE124 0 "register_operand" "")
11605 (match_operand:SSEMODE124 1 "register_operand" "")
11606 (match_operand:SSEMODE124 2 "register_operand" "")]
11609 rtx neg = gen_reg_rtx (<MODE>mode);
11610 emit_insn (gen_neg<mode>2 (neg, operands[2]));
11611 emit_insn (gen_xop_lshl<mode>3 (operands[0], operands[1], neg));
11615 (define_expand "vashr<mode>3"
11616 [(match_operand:SSEMODE124 0 "register_operand" "")
11617 (match_operand:SSEMODE124 1 "register_operand" "")
11618 (match_operand:SSEMODE124 2 "register_operand" "")]
11621 rtx neg = gen_reg_rtx (<MODE>mode);
11622 emit_insn (gen_neg<mode>2 (neg, operands[2]));
11623 emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], neg));
11627 (define_expand "vashl<mode>3"
11628 [(match_operand:SSEMODE124 0 "register_operand" "")
11629 (match_operand:SSEMODE124 1 "register_operand" "")
11630 (match_operand:SSEMODE124 2 "register_operand" "")]
11633 emit_insn (gen_xop_ashl<mode>3 (operands[0], operands[1], operands[2]));
11637 (define_insn "xop_ashl<mode>3"
11638 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
11639 (if_then_else:SSEMODE1248
11641 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
11643 (ashift:SSEMODE1248
11644 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
11646 (ashiftrt:SSEMODE1248
11648 (neg:SSEMODE1248 (match_dup 2)))))]
11649 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 3, true, 1, false)"
11650 "vpsha<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
11651 [(set_attr "type" "sseishft")
11652 (set_attr "prefix_data16" "0")
11653 (set_attr "prefix_extra" "2")
11654 (set_attr "mode" "TI")])
11656 (define_insn "xop_lshl<mode>3"
11657 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
11658 (if_then_else:SSEMODE1248
11660 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "x,m")
11662 (ashift:SSEMODE1248
11663 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm,x")
11665 (lshiftrt:SSEMODE1248
11667 (neg:SSEMODE1248 (match_dup 2)))))]
11668 "TARGET_XOP && ix86_fma4_valid_op_p (operands, insn, 3, true, 1, false)"
11669 "vpshl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
11670 [(set_attr "type" "sseishft")
11671 (set_attr "prefix_data16" "0")
11672 (set_attr "prefix_extra" "2")
11673 (set_attr "mode" "TI")])
11675 ;; SSE2 doesn't have some shift varients, so define versions for XOP
11676 (define_expand "ashlv16qi3"
11677 [(match_operand:V16QI 0 "register_operand" "")
11678 (match_operand:V16QI 1 "register_operand" "")
11679 (match_operand:SI 2 "nonmemory_operand" "")]
11682 rtvec vs = rtvec_alloc (16);
11683 rtx par = gen_rtx_PARALLEL (V16QImode, vs);
11684 rtx reg = gen_reg_rtx (V16QImode);
11686 for (i = 0; i < 16; i++)
11687 RTVEC_ELT (vs, i) = operands[2];
11689 emit_insn (gen_vec_initv16qi (reg, par));
11690 emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg));
11694 (define_expand "lshlv16qi3"
11695 [(match_operand:V16QI 0 "register_operand" "")
11696 (match_operand:V16QI 1 "register_operand" "")
11697 (match_operand:SI 2 "nonmemory_operand" "")]
11700 rtvec vs = rtvec_alloc (16);
11701 rtx par = gen_rtx_PARALLEL (V16QImode, vs);
11702 rtx reg = gen_reg_rtx (V16QImode);
11704 for (i = 0; i < 16; i++)
11705 RTVEC_ELT (vs, i) = operands[2];
11707 emit_insn (gen_vec_initv16qi (reg, par));
11708 emit_insn (gen_xop_lshlv16qi3 (operands[0], operands[1], reg));
11712 (define_expand "ashrv16qi3"
11713 [(match_operand:V16QI 0 "register_operand" "")
11714 (match_operand:V16QI 1 "register_operand" "")
11715 (match_operand:SI 2 "nonmemory_operand" "")]
11718 rtvec vs = rtvec_alloc (16);
11719 rtx par = gen_rtx_PARALLEL (V16QImode, vs);
11720 rtx reg = gen_reg_rtx (V16QImode);
11722 rtx ele = ((CONST_INT_P (operands[2]))
11723 ? GEN_INT (- INTVAL (operands[2]))
11726 for (i = 0; i < 16; i++)
11727 RTVEC_ELT (vs, i) = ele;
11729 emit_insn (gen_vec_initv16qi (reg, par));
11731 if (!CONST_INT_P (operands[2]))
11733 rtx neg = gen_reg_rtx (V16QImode);
11734 emit_insn (gen_negv16qi2 (neg, reg));
11735 emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], neg));
11738 emit_insn (gen_xop_ashlv16qi3 (operands[0], operands[1], reg));
11743 (define_expand "ashrv2di3"
11744 [(match_operand:V2DI 0 "register_operand" "")
11745 (match_operand:V2DI 1 "register_operand" "")
11746 (match_operand:DI 2 "nonmemory_operand" "")]
11749 rtvec vs = rtvec_alloc (2);
11750 rtx par = gen_rtx_PARALLEL (V2DImode, vs);
11751 rtx reg = gen_reg_rtx (V2DImode);
11754 if (CONST_INT_P (operands[2]))
11755 ele = GEN_INT (- INTVAL (operands[2]));
11756 else if (GET_MODE (operands[2]) != DImode)
11758 rtx move = gen_reg_rtx (DImode);
11759 ele = gen_reg_rtx (DImode);
11760 convert_move (move, operands[2], false);
11761 emit_insn (gen_negdi2 (ele, move));
11765 ele = gen_reg_rtx (DImode);
11766 emit_insn (gen_negdi2 (ele, operands[2]));
11769 RTVEC_ELT (vs, 0) = ele;
11770 RTVEC_ELT (vs, 1) = ele;
11771 emit_insn (gen_vec_initv2di (reg, par));
11772 emit_insn (gen_xop_ashlv2di3 (operands[0], operands[1], reg));
11776 ;; XOP FRCZ support
11778 (define_insn "xop_frcz<mode>2"
11779 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
11781 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")]
11784 "vfrcz<ssemodesuffixf4>\t{%1, %0|%0, %1}"
11785 [(set_attr "type" "ssecvt1")
11786 (set_attr "mode" "<MODE>")])
11789 (define_insn "xop_vmfrcz<mode>2"
11790 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
11791 (vec_merge:SSEMODEF2P
11793 [(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]
11795 (match_operand:SSEMODEF2P 1 "register_operand" "0")
11798 "vfrcz<ssemodesuffixf2s>\t{%2, %0|%0, %2}"
11799 [(set_attr "type" "ssecvt1")
11800 (set_attr "mode" "<MODE>")])
11802 (define_insn "xop_frcz<mode>2256"
11803 [(set (match_operand:FMA4MODEF4 0 "register_operand" "=x")
11805 [(match_operand:FMA4MODEF4 1 "nonimmediate_operand" "xm")]
11808 "vfrcz<fma4modesuffixf4>\t{%1, %0|%0, %1}"
11809 [(set_attr "type" "ssecvt1")
11810 (set_attr "mode" "<MODE>")])
11812 (define_insn "xop_maskcmp<mode>3"
11813 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
11814 (match_operator:SSEMODE1248 1 "ix86_comparison_int_operator"
11815 [(match_operand:SSEMODE1248 2 "register_operand" "x")
11816 (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
11818 "vpcom%Y1<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
11819 [(set_attr "type" "sse4arg")
11820 (set_attr "prefix_data16" "0")
11821 (set_attr "prefix_rep" "0")
11822 (set_attr "prefix_extra" "2")
11823 (set_attr "length_immediate" "1")
11824 (set_attr "mode" "TI")])
11826 (define_insn "xop_maskcmp_uns<mode>3"
11827 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
11828 (match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
11829 [(match_operand:SSEMODE1248 2 "register_operand" "x")
11830 (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
11832 "vpcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
11833 [(set_attr "type" "ssecmp")
11834 (set_attr "prefix_data16" "0")
11835 (set_attr "prefix_rep" "0")
11836 (set_attr "prefix_extra" "2")
11837 (set_attr "length_immediate" "1")
11838 (set_attr "mode" "TI")])
11840 ;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
11841 ;; and pcomneu* not to be converted to the signed ones in case somebody needs
11842 ;; the exact instruction generated for the intrinsic.
11843 (define_insn "xop_maskcmp_uns2<mode>3"
11844 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
11845 (unspec:SSEMODE1248
11846 [(match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
11847 [(match_operand:SSEMODE1248 2 "register_operand" "x")
11848 (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")])]
11849 UNSPEC_XOP_UNSIGNED_CMP))]
11851 "vpcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
11852 [(set_attr "type" "ssecmp")
11853 (set_attr "prefix_data16" "0")
11854 (set_attr "prefix_extra" "2")
11855 (set_attr "length_immediate" "1")
11856 (set_attr "mode" "TI")])
11858 ;; Pcomtrue and pcomfalse support. These are useless instructions, but are
11859 ;; being added here to be complete.
11860 (define_insn "xop_pcom_tf<mode>3"
11861 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
11862 (unspec:SSEMODE1248
11863 [(match_operand:SSEMODE1248 1 "register_operand" "x")
11864 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")
11865 (match_operand:SI 3 "const_int_operand" "n")]
11866 UNSPEC_XOP_TRUEFALSE))]
11869 return ((INTVAL (operands[3]) != 0)
11870 ? "vpcomtrue<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
11871 : "vpcomfalse<ssevecsize>\t{%2, %1, %0|%0, %1, %2}");
11873 [(set_attr "type" "ssecmp")
11874 (set_attr "prefix_data16" "0")
11875 (set_attr "prefix_extra" "2")
11876 (set_attr "length_immediate" "1")
11877 (set_attr "mode" "TI")])
11879 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
11880 (define_insn "*avx_aesenc"
11881 [(set (match_operand:V2DI 0 "register_operand" "=x")
11882 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11883 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11885 "TARGET_AES && TARGET_AVX"
11886 "vaesenc\t{%2, %1, %0|%0, %1, %2}"
11887 [(set_attr "type" "sselog1")
11888 (set_attr "prefix_extra" "1")
11889 (set_attr "prefix" "vex")
11890 (set_attr "mode" "TI")])
11892 (define_insn "aesenc"
11893 [(set (match_operand:V2DI 0 "register_operand" "=x")
11894 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11895 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11898 "aesenc\t{%2, %0|%0, %2}"
11899 [(set_attr "type" "sselog1")
11900 (set_attr "prefix_extra" "1")
11901 (set_attr "mode" "TI")])
11903 (define_insn "*avx_aesenclast"
11904 [(set (match_operand:V2DI 0 "register_operand" "=x")
11905 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11906 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11907 UNSPEC_AESENCLAST))]
11908 "TARGET_AES && TARGET_AVX"
11909 "vaesenclast\t{%2, %1, %0|%0, %1, %2}"
11910 [(set_attr "type" "sselog1")
11911 (set_attr "prefix_extra" "1")
11912 (set_attr "prefix" "vex")
11913 (set_attr "mode" "TI")])
11915 (define_insn "aesenclast"
11916 [(set (match_operand:V2DI 0 "register_operand" "=x")
11917 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11918 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11919 UNSPEC_AESENCLAST))]
11921 "aesenclast\t{%2, %0|%0, %2}"
11922 [(set_attr "type" "sselog1")
11923 (set_attr "prefix_extra" "1")
11924 (set_attr "mode" "TI")])
11926 (define_insn "*avx_aesdec"
11927 [(set (match_operand:V2DI 0 "register_operand" "=x")
11928 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11929 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11931 "TARGET_AES && TARGET_AVX"
11932 "vaesdec\t{%2, %1, %0|%0, %1, %2}"
11933 [(set_attr "type" "sselog1")
11934 (set_attr "prefix_extra" "1")
11935 (set_attr "prefix" "vex")
11936 (set_attr "mode" "TI")])
11938 (define_insn "aesdec"
11939 [(set (match_operand:V2DI 0 "register_operand" "=x")
11940 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11941 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11944 "aesdec\t{%2, %0|%0, %2}"
11945 [(set_attr "type" "sselog1")
11946 (set_attr "prefix_extra" "1")
11947 (set_attr "mode" "TI")])
11949 (define_insn "*avx_aesdeclast"
11950 [(set (match_operand:V2DI 0 "register_operand" "=x")
11951 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11952 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11953 UNSPEC_AESDECLAST))]
11954 "TARGET_AES && TARGET_AVX"
11955 "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
11956 [(set_attr "type" "sselog1")
11957 (set_attr "prefix_extra" "1")
11958 (set_attr "prefix" "vex")
11959 (set_attr "mode" "TI")])
11961 (define_insn "aesdeclast"
11962 [(set (match_operand:V2DI 0 "register_operand" "=x")
11963 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
11964 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
11965 UNSPEC_AESDECLAST))]
11967 "aesdeclast\t{%2, %0|%0, %2}"
11968 [(set_attr "type" "sselog1")
11969 (set_attr "prefix_extra" "1")
11970 (set_attr "mode" "TI")])
11972 (define_insn "aesimc"
11973 [(set (match_operand:V2DI 0 "register_operand" "=x")
11974 (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm")]
11977 "%vaesimc\t{%1, %0|%0, %1}"
11978 [(set_attr "type" "sselog1")
11979 (set_attr "prefix_extra" "1")
11980 (set_attr "prefix" "maybe_vex")
11981 (set_attr "mode" "TI")])
11983 (define_insn "aeskeygenassist"
11984 [(set (match_operand:V2DI 0 "register_operand" "=x")
11985 (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm")
11986 (match_operand:SI 2 "const_0_to_255_operand" "n")]
11987 UNSPEC_AESKEYGENASSIST))]
11989 "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
11990 [(set_attr "type" "sselog1")
11991 (set_attr "prefix_extra" "1")
11992 (set_attr "length_immediate" "1")
11993 (set_attr "prefix" "maybe_vex")
11994 (set_attr "mode" "TI")])
11996 (define_insn "*vpclmulqdq"
11997 [(set (match_operand:V2DI 0 "register_operand" "=x")
11998 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
11999 (match_operand:V2DI 2 "nonimmediate_operand" "xm")
12000 (match_operand:SI 3 "const_0_to_255_operand" "n")]
12002 "TARGET_PCLMUL && TARGET_AVX"
12003 "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
12004 [(set_attr "type" "sselog1")
12005 (set_attr "prefix_extra" "1")
12006 (set_attr "length_immediate" "1")
12007 (set_attr "prefix" "vex")
12008 (set_attr "mode" "TI")])
12010 (define_insn "pclmulqdq"
12011 [(set (match_operand:V2DI 0 "register_operand" "=x")
12012 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
12013 (match_operand:V2DI 2 "nonimmediate_operand" "xm")
12014 (match_operand:SI 3 "const_0_to_255_operand" "n")]
12017 "pclmulqdq\t{%3, %2, %0|%0, %2, %3}"
12018 [(set_attr "type" "sselog1")
12019 (set_attr "prefix_extra" "1")
12020 (set_attr "length_immediate" "1")
12021 (set_attr "mode" "TI")])
12023 (define_expand "avx_vzeroall"
12024 [(match_par_dup 0 [(const_int 0)])]
12027 int nregs = TARGET_64BIT ? 16 : 8;
12030 operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs + 1));
12032 XVECEXP (operands[0], 0, 0)
12033 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
12036 for (regno = 0; regno < nregs; regno++)
12037 XVECEXP (operands[0], 0, regno + 1)
12038 = gen_rtx_SET (VOIDmode,
12039 gen_rtx_REG (V8SImode, SSE_REGNO (regno)),
12040 CONST0_RTX (V8SImode));
12043 (define_insn "*avx_vzeroall"
12044 [(match_parallel 0 "vzeroall_operation"
12045 [(unspec_volatile [(const_int 0)] UNSPECV_VZEROALL)])]
12048 [(set_attr "type" "sse")
12049 (set_attr "modrm" "0")
12050 (set_attr "memory" "none")
12051 (set_attr "prefix" "vex")
12052 (set_attr "mode" "OI")])
12054 ;; vzeroupper clobbers the upper 128bits of AVX registers.
12055 (define_expand "avx_vzeroupper"
12056 [(match_par_dup 0 [(const_int 0)])]
12059 int nregs = TARGET_64BIT ? 16 : 8;
12062 operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs + 1));
12064 XVECEXP (operands[0], 0, 0)
12065 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
12066 UNSPECV_VZEROUPPER);
12068 for (regno = 0; regno < nregs; regno++)
12069 XVECEXP (operands[0], 0, regno + 1)
12070 = gen_rtx_CLOBBER (VOIDmode,
12071 gen_rtx_REG (V8SImode, SSE_REGNO (regno)));
12074 (define_insn "*avx_vzeroupper"
12075 [(match_parallel 0 "vzeroupper_operation"
12076 [(unspec_volatile [(const_int 0)] UNSPECV_VZEROUPPER)])]
12079 [(set_attr "type" "sse")
12080 (set_attr "modrm" "0")
12081 (set_attr "memory" "none")
12082 (set_attr "prefix" "vex")
12083 (set_attr "mode" "OI")])
12085 (define_expand "avx_vpermil<mode>"
12086 [(set (match_operand:AVXMODEFDP 0 "register_operand" "")
12087 (vec_select:AVXMODEFDP
12088 (match_operand:AVXMODEFDP 1 "nonimmediate_operand" "")
12089 (match_operand:SI 2 "const_0_to_255_operand" "")))]
12092 int mask = INTVAL (operands[2]);
12093 rtx perm[<ssescalarnum>];
12095 perm[0] = GEN_INT (mask & 1);
12096 perm[1] = GEN_INT ((mask >> 1) & 1);
12097 if (<MODE>mode == V4DFmode)
12099 perm[2] = GEN_INT (((mask >> 2) & 1) + 2);
12100 perm[3] = GEN_INT (((mask >> 3) & 1) + 2);
12104 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (<ssescalarnum>, perm));
12107 (define_expand "avx_vpermil<mode>"
12108 [(set (match_operand:AVXMODEFSP 0 "register_operand" "")
12109 (vec_select:AVXMODEFSP
12110 (match_operand:AVXMODEFSP 1 "nonimmediate_operand" "")
12111 (match_operand:SI 2 "const_0_to_255_operand" "")))]
12114 int mask = INTVAL (operands[2]);
12115 rtx perm[<ssescalarnum>];
12117 perm[0] = GEN_INT (mask & 3);
12118 perm[1] = GEN_INT ((mask >> 2) & 3);
12119 perm[2] = GEN_INT ((mask >> 4) & 3);
12120 perm[3] = GEN_INT ((mask >> 6) & 3);
12121 if (<MODE>mode == V8SFmode)
12123 perm[4] = GEN_INT ((mask & 3) + 4);
12124 perm[5] = GEN_INT (((mask >> 2) & 3) + 4);
12125 perm[6] = GEN_INT (((mask >> 4) & 3) + 4);
12126 perm[7] = GEN_INT (((mask >> 6) & 3) + 4);
12130 = gen_rtx_PARALLEL (VOIDmode, gen_rtvec_v (<ssescalarnum>, perm));
12133 (define_insn "*avx_vpermilp<mode>"
12134 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
12135 (vec_select:AVXMODEF2P
12136 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")
12137 (match_parallel 2 "avx_vpermilp_<mode>_operand"
12138 [(match_operand 3 "const_int_operand" "")])))]
12141 int mask = avx_vpermilp_parallel (operands[2], <MODE>mode) - 1;
12142 operands[2] = GEN_INT (mask);
12143 return "vpermilp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}";
12145 [(set_attr "type" "sselog")
12146 (set_attr "prefix_extra" "1")
12147 (set_attr "length_immediate" "1")
12148 (set_attr "prefix" "vex")
12149 (set_attr "mode" "<MODE>")])
12151 (define_insn "avx_vpermilvar<mode>3"
12152 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
12154 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
12155 (match_operand:<avxpermvecmode> 2 "nonimmediate_operand" "xm")]
12158 "vpermilp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
12159 [(set_attr "type" "sselog")
12160 (set_attr "prefix_extra" "1")
12161 (set_attr "prefix" "vex")
12162 (set_attr "mode" "<MODE>")])
12164 (define_insn "avx_vperm2f128<mode>3"
12165 [(set (match_operand:AVX256MODE2P 0 "register_operand" "=x")
12166 (unspec:AVX256MODE2P
12167 [(match_operand:AVX256MODE2P 1 "register_operand" "x")
12168 (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm")
12169 (match_operand:SI 3 "const_0_to_255_operand" "n")]
12170 UNSPEC_VPERMIL2F128))]
12172 "vperm2f128\t{%3, %2, %1, %0|%0, %1, %2, %3}"
12173 [(set_attr "type" "sselog")
12174 (set_attr "prefix_extra" "1")
12175 (set_attr "length_immediate" "1")
12176 (set_attr "prefix" "vex")
12177 (set_attr "mode" "V8SF")])
12179 (define_insn "avx_vbroadcasts<avxmodesuffixf2c><avxmodesuffix>"
12180 [(set (match_operand:AVXMODEF4P 0 "register_operand" "=x")
12181 (vec_concat:AVXMODEF4P
12182 (vec_concat:<avxhalfvecmode>
12183 (match_operand:<avxscalarmode> 1 "memory_operand" "m")
12185 (vec_concat:<avxhalfvecmode>
12189 "vbroadcasts<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
12190 [(set_attr "type" "ssemov")
12191 (set_attr "prefix_extra" "1")
12192 (set_attr "prefix" "vex")
12193 (set_attr "mode" "<avxscalarmode>")])
12195 (define_insn "avx_vbroadcastss256"
12196 [(set (match_operand:V8SF 0 "register_operand" "=x")
12200 (match_operand:SF 1 "memory_operand" "m")
12213 "vbroadcastss\t{%1, %0|%0, %1}"
12214 [(set_attr "type" "ssemov")
12215 (set_attr "prefix_extra" "1")
12216 (set_attr "prefix" "vex")
12217 (set_attr "mode" "SF")])
12219 (define_insn "avx_vbroadcastf128_p<avxmodesuffixf2c>256"
12220 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x")
12221 (vec_concat:AVX256MODEF2P
12222 (match_operand:<avxhalfvecmode> 1 "memory_operand" "m")
12225 "vbroadcastf128\t{%1, %0|%0, %1}"
12226 [(set_attr "type" "ssemov")
12227 (set_attr "prefix_extra" "1")
12228 (set_attr "prefix" "vex")
12229 (set_attr "mode" "V4SF")])
12231 (define_expand "avx_vinsertf128<mode>"
12232 [(match_operand:AVX256MODE 0 "register_operand" "")
12233 (match_operand:AVX256MODE 1 "register_operand" "")
12234 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "")
12235 (match_operand:SI 3 "const_0_to_1_operand" "")]
12238 switch (INTVAL (operands[3]))
12241 emit_insn (gen_vec_set_lo_<mode> (operands[0], operands[1],
12245 emit_insn (gen_vec_set_hi_<mode> (operands[0], operands[1],
12249 gcc_unreachable ();
12254 (define_insn "vec_set_lo_<mode>"
12255 [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
12256 (vec_concat:AVX256MODE4P
12257 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")
12258 (vec_select:<avxhalfvecmode>
12259 (match_operand:AVX256MODE4P 1 "register_operand" "x")
12260 (parallel [(const_int 2) (const_int 3)]))))]
12262 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
12263 [(set_attr "type" "sselog")
12264 (set_attr "prefix_extra" "1")
12265 (set_attr "length_immediate" "1")
12266 (set_attr "prefix" "vex")
12267 (set_attr "mode" "V8SF")])
12269 (define_insn "vec_set_hi_<mode>"
12270 [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
12271 (vec_concat:AVX256MODE4P
12272 (vec_select:<avxhalfvecmode>
12273 (match_operand:AVX256MODE4P 1 "register_operand" "x")
12274 (parallel [(const_int 0) (const_int 1)]))
12275 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")))]
12277 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
12278 [(set_attr "type" "sselog")
12279 (set_attr "prefix_extra" "1")
12280 (set_attr "length_immediate" "1")
12281 (set_attr "prefix" "vex")
12282 (set_attr "mode" "V8SF")])
12284 (define_insn "vec_set_lo_<mode>"
12285 [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
12286 (vec_concat:AVX256MODE8P
12287 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")
12288 (vec_select:<avxhalfvecmode>
12289 (match_operand:AVX256MODE8P 1 "register_operand" "x")
12290 (parallel [(const_int 4) (const_int 5)
12291 (const_int 6) (const_int 7)]))))]
12293 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
12294 [(set_attr "type" "sselog")
12295 (set_attr "prefix_extra" "1")
12296 (set_attr "length_immediate" "1")
12297 (set_attr "prefix" "vex")
12298 (set_attr "mode" "V8SF")])
12300 (define_insn "vec_set_hi_<mode>"
12301 [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
12302 (vec_concat:AVX256MODE8P
12303 (vec_select:<avxhalfvecmode>
12304 (match_operand:AVX256MODE8P 1 "register_operand" "x")
12305 (parallel [(const_int 0) (const_int 1)
12306 (const_int 2) (const_int 3)]))
12307 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")))]
12309 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
12310 [(set_attr "type" "sselog")
12311 (set_attr "prefix_extra" "1")
12312 (set_attr "length_immediate" "1")
12313 (set_attr "prefix" "vex")
12314 (set_attr "mode" "V8SF")])
12316 (define_insn "vec_set_lo_v16hi"
12317 [(set (match_operand:V16HI 0 "register_operand" "=x")
12319 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
12321 (match_operand:V16HI 1 "register_operand" "x")
12322 (parallel [(const_int 8) (const_int 9)
12323 (const_int 10) (const_int 11)
12324 (const_int 12) (const_int 13)
12325 (const_int 14) (const_int 15)]))))]
12327 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
12328 [(set_attr "type" "sselog")
12329 (set_attr "prefix_extra" "1")
12330 (set_attr "length_immediate" "1")
12331 (set_attr "prefix" "vex")
12332 (set_attr "mode" "V8SF")])
12334 (define_insn "vec_set_hi_v16hi"
12335 [(set (match_operand:V16HI 0 "register_operand" "=x")
12338 (match_operand:V16HI 1 "register_operand" "x")
12339 (parallel [(const_int 0) (const_int 1)
12340 (const_int 2) (const_int 3)
12341 (const_int 4) (const_int 5)
12342 (const_int 6) (const_int 7)]))
12343 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
12345 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
12346 [(set_attr "type" "sselog")
12347 (set_attr "prefix_extra" "1")
12348 (set_attr "length_immediate" "1")
12349 (set_attr "prefix" "vex")
12350 (set_attr "mode" "V8SF")])
12352 (define_insn "vec_set_lo_v32qi"
12353 [(set (match_operand:V32QI 0 "register_operand" "=x")
12355 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
12357 (match_operand:V32QI 1 "register_operand" "x")
12358 (parallel [(const_int 16) (const_int 17)
12359 (const_int 18) (const_int 19)
12360 (const_int 20) (const_int 21)
12361 (const_int 22) (const_int 23)
12362 (const_int 24) (const_int 25)
12363 (const_int 26) (const_int 27)
12364 (const_int 28) (const_int 29)
12365 (const_int 30) (const_int 31)]))))]
12367 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
12368 [(set_attr "type" "sselog")
12369 (set_attr "prefix_extra" "1")
12370 (set_attr "length_immediate" "1")
12371 (set_attr "prefix" "vex")
12372 (set_attr "mode" "V8SF")])
12374 (define_insn "vec_set_hi_v32qi"
12375 [(set (match_operand:V32QI 0 "register_operand" "=x")
12378 (match_operand:V32QI 1 "register_operand" "x")
12379 (parallel [(const_int 0) (const_int 1)
12380 (const_int 2) (const_int 3)
12381 (const_int 4) (const_int 5)
12382 (const_int 6) (const_int 7)
12383 (const_int 8) (const_int 9)
12384 (const_int 10) (const_int 11)
12385 (const_int 12) (const_int 13)
12386 (const_int 14) (const_int 15)]))
12387 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
12389 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
12390 [(set_attr "type" "sselog")
12391 (set_attr "prefix_extra" "1")
12392 (set_attr "length_immediate" "1")
12393 (set_attr "prefix" "vex")
12394 (set_attr "mode" "V8SF")])
12396 (define_insn "avx_maskloadp<avxmodesuffixf2c><avxmodesuffix>"
12397 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
12399 [(match_operand:AVXMODEF2P 1 "memory_operand" "m")
12400 (match_operand:AVXMODEF2P 2 "register_operand" "x")
12404 "vmaskmovp<avxmodesuffixf2c>\t{%1, %2, %0|%0, %2, %1}"
12405 [(set_attr "type" "sselog1")
12406 (set_attr "prefix_extra" "1")
12407 (set_attr "prefix" "vex")
12408 (set_attr "mode" "<MODE>")])
12410 (define_insn "avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>"
12411 [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
12413 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
12414 (match_operand:AVXMODEF2P 2 "register_operand" "x")
12416 UNSPEC_MASKSTORE))]
12418 "vmaskmovp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
12419 [(set_attr "type" "sselog1")
12420 (set_attr "prefix_extra" "1")
12421 (set_attr "prefix" "vex")
12422 (set_attr "mode" "<MODE>")])
12424 (define_insn "avx_<avxmodesuffixp><avxmodesuffix>_<avxmodesuffixp>"
12425 [(set (match_operand:AVX256MODE2P 0 "register_operand" "=x,x")
12426 (unspec:AVX256MODE2P
12427 [(match_operand:<avxhalfvecmode> 1 "nonimmediate_operand" "0,xm")]
12431 switch (which_alternative)
12436 switch (get_attr_mode (insn))
12439 return "vmovaps\t{%1, %x0|%x0, %1}";
12441 return "vmovapd\t{%1, %x0|%x0, %1}";
12443 return "vmovdqa\t{%1, %x0|%x0, %1}";
12450 gcc_unreachable ();
12452 [(set_attr "type" "ssemov")
12453 (set_attr "prefix" "vex")
12454 (set_attr "mode" "<avxvecmode>")
12455 (set (attr "length")
12456 (if_then_else (eq_attr "alternative" "0")
12458 (const_string "*")))])
12460 (define_insn "avx_<avxmodesuffixp>_<avxmodesuffixp><avxmodesuffix>"
12461 [(set (match_operand:<avxhalfvecmode> 0 "register_operand" "=x,x")
12462 (unspec:<avxhalfvecmode>
12463 [(match_operand:AVX256MODE2P 1 "nonimmediate_operand" "0,xm")]
12467 switch (which_alternative)
12472 switch (get_attr_mode (insn))
12475 return "vmovaps\t{%x1, %0|%0, %x1}";
12477 return "vmovapd\t{%x1, %0|%0, %x1}";
12479 return "vmovdqa\t{%x1, %0|%0, %x1}";
12486 gcc_unreachable ();
12488 [(set_attr "type" "ssemov")
12489 (set_attr "prefix" "vex")
12490 (set_attr "mode" "<avxvecmode>")
12491 (set (attr "length")
12492 (if_then_else (eq_attr "alternative" "0")
12494 (const_string "*")))])
12496 (define_expand "vec_init<mode>"
12497 [(match_operand:AVX256MODE 0 "register_operand" "")
12498 (match_operand 1 "" "")]
12501 ix86_expand_vector_init (false, operands[0], operands[1]);
12505 (define_insn "*vec_concat<mode>_avx"
12506 [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
12507 (vec_concat:AVX256MODE
12508 (match_operand:<avxhalfvecmode> 1 "register_operand" "x,x")
12509 (match_operand:<avxhalfvecmode> 2 "vector_move_operand" "xm,C")))]
12512 switch (which_alternative)
12515 return "vinsertf128\t{$0x1, %2, %t1, %0|%0, %t1, %2, 0x1}";
12517 switch (get_attr_mode (insn))
12520 return "vmovaps\t{%1, %x0|%x0, %1}";
12522 return "vmovapd\t{%1, %x0|%x0, %1}";
12524 return "vmovdqa\t{%1, %x0|%x0, %1}";
12527 gcc_unreachable ();
12530 [(set_attr "type" "sselog,ssemov")
12531 (set_attr "prefix_extra" "1,*")
12532 (set_attr "length_immediate" "1,*")
12533 (set_attr "prefix" "vex")
12534 (set_attr "mode" "<avxvecmode>")])