* config/i386/i386.md (maxmin_int): Rename code attribute from maxminiprefix and update all users. (maxmin_float): Ditto from maxminfprefix. (logic): Ditto from logicprefix. (absneg_mnemonic): Ditto from absnegprefix. * config/i386/mmx.md: Update all users of maxminiprefix, maxminfprefix and loficprefix for rename. * config/i386/sse.md: Ditto. * config/i386/sync.md (sync_<code><mode>): Update for logicprefix rename. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158350 138bc75d-0d04-0410-961f-82ee72b054a4
2010-05-14 Harsha Jagasia <harsha.jagasia@amd.com> * config.gcc: Add support for --with-cpu option for bdver1. * config/i386/i386.h (TARGET_BDVER1): New macro. (ix86_tune_indices): Change SSE_UNALIGNED_MOVE_OPTIMAL to SSE_UNALIGNED_LOAD_OPTIMAL. Add SSE_UNALIGNED_STORE_OPTIMAL. (ix86_tune_features) :Change SSE_UNALIGNED_MOVE_OPTIMAL to SSE_UNALIGNED_LOAD_OPTIMAL. Add SSE_UNALIGNED_STORE_OPTIMAL. Add SSE_PACKED_SINGLE_INSN_OPTIMAL. (TARGET_CPU_DEFAULT_NAMES): Add bdver1. (processor_type): Add PROCESSOR_BDVER1. * config/i386/i386.md: Add bdver1 as a new cpu attribute to match processor_type in config/i386/i386.h. Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit movaps <reg, reg> instead of movapd <reg, reg> when replacing movsd <reg, reg> or movss <reg, reg> for SSE and AVX. Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed xor instead of packed double/packed integer xor for SSE and AVX when moving a zero value. * config/i386/sse.md: Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit movaps instead of movapd/movdqa for SSE and AVX. Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed single logical operations i.e and, or and xor instead of packed double logical operations for SSE and AVX. * config/i386/i386-c.c: (ix86_target_macros_internal): Add PROCESSOR_BDVER1. * config/i386/driver-i386.c: Turn on -mtune=native for BDVER1. (has_fma4, has_xop): New. * config/i386/i386.c (bdver1_cost): New variable. (m_BDVER1): New macro. (m_AMD_MULTIPLE): Add m_BDVER1. (x86_tune_use_leave, x86_tune_push_memory, x86_tune_unroll_strlen, x86_tune_deep_branch_prediction, x86_tune_use_sahf, x86_tune_movx, x86_tune_use_simode_fiop, x86_tune_promote_qimode, x86_tune_add_esp_8, x86_tune_tune_sub_esp_4, x86_tune_sub_esp_8, x86_tune_integer_dfmode_moves, x86_tune_partial_reg_dependency, x86_tune_sse_partial_reg_dependency, x86_tune_sse_unaligned_load_optimal, x86_tune_sse_unaligned_store_optimal, x86_tune_sse_typeless_stores, x86_tune_memory_mismatch_stall, x86_tune_use_ffreep, x86_tune_inter_unit_moves, x86_tune_inter_unit_conversions, x86_tune_use_bt, x86_tune_pad_returns, x86_tune_slow_imul_imm32_mem, x86_tune_slow_imul_imm8, x86_tune_fuse_cmp_and_branch): Enable/disable for bdver1. (processor_target_table): Add bdver1_cost. (cpu_names): Add bdver1. (override_options): Set up PROCESSOR_BDVER1 for bdver1 entry in processor_alias_table. (ix86_expand_vector_move_misalign): Change TARGET_SSE_UNALIGNED_MOVE_OPTIMAL to TARGET_SSE_UNALIGNED_LOAD_OPTIMAL. Check for TARGET_SSE_UNALIGNED_STORE_OPTIMAL. Check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit movups instead of movupd/movdqu for SSE and AVX. (ix86_tune_issue_rate): Add PROCESSOR_BDVER1. (ix86_tune_adjust_cost): Add code for bdver1. (standard_sse_constant_opcode): Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed single xor instead of packed double xor for SSE and AVX. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159399 138bc75d-0d04-0410-961f-82ee72b054a4
Support AVX for cmpss/cmpsd. gcc/ 2010-05-12 H.J. Lu <hongjiu.lu@intel.com> PR target/44088 * config/i386/sse.md (*avx_vmmaskcmp<mode>3): New. gcc/testsuite/ 2010-05-12 H.J. Lu <hongjiu.lu@intel.com> PR target/44088 * gcc.target/i386/avx-cmpsd-1.c: New. * gcc.target/i386/avx-cmpsd-2.c: Likewise. * gcc.target/i386/avx-cmpss-1.c: Likewise. * gcc.target/i386/avx-cmpss-2.c: Likewise. * gcc.target/i386/sse-cmpss-1.c: Likewise. * gcc.target/i386/sse2-cmpsd-1.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159319 138bc75d-0d04-0410-961f-82ee72b054a4
* config/i386/i386.md (maxmin_int): Rename code attribute from maxminiprefix and update all users. (maxmin_float): Ditto from maxminfprefix. (logic): Ditto from logicprefix. (absneg_mnemonic): Ditto from absnegprefix. * config/i386/mmx.md: Update all users of maxminiprefix, maxminfprefix and loficprefix for rename. * config/i386/sse.md: Ditto. * config/i386/sync.md (sync_<code><mode>): Update for logicprefix rename. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158350 138bc75d-0d04-0410-961f-82ee72b054a4
2010-05-14 Harsha Jagasia <harsha.jagasia@amd.com> * config.gcc: Add support for --with-cpu option for bdver1. * config/i386/i386.h (TARGET_BDVER1): New macro. (ix86_tune_indices): Change SSE_UNALIGNED_MOVE_OPTIMAL to SSE_UNALIGNED_LOAD_OPTIMAL. Add SSE_UNALIGNED_STORE_OPTIMAL. (ix86_tune_features) :Change SSE_UNALIGNED_MOVE_OPTIMAL to SSE_UNALIGNED_LOAD_OPTIMAL. Add SSE_UNALIGNED_STORE_OPTIMAL. Add SSE_PACKED_SINGLE_INSN_OPTIMAL. (TARGET_CPU_DEFAULT_NAMES): Add bdver1. (processor_type): Add PROCESSOR_BDVER1. * config/i386/i386.md: Add bdver1 as a new cpu attribute to match processor_type in config/i386/i386.h. Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit movaps <reg, reg> instead of movapd <reg, reg> when replacing movsd <reg, reg> or movss <reg, reg> for SSE and AVX. Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed xor instead of packed double/packed integer xor for SSE and AVX when moving a zero value. * config/i386/sse.md: Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit movaps instead of movapd/movdqa for SSE and AVX. Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed single logical operations i.e and, or and xor instead of packed double logical operations for SSE and AVX. * config/i386/i386-c.c: (ix86_target_macros_internal): Add PROCESSOR_BDVER1. * config/i386/driver-i386.c: Turn on -mtune=native for BDVER1. (has_fma4, has_xop): New. * config/i386/i386.c (bdver1_cost): New variable. (m_BDVER1): New macro. (m_AMD_MULTIPLE): Add m_BDVER1. (x86_tune_use_leave, x86_tune_push_memory, x86_tune_unroll_strlen, x86_tune_deep_branch_prediction, x86_tune_use_sahf, x86_tune_movx, x86_tune_use_simode_fiop, x86_tune_promote_qimode, x86_tune_add_esp_8, x86_tune_tune_sub_esp_4, x86_tune_sub_esp_8, x86_tune_integer_dfmode_moves, x86_tune_partial_reg_dependency, x86_tune_sse_partial_reg_dependency, x86_tune_sse_unaligned_load_optimal, x86_tune_sse_unaligned_store_optimal, x86_tune_sse_typeless_stores, x86_tune_memory_mismatch_stall, x86_tune_use_ffreep, x86_tune_inter_unit_moves, x86_tune_inter_unit_conversions, x86_tune_use_bt, x86_tune_pad_returns, x86_tune_slow_imul_imm32_mem, x86_tune_slow_imul_imm8, x86_tune_fuse_cmp_and_branch): Enable/disable for bdver1. (processor_target_table): Add bdver1_cost. (cpu_names): Add bdver1. (override_options): Set up PROCESSOR_BDVER1 for bdver1 entry in processor_alias_table. (ix86_expand_vector_move_misalign): Change TARGET_SSE_UNALIGNED_MOVE_OPTIMAL to TARGET_SSE_UNALIGNED_LOAD_OPTIMAL. Check for TARGET_SSE_UNALIGNED_STORE_OPTIMAL. Check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit movups instead of movupd/movdqu for SSE and AVX. (ix86_tune_issue_rate): Add PROCESSOR_BDVER1. (ix86_tune_adjust_cost): Add code for bdver1. (standard_sse_constant_opcode): Add check for TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL to emit packed single xor instead of packed double xor for SSE and AVX. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159399 138bc75d-0d04-0410-961f-82ee72b054a4
Support AVX for cmpss/cmpsd. gcc/ 2010-05-12 H.J. Lu <hongjiu.lu@intel.com> PR target/44088 * config/i386/sse.md (*avx_vmmaskcmp<mode>3): New. gcc/testsuite/ 2010-05-12 H.J. Lu <hongjiu.lu@intel.com> PR target/44088 * gcc.target/i386/avx-cmpsd-1.c: New. * gcc.target/i386/avx-cmpsd-2.c: Likewise. * gcc.target/i386/avx-cmpss-1.c: Likewise. * gcc.target/i386/avx-cmpss-2.c: Likewise. * gcc.target/i386/sse-cmpss-1.c: Likewise. * gcc.target/i386/sse2-cmpsd-1.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@159319 138bc75d-0d04-0410-961f-82ee72b054a4
* config/i386/i386.md (maxmin_int): Rename code attribute from maxminiprefix and update all users. (maxmin_float): Ditto from maxminfprefix. (logic): Ditto from logicprefix. (absneg_mnemonic): Ditto from absnegprefix. * config/i386/mmx.md: Update all users of maxminiprefix, maxminfprefix and loficprefix for rename. * config/i386/sse.md: Ditto. * config/i386/sync.md (sync_<code><mode>): Update for logicprefix rename. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158350 138bc75d-0d04-0410-961f-82ee72b054a4
2010-04-09 Richard Guenther <rguenther@suse.de> PR target/43152 * config/i386/sse.md (vcond<mode>): Handle AVX modes as well. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158158 138bc75d-0d04-0410-961f-82ee72b054a4
PR target/43067 * config/i386/sse.md (xop_mulv2div2di3_low): Change type attribute to ssemul. (xop_mulv2div2di3_high): Ditto. testsuite/ChangeLog: PR target/43067 * gcc.target/i386/pr43067.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@156929 138bc75d-0d04-0410-961f-82ee72b054a4
PR target/43103 * config/i386/sse.md (xop_vpermil2<mode>3): Use avxmodesuffixf2c for insn mnemonic suffix. testsuite/ChangeLog: PR target/43103 * gcc.target/i386/xop-check.h: Include m256-check.h. * gcc.target/i386/xop-vpermil2ps-1.c: Include x86intrin.h. * gcc.target/i386/xop-vpermil2ps-256-1.c: Ditto. * gcc.target/i386/xop-vpermil2pd-1.c: Ditto. * gcc.target/i386/xop-vpermil2pd-256-1.c: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@156827 138bc75d-0d04-0410-961f-82ee72b054a4
Add support for vpermil2p* in XOP. 2010-02-13 Sebastian Pop <sebastian.pop@amd.com> * config/i386/i386-builtin-types.def (V2DF_FTYPE_V2DF_V2DF_V2DI_INT): Declared. (V4DF_FTYPE_V4DF_V4DF_V4DI_INT): Declared. (V4SF_FTYPE_V4SF_V4SF_V4SI_INT): Declared. (V8SF_FTYPE_V8SF_V8SF_V8SI_INT): Declared. * config/i386/i386.c (enum ix86_builtins): Add IX86_BUILTIN_VPERMIL2PD, IX86_BUILTIN_VPERMIL2PS, IX86_BUILTIN_VPERMIL2PD256, and IX86_BUILTIN_VPERMIL2PS256. (MULTI_ARG_4_DF2_DI_I): Defined. (MULTI_ARG_4_DF2_DI_I1): Defined. (MULTI_ARG_4_SF2_SI_I): Defined. (MULTI_ARG_4_SF2_SI_I1): Defined. (bdesc_multi_arg): Add __builtin_ia32_vpermil2pd, __builtin_ia32_vpermil2ps, __builtin_ia32_vpermil2pd256, and __builtin_ia32_vpermil2ps256. (ix86_expand_multi_arg_builtin): Handle MULTI_ARG_4_DF2_DI_I, MULTI_ARG_4_DF2_DI_I1, MULTI_ARG_4_SF2_SI_I, and MULTI_ARG_4_SF2_SI_I1. Handle builtins with 4 arguments. (ix86_expand_args_builtin): Handle MULTI_ARG_4_DF2_DI_I, MULTI_ARG_4_DF2_DI_I1, MULTI_ARG_4_SF2_SI_I, and MULTI_ARG_4_SF2_SI_I1. Handle CODE_FOR_xop_vpermil2v2df3, CODE_FOR_xop_vpermil2v4sf3, CODE_FOR_xop_vpermil2v4df3, and CODE_FOR_xop_vpermil2v8sf3. * config/i386/i386.md (UNSPEC_VPERMIL2): Declared. * config/i386/sse.md (xop_vpermil2<mode>3): New insn pattern. * config/i386/xopintrin.h (_mm_permute2_pd): New. (_mm256_permute2_pd): New. (_mm_permute2_ps): New. (_mm256_permute2_ps): New. * gcc.target/i386/sse-14.c: Add tests for _mm_permute2_pd, _mm256_permute2_pd, _mm_permute2_ps, and _mm256_permute2_ps. * gcc.target/i386/xop-vpermil2pd-1.c: New. * gcc.target/i386/xop-vpermil2pd-256-1.c: New. * gcc.target/i386/xop-vpermil2ps-1.c: New. * gcc.target/i386/xop-vpermil2ps-256-1.c: New. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@156778 138bc75d-0d04-0410-961f-82ee72b054a4
* config/i386/sse.md (avx_vperm2f128<mode>3): Fix typo. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155943 138bc75d-0d04-0410-961f-82ee72b054a4
Add smaxv2di3, umaxv2di3, sminv2di3 and uminv2di3 gcc/ 2010-01-05 H.J. Lu <hongjiu.lu@intel.com> PR target/42542 * config/i386/sse.md (smaxv2di3): New. (umaxv2di3): Likewise. (sminv2di3): Likewise. (uminv2di3): Likewise. gcc/testsuite/ 2010-01-05 H.J. Lu <hongjiu.lu@intel.com> PR target/42542 * gcc.target/i386/pr42542-4.c: New. * gcc.target/i386/pr42542-4a.c: Likewise. * gcc.target/i386/pr42542-5.c: Likewise. * gcc.target/i386/pr42542-5a.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155666 138bc75d-0d04-0410-961f-82ee72b054a4
Properly convert GTU to GT for V4SI and V2DI gcc/ 2010-01-05 Paolo Bonzini <bonzinI@gnu.rg> H.J. Lu <hongjiu.lu@intel.com> PR target/42542 * config/i386/i386.c (ix86_expand_int_vcond): Convert GTU to GT for V4SI and V2DI by subtracting (-(INT MAX) - 1) from both operands to make them signed. * config/i386/sse.md (umaxv4si3): Revert the last change. (umin<mode>3): Likewise. (uminv8hi3): Removed. (uminv4si3): Likewise. gcc/testsuite/ 2010-01-05 H.J. Lu <hongjiu.lu@intel.com> * gcc.target/i386/pr42542-1.c (res): Make it 8 elements. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155660 138bc75d-0d04-0410-961f-82ee72b054a4
Don't convert GTU to GT for V4SI and V2DI gcc/ 2010-01-04 H.J. Lu <hongjiu.lu@intel.com> PR target/42542 * config/i386/i386.c (ix86_expand_int_vcond): Don't convert GTU to GT for V4SI and V2DI. * config/i386/sse.md (umaxv4si3): Enabled for SSE4.1 and XOP. (umin<mode>3): Removed. (uminv8hi3): New. (uminv4si3): Likewise. gcc/testsuite/ 2010-01-04 H.J. Lu <hongjiu.lu@intel.com> PR target/42542 * gcc.target/i386/pr42542-1.c: New. * gcc.target/i386/pr42542-1a.c: Likewise. * gcc.target/i386/pr42542-1b.c: Likewise. * gcc.target/i386/pr42542-2.c: Likewise. * gcc.target/i386/pr42542-2a.c: Likewise. * gcc.target/i386/pr42542-2b.c: Likewise. * gcc.target/i386/pr42542-3.c: Likewise. * gcc.target/i386/pr42542-3a.c: Likewise. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155618 138bc75d-0d04-0410-961f-82ee72b054a4
PR target/32280 * config/i386/i386-modes.def (V1TI): New vector mode. * config/i386/i386.h (VALID_SSE_REG_MODE): Add V1TImode. (SSE_REG_MODE_P): Ditto. * config/i386/sse.md (SSEMODE16): New mode iterator. (AVXMODE16): Ditto. (avxvecmode): Handle V1TI mode. (*avx_mov<mode>_internal): Use AVXMODE16 instead of AVXMODE. (mov<mode>): Use SSEMODE16 instead of SSEMODE. (*mov<mode>_internal): Ditto. (push<mode>1): Ditto. (movmisalign<mode>): Ditto. (sse2_ashlv1ti): Rename from sse2_ashlti. (sse2_lshrv1ti): Rename from sse2_lshrti. (*avx_ashlv1ti): Rename from *avx_ashlti and move from i386.md. (*avx_lshrv1ti): Rename from *avx_lshrti and move from i386.md. (vec_shl_<mode>): Convert operands to V1TImode and use V1TI shift. (vec_shr_<mode>): Ditto. (*sse2_mulv4si3): Update for renamed sse2_ashlv1ti3. (udot_prodv4si): Ditto. * config/i386/i386.c (classify_argument): Handle V1TImode. (function_arg_advance_32): Ditto. (function_arg_32): Ditto. (ix86_expand_sse4_unpack): Convert operands to V1TImode and update for renamed gen_sse2_lshrv1ti3. (ix86_expand_args_builtin) <V2DI_FTYPE_V2DI_INT_CONVERT>: Set rmode to V1TImode. (struct builtin_description) <__builtin_ia32_pslldqi128>: Update for renamed sse2_ashlv1ti3. <__builtin_ia32_psrldqi128>: Update for renamed sse2_lshrv1ti3. Revert: 2007-06-11 Uros Bizjak <ubizjak@gmail.com> PR target/32280 * config/i386/sse.md ("sse2_ashlti", "sse2_lshrti3"): Move ... * config/i386/i386.md ("sse2_ashlti", "sse2_lshrti3"): ... to here. testsuite/ChangeLog: PR target/32280 * gcc.target/i386/pr32280-1.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155312 138bc75d-0d04-0410-961f-82ee72b054a4
Remove XOP splitters. * config/i386/i386-protos.h (ix86_expand_fma4_multiple_memory): Removed. * config/i386/i386.c (ix86_expand_fma4_multiple_memory): Removed. * config/i386/sse.md: Remove all XOP splitters. Allow the second and fourth operands of XOP multiply-add insns to be nonimmediate. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155057 138bc75d-0d04-0410-961f-82ee72b054a4
Remove all FMA4 splitters. * config/i386/sse.md: Remove all FMA4 splitters. Allow the second operand of FMA4 insns to be a nonimmediate. Fix comments punctuation. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155056 138bc75d-0d04-0410-961f-82ee72b054a4
* config/i386/i386.md (any_or): New code iterator. (any_logic): Rename from plogic code iterator. (logicprefix): Rename from plogicprefix code attribute. (<code><mode>3): Macroize expander from {ior,xor}<mode>3 using any_or code iterator. (*<code><mode>_1): Macroize insn from *{ior,xor}<mode>_1 using any_or code iterator. (*<code><mode>_2): Ditto from *{ior,xor}<mode>_2. (*<code><mode>_3): Ditto from *{ior,xor}<mode>_3. (ior and xor splitters): Ditto. * config/i386/mmx.md: Updated for rename. * config/i386/sse.md: Ditto. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155037 138bc75d-0d04-0410-961f-82ee72b054a4
Add TARGET_FUSED_MADD to FMA4 insns. * config/i386/i386.c (TARGET_DEFAULT_TARGET_FLAGS): Add MASK_FUSED_MADD. * config/i386/i386.h (CC1_CPU_SPEC_1): Remove "'-mfused-madd' was removed". * config/i386/i386.opt (mfused-madd): New. * config/i386/sse.md: Add TARGET_FUSED_MADD to FMA4 insns. * doc/invoke.texi (-mfused-madd, -mno-fused-madd): Document. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@155015 138bc75d-0d04-0410-961f-82ee72b054a4