1 /* Optimize by combining instructions for GNU compiler.
2 Copyright (C) 1987, 1988, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
22 /* This module is essentially the "combiner" phase of the U. of Arizona
23 Portable Optimizer, but redone to work on our list-structured
24 representation for RTL instead of their string representation.
26 The LOG_LINKS of each insn identify the most recent assignment
27 to each REG used in the insn. It is a list of previous insns,
28 each of which contains a SET for a REG that is used in this insn
29 and not used or set in between. LOG_LINKs never cross basic blocks.
30 They were set up by the preceding pass (lifetime analysis).
32 We try to combine each pair of insns joined by a logical link.
33 We also try to combine triples of insns A, B and C when
34 C has a link back to B and B has a link back to A.
36 LOG_LINKS does not have links for use of the CC0. They don't
37 need to, because the insn that sets the CC0 is always immediately
38 before the insn that tests it. So we always regard a branch
39 insn as having a logical link to the preceding insn. The same is true
40 for an insn explicitly using CC0.
42 We check (with use_crosses_set_p) to avoid combining in such a way
43 as to move a computation to a place where its value would be different.
45 Combination is done by mathematically substituting the previous
46 insn(s) values for the regs they set into the expressions in
47 the later insns that refer to these regs. If the result is a valid insn
48 for our target machine, according to the machine description,
49 we install it, delete the earlier insns, and update the data flow
50 information (LOG_LINKS and REG_NOTES) for what we did.
52 There are a few exceptions where the dataflow information created by
53 flow.c aren't completely updated:
55 - reg_live_length is not updated
56 - reg_n_refs is not adjusted in the rare case when a register is
57 no longer required in a computation
58 - there are extremely rare cases (see distribute_regnotes) when a
60 - a LOG_LINKS entry that refers to an insn with multiple SETs may be
61 removed because there is no way to know which register it was
64 To simplify substitution, we combine only when the earlier insn(s)
65 consist of only a single assignment. To simplify updating afterward,
66 we never combine when a subroutine call appears in the middle.
68 Since we do not represent assignments to CC0 explicitly except when that
69 is all an insn does, there is no LOG_LINKS entry in an insn that uses
70 the condition code for the insn that set the condition code.
71 Fortunately, these two insns must be consecutive.
72 Therefore, every JUMP_INSN is taken to have an implicit logical link
73 to the preceding insn. This is not quite right, since non-jumps can
74 also use the condition code; but in practice such insns would not
79 #include "coretypes.h"
86 #include "hard-reg-set.h"
87 #include "basic-block.h"
88 #include "insn-config.h"
90 /* Include expr.h after insn-config.h so we get HAVE_conditional_move. */
92 #include "insn-attr.h"
98 #include "insn-codes.h"
99 #include "rtlhooks-def.h"
100 /* Include output.h for dump_file. */
104 #include "tree-pass.h"
106 /* Number of attempts to combine instructions in this function. */
108 static int combine_attempts;
110 /* Number of attempts that got as far as substitution in this function. */
112 static int combine_merges;
114 /* Number of instructions combined with added SETs in this function. */
116 static int combine_extras;
118 /* Number of instructions combined in this function. */
120 static int combine_successes;
122 /* Totals over entire compilation. */
124 static int total_attempts, total_merges, total_extras, total_successes;
127 /* Vector mapping INSN_UIDs to cuids.
128 The cuids are like uids but increase monotonically always.
129 Combine always uses cuids so that it can compare them.
130 But actually renumbering the uids, which we used to do,
131 proves to be a bad idea because it makes it hard to compare
132 the dumps produced by earlier passes with those from later passes. */
134 static int *uid_cuid;
135 static int max_uid_cuid;
137 /* Get the cuid of an insn. */
139 #define INSN_CUID(INSN) \
140 (INSN_UID (INSN) > max_uid_cuid ? insn_cuid (INSN) : uid_cuid[INSN_UID (INSN)])
142 /* In case BITS_PER_WORD == HOST_BITS_PER_WIDE_INT, shifting by
143 BITS_PER_WORD would invoke undefined behavior. Work around it. */
145 #define UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD(val) \
146 (((unsigned HOST_WIDE_INT) (val) << (BITS_PER_WORD - 1)) << 1)
148 /* Maximum register number, which is the size of the tables below. */
150 static unsigned int combine_max_regno;
153 /* Record last point of death of (hard or pseudo) register n. */
156 /* Record last point of modification of (hard or pseudo) register n. */
159 /* The next group of fields allows the recording of the last value assigned
160 to (hard or pseudo) register n. We use this information to see if an
161 operation being processed is redundant given a prior operation performed
162 on the register. For example, an `and' with a constant is redundant if
163 all the zero bits are already known to be turned off.
165 We use an approach similar to that used by cse, but change it in the
168 (1) We do not want to reinitialize at each label.
169 (2) It is useful, but not critical, to know the actual value assigned
170 to a register. Often just its form is helpful.
172 Therefore, we maintain the following fields:
174 last_set_value the last value assigned
175 last_set_label records the value of label_tick when the
176 register was assigned
177 last_set_table_tick records the value of label_tick when a
178 value using the register is assigned
179 last_set_invalid set to nonzero when it is not valid
180 to use the value of this register in some
183 To understand the usage of these tables, it is important to understand
184 the distinction between the value in last_set_value being valid and
185 the register being validly contained in some other expression in the
188 (The next two parameters are out of date).
190 reg_stat[i].last_set_value is valid if it is nonzero, and either
191 reg_n_sets[i] is 1 or reg_stat[i].last_set_label == label_tick.
193 Register I may validly appear in any expression returned for the value
194 of another register if reg_n_sets[i] is 1. It may also appear in the
195 value for register J if reg_stat[j].last_set_invalid is zero, or
196 reg_stat[i].last_set_label < reg_stat[j].last_set_label.
198 If an expression is found in the table containing a register which may
199 not validly appear in an expression, the register is replaced by
200 something that won't match, (clobber (const_int 0)). */
202 /* Record last value assigned to (hard or pseudo) register n. */
206 /* Record the value of label_tick when an expression involving register n
207 is placed in last_set_value. */
209 int last_set_table_tick;
211 /* Record the value of label_tick when the value for register n is placed in
216 /* These fields are maintained in parallel with last_set_value and are
217 used to store the mode in which the register was last set, the bits
218 that were known to be zero when it was last set, and the number of
219 sign bits copies it was known to have when it was last set. */
221 unsigned HOST_WIDE_INT last_set_nonzero_bits;
222 char last_set_sign_bit_copies;
223 ENUM_BITFIELD(machine_mode) last_set_mode : 8;
225 /* Set nonzero if references to register n in expressions should not be
226 used. last_set_invalid is set nonzero when this register is being
227 assigned to and last_set_table_tick == label_tick. */
229 char last_set_invalid;
231 /* Some registers that are set more than once and used in more than one
232 basic block are nevertheless always set in similar ways. For example,
233 a QImode register may be loaded from memory in two places on a machine
234 where byte loads zero extend.
236 We record in the following fields if a register has some leading bits
237 that are always equal to the sign bit, and what we know about the
238 nonzero bits of a register, specifically which bits are known to be
241 If an entry is zero, it means that we don't know anything special. */
243 unsigned char sign_bit_copies;
245 unsigned HOST_WIDE_INT nonzero_bits;
248 static struct reg_stat *reg_stat;
250 /* Record the cuid of the last insn that invalidated memory
251 (anything that writes memory, and subroutine calls, but not pushes). */
253 static int mem_last_set;
255 /* Record the cuid of the last CALL_INSN
256 so we can tell whether a potential combination crosses any calls. */
258 static int last_call_cuid;
260 /* When `subst' is called, this is the insn that is being modified
261 (by combining in a previous insn). The PATTERN of this insn
262 is still the old pattern partially modified and it should not be
263 looked at, but this may be used to examine the successors of the insn
264 to judge whether a simplification is valid. */
266 static rtx subst_insn;
268 /* This is the lowest CUID that `subst' is currently dealing with.
269 get_last_value will not return a value if the register was set at or
270 after this CUID. If not for this mechanism, we could get confused if
271 I2 or I1 in try_combine were an insn that used the old value of a register
272 to obtain a new value. In that case, we might erroneously get the
273 new value of the register when we wanted the old one. */
275 static int subst_low_cuid;
277 /* This contains any hard registers that are used in newpat; reg_dead_at_p
278 must consider all these registers to be always live. */
280 static HARD_REG_SET newpat_used_regs;
282 /* This is an insn to which a LOG_LINKS entry has been added. If this
283 insn is the earlier than I2 or I3, combine should rescan starting at
286 static rtx added_links_insn;
288 /* Basic block in which we are performing combines. */
289 static basic_block this_basic_block;
291 /* A bitmap indicating which blocks had registers go dead at entry.
292 After combine, we'll need to re-do global life analysis with
293 those blocks as starting points. */
294 static sbitmap refresh_blocks;
296 /* The following array records the insn_rtx_cost for every insn
297 in the instruction stream. */
299 static int *uid_insn_cost;
301 /* Length of the currently allocated uid_insn_cost array. */
303 static int last_insn_cost;
305 /* Incremented for each label. */
307 static int label_tick;
309 /* Mode used to compute significance in reg_stat[].nonzero_bits. It is the
310 largest integer mode that can fit in HOST_BITS_PER_WIDE_INT. */
312 static enum machine_mode nonzero_bits_mode;
314 /* Nonzero when reg_stat[].nonzero_bits and reg_stat[].sign_bit_copies can
315 be safely used. It is zero while computing them and after combine has
316 completed. This former test prevents propagating values based on
317 previously set values, which can be incorrect if a variable is modified
320 static int nonzero_sign_valid;
323 /* Record one modification to rtl structure
324 to be undone by storing old_contents into *where.
325 is_int is 1 if the contents are an int. */
331 union {rtx r; int i;} old_contents;
332 union {rtx *r; int *i;} where;
335 /* Record a bunch of changes to be undone, up to MAX_UNDO of them.
336 num_undo says how many are currently recorded.
338 other_insn is nonzero if we have modified some other insn in the process
339 of working on subst_insn. It must be verified too. */
348 static struct undobuf undobuf;
350 /* Number of times the pseudo being substituted for
351 was found and replaced. */
353 static int n_occurrences;
355 static rtx reg_nonzero_bits_for_combine (rtx, enum machine_mode, rtx,
357 unsigned HOST_WIDE_INT,
358 unsigned HOST_WIDE_INT *);
359 static rtx reg_num_sign_bit_copies_for_combine (rtx, enum machine_mode, rtx,
361 unsigned int, unsigned int *);
362 static void do_SUBST (rtx *, rtx);
363 static void do_SUBST_INT (int *, int);
364 static void init_reg_last (void);
365 static void setup_incoming_promotions (void);
366 static void set_nonzero_bits_and_sign_copies (rtx, rtx, void *);
367 static int cant_combine_insn_p (rtx);
368 static int can_combine_p (rtx, rtx, rtx, rtx, rtx *, rtx *);
369 static int combinable_i3pat (rtx, rtx *, rtx, rtx, int, rtx *);
370 static int contains_muldiv (rtx);
371 static rtx try_combine (rtx, rtx, rtx, int *);
372 static void undo_all (void);
373 static void undo_commit (void);
374 static rtx *find_split_point (rtx *, rtx);
375 static rtx subst (rtx, rtx, rtx, int, int);
376 static rtx combine_simplify_rtx (rtx, enum machine_mode, int);
377 static rtx simplify_if_then_else (rtx);
378 static rtx simplify_set (rtx);
379 static rtx simplify_logical (rtx);
380 static rtx expand_compound_operation (rtx);
381 static rtx expand_field_assignment (rtx);
382 static rtx make_extraction (enum machine_mode, rtx, HOST_WIDE_INT,
383 rtx, unsigned HOST_WIDE_INT, int, int, int);
384 static rtx extract_left_shift (rtx, int);
385 static rtx make_compound_operation (rtx, enum rtx_code);
386 static int get_pos_from_mask (unsigned HOST_WIDE_INT,
387 unsigned HOST_WIDE_INT *);
388 static rtx canon_reg_for_combine (rtx, rtx);
389 static rtx force_to_mode (rtx, enum machine_mode,
390 unsigned HOST_WIDE_INT, int);
391 static rtx if_then_else_cond (rtx, rtx *, rtx *);
392 static rtx known_cond (rtx, enum rtx_code, rtx, rtx);
393 static int rtx_equal_for_field_assignment_p (rtx, rtx);
394 static rtx make_field_assignment (rtx);
395 static rtx apply_distributive_law (rtx);
396 static rtx distribute_and_simplify_rtx (rtx, int);
397 static rtx simplify_and_const_int (rtx, enum machine_mode, rtx,
398 unsigned HOST_WIDE_INT);
399 static int merge_outer_ops (enum rtx_code *, HOST_WIDE_INT *, enum rtx_code,
400 HOST_WIDE_INT, enum machine_mode, int *);
401 static rtx simplify_shift_const (rtx, enum rtx_code, enum machine_mode, rtx,
403 static int recog_for_combine (rtx *, rtx, rtx *);
404 static rtx gen_lowpart_for_combine (enum machine_mode, rtx);
405 static enum rtx_code simplify_comparison (enum rtx_code, rtx *, rtx *);
406 static void update_table_tick (rtx);
407 static void record_value_for_reg (rtx, rtx, rtx);
408 static void check_promoted_subreg (rtx, rtx);
409 static void record_dead_and_set_regs_1 (rtx, rtx, void *);
410 static void record_dead_and_set_regs (rtx);
411 static int get_last_value_validate (rtx *, rtx, int, int);
412 static rtx get_last_value (rtx);
413 static int use_crosses_set_p (rtx, int);
414 static void reg_dead_at_p_1 (rtx, rtx, void *);
415 static int reg_dead_at_p (rtx, rtx);
416 static void move_deaths (rtx, rtx, int, rtx, rtx *);
417 static int reg_bitfield_target_p (rtx, rtx);
418 static void distribute_notes (rtx, rtx, rtx, rtx, rtx, rtx);
419 static void distribute_links (rtx);
420 static void mark_used_regs_combine (rtx);
421 static int insn_cuid (rtx);
422 static void record_promoted_value (rtx, rtx);
423 static int unmentioned_reg_p_1 (rtx *, void *);
424 static bool unmentioned_reg_p (rtx, rtx);
427 /* It is not safe to use ordinary gen_lowpart in combine.
428 See comments in gen_lowpart_for_combine. */
429 #undef RTL_HOOKS_GEN_LOWPART
430 #define RTL_HOOKS_GEN_LOWPART gen_lowpart_for_combine
432 /* Our implementation of gen_lowpart never emits a new pseudo. */
433 #undef RTL_HOOKS_GEN_LOWPART_NO_EMIT
434 #define RTL_HOOKS_GEN_LOWPART_NO_EMIT gen_lowpart_for_combine
436 #undef RTL_HOOKS_REG_NONZERO_REG_BITS
437 #define RTL_HOOKS_REG_NONZERO_REG_BITS reg_nonzero_bits_for_combine
439 #undef RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES
440 #define RTL_HOOKS_REG_NUM_SIGN_BIT_COPIES reg_num_sign_bit_copies_for_combine
442 static const struct rtl_hooks combine_rtl_hooks = RTL_HOOKS_INITIALIZER;
445 /* Substitute NEWVAL, an rtx expression, into INTO, a place in some
446 insn. The substitution can be undone by undo_all. If INTO is already
447 set to NEWVAL, do not record this change. Because computing NEWVAL might
448 also call SUBST, we have to compute it before we put anything into
452 do_SUBST (rtx *into, rtx newval)
457 if (oldval == newval)
460 /* We'd like to catch as many invalid transformations here as
461 possible. Unfortunately, there are way too many mode changes
462 that are perfectly valid, so we'd waste too much effort for
463 little gain doing the checks here. Focus on catching invalid
464 transformations involving integer constants. */
465 if (GET_MODE_CLASS (GET_MODE (oldval)) == MODE_INT
466 && GET_CODE (newval) == CONST_INT)
468 /* Sanity check that we're replacing oldval with a CONST_INT
469 that is a valid sign-extension for the original mode. */
470 gcc_assert (INTVAL (newval)
471 == trunc_int_for_mode (INTVAL (newval), GET_MODE (oldval)));
473 /* Replacing the operand of a SUBREG or a ZERO_EXTEND with a
474 CONST_INT is not valid, because after the replacement, the
475 original mode would be gone. Unfortunately, we can't tell
476 when do_SUBST is called to replace the operand thereof, so we
477 perform this test on oldval instead, checking whether an
478 invalid replacement took place before we got here. */
479 gcc_assert (!(GET_CODE (oldval) == SUBREG
480 && GET_CODE (SUBREG_REG (oldval)) == CONST_INT));
481 gcc_assert (!(GET_CODE (oldval) == ZERO_EXTEND
482 && GET_CODE (XEXP (oldval, 0)) == CONST_INT));
486 buf = undobuf.frees, undobuf.frees = buf->next;
488 buf = xmalloc (sizeof (struct undo));
492 buf->old_contents.r = oldval;
495 buf->next = undobuf.undos, undobuf.undos = buf;
498 #define SUBST(INTO, NEWVAL) do_SUBST(&(INTO), (NEWVAL))
500 /* Similar to SUBST, but NEWVAL is an int expression. Note that substitution
501 for the value of a HOST_WIDE_INT value (including CONST_INT) is
505 do_SUBST_INT (int *into, int newval)
510 if (oldval == newval)
514 buf = undobuf.frees, undobuf.frees = buf->next;
516 buf = xmalloc (sizeof (struct undo));
520 buf->old_contents.i = oldval;
523 buf->next = undobuf.undos, undobuf.undos = buf;
526 #define SUBST_INT(INTO, NEWVAL) do_SUBST_INT(&(INTO), (NEWVAL))
528 /* Subroutine of try_combine. Determine whether the combine replacement
529 patterns NEWPAT and NEWI2PAT are cheaper according to insn_rtx_cost
530 that the original instruction sequence I1, I2 and I3. Note that I1
531 and/or NEWI2PAT may be NULL_RTX. This function returns false, if the
532 costs of all instructions can be estimated, and the replacements are
533 more expensive than the original sequence. */
536 combine_validate_cost (rtx i1, rtx i2, rtx i3, rtx newpat, rtx newi2pat)
538 int i1_cost, i2_cost, i3_cost;
539 int new_i2_cost, new_i3_cost;
540 int old_cost, new_cost;
542 /* Lookup the original insn_rtx_costs. */
543 i2_cost = INSN_UID (i2) <= last_insn_cost
544 ? uid_insn_cost[INSN_UID (i2)] : 0;
545 i3_cost = INSN_UID (i3) <= last_insn_cost
546 ? uid_insn_cost[INSN_UID (i3)] : 0;
550 i1_cost = INSN_UID (i1) <= last_insn_cost
551 ? uid_insn_cost[INSN_UID (i1)] : 0;
552 old_cost = (i1_cost > 0 && i2_cost > 0 && i3_cost > 0)
553 ? i1_cost + i2_cost + i3_cost : 0;
557 old_cost = (i2_cost > 0 && i3_cost > 0) ? i2_cost + i3_cost : 0;
561 /* Calculate the replacement insn_rtx_costs. */
562 new_i3_cost = insn_rtx_cost (newpat);
565 new_i2_cost = insn_rtx_cost (newi2pat);
566 new_cost = (new_i2_cost > 0 && new_i3_cost > 0)
567 ? new_i2_cost + new_i3_cost : 0;
571 new_cost = new_i3_cost;
575 if (undobuf.other_insn)
577 int old_other_cost, new_other_cost;
579 old_other_cost = (INSN_UID (undobuf.other_insn) <= last_insn_cost
580 ? uid_insn_cost[INSN_UID (undobuf.other_insn)] : 0);
581 new_other_cost = insn_rtx_cost (PATTERN (undobuf.other_insn));
582 if (old_other_cost > 0 && new_other_cost > 0)
584 old_cost += old_other_cost;
585 new_cost += new_other_cost;
591 /* Disallow this recombination if both new_cost and old_cost are
592 greater than zero, and new_cost is greater than old cost. */
594 && new_cost > old_cost)
601 "rejecting combination of insns %d, %d and %d\n",
602 INSN_UID (i1), INSN_UID (i2), INSN_UID (i3));
603 fprintf (dump_file, "original costs %d + %d + %d = %d\n",
604 i1_cost, i2_cost, i3_cost, old_cost);
609 "rejecting combination of insns %d and %d\n",
610 INSN_UID (i2), INSN_UID (i3));
611 fprintf (dump_file, "original costs %d + %d = %d\n",
612 i2_cost, i3_cost, old_cost);
617 fprintf (dump_file, "replacement costs %d + %d = %d\n",
618 new_i2_cost, new_i3_cost, new_cost);
621 fprintf (dump_file, "replacement cost %d\n", new_cost);
627 /* Update the uid_insn_cost array with the replacement costs. */
628 uid_insn_cost[INSN_UID (i2)] = new_i2_cost;
629 uid_insn_cost[INSN_UID (i3)] = new_i3_cost;
631 uid_insn_cost[INSN_UID (i1)] = 0;
636 /* Main entry point for combiner. F is the first insn of the function.
637 NREGS is the first unused pseudo-reg number.
639 Return nonzero if the combiner has turned an indirect jump
640 instruction into a direct jump. */
642 combine_instructions (rtx f, unsigned int nregs)
650 rtx links, nextlinks;
651 sbitmap_iterator sbi;
653 int new_direct_jump_p = 0;
655 combine_attempts = 0;
658 combine_successes = 0;
660 combine_max_regno = nregs;
662 rtl_hooks = combine_rtl_hooks;
664 reg_stat = xcalloc (nregs, sizeof (struct reg_stat));
666 init_recog_no_volatile ();
668 /* Compute maximum uid value so uid_cuid can be allocated. */
670 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
671 if (INSN_UID (insn) > i)
674 uid_cuid = xmalloc ((i + 1) * sizeof (int));
677 nonzero_bits_mode = mode_for_size (HOST_BITS_PER_WIDE_INT, MODE_INT, 0);
679 /* Don't use reg_stat[].nonzero_bits when computing it. This can cause
680 problems when, for example, we have j <<= 1 in a loop. */
682 nonzero_sign_valid = 0;
684 /* Compute the mapping from uids to cuids.
685 Cuids are numbers assigned to insns, like uids,
686 except that cuids increase monotonically through the code.
688 Scan all SETs and see if we can deduce anything about what
689 bits are known to be zero for some registers and how many copies
690 of the sign bit are known to exist for those registers.
692 Also set any known values so that we can use it while searching
693 for what bits are known to be set. */
697 setup_incoming_promotions ();
699 refresh_blocks = sbitmap_alloc (last_basic_block);
700 sbitmap_zero (refresh_blocks);
702 /* Allocate array of current insn_rtx_costs. */
703 uid_insn_cost = xcalloc (max_uid_cuid + 1, sizeof (int));
704 last_insn_cost = max_uid_cuid;
706 for (insn = f, i = 0; insn; insn = NEXT_INSN (insn))
708 uid_cuid[INSN_UID (insn)] = ++i;
714 note_stores (PATTERN (insn), set_nonzero_bits_and_sign_copies,
716 record_dead_and_set_regs (insn);
719 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
720 if (REG_NOTE_KIND (links) == REG_INC)
721 set_nonzero_bits_and_sign_copies (XEXP (links, 0), NULL_RTX,
725 /* Record the current insn_rtx_cost of this instruction. */
726 if (NONJUMP_INSN_P (insn))
727 uid_insn_cost[INSN_UID (insn)] = insn_rtx_cost (PATTERN (insn));
729 fprintf(dump_file, "insn_cost %d: %d\n",
730 INSN_UID (insn), uid_insn_cost[INSN_UID (insn)]);
737 nonzero_sign_valid = 1;
739 /* Now scan all the insns in forward order. */
745 setup_incoming_promotions ();
747 FOR_EACH_BB (this_basic_block)
749 for (insn = BB_HEAD (this_basic_block);
750 insn != NEXT_INSN (BB_END (this_basic_block));
751 insn = next ? next : NEXT_INSN (insn))
758 else if (INSN_P (insn))
760 /* See if we know about function return values before this
761 insn based upon SUBREG flags. */
762 check_promoted_subreg (insn, PATTERN (insn));
764 /* Try this insn with each insn it links back to. */
766 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
767 if ((next = try_combine (insn, XEXP (links, 0),
768 NULL_RTX, &new_direct_jump_p)) != 0)
771 /* Try each sequence of three linked insns ending with this one. */
773 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
775 rtx link = XEXP (links, 0);
777 /* If the linked insn has been replaced by a note, then there
778 is no point in pursuing this chain any further. */
782 for (nextlinks = LOG_LINKS (link);
784 nextlinks = XEXP (nextlinks, 1))
785 if ((next = try_combine (insn, link,
787 &new_direct_jump_p)) != 0)
792 /* Try to combine a jump insn that uses CC0
793 with a preceding insn that sets CC0, and maybe with its
794 logical predecessor as well.
795 This is how we make decrement-and-branch insns.
796 We need this special code because data flow connections
797 via CC0 do not get entered in LOG_LINKS. */
800 && (prev = prev_nonnote_insn (insn)) != 0
801 && NONJUMP_INSN_P (prev)
802 && sets_cc0_p (PATTERN (prev)))
804 if ((next = try_combine (insn, prev,
805 NULL_RTX, &new_direct_jump_p)) != 0)
808 for (nextlinks = LOG_LINKS (prev); nextlinks;
809 nextlinks = XEXP (nextlinks, 1))
810 if ((next = try_combine (insn, prev,
812 &new_direct_jump_p)) != 0)
816 /* Do the same for an insn that explicitly references CC0. */
817 if (NONJUMP_INSN_P (insn)
818 && (prev = prev_nonnote_insn (insn)) != 0
819 && NONJUMP_INSN_P (prev)
820 && sets_cc0_p (PATTERN (prev))
821 && GET_CODE (PATTERN (insn)) == SET
822 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (insn))))
824 if ((next = try_combine (insn, prev,
825 NULL_RTX, &new_direct_jump_p)) != 0)
828 for (nextlinks = LOG_LINKS (prev); nextlinks;
829 nextlinks = XEXP (nextlinks, 1))
830 if ((next = try_combine (insn, prev,
832 &new_direct_jump_p)) != 0)
836 /* Finally, see if any of the insns that this insn links to
837 explicitly references CC0. If so, try this insn, that insn,
838 and its predecessor if it sets CC0. */
839 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
840 if (NONJUMP_INSN_P (XEXP (links, 0))
841 && GET_CODE (PATTERN (XEXP (links, 0))) == SET
842 && reg_mentioned_p (cc0_rtx, SET_SRC (PATTERN (XEXP (links, 0))))
843 && (prev = prev_nonnote_insn (XEXP (links, 0))) != 0
844 && NONJUMP_INSN_P (prev)
845 && sets_cc0_p (PATTERN (prev))
846 && (next = try_combine (insn, XEXP (links, 0),
847 prev, &new_direct_jump_p)) != 0)
851 /* Try combining an insn with two different insns whose results it
853 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
854 for (nextlinks = XEXP (links, 1); nextlinks;
855 nextlinks = XEXP (nextlinks, 1))
856 if ((next = try_combine (insn, XEXP (links, 0),
858 &new_direct_jump_p)) != 0)
861 /* Try this insn with each REG_EQUAL note it links back to. */
862 for (links = LOG_LINKS (insn); links; links = XEXP (links, 1))
865 rtx temp = XEXP (links, 0);
866 if ((set = single_set (temp)) != 0
867 && (note = find_reg_equal_equiv_note (temp)) != 0
868 && (note = XEXP (note, 0), GET_CODE (note)) != EXPR_LIST
869 /* Avoid using a register that may already been marked
870 dead by an earlier instruction. */
871 && ! unmentioned_reg_p (note, SET_SRC (set))
872 && (GET_MODE (note) == VOIDmode
873 ? SCALAR_INT_MODE_P (GET_MODE (SET_DEST (set)))
874 : GET_MODE (SET_DEST (set)) == GET_MODE (note)))
876 /* Temporarily replace the set's source with the
877 contents of the REG_EQUAL note. The insn will
878 be deleted or recognized by try_combine. */
879 rtx orig = SET_SRC (set);
880 SET_SRC (set) = note;
881 next = try_combine (insn, temp, NULL_RTX,
885 SET_SRC (set) = orig;
890 record_dead_and_set_regs (insn);
899 EXECUTE_IF_SET_IN_SBITMAP (refresh_blocks, 0, j, sbi)
900 BASIC_BLOCK (j)->flags |= BB_DIRTY;
901 new_direct_jump_p |= purge_all_dead_edges ();
902 delete_noop_moves ();
904 update_life_info_in_dirty_blocks (UPDATE_LIFE_GLOBAL_RM_NOTES,
905 PROP_DEATH_NOTES | PROP_SCAN_DEAD_CODE
906 | PROP_KILL_DEAD_CODE);
909 sbitmap_free (refresh_blocks);
910 free (uid_insn_cost);
915 struct undo *undo, *next;
916 for (undo = undobuf.frees; undo; undo = next)
924 total_attempts += combine_attempts;
925 total_merges += combine_merges;
926 total_extras += combine_extras;
927 total_successes += combine_successes;
929 nonzero_sign_valid = 0;
930 rtl_hooks = general_rtl_hooks;
932 /* Make recognizer allow volatile MEMs again. */
935 return new_direct_jump_p;
938 /* Wipe the last_xxx fields of reg_stat in preparation for another pass. */
944 for (i = 0; i < combine_max_regno; i++)
945 memset (reg_stat + i, 0, offsetof (struct reg_stat, sign_bit_copies));
948 /* Set up any promoted values for incoming argument registers. */
951 setup_incoming_promotions (void)
955 enum machine_mode mode;
957 rtx first = get_insns ();
959 if (targetm.calls.promote_function_args (TREE_TYPE (cfun->decl)))
961 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
962 /* Check whether this register can hold an incoming pointer
963 argument. FUNCTION_ARG_REGNO_P tests outgoing register
964 numbers, so translate if necessary due to register windows. */
965 if (FUNCTION_ARG_REGNO_P (OUTGOING_REGNO (regno))
966 && (reg = promoted_input_arg (regno, &mode, &unsignedp)) != 0)
969 (reg, first, gen_rtx_fmt_e ((unsignedp ? ZERO_EXTEND
972 gen_rtx_CLOBBER (mode, const0_rtx)));
977 /* Called via note_stores. If X is a pseudo that is narrower than
978 HOST_BITS_PER_WIDE_INT and is being set, record what bits are known zero.
980 If we are setting only a portion of X and we can't figure out what
981 portion, assume all bits will be used since we don't know what will
984 Similarly, set how many bits of X are known to be copies of the sign bit
985 at all locations in the function. This is the smallest number implied
989 set_nonzero_bits_and_sign_copies (rtx x, rtx set,
990 void *data ATTRIBUTE_UNUSED)
995 && REGNO (x) >= FIRST_PSEUDO_REGISTER
996 /* If this register is undefined at the start of the file, we can't
997 say what its contents were. */
999 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start, REGNO (x))
1000 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
1002 if (set == 0 || GET_CODE (set) == CLOBBER)
1004 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1005 reg_stat[REGNO (x)].sign_bit_copies = 1;
1009 /* If this is a complex assignment, see if we can convert it into a
1010 simple assignment. */
1011 set = expand_field_assignment (set);
1013 /* If this is a simple assignment, or we have a paradoxical SUBREG,
1014 set what we know about X. */
1016 if (SET_DEST (set) == x
1017 || (GET_CODE (SET_DEST (set)) == SUBREG
1018 && (GET_MODE_SIZE (GET_MODE (SET_DEST (set)))
1019 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (set)))))
1020 && SUBREG_REG (SET_DEST (set)) == x))
1022 rtx src = SET_SRC (set);
1024 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
1025 /* If X is narrower than a word and SRC is a non-negative
1026 constant that would appear negative in the mode of X,
1027 sign-extend it for use in reg_stat[].nonzero_bits because some
1028 machines (maybe most) will actually do the sign-extension
1029 and this is the conservative approach.
1031 ??? For 2.5, try to tighten up the MD files in this regard
1032 instead of this kludge. */
1034 if (GET_MODE_BITSIZE (GET_MODE (x)) < BITS_PER_WORD
1035 && GET_CODE (src) == CONST_INT
1037 && 0 != (INTVAL (src)
1038 & ((HOST_WIDE_INT) 1
1039 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
1040 src = GEN_INT (INTVAL (src)
1041 | ((HOST_WIDE_INT) (-1)
1042 << GET_MODE_BITSIZE (GET_MODE (x))));
1045 /* Don't call nonzero_bits if it cannot change anything. */
1046 if (reg_stat[REGNO (x)].nonzero_bits != ~(unsigned HOST_WIDE_INT) 0)
1047 reg_stat[REGNO (x)].nonzero_bits
1048 |= nonzero_bits (src, nonzero_bits_mode);
1049 num = num_sign_bit_copies (SET_SRC (set), GET_MODE (x));
1050 if (reg_stat[REGNO (x)].sign_bit_copies == 0
1051 || reg_stat[REGNO (x)].sign_bit_copies > num)
1052 reg_stat[REGNO (x)].sign_bit_copies = num;
1056 reg_stat[REGNO (x)].nonzero_bits = GET_MODE_MASK (GET_MODE (x));
1057 reg_stat[REGNO (x)].sign_bit_copies = 1;
1062 /* See if INSN can be combined into I3. PRED and SUCC are optionally
1063 insns that were previously combined into I3 or that will be combined
1064 into the merger of INSN and I3.
1066 Return 0 if the combination is not allowed for any reason.
1068 If the combination is allowed, *PDEST will be set to the single
1069 destination of INSN and *PSRC to the single source, and this function
1073 can_combine_p (rtx insn, rtx i3, rtx pred ATTRIBUTE_UNUSED, rtx succ,
1074 rtx *pdest, rtx *psrc)
1077 rtx set = 0, src, dest;
1082 int all_adjacent = (succ ? (next_active_insn (insn) == succ
1083 && next_active_insn (succ) == i3)
1084 : next_active_insn (insn) == i3);
1086 /* Can combine only if previous insn is a SET of a REG, a SUBREG or CC0.
1087 or a PARALLEL consisting of such a SET and CLOBBERs.
1089 If INSN has CLOBBER parallel parts, ignore them for our processing.
1090 By definition, these happen during the execution of the insn. When it
1091 is merged with another insn, all bets are off. If they are, in fact,
1092 needed and aren't also supplied in I3, they may be added by
1093 recog_for_combine. Otherwise, it won't match.
1095 We can also ignore a SET whose SET_DEST is mentioned in a REG_UNUSED
1098 Get the source and destination of INSN. If more than one, can't
1101 if (GET_CODE (PATTERN (insn)) == SET)
1102 set = PATTERN (insn);
1103 else if (GET_CODE (PATTERN (insn)) == PARALLEL
1104 && GET_CODE (XVECEXP (PATTERN (insn), 0, 0)) == SET)
1106 for (i = 0; i < XVECLEN (PATTERN (insn), 0); i++)
1108 rtx elt = XVECEXP (PATTERN (insn), 0, i);
1111 switch (GET_CODE (elt))
1113 /* This is important to combine floating point insns
1114 for the SH4 port. */
1116 /* Combining an isolated USE doesn't make sense.
1117 We depend here on combinable_i3pat to reject them. */
1118 /* The code below this loop only verifies that the inputs of
1119 the SET in INSN do not change. We call reg_set_between_p
1120 to verify that the REG in the USE does not change between
1122 If the USE in INSN was for a pseudo register, the matching
1123 insn pattern will likely match any register; combining this
1124 with any other USE would only be safe if we knew that the
1125 used registers have identical values, or if there was
1126 something to tell them apart, e.g. different modes. For
1127 now, we forgo such complicated tests and simply disallow
1128 combining of USES of pseudo registers with any other USE. */
1129 if (REG_P (XEXP (elt, 0))
1130 && GET_CODE (PATTERN (i3)) == PARALLEL)
1132 rtx i3pat = PATTERN (i3);
1133 int i = XVECLEN (i3pat, 0) - 1;
1134 unsigned int regno = REGNO (XEXP (elt, 0));
1138 rtx i3elt = XVECEXP (i3pat, 0, i);
1140 if (GET_CODE (i3elt) == USE
1141 && REG_P (XEXP (i3elt, 0))
1142 && (REGNO (XEXP (i3elt, 0)) == regno
1143 ? reg_set_between_p (XEXP (elt, 0),
1144 PREV_INSN (insn), i3)
1145 : regno >= FIRST_PSEUDO_REGISTER))
1152 /* We can ignore CLOBBERs. */
1157 /* Ignore SETs whose result isn't used but not those that
1158 have side-effects. */
1159 if (find_reg_note (insn, REG_UNUSED, SET_DEST (elt))
1160 && (!(note = find_reg_note (insn, REG_EH_REGION, NULL_RTX))
1161 || INTVAL (XEXP (note, 0)) <= 0)
1162 && ! side_effects_p (elt))
1165 /* If we have already found a SET, this is a second one and
1166 so we cannot combine with this insn. */
1174 /* Anything else means we can't combine. */
1180 /* If SET_SRC is an ASM_OPERANDS we can't throw away these CLOBBERs,
1181 so don't do anything with it. */
1182 || GET_CODE (SET_SRC (set)) == ASM_OPERANDS)
1191 set = expand_field_assignment (set);
1192 src = SET_SRC (set), dest = SET_DEST (set);
1194 /* Don't eliminate a store in the stack pointer. */
1195 if (dest == stack_pointer_rtx
1196 /* Don't combine with an insn that sets a register to itself if it has
1197 a REG_EQUAL note. This may be part of a REG_NO_CONFLICT sequence. */
1198 || (rtx_equal_p (src, dest) && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1199 /* Can't merge an ASM_OPERANDS. */
1200 || GET_CODE (src) == ASM_OPERANDS
1201 /* Can't merge a function call. */
1202 || GET_CODE (src) == CALL
1203 /* Don't eliminate a function call argument. */
1205 && (find_reg_fusage (i3, USE, dest)
1207 && REGNO (dest) < FIRST_PSEUDO_REGISTER
1208 && global_regs[REGNO (dest)])))
1209 /* Don't substitute into an incremented register. */
1210 || FIND_REG_INC_NOTE (i3, dest)
1211 || (succ && FIND_REG_INC_NOTE (succ, dest))
1212 /* Don't substitute into a non-local goto, this confuses CFG. */
1213 || (JUMP_P (i3) && find_reg_note (i3, REG_NON_LOCAL_GOTO, NULL_RTX))
1215 /* Don't combine the end of a libcall into anything. */
1216 /* ??? This gives worse code, and appears to be unnecessary, since no
1217 pass after flow uses REG_LIBCALL/REG_RETVAL notes. Local-alloc does
1218 use REG_RETVAL notes for noconflict blocks, but other code here
1219 makes sure that those insns don't disappear. */
1220 || find_reg_note (insn, REG_RETVAL, NULL_RTX)
1222 /* Make sure that DEST is not used after SUCC but before I3. */
1223 || (succ && ! all_adjacent
1224 && reg_used_between_p (dest, succ, i3))
1225 /* Make sure that the value that is to be substituted for the register
1226 does not use any registers whose values alter in between. However,
1227 If the insns are adjacent, a use can't cross a set even though we
1228 think it might (this can happen for a sequence of insns each setting
1229 the same destination; last_set of that register might point to
1230 a NOTE). If INSN has a REG_EQUIV note, the register is always
1231 equivalent to the memory so the substitution is valid even if there
1232 are intervening stores. Also, don't move a volatile asm or
1233 UNSPEC_VOLATILE across any other insns. */
1236 || ! find_reg_note (insn, REG_EQUIV, src))
1237 && use_crosses_set_p (src, INSN_CUID (insn)))
1238 || (GET_CODE (src) == ASM_OPERANDS && MEM_VOLATILE_P (src))
1239 || GET_CODE (src) == UNSPEC_VOLATILE))
1240 /* If there is a REG_NO_CONFLICT note for DEST in I3 or SUCC, we get
1241 better register allocation by not doing the combine. */
1242 || find_reg_note (i3, REG_NO_CONFLICT, dest)
1243 || (succ && find_reg_note (succ, REG_NO_CONFLICT, dest))
1244 /* Don't combine across a CALL_INSN, because that would possibly
1245 change whether the life span of some REGs crosses calls or not,
1246 and it is a pain to update that information.
1247 Exception: if source is a constant, moving it later can't hurt.
1248 Accept that special case, because it helps -fforce-addr a lot. */
1249 || (INSN_CUID (insn) < last_call_cuid && ! CONSTANT_P (src)))
1252 /* DEST must either be a REG or CC0. */
1255 /* If register alignment is being enforced for multi-word items in all
1256 cases except for parameters, it is possible to have a register copy
1257 insn referencing a hard register that is not allowed to contain the
1258 mode being copied and which would not be valid as an operand of most
1259 insns. Eliminate this problem by not combining with such an insn.
1261 Also, on some machines we don't want to extend the life of a hard
1265 && ((REGNO (dest) < FIRST_PSEUDO_REGISTER
1266 && ! HARD_REGNO_MODE_OK (REGNO (dest), GET_MODE (dest)))
1267 /* Don't extend the life of a hard register unless it is
1268 user variable (if we have few registers) or it can't
1269 fit into the desired register (meaning something special
1271 Also avoid substituting a return register into I3, because
1272 reload can't handle a conflict with constraints of other
1274 || (REGNO (src) < FIRST_PSEUDO_REGISTER
1275 && ! HARD_REGNO_MODE_OK (REGNO (src), GET_MODE (src)))))
1278 else if (GET_CODE (dest) != CC0)
1282 if (GET_CODE (PATTERN (i3)) == PARALLEL)
1283 for (i = XVECLEN (PATTERN (i3), 0) - 1; i >= 0; i--)
1284 if (GET_CODE (XVECEXP (PATTERN (i3), 0, i)) == CLOBBER)
1286 /* Don't substitute for a register intended as a clobberable
1288 rtx reg = XEXP (XVECEXP (PATTERN (i3), 0, i), 0);
1289 if (rtx_equal_p (reg, dest))
1292 /* If the clobber represents an earlyclobber operand, we must not
1293 substitute an expression containing the clobbered register.
1294 As we do not analyze the constraint strings here, we have to
1295 make the conservative assumption. However, if the register is
1296 a fixed hard reg, the clobber cannot represent any operand;
1297 we leave it up to the machine description to either accept or
1298 reject use-and-clobber patterns. */
1300 || REGNO (reg) >= FIRST_PSEUDO_REGISTER
1301 || !fixed_regs[REGNO (reg)])
1302 if (reg_overlap_mentioned_p (reg, src))
1306 /* If INSN contains anything volatile, or is an `asm' (whether volatile
1307 or not), reject, unless nothing volatile comes between it and I3 */
1309 if (GET_CODE (src) == ASM_OPERANDS || volatile_refs_p (src))
1311 /* Make sure succ doesn't contain a volatile reference. */
1312 if (succ != 0 && volatile_refs_p (PATTERN (succ)))
1315 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1316 if (INSN_P (p) && p != succ && volatile_refs_p (PATTERN (p)))
1320 /* If INSN is an asm, and DEST is a hard register, reject, since it has
1321 to be an explicit register variable, and was chosen for a reason. */
1323 if (GET_CODE (src) == ASM_OPERANDS
1324 && REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER)
1327 /* If there are any volatile insns between INSN and I3, reject, because
1328 they might affect machine state. */
1330 for (p = NEXT_INSN (insn); p != i3; p = NEXT_INSN (p))
1331 if (INSN_P (p) && p != succ && volatile_insn_p (PATTERN (p)))
1334 /* If INSN contains an autoincrement or autodecrement, make sure that
1335 register is not used between there and I3, and not already used in
1336 I3 either. Neither must it be used in PRED or SUCC, if they exist.
1337 Also insist that I3 not be a jump; if it were one
1338 and the incremented register were spilled, we would lose. */
1341 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
1342 if (REG_NOTE_KIND (link) == REG_INC
1344 || reg_used_between_p (XEXP (link, 0), insn, i3)
1345 || (pred != NULL_RTX
1346 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (pred)))
1347 || (succ != NULL_RTX
1348 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (succ)))
1349 || reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i3))))
1354 /* Don't combine an insn that follows a CC0-setting insn.
1355 An insn that uses CC0 must not be separated from the one that sets it.
1356 We do, however, allow I2 to follow a CC0-setting insn if that insn
1357 is passed as I1; in that case it will be deleted also.
1358 We also allow combining in this case if all the insns are adjacent
1359 because that would leave the two CC0 insns adjacent as well.
1360 It would be more logical to test whether CC0 occurs inside I1 or I2,
1361 but that would be much slower, and this ought to be equivalent. */
1363 p = prev_nonnote_insn (insn);
1364 if (p && p != pred && NONJUMP_INSN_P (p) && sets_cc0_p (PATTERN (p))
1369 /* If we get here, we have passed all the tests and the combination is
1378 /* LOC is the location within I3 that contains its pattern or the component
1379 of a PARALLEL of the pattern. We validate that it is valid for combining.
1381 One problem is if I3 modifies its output, as opposed to replacing it
1382 entirely, we can't allow the output to contain I2DEST or I1DEST as doing
1383 so would produce an insn that is not equivalent to the original insns.
1387 (set (reg:DI 101) (reg:DI 100))
1388 (set (subreg:SI (reg:DI 101) 0) <foo>)
1390 This is NOT equivalent to:
1392 (parallel [(set (subreg:SI (reg:DI 100) 0) <foo>)
1393 (set (reg:DI 101) (reg:DI 100))])
1395 Not only does this modify 100 (in which case it might still be valid
1396 if 100 were dead in I2), it sets 101 to the ORIGINAL value of 100.
1398 We can also run into a problem if I2 sets a register that I1
1399 uses and I1 gets directly substituted into I3 (not via I2). In that
1400 case, we would be getting the wrong value of I2DEST into I3, so we
1401 must reject the combination. This case occurs when I2 and I1 both
1402 feed into I3, rather than when I1 feeds into I2, which feeds into I3.
1403 If I1_NOT_IN_SRC is nonzero, it means that finding I1 in the source
1404 of a SET must prevent combination from occurring.
1406 Before doing the above check, we first try to expand a field assignment
1407 into a set of logical operations.
1409 If PI3_DEST_KILLED is nonzero, it is a pointer to a location in which
1410 we place a register that is both set and used within I3. If more than one
1411 such register is detected, we fail.
1413 Return 1 if the combination is valid, zero otherwise. */
1416 combinable_i3pat (rtx i3, rtx *loc, rtx i2dest, rtx i1dest,
1417 int i1_not_in_src, rtx *pi3dest_killed)
1421 if (GET_CODE (x) == SET)
1424 rtx dest = SET_DEST (set);
1425 rtx src = SET_SRC (set);
1426 rtx inner_dest = dest;
1429 while (GET_CODE (inner_dest) == STRICT_LOW_PART
1430 || GET_CODE (inner_dest) == SUBREG
1431 || GET_CODE (inner_dest) == ZERO_EXTRACT)
1432 inner_dest = XEXP (inner_dest, 0);
1434 /* Check for the case where I3 modifies its output, as discussed
1435 above. We don't want to prevent pseudos from being combined
1436 into the address of a MEM, so only prevent the combination if
1437 i1 or i2 set the same MEM. */
1438 if ((inner_dest != dest &&
1439 (!MEM_P (inner_dest)
1440 || rtx_equal_p (i2dest, inner_dest)
1441 || (i1dest && rtx_equal_p (i1dest, inner_dest)))
1442 && (reg_overlap_mentioned_p (i2dest, inner_dest)
1443 || (i1dest && reg_overlap_mentioned_p (i1dest, inner_dest))))
1445 /* This is the same test done in can_combine_p except we can't test
1446 all_adjacent; we don't have to, since this instruction will stay
1447 in place, thus we are not considering increasing the lifetime of
1450 Also, if this insn sets a function argument, combining it with
1451 something that might need a spill could clobber a previous
1452 function argument; the all_adjacent test in can_combine_p also
1453 checks this; here, we do a more specific test for this case. */
1455 || (REG_P (inner_dest)
1456 && REGNO (inner_dest) < FIRST_PSEUDO_REGISTER
1457 && (! HARD_REGNO_MODE_OK (REGNO (inner_dest),
1458 GET_MODE (inner_dest))))
1459 || (i1_not_in_src && reg_overlap_mentioned_p (i1dest, src)))
1462 /* If DEST is used in I3, it is being killed in this insn, so
1463 record that for later. We have to consider paradoxical
1464 subregs here, since they kill the whole register, but we
1465 ignore partial subregs, STRICT_LOW_PART, etc.
1466 Never add REG_DEAD notes for the FRAME_POINTER_REGNUM or the
1467 STACK_POINTER_REGNUM, since these are always considered to be
1468 live. Similarly for ARG_POINTER_REGNUM if it is fixed. */
1470 if (GET_CODE (subdest) == SUBREG
1471 && (GET_MODE_SIZE (GET_MODE (subdest))
1472 >= GET_MODE_SIZE (GET_MODE (SUBREG_REG (subdest)))))
1473 subdest = SUBREG_REG (subdest);
1476 && reg_referenced_p (subdest, PATTERN (i3))
1477 && REGNO (subdest) != FRAME_POINTER_REGNUM
1478 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
1479 && REGNO (subdest) != HARD_FRAME_POINTER_REGNUM
1481 #if ARG_POINTER_REGNUM != FRAME_POINTER_REGNUM
1482 && (REGNO (subdest) != ARG_POINTER_REGNUM
1483 || ! fixed_regs [REGNO (subdest)])
1485 && REGNO (subdest) != STACK_POINTER_REGNUM)
1487 if (*pi3dest_killed)
1490 *pi3dest_killed = subdest;
1494 else if (GET_CODE (x) == PARALLEL)
1498 for (i = 0; i < XVECLEN (x, 0); i++)
1499 if (! combinable_i3pat (i3, &XVECEXP (x, 0, i), i2dest, i1dest,
1500 i1_not_in_src, pi3dest_killed))
1507 /* Return 1 if X is an arithmetic expression that contains a multiplication
1508 and division. We don't count multiplications by powers of two here. */
1511 contains_muldiv (rtx x)
1513 switch (GET_CODE (x))
1515 case MOD: case DIV: case UMOD: case UDIV:
1519 return ! (GET_CODE (XEXP (x, 1)) == CONST_INT
1520 && exact_log2 (INTVAL (XEXP (x, 1))) >= 0);
1523 return contains_muldiv (XEXP (x, 0))
1524 || contains_muldiv (XEXP (x, 1));
1527 return contains_muldiv (XEXP (x, 0));
1533 /* Determine whether INSN can be used in a combination. Return nonzero if
1534 not. This is used in try_combine to detect early some cases where we
1535 can't perform combinations. */
1538 cant_combine_insn_p (rtx insn)
1543 /* If this isn't really an insn, we can't do anything.
1544 This can occur when flow deletes an insn that it has merged into an
1545 auto-increment address. */
1546 if (! INSN_P (insn))
1549 /* Never combine loads and stores involving hard regs that are likely
1550 to be spilled. The register allocator can usually handle such
1551 reg-reg moves by tying. If we allow the combiner to make
1552 substitutions of likely-spilled regs, reload might die.
1553 As an exception, we allow combinations involving fixed regs; these are
1554 not available to the register allocator so there's no risk involved. */
1556 set = single_set (insn);
1559 src = SET_SRC (set);
1560 dest = SET_DEST (set);
1561 if (GET_CODE (src) == SUBREG)
1562 src = SUBREG_REG (src);
1563 if (GET_CODE (dest) == SUBREG)
1564 dest = SUBREG_REG (dest);
1565 if (REG_P (src) && REG_P (dest)
1566 && ((REGNO (src) < FIRST_PSEUDO_REGISTER
1567 && ! fixed_regs[REGNO (src)]
1568 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (src))))
1569 || (REGNO (dest) < FIRST_PSEUDO_REGISTER
1570 && ! fixed_regs[REGNO (dest)]
1571 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (REGNO (dest))))))
1577 struct likely_spilled_retval_info
1579 unsigned regno, nregs;
1583 /* Called via note_stores by likely_spilled_retval_p. Remove from info->mask
1584 hard registers that are known to be written to / clobbered in full. */
1586 likely_spilled_retval_1 (rtx x, rtx set, void *data)
1588 struct likely_spilled_retval_info *info = data;
1589 unsigned regno, nregs;
1592 if (!REG_P (XEXP (set, 0)))
1595 if (regno >= info->regno + info->nregs)
1597 nregs = hard_regno_nregs[regno][GET_MODE (x)];
1598 if (regno + nregs <= info->regno)
1600 new_mask = (2U << (nregs - 1)) - 1;
1601 if (regno < info->regno)
1602 new_mask >>= info->regno - regno;
1604 new_mask <<= regno - info->regno;
1605 info->mask &= new_mask;
1608 /* Return nonzero iff part of the return value is live during INSN, and
1609 it is likely spilled. This can happen when more than one insn is needed
1610 to copy the return value, e.g. when we consider to combine into the
1611 second copy insn for a complex value. */
1614 likely_spilled_retval_p (rtx insn)
1616 rtx use = BB_END (this_basic_block);
1618 unsigned regno, nregs;
1619 /* We assume here that no machine mode needs more than
1620 32 hard registers when the value overlaps with a register
1621 for which FUNCTION_VALUE_REGNO_P is true. */
1623 struct likely_spilled_retval_info info;
1625 if (!NONJUMP_INSN_P (use) || GET_CODE (PATTERN (use)) != USE || insn == use)
1627 reg = XEXP (PATTERN (use), 0);
1628 if (!REG_P (reg) || !FUNCTION_VALUE_REGNO_P (REGNO (reg)))
1630 regno = REGNO (reg);
1631 nregs = hard_regno_nregs[regno][GET_MODE (reg)];
1634 mask = (2U << (nregs - 1)) - 1;
1636 /* Disregard parts of the return value that are set later. */
1640 for (p = PREV_INSN (use); info.mask && p != insn; p = PREV_INSN (p))
1641 note_stores (PATTERN (insn), likely_spilled_retval_1, &info);
1644 /* Check if any of the (probably) live return value registers is
1649 if ((mask & 1 << nregs)
1650 && CLASS_LIKELY_SPILLED_P (REGNO_REG_CLASS (regno + nregs)))
1656 /* Adjust INSN after we made a change to its destination.
1658 Changing the destination can invalidate notes that say something about
1659 the results of the insn and a LOG_LINK pointing to the insn. */
1662 adjust_for_new_dest (rtx insn)
1666 /* For notes, be conservative and simply remove them. */
1667 loc = ®_NOTES (insn);
1670 enum reg_note kind = REG_NOTE_KIND (*loc);
1671 if (kind == REG_EQUAL || kind == REG_EQUIV)
1672 *loc = XEXP (*loc, 1);
1674 loc = &XEXP (*loc, 1);
1677 /* The new insn will have a destination that was previously the destination
1678 of an insn just above it. Call distribute_links to make a LOG_LINK from
1679 the next use of that destination. */
1680 distribute_links (gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX));
1683 /* Return TRUE if combine can reuse reg X in mode MODE.
1684 ADDED_SETS is nonzero if the original set is still required. */
1686 can_change_dest_mode (rtx x, int added_sets, enum machine_mode mode)
1694 /* Allow hard registers if the new mode is legal, and occupies no more
1695 registers than the old mode. */
1696 if (regno < FIRST_PSEUDO_REGISTER)
1697 return (HARD_REGNO_MODE_OK (regno, mode)
1698 && (hard_regno_nregs[regno][GET_MODE (x)]
1699 >= hard_regno_nregs[regno][mode]));
1701 /* Or a pseudo that is only used once. */
1702 return (REG_N_SETS (regno) == 1 && !added_sets
1703 && !REG_USERVAR_P (x));
1706 /* Try to combine the insns I1 and I2 into I3.
1707 Here I1 and I2 appear earlier than I3.
1708 I1 can be zero; then we combine just I2 into I3.
1710 If we are combining three insns and the resulting insn is not recognized,
1711 try splitting it into two insns. If that happens, I2 and I3 are retained
1712 and I1 is pseudo-deleted by turning it into a NOTE. Otherwise, I1 and I2
1715 Return 0 if the combination does not work. Then nothing is changed.
1716 If we did the combination, return the insn at which combine should
1719 Set NEW_DIRECT_JUMP_P to a nonzero value if try_combine creates a
1720 new direct jump instruction. */
1723 try_combine (rtx i3, rtx i2, rtx i1, int *new_direct_jump_p)
1725 /* New patterns for I3 and I2, respectively. */
1726 rtx newpat, newi2pat = 0;
1727 rtvec newpat_vec_with_clobbers = 0;
1728 int substed_i2 = 0, substed_i1 = 0;
1729 /* Indicates need to preserve SET in I1 or I2 in I3 if it is not dead. */
1730 int added_sets_1, added_sets_2;
1731 /* Total number of SETs to put into I3. */
1733 /* Nonzero if I2's body now appears in I3. */
1735 /* INSN_CODEs for new I3, new I2, and user of condition code. */
1736 int insn_code_number, i2_code_number = 0, other_code_number = 0;
1737 /* Contains I3 if the destination of I3 is used in its source, which means
1738 that the old life of I3 is being killed. If that usage is placed into
1739 I2 and not in I3, a REG_DEAD note must be made. */
1740 rtx i3dest_killed = 0;
1741 /* SET_DEST and SET_SRC of I2 and I1. */
1742 rtx i2dest, i2src, i1dest = 0, i1src = 0;
1743 /* PATTERN (I2), or a copy of it in certain cases. */
1745 /* Indicates if I2DEST or I1DEST is in I2SRC or I1_SRC. */
1746 int i2dest_in_i2src = 0, i1dest_in_i1src = 0, i2dest_in_i1src = 0;
1747 int i2dest_killed = 0, i1dest_killed = 0;
1748 int i1_feeds_i3 = 0;
1749 /* Notes that must be added to REG_NOTES in I3 and I2. */
1750 rtx new_i3_notes, new_i2_notes;
1751 /* Notes that we substituted I3 into I2 instead of the normal case. */
1752 int i3_subst_into_i2 = 0;
1753 /* Notes that I1, I2 or I3 is a MULT operation. */
1762 /* Exit early if one of the insns involved can't be used for
1764 if (cant_combine_insn_p (i3)
1765 || cant_combine_insn_p (i2)
1766 || (i1 && cant_combine_insn_p (i1))
1767 || likely_spilled_retval_p (i3)
1768 /* We also can't do anything if I3 has a
1769 REG_LIBCALL note since we don't want to disrupt the contiguity of a
1772 /* ??? This gives worse code, and appears to be unnecessary, since no
1773 pass after flow uses REG_LIBCALL/REG_RETVAL notes. */
1774 || find_reg_note (i3, REG_LIBCALL, NULL_RTX)
1780 undobuf.other_insn = 0;
1782 /* Reset the hard register usage information. */
1783 CLEAR_HARD_REG_SET (newpat_used_regs);
1785 /* If I1 and I2 both feed I3, they can be in any order. To simplify the
1786 code below, set I1 to be the earlier of the two insns. */
1787 if (i1 && INSN_CUID (i1) > INSN_CUID (i2))
1788 temp = i1, i1 = i2, i2 = temp;
1790 added_links_insn = 0;
1792 /* First check for one important special-case that the code below will
1793 not handle. Namely, the case where I1 is zero, I2 is a PARALLEL
1794 and I3 is a SET whose SET_SRC is a SET_DEST in I2. In that case,
1795 we may be able to replace that destination with the destination of I3.
1796 This occurs in the common code where we compute both a quotient and
1797 remainder into a structure, in which case we want to do the computation
1798 directly into the structure to avoid register-register copies.
1800 Note that this case handles both multiple sets in I2 and also
1801 cases where I2 has a number of CLOBBER or PARALLELs.
1803 We make very conservative checks below and only try to handle the
1804 most common cases of this. For example, we only handle the case
1805 where I2 and I3 are adjacent to avoid making difficult register
1808 if (i1 == 0 && NONJUMP_INSN_P (i3) && GET_CODE (PATTERN (i3)) == SET
1809 && REG_P (SET_SRC (PATTERN (i3)))
1810 && REGNO (SET_SRC (PATTERN (i3))) >= FIRST_PSEUDO_REGISTER
1811 && find_reg_note (i3, REG_DEAD, SET_SRC (PATTERN (i3)))
1812 && GET_CODE (PATTERN (i2)) == PARALLEL
1813 && ! side_effects_p (SET_DEST (PATTERN (i3)))
1814 /* If the dest of I3 is a ZERO_EXTRACT or STRICT_LOW_PART, the code
1815 below would need to check what is inside (and reg_overlap_mentioned_p
1816 doesn't support those codes anyway). Don't allow those destinations;
1817 the resulting insn isn't likely to be recognized anyway. */
1818 && GET_CODE (SET_DEST (PATTERN (i3))) != ZERO_EXTRACT
1819 && GET_CODE (SET_DEST (PATTERN (i3))) != STRICT_LOW_PART
1820 && ! reg_overlap_mentioned_p (SET_SRC (PATTERN (i3)),
1821 SET_DEST (PATTERN (i3)))
1822 && next_real_insn (i2) == i3)
1824 rtx p2 = PATTERN (i2);
1826 /* Make sure that the destination of I3,
1827 which we are going to substitute into one output of I2,
1828 is not used within another output of I2. We must avoid making this:
1829 (parallel [(set (mem (reg 69)) ...)
1830 (set (reg 69) ...)])
1831 which is not well-defined as to order of actions.
1832 (Besides, reload can't handle output reloads for this.)
1834 The problem can also happen if the dest of I3 is a memory ref,
1835 if another dest in I2 is an indirect memory ref. */
1836 for (i = 0; i < XVECLEN (p2, 0); i++)
1837 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1838 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1839 && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)),
1840 SET_DEST (XVECEXP (p2, 0, i))))
1843 if (i == XVECLEN (p2, 0))
1844 for (i = 0; i < XVECLEN (p2, 0); i++)
1845 if ((GET_CODE (XVECEXP (p2, 0, i)) == SET
1846 || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER)
1847 && SET_DEST (XVECEXP (p2, 0, i)) == SET_SRC (PATTERN (i3)))
1852 subst_low_cuid = INSN_CUID (i2);
1854 added_sets_2 = added_sets_1 = 0;
1855 i2dest = SET_SRC (PATTERN (i3));
1856 i2dest_killed = dead_or_set_p (i2, i2dest);
1858 /* Replace the dest in I2 with our dest and make the resulting
1859 insn the new pattern for I3. Then skip to where we
1860 validate the pattern. Everything was set up above. */
1861 SUBST (SET_DEST (XVECEXP (p2, 0, i)),
1862 SET_DEST (PATTERN (i3)));
1865 i3_subst_into_i2 = 1;
1866 goto validate_replacement;
1870 /* If I2 is setting a double-word pseudo to a constant and I3 is setting
1871 one of those words to another constant, merge them by making a new
1874 && (temp = single_set (i2)) != 0
1875 && (GET_CODE (SET_SRC (temp)) == CONST_INT
1876 || GET_CODE (SET_SRC (temp)) == CONST_DOUBLE)
1877 && REG_P (SET_DEST (temp))
1878 && GET_MODE_CLASS (GET_MODE (SET_DEST (temp))) == MODE_INT
1879 && GET_MODE_SIZE (GET_MODE (SET_DEST (temp))) == 2 * UNITS_PER_WORD
1880 && GET_CODE (PATTERN (i3)) == SET
1881 && GET_CODE (SET_DEST (PATTERN (i3))) == SUBREG
1882 && SUBREG_REG (SET_DEST (PATTERN (i3))) == SET_DEST (temp)
1883 && GET_MODE_CLASS (GET_MODE (SET_DEST (PATTERN (i3)))) == MODE_INT
1884 && GET_MODE_SIZE (GET_MODE (SET_DEST (PATTERN (i3)))) == UNITS_PER_WORD
1885 && GET_CODE (SET_SRC (PATTERN (i3))) == CONST_INT)
1887 HOST_WIDE_INT lo, hi;
1889 if (GET_CODE (SET_SRC (temp)) == CONST_INT)
1890 lo = INTVAL (SET_SRC (temp)), hi = lo < 0 ? -1 : 0;
1893 lo = CONST_DOUBLE_LOW (SET_SRC (temp));
1894 hi = CONST_DOUBLE_HIGH (SET_SRC (temp));
1897 if (subreg_lowpart_p (SET_DEST (PATTERN (i3))))
1899 /* We don't handle the case of the target word being wider
1900 than a host wide int. */
1901 gcc_assert (HOST_BITS_PER_WIDE_INT >= BITS_PER_WORD);
1903 lo &= ~(UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1);
1904 lo |= (INTVAL (SET_SRC (PATTERN (i3)))
1905 & (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1907 else if (HOST_BITS_PER_WIDE_INT == BITS_PER_WORD)
1908 hi = INTVAL (SET_SRC (PATTERN (i3)));
1909 else if (HOST_BITS_PER_WIDE_INT >= 2 * BITS_PER_WORD)
1911 int sign = -(int) ((unsigned HOST_WIDE_INT) lo
1912 >> (HOST_BITS_PER_WIDE_INT - 1));
1914 lo &= ~ (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1915 (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD (1) - 1));
1916 lo |= (UWIDE_SHIFT_LEFT_BY_BITS_PER_WORD
1917 (INTVAL (SET_SRC (PATTERN (i3)))));
1919 hi = lo < 0 ? -1 : 0;
1922 /* We don't handle the case of the higher word not fitting
1923 entirely in either hi or lo. */
1928 subst_low_cuid = INSN_CUID (i2);
1929 added_sets_2 = added_sets_1 = 0;
1930 i2dest = SET_DEST (temp);
1931 i2dest_killed = dead_or_set_p (i2, i2dest);
1933 SUBST (SET_SRC (temp),
1934 immed_double_const (lo, hi, GET_MODE (SET_DEST (temp))));
1936 newpat = PATTERN (i2);
1937 goto validate_replacement;
1941 /* If we have no I1 and I2 looks like:
1942 (parallel [(set (reg:CC X) (compare:CC OP (const_int 0)))
1944 make up a dummy I1 that is
1947 (set (reg:CC X) (compare:CC Y (const_int 0)))
1949 (We can ignore any trailing CLOBBERs.)
1951 This undoes a previous combination and allows us to match a branch-and-
1954 if (i1 == 0 && GET_CODE (PATTERN (i2)) == PARALLEL
1955 && XVECLEN (PATTERN (i2), 0) >= 2
1956 && GET_CODE (XVECEXP (PATTERN (i2), 0, 0)) == SET
1957 && (GET_MODE_CLASS (GET_MODE (SET_DEST (XVECEXP (PATTERN (i2), 0, 0))))
1959 && GET_CODE (SET_SRC (XVECEXP (PATTERN (i2), 0, 0))) == COMPARE
1960 && XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 1) == const0_rtx
1961 && GET_CODE (XVECEXP (PATTERN (i2), 0, 1)) == SET
1962 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, 1)))
1963 && rtx_equal_p (XEXP (SET_SRC (XVECEXP (PATTERN (i2), 0, 0)), 0),
1964 SET_SRC (XVECEXP (PATTERN (i2), 0, 1))))
1966 for (i = XVECLEN (PATTERN (i2), 0) - 1; i >= 2; i--)
1967 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != CLOBBER)
1972 /* We make I1 with the same INSN_UID as I2. This gives it
1973 the same INSN_CUID for value tracking. Our fake I1 will
1974 never appear in the insn stream so giving it the same INSN_UID
1975 as I2 will not cause a problem. */
1977 i1 = gen_rtx_INSN (VOIDmode, INSN_UID (i2), NULL_RTX, i2,
1978 BLOCK_FOR_INSN (i2), INSN_LOCATOR (i2),
1979 XVECEXP (PATTERN (i2), 0, 1), -1, NULL_RTX,
1982 SUBST (PATTERN (i2), XVECEXP (PATTERN (i2), 0, 0));
1983 SUBST (XEXP (SET_SRC (PATTERN (i2)), 0),
1984 SET_DEST (PATTERN (i1)));
1989 /* Verify that I2 and I1 are valid for combining. */
1990 if (! can_combine_p (i2, i3, i1, NULL_RTX, &i2dest, &i2src)
1991 || (i1 && ! can_combine_p (i1, i3, NULL_RTX, i2, &i1dest, &i1src)))
1997 /* Record whether I2DEST is used in I2SRC and similarly for the other
1998 cases. Knowing this will help in register status updating below. */
1999 i2dest_in_i2src = reg_overlap_mentioned_p (i2dest, i2src);
2000 i1dest_in_i1src = i1 && reg_overlap_mentioned_p (i1dest, i1src);
2001 i2dest_in_i1src = i1 && reg_overlap_mentioned_p (i2dest, i1src);
2002 i2dest_killed = dead_or_set_p (i2, i2dest);
2003 i1dest_killed = i1 && dead_or_set_p (i1, i1dest);
2005 /* See if I1 directly feeds into I3. It does if I1DEST is not used
2007 i1_feeds_i3 = i1 && ! reg_overlap_mentioned_p (i1dest, i2src);
2009 /* Ensure that I3's pattern can be the destination of combines. */
2010 if (! combinable_i3pat (i3, &PATTERN (i3), i2dest, i1dest,
2011 i1 && i2dest_in_i1src && i1_feeds_i3,
2018 /* See if any of the insns is a MULT operation. Unless one is, we will
2019 reject a combination that is, since it must be slower. Be conservative
2021 if (GET_CODE (i2src) == MULT
2022 || (i1 != 0 && GET_CODE (i1src) == MULT)
2023 || (GET_CODE (PATTERN (i3)) == SET
2024 && GET_CODE (SET_SRC (PATTERN (i3))) == MULT))
2027 /* If I3 has an inc, then give up if I1 or I2 uses the reg that is inc'd.
2028 We used to do this EXCEPT in one case: I3 has a post-inc in an
2029 output operand. However, that exception can give rise to insns like
2031 which is a famous insn on the PDP-11 where the value of r3 used as the
2032 source was model-dependent. Avoid this sort of thing. */
2035 if (!(GET_CODE (PATTERN (i3)) == SET
2036 && REG_P (SET_SRC (PATTERN (i3)))
2037 && MEM_P (SET_DEST (PATTERN (i3)))
2038 && (GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_INC
2039 || GET_CODE (XEXP (SET_DEST (PATTERN (i3)), 0)) == POST_DEC)))
2040 /* It's not the exception. */
2043 for (link = REG_NOTES (i3); link; link = XEXP (link, 1))
2044 if (REG_NOTE_KIND (link) == REG_INC
2045 && (reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i2))
2047 && reg_overlap_mentioned_p (XEXP (link, 0), PATTERN (i1)))))
2054 /* See if the SETs in I1 or I2 need to be kept around in the merged
2055 instruction: whenever the value set there is still needed past I3.
2056 For the SETs in I2, this is easy: we see if I2DEST dies or is set in I3.
2058 For the SET in I1, we have two cases: If I1 and I2 independently
2059 feed into I3, the set in I1 needs to be kept around if I1DEST dies
2060 or is set in I3. Otherwise (if I1 feeds I2 which feeds I3), the set
2061 in I1 needs to be kept around unless I1DEST dies or is set in either
2062 I2 or I3. We can distinguish these cases by seeing if I2SRC mentions
2063 I1DEST. If so, we know I1 feeds into I2. */
2065 added_sets_2 = ! dead_or_set_p (i3, i2dest);
2068 = i1 && ! (i1_feeds_i3 ? dead_or_set_p (i3, i1dest)
2069 : (dead_or_set_p (i3, i1dest) || dead_or_set_p (i2, i1dest)));
2071 /* If the set in I2 needs to be kept around, we must make a copy of
2072 PATTERN (I2), so that when we substitute I1SRC for I1DEST in
2073 PATTERN (I2), we are only substituting for the original I1DEST, not into
2074 an already-substituted copy. This also prevents making self-referential
2075 rtx. If I2 is a PARALLEL, we just need the piece that assigns I2SRC to
2078 i2pat = (GET_CODE (PATTERN (i2)) == PARALLEL
2079 ? gen_rtx_SET (VOIDmode, i2dest, i2src)
2083 i2pat = copy_rtx (i2pat);
2087 /* Substitute in the latest insn for the regs set by the earlier ones. */
2089 maxreg = max_reg_num ();
2094 /* Many machines that don't use CC0 have insns that can both perform an
2095 arithmetic operation and set the condition code. These operations will
2096 be represented as a PARALLEL with the first element of the vector
2097 being a COMPARE of an arithmetic operation with the constant zero.
2098 The second element of the vector will set some pseudo to the result
2099 of the same arithmetic operation. If we simplify the COMPARE, we won't
2100 match such a pattern and so will generate an extra insn. Here we test
2101 for this case, where both the comparison and the operation result are
2102 needed, and make the PARALLEL by just replacing I2DEST in I3SRC with
2103 I2SRC. Later we will make the PARALLEL that contains I2. */
2105 if (i1 == 0 && added_sets_2 && GET_CODE (PATTERN (i3)) == SET
2106 && GET_CODE (SET_SRC (PATTERN (i3))) == COMPARE
2107 && XEXP (SET_SRC (PATTERN (i3)), 1) == const0_rtx
2108 && rtx_equal_p (XEXP (SET_SRC (PATTERN (i3)), 0), i2dest))
2110 #ifdef SELECT_CC_MODE
2112 enum machine_mode compare_mode;
2115 newpat = PATTERN (i3);
2116 SUBST (XEXP (SET_SRC (newpat), 0), i2src);
2120 #ifdef SELECT_CC_MODE
2121 /* See if a COMPARE with the operand we substituted in should be done
2122 with the mode that is currently being used. If not, do the same
2123 processing we do in `subst' for a SET; namely, if the destination
2124 is used only once, try to replace it with a register of the proper
2125 mode and also replace the COMPARE. */
2126 if (undobuf.other_insn == 0
2127 && (cc_use = find_single_use (SET_DEST (newpat), i3,
2128 &undobuf.other_insn))
2129 && ((compare_mode = SELECT_CC_MODE (GET_CODE (*cc_use),
2131 != GET_MODE (SET_DEST (newpat))))
2133 if (can_change_dest_mode(SET_DEST (newpat), added_sets_2,
2136 unsigned int regno = REGNO (SET_DEST (newpat));
2137 rtx new_dest = gen_rtx_REG (compare_mode, regno);
2139 if (regno >= FIRST_PSEUDO_REGISTER)
2140 SUBST (regno_reg_rtx[regno], new_dest);
2142 SUBST (SET_DEST (newpat), new_dest);
2143 SUBST (XEXP (*cc_use, 0), new_dest);
2144 SUBST (SET_SRC (newpat),
2145 gen_rtx_COMPARE (compare_mode, i2src, const0_rtx));
2148 undobuf.other_insn = 0;
2155 /* It is possible that the source of I2 or I1 may be performing
2156 an unneeded operation, such as a ZERO_EXTEND of something
2157 that is known to have the high part zero. Handle that case
2158 by letting subst look at the innermost one of them.
2160 Another way to do this would be to have a function that tries
2161 to simplify a single insn instead of merging two or more
2162 insns. We don't do this because of the potential of infinite
2163 loops and because of the potential extra memory required.
2164 However, doing it the way we are is a bit of a kludge and
2165 doesn't catch all cases.
2167 But only do this if -fexpensive-optimizations since it slows
2168 things down and doesn't usually win.
2170 This is not done in the COMPARE case above because the
2171 unmodified I2PAT is used in the PARALLEL and so a pattern
2172 with a modified I2SRC would not match. */
2174 if (flag_expensive_optimizations)
2176 /* Pass pc_rtx so no substitutions are done, just
2180 subst_low_cuid = INSN_CUID (i1);
2181 i1src = subst (i1src, pc_rtx, pc_rtx, 0, 0);
2185 subst_low_cuid = INSN_CUID (i2);
2186 i2src = subst (i2src, pc_rtx, pc_rtx, 0, 0);
2190 n_occurrences = 0; /* `subst' counts here */
2192 /* If I1 feeds into I2 (not into I3) and I1DEST is in I1SRC, we
2193 need to make a unique copy of I2SRC each time we substitute it
2194 to avoid self-referential rtl. */
2196 subst_low_cuid = INSN_CUID (i2);
2197 newpat = subst (PATTERN (i3), i2dest, i2src, 0,
2198 ! i1_feeds_i3 && i1dest_in_i1src);
2201 /* Record whether i2's body now appears within i3's body. */
2202 i2_is_used = n_occurrences;
2205 /* If we already got a failure, don't try to do more. Otherwise,
2206 try to substitute in I1 if we have it. */
2208 if (i1 && GET_CODE (newpat) != CLOBBER)
2210 /* Before we can do this substitution, we must redo the test done
2211 above (see detailed comments there) that ensures that I1DEST
2212 isn't mentioned in any SETs in NEWPAT that are field assignments. */
2214 if (! combinable_i3pat (NULL_RTX, &newpat, i1dest, NULL_RTX,
2222 subst_low_cuid = INSN_CUID (i1);
2223 newpat = subst (newpat, i1dest, i1src, 0, 0);
2227 /* Fail if an autoincrement side-effect has been duplicated. Be careful
2228 to count all the ways that I2SRC and I1SRC can be used. */
2229 if ((FIND_REG_INC_NOTE (i2, NULL_RTX) != 0
2230 && i2_is_used + added_sets_2 > 1)
2231 || (i1 != 0 && FIND_REG_INC_NOTE (i1, NULL_RTX) != 0
2232 && (n_occurrences + added_sets_1 + (added_sets_2 && ! i1_feeds_i3)
2234 /* Fail if we tried to make a new register. */
2235 || max_reg_num () != maxreg
2236 /* Fail if we couldn't do something and have a CLOBBER. */
2237 || GET_CODE (newpat) == CLOBBER
2238 /* Fail if this new pattern is a MULT and we didn't have one before
2239 at the outer level. */
2240 || (GET_CODE (newpat) == SET && GET_CODE (SET_SRC (newpat)) == MULT
2247 /* If the actions of the earlier insns must be kept
2248 in addition to substituting them into the latest one,
2249 we must make a new PARALLEL for the latest insn
2250 to hold additional the SETs. */
2252 if (added_sets_1 || added_sets_2)
2256 if (GET_CODE (newpat) == PARALLEL)
2258 rtvec old = XVEC (newpat, 0);
2259 total_sets = XVECLEN (newpat, 0) + added_sets_1 + added_sets_2;
2260 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2261 memcpy (XVEC (newpat, 0)->elem, &old->elem[0],
2262 sizeof (old->elem[0]) * old->num_elem);
2267 total_sets = 1 + added_sets_1 + added_sets_2;
2268 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (total_sets));
2269 XVECEXP (newpat, 0, 0) = old;
2273 XVECEXP (newpat, 0, --total_sets)
2274 = (GET_CODE (PATTERN (i1)) == PARALLEL
2275 ? gen_rtx_SET (VOIDmode, i1dest, i1src) : PATTERN (i1));
2279 /* If there is no I1, use I2's body as is. We used to also not do
2280 the subst call below if I2 was substituted into I3,
2281 but that could lose a simplification. */
2283 XVECEXP (newpat, 0, --total_sets) = i2pat;
2285 /* See comment where i2pat is assigned. */
2286 XVECEXP (newpat, 0, --total_sets)
2287 = subst (i2pat, i1dest, i1src, 0, 0);
2291 /* We come here when we are replacing a destination in I2 with the
2292 destination of I3. */
2293 validate_replacement:
2295 /* Note which hard regs this insn has as inputs. */
2296 mark_used_regs_combine (newpat);
2298 /* If recog_for_combine fails, it strips existing clobbers. If we'll
2299 consider splitting this pattern, we might need these clobbers. */
2300 if (i1 && GET_CODE (newpat) == PARALLEL
2301 && GET_CODE (XVECEXP (newpat, 0, XVECLEN (newpat, 0) - 1)) == CLOBBER)
2303 int len = XVECLEN (newpat, 0);
2305 newpat_vec_with_clobbers = rtvec_alloc (len);
2306 for (i = 0; i < len; i++)
2307 RTVEC_ELT (newpat_vec_with_clobbers, i) = XVECEXP (newpat, 0, i);
2310 /* Is the result of combination a valid instruction? */
2311 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2313 /* If the result isn't valid, see if it is a PARALLEL of two SETs where
2314 the second SET's destination is a register that is unused and isn't
2315 marked as an instruction that might trap in an EH region. In that case,
2316 we just need the first SET. This can occur when simplifying a divmod
2317 insn. We *must* test for this case here because the code below that
2318 splits two independent SETs doesn't handle this case correctly when it
2319 updates the register status.
2321 It's pointless doing this if we originally had two sets, one from
2322 i3, and one from i2. Combining then splitting the parallel results
2323 in the original i2 again plus an invalid insn (which we delete).
2324 The net effect is only to move instructions around, which makes
2325 debug info less accurate.
2327 Also check the case where the first SET's destination is unused.
2328 That would not cause incorrect code, but does cause an unneeded
2331 if (insn_code_number < 0
2332 && !(added_sets_2 && i1 == 0)
2333 && GET_CODE (newpat) == PARALLEL
2334 && XVECLEN (newpat, 0) == 2
2335 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2336 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2337 && asm_noperands (newpat) < 0)
2339 rtx set0 = XVECEXP (newpat, 0, 0);
2340 rtx set1 = XVECEXP (newpat, 0, 1);
2343 if (((REG_P (SET_DEST (set1))
2344 && find_reg_note (i3, REG_UNUSED, SET_DEST (set1)))
2345 || (GET_CODE (SET_DEST (set1)) == SUBREG
2346 && find_reg_note (i3, REG_UNUSED, SUBREG_REG (SET_DEST (set1)))))
2347 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2348 || INTVAL (XEXP (note, 0)) <= 0)
2349 && ! side_effects_p (SET_SRC (set1)))
2352 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2355 else if (((REG_P (SET_DEST (set0))
2356 && find_reg_note (i3, REG_UNUSED, SET_DEST (set0)))
2357 || (GET_CODE (SET_DEST (set0)) == SUBREG
2358 && find_reg_note (i3, REG_UNUSED,
2359 SUBREG_REG (SET_DEST (set0)))))
2360 && (!(note = find_reg_note (i3, REG_EH_REGION, NULL_RTX))
2361 || INTVAL (XEXP (note, 0)) <= 0)
2362 && ! side_effects_p (SET_SRC (set0)))
2365 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2367 if (insn_code_number >= 0)
2369 /* If we will be able to accept this, we have made a
2370 change to the destination of I3. This requires us to
2371 do a few adjustments. */
2373 PATTERN (i3) = newpat;
2374 adjust_for_new_dest (i3);
2379 /* If we were combining three insns and the result is a simple SET
2380 with no ASM_OPERANDS that wasn't recognized, try to split it into two
2381 insns. There are two ways to do this. It can be split using a
2382 machine-specific method (like when you have an addition of a large
2383 constant) or by combine in the function find_split_point. */
2385 if (i1 && insn_code_number < 0 && GET_CODE (newpat) == SET
2386 && asm_noperands (newpat) < 0)
2388 rtx m_split, *split;
2389 rtx ni2dest = i2dest;
2391 /* See if the MD file can split NEWPAT. If it can't, see if letting it
2392 use I2DEST as a scratch register will help. In the latter case,
2393 convert I2DEST to the mode of the source of NEWPAT if we can. */
2395 m_split = split_insns (newpat, i3);
2397 /* We can only use I2DEST as a scratch reg if it doesn't overlap any
2398 inputs of NEWPAT. */
2400 /* ??? If I2DEST is not safe, and I1DEST exists, then it would be
2401 possible to try that as a scratch reg. This would require adding
2402 more code to make it work though. */
2404 if (m_split == 0 && ! reg_overlap_mentioned_p (ni2dest, newpat))
2406 enum machine_mode new_mode = GET_MODE (SET_DEST (newpat));
2407 /* If I2DEST is a hard register or the only use of a pseudo,
2408 we can change its mode. */
2409 if (new_mode != GET_MODE (i2dest)
2410 && new_mode != VOIDmode
2411 && can_change_dest_mode (i2dest, added_sets_2, new_mode))
2412 ni2dest = gen_rtx_REG (GET_MODE (SET_DEST (newpat)),
2415 m_split = split_insns (gen_rtx_PARALLEL
2417 gen_rtvec (2, newpat,
2418 gen_rtx_CLOBBER (VOIDmode,
2421 /* If the split with the mode-changed register didn't work, try
2422 the original register. */
2423 if (! m_split && ni2dest != i2dest)
2426 m_split = split_insns (gen_rtx_PARALLEL
2428 gen_rtvec (2, newpat,
2429 gen_rtx_CLOBBER (VOIDmode,
2435 /* If recog_for_combine has discarded clobbers, try to use them
2436 again for the split. */
2437 if (m_split == 0 && newpat_vec_with_clobbers)
2439 = split_insns (gen_rtx_PARALLEL (VOIDmode,
2440 newpat_vec_with_clobbers), i3);
2442 if (m_split && NEXT_INSN (m_split) == NULL_RTX)
2444 m_split = PATTERN (m_split);
2445 insn_code_number = recog_for_combine (&m_split, i3, &new_i3_notes);
2446 if (insn_code_number >= 0)
2449 else if (m_split && NEXT_INSN (NEXT_INSN (m_split)) == NULL_RTX
2450 && (next_real_insn (i2) == i3
2451 || ! use_crosses_set_p (PATTERN (m_split), INSN_CUID (i2))))
2454 rtx newi3pat = PATTERN (NEXT_INSN (m_split));
2455 newi2pat = PATTERN (m_split);
2457 i3set = single_set (NEXT_INSN (m_split));
2458 i2set = single_set (m_split);
2460 /* In case we changed the mode of I2DEST, replace it in the
2461 pseudo-register table here. We can't do it above in case this
2462 code doesn't get executed and we do a split the other way. */
2464 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2465 SUBST (regno_reg_rtx[REGNO (i2dest)], ni2dest);
2467 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2469 /* If I2 or I3 has multiple SETs, we won't know how to track
2470 register status, so don't use these insns. If I2's destination
2471 is used between I2 and I3, we also can't use these insns. */
2473 if (i2_code_number >= 0 && i2set && i3set
2474 && (next_real_insn (i2) == i3
2475 || ! reg_used_between_p (SET_DEST (i2set), i2, i3)))
2476 insn_code_number = recog_for_combine (&newi3pat, i3,
2478 if (insn_code_number >= 0)
2481 /* It is possible that both insns now set the destination of I3.
2482 If so, we must show an extra use of it. */
2484 if (insn_code_number >= 0)
2486 rtx new_i3_dest = SET_DEST (i3set);
2487 rtx new_i2_dest = SET_DEST (i2set);
2489 while (GET_CODE (new_i3_dest) == ZERO_EXTRACT
2490 || GET_CODE (new_i3_dest) == STRICT_LOW_PART
2491 || GET_CODE (new_i3_dest) == SUBREG)
2492 new_i3_dest = XEXP (new_i3_dest, 0);
2494 while (GET_CODE (new_i2_dest) == ZERO_EXTRACT
2495 || GET_CODE (new_i2_dest) == STRICT_LOW_PART
2496 || GET_CODE (new_i2_dest) == SUBREG)
2497 new_i2_dest = XEXP (new_i2_dest, 0);
2499 if (REG_P (new_i3_dest)
2500 && REG_P (new_i2_dest)
2501 && REGNO (new_i3_dest) == REGNO (new_i2_dest))
2502 REG_N_SETS (REGNO (new_i2_dest))++;
2506 /* If we can split it and use I2DEST, go ahead and see if that
2507 helps things be recognized. Verify that none of the registers
2508 are set between I2 and I3. */
2509 if (insn_code_number < 0 && (split = find_split_point (&newpat, i3)) != 0
2513 /* We need I2DEST in the proper mode. If it is a hard register
2514 or the only use of a pseudo, we can change its mode.
2515 Make sure we don't change a hard register to have a mode that
2516 isn't valid for it, or change the number of registers. */
2517 && (GET_MODE (*split) == GET_MODE (i2dest)
2518 || GET_MODE (*split) == VOIDmode
2519 || can_change_dest_mode (i2dest, added_sets_2,
2521 && (next_real_insn (i2) == i3
2522 || ! use_crosses_set_p (*split, INSN_CUID (i2)))
2523 /* We can't overwrite I2DEST if its value is still used by
2525 && ! reg_referenced_p (i2dest, newpat))
2527 rtx newdest = i2dest;
2528 enum rtx_code split_code = GET_CODE (*split);
2529 enum machine_mode split_mode = GET_MODE (*split);
2531 /* Get NEWDEST as a register in the proper mode. We have already
2532 validated that we can do this. */
2533 if (GET_MODE (i2dest) != split_mode && split_mode != VOIDmode)
2535 newdest = gen_rtx_REG (split_mode, REGNO (i2dest));
2537 if (REGNO (i2dest) >= FIRST_PSEUDO_REGISTER)
2538 SUBST (regno_reg_rtx[REGNO (i2dest)], newdest);
2541 /* If *SPLIT is a (mult FOO (const_int pow2)), convert it to
2542 an ASHIFT. This can occur if it was inside a PLUS and hence
2543 appeared to be a memory address. This is a kludge. */
2544 if (split_code == MULT
2545 && GET_CODE (XEXP (*split, 1)) == CONST_INT
2546 && INTVAL (XEXP (*split, 1)) > 0
2547 && (i = exact_log2 (INTVAL (XEXP (*split, 1)))) >= 0)
2549 SUBST (*split, gen_rtx_ASHIFT (split_mode,
2550 XEXP (*split, 0), GEN_INT (i)));
2551 /* Update split_code because we may not have a multiply
2553 split_code = GET_CODE (*split);
2556 #ifdef INSN_SCHEDULING
2557 /* If *SPLIT is a paradoxical SUBREG, when we split it, it should
2558 be written as a ZERO_EXTEND. */
2559 if (split_code == SUBREG && MEM_P (SUBREG_REG (*split)))
2561 #ifdef LOAD_EXTEND_OP
2562 /* Or as a SIGN_EXTEND if LOAD_EXTEND_OP says that that's
2563 what it really is. */
2564 if (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (*split)))
2566 SUBST (*split, gen_rtx_SIGN_EXTEND (split_mode,
2567 SUBREG_REG (*split)));
2570 SUBST (*split, gen_rtx_ZERO_EXTEND (split_mode,
2571 SUBREG_REG (*split)));
2575 newi2pat = gen_rtx_SET (VOIDmode, newdest, *split);
2576 SUBST (*split, newdest);
2577 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2579 /* recog_for_combine might have added CLOBBERs to newi2pat.
2580 Make sure NEWPAT does not depend on the clobbered regs. */
2581 if (GET_CODE (newi2pat) == PARALLEL)
2582 for (i = XVECLEN (newi2pat, 0) - 1; i >= 0; i--)
2583 if (GET_CODE (XVECEXP (newi2pat, 0, i)) == CLOBBER)
2585 rtx reg = XEXP (XVECEXP (newi2pat, 0, i), 0);
2586 if (reg_overlap_mentioned_p (reg, newpat))
2593 /* If the split point was a MULT and we didn't have one before,
2594 don't use one now. */
2595 if (i2_code_number >= 0 && ! (split_code == MULT && ! have_mult))
2596 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2600 /* Check for a case where we loaded from memory in a narrow mode and
2601 then sign extended it, but we need both registers. In that case,
2602 we have a PARALLEL with both loads from the same memory location.
2603 We can split this into a load from memory followed by a register-register
2604 copy. This saves at least one insn, more if register allocation can
2607 We cannot do this if the destination of the first assignment is a
2608 condition code register or cc0. We eliminate this case by making sure
2609 the SET_DEST and SET_SRC have the same mode.
2611 We cannot do this if the destination of the second assignment is
2612 a register that we have already assumed is zero-extended. Similarly
2613 for a SUBREG of such a register. */
2615 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2616 && GET_CODE (newpat) == PARALLEL
2617 && XVECLEN (newpat, 0) == 2
2618 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2619 && GET_CODE (SET_SRC (XVECEXP (newpat, 0, 0))) == SIGN_EXTEND
2620 && (GET_MODE (SET_DEST (XVECEXP (newpat, 0, 0)))
2621 == GET_MODE (SET_SRC (XVECEXP (newpat, 0, 0))))
2622 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2623 && rtx_equal_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2624 XEXP (SET_SRC (XVECEXP (newpat, 0, 0)), 0))
2625 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2627 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2628 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2629 && ! (temp = SET_DEST (XVECEXP (newpat, 0, 1)),
2631 && reg_stat[REGNO (temp)].nonzero_bits != 0
2632 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2633 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2634 && (reg_stat[REGNO (temp)].nonzero_bits
2635 != GET_MODE_MASK (word_mode))))
2636 && ! (GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) == SUBREG
2637 && (temp = SUBREG_REG (SET_DEST (XVECEXP (newpat, 0, 1))),
2639 && reg_stat[REGNO (temp)].nonzero_bits != 0
2640 && GET_MODE_BITSIZE (GET_MODE (temp)) < BITS_PER_WORD
2641 && GET_MODE_BITSIZE (GET_MODE (temp)) < HOST_BITS_PER_INT
2642 && (reg_stat[REGNO (temp)].nonzero_bits
2643 != GET_MODE_MASK (word_mode)))))
2644 && ! reg_overlap_mentioned_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2645 SET_SRC (XVECEXP (newpat, 0, 1)))
2646 && ! find_reg_note (i3, REG_UNUSED,
2647 SET_DEST (XVECEXP (newpat, 0, 0))))
2651 newi2pat = XVECEXP (newpat, 0, 0);
2652 ni2dest = SET_DEST (XVECEXP (newpat, 0, 0));
2653 newpat = XVECEXP (newpat, 0, 1);
2654 SUBST (SET_SRC (newpat),
2655 gen_lowpart (GET_MODE (SET_SRC (newpat)), ni2dest));
2656 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2658 if (i2_code_number >= 0)
2659 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2661 if (insn_code_number >= 0)
2665 /* Similarly, check for a case where we have a PARALLEL of two independent
2666 SETs but we started with three insns. In this case, we can do the sets
2667 as two separate insns. This case occurs when some SET allows two
2668 other insns to combine, but the destination of that SET is still live. */
2670 else if (i1 && insn_code_number < 0 && asm_noperands (newpat) < 0
2671 && GET_CODE (newpat) == PARALLEL
2672 && XVECLEN (newpat, 0) == 2
2673 && GET_CODE (XVECEXP (newpat, 0, 0)) == SET
2674 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != ZERO_EXTRACT
2675 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != STRICT_LOW_PART
2676 && GET_CODE (XVECEXP (newpat, 0, 1)) == SET
2677 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != ZERO_EXTRACT
2678 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != STRICT_LOW_PART
2679 && ! use_crosses_set_p (SET_SRC (XVECEXP (newpat, 0, 1)),
2681 /* Don't pass sets with (USE (MEM ...)) dests to the following. */
2682 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 1))) != USE
2683 && GET_CODE (SET_DEST (XVECEXP (newpat, 0, 0))) != USE
2684 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 1)),
2685 XVECEXP (newpat, 0, 0))
2686 && ! reg_referenced_p (SET_DEST (XVECEXP (newpat, 0, 0)),
2687 XVECEXP (newpat, 0, 1))
2688 && ! (contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 0)))
2689 && contains_muldiv (SET_SRC (XVECEXP (newpat, 0, 1)))))
2691 /* Normally, it doesn't matter which of the two is done first,
2692 but it does if one references cc0. In that case, it has to
2695 if (reg_referenced_p (cc0_rtx, XVECEXP (newpat, 0, 0)))
2697 newi2pat = XVECEXP (newpat, 0, 0);
2698 newpat = XVECEXP (newpat, 0, 1);
2703 newi2pat = XVECEXP (newpat, 0, 1);
2704 newpat = XVECEXP (newpat, 0, 0);
2707 i2_code_number = recog_for_combine (&newi2pat, i2, &new_i2_notes);
2709 if (i2_code_number >= 0)
2710 insn_code_number = recog_for_combine (&newpat, i3, &new_i3_notes);
2713 /* If it still isn't recognized, fail and change things back the way they
2715 if ((insn_code_number < 0
2716 /* Is the result a reasonable ASM_OPERANDS? */
2717 && (! check_asm_operands (newpat) || added_sets_1 || added_sets_2)))
2723 /* If we had to change another insn, make sure it is valid also. */
2724 if (undobuf.other_insn)
2726 rtx other_pat = PATTERN (undobuf.other_insn);
2727 rtx new_other_notes;
2730 CLEAR_HARD_REG_SET (newpat_used_regs);
2732 other_code_number = recog_for_combine (&other_pat, undobuf.other_insn,
2735 if (other_code_number < 0 && ! check_asm_operands (other_pat))
2741 PATTERN (undobuf.other_insn) = other_pat;
2743 /* If any of the notes in OTHER_INSN were REG_UNUSED, ensure that they
2744 are still valid. Then add any non-duplicate notes added by
2745 recog_for_combine. */
2746 for (note = REG_NOTES (undobuf.other_insn); note; note = next)
2748 next = XEXP (note, 1);
2750 if (REG_NOTE_KIND (note) == REG_UNUSED
2751 && ! reg_set_p (XEXP (note, 0), PATTERN (undobuf.other_insn)))
2753 if (REG_P (XEXP (note, 0)))
2754 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
2756 remove_note (undobuf.other_insn, note);
2760 for (note = new_other_notes; note; note = XEXP (note, 1))
2761 if (REG_P (XEXP (note, 0)))
2762 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
2764 distribute_notes (new_other_notes, undobuf.other_insn,
2765 undobuf.other_insn, NULL_RTX, NULL_RTX, NULL_RTX);
2768 /* If I2 is the CC0 setter and I3 is the CC0 user then check whether
2769 they are adjacent to each other or not. */
2771 rtx p = prev_nonnote_insn (i3);
2772 if (p && p != i2 && NONJUMP_INSN_P (p) && newi2pat
2773 && sets_cc0_p (newi2pat))
2781 /* Only allow this combination if insn_rtx_costs reports that the
2782 replacement instructions are cheaper than the originals. */
2783 if (!combine_validate_cost (i1, i2, i3, newpat, newi2pat))
2789 /* We now know that we can do this combination. Merge the insns and
2790 update the status of registers and LOG_LINKS. */
2798 /* I3 now uses what used to be its destination and which is now
2799 I2's destination. This requires us to do a few adjustments. */
2800 PATTERN (i3) = newpat;
2801 adjust_for_new_dest (i3);
2803 /* We need a LOG_LINK from I3 to I2. But we used to have one,
2806 However, some later insn might be using I2's dest and have
2807 a LOG_LINK pointing at I3. We must remove this link.
2808 The simplest way to remove the link is to point it at I1,
2809 which we know will be a NOTE. */
2811 /* newi2pat is usually a SET here; however, recog_for_combine might
2812 have added some clobbers. */
2813 if (GET_CODE (newi2pat) == PARALLEL)
2814 ni2dest = SET_DEST (XVECEXP (newi2pat, 0, 0));
2816 ni2dest = SET_DEST (newi2pat);
2818 for (insn = NEXT_INSN (i3);
2819 insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2820 || insn != BB_HEAD (this_basic_block->next_bb));
2821 insn = NEXT_INSN (insn))
2823 if (INSN_P (insn) && reg_referenced_p (ni2dest, PATTERN (insn)))
2825 for (link = LOG_LINKS (insn); link;
2826 link = XEXP (link, 1))
2827 if (XEXP (link, 0) == i3)
2828 XEXP (link, 0) = i1;
2836 rtx i3notes, i2notes, i1notes = 0;
2837 rtx i3links, i2links, i1links = 0;
2840 /* Compute which registers we expect to eliminate. newi2pat may be setting
2841 either i3dest or i2dest, so we must check it. Also, i1dest may be the
2842 same as i3dest, in which case newi2pat may be setting i1dest. */
2843 rtx elim_i2 = ((newi2pat && reg_set_p (i2dest, newi2pat))
2844 || i2dest_in_i2src || i2dest_in_i1src
2847 rtx elim_i1 = (i1 == 0 || i1dest_in_i1src
2848 || (newi2pat && reg_set_p (i1dest, newi2pat))
2852 /* Get the old REG_NOTES and LOG_LINKS from all our insns and
2854 i3notes = REG_NOTES (i3), i3links = LOG_LINKS (i3);
2855 i2notes = REG_NOTES (i2), i2links = LOG_LINKS (i2);
2857 i1notes = REG_NOTES (i1), i1links = LOG_LINKS (i1);
2859 /* Ensure that we do not have something that should not be shared but
2860 occurs multiple times in the new insns. Check this by first
2861 resetting all the `used' flags and then copying anything is shared. */
2863 reset_used_flags (i3notes);
2864 reset_used_flags (i2notes);
2865 reset_used_flags (i1notes);
2866 reset_used_flags (newpat);
2867 reset_used_flags (newi2pat);
2868 if (undobuf.other_insn)
2869 reset_used_flags (PATTERN (undobuf.other_insn));
2871 i3notes = copy_rtx_if_shared (i3notes);
2872 i2notes = copy_rtx_if_shared (i2notes);
2873 i1notes = copy_rtx_if_shared (i1notes);
2874 newpat = copy_rtx_if_shared (newpat);
2875 newi2pat = copy_rtx_if_shared (newi2pat);
2876 if (undobuf.other_insn)
2877 reset_used_flags (PATTERN (undobuf.other_insn));
2879 INSN_CODE (i3) = insn_code_number;
2880 PATTERN (i3) = newpat;
2882 if (CALL_P (i3) && CALL_INSN_FUNCTION_USAGE (i3))
2884 rtx call_usage = CALL_INSN_FUNCTION_USAGE (i3);
2886 reset_used_flags (call_usage);
2887 call_usage = copy_rtx (call_usage);
2890 replace_rtx (call_usage, i2dest, i2src);
2893 replace_rtx (call_usage, i1dest, i1src);
2895 CALL_INSN_FUNCTION_USAGE (i3) = call_usage;
2898 if (undobuf.other_insn)
2899 INSN_CODE (undobuf.other_insn) = other_code_number;
2901 /* We had one special case above where I2 had more than one set and
2902 we replaced a destination of one of those sets with the destination
2903 of I3. In that case, we have to update LOG_LINKS of insns later
2904 in this basic block. Note that this (expensive) case is rare.
2906 Also, in this case, we must pretend that all REG_NOTEs for I2
2907 actually came from I3, so that REG_UNUSED notes from I2 will be
2908 properly handled. */
2910 if (i3_subst_into_i2)
2912 for (i = 0; i < XVECLEN (PATTERN (i2), 0); i++)
2913 if (GET_CODE (XVECEXP (PATTERN (i2), 0, i)) != USE
2914 && REG_P (SET_DEST (XVECEXP (PATTERN (i2), 0, i)))
2915 && SET_DEST (XVECEXP (PATTERN (i2), 0, i)) != i2dest
2916 && ! find_reg_note (i2, REG_UNUSED,
2917 SET_DEST (XVECEXP (PATTERN (i2), 0, i))))
2918 for (temp = NEXT_INSN (i2);
2919 temp && (this_basic_block->next_bb == EXIT_BLOCK_PTR
2920 || BB_HEAD (this_basic_block) != temp);
2921 temp = NEXT_INSN (temp))
2922 if (temp != i3 && INSN_P (temp))
2923 for (link = LOG_LINKS (temp); link; link = XEXP (link, 1))
2924 if (XEXP (link, 0) == i2)
2925 XEXP (link, 0) = i3;
2930 while (XEXP (link, 1))
2931 link = XEXP (link, 1);
2932 XEXP (link, 1) = i2notes;
2946 INSN_CODE (i2) = i2_code_number;
2947 PATTERN (i2) = newi2pat;
2950 SET_INSN_DELETED (i2);
2956 SET_INSN_DELETED (i1);
2959 /* Get death notes for everything that is now used in either I3 or
2960 I2 and used to die in a previous insn. If we built two new
2961 patterns, move from I1 to I2 then I2 to I3 so that we get the
2962 proper movement on registers that I2 modifies. */
2966 move_deaths (newi2pat, NULL_RTX, INSN_CUID (i1), i2, &midnotes);
2967 move_deaths (newpat, newi2pat, INSN_CUID (i1), i3, &midnotes);
2970 move_deaths (newpat, NULL_RTX, i1 ? INSN_CUID (i1) : INSN_CUID (i2),
2973 /* Distribute all the LOG_LINKS and REG_NOTES from I1, I2, and I3. */
2975 distribute_notes (i3notes, i3, i3, newi2pat ? i2 : NULL_RTX,
2978 distribute_notes (i2notes, i2, i3, newi2pat ? i2 : NULL_RTX,
2981 distribute_notes (i1notes, i1, i3, newi2pat ? i2 : NULL_RTX,
2984 distribute_notes (midnotes, NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
2987 /* Distribute any notes added to I2 or I3 by recog_for_combine. We
2988 know these are REG_UNUSED and want them to go to the desired insn,
2989 so we always pass it as i3. We have not counted the notes in
2990 reg_n_deaths yet, so we need to do so now. */
2992 if (newi2pat && new_i2_notes)
2994 for (temp = new_i2_notes; temp; temp = XEXP (temp, 1))
2995 if (REG_P (XEXP (temp, 0)))
2996 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
2998 distribute_notes (new_i2_notes, i2, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3003 for (temp = new_i3_notes; temp; temp = XEXP (temp, 1))
3004 if (REG_P (XEXP (temp, 0)))
3005 REG_N_DEATHS (REGNO (XEXP (temp, 0)))++;
3007 distribute_notes (new_i3_notes, i3, i3, NULL_RTX, NULL_RTX, NULL_RTX);
3010 /* If I3DEST was used in I3SRC, it really died in I3. We may need to
3011 put a REG_DEAD note for it somewhere. If NEWI2PAT exists and sets
3012 I3DEST, the death must be somewhere before I2, not I3. If we passed I3
3013 in that case, it might delete I2. Similarly for I2 and I1.
3014 Show an additional death due to the REG_DEAD note we make here. If
3015 we discard it in distribute_notes, we will decrement it again. */
3019 if (REG_P (i3dest_killed))
3020 REG_N_DEATHS (REGNO (i3dest_killed))++;
3022 if (newi2pat && reg_set_p (i3dest_killed, newi2pat))
3023 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3025 NULL_RTX, i2, NULL_RTX, elim_i2, elim_i1);
3027 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i3dest_killed,
3029 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3033 if (i2dest_in_i2src)
3036 REG_N_DEATHS (REGNO (i2dest))++;
3038 if (newi2pat && reg_set_p (i2dest, newi2pat))
3039 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3040 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3042 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i2dest, NULL_RTX),
3043 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3044 NULL_RTX, NULL_RTX);
3047 if (i1dest_in_i1src)
3050 REG_N_DEATHS (REGNO (i1dest))++;
3052 if (newi2pat && reg_set_p (i1dest, newi2pat))
3053 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3054 NULL_RTX, i2, NULL_RTX, NULL_RTX, NULL_RTX);
3056 distribute_notes (gen_rtx_EXPR_LIST (REG_DEAD, i1dest, NULL_RTX),
3057 NULL_RTX, i3, newi2pat ? i2 : NULL_RTX,
3058 NULL_RTX, NULL_RTX);
3061 distribute_links (i3links);
3062 distribute_links (i2links);
3063 distribute_links (i1links);
3068 rtx i2_insn = 0, i2_val = 0, set;
3070 /* The insn that used to set this register doesn't exist, and
3071 this life of the register may not exist either. See if one of
3072 I3's links points to an insn that sets I2DEST. If it does,
3073 that is now the last known value for I2DEST. If we don't update
3074 this and I2 set the register to a value that depended on its old
3075 contents, we will get confused. If this insn is used, thing
3076 will be set correctly in combine_instructions. */
3078 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3079 if ((set = single_set (XEXP (link, 0))) != 0
3080 && rtx_equal_p (i2dest, SET_DEST (set)))
3081 i2_insn = XEXP (link, 0), i2_val = SET_SRC (set);
3083 record_value_for_reg (i2dest, i2_insn, i2_val);
3085 /* If the reg formerly set in I2 died only once and that was in I3,
3086 zero its use count so it won't make `reload' do any work. */
3088 && (newi2pat == 0 || ! reg_mentioned_p (i2dest, newi2pat))
3089 && ! i2dest_in_i2src)
3091 regno = REGNO (i2dest);
3092 REG_N_SETS (regno)--;
3096 if (i1 && REG_P (i1dest))
3099 rtx i1_insn = 0, i1_val = 0, set;
3101 for (link = LOG_LINKS (i3); link; link = XEXP (link, 1))
3102 if ((set = single_set (XEXP (link, 0))) != 0
3103 && rtx_equal_p (i1dest, SET_DEST (set)))
3104 i1_insn = XEXP (link, 0), i1_val = SET_SRC (set);
3106 record_value_for_reg (i1dest, i1_insn, i1_val);
3108 regno = REGNO (i1dest);
3109 if (! added_sets_1 && ! i1dest_in_i1src)
3110 REG_N_SETS (regno)--;
3113 /* Update reg_stat[].nonzero_bits et al for any changes that may have
3114 been made to this insn. The order of
3115 set_nonzero_bits_and_sign_copies() is important. Because newi2pat
3116 can affect nonzero_bits of newpat */
3118 note_stores (newi2pat, set_nonzero_bits_and_sign_copies, NULL);
3119 note_stores (newpat, set_nonzero_bits_and_sign_copies, NULL);
3121 /* Set new_direct_jump_p if a new return or simple jump instruction
3124 If I3 is now an unconditional jump, ensure that it has a
3125 BARRIER following it since it may have initially been a
3126 conditional jump. It may also be the last nonnote insn. */
3128 if (returnjump_p (i3) || any_uncondjump_p (i3))
3130 *new_direct_jump_p = 1;
3131 mark_jump_label (PATTERN (i3), i3, 0);
3133 if ((temp = next_nonnote_insn (i3)) == NULL_RTX
3134 || !BARRIER_P (temp))
3135 emit_barrier_after (i3);
3138 if (undobuf.other_insn != NULL_RTX
3139 && (returnjump_p (undobuf.other_insn)
3140 || any_uncondjump_p (undobuf.other_insn)))
3142 *new_direct_jump_p = 1;
3144 if ((temp = next_nonnote_insn (undobuf.other_insn)) == NULL_RTX
3145 || !BARRIER_P (temp))
3146 emit_barrier_after (undobuf.other_insn);
3149 /* An NOOP jump does not need barrier, but it does need cleaning up
3151 if (GET_CODE (newpat) == SET
3152 && SET_SRC (newpat) == pc_rtx
3153 && SET_DEST (newpat) == pc_rtx)
3154 *new_direct_jump_p = 1;
3157 combine_successes++;
3160 if (added_links_insn
3161 && (newi2pat == 0 || INSN_CUID (added_links_insn) < INSN_CUID (i2))
3162 && INSN_CUID (added_links_insn) < INSN_CUID (i3))
3163 return added_links_insn;
3165 return newi2pat ? i2 : i3;
3168 /* Undo all the modifications recorded in undobuf. */
3173 struct undo *undo, *next;
3175 for (undo = undobuf.undos; undo; undo = next)
3179 *undo->where.i = undo->old_contents.i;
3181 *undo->where.r = undo->old_contents.r;
3183 undo->next = undobuf.frees;
3184 undobuf.frees = undo;
3190 /* We've committed to accepting the changes we made. Move all
3191 of the undos to the free list. */
3196 struct undo *undo, *next;
3198 for (undo = undobuf.undos; undo; undo = next)
3201 undo->next = undobuf.frees;
3202 undobuf.frees = undo;
3208 /* Find the innermost point within the rtx at LOC, possibly LOC itself,
3209 where we have an arithmetic expression and return that point. LOC will
3212 try_combine will call this function to see if an insn can be split into
3216 find_split_point (rtx *loc, rtx insn)
3219 enum rtx_code code = GET_CODE (x);
3221 unsigned HOST_WIDE_INT len = 0;
3222 HOST_WIDE_INT pos = 0;
3224 rtx inner = NULL_RTX;
3226 /* First special-case some codes. */
3230 #ifdef INSN_SCHEDULING
3231 /* If we are making a paradoxical SUBREG invalid, it becomes a split
3233 if (MEM_P (SUBREG_REG (x)))
3236 return find_split_point (&SUBREG_REG (x), insn);
3240 /* If we have (mem (const ..)) or (mem (symbol_ref ...)), split it
3241 using LO_SUM and HIGH. */
3242 if (GET_CODE (XEXP (x, 0)) == CONST
3243 || GET_CODE (XEXP (x, 0)) == SYMBOL_REF)
3246 gen_rtx_LO_SUM (Pmode,
3247 gen_rtx_HIGH (Pmode, XEXP (x, 0)),
3249 return &XEXP (XEXP (x, 0), 0);
3253 /* If we have a PLUS whose second operand is a constant and the
3254 address is not valid, perhaps will can split it up using
3255 the machine-specific way to split large constants. We use
3256 the first pseudo-reg (one of the virtual regs) as a placeholder;
3257 it will not remain in the result. */
3258 if (GET_CODE (XEXP (x, 0)) == PLUS
3259 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
3260 && ! memory_address_p (GET_MODE (x), XEXP (x, 0)))
3262 rtx reg = regno_reg_rtx[FIRST_PSEUDO_REGISTER];
3263 rtx seq = split_insns (gen_rtx_SET (VOIDmode, reg, XEXP (x, 0)),
3266 /* This should have produced two insns, each of which sets our
3267 placeholder. If the source of the second is a valid address,
3268 we can make put both sources together and make a split point
3272 && NEXT_INSN (seq) != NULL_RTX
3273 && NEXT_INSN (NEXT_INSN (seq)) == NULL_RTX
3274 && NONJUMP_INSN_P (seq)
3275 && GET_CODE (PATTERN (seq)) == SET
3276 && SET_DEST (PATTERN (seq)) == reg
3277 && ! reg_mentioned_p (reg,
3278 SET_SRC (PATTERN (seq)))
3279 && NONJUMP_INSN_P (NEXT_INSN (seq))
3280 && GET_CODE (PATTERN (NEXT_INSN (seq))) == SET
3281 && SET_DEST (PATTERN (NEXT_INSN (seq))) == reg
3282 && memory_address_p (GET_MODE (x),
3283 SET_SRC (PATTERN (NEXT_INSN (seq)))))
3285 rtx src1 = SET_SRC (PATTERN (seq));
3286 rtx src2 = SET_SRC (PATTERN (NEXT_INSN (seq)));
3288 /* Replace the placeholder in SRC2 with SRC1. If we can
3289 find where in SRC2 it was placed, that can become our
3290 split point and we can replace this address with SRC2.
3291 Just try two obvious places. */
3293 src2 = replace_rtx (src2, reg, src1);
3295 if (XEXP (src2, 0) == src1)
3296 split = &XEXP (src2, 0);
3297 else if (GET_RTX_FORMAT (GET_CODE (XEXP (src2, 0)))[0] == 'e'
3298 && XEXP (XEXP (src2, 0), 0) == src1)
3299 split = &XEXP (XEXP (src2, 0), 0);
3303 SUBST (XEXP (x, 0), src2);
3308 /* If that didn't work, perhaps the first operand is complex and
3309 needs to be computed separately, so make a split point there.
3310 This will occur on machines that just support REG + CONST
3311 and have a constant moved through some previous computation. */
3313 else if (!OBJECT_P (XEXP (XEXP (x, 0), 0))
3314 && ! (GET_CODE (XEXP (XEXP (x, 0), 0)) == SUBREG
3315 && OBJECT_P (SUBREG_REG (XEXP (XEXP (x, 0), 0)))))
3316 return &XEXP (XEXP (x, 0), 0);
3322 /* If SET_DEST is CC0 and SET_SRC is not an operand, a COMPARE, or a
3323 ZERO_EXTRACT, the most likely reason why this doesn't match is that
3324 we need to put the operand into a register. So split at that
3327 if (SET_DEST (x) == cc0_rtx
3328 && GET_CODE (SET_SRC (x)) != COMPARE
3329 && GET_CODE (SET_SRC (x)) != ZERO_EXTRACT
3330 && !OBJECT_P (SET_SRC (x))
3331 && ! (GET_CODE (SET_SRC (x)) == SUBREG
3332 && OBJECT_P (SUBREG_REG (SET_SRC (x)))))
3333 return &SET_SRC (x);
3336 /* See if we can split SET_SRC as it stands. */
3337 split = find_split_point (&SET_SRC (x), insn);
3338 if (split && split != &SET_SRC (x))
3341 /* See if we can split SET_DEST as it stands. */
3342 split = find_split_point (&SET_DEST (x), insn);
3343 if (split && split != &SET_DEST (x))
3346 /* See if this is a bitfield assignment with everything constant. If
3347 so, this is an IOR of an AND, so split it into that. */
3348 if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
3349 && (GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)))
3350 <= HOST_BITS_PER_WIDE_INT)
3351 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT
3352 && GET_CODE (XEXP (SET_DEST (x), 2)) == CONST_INT
3353 && GET_CODE (SET_SRC (x)) == CONST_INT
3354 && ((INTVAL (XEXP (SET_DEST (x), 1))
3355 + INTVAL (XEXP (SET_DEST (x), 2)))
3356 <= GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0))))
3357 && ! side_effects_p (XEXP (SET_DEST (x), 0)))
3359 HOST_WIDE_INT pos = INTVAL (XEXP (SET_DEST (x), 2));
3360 unsigned HOST_WIDE_INT len = INTVAL (XEXP (SET_DEST (x), 1));
3361 unsigned HOST_WIDE_INT src = INTVAL (SET_SRC (x));
3362 rtx dest = XEXP (SET_DEST (x), 0);
3363 enum machine_mode mode = GET_MODE (dest);
3364 unsigned HOST_WIDE_INT mask = ((HOST_WIDE_INT) 1 << len) - 1;
3367 if (BITS_BIG_ENDIAN)
3368 pos = GET_MODE_BITSIZE (mode) - len - pos;
3370 or_mask = gen_int_mode (src << pos, mode);
3373 simplify_gen_binary (IOR, mode, dest, or_mask));
3376 rtx negmask = gen_int_mode (~(mask << pos), mode);
3378 simplify_gen_binary (IOR, mode,
3379 simplify_gen_binary (AND, mode,
3384 SUBST (SET_DEST (x), dest);
3386 split = find_split_point (&SET_SRC (x), insn);
3387 if (split && split != &SET_SRC (x))
3391 /* Otherwise, see if this is an operation that we can split into two.
3392 If so, try to split that. */
3393 code = GET_CODE (SET_SRC (x));
3398 /* If we are AND'ing with a large constant that is only a single
3399 bit and the result is only being used in a context where we
3400 need to know if it is zero or nonzero, replace it with a bit
3401 extraction. This will avoid the large constant, which might
3402 have taken more than one insn to make. If the constant were
3403 not a valid argument to the AND but took only one insn to make,
3404 this is no worse, but if it took more than one insn, it will
3407 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3408 && REG_P (XEXP (SET_SRC (x), 0))
3409 && (pos = exact_log2 (INTVAL (XEXP (SET_SRC (x), 1)))) >= 7
3410 && REG_P (SET_DEST (x))
3411 && (split = find_single_use (SET_DEST (x), insn, (rtx*) 0)) != 0
3412 && (GET_CODE (*split) == EQ || GET_CODE (*split) == NE)
3413 && XEXP (*split, 0) == SET_DEST (x)
3414 && XEXP (*split, 1) == const0_rtx)
3416 rtx extraction = make_extraction (GET_MODE (SET_DEST (x)),
3417 XEXP (SET_SRC (x), 0),
3418 pos, NULL_RTX, 1, 1, 0, 0);
3419 if (extraction != 0)
3421 SUBST (SET_SRC (x), extraction);
3422 return find_split_point (loc, insn);
3428 /* If STORE_FLAG_VALUE is -1, this is (NE X 0) and only one bit of X
3429 is known to be on, this can be converted into a NEG of a shift. */
3430 if (STORE_FLAG_VALUE == -1 && XEXP (SET_SRC (x), 1) == const0_rtx
3431 && GET_MODE (SET_SRC (x)) == GET_MODE (XEXP (SET_SRC (x), 0))
3432 && 1 <= (pos = exact_log2
3433 (nonzero_bits (XEXP (SET_SRC (x), 0),
3434 GET_MODE (XEXP (SET_SRC (x), 0))))))
3436 enum machine_mode mode = GET_MODE (XEXP (SET_SRC (x), 0));
3440 gen_rtx_LSHIFTRT (mode,
3441 XEXP (SET_SRC (x), 0),
3444 split = find_split_point (&SET_SRC (x), insn);
3445 if (split && split != &SET_SRC (x))
3451 inner = XEXP (SET_SRC (x), 0);
3453 /* We can't optimize if either mode is a partial integer
3454 mode as we don't know how many bits are significant
3456 if (GET_MODE_CLASS (GET_MODE (inner)) == MODE_PARTIAL_INT
3457 || GET_MODE_CLASS (GET_MODE (SET_SRC (x))) == MODE_PARTIAL_INT)
3461 len = GET_MODE_BITSIZE (GET_MODE (inner));
3467 if (GET_CODE (XEXP (SET_SRC (x), 1)) == CONST_INT
3468 && GET_CODE (XEXP (SET_SRC (x), 2)) == CONST_INT)
3470 inner = XEXP (SET_SRC (x), 0);
3471 len = INTVAL (XEXP (SET_SRC (x), 1));
3472 pos = INTVAL (XEXP (SET_SRC (x), 2));
3474 if (BITS_BIG_ENDIAN)
3475 pos = GET_MODE_BITSIZE (GET_MODE (inner)) - len - pos;
3476 unsignedp = (code == ZERO_EXTRACT);
3484 if (len && pos >= 0 && pos + len <= GET_MODE_BITSIZE (GET_MODE (inner)))
3486 enum machine_mode mode = GET_MODE (SET_SRC (x));
3488 /* For unsigned, we have a choice of a shift followed by an
3489 AND or two shifts. Use two shifts for field sizes where the
3490 constant might be too large. We assume here that we can
3491 always at least get 8-bit constants in an AND insn, which is
3492 true for every current RISC. */
3494 if (unsignedp && len <= 8)
3499 (mode, gen_lowpart (mode, inner),
3501 GEN_INT (((HOST_WIDE_INT) 1 << len) - 1)));
3503 split = find_split_point (&SET_SRC (x), insn);
3504 if (split && split != &SET_SRC (x))
3511 (unsignedp ? LSHIFTRT : ASHIFTRT, mode,
3512 gen_rtx_ASHIFT (mode,
3513 gen_lowpart (mode, inner),
3514 GEN_INT (GET_MODE_BITSIZE (mode)
3516 GEN_INT (GET_MODE_BITSIZE (mode) - len)));
3518 split = find_split_point (&SET_SRC (x), insn);
3519 if (split && split != &SET_SRC (x))
3524 /* See if this is a simple operation with a constant as the second
3525 operand. It might be that this constant is out of range and hence
3526 could be used as a split point. */
3527 if (BINARY_P (SET_SRC (x))
3528 && CONSTANT_P (XEXP (SET_SRC (x), 1))
3529 && (OBJECT_P (XEXP (SET_SRC (x), 0))
3530 || (GET_CODE (XEXP (SET_SRC (x), 0)) == SUBREG
3531 && OBJECT_P (SUBREG_REG (XEXP (SET_SRC (x), 0))))))
3532 return &XEXP (SET_SRC (x), 1);
3534 /* Finally, see if this is a simple operation with its first operand
3535 not in a register. The operation might require this operand in a
3536 register, so return it as a split point. We can always do this
3537 because if the first operand were another operation, we would have
3538 already found it as a split point. */
3539 if ((BINARY_P (SET_SRC (x)) || UNARY_P (SET_SRC (x)))
3540 && ! register_operand (XEXP (SET_SRC (x), 0), VOIDmode))
3541 return &XEXP (SET_SRC (x), 0);
3547 /* We write NOR as (and (not A) (not B)), but if we don't have a NOR,
3548 it is better to write this as (not (ior A B)) so we can split it.
3549 Similarly for IOR. */
3550 if (GET_CODE (XEXP (x, 0)) == NOT && GET_CODE (XEXP (x, 1)) == NOT)
3553 gen_rtx_NOT (GET_MODE (x),
3554 gen_rtx_fmt_ee (code == IOR ? AND : IOR,
3556 XEXP (XEXP (x, 0), 0),
3557 XEXP (XEXP (x, 1), 0))));
3558 return find_split_point (loc, insn);
3561 /* Many RISC machines have a large set of logical insns. If the
3562 second operand is a NOT, put it first so we will try to split the
3563 other operand first. */
3564 if (GET_CODE (XEXP (x, 1)) == NOT)
3566 rtx tem = XEXP (x, 0);
3567 SUBST (XEXP (x, 0), XEXP (x, 1));
3568 SUBST (XEXP (x, 1), tem);
3576 /* Otherwise, select our actions depending on our rtx class. */
3577 switch (GET_RTX_CLASS (code))
3579 case RTX_BITFIELD_OPS: /* This is ZERO_EXTRACT and SIGN_EXTRACT. */
3581 split = find_split_point (&XEXP (x, 2), insn);
3584 /* ... fall through ... */
3586 case RTX_COMM_ARITH:
3588 case RTX_COMM_COMPARE:
3589 split = find_split_point (&XEXP (x, 1), insn);
3592 /* ... fall through ... */
3594 /* Some machines have (and (shift ...) ...) insns. If X is not
3595 an AND, but XEXP (X, 0) is, use it as our split point. */
3596 if (GET_CODE (x) != AND && GET_CODE (XEXP (x, 0)) == AND)
3597 return &XEXP (x, 0);
3599 split = find_split_point (&XEXP (x, 0), insn);
3605 /* Otherwise, we don't have a split point. */
3610 /* Throughout X, replace FROM with TO, and return the result.
3611 The result is TO if X is FROM;
3612 otherwise the result is X, but its contents may have been modified.
3613 If they were modified, a record was made in undobuf so that
3614 undo_all will (among other things) return X to its original state.
3616 If the number of changes necessary is too much to record to undo,
3617 the excess changes are not made, so the result is invalid.
3618 The changes already made can still be undone.
3619 undobuf.num_undo is incremented for such changes, so by testing that
3620 the caller can tell whether the result is valid.
3622 `n_occurrences' is incremented each time FROM is replaced.
3624 IN_DEST is nonzero if we are processing the SET_DEST of a SET.
3626 UNIQUE_COPY is nonzero if each substitution must be unique. We do this
3627 by copying if `n_occurrences' is nonzero. */
3630 subst (rtx x, rtx from, rtx to, int in_dest, int unique_copy)
3632 enum rtx_code code = GET_CODE (x);
3633 enum machine_mode op0_mode = VOIDmode;
3638 /* Two expressions are equal if they are identical copies of a shared
3639 RTX or if they are both registers with the same register number
3642 #define COMBINE_RTX_EQUAL_P(X,Y) \
3644 || (REG_P (X) && REG_P (Y) \
3645 && REGNO (X) == REGNO (Y) && GET_MODE (X) == GET_MODE (Y)))
3647 if (! in_dest && COMBINE_RTX_EQUAL_P (x, from))
3650 return (unique_copy && n_occurrences > 1 ? copy_rtx (to) : to);
3653 /* If X and FROM are the same register but different modes, they will
3654 not have been seen as equal above. However, flow.c will make a
3655 LOG_LINKS entry for that case. If we do nothing, we will try to
3656 rerecognize our original insn and, when it succeeds, we will
3657 delete the feeding insn, which is incorrect.
3659 So force this insn not to match in this (rare) case. */
3660 if (! in_dest && code == REG && REG_P (from)
3661 && REGNO (x) == REGNO (from))
3662 return gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
3664 /* If this is an object, we are done unless it is a MEM or LO_SUM, both
3665 of which may contain things that can be combined. */
3666 if (code != MEM && code != LO_SUM && OBJECT_P (x))
3669 /* It is possible to have a subexpression appear twice in the insn.
3670 Suppose that FROM is a register that appears within TO.
3671 Then, after that subexpression has been scanned once by `subst',
3672 the second time it is scanned, TO may be found. If we were
3673 to scan TO here, we would find FROM within it and create a
3674 self-referent rtl structure which is completely wrong. */
3675 if (COMBINE_RTX_EQUAL_P (x, to))
3678 /* Parallel asm_operands need special attention because all of the
3679 inputs are shared across the arms. Furthermore, unsharing the
3680 rtl results in recognition failures. Failure to handle this case
3681 specially can result in circular rtl.
3683 Solve this by doing a normal pass across the first entry of the
3684 parallel, and only processing the SET_DESTs of the subsequent
3687 if (code == PARALLEL
3688 && GET_CODE (XVECEXP (x, 0, 0)) == SET
3689 && GET_CODE (SET_SRC (XVECEXP (x, 0, 0))) == ASM_OPERANDS)
3691 new = subst (XVECEXP (x, 0, 0), from, to, 0, unique_copy);
3693 /* If this substitution failed, this whole thing fails. */
3694 if (GET_CODE (new) == CLOBBER
3695 && XEXP (new, 0) == const0_rtx)
3698 SUBST (XVECEXP (x, 0, 0), new);
3700 for (i = XVECLEN (x, 0) - 1; i >= 1; i--)
3702 rtx dest = SET_DEST (XVECEXP (x, 0, i));
3705 && GET_CODE (dest) != CC0
3706 && GET_CODE (dest) != PC)
3708 new = subst (dest, from, to, 0, unique_copy);
3710 /* If this substitution failed, this whole thing fails. */
3711 if (GET_CODE (new) == CLOBBER
3712 && XEXP (new, 0) == const0_rtx)
3715 SUBST (SET_DEST (XVECEXP (x, 0, i)), new);
3721 len = GET_RTX_LENGTH (code);
3722 fmt = GET_RTX_FORMAT (code);
3724 /* We don't need to process a SET_DEST that is a register, CC0,
3725 or PC, so set up to skip this common case. All other cases
3726 where we want to suppress replacing something inside a
3727 SET_SRC are handled via the IN_DEST operand. */
3729 && (REG_P (SET_DEST (x))
3730 || GET_CODE (SET_DEST (x)) == CC0
3731 || GET_CODE (SET_DEST (x)) == PC))
3734 /* Get the mode of operand 0 in case X is now a SIGN_EXTEND of a
3737 op0_mode = GET_MODE (XEXP (x, 0));
3739 for (i = 0; i < len; i++)
3744 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3746 if (COMBINE_RTX_EQUAL_P (XVECEXP (x, i, j), from))
3748 new = (unique_copy && n_occurrences
3749 ? copy_rtx (to) : to);
3754 new = subst (XVECEXP (x, i, j), from, to, 0,
3757 /* If this substitution failed, this whole thing
3759 if (GET_CODE (new) == CLOBBER
3760 && XEXP (new, 0) == const0_rtx)
3764 SUBST (XVECEXP (x, i, j), new);
3767 else if (fmt[i] == 'e')
3769 /* If this is a register being set, ignore it. */
3773 && (((code == SUBREG || code == ZERO_EXTRACT)
3775 || code == STRICT_LOW_PART))
3778 else if (COMBINE_RTX_EQUAL_P (XEXP (x, i), from))
3780 /* In general, don't install a subreg involving two
3781 modes not tieable. It can worsen register
3782 allocation, and can even make invalid reload
3783 insns, since the reg inside may need to be copied
3784 from in the outside mode, and that may be invalid
3785 if it is an fp reg copied in integer mode.
3787 We allow two exceptions to this: It is valid if
3788 it is inside another SUBREG and the mode of that
3789 SUBREG and the mode of the inside of TO is
3790 tieable and it is valid if X is a SET that copies
3793 if (GET_CODE (to) == SUBREG
3794 && ! MODES_TIEABLE_P (GET_MODE (to),
3795 GET_MODE (SUBREG_REG (to)))
3796 && ! (code == SUBREG
3797 && MODES_TIEABLE_P (GET_MODE (x),
3798 GET_MODE (SUBREG_REG (to))))
3800 && ! (code == SET && i == 1 && XEXP (x, 0) == cc0_rtx)
3803 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3805 #ifdef CANNOT_CHANGE_MODE_CLASS
3808 && REGNO (to) < FIRST_PSEUDO_REGISTER
3809 && REG_CANNOT_CHANGE_MODE_P (REGNO (to),
3812 return gen_rtx_CLOBBER (VOIDmode, const0_rtx);
3815 new = (unique_copy && n_occurrences ? copy_rtx (to) : to);
3819 /* If we are in a SET_DEST, suppress most cases unless we
3820 have gone inside a MEM, in which case we want to
3821 simplify the address. We assume here that things that
3822 are actually part of the destination have their inner
3823 parts in the first expression. This is true for SUBREG,
3824 STRICT_LOW_PART, and ZERO_EXTRACT, which are the only
3825 things aside from REG and MEM that should appear in a
3827 new = subst (XEXP (x, i), from, to,
3829 && (code == SUBREG || code == STRICT_LOW_PART
3830 || code == ZERO_EXTRACT))
3832 && i == 0), unique_copy);
3834 /* If we found that we will have to reject this combination,
3835 indicate that by returning the CLOBBER ourselves, rather than
3836 an expression containing it. This will speed things up as
3837 well as prevent accidents where two CLOBBERs are considered
3838 to be equal, thus producing an incorrect simplification. */
3840 if (GET_CODE (new) == CLOBBER && XEXP (new, 0) == const0_rtx)
3843 if (GET_CODE (x) == SUBREG
3844 && (GET_CODE (new) == CONST_INT
3845 || GET_CODE (new) == CONST_DOUBLE))
3847 enum machine_mode mode = GET_MODE (x);
3849 x = simplify_subreg (GET_MODE (x), new,
3850 GET_MODE (SUBREG_REG (x)),
3853 x = gen_rtx_CLOBBER (mode, const0_rtx);
3855 else if (GET_CODE (new) == CONST_INT
3856 && GET_CODE (x) == ZERO_EXTEND)
3858 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
3859 new, GET_MODE (XEXP (x, 0)));
3863 SUBST (XEXP (x, i), new);
3868 /* Try to simplify X. If the simplification changed the code, it is likely
3869 that further simplification will help, so loop, but limit the number
3870 of repetitions that will be performed. */
3872 for (i = 0; i < 4; i++)
3874 /* If X is sufficiently simple, don't bother trying to do anything
3876 if (code != CONST_INT && code != REG && code != CLOBBER)
3877 x = combine_simplify_rtx (x, op0_mode, in_dest);
3879 if (GET_CODE (x) == code)
3882 code = GET_CODE (x);
3884 /* We no longer know the original mode of operand 0 since we
3885 have changed the form of X) */
3886 op0_mode = VOIDmode;
3892 /* Simplify X, a piece of RTL. We just operate on the expression at the
3893 outer level; call `subst' to simplify recursively. Return the new
3896 OP0_MODE is the original mode of XEXP (x, 0). IN_DEST is nonzero
3897 if we are inside a SET_DEST. */
3900 combine_simplify_rtx (rtx x, enum machine_mode op0_mode, int in_dest)
3902 enum rtx_code code = GET_CODE (x);
3903 enum machine_mode mode = GET_MODE (x);
3907 /* If this is a commutative operation, put a constant last and a complex
3908 expression first. We don't need to do this for comparisons here. */
3909 if (COMMUTATIVE_ARITH_P (x)
3910 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
3913 SUBST (XEXP (x, 0), XEXP (x, 1));
3914 SUBST (XEXP (x, 1), temp);
3917 /* If this is a simple operation applied to an IF_THEN_ELSE, try
3918 applying it to the arms of the IF_THEN_ELSE. This often simplifies
3919 things. Check for cases where both arms are testing the same
3922 Don't do anything if all operands are very simple. */
3925 && ((!OBJECT_P (XEXP (x, 0))
3926 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3927 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))
3928 || (!OBJECT_P (XEXP (x, 1))
3929 && ! (GET_CODE (XEXP (x, 1)) == SUBREG
3930 && OBJECT_P (SUBREG_REG (XEXP (x, 1)))))))
3932 && (!OBJECT_P (XEXP (x, 0))
3933 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
3934 && OBJECT_P (SUBREG_REG (XEXP (x, 0)))))))
3936 rtx cond, true_rtx, false_rtx;
3938 cond = if_then_else_cond (x, &true_rtx, &false_rtx);
3940 /* If everything is a comparison, what we have is highly unlikely
3941 to be simpler, so don't use it. */
3942 && ! (COMPARISON_P (x)
3943 && (COMPARISON_P (true_rtx) || COMPARISON_P (false_rtx))))
3945 rtx cop1 = const0_rtx;
3946 enum rtx_code cond_code = simplify_comparison (NE, &cond, &cop1);
3948 if (cond_code == NE && COMPARISON_P (cond))
3951 /* Simplify the alternative arms; this may collapse the true and
3952 false arms to store-flag values. Be careful to use copy_rtx
3953 here since true_rtx or false_rtx might share RTL with x as a
3954 result of the if_then_else_cond call above. */
3955 true_rtx = subst (copy_rtx (true_rtx), pc_rtx, pc_rtx, 0, 0);
3956 false_rtx = subst (copy_rtx (false_rtx), pc_rtx, pc_rtx, 0, 0);
3958 /* If true_rtx and false_rtx are not general_operands, an if_then_else
3959 is unlikely to be simpler. */
3960 if (general_operand (true_rtx, VOIDmode)
3961 && general_operand (false_rtx, VOIDmode))
3963 enum rtx_code reversed;
3965 /* Restarting if we generate a store-flag expression will cause
3966 us to loop. Just drop through in this case. */
3968 /* If the result values are STORE_FLAG_VALUE and zero, we can
3969 just make the comparison operation. */
3970 if (true_rtx == const_true_rtx && false_rtx == const0_rtx)
3971 x = simplify_gen_relational (cond_code, mode, VOIDmode,
3973 else if (true_rtx == const0_rtx && false_rtx == const_true_rtx
3974 && ((reversed = reversed_comparison_code_parts
3975 (cond_code, cond, cop1, NULL))
3977 x = simplify_gen_relational (reversed, mode, VOIDmode,
3980 /* Likewise, we can make the negate of a comparison operation
3981 if the result values are - STORE_FLAG_VALUE and zero. */
3982 else if (GET_CODE (true_rtx) == CONST_INT
3983 && INTVAL (true_rtx) == - STORE_FLAG_VALUE
3984 && false_rtx == const0_rtx)
3985 x = simplify_gen_unary (NEG, mode,
3986 simplify_gen_relational (cond_code,
3990 else if (GET_CODE (false_rtx) == CONST_INT
3991 && INTVAL (false_rtx) == - STORE_FLAG_VALUE
3992 && true_rtx == const0_rtx
3993 && ((reversed = reversed_comparison_code_parts
3994 (cond_code, cond, cop1, NULL))
3996 x = simplify_gen_unary (NEG, mode,
3997 simplify_gen_relational (reversed,
4002 return gen_rtx_IF_THEN_ELSE (mode,
4003 simplify_gen_relational (cond_code,
4008 true_rtx, false_rtx);
4010 code = GET_CODE (x);
4011 op0_mode = VOIDmode;
4016 /* Try to fold this expression in case we have constants that weren't
4019 switch (GET_RTX_CLASS (code))
4022 if (op0_mode == VOIDmode)
4023 op0_mode = GET_MODE (XEXP (x, 0));
4024 temp = simplify_unary_operation (code, mode, XEXP (x, 0), op0_mode);
4027 case RTX_COMM_COMPARE:
4029 enum machine_mode cmp_mode = GET_MODE (XEXP (x, 0));
4030 if (cmp_mode == VOIDmode)
4032 cmp_mode = GET_MODE (XEXP (x, 1));
4033 if (cmp_mode == VOIDmode)
4034 cmp_mode = op0_mode;
4036 temp = simplify_relational_operation (code, mode, cmp_mode,
4037 XEXP (x, 0), XEXP (x, 1));
4040 case RTX_COMM_ARITH:
4042 temp = simplify_binary_operation (code, mode, XEXP (x, 0), XEXP (x, 1));
4044 case RTX_BITFIELD_OPS:
4046 temp = simplify_ternary_operation (code, mode, op0_mode, XEXP (x, 0),
4047 XEXP (x, 1), XEXP (x, 2));
4056 code = GET_CODE (temp);
4057 op0_mode = VOIDmode;
4058 mode = GET_MODE (temp);
4061 /* First see if we can apply the inverse distributive law. */
4062 if (code == PLUS || code == MINUS
4063 || code == AND || code == IOR || code == XOR)
4065 x = apply_distributive_law (x);
4066 code = GET_CODE (x);
4067 op0_mode = VOIDmode;
4070 /* If CODE is an associative operation not otherwise handled, see if we
4071 can associate some operands. This can win if they are constants or
4072 if they are logically related (i.e. (a & b) & a). */
4073 if ((code == PLUS || code == MINUS || code == MULT || code == DIV
4074 || code == AND || code == IOR || code == XOR
4075 || code == SMAX || code == SMIN || code == UMAX || code == UMIN)
4076 && ((INTEGRAL_MODE_P (mode) && code != DIV)
4077 || (flag_unsafe_math_optimizations && FLOAT_MODE_P (mode))))
4079 if (GET_CODE (XEXP (x, 0)) == code)
4081 rtx other = XEXP (XEXP (x, 0), 0);
4082 rtx inner_op0 = XEXP (XEXP (x, 0), 1);
4083 rtx inner_op1 = XEXP (x, 1);
4086 /* Make sure we pass the constant operand if any as the second
4087 one if this is a commutative operation. */
4088 if (CONSTANT_P (inner_op0) && COMMUTATIVE_ARITH_P (x))
4090 rtx tem = inner_op0;
4091 inner_op0 = inner_op1;
4094 inner = simplify_binary_operation (code == MINUS ? PLUS
4095 : code == DIV ? MULT
4097 mode, inner_op0, inner_op1);
4099 /* For commutative operations, try the other pair if that one
4101 if (inner == 0 && COMMUTATIVE_ARITH_P (x))
4103 other = XEXP (XEXP (x, 0), 1);
4104 inner = simplify_binary_operation (code, mode,
4105 XEXP (XEXP (x, 0), 0),
4110 return simplify_gen_binary (code, mode, other, inner);
4114 /* A little bit of algebraic simplification here. */
4118 /* Ensure that our address has any ASHIFTs converted to MULT in case
4119 address-recognizing predicates are called later. */
4120 temp = make_compound_operation (XEXP (x, 0), MEM);
4121 SUBST (XEXP (x, 0), temp);
4125 if (op0_mode == VOIDmode)
4126 op0_mode = GET_MODE (SUBREG_REG (x));
4128 /* See if this can be moved to simplify_subreg. */
4129 if (CONSTANT_P (SUBREG_REG (x))
4130 && subreg_lowpart_offset (mode, op0_mode) == SUBREG_BYTE (x)
4131 /* Don't call gen_lowpart if the inner mode
4132 is VOIDmode and we cannot simplify it, as SUBREG without
4133 inner mode is invalid. */
4134 && (GET_MODE (SUBREG_REG (x)) != VOIDmode
4135 || gen_lowpart_common (mode, SUBREG_REG (x))))
4136 return gen_lowpart (mode, SUBREG_REG (x));
4138 if (GET_MODE_CLASS (GET_MODE (SUBREG_REG (x))) == MODE_CC)
4142 temp = simplify_subreg (mode, SUBREG_REG (x), op0_mode,
4148 /* Don't change the mode of the MEM if that would change the meaning
4150 if (MEM_P (SUBREG_REG (x))
4151 && (MEM_VOLATILE_P (SUBREG_REG (x))
4152 || mode_dependent_address_p (XEXP (SUBREG_REG (x), 0))))
4153 return gen_rtx_CLOBBER (mode, const0_rtx);
4155 /* Note that we cannot do any narrowing for non-constants since
4156 we might have been counting on using the fact that some bits were
4157 zero. We now do this in the SET. */
4162 temp = expand_compound_operation (XEXP (x, 0));
4164 /* For C equal to the width of MODE minus 1, (neg (ashiftrt X C)) can be
4165 replaced by (lshiftrt X C). This will convert
4166 (neg (sign_extract X 1 Y)) to (zero_extract X 1 Y). */
4168 if (GET_CODE (temp) == ASHIFTRT
4169 && GET_CODE (XEXP (temp, 1)) == CONST_INT
4170 && INTVAL (XEXP (temp, 1)) == GET_MODE_BITSIZE (mode) - 1)
4171 return simplify_shift_const (temp, LSHIFTRT, mode, XEXP (temp, 0),
4172 INTVAL (XEXP (temp, 1)));
4174 /* If X has only a single bit that might be nonzero, say, bit I, convert
4175 (neg X) to (ashiftrt (ashift X C-I) C-I) where C is the bitsize of
4176 MODE minus 1. This will convert (neg (zero_extract X 1 Y)) to
4177 (sign_extract X 1 Y). But only do this if TEMP isn't a register
4178 or a SUBREG of one since we'd be making the expression more
4179 complex if it was just a register. */
4182 && ! (GET_CODE (temp) == SUBREG
4183 && REG_P (SUBREG_REG (temp)))
4184 && (i = exact_log2 (nonzero_bits (temp, mode))) >= 0)
4186 rtx temp1 = simplify_shift_const
4187 (NULL_RTX, ASHIFTRT, mode,
4188 simplify_shift_const (NULL_RTX, ASHIFT, mode, temp,
4189 GET_MODE_BITSIZE (mode) - 1 - i),
4190 GET_MODE_BITSIZE (mode) - 1 - i);
4192 /* If all we did was surround TEMP with the two shifts, we
4193 haven't improved anything, so don't use it. Otherwise,
4194 we are better off with TEMP1. */
4195 if (GET_CODE (temp1) != ASHIFTRT
4196 || GET_CODE (XEXP (temp1, 0)) != ASHIFT
4197 || XEXP (XEXP (temp1, 0), 0) != temp)
4203 /* We can't handle truncation to a partial integer mode here
4204 because we don't know the real bitsize of the partial
4206 if (GET_MODE_CLASS (mode) == MODE_PARTIAL_INT)
4209 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4210 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (mode),
4211 GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))))
4213 force_to_mode (XEXP (x, 0), GET_MODE (XEXP (x, 0)),
4214 GET_MODE_MASK (mode), 0));
4216 /* Similarly to what we do in simplify-rtx.c, a truncate of a register
4217 whose value is a comparison can be replaced with a subreg if
4218 STORE_FLAG_VALUE permits. */
4219 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4220 && ((HOST_WIDE_INT) STORE_FLAG_VALUE & ~GET_MODE_MASK (mode)) == 0
4221 && (temp = get_last_value (XEXP (x, 0)))
4222 && COMPARISON_P (temp))
4223 return gen_lowpart (mode, XEXP (x, 0));
4228 /* Convert (compare FOO (const_int 0)) to FOO unless we aren't
4229 using cc0, in which case we want to leave it as a COMPARE
4230 so we can distinguish it from a register-register-copy. */
4231 if (XEXP (x, 1) == const0_rtx)
4234 /* x - 0 is the same as x unless x's mode has signed zeros and
4235 allows rounding towards -infinity. Under those conditions,
4237 if (!(HONOR_SIGNED_ZEROS (GET_MODE (XEXP (x, 0)))
4238 && HONOR_SIGN_DEPENDENT_ROUNDING (GET_MODE (XEXP (x, 0))))
4239 && XEXP (x, 1) == CONST0_RTX (GET_MODE (XEXP (x, 0))))
4245 /* (const (const X)) can become (const X). Do it this way rather than
4246 returning the inner CONST since CONST can be shared with a
4248 if (GET_CODE (XEXP (x, 0)) == CONST)
4249 SUBST (XEXP (x, 0), XEXP (XEXP (x, 0), 0));
4254 /* Convert (lo_sum (high FOO) FOO) to FOO. This is necessary so we
4255 can add in an offset. find_split_point will split this address up
4256 again if it doesn't match. */
4257 if (GET_CODE (XEXP (x, 0)) == HIGH
4258 && rtx_equal_p (XEXP (XEXP (x, 0), 0), XEXP (x, 1)))
4264 /* (plus (xor (and <foo> (const_int pow2 - 1)) <c>) <-c>)
4265 when c is (const_int (pow2 + 1) / 2) is a sign extension of a
4266 bit-field and can be replaced by either a sign_extend or a
4267 sign_extract. The `and' may be a zero_extend and the two
4268 <c>, -<c> constants may be reversed. */
4269 if (GET_CODE (XEXP (x, 0)) == XOR
4270 && GET_CODE (XEXP (x, 1)) == CONST_INT
4271 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
4272 && INTVAL (XEXP (x, 1)) == -INTVAL (XEXP (XEXP (x, 0), 1))
4273 && ((i = exact_log2 (INTVAL (XEXP (XEXP (x, 0), 1)))) >= 0
4274 || (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
4275 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4276 && ((GET_CODE (XEXP (XEXP (x, 0), 0)) == AND
4277 && GET_CODE (XEXP (XEXP (XEXP (x, 0), 0), 1)) == CONST_INT
4278 && (INTVAL (XEXP (XEXP (XEXP (x, 0), 0), 1))
4279 == ((HOST_WIDE_INT) 1 << (i + 1)) - 1))
4280 || (GET_CODE (XEXP (XEXP (x, 0), 0)) == ZERO_EXTEND
4281 && (GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (XEXP (x, 0), 0), 0)))
4282 == (unsigned int) i + 1))))
4283 return simplify_shift_const
4284 (NULL_RTX, ASHIFTRT, mode,
4285 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4286 XEXP (XEXP (XEXP (x, 0), 0), 0),
4287 GET_MODE_BITSIZE (mode) - (i + 1)),
4288 GET_MODE_BITSIZE (mode) - (i + 1));
4290 /* If only the low-order bit of X is possibly nonzero, (plus x -1)
4291 can become (ashiftrt (ashift (xor x 1) C) C) where C is
4292 the bitsize of the mode - 1. This allows simplification of
4293 "a = (b & 8) == 0;" */
4294 if (XEXP (x, 1) == constm1_rtx
4295 && !REG_P (XEXP (x, 0))
4296 && ! (GET_CODE (XEXP (x, 0)) == SUBREG
4297 && REG_P (SUBREG_REG (XEXP (x, 0))))
4298 && nonzero_bits (XEXP (x, 0), mode) == 1)
4299 return simplify_shift_const (NULL_RTX, ASHIFTRT, mode,
4300 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4301 gen_rtx_XOR (mode, XEXP (x, 0), const1_rtx),
4302 GET_MODE_BITSIZE (mode) - 1),
4303 GET_MODE_BITSIZE (mode) - 1);
4305 /* If we are adding two things that have no bits in common, convert
4306 the addition into an IOR. This will often be further simplified,
4307 for example in cases like ((a & 1) + (a & 2)), which can
4310 if (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4311 && (nonzero_bits (XEXP (x, 0), mode)
4312 & nonzero_bits (XEXP (x, 1), mode)) == 0)
4314 /* Try to simplify the expression further. */
4315 rtx tor = simplify_gen_binary (IOR, mode, XEXP (x, 0), XEXP (x, 1));
4316 temp = combine_simplify_rtx (tor, mode, in_dest);
4318 /* If we could, great. If not, do not go ahead with the IOR
4319 replacement, since PLUS appears in many special purpose
4320 address arithmetic instructions. */
4321 if (GET_CODE (temp) != CLOBBER && temp != tor)
4327 /* (minus <foo> (and <foo> (const_int -pow2))) becomes
4328 (and <foo> (const_int pow2-1)) */
4329 if (GET_CODE (XEXP (x, 1)) == AND
4330 && GET_CODE (XEXP (XEXP (x, 1), 1)) == CONST_INT
4331 && exact_log2 (-INTVAL (XEXP (XEXP (x, 1), 1))) >= 0
4332 && rtx_equal_p (XEXP (XEXP (x, 1), 0), XEXP (x, 0)))
4333 return simplify_and_const_int (NULL_RTX, mode, XEXP (x, 0),
4334 -INTVAL (XEXP (XEXP (x, 1), 1)) - 1);
4338 /* If we have (mult (plus A B) C), apply the distributive law and then
4339 the inverse distributive law to see if things simplify. This
4340 occurs mostly in addresses, often when unrolling loops. */
4342 if (GET_CODE (XEXP (x, 0)) == PLUS)
4344 rtx result = distribute_and_simplify_rtx (x, 0);
4349 /* Try simplify a*(b/c) as (a*b)/c. */
4350 if (FLOAT_MODE_P (mode) && flag_unsafe_math_optimizations
4351 && GET_CODE (XEXP (x, 0)) == DIV)
4353 rtx tem = simplify_binary_operation (MULT, mode,
4354 XEXP (XEXP (x, 0), 0),
4357 return simplify_gen_binary (DIV, mode, tem, XEXP (XEXP (x, 0), 1));
4362 /* If this is a divide by a power of two, treat it as a shift if
4363 its first operand is a shift. */
4364 if (GET_CODE (XEXP (x, 1)) == CONST_INT
4365 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0
4366 && (GET_CODE (XEXP (x, 0)) == ASHIFT
4367 || GET_CODE (XEXP (x, 0)) == LSHIFTRT
4368 || GET_CODE (XEXP (x, 0)) == ASHIFTRT
4369 || GET_CODE (XEXP (x, 0)) == ROTATE
4370 || GET_CODE (XEXP (x, 0)) == ROTATERT))
4371 return simplify_shift_const (NULL_RTX, LSHIFTRT, mode, XEXP (x, 0), i);
4375 case GT: case GTU: case GE: case GEU:
4376 case LT: case LTU: case LE: case LEU:
4377 case UNEQ: case LTGT:
4378 case UNGT: case UNGE:
4379 case UNLT: case UNLE:
4380 case UNORDERED: case ORDERED:
4381 /* If the first operand is a condition code, we can't do anything
4383 if (GET_CODE (XEXP (x, 0)) == COMPARE
4384 || (GET_MODE_CLASS (GET_MODE (XEXP (x, 0))) != MODE_CC
4385 && ! CC0_P (XEXP (x, 0))))
4387 rtx op0 = XEXP (x, 0);
4388 rtx op1 = XEXP (x, 1);
4389 enum rtx_code new_code;
4391 if (GET_CODE (op0) == COMPARE)
4392 op1 = XEXP (op0, 1), op0 = XEXP (op0, 0);
4394 /* Simplify our comparison, if possible. */
4395 new_code = simplify_comparison (code, &op0, &op1);
4397 /* If STORE_FLAG_VALUE is 1, we can convert (ne x 0) to simply X
4398 if only the low-order bit is possibly nonzero in X (such as when
4399 X is a ZERO_EXTRACT of one bit). Similarly, we can convert EQ to
4400 (xor X 1) or (minus 1 X); we use the former. Finally, if X is
4401 known to be either 0 or -1, NE becomes a NEG and EQ becomes
4404 Remove any ZERO_EXTRACT we made when thinking this was a
4405 comparison. It may now be simpler to use, e.g., an AND. If a
4406 ZERO_EXTRACT is indeed appropriate, it will be placed back by
4407 the call to make_compound_operation in the SET case. */
4409 if (STORE_FLAG_VALUE == 1
4410 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4411 && op1 == const0_rtx
4412 && mode == GET_MODE (op0)
4413 && nonzero_bits (op0, mode) == 1)
4414 return gen_lowpart (mode,
4415 expand_compound_operation (op0));
4417 else if (STORE_FLAG_VALUE == 1
4418 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4419 && op1 == const0_rtx
4420 && mode == GET_MODE (op0)
4421 && (num_sign_bit_copies (op0, mode)
4422 == GET_MODE_BITSIZE (mode)))
4424 op0 = expand_compound_operation (op0);
4425 return simplify_gen_unary (NEG, mode,
4426 gen_lowpart (mode, op0),
4430 else if (STORE_FLAG_VALUE == 1
4431 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4432 && op1 == const0_rtx
4433 && mode == GET_MODE (op0)
4434 && nonzero_bits (op0, mode) == 1)
4436 op0 = expand_compound_operation (op0);
4437 return simplify_gen_binary (XOR, mode,
4438 gen_lowpart (mode, op0),
4442 else if (STORE_FLAG_VALUE == 1
4443 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4444 && op1 == const0_rtx
4445 && mode == GET_MODE (op0)
4446 && (num_sign_bit_copies (op0, mode)
4447 == GET_MODE_BITSIZE (mode)))
4449 op0 = expand_compound_operation (op0);
4450 return plus_constant (gen_lowpart (mode, op0), 1);
4453 /* If STORE_FLAG_VALUE is -1, we have cases similar to
4455 if (STORE_FLAG_VALUE == -1
4456 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4457 && op1 == const0_rtx
4458 && (num_sign_bit_copies (op0, mode)
4459 == GET_MODE_BITSIZE (mode)))
4460 return gen_lowpart (mode,
4461 expand_compound_operation (op0));
4463 else if (STORE_FLAG_VALUE == -1
4464 && new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4465 && op1 == const0_rtx
4466 && mode == GET_MODE (op0)
4467 && nonzero_bits (op0, mode) == 1)
4469 op0 = expand_compound_operation (op0);
4470 return simplify_gen_unary (NEG, mode,
4471 gen_lowpart (mode, op0),
4475 else if (STORE_FLAG_VALUE == -1
4476 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4477 && op1 == const0_rtx
4478 && mode == GET_MODE (op0)
4479 && (num_sign_bit_copies (op0, mode)
4480 == GET_MODE_BITSIZE (mode)))
4482 op0 = expand_compound_operation (op0);
4483 return simplify_gen_unary (NOT, mode,
4484 gen_lowpart (mode, op0),
4488 /* If X is 0/1, (eq X 0) is X-1. */
4489 else if (STORE_FLAG_VALUE == -1
4490 && new_code == EQ && GET_MODE_CLASS (mode) == MODE_INT
4491 && op1 == const0_rtx
4492 && mode == GET_MODE (op0)
4493 && nonzero_bits (op0, mode) == 1)
4495 op0 = expand_compound_operation (op0);
4496 return plus_constant (gen_lowpart (mode, op0), -1);
4499 /* If STORE_FLAG_VALUE says to just test the sign bit and X has just
4500 one bit that might be nonzero, we can convert (ne x 0) to
4501 (ashift x c) where C puts the bit in the sign bit. Remove any
4502 AND with STORE_FLAG_VALUE when we are done, since we are only
4503 going to test the sign bit. */
4504 if (new_code == NE && GET_MODE_CLASS (mode) == MODE_INT
4505 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4506 && ((STORE_FLAG_VALUE & GET_MODE_MASK (mode))
4507 == (unsigned HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (mode) - 1))
4508 && op1 == const0_rtx
4509 && mode == GET_MODE (op0)
4510 && (i = exact_log2 (nonzero_bits (op0, mode))) >= 0)
4512 x = simplify_shift_const (NULL_RTX, ASHIFT, mode,
4513 expand_compound_operation (op0),
4514 GET_MODE_BITSIZE (mode) - 1 - i);
4515 if (GET_CODE (x) == AND && XEXP (x, 1) == const_true_rtx)
4521 /* If the code changed, return a whole new comparison. */
4522 if (new_code != code)
4523 return gen_rtx_fmt_ee (new_code, mode, op0, op1);
4525 /* Otherwise, keep this operation, but maybe change its operands.
4526 This also converts (ne (compare FOO BAR) 0) to (ne FOO BAR). */
4527 SUBST (XEXP (x, 0), op0);
4528 SUBST (XEXP (x, 1), op1);
4533 return simplify_if_then_else (x);
4539 /* If we are processing SET_DEST, we are done. */
4543 return expand_compound_operation (x);
4546 return simplify_set (x);
4550 return simplify_logical (x);
4557 /* If this is a shift by a constant amount, simplify it. */
4558 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
4559 return simplify_shift_const (x, code, mode, XEXP (x, 0),
4560 INTVAL (XEXP (x, 1)));
4562 else if (SHIFT_COUNT_TRUNCATED && !REG_P (XEXP (x, 1)))
4564 force_to_mode (XEXP (x, 1), GET_MODE (XEXP (x, 1)),
4566 << exact_log2 (GET_MODE_BITSIZE (GET_MODE (x))))
4578 /* Simplify X, an IF_THEN_ELSE expression. Return the new expression. */
4581 simplify_if_then_else (rtx x)
4583 enum machine_mode mode = GET_MODE (x);
4584 rtx cond = XEXP (x, 0);
4585 rtx true_rtx = XEXP (x, 1);
4586 rtx false_rtx = XEXP (x, 2);
4587 enum rtx_code true_code = GET_CODE (cond);
4588 int comparison_p = COMPARISON_P (cond);
4591 enum rtx_code false_code;
4594 /* Simplify storing of the truth value. */
4595 if (comparison_p && true_rtx == const_true_rtx && false_rtx == const0_rtx)
4596 return simplify_gen_relational (true_code, mode, VOIDmode,
4597 XEXP (cond, 0), XEXP (cond, 1));
4599 /* Also when the truth value has to be reversed. */
4601 && true_rtx == const0_rtx && false_rtx == const_true_rtx
4602 && (reversed = reversed_comparison (cond, mode)))
4605 /* Sometimes we can simplify the arm of an IF_THEN_ELSE if a register used
4606 in it is being compared against certain values. Get the true and false
4607 comparisons and see if that says anything about the value of each arm. */
4610 && ((false_code = reversed_comparison_code (cond, NULL))
4612 && REG_P (XEXP (cond, 0)))
4615 rtx from = XEXP (cond, 0);
4616 rtx true_val = XEXP (cond, 1);
4617 rtx false_val = true_val;
4620 /* If FALSE_CODE is EQ, swap the codes and arms. */
4622 if (false_code == EQ)
4624 swapped = 1, true_code = EQ, false_code = NE;
4625 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4628 /* If we are comparing against zero and the expression being tested has
4629 only a single bit that might be nonzero, that is its value when it is
4630 not equal to zero. Similarly if it is known to be -1 or 0. */
4632 if (true_code == EQ && true_val == const0_rtx
4633 && exact_log2 (nzb = nonzero_bits (from, GET_MODE (from))) >= 0)
4634 false_code = EQ, false_val = GEN_INT (nzb);
4635 else if (true_code == EQ && true_val == const0_rtx
4636 && (num_sign_bit_copies (from, GET_MODE (from))
4637 == GET_MODE_BITSIZE (GET_MODE (from))))
4638 false_code = EQ, false_val = constm1_rtx;
4640 /* Now simplify an arm if we know the value of the register in the
4641 branch and it is used in the arm. Be careful due to the potential
4642 of locally-shared RTL. */
4644 if (reg_mentioned_p (from, true_rtx))
4645 true_rtx = subst (known_cond (copy_rtx (true_rtx), true_code,
4647 pc_rtx, pc_rtx, 0, 0);
4648 if (reg_mentioned_p (from, false_rtx))
4649 false_rtx = subst (known_cond (copy_rtx (false_rtx), false_code,
4651 pc_rtx, pc_rtx, 0, 0);
4653 SUBST (XEXP (x, 1), swapped ? false_rtx : true_rtx);
4654 SUBST (XEXP (x, 2), swapped ? true_rtx : false_rtx);
4656 true_rtx = XEXP (x, 1);
4657 false_rtx = XEXP (x, 2);
4658 true_code = GET_CODE (cond);
4661 /* If we have (if_then_else FOO (pc) (label_ref BAR)) and FOO can be
4662 reversed, do so to avoid needing two sets of patterns for
4663 subtract-and-branch insns. Similarly if we have a constant in the true
4664 arm, the false arm is the same as the first operand of the comparison, or
4665 the false arm is more complicated than the true arm. */
4668 && reversed_comparison_code (cond, NULL) != UNKNOWN
4669 && (true_rtx == pc_rtx
4670 || (CONSTANT_P (true_rtx)
4671 && GET_CODE (false_rtx) != CONST_INT && false_rtx != pc_rtx)
4672 || true_rtx == const0_rtx
4673 || (OBJECT_P (true_rtx) && !OBJECT_P (false_rtx))
4674 || (GET_CODE (true_rtx) == SUBREG && OBJECT_P (SUBREG_REG (true_rtx))
4675 && !OBJECT_P (false_rtx))
4676 || reg_mentioned_p (true_rtx, false_rtx)
4677 || rtx_equal_p (false_rtx, XEXP (cond, 0))))
4679 true_code = reversed_comparison_code (cond, NULL);
4680 SUBST (XEXP (x, 0), reversed_comparison (cond, GET_MODE (cond)));
4681 SUBST (XEXP (x, 1), false_rtx);
4682 SUBST (XEXP (x, 2), true_rtx);
4684 temp = true_rtx, true_rtx = false_rtx, false_rtx = temp;
4687 /* It is possible that the conditional has been simplified out. */
4688 true_code = GET_CODE (cond);
4689 comparison_p = COMPARISON_P (cond);
4692 /* If the two arms are identical, we don't need the comparison. */
4694 if (rtx_equal_p (true_rtx, false_rtx) && ! side_effects_p (cond))
4697 /* Convert a == b ? b : a to "a". */
4698 if (true_code == EQ && ! side_effects_p (cond)
4699 && !HONOR_NANS (mode)
4700 && rtx_equal_p (XEXP (cond, 0), false_rtx)
4701 && rtx_equal_p (XEXP (cond, 1), true_rtx))
4703 else if (true_code == NE && ! side_effects_p (cond)
4704 && !HONOR_NANS (mode)
4705 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4706 && rtx_equal_p (XEXP (cond, 1), false_rtx))
4709 /* Look for cases where we have (abs x) or (neg (abs X)). */
4711 if (GET_MODE_CLASS (mode) == MODE_INT
4712 && GET_CODE (false_rtx) == NEG
4713 && rtx_equal_p (true_rtx, XEXP (false_rtx, 0))
4715 && rtx_equal_p (true_rtx, XEXP (cond, 0))
4716 && ! side_effects_p (true_rtx))
4721 return simplify_gen_unary (ABS, mode, true_rtx, mode);
4725 simplify_gen_unary (NEG, mode,
4726 simplify_gen_unary (ABS, mode, true_rtx, mode),
4732 /* Look for MIN or MAX. */
4734 if ((! FLOAT_MODE_P (mode) || flag_unsafe_math_optimizations)
4736 && rtx_equal_p (XEXP (cond, 0), true_rtx)
4737 && rtx_equal_p (XEXP (cond, 1), false_rtx)
4738 && ! side_effects_p (cond))
4743 return simplify_gen_binary (SMAX, mode, true_rtx, false_rtx);
4746 return simplify_gen_binary (SMIN, mode, true_rtx, false_rtx);
4749 return simplify_gen_binary (UMAX, mode, true_rtx, false_rtx);
4752 return simplify_gen_binary (UMIN, mode, true_rtx, false_rtx);
4757 /* If we have (if_then_else COND (OP Z C1) Z) and OP is an identity when its
4758 second operand is zero, this can be done as (OP Z (mult COND C2)) where
4759 C2 = C1 * STORE_FLAG_VALUE. Similarly if OP has an outer ZERO_EXTEND or
4760 SIGN_EXTEND as long as Z is already extended (so we don't destroy it).
4761 We can do this kind of thing in some cases when STORE_FLAG_VALUE is
4762 neither 1 or -1, but it isn't worth checking for. */
4764 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
4766 && GET_MODE_CLASS (mode) == MODE_INT
4767 && ! side_effects_p (x))
4769 rtx t = make_compound_operation (true_rtx, SET);
4770 rtx f = make_compound_operation (false_rtx, SET);
4771 rtx cond_op0 = XEXP (cond, 0);
4772 rtx cond_op1 = XEXP (cond, 1);
4773 enum rtx_code op = UNKNOWN, extend_op = UNKNOWN;
4774 enum machine_mode m = mode;
4775 rtx z = 0, c1 = NULL_RTX;
4777 if ((GET_CODE (t) == PLUS || GET_CODE (t) == MINUS
4778 || GET_CODE (t) == IOR || GET_CODE (t) == XOR
4779 || GET_CODE (t) == ASHIFT
4780 || GET_CODE (t) == LSHIFTRT || GET_CODE (t) == ASHIFTRT)
4781 && rtx_equal_p (XEXP (t, 0), f))
4782 c1 = XEXP (t, 1), op = GET_CODE (t), z = f;
4784 /* If an identity-zero op is commutative, check whether there
4785 would be a match if we swapped the operands. */
4786 else if ((GET_CODE (t) == PLUS || GET_CODE (t) == IOR
4787 || GET_CODE (t) == XOR)
4788 && rtx_equal_p (XEXP (t, 1), f))
4789 c1 = XEXP (t, 0), op = GET_CODE (t), z = f;
4790 else if (GET_CODE (t) == SIGN_EXTEND
4791 && (GET_CODE (XEXP (t, 0)) == PLUS
4792 || GET_CODE (XEXP (t, 0)) == MINUS
4793 || GET_CODE (XEXP (t, 0)) == IOR
4794 || GET_CODE (XEXP (t, 0)) == XOR
4795 || GET_CODE (XEXP (t, 0)) == ASHIFT
4796 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4797 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4798 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4799 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4800 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4801 && (num_sign_bit_copies (f, GET_MODE (f))
4803 (GET_MODE_BITSIZE (mode)
4804 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 0))))))
4806 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4807 extend_op = SIGN_EXTEND;
4808 m = GET_MODE (XEXP (t, 0));
4810 else if (GET_CODE (t) == SIGN_EXTEND
4811 && (GET_CODE (XEXP (t, 0)) == PLUS
4812 || GET_CODE (XEXP (t, 0)) == IOR
4813 || GET_CODE (XEXP (t, 0)) == XOR)
4814 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4815 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4816 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4817 && (num_sign_bit_copies (f, GET_MODE (f))
4819 (GET_MODE_BITSIZE (mode)
4820 - GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (t, 0), 1))))))
4822 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4823 extend_op = SIGN_EXTEND;
4824 m = GET_MODE (XEXP (t, 0));
4826 else if (GET_CODE (t) == ZERO_EXTEND
4827 && (GET_CODE (XEXP (t, 0)) == PLUS
4828 || GET_CODE (XEXP (t, 0)) == MINUS
4829 || GET_CODE (XEXP (t, 0)) == IOR
4830 || GET_CODE (XEXP (t, 0)) == XOR
4831 || GET_CODE (XEXP (t, 0)) == ASHIFT
4832 || GET_CODE (XEXP (t, 0)) == LSHIFTRT
4833 || GET_CODE (XEXP (t, 0)) == ASHIFTRT)
4834 && GET_CODE (XEXP (XEXP (t, 0), 0)) == SUBREG
4835 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4836 && subreg_lowpart_p (XEXP (XEXP (t, 0), 0))
4837 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 0)), f)
4838 && ((nonzero_bits (f, GET_MODE (f))
4839 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 0))))
4842 c1 = XEXP (XEXP (t, 0), 1); z = f; op = GET_CODE (XEXP (t, 0));
4843 extend_op = ZERO_EXTEND;
4844 m = GET_MODE (XEXP (t, 0));
4846 else if (GET_CODE (t) == ZERO_EXTEND
4847 && (GET_CODE (XEXP (t, 0)) == PLUS
4848 || GET_CODE (XEXP (t, 0)) == IOR
4849 || GET_CODE (XEXP (t, 0)) == XOR)
4850 && GET_CODE (XEXP (XEXP (t, 0), 1)) == SUBREG
4851 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
4852 && subreg_lowpart_p (XEXP (XEXP (t, 0), 1))
4853 && rtx_equal_p (SUBREG_REG (XEXP (XEXP (t, 0), 1)), f)
4854 && ((nonzero_bits (f, GET_MODE (f))
4855 & ~GET_MODE_MASK (GET_MODE (XEXP (XEXP (t, 0), 1))))
4858 c1 = XEXP (XEXP (t, 0), 0); z = f; op = GET_CODE (XEXP (t, 0));
4859 extend_op = ZERO_EXTEND;
4860 m = GET_MODE (XEXP (t, 0));
4865 temp = subst (simplify_gen_relational (true_code, m, VOIDmode,
4866 cond_op0, cond_op1),
4867 pc_rtx, pc_rtx, 0, 0);
4868 temp = simplify_gen_binary (MULT, m, temp,
4869 simplify_gen_binary (MULT, m, c1,
4871 temp = subst (temp, pc_rtx, pc_rtx, 0, 0);
4872 temp = simplify_gen_binary (op, m, gen_lowpart (m, z), temp);
4874 if (extend_op != UNKNOWN)
4875 temp = simplify_gen_unary (extend_op, mode, temp, m);
4881 /* If we have (if_then_else (ne A 0) C1 0) and either A is known to be 0 or
4882 1 and C1 is a single bit or A is known to be 0 or -1 and C1 is the
4883 negation of a single bit, we can convert this operation to a shift. We
4884 can actually do this more generally, but it doesn't seem worth it. */
4886 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4887 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4888 && ((1 == nonzero_bits (XEXP (cond, 0), mode)
4889 && (i = exact_log2 (INTVAL (true_rtx))) >= 0)
4890 || ((num_sign_bit_copies (XEXP (cond, 0), mode)
4891 == GET_MODE_BITSIZE (mode))
4892 && (i = exact_log2 (-INTVAL (true_rtx))) >= 0)))
4894 simplify_shift_const (NULL_RTX, ASHIFT, mode,
4895 gen_lowpart (mode, XEXP (cond, 0)), i);
4897 /* (IF_THEN_ELSE (NE REG 0) (0) (8)) is REG for nonzero_bits (REG) == 8. */
4898 if (true_code == NE && XEXP (cond, 1) == const0_rtx
4899 && false_rtx == const0_rtx && GET_CODE (true_rtx) == CONST_INT
4900 && GET_MODE (XEXP (cond, 0)) == mode
4901 && (INTVAL (true_rtx) & GET_MODE_MASK (mode))
4902 == nonzero_bits (XEXP (cond, 0), mode)
4903 && (i = exact_log2 (INTVAL (true_rtx) & GET_MODE_MASK (mode))) >= 0)
4904 return XEXP (cond, 0);
4909 /* Simplify X, a SET expression. Return the new expression. */
4912 simplify_set (rtx x)
4914 rtx src = SET_SRC (x);
4915 rtx dest = SET_DEST (x);
4916 enum machine_mode mode
4917 = GET_MODE (src) != VOIDmode ? GET_MODE (src) : GET_MODE (dest);
4921 /* (set (pc) (return)) gets written as (return). */
4922 if (GET_CODE (dest) == PC && GET_CODE (src) == RETURN)
4925 /* Now that we know for sure which bits of SRC we are using, see if we can
4926 simplify the expression for the object knowing that we only need the
4929 if (GET_MODE_CLASS (mode) == MODE_INT
4930 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
4932 src = force_to_mode (src, mode, ~(HOST_WIDE_INT) 0, 0);
4933 SUBST (SET_SRC (x), src);
4936 /* If we are setting CC0 or if the source is a COMPARE, look for the use of
4937 the comparison result and try to simplify it unless we already have used
4938 undobuf.other_insn. */
4939 if ((GET_MODE_CLASS (mode) == MODE_CC
4940 || GET_CODE (src) == COMPARE
4942 && (cc_use = find_single_use (dest, subst_insn, &other_insn)) != 0
4943 && (undobuf.other_insn == 0 || other_insn == undobuf.other_insn)
4944 && COMPARISON_P (*cc_use)
4945 && rtx_equal_p (XEXP (*cc_use, 0), dest))
4947 enum rtx_code old_code = GET_CODE (*cc_use);
4948 enum rtx_code new_code;
4950 int other_changed = 0;
4951 enum machine_mode compare_mode = GET_MODE (dest);
4953 if (GET_CODE (src) == COMPARE)
4954 op0 = XEXP (src, 0), op1 = XEXP (src, 1);
4956 op0 = src, op1 = CONST0_RTX (GET_MODE (src));
4958 tmp = simplify_relational_operation (old_code, compare_mode, VOIDmode,
4961 new_code = old_code;
4962 else if (!CONSTANT_P (tmp))
4964 new_code = GET_CODE (tmp);
4965 op0 = XEXP (tmp, 0);
4966 op1 = XEXP (tmp, 1);
4970 rtx pat = PATTERN (other_insn);
4971 undobuf.other_insn = other_insn;
4972 SUBST (*cc_use, tmp);
4974 /* Attempt to simplify CC user. */
4975 if (GET_CODE (pat) == SET)
4977 rtx new = simplify_rtx (SET_SRC (pat));
4978 if (new != NULL_RTX)
4979 SUBST (SET_SRC (pat), new);
4982 /* Convert X into a no-op move. */
4983 SUBST (SET_DEST (x), pc_rtx);
4984 SUBST (SET_SRC (x), pc_rtx);
4988 /* Simplify our comparison, if possible. */
4989 new_code = simplify_comparison (new_code, &op0, &op1);
4991 #ifdef SELECT_CC_MODE
4992 /* If this machine has CC modes other than CCmode, check to see if we
4993 need to use a different CC mode here. */
4994 if (GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC)
4995 compare_mode = GET_MODE (op0);
4997 compare_mode = SELECT_CC_MODE (new_code, op0, op1);
5000 /* If the mode changed, we have to change SET_DEST, the mode in the
5001 compare, and the mode in the place SET_DEST is used. If SET_DEST is
5002 a hard register, just build new versions with the proper mode. If it
5003 is a pseudo, we lose unless it is only time we set the pseudo, in
5004 which case we can safely change its mode. */
5005 if (compare_mode != GET_MODE (dest))
5007 if (can_change_dest_mode (dest, 0, compare_mode))
5009 unsigned int regno = REGNO (dest);
5010 rtx new_dest = gen_rtx_REG (compare_mode, regno);
5012 if (regno >= FIRST_PSEUDO_REGISTER)
5013 SUBST (regno_reg_rtx[regno], new_dest);
5015 SUBST (SET_DEST (x), new_dest);
5016 SUBST (XEXP (*cc_use, 0), new_dest);
5023 #endif /* SELECT_CC_MODE */
5025 /* If the code changed, we have to build a new comparison in
5026 undobuf.other_insn. */
5027 if (new_code != old_code)
5029 int other_changed_previously = other_changed;
5030 unsigned HOST_WIDE_INT mask;
5032 SUBST (*cc_use, gen_rtx_fmt_ee (new_code, GET_MODE (*cc_use),
5036 /* If the only change we made was to change an EQ into an NE or
5037 vice versa, OP0 has only one bit that might be nonzero, and OP1
5038 is zero, check if changing the user of the condition code will
5039 produce a valid insn. If it won't, we can keep the original code
5040 in that insn by surrounding our operation with an XOR. */
5042 if (((old_code == NE && new_code == EQ)
5043 || (old_code == EQ && new_code == NE))
5044 && ! other_changed_previously && op1 == const0_rtx
5045 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
5046 && exact_log2 (mask = nonzero_bits (op0, GET_MODE (op0))) >= 0)
5048 rtx pat = PATTERN (other_insn), note = 0;
5050 if ((recog_for_combine (&pat, other_insn, ¬e) < 0
5051 && ! check_asm_operands (pat)))
5053 PUT_CODE (*cc_use, old_code);
5056 op0 = simplify_gen_binary (XOR, GET_MODE (op0),
5057 op0, GEN_INT (mask));
5063 undobuf.other_insn = other_insn;
5066 /* If we are now comparing against zero, change our source if
5067 needed. If we do not use cc0, we always have a COMPARE. */
5068 if (op1 == const0_rtx && dest == cc0_rtx)
5070 SUBST (SET_SRC (x), op0);
5076 /* Otherwise, if we didn't previously have a COMPARE in the
5077 correct mode, we need one. */
5078 if (GET_CODE (src) != COMPARE || GET_MODE (src) != compare_mode)
5080 SUBST (SET_SRC (x), gen_rtx_COMPARE (compare_mode, op0, op1));
5083 else if (GET_MODE (op0) == compare_mode && op1 == const0_rtx)
5085 SUBST(SET_SRC (x), op0);
5090 /* Otherwise, update the COMPARE if needed. */
5091 SUBST (XEXP (src, 0), op0);
5092 SUBST (XEXP (src, 1), op1);
5097 /* Get SET_SRC in a form where we have placed back any
5098 compound expressions. Then do the checks below. */
5099 src = make_compound_operation (src, SET);
5100 SUBST (SET_SRC (x), src);
5103 /* If we have (set x (subreg:m1 (op:m2 ...) 0)) with OP being some operation,
5104 and X being a REG or (subreg (reg)), we may be able to convert this to
5105 (set (subreg:m2 x) (op)).
5107 We can always do this if M1 is narrower than M2 because that means that
5108 we only care about the low bits of the result.
5110 However, on machines without WORD_REGISTER_OPERATIONS defined, we cannot
5111 perform a narrower operation than requested since the high-order bits will
5112 be undefined. On machine where it is defined, this transformation is safe
5113 as long as M1 and M2 have the same number of words. */
5115 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5116 && !OBJECT_P (SUBREG_REG (src))
5117 && (((GET_MODE_SIZE (GET_MODE (src)) + (UNITS_PER_WORD - 1))
5119 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (src)))
5120 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))
5121 #ifndef WORD_REGISTER_OPERATIONS
5122 && (GET_MODE_SIZE (GET_MODE (src))
5123 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5125 #ifdef CANNOT_CHANGE_MODE_CLASS
5126 && ! (REG_P (dest) && REGNO (dest) < FIRST_PSEUDO_REGISTER
5127 && REG_CANNOT_CHANGE_MODE_P (REGNO (dest),
5128 GET_MODE (SUBREG_REG (src)),
5132 || (GET_CODE (dest) == SUBREG
5133 && REG_P (SUBREG_REG (dest)))))
5135 SUBST (SET_DEST (x),
5136 gen_lowpart (GET_MODE (SUBREG_REG (src)),
5138 SUBST (SET_SRC (x), SUBREG_REG (src));
5140 src = SET_SRC (x), dest = SET_DEST (x);
5144 /* If we have (set (cc0) (subreg ...)), we try to remove the subreg
5147 && GET_CODE (src) == SUBREG
5148 && subreg_lowpart_p (src)
5149 && (GET_MODE_BITSIZE (GET_MODE (src))
5150 < GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (src)))))
5152 rtx inner = SUBREG_REG (src);
5153 enum machine_mode inner_mode = GET_MODE (inner);
5155 /* Here we make sure that we don't have a sign bit on. */
5156 if (GET_MODE_BITSIZE (inner_mode) <= HOST_BITS_PER_WIDE_INT
5157 && (nonzero_bits (inner, inner_mode)
5158 < ((unsigned HOST_WIDE_INT) 1
5159 << (GET_MODE_BITSIZE (GET_MODE (src)) - 1))))
5161 SUBST (SET_SRC (x), inner);
5167 #ifdef LOAD_EXTEND_OP
5168 /* If we have (set FOO (subreg:M (mem:N BAR) 0)) with M wider than N, this
5169 would require a paradoxical subreg. Replace the subreg with a
5170 zero_extend to avoid the reload that would otherwise be required. */
5172 if (GET_CODE (src) == SUBREG && subreg_lowpart_p (src)
5173 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))) != UNKNOWN
5174 && SUBREG_BYTE (src) == 0
5175 && (GET_MODE_SIZE (GET_MODE (src))
5176 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (src))))
5177 && MEM_P (SUBREG_REG (src)))
5180 gen_rtx_fmt_e (LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (src))),
5181 GET_MODE (src), SUBREG_REG (src)));
5187 /* If we don't have a conditional move, SET_SRC is an IF_THEN_ELSE, and we
5188 are comparing an item known to be 0 or -1 against 0, use a logical
5189 operation instead. Check for one of the arms being an IOR of the other
5190 arm with some value. We compute three terms to be IOR'ed together. In
5191 practice, at most two will be nonzero. Then we do the IOR's. */
5193 if (GET_CODE (dest) != PC
5194 && GET_CODE (src) == IF_THEN_ELSE
5195 && GET_MODE_CLASS (GET_MODE (src)) == MODE_INT
5196 && (GET_CODE (XEXP (src, 0)) == EQ || GET_CODE (XEXP (src, 0)) == NE)
5197 && XEXP (XEXP (src, 0), 1) == const0_rtx
5198 && GET_MODE (src) == GET_MODE (XEXP (XEXP (src, 0), 0))
5199 #ifdef HAVE_conditional_move
5200 && ! can_conditionally_move_p (GET_MODE (src))
5202 && (num_sign_bit_copies (XEXP (XEXP (src, 0), 0),
5203 GET_MODE (XEXP (XEXP (src, 0), 0)))
5204 == GET_MODE_BITSIZE (GET_MODE (XEXP (XEXP (src, 0), 0))))
5205 && ! side_effects_p (src))
5207 rtx true_rtx = (GET_CODE (XEXP (src, 0)) == NE
5208 ? XEXP (src, 1) : XEXP (src, 2));
5209 rtx false_rtx = (GET_CODE (XEXP (src, 0)) == NE
5210 ? XEXP (src, 2) : XEXP (src, 1));
5211 rtx term1 = const0_rtx, term2, term3;
5213 if (GET_CODE (true_rtx) == IOR
5214 && rtx_equal_p (XEXP (true_rtx, 0), false_rtx))
5215 term1 = false_rtx, true_rtx = XEXP (true_rtx, 1), false_rtx = const0_rtx;
5216 else if (GET_CODE (true_rtx) == IOR
5217 && rtx_equal_p (XEXP (true_rtx, 1), false_rtx))
5218 term1 = false_rtx, true_rtx = XEXP (true_rtx, 0), false_rtx = const0_rtx;
5219 else if (GET_CODE (false_rtx) == IOR
5220 && rtx_equal_p (XEXP (false_rtx, 0), true_rtx))
5221 term1 = true_rtx, false_rtx = XEXP (false_rtx, 1), true_rtx = const0_rtx;
5222 else if (GET_CODE (false_rtx) == IOR
5223 && rtx_equal_p (XEXP (false_rtx, 1), true_rtx))
5224 term1 = true_rtx, false_rtx = XEXP (false_rtx, 0), true_rtx = const0_rtx;
5226 term2 = simplify_gen_binary (AND, GET_MODE (src),
5227 XEXP (XEXP (src, 0), 0), true_rtx);
5228 term3 = simplify_gen_binary (AND, GET_MODE (src),
5229 simplify_gen_unary (NOT, GET_MODE (src),
5230 XEXP (XEXP (src, 0), 0),
5235 simplify_gen_binary (IOR, GET_MODE (src),
5236 simplify_gen_binary (IOR, GET_MODE (src),
5243 /* If either SRC or DEST is a CLOBBER of (const_int 0), make this
5244 whole thing fail. */
5245 if (GET_CODE (src) == CLOBBER && XEXP (src, 0) == const0_rtx)
5247 else if (GET_CODE (dest) == CLOBBER && XEXP (dest, 0) == const0_rtx)
5250 /* Convert this into a field assignment operation, if possible. */
5251 return make_field_assignment (x);
5254 /* Simplify, X, and AND, IOR, or XOR operation, and return the simplified
5258 simplify_logical (rtx x)
5260 enum machine_mode mode = GET_MODE (x);
5261 rtx op0 = XEXP (x, 0);
5262 rtx op1 = XEXP (x, 1);
5264 switch (GET_CODE (x))
5267 /* We can call simplify_and_const_int only if we don't lose
5268 any (sign) bits when converting INTVAL (op1) to
5269 "unsigned HOST_WIDE_INT". */
5270 if (GET_CODE (op1) == CONST_INT
5271 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
5272 || INTVAL (op1) > 0))
5274 x = simplify_and_const_int (x, mode, op0, INTVAL (op1));
5275 if (GET_CODE (x) != AND)
5282 /* If we have any of (and (ior A B) C) or (and (xor A B) C),
5283 apply the distributive law and then the inverse distributive
5284 law to see if things simplify. */
5285 if (GET_CODE (op0) == IOR || GET_CODE (op0) == XOR)
5287 rtx result = distribute_and_simplify_rtx (x, 0);
5291 if (GET_CODE (op1) == IOR || GET_CODE (op1) == XOR)
5293 rtx result = distribute_and_simplify_rtx (x, 1);
5300 /* If we have (ior (and A B) C), apply the distributive law and then
5301 the inverse distributive law to see if things simplify. */
5303 if (GET_CODE (op0) == AND)
5305 rtx result = distribute_and_simplify_rtx (x, 0);
5310 if (GET_CODE (op1) == AND)
5312 rtx result = distribute_and_simplify_rtx (x, 1);
5325 /* We consider ZERO_EXTRACT, SIGN_EXTRACT, and SIGN_EXTEND as "compound
5326 operations" because they can be replaced with two more basic operations.
5327 ZERO_EXTEND is also considered "compound" because it can be replaced with
5328 an AND operation, which is simpler, though only one operation.
5330 The function expand_compound_operation is called with an rtx expression
5331 and will convert it to the appropriate shifts and AND operations,
5332 simplifying at each stage.
5334 The function make_compound_operation is called to convert an expression
5335 consisting of shifts and ANDs into the equivalent compound expression.
5336 It is the inverse of this function, loosely speaking. */
5339 expand_compound_operation (rtx x)
5341 unsigned HOST_WIDE_INT pos = 0, len;
5343 unsigned int modewidth;
5346 switch (GET_CODE (x))
5351 /* We can't necessarily use a const_int for a multiword mode;
5352 it depends on implicitly extending the value.
5353 Since we don't know the right way to extend it,
5354 we can't tell whether the implicit way is right.
5356 Even for a mode that is no wider than a const_int,
5357 we can't win, because we need to sign extend one of its bits through
5358 the rest of it, and we don't know which bit. */
5359 if (GET_CODE (XEXP (x, 0)) == CONST_INT)
5362 /* Return if (subreg:MODE FROM 0) is not a safe replacement for
5363 (zero_extend:MODE FROM) or (sign_extend:MODE FROM). It is for any MEM
5364 because (SUBREG (MEM...)) is guaranteed to cause the MEM to be
5365 reloaded. If not for that, MEM's would very rarely be safe.
5367 Reject MODEs bigger than a word, because we might not be able
5368 to reference a two-register group starting with an arbitrary register
5369 (and currently gen_lowpart might crash for a SUBREG). */
5371 if (GET_MODE_SIZE (GET_MODE (XEXP (x, 0))) > UNITS_PER_WORD)
5374 /* Reject MODEs that aren't scalar integers because turning vector
5375 or complex modes into shifts causes problems. */
5377 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5380 len = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)));
5381 /* If the inner object has VOIDmode (the only way this can happen
5382 is if it is an ASM_OPERANDS), we can't do anything since we don't
5383 know how much masking to do. */
5392 /* ... fall through ... */
5395 /* If the operand is a CLOBBER, just return it. */
5396 if (GET_CODE (XEXP (x, 0)) == CLOBBER)
5399 if (GET_CODE (XEXP (x, 1)) != CONST_INT
5400 || GET_CODE (XEXP (x, 2)) != CONST_INT
5401 || GET_MODE (XEXP (x, 0)) == VOIDmode)
5404 /* Reject MODEs that aren't scalar integers because turning vector
5405 or complex modes into shifts causes problems. */
5407 if (! SCALAR_INT_MODE_P (GET_MODE (XEXP (x, 0))))
5410 len = INTVAL (XEXP (x, 1));
5411 pos = INTVAL (XEXP (x, 2));
5413 /* If this goes outside the object being extracted, replace the object
5414 with a (use (mem ...)) construct that only combine understands
5415 and is used only for this purpose. */
5416 if (len + pos > GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))))
5417 SUBST (XEXP (x, 0), gen_rtx_USE (GET_MODE (x), XEXP (x, 0)));
5419 if (BITS_BIG_ENDIAN)
5420 pos = GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0))) - len - pos;
5427 /* Convert sign extension to zero extension, if we know that the high
5428 bit is not set, as this is easier to optimize. It will be converted
5429 back to cheaper alternative in make_extraction. */
5430 if (GET_CODE (x) == SIGN_EXTEND
5431 && (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5432 && ((nonzero_bits (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
5433 & ~(((unsigned HOST_WIDE_INT)
5434 GET_MODE_MASK (GET_MODE (XEXP (x, 0))))
5438 rtx temp = gen_rtx_ZERO_EXTEND (GET_MODE (x), XEXP (x, 0));
5439 rtx temp2 = expand_compound_operation (temp);
5441 /* Make sure this is a profitable operation. */
5442 if (rtx_cost (x, SET) > rtx_cost (temp2, SET))
5444 else if (rtx_cost (x, SET) > rtx_cost (temp, SET))
5450 /* We can optimize some special cases of ZERO_EXTEND. */
5451 if (GET_CODE (x) == ZERO_EXTEND)
5453 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI if we
5454 know that the last value didn't have any inappropriate bits
5456 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5457 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5458 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5459 && (nonzero_bits (XEXP (XEXP (x, 0), 0), GET_MODE (x))
5460 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5461 return XEXP (XEXP (x, 0), 0);
5463 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5464 if (GET_CODE (XEXP (x, 0)) == SUBREG
5465 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5466 && subreg_lowpart_p (XEXP (x, 0))
5467 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
5468 && (nonzero_bits (SUBREG_REG (XEXP (x, 0)), GET_MODE (x))
5469 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5470 return SUBREG_REG (XEXP (x, 0));
5472 /* (zero_extend:DI (truncate:SI foo:DI)) is just foo:DI when foo
5473 is a comparison and STORE_FLAG_VALUE permits. This is like
5474 the first case, but it works even when GET_MODE (x) is larger
5475 than HOST_WIDE_INT. */
5476 if (GET_CODE (XEXP (x, 0)) == TRUNCATE
5477 && GET_MODE (XEXP (XEXP (x, 0), 0)) == GET_MODE (x)
5478 && COMPARISON_P (XEXP (XEXP (x, 0), 0))
5479 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5480 <= HOST_BITS_PER_WIDE_INT)
5481 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5482 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5483 return XEXP (XEXP (x, 0), 0);
5485 /* Likewise for (zero_extend:DI (subreg:SI foo:DI 0)). */
5486 if (GET_CODE (XEXP (x, 0)) == SUBREG
5487 && GET_MODE (SUBREG_REG (XEXP (x, 0))) == GET_MODE (x)
5488 && subreg_lowpart_p (XEXP (x, 0))
5489 && COMPARISON_P (SUBREG_REG (XEXP (x, 0)))
5490 && (GET_MODE_BITSIZE (GET_MODE (XEXP (x, 0)))
5491 <= HOST_BITS_PER_WIDE_INT)
5492 && ((HOST_WIDE_INT) STORE_FLAG_VALUE
5493 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
5494 return SUBREG_REG (XEXP (x, 0));
5498 /* If we reach here, we want to return a pair of shifts. The inner
5499 shift is a left shift of BITSIZE - POS - LEN bits. The outer
5500 shift is a right shift of BITSIZE - LEN bits. It is arithmetic or
5501 logical depending on the value of UNSIGNEDP.
5503 If this was a ZERO_EXTEND or ZERO_EXTRACT, this pair of shifts will be
5504 converted into an AND of a shift.
5506 We must check for the case where the left shift would have a negative
5507 count. This can happen in a case like (x >> 31) & 255 on machines
5508 that can't shift by a constant. On those machines, we would first
5509 combine the shift with the AND to produce a variable-position
5510 extraction. Then the constant of 31 would be substituted in to produce
5511 a such a position. */
5513 modewidth = GET_MODE_BITSIZE (GET_MODE (x));
5514 if (modewidth + len >= pos)
5515 tem = simplify_shift_const (NULL_RTX, unsignedp ? LSHIFTRT : ASHIFTRT,
5517 simplify_shift_const (NULL_RTX, ASHIFT,
5520 modewidth - pos - len),
5523 else if (unsignedp && len < HOST_BITS_PER_WIDE_INT)
5524 tem = simplify_and_const_int (NULL_RTX, GET_MODE (x),
5525 simplify_shift_const (NULL_RTX, LSHIFTRT,
5528 ((HOST_WIDE_INT) 1 << len) - 1);
5530 /* Any other cases we can't handle. */
5533 /* If we couldn't do this for some reason, return the original
5535 if (GET_CODE (tem) == CLOBBER)
5541 /* X is a SET which contains an assignment of one object into
5542 a part of another (such as a bit-field assignment, STRICT_LOW_PART,
5543 or certain SUBREGS). If possible, convert it into a series of
5546 We half-heartedly support variable positions, but do not at all
5547 support variable lengths. */
5550 expand_field_assignment (rtx x)
5553 rtx pos; /* Always counts from low bit. */
5555 rtx mask, cleared, masked;
5556 enum machine_mode compute_mode;
5558 /* Loop until we find something we can't simplify. */
5561 if (GET_CODE (SET_DEST (x)) == STRICT_LOW_PART
5562 && GET_CODE (XEXP (SET_DEST (x), 0)) == SUBREG)
5564 inner = SUBREG_REG (XEXP (SET_DEST (x), 0));
5565 len = GET_MODE_BITSIZE (GET_MODE (XEXP (SET_DEST (x), 0)));
5566 pos = GEN_INT (subreg_lsb (XEXP (SET_DEST (x), 0)));
5568 else if (GET_CODE (SET_DEST (x)) == ZERO_EXTRACT
5569 && GET_CODE (XEXP (SET_DEST (x), 1)) == CONST_INT)
5571 inner = XEXP (SET_DEST (x), 0);
5572 len = INTVAL (XEXP (SET_DEST (x), 1));
5573 pos = XEXP (SET_DEST (x), 2);
5575 /* If the position is constant and spans the width of INNER,
5576 surround INNER with a USE to indicate this. */
5577 if (GET_CODE (pos) == CONST_INT
5578 && INTVAL (pos) + len > GET_MODE_BITSIZE (GET_MODE (inner)))
5579 inner = gen_rtx_USE (GET_MODE (SET_DEST (x)), inner);
5581 if (BITS_BIG_ENDIAN)
5583 if (GET_CODE (pos) == CONST_INT)
5584 pos = GEN_INT (GET_MODE_BITSIZE (GET_MODE (inner)) - len
5586 else if (GET_CODE (pos) == MINUS
5587 && GET_CODE (XEXP (pos, 1)) == CONST_INT
5588 && (INTVAL (XEXP (pos, 1))
5589 == GET_MODE_BITSIZE (GET_MODE (inner)) - len))
5590 /* If position is ADJUST - X, new position is X. */
5591 pos = XEXP (pos, 0);
5593 pos = simplify_gen_binary (MINUS, GET_MODE (pos),
5594 GEN_INT (GET_MODE_BITSIZE (
5601 /* A SUBREG between two modes that occupy the same numbers of words
5602 can be done by moving the SUBREG to the source. */
5603 else if (GET_CODE (SET_DEST (x)) == SUBREG
5604 /* We need SUBREGs to compute nonzero_bits properly. */
5605 && nonzero_sign_valid
5606 && (((GET_MODE_SIZE (GET_MODE (SET_DEST (x)))
5607 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
5608 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (x))))
5609 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)))
5611 x = gen_rtx_SET (VOIDmode, SUBREG_REG (SET_DEST (x)),
5613 (GET_MODE (SUBREG_REG (SET_DEST (x))),
5620 while (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5621 inner = SUBREG_REG (inner);
5623 compute_mode = GET_MODE (inner);
5625 /* Don't attempt bitwise arithmetic on non scalar integer modes. */
5626 if (! SCALAR_INT_MODE_P (compute_mode))
5628 enum machine_mode imode;
5630 /* Don't do anything for vector or complex integral types. */
5631 if (! FLOAT_MODE_P (compute_mode))
5634 /* Try to find an integral mode to pun with. */
5635 imode = mode_for_size (GET_MODE_BITSIZE (compute_mode), MODE_INT, 0);
5636 if (imode == BLKmode)
5639 compute_mode = imode;
5640 inner = gen_lowpart (imode, inner);
5643 /* Compute a mask of LEN bits, if we can do this on the host machine. */
5644 if (len >= HOST_BITS_PER_WIDE_INT)
5647 /* Now compute the equivalent expression. Make a copy of INNER
5648 for the SET_DEST in case it is a MEM into which we will substitute;
5649 we don't want shared RTL in that case. */
5650 mask = GEN_INT (((HOST_WIDE_INT) 1 << len) - 1);
5651 cleared = simplify_gen_binary (AND, compute_mode,
5652 simplify_gen_unary (NOT, compute_mode,
5653 simplify_gen_binary (ASHIFT,
5658 masked = simplify_gen_binary (ASHIFT, compute_mode,
5659 simplify_gen_binary (
5661 gen_lowpart (compute_mode, SET_SRC (x)),
5665 x = gen_rtx_SET (VOIDmode, copy_rtx (inner),
5666 simplify_gen_binary (IOR, compute_mode,
5673 /* Return an RTX for a reference to LEN bits of INNER. If POS_RTX is nonzero,
5674 it is an RTX that represents a variable starting position; otherwise,
5675 POS is the (constant) starting bit position (counted from the LSB).
5677 INNER may be a USE. This will occur when we started with a bitfield
5678 that went outside the boundary of the object in memory, which is
5679 allowed on most machines. To isolate this case, we produce a USE
5680 whose mode is wide enough and surround the MEM with it. The only
5681 code that understands the USE is this routine. If it is not removed,
5682 it will cause the resulting insn not to match.
5684 UNSIGNEDP is nonzero for an unsigned reference and zero for a
5687 IN_DEST is nonzero if this is a reference in the destination of a
5688 SET. This is used when a ZERO_ or SIGN_EXTRACT isn't needed. If nonzero,
5689 a STRICT_LOW_PART will be used, if zero, ZERO_EXTEND or SIGN_EXTEND will
5692 IN_COMPARE is nonzero if we are in a COMPARE. This means that a
5693 ZERO_EXTRACT should be built even for bits starting at bit 0.
5695 MODE is the desired mode of the result (if IN_DEST == 0).
5697 The result is an RTX for the extraction or NULL_RTX if the target
5701 make_extraction (enum machine_mode mode, rtx inner, HOST_WIDE_INT pos,
5702 rtx pos_rtx, unsigned HOST_WIDE_INT len, int unsignedp,
5703 int in_dest, int in_compare)
5705 /* This mode describes the size of the storage area
5706 to fetch the overall value from. Within that, we
5707 ignore the POS lowest bits, etc. */
5708 enum machine_mode is_mode = GET_MODE (inner);
5709 enum machine_mode inner_mode;
5710 enum machine_mode wanted_inner_mode = byte_mode;
5711 enum machine_mode wanted_inner_reg_mode = word_mode;
5712 enum machine_mode pos_mode = word_mode;
5713 enum machine_mode extraction_mode = word_mode;
5714 enum machine_mode tmode = mode_for_size (len, MODE_INT, 1);
5717 rtx orig_pos_rtx = pos_rtx;
5718 HOST_WIDE_INT orig_pos;
5720 /* Get some information about INNER and get the innermost object. */
5721 if (GET_CODE (inner) == USE)
5722 /* (use:SI (mem:QI foo)) stands for (mem:SI foo). */
5723 /* We don't need to adjust the position because we set up the USE
5724 to pretend that it was a full-word object. */
5725 spans_byte = 1, inner = XEXP (inner, 0);
5726 else if (GET_CODE (inner) == SUBREG && subreg_lowpart_p (inner))
5728 /* If going from (subreg:SI (mem:QI ...)) to (mem:QI ...),
5729 consider just the QI as the memory to extract from.
5730 The subreg adds or removes high bits; its mode is
5731 irrelevant to the meaning of this extraction,
5732 since POS and LEN count from the lsb. */
5733 if (MEM_P (SUBREG_REG (inner)))
5734 is_mode = GET_MODE (SUBREG_REG (inner));
5735 inner = SUBREG_REG (inner);
5737 else if (GET_CODE (inner) == ASHIFT
5738 && GET_CODE (XEXP (inner, 1)) == CONST_INT
5739 && pos_rtx == 0 && pos == 0
5740 && len > (unsigned HOST_WIDE_INT) INTVAL (XEXP (inner, 1)))
5742 /* We're extracting the least significant bits of an rtx
5743 (ashift X (const_int C)), where LEN > C. Extract the
5744 least significant (LEN - C) bits of X, giving an rtx
5745 whose mode is MODE, then shift it left C times. */
5746 new = make_extraction (mode, XEXP (inner, 0),
5747 0, 0, len - INTVAL (XEXP (inner, 1)),
5748 unsignedp, in_dest, in_compare);
5750 return gen_rtx_ASHIFT (mode, new, XEXP (inner, 1));
5753 inner_mode = GET_MODE (inner);
5755 if (pos_rtx && GET_CODE (pos_rtx) == CONST_INT)
5756 pos = INTVAL (pos_rtx), pos_rtx = 0;
5758 /* See if this can be done without an extraction. We never can if the
5759 width of the field is not the same as that of some integer mode. For
5760 registers, we can only avoid the extraction if the position is at the
5761 low-order bit and this is either not in the destination or we have the
5762 appropriate STRICT_LOW_PART operation available.
5764 For MEM, we can avoid an extract if the field starts on an appropriate
5765 boundary and we can change the mode of the memory reference. However,
5766 we cannot directly access the MEM if we have a USE and the underlying
5767 MEM is not TMODE. This combination means that MEM was being used in a
5768 context where bits outside its mode were being referenced; that is only
5769 valid in bit-field insns. */
5771 if (tmode != BLKmode
5772 && ! (spans_byte && inner_mode != tmode)
5773 && ((pos_rtx == 0 && (pos % BITS_PER_WORD) == 0
5777 && have_insn_for (STRICT_LOW_PART, tmode))))
5778 || (MEM_P (inner) && pos_rtx == 0
5780 % (STRICT_ALIGNMENT ? GET_MODE_ALIGNMENT (tmode)
5781 : BITS_PER_UNIT)) == 0
5782 /* We can't do this if we are widening INNER_MODE (it
5783 may not be aligned, for one thing). */
5784 && GET_MODE_BITSIZE (inner_mode) >= GET_MODE_BITSIZE (tmode)
5785 && (inner_mode == tmode
5786 || (! mode_dependent_address_p (XEXP (inner, 0))
5787 && ! MEM_VOLATILE_P (inner))))))
5789 /* If INNER is a MEM, make a new MEM that encompasses just the desired
5790 field. If the original and current mode are the same, we need not
5791 adjust the offset. Otherwise, we do if bytes big endian.
5793 If INNER is not a MEM, get a piece consisting of just the field
5794 of interest (in this case POS % BITS_PER_WORD must be 0). */
5798 HOST_WIDE_INT offset;
5800 /* POS counts from lsb, but make OFFSET count in memory order. */
5801 if (BYTES_BIG_ENDIAN)
5802 offset = (GET_MODE_BITSIZE (is_mode) - len - pos) / BITS_PER_UNIT;
5804 offset = pos / BITS_PER_UNIT;
5806 new = adjust_address_nv (inner, tmode, offset);
5808 else if (REG_P (inner))
5810 if (tmode != inner_mode)
5812 /* We can't call gen_lowpart in a DEST since we
5813 always want a SUBREG (see below) and it would sometimes
5814 return a new hard register. */
5817 HOST_WIDE_INT final_word = pos / BITS_PER_WORD;
5819 if (WORDS_BIG_ENDIAN
5820 && GET_MODE_SIZE (inner_mode) > UNITS_PER_WORD)
5821 final_word = ((GET_MODE_SIZE (inner_mode)
5822 - GET_MODE_SIZE (tmode))
5823 / UNITS_PER_WORD) - final_word;
5825 final_word *= UNITS_PER_WORD;
5826 if (BYTES_BIG_ENDIAN &&
5827 GET_MODE_SIZE (inner_mode) > GET_MODE_SIZE (tmode))
5828 final_word += (GET_MODE_SIZE (inner_mode)
5829 - GET_MODE_SIZE (tmode)) % UNITS_PER_WORD;
5831 /* Avoid creating invalid subregs, for example when
5832 simplifying (x>>32)&255. */
5833 if (!validate_subreg (tmode, inner_mode, inner, final_word))
5836 new = gen_rtx_SUBREG (tmode, inner, final_word);
5839 new = gen_lowpart (tmode, inner);
5845 new = force_to_mode (inner, tmode,
5846 len >= HOST_BITS_PER_WIDE_INT
5847 ? ~(unsigned HOST_WIDE_INT) 0
5848 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
5851 /* If this extraction is going into the destination of a SET,
5852 make a STRICT_LOW_PART unless we made a MEM. */
5855 return (MEM_P (new) ? new
5856 : (GET_CODE (new) != SUBREG
5857 ? gen_rtx_CLOBBER (tmode, const0_rtx)
5858 : gen_rtx_STRICT_LOW_PART (VOIDmode, new)));
5863 if (GET_CODE (new) == CONST_INT)
5864 return gen_int_mode (INTVAL (new), mode);
5866 /* If we know that no extraneous bits are set, and that the high
5867 bit is not set, convert the extraction to the cheaper of
5868 sign and zero extension, that are equivalent in these cases. */
5869 if (flag_expensive_optimizations
5870 && (GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
5871 && ((nonzero_bits (new, tmode)
5872 & ~(((unsigned HOST_WIDE_INT)
5873 GET_MODE_MASK (tmode))
5877 rtx temp = gen_rtx_ZERO_EXTEND (mode, new);
5878 rtx temp1 = gen_rtx_SIGN_EXTEND (mode, new);
5880 /* Prefer ZERO_EXTENSION, since it gives more information to
5882 if (rtx_cost (temp, SET) <= rtx_cost (temp1, SET))
5887 /* Otherwise, sign- or zero-extend unless we already are in the
5890 return (gen_rtx_fmt_e (unsignedp ? ZERO_EXTEND : SIGN_EXTEND,
5894 /* Unless this is a COMPARE or we have a funny memory reference,
5895 don't do anything with zero-extending field extracts starting at
5896 the low-order bit since they are simple AND operations. */
5897 if (pos_rtx == 0 && pos == 0 && ! in_dest
5898 && ! in_compare && ! spans_byte && unsignedp)
5901 /* Unless we are allowed to span bytes or INNER is not MEM, reject this if
5902 we would be spanning bytes or if the position is not a constant and the
5903 length is not 1. In all other cases, we would only be going outside
5904 our object in cases when an original shift would have been
5906 if (! spans_byte && MEM_P (inner)
5907 && ((pos_rtx == 0 && pos + len > GET_MODE_BITSIZE (is_mode))
5908 || (pos_rtx != 0 && len != 1)))
5911 /* Get the mode to use should INNER not be a MEM, the mode for the position,
5912 and the mode for the result. */
5913 if (in_dest && mode_for_extraction (EP_insv, -1) != MAX_MACHINE_MODE)
5915 wanted_inner_reg_mode = mode_for_extraction (EP_insv, 0);
5916 pos_mode = mode_for_extraction (EP_insv, 2);
5917 extraction_mode = mode_for_extraction (EP_insv, 3);
5920 if (! in_dest && unsignedp
5921 && mode_for_extraction (EP_extzv, -1) != MAX_MACHINE_MODE)
5923 wanted_inner_reg_mode = mode_for_extraction (EP_extzv, 1);
5924 pos_mode = mode_for_extraction (EP_extzv, 3);
5925 extraction_mode = mode_for_extraction (EP_extzv, 0);
5928 if (! in_dest && ! unsignedp
5929 && mode_for_extraction (EP_extv, -1) != MAX_MACHINE_MODE)
5931 wanted_inner_reg_mode = mode_for_extraction (EP_extv, 1);
5932 pos_mode = mode_for_extraction (EP_extv, 3);
5933 extraction_mode = mode_for_extraction (EP_extv, 0);
5936 /* Never narrow an object, since that might not be safe. */
5938 if (mode != VOIDmode
5939 && GET_MODE_SIZE (extraction_mode) < GET_MODE_SIZE (mode))
5940 extraction_mode = mode;
5942 if (pos_rtx && GET_MODE (pos_rtx) != VOIDmode
5943 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
5944 pos_mode = GET_MODE (pos_rtx);
5946 /* If this is not from memory, the desired mode is wanted_inner_reg_mode;
5947 if we have to change the mode of memory and cannot, the desired mode is
5950 wanted_inner_mode = wanted_inner_reg_mode;
5951 else if (inner_mode != wanted_inner_mode
5952 && (mode_dependent_address_p (XEXP (inner, 0))
5953 || MEM_VOLATILE_P (inner)))
5954 wanted_inner_mode = extraction_mode;
5958 if (BITS_BIG_ENDIAN)
5960 /* POS is passed as if BITS_BIG_ENDIAN == 0, so we need to convert it to
5961 BITS_BIG_ENDIAN style. If position is constant, compute new
5962 position. Otherwise, build subtraction.
5963 Note that POS is relative to the mode of the original argument.
5964 If it's a MEM we need to recompute POS relative to that.
5965 However, if we're extracting from (or inserting into) a register,
5966 we want to recompute POS relative to wanted_inner_mode. */
5967 int width = (MEM_P (inner)
5968 ? GET_MODE_BITSIZE (is_mode)
5969 : GET_MODE_BITSIZE (wanted_inner_mode));
5972 pos = width - len - pos;
5975 = gen_rtx_MINUS (GET_MODE (pos_rtx), GEN_INT (width - len), pos_rtx);
5976 /* POS may be less than 0 now, but we check for that below.
5977 Note that it can only be less than 0 if !MEM_P (inner). */
5980 /* If INNER has a wider mode, make it smaller. If this is a constant
5981 extract, try to adjust the byte to point to the byte containing
5983 if (wanted_inner_mode != VOIDmode
5984 && GET_MODE_SIZE (wanted_inner_mode) < GET_MODE_SIZE (is_mode)
5986 && (inner_mode == wanted_inner_mode
5987 || (! mode_dependent_address_p (XEXP (inner, 0))
5988 && ! MEM_VOLATILE_P (inner))))))
5992 /* The computations below will be correct if the machine is big
5993 endian in both bits and bytes or little endian in bits and bytes.
5994 If it is mixed, we must adjust. */
5996 /* If bytes are big endian and we had a paradoxical SUBREG, we must
5997 adjust OFFSET to compensate. */
5998 if (BYTES_BIG_ENDIAN
6000 && GET_MODE_SIZE (inner_mode) < GET_MODE_SIZE (is_mode))
6001 offset -= GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (inner_mode);
6003 /* If this is a constant position, we can move to the desired byte.
6004 Be careful not to go beyond the original object and maintain the
6005 natural alignment of the memory. */
6008 enum machine_mode bfmode = smallest_mode_for_size (len, MODE_INT);
6009 offset += (pos / GET_MODE_BITSIZE (bfmode)) * GET_MODE_SIZE (bfmode);
6010 pos %= GET_MODE_BITSIZE (bfmode);
6013 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN
6015 && is_mode != wanted_inner_mode)
6016 offset = (GET_MODE_SIZE (is_mode)
6017 - GET_MODE_SIZE (wanted_inner_mode) - offset);
6019 if (offset != 0 || inner_mode != wanted_inner_mode)
6020 inner = adjust_address_nv (inner, wanted_inner_mode, offset);
6023 /* If INNER is not memory, we can always get it into the proper mode. If we
6024 are changing its mode, POS must be a constant and smaller than the size
6026 else if (!MEM_P (inner))
6028 if (GET_MODE (inner) != wanted_inner_mode
6030 || orig_pos + len > GET_MODE_BITSIZE (wanted_inner_mode)))
6033 inner = force_to_mode (inner, wanted_inner_mode,
6035 || len + orig_pos >= HOST_BITS_PER_WIDE_INT
6036 ? ~(unsigned HOST_WIDE_INT) 0
6037 : ((((unsigned HOST_WIDE_INT) 1 << len) - 1)
6042 /* Adjust mode of POS_RTX, if needed. If we want a wider mode, we
6043 have to zero extend. Otherwise, we can just use a SUBREG. */
6045 && GET_MODE_SIZE (pos_mode) > GET_MODE_SIZE (GET_MODE (pos_rtx)))
6047 rtx temp = gen_rtx_ZERO_EXTEND (pos_mode, pos_rtx);
6049 /* If we know that no extraneous bits are set, and that the high
6050 bit is not set, convert extraction to cheaper one - either
6051 SIGN_EXTENSION or ZERO_EXTENSION, that are equivalent in these
6053 if (flag_expensive_optimizations
6054 && (GET_MODE_BITSIZE (GET_MODE (pos_rtx)) <= HOST_BITS_PER_WIDE_INT
6055 && ((nonzero_bits (pos_rtx, GET_MODE (pos_rtx))
6056 & ~(((unsigned HOST_WIDE_INT)
6057 GET_MODE_MASK (GET_MODE (pos_rtx)))
6061 rtx temp1 = gen_rtx_SIGN_EXTEND (pos_mode, pos_rtx);
6063 /* Prefer ZERO_EXTENSION, since it gives more information to
6065 if (rtx_cost (temp1, SET) < rtx_cost (temp, SET))
6070 else if (pos_rtx != 0
6071 && GET_MODE_SIZE (pos_mode) < GET_MODE_SIZE (GET_MODE (pos_rtx)))
6072 pos_rtx = gen_lowpart (pos_mode, pos_rtx);
6074 /* Make POS_RTX unless we already have it and it is correct. If we don't
6075 have a POS_RTX but we do have an ORIG_POS_RTX, the latter must
6077 if (pos_rtx == 0 && orig_pos_rtx != 0 && INTVAL (orig_pos_rtx) == pos)
6078 pos_rtx = orig_pos_rtx;
6080 else if (pos_rtx == 0)
6081 pos_rtx = GEN_INT (pos);
6083 /* Make the required operation. See if we can use existing rtx. */
6084 new = gen_rtx_fmt_eee (unsignedp ? ZERO_EXTRACT : SIGN_EXTRACT,
6085 extraction_mode, inner, GEN_INT (len), pos_rtx);
6087 new = gen_lowpart (mode, new);
6092 /* See if X contains an ASHIFT of COUNT or more bits that can be commuted
6093 with any other operations in X. Return X without that shift if so. */
6096 extract_left_shift (rtx x, int count)
6098 enum rtx_code code = GET_CODE (x);
6099 enum machine_mode mode = GET_MODE (x);
6105 /* This is the shift itself. If it is wide enough, we will return
6106 either the value being shifted if the shift count is equal to
6107 COUNT or a shift for the difference. */
6108 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6109 && INTVAL (XEXP (x, 1)) >= count)
6110 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (x, 0),
6111 INTVAL (XEXP (x, 1)) - count);
6115 if ((tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6116 return simplify_gen_unary (code, mode, tem, mode);
6120 case PLUS: case IOR: case XOR: case AND:
6121 /* If we can safely shift this constant and we find the inner shift,
6122 make a new operation. */
6123 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6124 && (INTVAL (XEXP (x, 1)) & ((((HOST_WIDE_INT) 1 << count)) - 1)) == 0
6125 && (tem = extract_left_shift (XEXP (x, 0), count)) != 0)
6126 return simplify_gen_binary (code, mode, tem,
6127 GEN_INT (INTVAL (XEXP (x, 1)) >> count));
6138 /* Look at the expression rooted at X. Look for expressions
6139 equivalent to ZERO_EXTRACT, SIGN_EXTRACT, ZERO_EXTEND, SIGN_EXTEND.
6140 Form these expressions.
6142 Return the new rtx, usually just X.
6144 Also, for machines like the VAX that don't have logical shift insns,
6145 try to convert logical to arithmetic shift operations in cases where
6146 they are equivalent. This undoes the canonicalizations to logical
6147 shifts done elsewhere.
6149 We try, as much as possible, to re-use rtl expressions to save memory.
6151 IN_CODE says what kind of expression we are processing. Normally, it is
6152 SET. In a memory address (inside a MEM, PLUS or minus, the latter two
6153 being kludges), it is MEM. When processing the arguments of a comparison
6154 or a COMPARE against zero, it is COMPARE. */
6157 make_compound_operation (rtx x, enum rtx_code in_code)
6159 enum rtx_code code = GET_CODE (x);
6160 enum machine_mode mode = GET_MODE (x);
6161 int mode_width = GET_MODE_BITSIZE (mode);
6163 enum rtx_code next_code;
6169 /* Select the code to be used in recursive calls. Once we are inside an
6170 address, we stay there. If we have a comparison, set to COMPARE,
6171 but once inside, go back to our default of SET. */
6173 next_code = (code == MEM || code == PLUS || code == MINUS ? MEM
6174 : ((code == COMPARE || COMPARISON_P (x))
6175 && XEXP (x, 1) == const0_rtx) ? COMPARE
6176 : in_code == COMPARE ? SET : in_code);
6178 /* Process depending on the code of this operation. If NEW is set
6179 nonzero, it will be returned. */
6184 /* Convert shifts by constants into multiplications if inside
6186 if (in_code == MEM && GET_CODE (XEXP (x, 1)) == CONST_INT
6187 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6188 && INTVAL (XEXP (x, 1)) >= 0)
6190 new = make_compound_operation (XEXP (x, 0), next_code);
6191 new = gen_rtx_MULT (mode, new,
6192 GEN_INT ((HOST_WIDE_INT) 1
6193 << INTVAL (XEXP (x, 1))));
6198 /* If the second operand is not a constant, we can't do anything
6200 if (GET_CODE (XEXP (x, 1)) != CONST_INT)
6203 /* If the constant is a power of two minus one and the first operand
6204 is a logical right shift, make an extraction. */
6205 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6206 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6208 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6209 new = make_extraction (mode, new, 0, XEXP (XEXP (x, 0), 1), i, 1,
6210 0, in_code == COMPARE);
6213 /* Same as previous, but for (subreg (lshiftrt ...)) in first op. */
6214 else if (GET_CODE (XEXP (x, 0)) == SUBREG
6215 && subreg_lowpart_p (XEXP (x, 0))
6216 && GET_CODE (SUBREG_REG (XEXP (x, 0))) == LSHIFTRT
6217 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6219 new = make_compound_operation (XEXP (SUBREG_REG (XEXP (x, 0)), 0),
6221 new = make_extraction (GET_MODE (SUBREG_REG (XEXP (x, 0))), new, 0,
6222 XEXP (SUBREG_REG (XEXP (x, 0)), 1), i, 1,
6223 0, in_code == COMPARE);
6225 /* Same as previous, but for (xor/ior (lshiftrt...) (lshiftrt...)). */
6226 else if ((GET_CODE (XEXP (x, 0)) == XOR
6227 || GET_CODE (XEXP (x, 0)) == IOR)
6228 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LSHIFTRT
6229 && GET_CODE (XEXP (XEXP (x, 0), 1)) == LSHIFTRT
6230 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6232 /* Apply the distributive law, and then try to make extractions. */
6233 new = gen_rtx_fmt_ee (GET_CODE (XEXP (x, 0)), mode,
6234 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 0),
6236 gen_rtx_AND (mode, XEXP (XEXP (x, 0), 1),
6238 new = make_compound_operation (new, in_code);
6241 /* If we are have (and (rotate X C) M) and C is larger than the number
6242 of bits in M, this is an extraction. */
6244 else if (GET_CODE (XEXP (x, 0)) == ROTATE
6245 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6246 && (i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0
6247 && i <= INTVAL (XEXP (XEXP (x, 0), 1)))
6249 new = make_compound_operation (XEXP (XEXP (x, 0), 0), next_code);
6250 new = make_extraction (mode, new,
6251 (GET_MODE_BITSIZE (mode)
6252 - INTVAL (XEXP (XEXP (x, 0), 1))),
6253 NULL_RTX, i, 1, 0, in_code == COMPARE);
6256 /* On machines without logical shifts, if the operand of the AND is
6257 a logical shift and our mask turns off all the propagated sign
6258 bits, we can replace the logical shift with an arithmetic shift. */
6259 else if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6260 && !have_insn_for (LSHIFTRT, mode)
6261 && have_insn_for (ASHIFTRT, mode)
6262 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6263 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6264 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6265 && mode_width <= HOST_BITS_PER_WIDE_INT)
6267 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
6269 mask >>= INTVAL (XEXP (XEXP (x, 0), 1));
6270 if ((INTVAL (XEXP (x, 1)) & ~mask) == 0)
6272 gen_rtx_ASHIFTRT (mode,
6273 make_compound_operation
6274 (XEXP (XEXP (x, 0), 0), next_code),
6275 XEXP (XEXP (x, 0), 1)));
6278 /* If the constant is one less than a power of two, this might be
6279 representable by an extraction even if no shift is present.
6280 If it doesn't end up being a ZERO_EXTEND, we will ignore it unless
6281 we are in a COMPARE. */
6282 else if ((i = exact_log2 (INTVAL (XEXP (x, 1)) + 1)) >= 0)
6283 new = make_extraction (mode,
6284 make_compound_operation (XEXP (x, 0),
6286 0, NULL_RTX, i, 1, 0, in_code == COMPARE);
6288 /* If we are in a comparison and this is an AND with a power of two,
6289 convert this into the appropriate bit extract. */
6290 else if (in_code == COMPARE
6291 && (i = exact_log2 (INTVAL (XEXP (x, 1)))) >= 0)
6292 new = make_extraction (mode,
6293 make_compound_operation (XEXP (x, 0),
6295 i, NULL_RTX, 1, 1, 0, 1);
6300 /* If the sign bit is known to be zero, replace this with an
6301 arithmetic shift. */
6302 if (have_insn_for (ASHIFTRT, mode)
6303 && ! have_insn_for (LSHIFTRT, mode)
6304 && mode_width <= HOST_BITS_PER_WIDE_INT
6305 && (nonzero_bits (XEXP (x, 0), mode) & (1 << (mode_width - 1))) == 0)
6307 new = gen_rtx_ASHIFTRT (mode,
6308 make_compound_operation (XEXP (x, 0),
6314 /* ... fall through ... */
6320 /* If we have (ashiftrt (ashift foo C1) C2) with C2 >= C1,
6321 this is a SIGN_EXTRACT. */
6322 if (GET_CODE (rhs) == CONST_INT
6323 && GET_CODE (lhs) == ASHIFT
6324 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
6325 && INTVAL (rhs) >= INTVAL (XEXP (lhs, 1)))
6327 new = make_compound_operation (XEXP (lhs, 0), next_code);
6328 new = make_extraction (mode, new,
6329 INTVAL (rhs) - INTVAL (XEXP (lhs, 1)),
6330 NULL_RTX, mode_width - INTVAL (rhs),
6331 code == LSHIFTRT, 0, in_code == COMPARE);
6335 /* See if we have operations between an ASHIFTRT and an ASHIFT.
6336 If so, try to merge the shifts into a SIGN_EXTEND. We could
6337 also do this for some cases of SIGN_EXTRACT, but it doesn't
6338 seem worth the effort; the case checked for occurs on Alpha. */
6341 && ! (GET_CODE (lhs) == SUBREG
6342 && (OBJECT_P (SUBREG_REG (lhs))))
6343 && GET_CODE (rhs) == CONST_INT
6344 && INTVAL (rhs) < HOST_BITS_PER_WIDE_INT
6345 && (new = extract_left_shift (lhs, INTVAL (rhs))) != 0)
6346 new = make_extraction (mode, make_compound_operation (new, next_code),
6347 0, NULL_RTX, mode_width - INTVAL (rhs),
6348 code == LSHIFTRT, 0, in_code == COMPARE);
6353 /* Call ourselves recursively on the inner expression. If we are
6354 narrowing the object and it has a different RTL code from
6355 what it originally did, do this SUBREG as a force_to_mode. */
6357 tem = make_compound_operation (SUBREG_REG (x), in_code);
6361 simplified = simplify_subreg (GET_MODE (x), tem, GET_MODE (tem),
6367 if (GET_CODE (tem) != GET_CODE (SUBREG_REG (x))
6368 && GET_MODE_SIZE (mode) < GET_MODE_SIZE (GET_MODE (tem))
6369 && subreg_lowpart_p (x))
6371 rtx newer = force_to_mode (tem, mode, ~(HOST_WIDE_INT) 0,
6374 /* If we have something other than a SUBREG, we might have
6375 done an expansion, so rerun ourselves. */
6376 if (GET_CODE (newer) != SUBREG)
6377 newer = make_compound_operation (newer, in_code);
6393 x = gen_lowpart (mode, new);
6394 code = GET_CODE (x);
6397 /* Now recursively process each operand of this operation. */
6398 fmt = GET_RTX_FORMAT (code);
6399 for (i = 0; i < GET_RTX_LENGTH (code); i++)
6402 new = make_compound_operation (XEXP (x, i), next_code);
6403 SUBST (XEXP (x, i), new);
6406 /* If this is a commutative operation, the changes to the operands
6407 may have made it noncanonical. */
6408 if (COMMUTATIVE_ARITH_P (x)
6409 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1)))
6412 SUBST (XEXP (x, 0), XEXP (x, 1));
6413 SUBST (XEXP (x, 1), tem);
6419 /* Given M see if it is a value that would select a field of bits
6420 within an item, but not the entire word. Return -1 if not.
6421 Otherwise, return the starting position of the field, where 0 is the
6424 *PLEN is set to the length of the field. */
6427 get_pos_from_mask (unsigned HOST_WIDE_INT m, unsigned HOST_WIDE_INT *plen)
6429 /* Get the bit number of the first 1 bit from the right, -1 if none. */
6430 int pos = exact_log2 (m & -m);
6434 /* Now shift off the low-order zero bits and see if we have a
6435 power of two minus 1. */
6436 len = exact_log2 ((m >> pos) + 1);
6445 /* If X refers to a register that equals REG in value, replace these
6446 references with REG. */
6448 canon_reg_for_combine (rtx x, rtx reg)
6455 enum rtx_code code = GET_CODE (x);
6456 switch (GET_RTX_CLASS (code))
6459 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6460 if (op0 != XEXP (x, 0))
6461 return simplify_gen_unary (GET_CODE (x), GET_MODE (x), op0,
6466 case RTX_COMM_ARITH:
6467 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6468 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6469 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6470 return simplify_gen_binary (GET_CODE (x), GET_MODE (x), op0, op1);
6474 case RTX_COMM_COMPARE:
6475 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6476 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6477 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6478 return simplify_gen_relational (GET_CODE (x), GET_MODE (x),
6479 GET_MODE (op0), op0, op1);
6483 case RTX_BITFIELD_OPS:
6484 op0 = canon_reg_for_combine (XEXP (x, 0), reg);
6485 op1 = canon_reg_for_combine (XEXP (x, 1), reg);
6486 op2 = canon_reg_for_combine (XEXP (x, 2), reg);
6487 if (op0 != XEXP (x, 0) || op1 != XEXP (x, 1) || op2 != XEXP (x, 2))
6488 return simplify_gen_ternary (GET_CODE (x), GET_MODE (x),
6489 GET_MODE (op0), op0, op1, op2);
6494 if (rtx_equal_p (get_last_value (reg), x)
6495 || rtx_equal_p (reg, get_last_value (x)))
6504 fmt = GET_RTX_FORMAT (code);
6506 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
6509 rtx op = canon_reg_for_combine (XEXP (x, i), reg);
6510 if (op != XEXP (x, i))
6520 else if (fmt[i] == 'E')
6523 for (j = 0; j < XVECLEN (x, i); j++)
6525 rtx op = canon_reg_for_combine (XVECEXP (x, i, j), reg);
6526 if (op != XVECEXP (x, i, j))
6533 XVECEXP (x, i, j) = op;
6544 /* See if X can be simplified knowing that we will only refer to it in
6545 MODE and will only refer to those bits that are nonzero in MASK.
6546 If other bits are being computed or if masking operations are done
6547 that select a superset of the bits in MASK, they can sometimes be
6550 Return a possibly simplified expression, but always convert X to
6551 MODE. If X is a CONST_INT, AND the CONST_INT with MASK.
6553 If JUST_SELECT is nonzero, don't optimize by noticing that bits in MASK
6554 are all off in X. This is used when X will be complemented, by either
6555 NOT, NEG, or XOR. */
6558 force_to_mode (rtx x, enum machine_mode mode, unsigned HOST_WIDE_INT mask,
6561 enum rtx_code code = GET_CODE (x);
6562 int next_select = just_select || code == XOR || code == NOT || code == NEG;
6563 enum machine_mode op_mode;
6564 unsigned HOST_WIDE_INT fuller_mask, nonzero;
6567 /* If this is a CALL or ASM_OPERANDS, don't do anything. Some of the
6568 code below will do the wrong thing since the mode of such an
6569 expression is VOIDmode.
6571 Also do nothing if X is a CLOBBER; this can happen if X was
6572 the return value from a call to gen_lowpart. */
6573 if (code == CALL || code == ASM_OPERANDS || code == CLOBBER)
6576 /* We want to perform the operation is its present mode unless we know
6577 that the operation is valid in MODE, in which case we do the operation
6579 op_mode = ((GET_MODE_CLASS (mode) == GET_MODE_CLASS (GET_MODE (x))
6580 && have_insn_for (code, mode))
6581 ? mode : GET_MODE (x));
6583 /* It is not valid to do a right-shift in a narrower mode
6584 than the one it came in with. */
6585 if ((code == LSHIFTRT || code == ASHIFTRT)
6586 && GET_MODE_BITSIZE (mode) < GET_MODE_BITSIZE (GET_MODE (x)))
6587 op_mode = GET_MODE (x);
6589 /* Truncate MASK to fit OP_MODE. */
6591 mask &= GET_MODE_MASK (op_mode);
6593 /* When we have an arithmetic operation, or a shift whose count we
6594 do not know, we need to assume that all bits up to the highest-order
6595 bit in MASK will be needed. This is how we form such a mask. */
6596 if (mask & ((unsigned HOST_WIDE_INT) 1 << (HOST_BITS_PER_WIDE_INT - 1)))
6597 fuller_mask = ~(unsigned HOST_WIDE_INT) 0;
6599 fuller_mask = (((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mask) + 1))
6602 /* Determine what bits of X are guaranteed to be (non)zero. */
6603 nonzero = nonzero_bits (x, mode);
6605 /* If none of the bits in X are needed, return a zero. */
6606 if (! just_select && (nonzero & mask) == 0)
6609 /* If X is a CONST_INT, return a new one. Do this here since the
6610 test below will fail. */
6611 if (GET_CODE (x) == CONST_INT)
6613 if (SCALAR_INT_MODE_P (mode))
6614 return gen_int_mode (INTVAL (x) & mask, mode);
6617 x = GEN_INT (INTVAL (x) & mask);
6618 return gen_lowpart_common (mode, x);
6622 /* If X is narrower than MODE and we want all the bits in X's mode, just
6623 get X in the proper mode. */
6624 if (GET_MODE_SIZE (GET_MODE (x)) < GET_MODE_SIZE (mode)
6625 && (GET_MODE_MASK (GET_MODE (x)) & ~mask) == 0)
6626 return gen_lowpart (mode, x);
6631 /* If X is a (clobber (const_int)), return it since we know we are
6632 generating something that won't match. */
6636 /* X is a (use (mem ..)) that was made from a bit-field extraction that
6637 spanned the boundary of the MEM. If we are now masking so it is
6638 within that boundary, we don't need the USE any more. */
6639 if (! BITS_BIG_ENDIAN
6640 && (mask & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))) == 0)
6641 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
6648 x = expand_compound_operation (x);
6649 if (GET_CODE (x) != code)
6650 return force_to_mode (x, mode, mask, next_select);
6654 if (subreg_lowpart_p (x)
6655 /* We can ignore the effect of this SUBREG if it narrows the mode or
6656 if the constant masks to zero all the bits the mode doesn't
6658 && ((GET_MODE_SIZE (GET_MODE (x))
6659 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
6661 & GET_MODE_MASK (GET_MODE (x))
6662 & ~GET_MODE_MASK (GET_MODE (SUBREG_REG (x)))))))
6663 return force_to_mode (SUBREG_REG (x), mode, mask, next_select);
6667 /* If this is an AND with a constant, convert it into an AND
6668 whose constant is the AND of that constant with MASK. If it
6669 remains an AND of MASK, delete it since it is redundant. */
6671 if (GET_CODE (XEXP (x, 1)) == CONST_INT)
6673 x = simplify_and_const_int (x, op_mode, XEXP (x, 0),
6674 mask & INTVAL (XEXP (x, 1)));
6676 /* If X is still an AND, see if it is an AND with a mask that
6677 is just some low-order bits. If so, and it is MASK, we don't
6680 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6681 && ((INTVAL (XEXP (x, 1)) & GET_MODE_MASK (GET_MODE (x)))
6685 /* If it remains an AND, try making another AND with the bits
6686 in the mode mask that aren't in MASK turned on. If the
6687 constant in the AND is wide enough, this might make a
6688 cheaper constant. */
6690 if (GET_CODE (x) == AND && GET_CODE (XEXP (x, 1)) == CONST_INT
6691 && GET_MODE_MASK (GET_MODE (x)) != mask
6692 && GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT)
6694 HOST_WIDE_INT cval = (INTVAL (XEXP (x, 1))
6695 | (GET_MODE_MASK (GET_MODE (x)) & ~mask));
6696 int width = GET_MODE_BITSIZE (GET_MODE (x));
6699 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative
6700 number, sign extend it. */
6701 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
6702 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6703 cval |= (HOST_WIDE_INT) -1 << width;
6705 y = simplify_gen_binary (AND, GET_MODE (x),
6706 XEXP (x, 0), GEN_INT (cval));
6707 if (rtx_cost (y, SET) < rtx_cost (x, SET))
6717 /* In (and (plus FOO C1) M), if M is a mask that just turns off
6718 low-order bits (as in an alignment operation) and FOO is already
6719 aligned to that boundary, mask C1 to that boundary as well.
6720 This may eliminate that PLUS and, later, the AND. */
6723 unsigned int width = GET_MODE_BITSIZE (mode);
6724 unsigned HOST_WIDE_INT smask = mask;
6726 /* If MODE is narrower than HOST_WIDE_INT and mask is a negative
6727 number, sign extend it. */
6729 if (width < HOST_BITS_PER_WIDE_INT
6730 && (smask & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
6731 smask |= (HOST_WIDE_INT) -1 << width;
6733 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6734 && exact_log2 (- smask) >= 0
6735 && (nonzero_bits (XEXP (x, 0), mode) & ~smask) == 0
6736 && (INTVAL (XEXP (x, 1)) & ~smask) != 0)
6737 return force_to_mode (plus_constant (XEXP (x, 0),
6738 (INTVAL (XEXP (x, 1)) & smask)),
6739 mode, smask, next_select);
6742 /* ... fall through ... */
6745 /* For PLUS, MINUS and MULT, we need any bits less significant than the
6746 most significant bit in MASK since carries from those bits will
6747 affect the bits we are interested in. */
6752 /* If X is (minus C Y) where C's least set bit is larger than any bit
6753 in the mask, then we may replace with (neg Y). */
6754 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6755 && (((unsigned HOST_WIDE_INT) (INTVAL (XEXP (x, 0))
6756 & -INTVAL (XEXP (x, 0))))
6759 x = simplify_gen_unary (NEG, GET_MODE (x), XEXP (x, 1),
6761 return force_to_mode (x, mode, mask, next_select);
6764 /* Similarly, if C contains every bit in the fuller_mask, then we may
6765 replace with (not Y). */
6766 if (GET_CODE (XEXP (x, 0)) == CONST_INT
6767 && ((INTVAL (XEXP (x, 0)) | (HOST_WIDE_INT) fuller_mask)
6768 == INTVAL (XEXP (x, 0))))
6770 x = simplify_gen_unary (NOT, GET_MODE (x),
6771 XEXP (x, 1), GET_MODE (x));
6772 return force_to_mode (x, mode, mask, next_select);
6780 /* If X is (ior (lshiftrt FOO C1) C2), try to commute the IOR and
6781 LSHIFTRT so we end up with an (and (lshiftrt (ior ...) ...) ...)
6782 operation which may be a bitfield extraction. Ensure that the
6783 constant we form is not wider than the mode of X. */
6785 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
6786 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
6787 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
6788 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT
6789 && GET_CODE (XEXP (x, 1)) == CONST_INT
6790 && ((INTVAL (XEXP (XEXP (x, 0), 1))
6791 + floor_log2 (INTVAL (XEXP (x, 1))))
6792 < GET_MODE_BITSIZE (GET_MODE (x)))
6793 && (INTVAL (XEXP (x, 1))
6794 & ~nonzero_bits (XEXP (x, 0), GET_MODE (x))) == 0)
6796 temp = GEN_INT ((INTVAL (XEXP (x, 1)) & mask)
6797 << INTVAL (XEXP (XEXP (x, 0), 1)));
6798 temp = simplify_gen_binary (GET_CODE (x), GET_MODE (x),
6799 XEXP (XEXP (x, 0), 0), temp);
6800 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), temp,
6801 XEXP (XEXP (x, 0), 1));
6802 return force_to_mode (x, mode, mask, next_select);
6806 /* For most binary operations, just propagate into the operation and
6807 change the mode if we have an operation of that mode. */
6809 op0 = gen_lowpart (op_mode,
6810 force_to_mode (XEXP (x, 0), mode, mask,
6812 op1 = gen_lowpart (op_mode,
6813 force_to_mode (XEXP (x, 1), mode, mask,
6816 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0) || op1 != XEXP (x, 1))
6817 x = simplify_gen_binary (code, op_mode, op0, op1);
6821 /* For left shifts, do the same, but just for the first operand.
6822 However, we cannot do anything with shifts where we cannot
6823 guarantee that the counts are smaller than the size of the mode
6824 because such a count will have a different meaning in a
6827 if (! (GET_CODE (XEXP (x, 1)) == CONST_INT
6828 && INTVAL (XEXP (x, 1)) >= 0
6829 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (mode))
6830 && ! (GET_MODE (XEXP (x, 1)) != VOIDmode
6831 && (nonzero_bits (XEXP (x, 1), GET_MODE (XEXP (x, 1)))
6832 < (unsigned HOST_WIDE_INT) GET_MODE_BITSIZE (mode))))
6835 /* If the shift count is a constant and we can do arithmetic in
6836 the mode of the shift, refine which bits we need. Otherwise, use the
6837 conservative form of the mask. */
6838 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6839 && INTVAL (XEXP (x, 1)) >= 0
6840 && INTVAL (XEXP (x, 1)) < GET_MODE_BITSIZE (op_mode)
6841 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6842 mask >>= INTVAL (XEXP (x, 1));
6846 op0 = gen_lowpart (op_mode,
6847 force_to_mode (XEXP (x, 0), op_mode,
6848 mask, next_select));
6850 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
6851 x = simplify_gen_binary (code, op_mode, op0, XEXP (x, 1));
6855 /* Here we can only do something if the shift count is a constant,
6856 this shift constant is valid for the host, and we can do arithmetic
6859 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6860 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT
6861 && GET_MODE_BITSIZE (op_mode) <= HOST_BITS_PER_WIDE_INT)
6863 rtx inner = XEXP (x, 0);
6864 unsigned HOST_WIDE_INT inner_mask;
6866 /* Select the mask of the bits we need for the shift operand. */
6867 inner_mask = mask << INTVAL (XEXP (x, 1));
6869 /* We can only change the mode of the shift if we can do arithmetic
6870 in the mode of the shift and INNER_MASK is no wider than the
6871 width of X's mode. */
6872 if ((inner_mask & ~GET_MODE_MASK (GET_MODE (x))) != 0)
6873 op_mode = GET_MODE (x);
6875 inner = force_to_mode (inner, op_mode, inner_mask, next_select);
6877 if (GET_MODE (x) != op_mode || inner != XEXP (x, 0))
6878 x = simplify_gen_binary (LSHIFTRT, op_mode, inner, XEXP (x, 1));
6881 /* If we have (and (lshiftrt FOO C1) C2) where the combination of the
6882 shift and AND produces only copies of the sign bit (C2 is one less
6883 than a power of two), we can do this with just a shift. */
6885 if (GET_CODE (x) == LSHIFTRT
6886 && GET_CODE (XEXP (x, 1)) == CONST_INT
6887 /* The shift puts one of the sign bit copies in the least significant
6889 && ((INTVAL (XEXP (x, 1))
6890 + num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0))))
6891 >= GET_MODE_BITSIZE (GET_MODE (x)))
6892 && exact_log2 (mask + 1) >= 0
6893 /* Number of bits left after the shift must be more than the mask
6895 && ((INTVAL (XEXP (x, 1)) + exact_log2 (mask + 1))
6896 <= GET_MODE_BITSIZE (GET_MODE (x)))
6897 /* Must be more sign bit copies than the mask needs. */
6898 && ((int) num_sign_bit_copies (XEXP (x, 0), GET_MODE (XEXP (x, 0)))
6899 >= exact_log2 (mask + 1)))
6900 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6901 GEN_INT (GET_MODE_BITSIZE (GET_MODE (x))
6902 - exact_log2 (mask + 1)));
6907 /* If we are just looking for the sign bit, we don't need this shift at
6908 all, even if it has a variable count. */
6909 if (GET_MODE_BITSIZE (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT
6910 && (mask == ((unsigned HOST_WIDE_INT) 1
6911 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
6912 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
6914 /* If this is a shift by a constant, get a mask that contains those bits
6915 that are not copies of the sign bit. We then have two cases: If
6916 MASK only includes those bits, this can be a logical shift, which may
6917 allow simplifications. If MASK is a single-bit field not within
6918 those bits, we are requesting a copy of the sign bit and hence can
6919 shift the sign bit to the appropriate location. */
6921 if (GET_CODE (XEXP (x, 1)) == CONST_INT && INTVAL (XEXP (x, 1)) >= 0
6922 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT)
6926 /* If the considered data is wider than HOST_WIDE_INT, we can't
6927 represent a mask for all its bits in a single scalar.
6928 But we only care about the lower bits, so calculate these. */
6930 if (GET_MODE_BITSIZE (GET_MODE (x)) > HOST_BITS_PER_WIDE_INT)
6932 nonzero = ~(HOST_WIDE_INT) 0;
6934 /* GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6935 is the number of bits a full-width mask would have set.
6936 We need only shift if these are fewer than nonzero can
6937 hold. If not, we must keep all bits set in nonzero. */
6939 if (GET_MODE_BITSIZE (GET_MODE (x)) - INTVAL (XEXP (x, 1))
6940 < HOST_BITS_PER_WIDE_INT)
6941 nonzero >>= INTVAL (XEXP (x, 1))
6942 + HOST_BITS_PER_WIDE_INT
6943 - GET_MODE_BITSIZE (GET_MODE (x)) ;
6947 nonzero = GET_MODE_MASK (GET_MODE (x));
6948 nonzero >>= INTVAL (XEXP (x, 1));
6951 if ((mask & ~nonzero) == 0
6952 || (i = exact_log2 (mask)) >= 0)
6954 x = simplify_shift_const
6955 (x, LSHIFTRT, GET_MODE (x), XEXP (x, 0),
6956 i < 0 ? INTVAL (XEXP (x, 1))
6957 : GET_MODE_BITSIZE (GET_MODE (x)) - 1 - i);
6959 if (GET_CODE (x) != ASHIFTRT)
6960 return force_to_mode (x, mode, mask, next_select);
6964 /* If MASK is 1, convert this to an LSHIFTRT. This can be done
6965 even if the shift count isn't a constant. */
6967 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
6968 XEXP (x, 0), XEXP (x, 1));
6972 /* If this is a zero- or sign-extension operation that just affects bits
6973 we don't care about, remove it. Be sure the call above returned
6974 something that is still a shift. */
6976 if ((GET_CODE (x) == LSHIFTRT || GET_CODE (x) == ASHIFTRT)
6977 && GET_CODE (XEXP (x, 1)) == CONST_INT
6978 && INTVAL (XEXP (x, 1)) >= 0
6979 && (INTVAL (XEXP (x, 1))
6980 <= GET_MODE_BITSIZE (GET_MODE (x)) - (floor_log2 (mask) + 1))
6981 && GET_CODE (XEXP (x, 0)) == ASHIFT
6982 && XEXP (XEXP (x, 0), 1) == XEXP (x, 1))
6983 return force_to_mode (XEXP (XEXP (x, 0), 0), mode, mask,
6990 /* If the shift count is constant and we can do computations
6991 in the mode of X, compute where the bits we care about are.
6992 Otherwise, we can't do anything. Don't change the mode of
6993 the shift or propagate MODE into the shift, though. */
6994 if (GET_CODE (XEXP (x, 1)) == CONST_INT
6995 && INTVAL (XEXP (x, 1)) >= 0)
6997 temp = simplify_binary_operation (code == ROTATE ? ROTATERT : ROTATE,
6998 GET_MODE (x), GEN_INT (mask),
7000 if (temp && GET_CODE (temp) == CONST_INT)
7002 force_to_mode (XEXP (x, 0), GET_MODE (x),
7003 INTVAL (temp), next_select));
7008 /* If we just want the low-order bit, the NEG isn't needed since it
7009 won't change the low-order bit. */
7011 return force_to_mode (XEXP (x, 0), mode, mask, just_select);
7013 /* We need any bits less significant than the most significant bit in
7014 MASK since carries from those bits will affect the bits we are
7020 /* (not FOO) is (xor FOO CONST), so if FOO is an LSHIFTRT, we can do the
7021 same as the XOR case above. Ensure that the constant we form is not
7022 wider than the mode of X. */
7024 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT
7025 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT
7026 && INTVAL (XEXP (XEXP (x, 0), 1)) >= 0
7027 && (INTVAL (XEXP (XEXP (x, 0), 1)) + floor_log2 (mask)
7028 < GET_MODE_BITSIZE (GET_MODE (x)))
7029 && INTVAL (XEXP (XEXP (x, 0), 1)) < HOST_BITS_PER_WIDE_INT)
7031 temp = gen_int_mode (mask << INTVAL (XEXP (XEXP (x, 0), 1)),
7033 temp = simplify_gen_binary (XOR, GET_MODE (x),
7034 XEXP (XEXP (x, 0), 0), temp);
7035 x = simplify_gen_binary (LSHIFTRT, GET_MODE (x),
7036 temp, XEXP (XEXP (x, 0), 1));
7038 return force_to_mode (x, mode, mask, next_select);
7041 /* (and (not FOO) CONST) is (not (or FOO (not CONST))), so we must
7042 use the full mask inside the NOT. */
7046 op0 = gen_lowpart (op_mode,
7047 force_to_mode (XEXP (x, 0), mode, mask,
7049 if (op_mode != GET_MODE (x) || op0 != XEXP (x, 0))
7050 x = simplify_gen_unary (code, op_mode, op0, op_mode);
7054 /* (and (ne FOO 0) CONST) can be (and FOO CONST) if CONST is included
7055 in STORE_FLAG_VALUE and FOO has a single bit that might be nonzero,
7056 which is equal to STORE_FLAG_VALUE. */
7057 if ((mask & ~STORE_FLAG_VALUE) == 0 && XEXP (x, 1) == const0_rtx
7058 && GET_MODE (XEXP (x, 0)) == mode
7059 && exact_log2 (nonzero_bits (XEXP (x, 0), mode)) >= 0
7060 && (nonzero_bits (XEXP (x, 0), mode)
7061 == (unsigned HOST_WIDE_INT) STORE_FLAG_VALUE))
7062 return force_to_mode (XEXP (x, 0), mode, mask, next_select);
7067 /* We have no way of knowing if the IF_THEN_ELSE can itself be
7068 written in a narrower mode. We play it safe and do not do so. */
7071 gen_lowpart (GET_MODE (x), force_to_mode (XEXP (x, 1), mode,
7072 mask, next_select)));
7074 gen_lowpart (GET_MODE (x), force_to_mode (XEXP (x, 2), mode,
7075 mask, next_select)));
7082 /* Ensure we return a value of the proper mode. */
7083 return gen_lowpart (mode, x);
7086 /* Return nonzero if X is an expression that has one of two values depending on
7087 whether some other value is zero or nonzero. In that case, we return the
7088 value that is being tested, *PTRUE is set to the value if the rtx being
7089 returned has a nonzero value, and *PFALSE is set to the other alternative.
7091 If we return zero, we set *PTRUE and *PFALSE to X. */
7094 if_then_else_cond (rtx x, rtx *ptrue, rtx *pfalse)
7096 enum machine_mode mode = GET_MODE (x);
7097 enum rtx_code code = GET_CODE (x);
7098 rtx cond0, cond1, true0, true1, false0, false1;
7099 unsigned HOST_WIDE_INT nz;
7101 /* If we are comparing a value against zero, we are done. */
7102 if ((code == NE || code == EQ)
7103 && XEXP (x, 1) == const0_rtx)
7105 *ptrue = (code == NE) ? const_true_rtx : const0_rtx;
7106 *pfalse = (code == NE) ? const0_rtx : const_true_rtx;
7110 /* If this is a unary operation whose operand has one of two values, apply
7111 our opcode to compute those values. */
7112 else if (UNARY_P (x)
7113 && (cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0)) != 0)
7115 *ptrue = simplify_gen_unary (code, mode, true0, GET_MODE (XEXP (x, 0)));
7116 *pfalse = simplify_gen_unary (code, mode, false0,
7117 GET_MODE (XEXP (x, 0)));
7121 /* If this is a COMPARE, do nothing, since the IF_THEN_ELSE we would
7122 make can't possibly match and would suppress other optimizations. */
7123 else if (code == COMPARE)
7126 /* If this is a binary operation, see if either side has only one of two
7127 values. If either one does or if both do and they are conditional on
7128 the same value, compute the new true and false values. */
7129 else if (BINARY_P (x))
7131 cond0 = if_then_else_cond (XEXP (x, 0), &true0, &false0);
7132 cond1 = if_then_else_cond (XEXP (x, 1), &true1, &false1);
7134 if ((cond0 != 0 || cond1 != 0)
7135 && ! (cond0 != 0 && cond1 != 0 && ! rtx_equal_p (cond0, cond1)))
7137 /* If if_then_else_cond returned zero, then true/false are the
7138 same rtl. We must copy one of them to prevent invalid rtl
7141 true0 = copy_rtx (true0);
7142 else if (cond1 == 0)
7143 true1 = copy_rtx (true1);
7145 if (COMPARISON_P (x))
7147 *ptrue = simplify_gen_relational (code, mode, VOIDmode,
7149 *pfalse = simplify_gen_relational (code, mode, VOIDmode,
7154 *ptrue = simplify_gen_binary (code, mode, true0, true1);
7155 *pfalse = simplify_gen_binary (code, mode, false0, false1);
7158 return cond0 ? cond0 : cond1;
7161 /* See if we have PLUS, IOR, XOR, MINUS or UMAX, where one of the
7162 operands is zero when the other is nonzero, and vice-versa,
7163 and STORE_FLAG_VALUE is 1 or -1. */
7165 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7166 && (code == PLUS || code == IOR || code == XOR || code == MINUS
7168 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7170 rtx op0 = XEXP (XEXP (x, 0), 1);
7171 rtx op1 = XEXP (XEXP (x, 1), 1);
7173 cond0 = XEXP (XEXP (x, 0), 0);
7174 cond1 = XEXP (XEXP (x, 1), 0);
7176 if (COMPARISON_P (cond0)
7177 && COMPARISON_P (cond1)
7178 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7179 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7180 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7181 || ((swap_condition (GET_CODE (cond0))
7182 == reversed_comparison_code (cond1, NULL))
7183 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7184 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7185 && ! side_effects_p (x))
7187 *ptrue = simplify_gen_binary (MULT, mode, op0, const_true_rtx);
7188 *pfalse = simplify_gen_binary (MULT, mode,
7190 ? simplify_gen_unary (NEG, mode,
7198 /* Similarly for MULT, AND and UMIN, except that for these the result
7200 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
7201 && (code == MULT || code == AND || code == UMIN)
7202 && GET_CODE (XEXP (x, 0)) == MULT && GET_CODE (XEXP (x, 1)) == MULT)
7204 cond0 = XEXP (XEXP (x, 0), 0);
7205 cond1 = XEXP (XEXP (x, 1), 0);
7207 if (COMPARISON_P (cond0)
7208 && COMPARISON_P (cond1)
7209 && ((GET_CODE (cond0) == reversed_comparison_code (cond1, NULL)
7210 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 0))
7211 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 1)))
7212 || ((swap_condition (GET_CODE (cond0))
7213 == reversed_comparison_code (cond1, NULL))
7214 && rtx_equal_p (XEXP (cond0, 0), XEXP (cond1, 1))
7215 && rtx_equal_p (XEXP (cond0, 1), XEXP (cond1, 0))))
7216 && ! side_effects_p (x))
7218 *ptrue = *pfalse = const0_rtx;
7224 else if (code == IF_THEN_ELSE)
7226 /* If we have IF_THEN_ELSE already, extract the condition and
7227 canonicalize it if it is NE or EQ. */
7228 cond0 = XEXP (x, 0);
7229 *ptrue = XEXP (x, 1), *pfalse = XEXP (x, 2);
7230 if (GET_CODE (cond0) == NE && XEXP (cond0, 1) == const0_rtx)
7231 return XEXP (cond0, 0);
7232 else if (GET_CODE (cond0) == EQ && XEXP (cond0, 1) == const0_rtx)
7234 *ptrue = XEXP (x, 2), *pfalse = XEXP (x, 1);
7235 return XEXP (cond0, 0);
7241 /* If X is a SUBREG, we can narrow both the true and false values
7242 if the inner expression, if there is a condition. */
7243 else if (code == SUBREG
7244 && 0 != (cond0 = if_then_else_cond (SUBREG_REG (x),
7247 true0 = simplify_gen_subreg (mode, true0,
7248 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7249 false0 = simplify_gen_subreg (mode, false0,
7250 GET_MODE (SUBREG_REG (x)), SUBREG_BYTE (x));
7251 if (true0 && false0)
7259 /* If X is a constant, this isn't special and will cause confusions
7260 if we treat it as such. Likewise if it is equivalent to a constant. */
7261 else if (CONSTANT_P (x)
7262 || ((cond0 = get_last_value (x)) != 0 && CONSTANT_P (cond0)))
7265 /* If we're in BImode, canonicalize on 0 and STORE_FLAG_VALUE, as that
7266 will be least confusing to the rest of the compiler. */
7267 else if (mode == BImode)
7269 *ptrue = GEN_INT (STORE_FLAG_VALUE), *pfalse = const0_rtx;
7273 /* If X is known to be either 0 or -1, those are the true and
7274 false values when testing X. */
7275 else if (x == constm1_rtx || x == const0_rtx
7276 || (mode != VOIDmode
7277 && num_sign_bit_copies (x, mode) == GET_MODE_BITSIZE (mode)))
7279 *ptrue = constm1_rtx, *pfalse = const0_rtx;
7283 /* Likewise for 0 or a single bit. */
7284 else if (SCALAR_INT_MODE_P (mode)
7285 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
7286 && exact_log2 (nz = nonzero_bits (x, mode)) >= 0)
7288 *ptrue = gen_int_mode (nz, mode), *pfalse = const0_rtx;
7292 /* Otherwise fail; show no condition with true and false values the same. */
7293 *ptrue = *pfalse = x;
7297 /* Return the value of expression X given the fact that condition COND
7298 is known to be true when applied to REG as its first operand and VAL
7299 as its second. X is known to not be shared and so can be modified in
7302 We only handle the simplest cases, and specifically those cases that
7303 arise with IF_THEN_ELSE expressions. */
7306 known_cond (rtx x, enum rtx_code cond, rtx reg, rtx val)
7308 enum rtx_code code = GET_CODE (x);
7313 if (side_effects_p (x))
7316 /* If either operand of the condition is a floating point value,
7317 then we have to avoid collapsing an EQ comparison. */
7319 && rtx_equal_p (x, reg)
7320 && ! FLOAT_MODE_P (GET_MODE (x))
7321 && ! FLOAT_MODE_P (GET_MODE (val)))
7324 if (cond == UNEQ && rtx_equal_p (x, reg))
7327 /* If X is (abs REG) and we know something about REG's relationship
7328 with zero, we may be able to simplify this. */
7330 if (code == ABS && rtx_equal_p (XEXP (x, 0), reg) && val == const0_rtx)
7333 case GE: case GT: case EQ:
7336 return simplify_gen_unary (NEG, GET_MODE (XEXP (x, 0)),
7338 GET_MODE (XEXP (x, 0)));
7343 /* The only other cases we handle are MIN, MAX, and comparisons if the
7344 operands are the same as REG and VAL. */
7346 else if (COMPARISON_P (x) || COMMUTATIVE_ARITH_P (x))
7348 if (rtx_equal_p (XEXP (x, 0), val))
7349 cond = swap_condition (cond), temp = val, val = reg, reg = temp;
7351 if (rtx_equal_p (XEXP (x, 0), reg) && rtx_equal_p (XEXP (x, 1), val))
7353 if (COMPARISON_P (x))
7355 if (comparison_dominates_p (cond, code))
7356 return const_true_rtx;
7358 code = reversed_comparison_code (x, NULL);
7360 && comparison_dominates_p (cond, code))
7365 else if (code == SMAX || code == SMIN
7366 || code == UMIN || code == UMAX)
7368 int unsignedp = (code == UMIN || code == UMAX);
7370 /* Do not reverse the condition when it is NE or EQ.
7371 This is because we cannot conclude anything about
7372 the value of 'SMAX (x, y)' when x is not equal to y,
7373 but we can when x equals y. */
7374 if ((code == SMAX || code == UMAX)
7375 && ! (cond == EQ || cond == NE))
7376 cond = reverse_condition (cond);
7381 return unsignedp ? x : XEXP (x, 1);
7383 return unsignedp ? x : XEXP (x, 0);
7385 return unsignedp ? XEXP (x, 1) : x;
7387 return unsignedp ? XEXP (x, 0) : x;
7394 else if (code == SUBREG)
7396 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (x));
7397 rtx new, r = known_cond (SUBREG_REG (x), cond, reg, val);
7399 if (SUBREG_REG (x) != r)
7401 /* We must simplify subreg here, before we lose track of the
7402 original inner_mode. */
7403 new = simplify_subreg (GET_MODE (x), r,
7404 inner_mode, SUBREG_BYTE (x));
7408 SUBST (SUBREG_REG (x), r);
7413 /* We don't have to handle SIGN_EXTEND here, because even in the
7414 case of replacing something with a modeless CONST_INT, a
7415 CONST_INT is already (supposed to be) a valid sign extension for
7416 its narrower mode, which implies it's already properly
7417 sign-extended for the wider mode. Now, for ZERO_EXTEND, the
7418 story is different. */
7419 else if (code == ZERO_EXTEND)
7421 enum machine_mode inner_mode = GET_MODE (XEXP (x, 0));
7422 rtx new, r = known_cond (XEXP (x, 0), cond, reg, val);
7424 if (XEXP (x, 0) != r)
7426 /* We must simplify the zero_extend here, before we lose
7427 track of the original inner_mode. */
7428 new = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x),
7433 SUBST (XEXP (x, 0), r);
7439 fmt = GET_RTX_FORMAT (code);
7440 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7443 SUBST (XEXP (x, i), known_cond (XEXP (x, i), cond, reg, val));
7444 else if (fmt[i] == 'E')
7445 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7446 SUBST (XVECEXP (x, i, j), known_cond (XVECEXP (x, i, j),
7453 /* See if X and Y are equal for the purposes of seeing if we can rewrite an
7454 assignment as a field assignment. */
7457 rtx_equal_for_field_assignment_p (rtx x, rtx y)
7459 if (x == y || rtx_equal_p (x, y))
7462 if (x == 0 || y == 0 || GET_MODE (x) != GET_MODE (y))
7465 /* Check for a paradoxical SUBREG of a MEM compared with the MEM.
7466 Note that all SUBREGs of MEM are paradoxical; otherwise they
7467 would have been rewritten. */
7468 if (MEM_P (x) && GET_CODE (y) == SUBREG
7469 && MEM_P (SUBREG_REG (y))
7470 && rtx_equal_p (SUBREG_REG (y),
7471 gen_lowpart (GET_MODE (SUBREG_REG (y)), x)))
7474 if (MEM_P (y) && GET_CODE (x) == SUBREG
7475 && MEM_P (SUBREG_REG (x))
7476 && rtx_equal_p (SUBREG_REG (x),
7477 gen_lowpart (GET_MODE (SUBREG_REG (x)), y)))
7480 /* We used to see if get_last_value of X and Y were the same but that's
7481 not correct. In one direction, we'll cause the assignment to have
7482 the wrong destination and in the case, we'll import a register into this
7483 insn that might have already have been dead. So fail if none of the
7484 above cases are true. */
7488 /* See if X, a SET operation, can be rewritten as a bit-field assignment.
7489 Return that assignment if so.
7491 We only handle the most common cases. */
7494 make_field_assignment (rtx x)
7496 rtx dest = SET_DEST (x);
7497 rtx src = SET_SRC (x);
7502 unsigned HOST_WIDE_INT len;
7504 enum machine_mode mode;
7506 /* If SRC was (and (not (ashift (const_int 1) POS)) DEST), this is
7507 a clear of a one-bit field. We will have changed it to
7508 (and (rotate (const_int -2) POS) DEST), so check for that. Also check
7511 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == ROTATE
7512 && GET_CODE (XEXP (XEXP (src, 0), 0)) == CONST_INT
7513 && INTVAL (XEXP (XEXP (src, 0), 0)) == -2
7514 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7516 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7519 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7523 if (GET_CODE (src) == AND && GET_CODE (XEXP (src, 0)) == SUBREG
7524 && subreg_lowpart_p (XEXP (src, 0))
7525 && (GET_MODE_SIZE (GET_MODE (XEXP (src, 0)))
7526 < GET_MODE_SIZE (GET_MODE (SUBREG_REG (XEXP (src, 0)))))
7527 && GET_CODE (SUBREG_REG (XEXP (src, 0))) == ROTATE
7528 && GET_CODE (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == CONST_INT
7529 && INTVAL (XEXP (SUBREG_REG (XEXP (src, 0)), 0)) == -2
7530 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7532 assign = make_extraction (VOIDmode, dest, 0,
7533 XEXP (SUBREG_REG (XEXP (src, 0)), 1),
7536 return gen_rtx_SET (VOIDmode, assign, const0_rtx);
7540 /* If SRC is (ior (ashift (const_int 1) POS) DEST), this is a set of a
7542 if (GET_CODE (src) == IOR && GET_CODE (XEXP (src, 0)) == ASHIFT
7543 && XEXP (XEXP (src, 0), 0) == const1_rtx
7544 && rtx_equal_for_field_assignment_p (dest, XEXP (src, 1)))
7546 assign = make_extraction (VOIDmode, dest, 0, XEXP (XEXP (src, 0), 1),
7549 return gen_rtx_SET (VOIDmode, assign, const1_rtx);
7553 /* If DEST is already a field assignment, i.e. ZERO_EXTRACT, and the
7554 SRC is an AND with all bits of that field set, then we can discard
7556 if (GET_CODE (dest) == ZERO_EXTRACT
7557 && GET_CODE (XEXP (dest, 1)) == CONST_INT
7558 && GET_CODE (src) == AND
7559 && GET_CODE (XEXP (src, 1)) == CONST_INT)
7561 HOST_WIDE_INT width = INTVAL (XEXP (dest, 1));
7562 unsigned HOST_WIDE_INT and_mask = INTVAL (XEXP (src, 1));
7563 unsigned HOST_WIDE_INT ze_mask;
7565 if (width >= HOST_BITS_PER_WIDE_INT)
7568 ze_mask = ((unsigned HOST_WIDE_INT)1 << width) - 1;
7570 /* Complete overlap. We can remove the source AND. */
7571 if ((and_mask & ze_mask) == ze_mask)
7572 return gen_rtx_SET (VOIDmode, dest, XEXP (src, 0));
7574 /* Partial overlap. We can reduce the source AND. */
7575 if ((and_mask & ze_mask) != and_mask)
7577 mode = GET_MODE (src);
7578 src = gen_rtx_AND (mode, XEXP (src, 0),
7579 gen_int_mode (and_mask & ze_mask, mode));
7580 return gen_rtx_SET (VOIDmode, dest, src);
7584 /* The other case we handle is assignments into a constant-position
7585 field. They look like (ior/xor (and DEST C1) OTHER). If C1 represents
7586 a mask that has all one bits except for a group of zero bits and
7587 OTHER is known to have zeros where C1 has ones, this is such an
7588 assignment. Compute the position and length from C1. Shift OTHER
7589 to the appropriate position, force it to the required mode, and
7590 make the extraction. Check for the AND in both operands. */
7592 if (GET_CODE (src) != IOR && GET_CODE (src) != XOR)
7595 rhs = expand_compound_operation (XEXP (src, 0));
7596 lhs = expand_compound_operation (XEXP (src, 1));
7598 if (GET_CODE (rhs) == AND
7599 && GET_CODE (XEXP (rhs, 1)) == CONST_INT
7600 && rtx_equal_for_field_assignment_p (XEXP (rhs, 0), dest))
7601 c1 = INTVAL (XEXP (rhs, 1)), other = lhs;
7602 else if (GET_CODE (lhs) == AND
7603 && GET_CODE (XEXP (lhs, 1)) == CONST_INT
7604 && rtx_equal_for_field_assignment_p (XEXP (lhs, 0), dest))
7605 c1 = INTVAL (XEXP (lhs, 1)), other = rhs;
7609 pos = get_pos_from_mask ((~c1) & GET_MODE_MASK (GET_MODE (dest)), &len);
7610 if (pos < 0 || pos + len > GET_MODE_BITSIZE (GET_MODE (dest))
7611 || GET_MODE_BITSIZE (GET_MODE (dest)) > HOST_BITS_PER_WIDE_INT
7612 || (c1 & nonzero_bits (other, GET_MODE (dest))) != 0)
7615 assign = make_extraction (VOIDmode, dest, pos, NULL_RTX, len, 1, 1, 0);
7619 /* The mode to use for the source is the mode of the assignment, or of
7620 what is inside a possible STRICT_LOW_PART. */
7621 mode = (GET_CODE (assign) == STRICT_LOW_PART
7622 ? GET_MODE (XEXP (assign, 0)) : GET_MODE (assign));
7624 /* Shift OTHER right POS places and make it the source, restricting it
7625 to the proper length and mode. */
7627 src = canon_reg_for_combine (simplify_shift_const (NULL_RTX, LSHIFTRT,
7631 src = force_to_mode (src, mode,
7632 GET_MODE_BITSIZE (mode) >= HOST_BITS_PER_WIDE_INT
7633 ? ~(unsigned HOST_WIDE_INT) 0
7634 : ((unsigned HOST_WIDE_INT) 1 << len) - 1,
7637 /* If SRC is masked by an AND that does not make a difference in
7638 the value being stored, strip it. */
7639 if (GET_CODE (assign) == ZERO_EXTRACT
7640 && GET_CODE (XEXP (assign, 1)) == CONST_INT
7641 && INTVAL (XEXP (assign, 1)) < HOST_BITS_PER_WIDE_INT
7642 && GET_CODE (src) == AND
7643 && GET_CODE (XEXP (src, 1)) == CONST_INT
7644 && ((unsigned HOST_WIDE_INT) INTVAL (XEXP (src, 1))
7645 == ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (assign, 1))) - 1))
7646 src = XEXP (src, 0);
7648 return gen_rtx_SET (VOIDmode, assign, src);
7651 /* See if X is of the form (+ (* a c) (* b c)) and convert to (* (+ a b) c)
7655 apply_distributive_law (rtx x)
7657 enum rtx_code code = GET_CODE (x);
7658 enum rtx_code inner_code;
7659 rtx lhs, rhs, other;
7662 /* Distributivity is not true for floating point as it can change the
7663 value. So we don't do it unless -funsafe-math-optimizations. */
7664 if (FLOAT_MODE_P (GET_MODE (x))
7665 && ! flag_unsafe_math_optimizations)
7668 /* The outer operation can only be one of the following: */
7669 if (code != IOR && code != AND && code != XOR
7670 && code != PLUS && code != MINUS)
7676 /* If either operand is a primitive we can't do anything, so get out
7678 if (OBJECT_P (lhs) || OBJECT_P (rhs))
7681 lhs = expand_compound_operation (lhs);
7682 rhs = expand_compound_operation (rhs);
7683 inner_code = GET_CODE (lhs);
7684 if (inner_code != GET_CODE (rhs))
7687 /* See if the inner and outer operations distribute. */
7694 /* These all distribute except over PLUS. */
7695 if (code == PLUS || code == MINUS)
7700 if (code != PLUS && code != MINUS)
7705 /* This is also a multiply, so it distributes over everything. */
7709 /* Non-paradoxical SUBREGs distributes over all operations,
7710 provided the inner modes and byte offsets are the same, this
7711 is an extraction of a low-order part, we don't convert an fp
7712 operation to int or vice versa, this is not a vector mode,
7713 and we would not be converting a single-word operation into a
7714 multi-word operation. The latter test is not required, but
7715 it prevents generating unneeded multi-word operations. Some
7716 of the previous tests are redundant given the latter test,
7717 but are retained because they are required for correctness.
7719 We produce the result slightly differently in this case. */
7721 if (GET_MODE (SUBREG_REG (lhs)) != GET_MODE (SUBREG_REG (rhs))
7722 || SUBREG_BYTE (lhs) != SUBREG_BYTE (rhs)
7723 || ! subreg_lowpart_p (lhs)
7724 || (GET_MODE_CLASS (GET_MODE (lhs))
7725 != GET_MODE_CLASS (GET_MODE (SUBREG_REG (lhs))))
7726 || (GET_MODE_SIZE (GET_MODE (lhs))
7727 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))))
7728 || VECTOR_MODE_P (GET_MODE (lhs))
7729 || GET_MODE_SIZE (GET_MODE (SUBREG_REG (lhs))) > UNITS_PER_WORD)
7732 tem = simplify_gen_binary (code, GET_MODE (SUBREG_REG (lhs)),
7733 SUBREG_REG (lhs), SUBREG_REG (rhs));
7734 return gen_lowpart (GET_MODE (x), tem);
7740 /* Set LHS and RHS to the inner operands (A and B in the example
7741 above) and set OTHER to the common operand (C in the example).
7742 There is only one way to do this unless the inner operation is
7744 if (COMMUTATIVE_ARITH_P (lhs)
7745 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 0)))
7746 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 1);
7747 else if (COMMUTATIVE_ARITH_P (lhs)
7748 && rtx_equal_p (XEXP (lhs, 0), XEXP (rhs, 1)))
7749 other = XEXP (lhs, 0), lhs = XEXP (lhs, 1), rhs = XEXP (rhs, 0);
7750 else if (COMMUTATIVE_ARITH_P (lhs)
7751 && rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 0)))
7752 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 1);
7753 else if (rtx_equal_p (XEXP (lhs, 1), XEXP (rhs, 1)))
7754 other = XEXP (lhs, 1), lhs = XEXP (lhs, 0), rhs = XEXP (rhs, 0);
7758 /* Form the new inner operation, seeing if it simplifies first. */
7759 tem = simplify_gen_binary (code, GET_MODE (x), lhs, rhs);
7761 /* There is one exception to the general way of distributing:
7762 (a | c) ^ (b | c) -> (a ^ b) & ~c */
7763 if (code == XOR && inner_code == IOR)
7766 other = simplify_gen_unary (NOT, GET_MODE (x), other, GET_MODE (x));
7769 /* We may be able to continuing distributing the result, so call
7770 ourselves recursively on the inner operation before forming the
7771 outer operation, which we return. */
7772 return simplify_gen_binary (inner_code, GET_MODE (x),
7773 apply_distributive_law (tem), other);
7776 /* See if X is of the form (* (+ A B) C), and if so convert to
7777 (+ (* A C) (* B C)) and try to simplify.
7779 Most of the time, this results in no change. However, if some of
7780 the operands are the same or inverses of each other, simplifications
7783 For example, (and (ior A B) (not B)) can occur as the result of
7784 expanding a bit field assignment. When we apply the distributive
7785 law to this, we get (ior (and (A (not B))) (and (B (not B)))),
7786 which then simplifies to (and (A (not B))).
7788 Note that no checks happen on the validity of applying the inverse
7789 distributive law. This is pointless since we can do it in the
7790 few places where this routine is called.
7792 N is the index of the term that is decomposed (the arithmetic operation,
7793 i.e. (+ A B) in the first example above). !N is the index of the term that
7794 is distributed, i.e. of C in the first example above. */
7796 distribute_and_simplify_rtx (rtx x, int n)
7798 enum machine_mode mode;
7799 enum rtx_code outer_code, inner_code;
7800 rtx decomposed, distributed, inner_op0, inner_op1, new_op0, new_op1, tmp;
7802 decomposed = XEXP (x, n);
7803 if (!ARITHMETIC_P (decomposed))
7806 mode = GET_MODE (x);
7807 outer_code = GET_CODE (x);
7808 distributed = XEXP (x, !n);
7810 inner_code = GET_CODE (decomposed);
7811 inner_op0 = XEXP (decomposed, 0);
7812 inner_op1 = XEXP (decomposed, 1);
7814 /* Special case (and (xor B C) (not A)), which is equivalent to
7815 (xor (ior A B) (ior A C)) */
7816 if (outer_code == AND && inner_code == XOR && GET_CODE (distributed) == NOT)
7818 distributed = XEXP (distributed, 0);
7824 /* Distribute the second term. */
7825 new_op0 = simplify_gen_binary (outer_code, mode, inner_op0, distributed);
7826 new_op1 = simplify_gen_binary (outer_code, mode, inner_op1, distributed);
7830 /* Distribute the first term. */
7831 new_op0 = simplify_gen_binary (outer_code, mode, distributed, inner_op0);
7832 new_op1 = simplify_gen_binary (outer_code, mode, distributed, inner_op1);
7835 tmp = apply_distributive_law (simplify_gen_binary (inner_code, mode,
7837 if (GET_CODE (tmp) != outer_code
7838 && rtx_cost (tmp, SET) < rtx_cost (x, SET))
7844 /* We have X, a logical `and' of VAROP with the constant CONSTOP, to be done
7847 Return an equivalent form, if different from X. Otherwise, return X. If
7848 X is zero, we are to always construct the equivalent form. */
7851 simplify_and_const_int (rtx x, enum machine_mode mode, rtx varop,
7852 unsigned HOST_WIDE_INT constop)
7854 unsigned HOST_WIDE_INT nonzero;
7857 /* Simplify VAROP knowing that we will be only looking at some of the
7860 Note by passing in CONSTOP, we guarantee that the bits not set in
7861 CONSTOP are not significant and will never be examined. We must
7862 ensure that is the case by explicitly masking out those bits
7863 before returning. */
7864 varop = force_to_mode (varop, mode, constop, 0);
7866 /* If VAROP is a CLOBBER, we will fail so return it. */
7867 if (GET_CODE (varop) == CLOBBER)
7870 /* If VAROP is a CONST_INT, then we need to apply the mask in CONSTOP
7871 to VAROP and return the new constant. */
7872 if (GET_CODE (varop) == CONST_INT)
7873 return gen_int_mode (INTVAL (varop) & constop, mode);
7875 /* See what bits may be nonzero in VAROP. Unlike the general case of
7876 a call to nonzero_bits, here we don't care about bits outside
7879 nonzero = nonzero_bits (varop, mode) & GET_MODE_MASK (mode);
7881 /* Turn off all bits in the constant that are known to already be zero.
7882 Thus, if the AND isn't needed at all, we will have CONSTOP == NONZERO_BITS
7883 which is tested below. */
7887 /* If we don't have any bits left, return zero. */
7891 /* If VAROP is a NEG of something known to be zero or 1 and CONSTOP is
7892 a power of two, we can replace this with an ASHIFT. */
7893 if (GET_CODE (varop) == NEG && nonzero_bits (XEXP (varop, 0), mode) == 1
7894 && (i = exact_log2 (constop)) >= 0)
7895 return simplify_shift_const (NULL_RTX, ASHIFT, mode, XEXP (varop, 0), i);
7897 /* If VAROP is an IOR or XOR, apply the AND to both branches of the IOR
7898 or XOR, then try to apply the distributive law. This may eliminate
7899 operations if either branch can be simplified because of the AND.
7900 It may also make some cases more complex, but those cases probably
7901 won't match a pattern either with or without this. */
7903 if (GET_CODE (varop) == IOR || GET_CODE (varop) == XOR)
7907 apply_distributive_law
7908 (simplify_gen_binary (GET_CODE (varop), GET_MODE (varop),
7909 simplify_and_const_int (NULL_RTX,
7913 simplify_and_const_int (NULL_RTX,
7918 /* If VAROP is PLUS, and the constant is a mask of low bits, distribute
7919 the AND and see if one of the operands simplifies to zero. If so, we
7920 may eliminate it. */
7922 if (GET_CODE (varop) == PLUS
7923 && exact_log2 (constop + 1) >= 0)
7927 o0 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 0), constop);
7928 o1 = simplify_and_const_int (NULL_RTX, mode, XEXP (varop, 1), constop);
7929 if (o0 == const0_rtx)
7931 if (o1 == const0_rtx)
7935 /* Get VAROP in MODE. Try to get a SUBREG if not. Don't make a new SUBREG
7936 if we already had one (just check for the simplest cases). */
7937 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
7938 && GET_MODE (XEXP (x, 0)) == mode
7939 && SUBREG_REG (XEXP (x, 0)) == varop)
7940 varop = XEXP (x, 0);
7942 varop = gen_lowpart (mode, varop);
7944 /* If we can't make the SUBREG, try to return what we were given. */
7945 if (GET_CODE (varop) == CLOBBER)
7946 return x ? x : varop;
7948 /* If we are only masking insignificant bits, return VAROP. */
7949 if (constop == nonzero)
7953 /* Otherwise, return an AND. */
7954 constop = trunc_int_for_mode (constop, mode);
7955 /* See how much, if any, of X we can use. */
7956 if (x == 0 || GET_CODE (x) != AND || GET_MODE (x) != mode)
7957 x = simplify_gen_binary (AND, mode, varop, GEN_INT (constop));
7961 if (GET_CODE (XEXP (x, 1)) != CONST_INT
7962 || (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) != constop)
7963 SUBST (XEXP (x, 1), GEN_INT (constop));
7965 SUBST (XEXP (x, 0), varop);
7972 /* Given a REG, X, compute which bits in X can be nonzero.
7973 We don't care about bits outside of those defined in MODE.
7975 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is
7976 a shift, AND, or zero_extract, we can do better. */
7979 reg_nonzero_bits_for_combine (rtx x, enum machine_mode mode,
7980 rtx known_x ATTRIBUTE_UNUSED,
7981 enum machine_mode known_mode ATTRIBUTE_UNUSED,
7982 unsigned HOST_WIDE_INT known_ret ATTRIBUTE_UNUSED,
7983 unsigned HOST_WIDE_INT *nonzero)
7987 /* If X is a register whose nonzero bits value is current, use it.
7988 Otherwise, if X is a register whose value we can find, use that
7989 value. Otherwise, use the previously-computed global nonzero bits
7990 for this register. */
7992 if (reg_stat[REGNO (x)].last_set_value != 0
7993 && (reg_stat[REGNO (x)].last_set_mode == mode
7994 || (GET_MODE_CLASS (reg_stat[REGNO (x)].last_set_mode) == MODE_INT
7995 && GET_MODE_CLASS (mode) == MODE_INT))
7996 && (reg_stat[REGNO (x)].last_set_label == label_tick
7997 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
7998 && REG_N_SETS (REGNO (x)) == 1
7999 && ! REGNO_REG_SET_P
8000 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8002 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8004 *nonzero &= reg_stat[REGNO (x)].last_set_nonzero_bits;
8008 tem = get_last_value (x);
8012 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND
8013 /* If X is narrower than MODE and TEM is a non-negative
8014 constant that would appear negative in the mode of X,
8015 sign-extend it for use in reg_nonzero_bits because some
8016 machines (maybe most) will actually do the sign-extension
8017 and this is the conservative approach.
8019 ??? For 2.5, try to tighten up the MD files in this regard
8020 instead of this kludge. */
8022 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode)
8023 && GET_CODE (tem) == CONST_INT
8025 && 0 != (INTVAL (tem)
8026 & ((HOST_WIDE_INT) 1
8027 << (GET_MODE_BITSIZE (GET_MODE (x)) - 1))))
8028 tem = GEN_INT (INTVAL (tem)
8029 | ((HOST_WIDE_INT) (-1)
8030 << GET_MODE_BITSIZE (GET_MODE (x))));
8034 else if (nonzero_sign_valid && reg_stat[REGNO (x)].nonzero_bits)
8036 unsigned HOST_WIDE_INT mask = reg_stat[REGNO (x)].nonzero_bits;
8038 if (GET_MODE_BITSIZE (GET_MODE (x)) < GET_MODE_BITSIZE (mode))
8039 /* We don't know anything about the upper bits. */
8040 mask |= GET_MODE_MASK (mode) ^ GET_MODE_MASK (GET_MODE (x));
8047 /* Return the number of bits at the high-order end of X that are known to
8048 be equal to the sign bit. X will be used in mode MODE; if MODE is
8049 VOIDmode, X will be used in its own mode. The returned value will always
8050 be between 1 and the number of bits in MODE. */
8053 reg_num_sign_bit_copies_for_combine (rtx x, enum machine_mode mode,
8054 rtx known_x ATTRIBUTE_UNUSED,
8055 enum machine_mode known_mode
8057 unsigned int known_ret ATTRIBUTE_UNUSED,
8058 unsigned int *result)
8062 if (reg_stat[REGNO (x)].last_set_value != 0
8063 && reg_stat[REGNO (x)].last_set_mode == mode
8064 && (reg_stat[REGNO (x)].last_set_label == label_tick
8065 || (REGNO (x) >= FIRST_PSEUDO_REGISTER
8066 && REG_N_SETS (REGNO (x)) == 1
8067 && ! REGNO_REG_SET_P
8068 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
8070 && INSN_CUID (reg_stat[REGNO (x)].last_set) < subst_low_cuid)
8072 *result = reg_stat[REGNO (x)].last_set_sign_bit_copies;
8076 tem = get_last_value (x);
8080 if (nonzero_sign_valid && reg_stat[REGNO (x)].sign_bit_copies != 0
8081 && GET_MODE_BITSIZE (GET_MODE (x)) == GET_MODE_BITSIZE (mode))
8082 *result = reg_stat[REGNO (x)].sign_bit_copies;
8087 /* Return the number of "extended" bits there are in X, when interpreted
8088 as a quantity in MODE whose signedness is indicated by UNSIGNEDP. For
8089 unsigned quantities, this is the number of high-order zero bits.
8090 For signed quantities, this is the number of copies of the sign bit
8091 minus 1. In both case, this function returns the number of "spare"
8092 bits. For example, if two quantities for which this function returns
8093 at least 1 are added, the addition is known not to overflow.
8095 This function will always return 0 unless called during combine, which
8096 implies that it must be called from a define_split. */
8099 extended_count (rtx x, enum machine_mode mode, int unsignedp)
8101 if (nonzero_sign_valid == 0)
8105 ? (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
8106 ? (unsigned int) (GET_MODE_BITSIZE (mode) - 1
8107 - floor_log2 (nonzero_bits (x, mode)))
8109 : num_sign_bit_copies (x, mode) - 1);
8112 /* This function is called from `simplify_shift_const' to merge two
8113 outer operations. Specifically, we have already found that we need
8114 to perform operation *POP0 with constant *PCONST0 at the outermost
8115 position. We would now like to also perform OP1 with constant CONST1
8116 (with *POP0 being done last).
8118 Return 1 if we can do the operation and update *POP0 and *PCONST0 with
8119 the resulting operation. *PCOMP_P is set to 1 if we would need to
8120 complement the innermost operand, otherwise it is unchanged.
8122 MODE is the mode in which the operation will be done. No bits outside
8123 the width of this mode matter. It is assumed that the width of this mode
8124 is smaller than or equal to HOST_BITS_PER_WIDE_INT.
8126 If *POP0 or OP1 are UNKNOWN, it means no operation is required. Only NEG, PLUS,
8127 IOR, XOR, and AND are supported. We may set *POP0 to SET if the proper
8128 result is simply *PCONST0.
8130 If the resulting operation cannot be expressed as one operation, we
8131 return 0 and do not change *POP0, *PCONST0, and *PCOMP_P. */
8134 merge_outer_ops (enum rtx_code *pop0, HOST_WIDE_INT *pconst0, enum rtx_code op1, HOST_WIDE_INT const1, enum machine_mode mode, int *pcomp_p)
8136 enum rtx_code op0 = *pop0;
8137 HOST_WIDE_INT const0 = *pconst0;
8139 const0 &= GET_MODE_MASK (mode);
8140 const1 &= GET_MODE_MASK (mode);
8142 /* If OP0 is an AND, clear unimportant bits in CONST1. */
8146 /* If OP0 or OP1 is UNKNOWN, this is easy. Similarly if they are the same or
8149 if (op1 == UNKNOWN || op0 == SET)
8152 else if (op0 == UNKNOWN)
8153 op0 = op1, const0 = const1;
8155 else if (op0 == op1)
8179 /* Otherwise, if either is a PLUS or NEG, we can't do anything. */
8180 else if (op0 == PLUS || op1 == PLUS || op0 == NEG || op1 == NEG)
8183 /* If the two constants aren't the same, we can't do anything. The
8184 remaining six cases can all be done. */
8185 else if (const0 != const1)
8193 /* (a & b) | b == b */
8195 else /* op1 == XOR */
8196 /* (a ^ b) | b == a | b */
8202 /* (a & b) ^ b == (~a) & b */
8203 op0 = AND, *pcomp_p = 1;
8204 else /* op1 == IOR */
8205 /* (a | b) ^ b == a & ~b */
8206 op0 = AND, const0 = ~const0;
8211 /* (a | b) & b == b */
8213 else /* op1 == XOR */
8214 /* (a ^ b) & b) == (~a) & b */
8221 /* Check for NO-OP cases. */
8222 const0 &= GET_MODE_MASK (mode);
8224 && (op0 == IOR || op0 == XOR || op0 == PLUS))
8226 else if (const0 == 0 && op0 == AND)
8228 else if ((unsigned HOST_WIDE_INT) const0 == GET_MODE_MASK (mode)
8232 /* ??? Slightly redundant with the above mask, but not entirely.
8233 Moving this above means we'd have to sign-extend the mode mask
8234 for the final test. */
8235 const0 = trunc_int_for_mode (const0, mode);
8243 /* Simplify a shift of VAROP by COUNT bits. CODE says what kind of shift.
8244 The result of the shift is RESULT_MODE. X, if nonzero, is an expression
8245 that we started with.
8247 The shift is normally computed in the widest mode we find in VAROP, as
8248 long as it isn't a different number of words than RESULT_MODE. Exceptions
8249 are ASHIFTRT and ROTATE, which are always done in their original mode, */
8252 simplify_shift_const (rtx x, enum rtx_code code,
8253 enum machine_mode result_mode, rtx varop,
8256 enum rtx_code orig_code = code;
8259 enum machine_mode mode = result_mode;
8260 enum machine_mode shift_mode, tmode;
8261 unsigned int mode_words
8262 = (GET_MODE_SIZE (mode) + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD;
8263 /* We form (outer_op (code varop count) (outer_const)). */
8264 enum rtx_code outer_op = UNKNOWN;
8265 HOST_WIDE_INT outer_const = 0;
8267 int complement_p = 0;
8270 /* Make sure and truncate the "natural" shift on the way in. We don't
8271 want to do this inside the loop as it makes it more difficult to
8273 if (SHIFT_COUNT_TRUNCATED)
8274 orig_count &= GET_MODE_BITSIZE (mode) - 1;
8276 /* If we were given an invalid count, don't do anything except exactly
8277 what was requested. */
8279 if (orig_count < 0 || orig_count >= (int) GET_MODE_BITSIZE (mode))
8284 return gen_rtx_fmt_ee (code, mode, varop, GEN_INT (orig_count));
8289 /* Unless one of the branches of the `if' in this loop does a `continue',
8290 we will `break' the loop after the `if'. */
8294 /* If we have an operand of (clobber (const_int 0)), just return that
8296 if (GET_CODE (varop) == CLOBBER)
8299 /* If we discovered we had to complement VAROP, leave. Making a NOT
8300 here would cause an infinite loop. */
8304 /* Convert ROTATERT to ROTATE. */
8305 if (code == ROTATERT)
8307 unsigned int bitsize = GET_MODE_BITSIZE (result_mode);;
8309 if (VECTOR_MODE_P (result_mode))
8310 count = bitsize / GET_MODE_NUNITS (result_mode) - count;
8312 count = bitsize - count;
8315 /* We need to determine what mode we will do the shift in. If the
8316 shift is a right shift or a ROTATE, we must always do it in the mode
8317 it was originally done in. Otherwise, we can do it in MODE, the
8318 widest mode encountered. */
8320 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8321 ? result_mode : mode);
8323 /* Handle cases where the count is greater than the size of the mode
8324 minus 1. For ASHIFT, use the size minus one as the count (this can
8325 occur when simplifying (lshiftrt (ashiftrt ..))). For rotates,
8326 take the count modulo the size. For other shifts, the result is
8329 Since these shifts are being produced by the compiler by combining
8330 multiple operations, each of which are defined, we know what the
8331 result is supposed to be. */
8333 if (count > (unsigned int) (GET_MODE_BITSIZE (shift_mode) - 1))
8335 if (code == ASHIFTRT)
8336 count = GET_MODE_BITSIZE (shift_mode) - 1;
8337 else if (code == ROTATE || code == ROTATERT)
8338 count %= GET_MODE_BITSIZE (shift_mode);
8341 /* We can't simply return zero because there may be an
8349 /* An arithmetic right shift of a quantity known to be -1 or 0
8351 if (code == ASHIFTRT
8352 && (num_sign_bit_copies (varop, shift_mode)
8353 == GET_MODE_BITSIZE (shift_mode)))
8359 /* If we are doing an arithmetic right shift and discarding all but
8360 the sign bit copies, this is equivalent to doing a shift by the
8361 bitsize minus one. Convert it into that shift because it will often
8362 allow other simplifications. */
8364 if (code == ASHIFTRT
8365 && (count + num_sign_bit_copies (varop, shift_mode)
8366 >= GET_MODE_BITSIZE (shift_mode)))
8367 count = GET_MODE_BITSIZE (shift_mode) - 1;
8369 /* We simplify the tests below and elsewhere by converting
8370 ASHIFTRT to LSHIFTRT if we know the sign bit is clear.
8371 `make_compound_operation' will convert it to an ASHIFTRT for
8372 those machines (such as VAX) that don't have an LSHIFTRT. */
8373 if (GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8375 && ((nonzero_bits (varop, shift_mode)
8376 & ((HOST_WIDE_INT) 1 << (GET_MODE_BITSIZE (shift_mode) - 1)))
8380 if (code == LSHIFTRT
8381 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8382 && !(nonzero_bits (varop, shift_mode) >> count))
8385 && GET_MODE_BITSIZE (shift_mode) <= HOST_BITS_PER_WIDE_INT
8386 && !((nonzero_bits (varop, shift_mode) << count)
8387 & GET_MODE_MASK (shift_mode)))
8390 switch (GET_CODE (varop))
8396 new = expand_compound_operation (varop);
8405 /* If we have (xshiftrt (mem ...) C) and C is MODE_WIDTH
8406 minus the width of a smaller mode, we can do this with a
8407 SIGN_EXTEND or ZERO_EXTEND from the narrower memory location. */
8408 if ((code == ASHIFTRT || code == LSHIFTRT)
8409 && ! mode_dependent_address_p (XEXP (varop, 0))
8410 && ! MEM_VOLATILE_P (varop)
8411 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8412 MODE_INT, 1)) != BLKmode)
8414 new = adjust_address_nv (varop, tmode,
8415 BYTES_BIG_ENDIAN ? 0
8416 : count / BITS_PER_UNIT);
8418 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8419 : ZERO_EXTEND, mode, new);
8426 /* Similar to the case above, except that we can only do this if
8427 the resulting mode is the same as that of the underlying
8428 MEM and adjust the address depending on the *bits* endianness
8429 because of the way that bit-field extract insns are defined. */
8430 if ((code == ASHIFTRT || code == LSHIFTRT)
8431 && (tmode = mode_for_size (GET_MODE_BITSIZE (mode) - count,
8432 MODE_INT, 1)) != BLKmode
8433 && tmode == GET_MODE (XEXP (varop, 0)))
8435 if (BITS_BIG_ENDIAN)
8436 new = XEXP (varop, 0);
8439 new = copy_rtx (XEXP (varop, 0));
8440 SUBST (XEXP (new, 0),
8441 plus_constant (XEXP (new, 0),
8442 count / BITS_PER_UNIT));
8445 varop = gen_rtx_fmt_e (code == ASHIFTRT ? SIGN_EXTEND
8446 : ZERO_EXTEND, mode, new);
8453 /* If VAROP is a SUBREG, strip it as long as the inner operand has
8454 the same number of words as what we've seen so far. Then store
8455 the widest mode in MODE. */
8456 if (subreg_lowpart_p (varop)
8457 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8458 > GET_MODE_SIZE (GET_MODE (varop)))
8459 && (unsigned int) ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (varop)))
8460 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD)
8463 varop = SUBREG_REG (varop);
8464 if (GET_MODE_SIZE (GET_MODE (varop)) > GET_MODE_SIZE (mode))
8465 mode = GET_MODE (varop);
8471 /* Some machines use MULT instead of ASHIFT because MULT
8472 is cheaper. But it is still better on those machines to
8473 merge two shifts into one. */
8474 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8475 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8478 = simplify_gen_binary (ASHIFT, GET_MODE (varop),
8480 GEN_INT (exact_log2 (
8481 INTVAL (XEXP (varop, 1)))));
8487 /* Similar, for when divides are cheaper. */
8488 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8489 && exact_log2 (INTVAL (XEXP (varop, 1))) >= 0)
8492 = simplify_gen_binary (LSHIFTRT, GET_MODE (varop),
8494 GEN_INT (exact_log2 (
8495 INTVAL (XEXP (varop, 1)))));
8501 /* If we are extracting just the sign bit of an arithmetic
8502 right shift, that shift is not needed. However, the sign
8503 bit of a wider mode may be different from what would be
8504 interpreted as the sign bit in a narrower mode, so, if
8505 the result is narrower, don't discard the shift. */
8506 if (code == LSHIFTRT
8507 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8508 && (GET_MODE_BITSIZE (result_mode)
8509 >= GET_MODE_BITSIZE (GET_MODE (varop))))
8511 varop = XEXP (varop, 0);
8515 /* ... fall through ... */
8520 /* Here we have two nested shifts. The result is usually the
8521 AND of a new shift with a mask. We compute the result below. */
8522 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8523 && INTVAL (XEXP (varop, 1)) >= 0
8524 && INTVAL (XEXP (varop, 1)) < GET_MODE_BITSIZE (GET_MODE (varop))
8525 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8526 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
8528 enum rtx_code first_code = GET_CODE (varop);
8529 unsigned int first_count = INTVAL (XEXP (varop, 1));
8530 unsigned HOST_WIDE_INT mask;
8533 /* We have one common special case. We can't do any merging if
8534 the inner code is an ASHIFTRT of a smaller mode. However, if
8535 we have (ashift:M1 (subreg:M1 (ashiftrt:M2 FOO C1) 0) C2)
8536 with C2 == GET_MODE_BITSIZE (M1) - GET_MODE_BITSIZE (M2),
8537 we can convert it to
8538 (ashiftrt:M1 (ashift:M1 (and:M1 (subreg:M1 FOO 0 C2) C3) C1).
8539 This simplifies certain SIGN_EXTEND operations. */
8540 if (code == ASHIFT && first_code == ASHIFTRT
8541 && count == (unsigned int)
8542 (GET_MODE_BITSIZE (result_mode)
8543 - GET_MODE_BITSIZE (GET_MODE (varop))))
8545 /* C3 has the low-order C1 bits zero. */
8547 mask = (GET_MODE_MASK (mode)
8548 & ~(((HOST_WIDE_INT) 1 << first_count) - 1));
8550 varop = simplify_and_const_int (NULL_RTX, result_mode,
8551 XEXP (varop, 0), mask);
8552 varop = simplify_shift_const (NULL_RTX, ASHIFT, result_mode,
8554 count = first_count;
8559 /* If this was (ashiftrt (ashift foo C1) C2) and FOO has more
8560 than C1 high-order bits equal to the sign bit, we can convert
8561 this to either an ASHIFT or an ASHIFTRT depending on the
8564 We cannot do this if VAROP's mode is not SHIFT_MODE. */
8566 if (code == ASHIFTRT && first_code == ASHIFT
8567 && GET_MODE (varop) == shift_mode
8568 && (num_sign_bit_copies (XEXP (varop, 0), shift_mode)
8571 varop = XEXP (varop, 0);
8573 signed_count = count - first_count;
8574 if (signed_count < 0)
8575 count = -signed_count, code = ASHIFT;
8577 count = signed_count;
8582 /* There are some cases we can't do. If CODE is ASHIFTRT,
8583 we can only do this if FIRST_CODE is also ASHIFTRT.
8585 We can't do the case when CODE is ROTATE and FIRST_CODE is
8588 If the mode of this shift is not the mode of the outer shift,
8589 we can't do this if either shift is a right shift or ROTATE.
8591 Finally, we can't do any of these if the mode is too wide
8592 unless the codes are the same.
8594 Handle the case where the shift codes are the same
8597 if (code == first_code)
8599 if (GET_MODE (varop) != result_mode
8600 && (code == ASHIFTRT || code == LSHIFTRT
8604 count += first_count;
8605 varop = XEXP (varop, 0);
8609 if (code == ASHIFTRT
8610 || (code == ROTATE && first_code == ASHIFTRT)
8611 || GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT
8612 || (GET_MODE (varop) != result_mode
8613 && (first_code == ASHIFTRT || first_code == LSHIFTRT
8614 || first_code == ROTATE
8615 || code == ROTATE)))
8618 /* To compute the mask to apply after the shift, shift the
8619 nonzero bits of the inner shift the same way the
8620 outer shift will. */
8622 mask_rtx = GEN_INT (nonzero_bits (varop, GET_MODE (varop)));
8625 = simplify_binary_operation (code, result_mode, mask_rtx,
8628 /* Give up if we can't compute an outer operation to use. */
8630 || GET_CODE (mask_rtx) != CONST_INT
8631 || ! merge_outer_ops (&outer_op, &outer_const, AND,
8633 result_mode, &complement_p))
8636 /* If the shifts are in the same direction, we add the
8637 counts. Otherwise, we subtract them. */
8638 signed_count = count;
8639 if ((code == ASHIFTRT || code == LSHIFTRT)
8640 == (first_code == ASHIFTRT || first_code == LSHIFTRT))
8641 signed_count += first_count;
8643 signed_count -= first_count;
8645 /* If COUNT is positive, the new shift is usually CODE,
8646 except for the two exceptions below, in which case it is
8647 FIRST_CODE. If the count is negative, FIRST_CODE should
8649 if (signed_count > 0
8650 && ((first_code == ROTATE && code == ASHIFT)
8651 || (first_code == ASHIFTRT && code == LSHIFTRT)))
8652 code = first_code, count = signed_count;
8653 else if (signed_count < 0)
8654 code = first_code, count = -signed_count;
8656 count = signed_count;
8658 varop = XEXP (varop, 0);
8662 /* If we have (A << B << C) for any shift, we can convert this to
8663 (A << C << B). This wins if A is a constant. Only try this if
8664 B is not a constant. */
8666 else if (GET_CODE (varop) == code
8667 && GET_CODE (XEXP (varop, 1)) != CONST_INT
8669 = simplify_binary_operation (code, mode,
8673 varop = gen_rtx_fmt_ee (code, mode, new, XEXP (varop, 1));
8680 /* Make this fit the case below. */
8681 varop = gen_rtx_XOR (mode, XEXP (varop, 0),
8682 GEN_INT (GET_MODE_MASK (mode)));
8688 /* If we have (xshiftrt (ior (plus X (const_int -1)) X) C)
8689 with C the size of VAROP - 1 and the shift is logical if
8690 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8691 we have an (le X 0) operation. If we have an arithmetic shift
8692 and STORE_FLAG_VALUE is 1 or we have a logical shift with
8693 STORE_FLAG_VALUE of -1, we have a (neg (le X 0)) operation. */
8695 if (GET_CODE (varop) == IOR && GET_CODE (XEXP (varop, 0)) == PLUS
8696 && XEXP (XEXP (varop, 0), 1) == constm1_rtx
8697 && (STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8698 && (code == LSHIFTRT || code == ASHIFTRT)
8699 && count == (unsigned int)
8700 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8701 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8704 varop = gen_rtx_LE (GET_MODE (varop), XEXP (varop, 1),
8707 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8708 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8713 /* If we have (shift (logical)), move the logical to the outside
8714 to allow it to possibly combine with another logical and the
8715 shift to combine with another shift. This also canonicalizes to
8716 what a ZERO_EXTRACT looks like. Also, some machines have
8717 (and (shift)) insns. */
8719 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8720 /* We can't do this if we have (ashiftrt (xor)) and the
8721 constant has its sign bit set in shift_mode. */
8722 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8723 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8725 && (new = simplify_binary_operation (code, result_mode,
8727 GEN_INT (count))) != 0
8728 && GET_CODE (new) == CONST_INT
8729 && merge_outer_ops (&outer_op, &outer_const, GET_CODE (varop),
8730 INTVAL (new), result_mode, &complement_p))
8732 varop = XEXP (varop, 0);
8736 /* If we can't do that, try to simplify the shift in each arm of the
8737 logical expression, make a new logical expression, and apply
8738 the inverse distributive law. This also can't be done
8739 for some (ashiftrt (xor)). */
8740 if (GET_CODE (XEXP (varop, 1)) == CONST_INT
8741 && !(code == ASHIFTRT && GET_CODE (varop) == XOR
8742 && 0 > trunc_int_for_mode (INTVAL (XEXP (varop, 1)),
8745 rtx lhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8746 XEXP (varop, 0), count);
8747 rtx rhs = simplify_shift_const (NULL_RTX, code, shift_mode,
8748 XEXP (varop, 1), count);
8750 varop = simplify_gen_binary (GET_CODE (varop), shift_mode,
8752 varop = apply_distributive_law (varop);
8760 /* Convert (lshiftrt (eq FOO 0) C) to (xor FOO 1) if STORE_FLAG_VALUE
8761 says that the sign bit can be tested, FOO has mode MODE, C is
8762 GET_MODE_BITSIZE (MODE) - 1, and FOO has only its low-order bit
8763 that may be nonzero. */
8764 if (code == LSHIFTRT
8765 && XEXP (varop, 1) == const0_rtx
8766 && GET_MODE (XEXP (varop, 0)) == result_mode
8767 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8768 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8769 && ((STORE_FLAG_VALUE
8770 & ((HOST_WIDE_INT) 1
8771 < (GET_MODE_BITSIZE (result_mode) - 1))))
8772 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8773 && merge_outer_ops (&outer_op, &outer_const, XOR,
8774 (HOST_WIDE_INT) 1, result_mode,
8777 varop = XEXP (varop, 0);
8784 /* (lshiftrt (neg A) C) where A is either 0 or 1 and C is one less
8785 than the number of bits in the mode is equivalent to A. */
8786 if (code == LSHIFTRT
8787 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8788 && nonzero_bits (XEXP (varop, 0), result_mode) == 1)
8790 varop = XEXP (varop, 0);
8795 /* NEG commutes with ASHIFT since it is multiplication. Move the
8796 NEG outside to allow shifts to combine. */
8798 && merge_outer_ops (&outer_op, &outer_const, NEG,
8799 (HOST_WIDE_INT) 0, result_mode,
8802 varop = XEXP (varop, 0);
8808 /* (lshiftrt (plus A -1) C) where A is either 0 or 1 and C
8809 is one less than the number of bits in the mode is
8810 equivalent to (xor A 1). */
8811 if (code == LSHIFTRT
8812 && count == (unsigned int) (GET_MODE_BITSIZE (result_mode) - 1)
8813 && XEXP (varop, 1) == constm1_rtx
8814 && nonzero_bits (XEXP (varop, 0), result_mode) == 1
8815 && merge_outer_ops (&outer_op, &outer_const, XOR,
8816 (HOST_WIDE_INT) 1, result_mode,
8820 varop = XEXP (varop, 0);
8824 /* If we have (xshiftrt (plus FOO BAR) C), and the only bits
8825 that might be nonzero in BAR are those being shifted out and those
8826 bits are known zero in FOO, we can replace the PLUS with FOO.
8827 Similarly in the other operand order. This code occurs when
8828 we are computing the size of a variable-size array. */
8830 if ((code == ASHIFTRT || code == LSHIFTRT)
8831 && count < HOST_BITS_PER_WIDE_INT
8832 && nonzero_bits (XEXP (varop, 1), result_mode) >> count == 0
8833 && (nonzero_bits (XEXP (varop, 1), result_mode)
8834 & nonzero_bits (XEXP (varop, 0), result_mode)) == 0)
8836 varop = XEXP (varop, 0);
8839 else if ((code == ASHIFTRT || code == LSHIFTRT)
8840 && count < HOST_BITS_PER_WIDE_INT
8841 && GET_MODE_BITSIZE (result_mode) <= HOST_BITS_PER_WIDE_INT
8842 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8844 && 0 == (nonzero_bits (XEXP (varop, 0), result_mode)
8845 & nonzero_bits (XEXP (varop, 1),
8848 varop = XEXP (varop, 1);
8852 /* (ashift (plus foo C) N) is (plus (ashift foo N) C'). */
8854 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8855 && (new = simplify_binary_operation (ASHIFT, result_mode,
8857 GEN_INT (count))) != 0
8858 && GET_CODE (new) == CONST_INT
8859 && merge_outer_ops (&outer_op, &outer_const, PLUS,
8860 INTVAL (new), result_mode, &complement_p))
8862 varop = XEXP (varop, 0);
8866 /* Check for 'PLUS signbit', which is the canonical form of 'XOR
8867 signbit', and attempt to change the PLUS to an XOR and move it to
8868 the outer operation as is done above in the AND/IOR/XOR case
8869 leg for shift(logical). See details in logical handling above
8870 for reasoning in doing so. */
8871 if (code == LSHIFTRT
8872 && GET_CODE (XEXP (varop, 1)) == CONST_INT
8873 && mode_signbit_p (result_mode, XEXP (varop, 1))
8874 && (new = simplify_binary_operation (code, result_mode,
8876 GEN_INT (count))) != 0
8877 && GET_CODE (new) == CONST_INT
8878 && merge_outer_ops (&outer_op, &outer_const, XOR,
8879 INTVAL (new), result_mode, &complement_p))
8881 varop = XEXP (varop, 0);
8888 /* If we have (xshiftrt (minus (ashiftrt X C)) X) C)
8889 with C the size of VAROP - 1 and the shift is logical if
8890 STORE_FLAG_VALUE is 1 and arithmetic if STORE_FLAG_VALUE is -1,
8891 we have a (gt X 0) operation. If the shift is arithmetic with
8892 STORE_FLAG_VALUE of 1 or logical with STORE_FLAG_VALUE == -1,
8893 we have a (neg (gt X 0)) operation. */
8895 if ((STORE_FLAG_VALUE == 1 || STORE_FLAG_VALUE == -1)
8896 && GET_CODE (XEXP (varop, 0)) == ASHIFTRT
8897 && count == (unsigned int)
8898 (GET_MODE_BITSIZE (GET_MODE (varop)) - 1)
8899 && (code == LSHIFTRT || code == ASHIFTRT)
8900 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8901 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (varop, 0), 1))
8903 && rtx_equal_p (XEXP (XEXP (varop, 0), 0), XEXP (varop, 1)))
8906 varop = gen_rtx_GT (GET_MODE (varop), XEXP (varop, 1),
8909 if (STORE_FLAG_VALUE == 1 ? code == ASHIFTRT : code == LSHIFTRT)
8910 varop = gen_rtx_NEG (GET_MODE (varop), varop);
8917 /* Change (lshiftrt (truncate (lshiftrt))) to (truncate (lshiftrt))
8918 if the truncate does not affect the value. */
8919 if (code == LSHIFTRT
8920 && GET_CODE (XEXP (varop, 0)) == LSHIFTRT
8921 && GET_CODE (XEXP (XEXP (varop, 0), 1)) == CONST_INT
8922 && (INTVAL (XEXP (XEXP (varop, 0), 1))
8923 >= (GET_MODE_BITSIZE (GET_MODE (XEXP (varop, 0)))
8924 - GET_MODE_BITSIZE (GET_MODE (varop)))))
8926 rtx varop_inner = XEXP (varop, 0);
8929 = gen_rtx_LSHIFTRT (GET_MODE (varop_inner),
8930 XEXP (varop_inner, 0),
8932 (count + INTVAL (XEXP (varop_inner, 1))));
8933 varop = gen_rtx_TRUNCATE (GET_MODE (varop), varop_inner);
8946 /* We need to determine what mode to do the shift in. If the shift is
8947 a right shift or ROTATE, we must always do it in the mode it was
8948 originally done in. Otherwise, we can do it in MODE, the widest mode
8949 encountered. The code we care about is that of the shift that will
8950 actually be done, not the shift that was originally requested. */
8952 = (code == ASHIFTRT || code == LSHIFTRT || code == ROTATE
8953 ? result_mode : mode);
8955 /* We have now finished analyzing the shift. The result should be
8956 a shift of type CODE with SHIFT_MODE shifting VAROP COUNT places. If
8957 OUTER_OP is non-UNKNOWN, it is an operation that needs to be applied
8958 to the result of the shift. OUTER_CONST is the relevant constant,
8959 but we must turn off all bits turned off in the shift.
8961 If we were passed a value for X, see if we can use any pieces of
8962 it. If not, make new rtx. */
8964 if (x && GET_RTX_CLASS (GET_CODE (x)) == RTX_BIN_ARITH
8965 && GET_CODE (XEXP (x, 1)) == CONST_INT
8966 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (x, 1)) == count)
8967 const_rtx = XEXP (x, 1);
8969 const_rtx = GEN_INT (count);
8971 if (x && GET_CODE (XEXP (x, 0)) == SUBREG
8972 && GET_MODE (XEXP (x, 0)) == shift_mode
8973 && SUBREG_REG (XEXP (x, 0)) == varop)
8974 varop = XEXP (x, 0);
8975 else if (GET_MODE (varop) != shift_mode)
8976 varop = gen_lowpart (shift_mode, varop);
8978 /* If we can't make the SUBREG, try to return what we were given. */
8979 if (GET_CODE (varop) == CLOBBER)
8980 return x ? x : varop;
8982 new = simplify_binary_operation (code, shift_mode, varop, const_rtx);
8986 x = gen_rtx_fmt_ee (code, shift_mode, varop, const_rtx);
8988 /* If we have an outer operation and we just made a shift, it is
8989 possible that we could have simplified the shift were it not
8990 for the outer operation. So try to do the simplification
8993 if (outer_op != UNKNOWN && GET_CODE (x) == code
8994 && GET_CODE (XEXP (x, 1)) == CONST_INT)
8995 x = simplify_shift_const (x, code, shift_mode, XEXP (x, 0),
8996 INTVAL (XEXP (x, 1)));
8998 /* If we were doing an LSHIFTRT in a wider mode than it was originally,
8999 turn off all the bits that the shift would have turned off. */
9000 if (orig_code == LSHIFTRT && result_mode != shift_mode)
9001 x = simplify_and_const_int (NULL_RTX, shift_mode, x,
9002 GET_MODE_MASK (result_mode) >> orig_count);
9004 /* Do the remainder of the processing in RESULT_MODE. */
9005 x = gen_lowpart (result_mode, x);
9007 /* If COMPLEMENT_P is set, we have to complement X before doing the outer
9010 x = simplify_gen_unary (NOT, result_mode, x, result_mode);
9012 if (outer_op != UNKNOWN)
9014 if (GET_MODE_BITSIZE (result_mode) < HOST_BITS_PER_WIDE_INT)
9015 outer_const = trunc_int_for_mode (outer_const, result_mode);
9017 if (outer_op == AND)
9018 x = simplify_and_const_int (NULL_RTX, result_mode, x, outer_const);
9019 else if (outer_op == SET)
9020 /* This means that we have determined that the result is
9021 equivalent to a constant. This should be rare. */
9022 x = GEN_INT (outer_const);
9023 else if (GET_RTX_CLASS (outer_op) == RTX_UNARY)
9024 x = simplify_gen_unary (outer_op, result_mode, x, result_mode);
9026 x = simplify_gen_binary (outer_op, result_mode, x,
9027 GEN_INT (outer_const));
9033 /* Like recog, but we receive the address of a pointer to a new pattern.
9034 We try to match the rtx that the pointer points to.
9035 If that fails, we may try to modify or replace the pattern,
9036 storing the replacement into the same pointer object.
9038 Modifications include deletion or addition of CLOBBERs.
9040 PNOTES is a pointer to a location where any REG_UNUSED notes added for
9041 the CLOBBERs are placed.
9043 The value is the final insn code from the pattern ultimately matched,
9047 recog_for_combine (rtx *pnewpat, rtx insn, rtx *pnotes)
9050 int insn_code_number;
9051 int num_clobbers_to_add = 0;
9054 rtx old_notes, old_pat;
9056 /* If PAT is a PARALLEL, check to see if it contains the CLOBBER
9057 we use to indicate that something didn't match. If we find such a
9058 thing, force rejection. */
9059 if (GET_CODE (pat) == PARALLEL)
9060 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--)
9061 if (GET_CODE (XVECEXP (pat, 0, i)) == CLOBBER
9062 && XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx)
9065 old_pat = PATTERN (insn);
9066 old_notes = REG_NOTES (insn);
9067 PATTERN (insn) = pat;
9068 REG_NOTES (insn) = 0;
9070 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9072 /* If it isn't, there is the possibility that we previously had an insn
9073 that clobbered some register as a side effect, but the combined
9074 insn doesn't need to do that. So try once more without the clobbers
9075 unless this represents an ASM insn. */
9077 if (insn_code_number < 0 && ! check_asm_operands (pat)
9078 && GET_CODE (pat) == PARALLEL)
9082 for (pos = 0, i = 0; i < XVECLEN (pat, 0); i++)
9083 if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER)
9086 SUBST (XVECEXP (pat, 0, pos), XVECEXP (pat, 0, i));
9090 SUBST_INT (XVECLEN (pat, 0), pos);
9093 pat = XVECEXP (pat, 0, 0);
9095 PATTERN (insn) = pat;
9096 insn_code_number = recog (pat, insn, &num_clobbers_to_add);
9098 PATTERN (insn) = old_pat;
9099 REG_NOTES (insn) = old_notes;
9101 /* Recognize all noop sets, these will be killed by followup pass. */
9102 if (insn_code_number < 0 && GET_CODE (pat) == SET && set_noop_p (pat))
9103 insn_code_number = NOOP_MOVE_INSN_CODE, num_clobbers_to_add = 0;
9105 /* If we had any clobbers to add, make a new pattern than contains
9106 them. Then check to make sure that all of them are dead. */
9107 if (num_clobbers_to_add)
9109 rtx newpat = gen_rtx_PARALLEL (VOIDmode,
9110 rtvec_alloc (GET_CODE (pat) == PARALLEL
9112 + num_clobbers_to_add)
9113 : num_clobbers_to_add + 1));
9115 if (GET_CODE (pat) == PARALLEL)
9116 for (i = 0; i < XVECLEN (pat, 0); i++)
9117 XVECEXP (newpat, 0, i) = XVECEXP (pat, 0, i);
9119 XVECEXP (newpat, 0, 0) = pat;
9121 add_clobbers (newpat, insn_code_number);
9123 for (i = XVECLEN (newpat, 0) - num_clobbers_to_add;
9124 i < XVECLEN (newpat, 0); i++)
9126 if (REG_P (XEXP (XVECEXP (newpat, 0, i), 0))
9127 && ! reg_dead_at_p (XEXP (XVECEXP (newpat, 0, i), 0), insn))
9129 notes = gen_rtx_EXPR_LIST (REG_UNUSED,
9130 XEXP (XVECEXP (newpat, 0, i), 0), notes);
9138 return insn_code_number;
9141 /* Like gen_lowpart_general but for use by combine. In combine it
9142 is not possible to create any new pseudoregs. However, it is
9143 safe to create invalid memory addresses, because combine will
9144 try to recognize them and all they will do is make the combine
9147 If for some reason this cannot do its job, an rtx
9148 (clobber (const_int 0)) is returned.
9149 An insn containing that will not be recognized. */
9152 gen_lowpart_for_combine (enum machine_mode omode, rtx x)
9154 enum machine_mode imode = GET_MODE (x);
9155 unsigned int osize = GET_MODE_SIZE (omode);
9156 unsigned int isize = GET_MODE_SIZE (imode);
9162 /* Return identity if this is a CONST or symbolic reference. */
9164 && (GET_CODE (x) == CONST
9165 || GET_CODE (x) == SYMBOL_REF
9166 || GET_CODE (x) == LABEL_REF))
9169 /* We can only support MODE being wider than a word if X is a
9170 constant integer or has a mode the same size. */
9171 if (GET_MODE_SIZE (omode) > UNITS_PER_WORD
9172 && ! ((imode == VOIDmode
9173 && (GET_CODE (x) == CONST_INT
9174 || GET_CODE (x) == CONST_DOUBLE))
9178 /* X might be a paradoxical (subreg (mem)). In that case, gen_lowpart
9179 won't know what to do. So we will strip off the SUBREG here and
9180 process normally. */
9181 if (GET_CODE (x) == SUBREG && MEM_P (SUBREG_REG (x)))
9185 /* For use in case we fall down into the address adjustments
9186 further below, we need to adjust the known mode and size of
9187 x; imode and isize, since we just adjusted x. */
9188 imode = GET_MODE (x);
9193 isize = GET_MODE_SIZE (imode);
9196 result = gen_lowpart_common (omode, x);
9198 #ifdef CANNOT_CHANGE_MODE_CLASS
9199 if (result != 0 && GET_CODE (result) == SUBREG)
9200 record_subregs_of_mode (result);
9210 /* Refuse to work on a volatile memory ref or one with a mode-dependent
9212 if (MEM_VOLATILE_P (x) || mode_dependent_address_p (XEXP (x, 0)))
9215 /* If we want to refer to something bigger than the original memref,
9216 generate a paradoxical subreg instead. That will force a reload
9217 of the original memref X. */
9219 return gen_rtx_SUBREG (omode, x, 0);
9221 if (WORDS_BIG_ENDIAN)
9222 offset = MAX (isize, UNITS_PER_WORD) - MAX (osize, UNITS_PER_WORD);
9224 /* Adjust the address so that the address-after-the-data is
9226 if (BYTES_BIG_ENDIAN)
9227 offset -= MIN (UNITS_PER_WORD, osize) - MIN (UNITS_PER_WORD, isize);
9229 return adjust_address_nv (x, omode, offset);
9232 /* If X is a comparison operator, rewrite it in a new mode. This
9233 probably won't match, but may allow further simplifications. */
9234 else if (COMPARISON_P (x))
9235 return gen_rtx_fmt_ee (GET_CODE (x), omode, XEXP (x, 0), XEXP (x, 1));
9237 /* If we couldn't simplify X any other way, just enclose it in a
9238 SUBREG. Normally, this SUBREG won't match, but some patterns may
9239 include an explicit SUBREG or we may simplify it further in combine. */
9245 offset = subreg_lowpart_offset (omode, imode);
9246 if (imode == VOIDmode)
9248 imode = int_mode_for_mode (omode);
9249 x = gen_lowpart_common (imode, x);
9253 res = simplify_gen_subreg (omode, x, imode, offset);
9259 return gen_rtx_CLOBBER (imode, const0_rtx);
9262 /* Simplify a comparison between *POP0 and *POP1 where CODE is the
9263 comparison code that will be tested.
9265 The result is a possibly different comparison code to use. *POP0 and
9266 *POP1 may be updated.
9268 It is possible that we might detect that a comparison is either always
9269 true or always false. However, we do not perform general constant
9270 folding in combine, so this knowledge isn't useful. Such tautologies
9271 should have been detected earlier. Hence we ignore all such cases. */
9273 static enum rtx_code
9274 simplify_comparison (enum rtx_code code, rtx *pop0, rtx *pop1)
9280 enum machine_mode mode, tmode;
9282 /* Try a few ways of applying the same transformation to both operands. */
9285 #ifndef WORD_REGISTER_OPERATIONS
9286 /* The test below this one won't handle SIGN_EXTENDs on these machines,
9287 so check specially. */
9288 if (code != GTU && code != GEU && code != LTU && code != LEU
9289 && GET_CODE (op0) == ASHIFTRT && GET_CODE (op1) == ASHIFTRT
9290 && GET_CODE (XEXP (op0, 0)) == ASHIFT
9291 && GET_CODE (XEXP (op1, 0)) == ASHIFT
9292 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == SUBREG
9293 && GET_CODE (XEXP (XEXP (op1, 0), 0)) == SUBREG
9294 && (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0)))
9295 == GET_MODE (SUBREG_REG (XEXP (XEXP (op1, 0), 0))))
9296 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9297 && XEXP (op0, 1) == XEXP (op1, 1)
9298 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
9299 && XEXP (op0, 1) == XEXP (XEXP (op1, 0), 1)
9300 && (INTVAL (XEXP (op0, 1))
9301 == (GET_MODE_BITSIZE (GET_MODE (op0))
9303 (GET_MODE (SUBREG_REG (XEXP (XEXP (op0, 0), 0))))))))
9305 op0 = SUBREG_REG (XEXP (XEXP (op0, 0), 0));
9306 op1 = SUBREG_REG (XEXP (XEXP (op1, 0), 0));
9310 /* If both operands are the same constant shift, see if we can ignore the
9311 shift. We can if the shift is a rotate or if the bits shifted out of
9312 this shift are known to be zero for both inputs and if the type of
9313 comparison is compatible with the shift. */
9314 if (GET_CODE (op0) == GET_CODE (op1)
9315 && GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9316 && ((GET_CODE (op0) == ROTATE && (code == NE || code == EQ))
9317 || ((GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFT)
9318 && (code != GT && code != LT && code != GE && code != LE))
9319 || (GET_CODE (op0) == ASHIFTRT
9320 && (code != GTU && code != LTU
9321 && code != GEU && code != LEU)))
9322 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9323 && INTVAL (XEXP (op0, 1)) >= 0
9324 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
9325 && XEXP (op0, 1) == XEXP (op1, 1))
9327 enum machine_mode mode = GET_MODE (op0);
9328 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9329 int shift_count = INTVAL (XEXP (op0, 1));
9331 if (GET_CODE (op0) == LSHIFTRT || GET_CODE (op0) == ASHIFTRT)
9332 mask &= (mask >> shift_count) << shift_count;
9333 else if (GET_CODE (op0) == ASHIFT)
9334 mask = (mask & (mask << shift_count)) >> shift_count;
9336 if ((nonzero_bits (XEXP (op0, 0), mode) & ~mask) == 0
9337 && (nonzero_bits (XEXP (op1, 0), mode) & ~mask) == 0)
9338 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0);
9343 /* If both operands are AND's of a paradoxical SUBREG by constant, the
9344 SUBREGs are of the same mode, and, in both cases, the AND would
9345 be redundant if the comparison was done in the narrower mode,
9346 do the comparison in the narrower mode (e.g., we are AND'ing with 1
9347 and the operand's possibly nonzero bits are 0xffffff01; in that case
9348 if we only care about QImode, we don't need the AND). This case
9349 occurs if the output mode of an scc insn is not SImode and
9350 STORE_FLAG_VALUE == 1 (e.g., the 386).
9352 Similarly, check for a case where the AND's are ZERO_EXTEND
9353 operations from some narrower mode even though a SUBREG is not
9356 else if (GET_CODE (op0) == AND && GET_CODE (op1) == AND
9357 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9358 && GET_CODE (XEXP (op1, 1)) == CONST_INT)
9360 rtx inner_op0 = XEXP (op0, 0);
9361 rtx inner_op1 = XEXP (op1, 0);
9362 HOST_WIDE_INT c0 = INTVAL (XEXP (op0, 1));
9363 HOST_WIDE_INT c1 = INTVAL (XEXP (op1, 1));
9366 if (GET_CODE (inner_op0) == SUBREG && GET_CODE (inner_op1) == SUBREG
9367 && (GET_MODE_SIZE (GET_MODE (inner_op0))
9368 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (inner_op0))))
9369 && (GET_MODE (SUBREG_REG (inner_op0))
9370 == GET_MODE (SUBREG_REG (inner_op1)))
9371 && (GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (inner_op0)))
9372 <= HOST_BITS_PER_WIDE_INT)
9373 && (0 == ((~c0) & nonzero_bits (SUBREG_REG (inner_op0),
9374 GET_MODE (SUBREG_REG (inner_op0)))))
9375 && (0 == ((~c1) & nonzero_bits (SUBREG_REG (inner_op1),
9376 GET_MODE (SUBREG_REG (inner_op1))))))
9378 op0 = SUBREG_REG (inner_op0);
9379 op1 = SUBREG_REG (inner_op1);
9381 /* The resulting comparison is always unsigned since we masked
9382 off the original sign bit. */
9383 code = unsigned_condition (code);
9389 for (tmode = GET_CLASS_NARROWEST_MODE
9390 (GET_MODE_CLASS (GET_MODE (op0)));
9391 tmode != GET_MODE (op0); tmode = GET_MODE_WIDER_MODE (tmode))
9392 if ((unsigned HOST_WIDE_INT) c0 == GET_MODE_MASK (tmode))
9394 op0 = gen_lowpart (tmode, inner_op0);
9395 op1 = gen_lowpart (tmode, inner_op1);
9396 code = unsigned_condition (code);
9405 /* If both operands are NOT, we can strip off the outer operation
9406 and adjust the comparison code for swapped operands; similarly for
9407 NEG, except that this must be an equality comparison. */
9408 else if ((GET_CODE (op0) == NOT && GET_CODE (op1) == NOT)
9409 || (GET_CODE (op0) == NEG && GET_CODE (op1) == NEG
9410 && (code == EQ || code == NE)))
9411 op0 = XEXP (op0, 0), op1 = XEXP (op1, 0), code = swap_condition (code);
9417 /* If the first operand is a constant, swap the operands and adjust the
9418 comparison code appropriately, but don't do this if the second operand
9419 is already a constant integer. */
9420 if (swap_commutative_operands_p (op0, op1))
9422 tem = op0, op0 = op1, op1 = tem;
9423 code = swap_condition (code);
9426 /* We now enter a loop during which we will try to simplify the comparison.
9427 For the most part, we only are concerned with comparisons with zero,
9428 but some things may really be comparisons with zero but not start
9429 out looking that way. */
9431 while (GET_CODE (op1) == CONST_INT)
9433 enum machine_mode mode = GET_MODE (op0);
9434 unsigned int mode_width = GET_MODE_BITSIZE (mode);
9435 unsigned HOST_WIDE_INT mask = GET_MODE_MASK (mode);
9436 int equality_comparison_p;
9437 int sign_bit_comparison_p;
9438 int unsigned_comparison_p;
9439 HOST_WIDE_INT const_op;
9441 /* We only want to handle integral modes. This catches VOIDmode,
9442 CCmode, and the floating-point modes. An exception is that we
9443 can handle VOIDmode if OP0 is a COMPARE or a comparison
9446 if (GET_MODE_CLASS (mode) != MODE_INT
9447 && ! (mode == VOIDmode
9448 && (GET_CODE (op0) == COMPARE || COMPARISON_P (op0))))
9451 /* Get the constant we are comparing against and turn off all bits
9452 not on in our mode. */
9453 const_op = INTVAL (op1);
9454 if (mode != VOIDmode)
9455 const_op = trunc_int_for_mode (const_op, mode);
9456 op1 = GEN_INT (const_op);
9458 /* If we are comparing against a constant power of two and the value
9459 being compared can only have that single bit nonzero (e.g., it was
9460 `and'ed with that bit), we can replace this with a comparison
9463 && (code == EQ || code == NE || code == GE || code == GEU
9464 || code == LT || code == LTU)
9465 && mode_width <= HOST_BITS_PER_WIDE_INT
9466 && exact_log2 (const_op) >= 0
9467 && nonzero_bits (op0, mode) == (unsigned HOST_WIDE_INT) const_op)
9469 code = (code == EQ || code == GE || code == GEU ? NE : EQ);
9470 op1 = const0_rtx, const_op = 0;
9473 /* Similarly, if we are comparing a value known to be either -1 or
9474 0 with -1, change it to the opposite comparison against zero. */
9477 && (code == EQ || code == NE || code == GT || code == LE
9478 || code == GEU || code == LTU)
9479 && num_sign_bit_copies (op0, mode) == mode_width)
9481 code = (code == EQ || code == LE || code == GEU ? NE : EQ);
9482 op1 = const0_rtx, const_op = 0;
9485 /* Do some canonicalizations based on the comparison code. We prefer
9486 comparisons against zero and then prefer equality comparisons.
9487 If we can reduce the size of a constant, we will do that too. */
9492 /* < C is equivalent to <= (C - 1) */
9496 op1 = GEN_INT (const_op);
9498 /* ... fall through to LE case below. */
9504 /* <= C is equivalent to < (C + 1); we do this for C < 0 */
9508 op1 = GEN_INT (const_op);
9512 /* If we are doing a <= 0 comparison on a value known to have
9513 a zero sign bit, we can replace this with == 0. */
9514 else if (const_op == 0
9515 && mode_width <= HOST_BITS_PER_WIDE_INT
9516 && (nonzero_bits (op0, mode)
9517 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9522 /* >= C is equivalent to > (C - 1). */
9526 op1 = GEN_INT (const_op);
9528 /* ... fall through to GT below. */
9534 /* > C is equivalent to >= (C + 1); we do this for C < 0. */
9538 op1 = GEN_INT (const_op);
9542 /* If we are doing a > 0 comparison on a value known to have
9543 a zero sign bit, we can replace this with != 0. */
9544 else if (const_op == 0
9545 && mode_width <= HOST_BITS_PER_WIDE_INT
9546 && (nonzero_bits (op0, mode)
9547 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)
9552 /* < C is equivalent to <= (C - 1). */
9556 op1 = GEN_INT (const_op);
9558 /* ... fall through ... */
9561 /* (unsigned) < 0x80000000 is equivalent to >= 0. */
9562 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9563 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9565 const_op = 0, op1 = const0_rtx;
9573 /* unsigned <= 0 is equivalent to == 0 */
9577 /* (unsigned) <= 0x7fffffff is equivalent to >= 0. */
9578 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9579 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9581 const_op = 0, op1 = const0_rtx;
9587 /* >= C is equivalent to > (C - 1). */
9591 op1 = GEN_INT (const_op);
9593 /* ... fall through ... */
9596 /* (unsigned) >= 0x80000000 is equivalent to < 0. */
9597 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9598 && (const_op == (HOST_WIDE_INT) 1 << (mode_width - 1)))
9600 const_op = 0, op1 = const0_rtx;
9608 /* unsigned > 0 is equivalent to != 0 */
9612 /* (unsigned) > 0x7fffffff is equivalent to < 0. */
9613 else if ((mode_width <= HOST_BITS_PER_WIDE_INT)
9614 && (const_op == ((HOST_WIDE_INT) 1 << (mode_width - 1)) - 1))
9616 const_op = 0, op1 = const0_rtx;
9625 /* Compute some predicates to simplify code below. */
9627 equality_comparison_p = (code == EQ || code == NE);
9628 sign_bit_comparison_p = ((code == LT || code == GE) && const_op == 0);
9629 unsigned_comparison_p = (code == LTU || code == LEU || code == GTU
9632 /* If this is a sign bit comparison and we can do arithmetic in
9633 MODE, say that we will only be needing the sign bit of OP0. */
9634 if (sign_bit_comparison_p
9635 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9636 op0 = force_to_mode (op0, mode,
9638 << (GET_MODE_BITSIZE (mode) - 1)),
9641 /* Now try cases based on the opcode of OP0. If none of the cases
9642 does a "continue", we exit this loop immediately after the
9645 switch (GET_CODE (op0))
9648 /* If we are extracting a single bit from a variable position in
9649 a constant that has only a single bit set and are comparing it
9650 with zero, we can convert this into an equality comparison
9651 between the position and the location of the single bit. */
9652 /* Except we can't if SHIFT_COUNT_TRUNCATED is set, since we might
9653 have already reduced the shift count modulo the word size. */
9654 if (!SHIFT_COUNT_TRUNCATED
9655 && GET_CODE (XEXP (op0, 0)) == CONST_INT
9656 && XEXP (op0, 1) == const1_rtx
9657 && equality_comparison_p && const_op == 0
9658 && (i = exact_log2 (INTVAL (XEXP (op0, 0)))) >= 0)
9660 if (BITS_BIG_ENDIAN)
9662 enum machine_mode new_mode
9663 = mode_for_extraction (EP_extzv, 1);
9664 if (new_mode == MAX_MACHINE_MODE)
9665 i = BITS_PER_WORD - 1 - i;
9669 i = (GET_MODE_BITSIZE (mode) - 1 - i);
9673 op0 = XEXP (op0, 2);
9677 /* Result is nonzero iff shift count is equal to I. */
9678 code = reverse_condition (code);
9682 /* ... fall through ... */
9685 tem = expand_compound_operation (op0);
9694 /* If testing for equality, we can take the NOT of the constant. */
9695 if (equality_comparison_p
9696 && (tem = simplify_unary_operation (NOT, mode, op1, mode)) != 0)
9698 op0 = XEXP (op0, 0);
9703 /* If just looking at the sign bit, reverse the sense of the
9705 if (sign_bit_comparison_p)
9707 op0 = XEXP (op0, 0);
9708 code = (code == GE ? LT : GE);
9714 /* If testing for equality, we can take the NEG of the constant. */
9715 if (equality_comparison_p
9716 && (tem = simplify_unary_operation (NEG, mode, op1, mode)) != 0)
9718 op0 = XEXP (op0, 0);
9723 /* The remaining cases only apply to comparisons with zero. */
9727 /* When X is ABS or is known positive,
9728 (neg X) is < 0 if and only if X != 0. */
9730 if (sign_bit_comparison_p
9731 && (GET_CODE (XEXP (op0, 0)) == ABS
9732 || (mode_width <= HOST_BITS_PER_WIDE_INT
9733 && (nonzero_bits (XEXP (op0, 0), mode)
9734 & ((HOST_WIDE_INT) 1 << (mode_width - 1))) == 0)))
9736 op0 = XEXP (op0, 0);
9737 code = (code == LT ? NE : EQ);
9741 /* If we have NEG of something whose two high-order bits are the
9742 same, we know that "(-a) < 0" is equivalent to "a > 0". */
9743 if (num_sign_bit_copies (op0, mode) >= 2)
9745 op0 = XEXP (op0, 0);
9746 code = swap_condition (code);
9752 /* If we are testing equality and our count is a constant, we
9753 can perform the inverse operation on our RHS. */
9754 if (equality_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
9755 && (tem = simplify_binary_operation (ROTATERT, mode,
9756 op1, XEXP (op0, 1))) != 0)
9758 op0 = XEXP (op0, 0);
9763 /* If we are doing a < 0 or >= 0 comparison, it means we are testing
9764 a particular bit. Convert it to an AND of a constant of that
9765 bit. This will be converted into a ZERO_EXTRACT. */
9766 if (const_op == 0 && sign_bit_comparison_p
9767 && GET_CODE (XEXP (op0, 1)) == CONST_INT
9768 && mode_width <= HOST_BITS_PER_WIDE_INT)
9770 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
9773 - INTVAL (XEXP (op0, 1)))));
9774 code = (code == LT ? NE : EQ);
9781 /* ABS is ignorable inside an equality comparison with zero. */
9782 if (const_op == 0 && equality_comparison_p)
9784 op0 = XEXP (op0, 0);
9790 /* Can simplify (compare (zero/sign_extend FOO) CONST) to
9791 (compare FOO CONST) if CONST fits in FOO's mode and we
9792 are either testing inequality or have an unsigned
9793 comparison with ZERO_EXTEND or a signed comparison with
9794 SIGN_EXTEND. But don't do it if we don't have a compare
9795 insn of the given mode, since we'd have to revert it
9796 later on, and then we wouldn't know whether to sign- or
9798 mode = GET_MODE (XEXP (op0, 0));
9799 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9800 && ! unsigned_comparison_p
9801 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9802 && ((unsigned HOST_WIDE_INT) const_op
9803 < (((unsigned HOST_WIDE_INT) 1
9804 << (GET_MODE_BITSIZE (mode) - 1))))
9805 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
9807 op0 = XEXP (op0, 0);
9813 /* Check for the case where we are comparing A - C1 with C2, that is
9815 (subreg:MODE (plus (A) (-C1))) op (C2)
9817 with C1 a constant, and try to lift the SUBREG, i.e. to do the
9818 comparison in the wider mode. One of the following two conditions
9819 must be true in order for this to be valid:
9821 1. The mode extension results in the same bit pattern being added
9822 on both sides and the comparison is equality or unsigned. As
9823 C2 has been truncated to fit in MODE, the pattern can only be
9826 2. The mode extension results in the sign bit being copied on
9829 The difficulty here is that we have predicates for A but not for
9830 (A - C1) so we need to check that C1 is within proper bounds so
9831 as to perturbate A as little as possible. */
9833 if (mode_width <= HOST_BITS_PER_WIDE_INT
9834 && subreg_lowpart_p (op0)
9835 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) > mode_width
9836 && GET_CODE (SUBREG_REG (op0)) == PLUS
9837 && GET_CODE (XEXP (SUBREG_REG (op0), 1)) == CONST_INT)
9839 enum machine_mode inner_mode = GET_MODE (SUBREG_REG (op0));
9840 rtx a = XEXP (SUBREG_REG (op0), 0);
9841 HOST_WIDE_INT c1 = -INTVAL (XEXP (SUBREG_REG (op0), 1));
9844 && (unsigned HOST_WIDE_INT) c1
9845 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)
9846 && (equality_comparison_p || unsigned_comparison_p)
9847 /* (A - C1) zero-extends if it is positive and sign-extends
9848 if it is negative, C2 both zero- and sign-extends. */
9849 && ((0 == (nonzero_bits (a, inner_mode)
9850 & ~GET_MODE_MASK (mode))
9852 /* (A - C1) sign-extends if it is positive and 1-extends
9853 if it is negative, C2 both sign- and 1-extends. */
9854 || (num_sign_bit_copies (a, inner_mode)
9855 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
9858 || ((unsigned HOST_WIDE_INT) c1
9859 < (unsigned HOST_WIDE_INT) 1 << (mode_width - 2)
9860 /* (A - C1) always sign-extends, like C2. */
9861 && num_sign_bit_copies (a, inner_mode)
9862 > (unsigned int) (GET_MODE_BITSIZE (inner_mode)
9863 - (mode_width - 1))))
9865 op0 = SUBREG_REG (op0);
9870 /* If the inner mode is narrower and we are extracting the low part,
9871 we can treat the SUBREG as if it were a ZERO_EXTEND. */
9872 if (subreg_lowpart_p (op0)
9873 && GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0))) < mode_width)
9874 /* Fall through */ ;
9878 /* ... fall through ... */
9881 mode = GET_MODE (XEXP (op0, 0));
9882 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
9883 && (unsigned_comparison_p || equality_comparison_p)
9884 && (GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
9885 && ((unsigned HOST_WIDE_INT) const_op < GET_MODE_MASK (mode))
9886 && cmp_optab->handlers[(int) mode].insn_code != CODE_FOR_nothing)
9888 op0 = XEXP (op0, 0);
9894 /* (eq (plus X A) B) -> (eq X (minus B A)). We can only do
9895 this for equality comparisons due to pathological cases involving
9897 if (equality_comparison_p
9898 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9899 op1, XEXP (op0, 1))))
9901 op0 = XEXP (op0, 0);
9906 /* (plus (abs X) (const_int -1)) is < 0 if and only if X == 0. */
9907 if (const_op == 0 && XEXP (op0, 1) == constm1_rtx
9908 && GET_CODE (XEXP (op0, 0)) == ABS && sign_bit_comparison_p)
9910 op0 = XEXP (XEXP (op0, 0), 0);
9911 code = (code == LT ? EQ : NE);
9917 /* We used to optimize signed comparisons against zero, but that
9918 was incorrect. Unsigned comparisons against zero (GTU, LEU)
9919 arrive here as equality comparisons, or (GEU, LTU) are
9920 optimized away. No need to special-case them. */
9922 /* (eq (minus A B) C) -> (eq A (plus B C)) or
9923 (eq B (minus A C)), whichever simplifies. We can only do
9924 this for equality comparisons due to pathological cases involving
9926 if (equality_comparison_p
9927 && 0 != (tem = simplify_binary_operation (PLUS, mode,
9928 XEXP (op0, 1), op1)))
9930 op0 = XEXP (op0, 0);
9935 if (equality_comparison_p
9936 && 0 != (tem = simplify_binary_operation (MINUS, mode,
9937 XEXP (op0, 0), op1)))
9939 op0 = XEXP (op0, 1);
9944 /* The sign bit of (minus (ashiftrt X C) X), where C is the number
9945 of bits in X minus 1, is one iff X > 0. */
9946 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == ASHIFTRT
9947 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
9948 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (op0, 0), 1))
9950 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
9952 op0 = XEXP (op0, 1);
9953 code = (code == GE ? LE : GT);
9959 /* (eq (xor A B) C) -> (eq A (xor B C)). This is a simplification
9960 if C is zero or B is a constant. */
9961 if (equality_comparison_p
9962 && 0 != (tem = simplify_binary_operation (XOR, mode,
9963 XEXP (op0, 1), op1)))
9965 op0 = XEXP (op0, 0);
9972 case UNEQ: case LTGT:
9973 case LT: case LTU: case UNLT: case LE: case LEU: case UNLE:
9974 case GT: case GTU: case UNGT: case GE: case GEU: case UNGE:
9975 case UNORDERED: case ORDERED:
9976 /* We can't do anything if OP0 is a condition code value, rather
9977 than an actual data value. */
9979 || CC0_P (XEXP (op0, 0))
9980 || GET_MODE_CLASS (GET_MODE (XEXP (op0, 0))) == MODE_CC)
9983 /* Get the two operands being compared. */
9984 if (GET_CODE (XEXP (op0, 0)) == COMPARE)
9985 tem = XEXP (XEXP (op0, 0), 0), tem1 = XEXP (XEXP (op0, 0), 1);
9987 tem = XEXP (op0, 0), tem1 = XEXP (op0, 1);
9989 /* Check for the cases where we simply want the result of the
9990 earlier test or the opposite of that result. */
9991 if (code == NE || code == EQ
9992 || (GET_MODE_BITSIZE (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT
9993 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
9994 && (STORE_FLAG_VALUE
9995 & (((HOST_WIDE_INT) 1
9996 << (GET_MODE_BITSIZE (GET_MODE (op0)) - 1))))
9997 && (code == LT || code == GE)))
9999 enum rtx_code new_code;
10000 if (code == LT || code == NE)
10001 new_code = GET_CODE (op0);
10003 new_code = reversed_comparison_code (op0, NULL);
10005 if (new_code != UNKNOWN)
10016 /* The sign bit of (ior (plus X (const_int -1)) X) is nonzero
10018 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 0)) == PLUS
10019 && XEXP (XEXP (op0, 0), 1) == constm1_rtx
10020 && rtx_equal_p (XEXP (XEXP (op0, 0), 0), XEXP (op0, 1)))
10022 op0 = XEXP (op0, 1);
10023 code = (code == GE ? GT : LE);
10029 /* Convert (and (xshift 1 X) Y) to (and (lshiftrt Y X) 1). This
10030 will be converted to a ZERO_EXTRACT later. */
10031 if (const_op == 0 && equality_comparison_p
10032 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10033 && XEXP (XEXP (op0, 0), 0) == const1_rtx)
10035 op0 = simplify_and_const_int
10036 (op0, mode, gen_rtx_LSHIFTRT (mode,
10038 XEXP (XEXP (op0, 0), 1)),
10039 (HOST_WIDE_INT) 1);
10043 /* If we are comparing (and (lshiftrt X C1) C2) for equality with
10044 zero and X is a comparison and C1 and C2 describe only bits set
10045 in STORE_FLAG_VALUE, we can compare with X. */
10046 if (const_op == 0 && equality_comparison_p
10047 && mode_width <= HOST_BITS_PER_WIDE_INT
10048 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10049 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT
10050 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10051 && INTVAL (XEXP (XEXP (op0, 0), 1)) >= 0
10052 && INTVAL (XEXP (XEXP (op0, 0), 1)) < HOST_BITS_PER_WIDE_INT)
10054 mask = ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10055 << INTVAL (XEXP (XEXP (op0, 0), 1)));
10056 if ((~STORE_FLAG_VALUE & mask) == 0
10057 && (COMPARISON_P (XEXP (XEXP (op0, 0), 0))
10058 || ((tem = get_last_value (XEXP (XEXP (op0, 0), 0))) != 0
10059 && COMPARISON_P (tem))))
10061 op0 = XEXP (XEXP (op0, 0), 0);
10066 /* If we are doing an equality comparison of an AND of a bit equal
10067 to the sign bit, replace this with a LT or GE comparison of
10068 the underlying value. */
10069 if (equality_comparison_p
10071 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10072 && mode_width <= HOST_BITS_PER_WIDE_INT
10073 && ((INTVAL (XEXP (op0, 1)) & GET_MODE_MASK (mode))
10074 == (unsigned HOST_WIDE_INT) 1 << (mode_width - 1)))
10076 op0 = XEXP (op0, 0);
10077 code = (code == EQ ? GE : LT);
10081 /* If this AND operation is really a ZERO_EXTEND from a narrower
10082 mode, the constant fits within that mode, and this is either an
10083 equality or unsigned comparison, try to do this comparison in
10084 the narrower mode. */
10085 if ((equality_comparison_p || unsigned_comparison_p)
10086 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10087 && (i = exact_log2 ((INTVAL (XEXP (op0, 1))
10088 & GET_MODE_MASK (mode))
10090 && const_op >> i == 0
10091 && (tmode = mode_for_size (i, MODE_INT, 1)) != BLKmode)
10093 op0 = gen_lowpart (tmode, XEXP (op0, 0));
10097 /* If this is (and:M1 (subreg:M2 X 0) (const_int C1)) where C1
10098 fits in both M1 and M2 and the SUBREG is either paradoxical
10099 or represents the low part, permute the SUBREG and the AND
10101 if (GET_CODE (XEXP (op0, 0)) == SUBREG)
10103 unsigned HOST_WIDE_INT c1;
10104 tmode = GET_MODE (SUBREG_REG (XEXP (op0, 0)));
10105 /* Require an integral mode, to avoid creating something like
10107 if (SCALAR_INT_MODE_P (tmode)
10108 /* It is unsafe to commute the AND into the SUBREG if the
10109 SUBREG is paradoxical and WORD_REGISTER_OPERATIONS is
10110 not defined. As originally written the upper bits
10111 have a defined value due to the AND operation.
10112 However, if we commute the AND inside the SUBREG then
10113 they no longer have defined values and the meaning of
10114 the code has been changed. */
10116 #ifdef WORD_REGISTER_OPERATIONS
10117 || (mode_width > GET_MODE_BITSIZE (tmode)
10118 && mode_width <= BITS_PER_WORD)
10120 || (mode_width <= GET_MODE_BITSIZE (tmode)
10121 && subreg_lowpart_p (XEXP (op0, 0))))
10122 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10123 && mode_width <= HOST_BITS_PER_WIDE_INT
10124 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT
10125 && ((c1 = INTVAL (XEXP (op0, 1))) & ~mask) == 0
10126 && (c1 & ~GET_MODE_MASK (tmode)) == 0
10128 && c1 != GET_MODE_MASK (tmode))
10130 op0 = simplify_gen_binary (AND, tmode,
10131 SUBREG_REG (XEXP (op0, 0)),
10132 gen_int_mode (c1, tmode));
10133 op0 = gen_lowpart (mode, op0);
10138 /* Convert (ne (and (not X) 1) 0) to (eq (and X 1) 0). */
10139 if (const_op == 0 && equality_comparison_p
10140 && XEXP (op0, 1) == const1_rtx
10141 && GET_CODE (XEXP (op0, 0)) == NOT)
10143 op0 = simplify_and_const_int
10144 (NULL_RTX, mode, XEXP (XEXP (op0, 0), 0), (HOST_WIDE_INT) 1);
10145 code = (code == NE ? EQ : NE);
10149 /* Convert (ne (and (lshiftrt (not X)) 1) 0) to
10150 (eq (and (lshiftrt X) 1) 0).
10151 Also handle the case where (not X) is expressed using xor. */
10152 if (const_op == 0 && equality_comparison_p
10153 && XEXP (op0, 1) == const1_rtx
10154 && GET_CODE (XEXP (op0, 0)) == LSHIFTRT)
10156 rtx shift_op = XEXP (XEXP (op0, 0), 0);
10157 rtx shift_count = XEXP (XEXP (op0, 0), 1);
10159 if (GET_CODE (shift_op) == NOT
10160 || (GET_CODE (shift_op) == XOR
10161 && GET_CODE (XEXP (shift_op, 1)) == CONST_INT
10162 && GET_CODE (shift_count) == CONST_INT
10163 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT
10164 && (INTVAL (XEXP (shift_op, 1))
10165 == (HOST_WIDE_INT) 1 << INTVAL (shift_count))))
10167 op0 = simplify_and_const_int
10169 gen_rtx_LSHIFTRT (mode, XEXP (shift_op, 0), shift_count),
10170 (HOST_WIDE_INT) 1);
10171 code = (code == NE ? EQ : NE);
10178 /* If we have (compare (ashift FOO N) (const_int C)) and
10179 the high order N bits of FOO (N+1 if an inequality comparison)
10180 are known to be zero, we can do this by comparing FOO with C
10181 shifted right N bits so long as the low-order N bits of C are
10183 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10184 && INTVAL (XEXP (op0, 1)) >= 0
10185 && ((INTVAL (XEXP (op0, 1)) + ! equality_comparison_p)
10186 < HOST_BITS_PER_WIDE_INT)
10188 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0)
10189 && mode_width <= HOST_BITS_PER_WIDE_INT
10190 && (nonzero_bits (XEXP (op0, 0), mode)
10191 & ~(mask >> (INTVAL (XEXP (op0, 1))
10192 + ! equality_comparison_p))) == 0)
10194 /* We must perform a logical shift, not an arithmetic one,
10195 as we want the top N bits of C to be zero. */
10196 unsigned HOST_WIDE_INT temp = const_op & GET_MODE_MASK (mode);
10198 temp >>= INTVAL (XEXP (op0, 1));
10199 op1 = gen_int_mode (temp, mode);
10200 op0 = XEXP (op0, 0);
10204 /* If we are doing a sign bit comparison, it means we are testing
10205 a particular bit. Convert it to the appropriate AND. */
10206 if (sign_bit_comparison_p && GET_CODE (XEXP (op0, 1)) == CONST_INT
10207 && mode_width <= HOST_BITS_PER_WIDE_INT)
10209 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10212 - INTVAL (XEXP (op0, 1)))));
10213 code = (code == LT ? NE : EQ);
10217 /* If this an equality comparison with zero and we are shifting
10218 the low bit to the sign bit, we can convert this to an AND of the
10220 if (const_op == 0 && equality_comparison_p
10221 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10222 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10225 op0 = simplify_and_const_int (NULL_RTX, mode, XEXP (op0, 0),
10226 (HOST_WIDE_INT) 1);
10232 /* If this is an equality comparison with zero, we can do this
10233 as a logical shift, which might be much simpler. */
10234 if (equality_comparison_p && const_op == 0
10235 && GET_CODE (XEXP (op0, 1)) == CONST_INT)
10237 op0 = simplify_shift_const (NULL_RTX, LSHIFTRT, mode,
10239 INTVAL (XEXP (op0, 1)));
10243 /* If OP0 is a sign extension and CODE is not an unsigned comparison,
10244 do the comparison in a narrower mode. */
10245 if (! unsigned_comparison_p
10246 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10247 && GET_CODE (XEXP (op0, 0)) == ASHIFT
10248 && XEXP (op0, 1) == XEXP (XEXP (op0, 0), 1)
10249 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10250 MODE_INT, 1)) != BLKmode
10251 && (((unsigned HOST_WIDE_INT) const_op
10252 + (GET_MODE_MASK (tmode) >> 1) + 1)
10253 <= GET_MODE_MASK (tmode)))
10255 op0 = gen_lowpart (tmode, XEXP (XEXP (op0, 0), 0));
10259 /* Likewise if OP0 is a PLUS of a sign extension with a
10260 constant, which is usually represented with the PLUS
10261 between the shifts. */
10262 if (! unsigned_comparison_p
10263 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10264 && GET_CODE (XEXP (op0, 0)) == PLUS
10265 && GET_CODE (XEXP (XEXP (op0, 0), 1)) == CONST_INT
10266 && GET_CODE (XEXP (XEXP (op0, 0), 0)) == ASHIFT
10267 && XEXP (op0, 1) == XEXP (XEXP (XEXP (op0, 0), 0), 1)
10268 && (tmode = mode_for_size (mode_width - INTVAL (XEXP (op0, 1)),
10269 MODE_INT, 1)) != BLKmode
10270 && (((unsigned HOST_WIDE_INT) const_op
10271 + (GET_MODE_MASK (tmode) >> 1) + 1)
10272 <= GET_MODE_MASK (tmode)))
10274 rtx inner = XEXP (XEXP (XEXP (op0, 0), 0), 0);
10275 rtx add_const = XEXP (XEXP (op0, 0), 1);
10276 rtx new_const = simplify_gen_binary (ASHIFTRT, GET_MODE (op0),
10277 add_const, XEXP (op0, 1));
10279 op0 = simplify_gen_binary (PLUS, tmode,
10280 gen_lowpart (tmode, inner),
10285 /* ... fall through ... */
10287 /* If we have (compare (xshiftrt FOO N) (const_int C)) and
10288 the low order N bits of FOO are known to be zero, we can do this
10289 by comparing FOO with C shifted left N bits so long as no
10290 overflow occurs. */
10291 if (GET_CODE (XEXP (op0, 1)) == CONST_INT
10292 && INTVAL (XEXP (op0, 1)) >= 0
10293 && INTVAL (XEXP (op0, 1)) < HOST_BITS_PER_WIDE_INT
10294 && mode_width <= HOST_BITS_PER_WIDE_INT
10295 && (nonzero_bits (XEXP (op0, 0), mode)
10296 & (((HOST_WIDE_INT) 1 << INTVAL (XEXP (op0, 1))) - 1)) == 0
10297 && (((unsigned HOST_WIDE_INT) const_op
10298 + (GET_CODE (op0) != LSHIFTRT
10299 ? ((GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1)) >> 1)
10302 <= GET_MODE_MASK (mode) >> INTVAL (XEXP (op0, 1))))
10304 /* If the shift was logical, then we must make the condition
10306 if (GET_CODE (op0) == LSHIFTRT)
10307 code = unsigned_condition (code);
10309 const_op <<= INTVAL (XEXP (op0, 1));
10310 op1 = GEN_INT (const_op);
10311 op0 = XEXP (op0, 0);
10315 /* If we are using this shift to extract just the sign bit, we
10316 can replace this with an LT or GE comparison. */
10318 && (equality_comparison_p || sign_bit_comparison_p)
10319 && GET_CODE (XEXP (op0, 1)) == CONST_INT
10320 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (op0, 1))
10323 op0 = XEXP (op0, 0);
10324 code = (code == NE || code == GT ? LT : GE);
10336 /* Now make any compound operations involved in this comparison. Then,
10337 check for an outmost SUBREG on OP0 that is not doing anything or is
10338 paradoxical. The latter transformation must only be performed when
10339 it is known that the "extra" bits will be the same in op0 and op1 or
10340 that they don't matter. There are three cases to consider:
10342 1. SUBREG_REG (op0) is a register. In this case the bits are don't
10343 care bits and we can assume they have any convenient value. So
10344 making the transformation is safe.
10346 2. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is not defined.
10347 In this case the upper bits of op0 are undefined. We should not make
10348 the simplification in that case as we do not know the contents of
10351 3. SUBREG_REG (op0) is a memory and LOAD_EXTEND_OP is defined and not
10352 UNKNOWN. In that case we know those bits are zeros or ones. We must
10353 also be sure that they are the same as the upper bits of op1.
10355 We can never remove a SUBREG for a non-equality comparison because
10356 the sign bit is in a different place in the underlying object. */
10358 op0 = make_compound_operation (op0, op1 == const0_rtx ? COMPARE : SET);
10359 op1 = make_compound_operation (op1, SET);
10361 if (GET_CODE (op0) == SUBREG && subreg_lowpart_p (op0)
10362 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_INT
10363 && GET_MODE_CLASS (GET_MODE (SUBREG_REG (op0))) == MODE_INT
10364 && (code == NE || code == EQ))
10366 if (GET_MODE_SIZE (GET_MODE (op0))
10367 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (op0))))
10369 /* For paradoxical subregs, allow case 1 as above. Case 3 isn't
10371 if (REG_P (SUBREG_REG (op0)))
10373 op0 = SUBREG_REG (op0);
10374 op1 = gen_lowpart (GET_MODE (op0), op1);
10377 else if ((GET_MODE_BITSIZE (GET_MODE (SUBREG_REG (op0)))
10378 <= HOST_BITS_PER_WIDE_INT)
10379 && (nonzero_bits (SUBREG_REG (op0),
10380 GET_MODE (SUBREG_REG (op0)))
10381 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10383 tem = gen_lowpart (GET_MODE (SUBREG_REG (op0)), op1);
10385 if ((nonzero_bits (tem, GET_MODE (SUBREG_REG (op0)))
10386 & ~GET_MODE_MASK (GET_MODE (op0))) == 0)
10387 op0 = SUBREG_REG (op0), op1 = tem;
10391 /* We now do the opposite procedure: Some machines don't have compare
10392 insns in all modes. If OP0's mode is an integer mode smaller than a
10393 word and we can't do a compare in that mode, see if there is a larger
10394 mode for which we can do the compare. There are a number of cases in
10395 which we can use the wider mode. */
10397 mode = GET_MODE (op0);
10398 if (mode != VOIDmode && GET_MODE_CLASS (mode) == MODE_INT
10399 && GET_MODE_SIZE (mode) < UNITS_PER_WORD
10400 && ! have_insn_for (COMPARE, mode))
10401 for (tmode = GET_MODE_WIDER_MODE (mode);
10403 && GET_MODE_BITSIZE (tmode) <= HOST_BITS_PER_WIDE_INT);
10404 tmode = GET_MODE_WIDER_MODE (tmode))
10405 if (have_insn_for (COMPARE, tmode))
10409 /* If the only nonzero bits in OP0 and OP1 are those in the
10410 narrower mode and this is an equality or unsigned comparison,
10411 we can use the wider mode. Similarly for sign-extended
10412 values, in which case it is true for all comparisons. */
10413 zero_extended = ((code == EQ || code == NE
10414 || code == GEU || code == GTU
10415 || code == LEU || code == LTU)
10416 && (nonzero_bits (op0, tmode)
10417 & ~GET_MODE_MASK (mode)) == 0
10418 && ((GET_CODE (op1) == CONST_INT
10419 || (nonzero_bits (op1, tmode)
10420 & ~GET_MODE_MASK (mode)) == 0)));
10423 || ((num_sign_bit_copies (op0, tmode)
10424 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10425 - GET_MODE_BITSIZE (mode)))
10426 && (num_sign_bit_copies (op1, tmode)
10427 > (unsigned int) (GET_MODE_BITSIZE (tmode)
10428 - GET_MODE_BITSIZE (mode)))))
10430 /* If OP0 is an AND and we don't have an AND in MODE either,
10431 make a new AND in the proper mode. */
10432 if (GET_CODE (op0) == AND
10433 && !have_insn_for (AND, mode))
10434 op0 = simplify_gen_binary (AND, tmode,
10435 gen_lowpart (tmode,
10437 gen_lowpart (tmode,
10440 op0 = gen_lowpart (tmode, op0);
10441 if (zero_extended && GET_CODE (op1) == CONST_INT)
10442 op1 = GEN_INT (INTVAL (op1) & GET_MODE_MASK (mode));
10443 op1 = gen_lowpart (tmode, op1);
10447 /* If this is a test for negative, we can make an explicit
10448 test of the sign bit. */
10450 if (op1 == const0_rtx && (code == LT || code == GE)
10451 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10453 op0 = simplify_gen_binary (AND, tmode,
10454 gen_lowpart (tmode, op0),
10455 GEN_INT ((HOST_WIDE_INT) 1
10456 << (GET_MODE_BITSIZE (mode)
10458 code = (code == LT) ? NE : EQ;
10463 #ifdef CANONICALIZE_COMPARISON
10464 /* If this machine only supports a subset of valid comparisons, see if we
10465 can convert an unsupported one into a supported one. */
10466 CANONICALIZE_COMPARISON (code, op0, op1);
10475 /* Utility function for record_value_for_reg. Count number of
10480 enum rtx_code code = GET_CODE (x);
10484 if (GET_RTX_CLASS (code) == '2'
10485 || GET_RTX_CLASS (code) == 'c')
10487 rtx x0 = XEXP (x, 0);
10488 rtx x1 = XEXP (x, 1);
10491 return 1 + 2 * count_rtxs (x0);
10493 if ((GET_RTX_CLASS (GET_CODE (x1)) == '2'
10494 || GET_RTX_CLASS (GET_CODE (x1)) == 'c')
10495 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10496 return 2 + 2 * count_rtxs (x0)
10497 + count_rtxs (x == XEXP (x1, 0)
10498 ? XEXP (x1, 1) : XEXP (x1, 0));
10500 if ((GET_RTX_CLASS (GET_CODE (x0)) == '2'
10501 || GET_RTX_CLASS (GET_CODE (x0)) == 'c')
10502 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10503 return 2 + 2 * count_rtxs (x1)
10504 + count_rtxs (x == XEXP (x0, 0)
10505 ? XEXP (x0, 1) : XEXP (x0, 0));
10508 fmt = GET_RTX_FORMAT (code);
10509 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10511 ret += count_rtxs (XEXP (x, i));
10516 /* Utility function for following routine. Called when X is part of a value
10517 being stored into last_set_value. Sets last_set_table_tick
10518 for each register mentioned. Similar to mention_regs in cse.c */
10521 update_table_tick (rtx x)
10523 enum rtx_code code = GET_CODE (x);
10524 const char *fmt = GET_RTX_FORMAT (code);
10529 unsigned int regno = REGNO (x);
10530 unsigned int endregno
10531 = regno + (regno < FIRST_PSEUDO_REGISTER
10532 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10535 for (r = regno; r < endregno; r++)
10536 reg_stat[r].last_set_table_tick = label_tick;
10541 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
10542 /* Note that we can't have an "E" in values stored; see
10543 get_last_value_validate. */
10546 /* Check for identical subexpressions. If x contains
10547 identical subexpression we only have to traverse one of
10549 if (i == 0 && ARITHMETIC_P (x))
10551 /* Note that at this point x1 has already been
10553 rtx x0 = XEXP (x, 0);
10554 rtx x1 = XEXP (x, 1);
10556 /* If x0 and x1 are identical then there is no need to
10561 /* If x0 is identical to a subexpression of x1 then while
10562 processing x1, x0 has already been processed. Thus we
10563 are done with x. */
10564 if (ARITHMETIC_P (x1)
10565 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10568 /* If x1 is identical to a subexpression of x0 then we
10569 still have to process the rest of x0. */
10570 if (ARITHMETIC_P (x0)
10571 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10573 update_table_tick (XEXP (x0, x1 == XEXP (x0, 0) ? 1 : 0));
10578 update_table_tick (XEXP (x, i));
10582 /* Record that REG is set to VALUE in insn INSN. If VALUE is zero, we
10583 are saying that the register is clobbered and we no longer know its
10584 value. If INSN is zero, don't update reg_stat[].last_set; this is
10585 only permitted with VALUE also zero and is used to invalidate the
10589 record_value_for_reg (rtx reg, rtx insn, rtx value)
10591 unsigned int regno = REGNO (reg);
10592 unsigned int endregno
10593 = regno + (regno < FIRST_PSEUDO_REGISTER
10594 ? hard_regno_nregs[regno][GET_MODE (reg)] : 1);
10597 /* If VALUE contains REG and we have a previous value for REG, substitute
10598 the previous value. */
10599 if (value && insn && reg_overlap_mentioned_p (reg, value))
10603 /* Set things up so get_last_value is allowed to see anything set up to
10605 subst_low_cuid = INSN_CUID (insn);
10606 tem = get_last_value (reg);
10608 /* If TEM is simply a binary operation with two CLOBBERs as operands,
10609 it isn't going to be useful and will take a lot of time to process,
10610 so just use the CLOBBER. */
10614 if (ARITHMETIC_P (tem)
10615 && GET_CODE (XEXP (tem, 0)) == CLOBBER
10616 && GET_CODE (XEXP (tem, 1)) == CLOBBER)
10617 tem = XEXP (tem, 0);
10618 else if (count_occurrences (value, reg, 1) >= 2)
10620 /* If there are two or more occurrences of REG in VALUE,
10621 prevent the value from growing too much. */
10622 if (count_rtxs (tem) > MAX_LAST_VALUE_RTL)
10623 tem = gen_rtx_CLOBBER (GET_MODE (tem), const0_rtx);
10626 value = replace_rtx (copy_rtx (value), reg, tem);
10630 /* For each register modified, show we don't know its value, that
10631 we don't know about its bitwise content, that its value has been
10632 updated, and that we don't know the location of the death of the
10634 for (i = regno; i < endregno; i++)
10637 reg_stat[i].last_set = insn;
10639 reg_stat[i].last_set_value = 0;
10640 reg_stat[i].last_set_mode = 0;
10641 reg_stat[i].last_set_nonzero_bits = 0;
10642 reg_stat[i].last_set_sign_bit_copies = 0;
10643 reg_stat[i].last_death = 0;
10646 /* Mark registers that are being referenced in this value. */
10648 update_table_tick (value);
10650 /* Now update the status of each register being set.
10651 If someone is using this register in this block, set this register
10652 to invalid since we will get confused between the two lives in this
10653 basic block. This makes using this register always invalid. In cse, we
10654 scan the table to invalidate all entries using this register, but this
10655 is too much work for us. */
10657 for (i = regno; i < endregno; i++)
10659 reg_stat[i].last_set_label = label_tick;
10660 if (value && reg_stat[i].last_set_table_tick == label_tick)
10661 reg_stat[i].last_set_invalid = 1;
10663 reg_stat[i].last_set_invalid = 0;
10666 /* The value being assigned might refer to X (like in "x++;"). In that
10667 case, we must replace it with (clobber (const_int 0)) to prevent
10669 if (value && ! get_last_value_validate (&value, insn,
10670 reg_stat[regno].last_set_label, 0))
10672 value = copy_rtx (value);
10673 if (! get_last_value_validate (&value, insn,
10674 reg_stat[regno].last_set_label, 1))
10678 /* For the main register being modified, update the value, the mode, the
10679 nonzero bits, and the number of sign bit copies. */
10681 reg_stat[regno].last_set_value = value;
10685 enum machine_mode mode = GET_MODE (reg);
10686 subst_low_cuid = INSN_CUID (insn);
10687 reg_stat[regno].last_set_mode = mode;
10688 if (GET_MODE_CLASS (mode) == MODE_INT
10689 && GET_MODE_BITSIZE (mode) <= HOST_BITS_PER_WIDE_INT)
10690 mode = nonzero_bits_mode;
10691 reg_stat[regno].last_set_nonzero_bits = nonzero_bits (value, mode);
10692 reg_stat[regno].last_set_sign_bit_copies
10693 = num_sign_bit_copies (value, GET_MODE (reg));
10697 /* Called via note_stores from record_dead_and_set_regs to handle one
10698 SET or CLOBBER in an insn. DATA is the instruction in which the
10699 set is occurring. */
10702 record_dead_and_set_regs_1 (rtx dest, rtx setter, void *data)
10704 rtx record_dead_insn = (rtx) data;
10706 if (GET_CODE (dest) == SUBREG)
10707 dest = SUBREG_REG (dest);
10711 /* If we are setting the whole register, we know its value. Otherwise
10712 show that we don't know the value. We can handle SUBREG in
10714 if (GET_CODE (setter) == SET && dest == SET_DEST (setter))
10715 record_value_for_reg (dest, record_dead_insn, SET_SRC (setter));
10716 else if (GET_CODE (setter) == SET
10717 && GET_CODE (SET_DEST (setter)) == SUBREG
10718 && SUBREG_REG (SET_DEST (setter)) == dest
10719 && GET_MODE_BITSIZE (GET_MODE (dest)) <= BITS_PER_WORD
10720 && subreg_lowpart_p (SET_DEST (setter)))
10721 record_value_for_reg (dest, record_dead_insn,
10722 gen_lowpart (GET_MODE (dest),
10723 SET_SRC (setter)));
10725 record_value_for_reg (dest, record_dead_insn, NULL_RTX);
10727 else if (MEM_P (dest)
10728 /* Ignore pushes, they clobber nothing. */
10729 && ! push_operand (dest, GET_MODE (dest)))
10730 mem_last_set = INSN_CUID (record_dead_insn);
10733 /* Update the records of when each REG was most recently set or killed
10734 for the things done by INSN. This is the last thing done in processing
10735 INSN in the combiner loop.
10737 We update reg_stat[], in particular fields last_set, last_set_value,
10738 last_set_mode, last_set_nonzero_bits, last_set_sign_bit_copies,
10739 last_death, and also the similar information mem_last_set (which insn
10740 most recently modified memory) and last_call_cuid (which insn was the
10741 most recent subroutine call). */
10744 record_dead_and_set_regs (rtx insn)
10749 for (link = REG_NOTES (insn); link; link = XEXP (link, 1))
10751 if (REG_NOTE_KIND (link) == REG_DEAD
10752 && REG_P (XEXP (link, 0)))
10754 unsigned int regno = REGNO (XEXP (link, 0));
10755 unsigned int endregno
10756 = regno + (regno < FIRST_PSEUDO_REGISTER
10757 ? hard_regno_nregs[regno][GET_MODE (XEXP (link, 0))]
10760 for (i = regno; i < endregno; i++)
10761 reg_stat[i].last_death = insn;
10763 else if (REG_NOTE_KIND (link) == REG_INC)
10764 record_value_for_reg (XEXP (link, 0), insn, NULL_RTX);
10769 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
10770 if (TEST_HARD_REG_BIT (regs_invalidated_by_call, i))
10772 reg_stat[i].last_set_value = 0;
10773 reg_stat[i].last_set_mode = 0;
10774 reg_stat[i].last_set_nonzero_bits = 0;
10775 reg_stat[i].last_set_sign_bit_copies = 0;
10776 reg_stat[i].last_death = 0;
10779 last_call_cuid = mem_last_set = INSN_CUID (insn);
10781 /* Don't bother recording what this insn does. It might set the
10782 return value register, but we can't combine into a call
10783 pattern anyway, so there's no point trying (and it may cause
10784 a crash, if e.g. we wind up asking for last_set_value of a
10785 SUBREG of the return value register). */
10789 note_stores (PATTERN (insn), record_dead_and_set_regs_1, insn);
10792 /* If a SUBREG has the promoted bit set, it is in fact a property of the
10793 register present in the SUBREG, so for each such SUBREG go back and
10794 adjust nonzero and sign bit information of the registers that are
10795 known to have some zero/sign bits set.
10797 This is needed because when combine blows the SUBREGs away, the
10798 information on zero/sign bits is lost and further combines can be
10799 missed because of that. */
10802 record_promoted_value (rtx insn, rtx subreg)
10805 unsigned int regno = REGNO (SUBREG_REG (subreg));
10806 enum machine_mode mode = GET_MODE (subreg);
10808 if (GET_MODE_BITSIZE (mode) > HOST_BITS_PER_WIDE_INT)
10811 for (links = LOG_LINKS (insn); links;)
10813 insn = XEXP (links, 0);
10814 set = single_set (insn);
10816 if (! set || !REG_P (SET_DEST (set))
10817 || REGNO (SET_DEST (set)) != regno
10818 || GET_MODE (SET_DEST (set)) != GET_MODE (SUBREG_REG (subreg)))
10820 links = XEXP (links, 1);
10824 if (reg_stat[regno].last_set == insn)
10826 if (SUBREG_PROMOTED_UNSIGNED_P (subreg) > 0)
10827 reg_stat[regno].last_set_nonzero_bits &= GET_MODE_MASK (mode);
10830 if (REG_P (SET_SRC (set)))
10832 regno = REGNO (SET_SRC (set));
10833 links = LOG_LINKS (insn);
10840 /* Scan X for promoted SUBREGs. For each one found,
10841 note what it implies to the registers used in it. */
10844 check_promoted_subreg (rtx insn, rtx x)
10846 if (GET_CODE (x) == SUBREG && SUBREG_PROMOTED_VAR_P (x)
10847 && REG_P (SUBREG_REG (x)))
10848 record_promoted_value (insn, x);
10851 const char *format = GET_RTX_FORMAT (GET_CODE (x));
10854 for (i = 0; i < GET_RTX_LENGTH (GET_CODE (x)); i++)
10858 check_promoted_subreg (insn, XEXP (x, i));
10862 if (XVEC (x, i) != 0)
10863 for (j = 0; j < XVECLEN (x, i); j++)
10864 check_promoted_subreg (insn, XVECEXP (x, i, j));
10870 /* Utility routine for the following function. Verify that all the registers
10871 mentioned in *LOC are valid when *LOC was part of a value set when
10872 label_tick == TICK. Return 0 if some are not.
10874 If REPLACE is nonzero, replace the invalid reference with
10875 (clobber (const_int 0)) and return 1. This replacement is useful because
10876 we often can get useful information about the form of a value (e.g., if
10877 it was produced by a shift that always produces -1 or 0) even though
10878 we don't know exactly what registers it was produced from. */
10881 get_last_value_validate (rtx *loc, rtx insn, int tick, int replace)
10884 const char *fmt = GET_RTX_FORMAT (GET_CODE (x));
10885 int len = GET_RTX_LENGTH (GET_CODE (x));
10890 unsigned int regno = REGNO (x);
10891 unsigned int endregno
10892 = regno + (regno < FIRST_PSEUDO_REGISTER
10893 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
10896 for (j = regno; j < endregno; j++)
10897 if (reg_stat[j].last_set_invalid
10898 /* If this is a pseudo-register that was only set once and not
10899 live at the beginning of the function, it is always valid. */
10900 || (! (regno >= FIRST_PSEUDO_REGISTER
10901 && REG_N_SETS (regno) == 1
10902 && (! REGNO_REG_SET_P
10903 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
10905 && reg_stat[j].last_set_label > tick))
10908 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10914 /* If this is a memory reference, make sure that there were
10915 no stores after it that might have clobbered the value. We don't
10916 have alias info, so we assume any store invalidates it. */
10917 else if (MEM_P (x) && !MEM_READONLY_P (x)
10918 && INSN_CUID (insn) <= mem_last_set)
10921 *loc = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx);
10925 for (i = 0; i < len; i++)
10929 /* Check for identical subexpressions. If x contains
10930 identical subexpression we only have to traverse one of
10932 if (i == 1 && ARITHMETIC_P (x))
10934 /* Note that at this point x0 has already been checked
10935 and found valid. */
10936 rtx x0 = XEXP (x, 0);
10937 rtx x1 = XEXP (x, 1);
10939 /* If x0 and x1 are identical then x is also valid. */
10943 /* If x1 is identical to a subexpression of x0 then
10944 while checking x0, x1 has already been checked. Thus
10945 it is valid and so as x. */
10946 if (ARITHMETIC_P (x0)
10947 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1)))
10950 /* If x0 is identical to a subexpression of x1 then x is
10951 valid iff the rest of x1 is valid. */
10952 if (ARITHMETIC_P (x1)
10953 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1)))
10955 get_last_value_validate (&XEXP (x1,
10956 x0 == XEXP (x1, 0) ? 1 : 0),
10957 insn, tick, replace);
10960 if (get_last_value_validate (&XEXP (x, i), insn, tick,
10964 /* Don't bother with these. They shouldn't occur anyway. */
10965 else if (fmt[i] == 'E')
10969 /* If we haven't found a reason for it to be invalid, it is valid. */
10973 /* Get the last value assigned to X, if known. Some registers
10974 in the value may be replaced with (clobber (const_int 0)) if their value
10975 is known longer known reliably. */
10978 get_last_value (rtx x)
10980 unsigned int regno;
10983 /* If this is a non-paradoxical SUBREG, get the value of its operand and
10984 then convert it to the desired mode. If this is a paradoxical SUBREG,
10985 we cannot predict what values the "extra" bits might have. */
10986 if (GET_CODE (x) == SUBREG
10987 && subreg_lowpart_p (x)
10988 && (GET_MODE_SIZE (GET_MODE (x))
10989 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
10990 && (value = get_last_value (SUBREG_REG (x))) != 0)
10991 return gen_lowpart (GET_MODE (x), value);
10997 value = reg_stat[regno].last_set_value;
10999 /* If we don't have a value, or if it isn't for this basic block and
11000 it's either a hard register, set more than once, or it's a live
11001 at the beginning of the function, return 0.
11003 Because if it's not live at the beginning of the function then the reg
11004 is always set before being used (is never used without being set).
11005 And, if it's set only once, and it's always set before use, then all
11006 uses must have the same last value, even if it's not from this basic
11010 || (reg_stat[regno].last_set_label != label_tick
11011 && (regno < FIRST_PSEUDO_REGISTER
11012 || REG_N_SETS (regno) != 1
11013 || (REGNO_REG_SET_P
11014 (ENTRY_BLOCK_PTR->next_bb->il.rtl->global_live_at_start,
11018 /* If the value was set in a later insn than the ones we are processing,
11019 we can't use it even if the register was only set once. */
11020 if (INSN_CUID (reg_stat[regno].last_set) >= subst_low_cuid)
11023 /* If the value has all its registers valid, return it. */
11024 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11025 reg_stat[regno].last_set_label, 0))
11028 /* Otherwise, make a copy and replace any invalid register with
11029 (clobber (const_int 0)). If that fails for some reason, return 0. */
11031 value = copy_rtx (value);
11032 if (get_last_value_validate (&value, reg_stat[regno].last_set,
11033 reg_stat[regno].last_set_label, 1))
11039 /* Return nonzero if expression X refers to a REG or to memory
11040 that is set in an instruction more recent than FROM_CUID. */
11043 use_crosses_set_p (rtx x, int from_cuid)
11047 enum rtx_code code = GET_CODE (x);
11051 unsigned int regno = REGNO (x);
11052 unsigned endreg = regno + (regno < FIRST_PSEUDO_REGISTER
11053 ? hard_regno_nregs[regno][GET_MODE (x)] : 1);
11055 #ifdef PUSH_ROUNDING
11056 /* Don't allow uses of the stack pointer to be moved,
11057 because we don't know whether the move crosses a push insn. */
11058 if (regno == STACK_POINTER_REGNUM && PUSH_ARGS)
11061 for (; regno < endreg; regno++)
11062 if (reg_stat[regno].last_set
11063 && INSN_CUID (reg_stat[regno].last_set) > from_cuid)
11068 if (code == MEM && mem_last_set > from_cuid)
11071 fmt = GET_RTX_FORMAT (code);
11073 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11078 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11079 if (use_crosses_set_p (XVECEXP (x, i, j), from_cuid))
11082 else if (fmt[i] == 'e'
11083 && use_crosses_set_p (XEXP (x, i), from_cuid))
11089 /* Define three variables used for communication between the following
11092 static unsigned int reg_dead_regno, reg_dead_endregno;
11093 static int reg_dead_flag;
11095 /* Function called via note_stores from reg_dead_at_p.
11097 If DEST is within [reg_dead_regno, reg_dead_endregno), set
11098 reg_dead_flag to 1 if X is a CLOBBER and to -1 it is a SET. */
11101 reg_dead_at_p_1 (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
11103 unsigned int regno, endregno;
11108 regno = REGNO (dest);
11109 endregno = regno + (regno < FIRST_PSEUDO_REGISTER
11110 ? hard_regno_nregs[regno][GET_MODE (dest)] : 1);
11112 if (reg_dead_endregno > regno && reg_dead_regno < endregno)
11113 reg_dead_flag = (GET_CODE (x) == CLOBBER) ? 1 : -1;
11116 /* Return nonzero if REG is known to be dead at INSN.
11118 We scan backwards from INSN. If we hit a REG_DEAD note or a CLOBBER
11119 referencing REG, it is dead. If we hit a SET referencing REG, it is
11120 live. Otherwise, see if it is live or dead at the start of the basic
11121 block we are in. Hard regs marked as being live in NEWPAT_USED_REGS
11122 must be assumed to be always live. */
11125 reg_dead_at_p (rtx reg, rtx insn)
11130 /* Set variables for reg_dead_at_p_1. */
11131 reg_dead_regno = REGNO (reg);
11132 reg_dead_endregno = reg_dead_regno + (reg_dead_regno < FIRST_PSEUDO_REGISTER
11133 ? hard_regno_nregs[reg_dead_regno]
11139 /* Check that reg isn't mentioned in NEWPAT_USED_REGS. For fixed registers
11140 we allow the machine description to decide whether use-and-clobber
11141 patterns are OK. */
11142 if (reg_dead_regno < FIRST_PSEUDO_REGISTER)
11144 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11145 if (!fixed_regs[i] && TEST_HARD_REG_BIT (newpat_used_regs, i))
11149 /* Scan backwards until we find a REG_DEAD note, SET, CLOBBER, label, or
11150 beginning of function. */
11151 for (; insn && !LABEL_P (insn) && !BARRIER_P (insn);
11152 insn = prev_nonnote_insn (insn))
11154 note_stores (PATTERN (insn), reg_dead_at_p_1, NULL);
11156 return reg_dead_flag == 1 ? 1 : 0;
11158 if (find_regno_note (insn, REG_DEAD, reg_dead_regno))
11162 /* Get the basic block that we were in. */
11164 block = ENTRY_BLOCK_PTR->next_bb;
11167 FOR_EACH_BB (block)
11168 if (insn == BB_HEAD (block))
11171 if (block == EXIT_BLOCK_PTR)
11175 for (i = reg_dead_regno; i < reg_dead_endregno; i++)
11176 if (REGNO_REG_SET_P (block->il.rtl->global_live_at_start, i))
11182 /* Note hard registers in X that are used. This code is similar to
11183 that in flow.c, but much simpler since we don't care about pseudos. */
11186 mark_used_regs_combine (rtx x)
11188 RTX_CODE code = GET_CODE (x);
11189 unsigned int regno;
11202 case ADDR_DIFF_VEC:
11205 /* CC0 must die in the insn after it is set, so we don't need to take
11206 special note of it here. */
11212 /* If we are clobbering a MEM, mark any hard registers inside the
11213 address as used. */
11214 if (MEM_P (XEXP (x, 0)))
11215 mark_used_regs_combine (XEXP (XEXP (x, 0), 0));
11220 /* A hard reg in a wide mode may really be multiple registers.
11221 If so, mark all of them just like the first. */
11222 if (regno < FIRST_PSEUDO_REGISTER)
11224 unsigned int endregno, r;
11226 /* None of this applies to the stack, frame or arg pointers. */
11227 if (regno == STACK_POINTER_REGNUM
11228 #if FRAME_POINTER_REGNUM != HARD_FRAME_POINTER_REGNUM
11229 || regno == HARD_FRAME_POINTER_REGNUM
11231 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM
11232 || (regno == ARG_POINTER_REGNUM && fixed_regs[regno])
11234 || regno == FRAME_POINTER_REGNUM)
11237 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11238 for (r = regno; r < endregno; r++)
11239 SET_HARD_REG_BIT (newpat_used_regs, r);
11245 /* If setting a MEM, or a SUBREG of a MEM, then note any hard regs in
11247 rtx testreg = SET_DEST (x);
11249 while (GET_CODE (testreg) == SUBREG
11250 || GET_CODE (testreg) == ZERO_EXTRACT
11251 || GET_CODE (testreg) == STRICT_LOW_PART)
11252 testreg = XEXP (testreg, 0);
11254 if (MEM_P (testreg))
11255 mark_used_regs_combine (XEXP (testreg, 0));
11257 mark_used_regs_combine (SET_SRC (x));
11265 /* Recursively scan the operands of this expression. */
11268 const char *fmt = GET_RTX_FORMAT (code);
11270 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
11273 mark_used_regs_combine (XEXP (x, i));
11274 else if (fmt[i] == 'E')
11278 for (j = 0; j < XVECLEN (x, i); j++)
11279 mark_used_regs_combine (XVECEXP (x, i, j));
11285 /* Remove register number REGNO from the dead registers list of INSN.
11287 Return the note used to record the death, if there was one. */
11290 remove_death (unsigned int regno, rtx insn)
11292 rtx note = find_regno_note (insn, REG_DEAD, regno);
11296 REG_N_DEATHS (regno)--;
11297 remove_note (insn, note);
11303 /* For each register (hardware or pseudo) used within expression X, if its
11304 death is in an instruction with cuid between FROM_CUID (inclusive) and
11305 TO_INSN (exclusive), put a REG_DEAD note for that register in the
11306 list headed by PNOTES.
11308 That said, don't move registers killed by maybe_kill_insn.
11310 This is done when X is being merged by combination into TO_INSN. These
11311 notes will then be distributed as needed. */
11314 move_deaths (rtx x, rtx maybe_kill_insn, int from_cuid, rtx to_insn,
11319 enum rtx_code code = GET_CODE (x);
11323 unsigned int regno = REGNO (x);
11324 rtx where_dead = reg_stat[regno].last_death;
11325 rtx before_dead, after_dead;
11327 /* Don't move the register if it gets killed in between from and to. */
11328 if (maybe_kill_insn && reg_set_p (x, maybe_kill_insn)
11329 && ! reg_referenced_p (x, maybe_kill_insn))
11332 /* WHERE_DEAD could be a USE insn made by combine, so first we
11333 make sure that we have insns with valid INSN_CUID values. */
11334 before_dead = where_dead;
11335 while (before_dead && INSN_UID (before_dead) > max_uid_cuid)
11336 before_dead = PREV_INSN (before_dead);
11338 after_dead = where_dead;
11339 while (after_dead && INSN_UID (after_dead) > max_uid_cuid)
11340 after_dead = NEXT_INSN (after_dead);
11342 if (before_dead && after_dead
11343 && INSN_CUID (before_dead) >= from_cuid
11344 && (INSN_CUID (after_dead) < INSN_CUID (to_insn)
11345 || (where_dead != after_dead
11346 && INSN_CUID (after_dead) == INSN_CUID (to_insn))))
11348 rtx note = remove_death (regno, where_dead);
11350 /* It is possible for the call above to return 0. This can occur
11351 when last_death points to I2 or I1 that we combined with.
11352 In that case make a new note.
11354 We must also check for the case where X is a hard register
11355 and NOTE is a death note for a range of hard registers
11356 including X. In that case, we must put REG_DEAD notes for
11357 the remaining registers in place of NOTE. */
11359 if (note != 0 && regno < FIRST_PSEUDO_REGISTER
11360 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11361 > GET_MODE_SIZE (GET_MODE (x))))
11363 unsigned int deadregno = REGNO (XEXP (note, 0));
11364 unsigned int deadend
11365 = (deadregno + hard_regno_nregs[deadregno]
11366 [GET_MODE (XEXP (note, 0))]);
11367 unsigned int ourend
11368 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11371 for (i = deadregno; i < deadend; i++)
11372 if (i < regno || i >= ourend)
11373 REG_NOTES (where_dead)
11374 = gen_rtx_EXPR_LIST (REG_DEAD,
11376 REG_NOTES (where_dead));
11379 /* If we didn't find any note, or if we found a REG_DEAD note that
11380 covers only part of the given reg, and we have a multi-reg hard
11381 register, then to be safe we must check for REG_DEAD notes
11382 for each register other than the first. They could have
11383 their own REG_DEAD notes lying around. */
11384 else if ((note == 0
11386 && (GET_MODE_SIZE (GET_MODE (XEXP (note, 0)))
11387 < GET_MODE_SIZE (GET_MODE (x)))))
11388 && regno < FIRST_PSEUDO_REGISTER
11389 && hard_regno_nregs[regno][GET_MODE (x)] > 1)
11391 unsigned int ourend
11392 = regno + hard_regno_nregs[regno][GET_MODE (x)];
11393 unsigned int i, offset;
11397 offset = hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))];
11401 for (i = regno + offset; i < ourend; i++)
11402 move_deaths (regno_reg_rtx[i],
11403 maybe_kill_insn, from_cuid, to_insn, &oldnotes);
11406 if (note != 0 && GET_MODE (XEXP (note, 0)) == GET_MODE (x))
11408 XEXP (note, 1) = *pnotes;
11412 *pnotes = gen_rtx_EXPR_LIST (REG_DEAD, x, *pnotes);
11414 REG_N_DEATHS (regno)++;
11420 else if (GET_CODE (x) == SET)
11422 rtx dest = SET_DEST (x);
11424 move_deaths (SET_SRC (x), maybe_kill_insn, from_cuid, to_insn, pnotes);
11426 /* In the case of a ZERO_EXTRACT, a STRICT_LOW_PART, or a SUBREG
11427 that accesses one word of a multi-word item, some
11428 piece of everything register in the expression is used by
11429 this insn, so remove any old death. */
11430 /* ??? So why do we test for equality of the sizes? */
11432 if (GET_CODE (dest) == ZERO_EXTRACT
11433 || GET_CODE (dest) == STRICT_LOW_PART
11434 || (GET_CODE (dest) == SUBREG
11435 && (((GET_MODE_SIZE (GET_MODE (dest))
11436 + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
11437 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest)))
11438 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))))
11440 move_deaths (dest, maybe_kill_insn, from_cuid, to_insn, pnotes);
11444 /* If this is some other SUBREG, we know it replaces the entire
11445 value, so use that as the destination. */
11446 if (GET_CODE (dest) == SUBREG)
11447 dest = SUBREG_REG (dest);
11449 /* If this is a MEM, adjust deaths of anything used in the address.
11450 For a REG (the only other possibility), the entire value is
11451 being replaced so the old value is not used in this insn. */
11454 move_deaths (XEXP (dest, 0), maybe_kill_insn, from_cuid,
11459 else if (GET_CODE (x) == CLOBBER)
11462 len = GET_RTX_LENGTH (code);
11463 fmt = GET_RTX_FORMAT (code);
11465 for (i = 0; i < len; i++)
11470 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
11471 move_deaths (XVECEXP (x, i, j), maybe_kill_insn, from_cuid,
11474 else if (fmt[i] == 'e')
11475 move_deaths (XEXP (x, i), maybe_kill_insn, from_cuid, to_insn, pnotes);
11479 /* Return 1 if X is the target of a bit-field assignment in BODY, the
11480 pattern of an insn. X must be a REG. */
11483 reg_bitfield_target_p (rtx x, rtx body)
11487 if (GET_CODE (body) == SET)
11489 rtx dest = SET_DEST (body);
11491 unsigned int regno, tregno, endregno, endtregno;
11493 if (GET_CODE (dest) == ZERO_EXTRACT)
11494 target = XEXP (dest, 0);
11495 else if (GET_CODE (dest) == STRICT_LOW_PART)
11496 target = SUBREG_REG (XEXP (dest, 0));
11500 if (GET_CODE (target) == SUBREG)
11501 target = SUBREG_REG (target);
11503 if (!REG_P (target))
11506 tregno = REGNO (target), regno = REGNO (x);
11507 if (tregno >= FIRST_PSEUDO_REGISTER || regno >= FIRST_PSEUDO_REGISTER)
11508 return target == x;
11510 endtregno = tregno + hard_regno_nregs[tregno][GET_MODE (target)];
11511 endregno = regno + hard_regno_nregs[regno][GET_MODE (x)];
11513 return endregno > tregno && regno < endtregno;
11516 else if (GET_CODE (body) == PARALLEL)
11517 for (i = XVECLEN (body, 0) - 1; i >= 0; i--)
11518 if (reg_bitfield_target_p (x, XVECEXP (body, 0, i)))
11524 /* Given a chain of REG_NOTES originally from FROM_INSN, try to place them
11525 as appropriate. I3 and I2 are the insns resulting from the combination
11526 insns including FROM (I2 may be zero).
11528 ELIM_I2 and ELIM_I1 are either zero or registers that we know will
11529 not need REG_DEAD notes because they are being substituted for. This
11530 saves searching in the most common cases.
11532 Each note in the list is either ignored or placed on some insns, depending
11533 on the type of note. */
11536 distribute_notes (rtx notes, rtx from_insn, rtx i3, rtx i2, rtx elim_i2,
11539 rtx note, next_note;
11542 for (note = notes; note; note = next_note)
11544 rtx place = 0, place2 = 0;
11546 /* If this NOTE references a pseudo register, ensure it references
11547 the latest copy of that register. */
11548 if (XEXP (note, 0) && REG_P (XEXP (note, 0))
11549 && REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER)
11550 XEXP (note, 0) = regno_reg_rtx[REGNO (XEXP (note, 0))];
11552 next_note = XEXP (note, 1);
11553 switch (REG_NOTE_KIND (note))
11557 /* Doesn't matter much where we put this, as long as it's somewhere.
11558 It is preferable to keep these notes on branches, which is most
11559 likely to be i3. */
11563 case REG_VALUE_PROFILE:
11564 /* Just get rid of this note, as it is unused later anyway. */
11567 case REG_NON_LOCAL_GOTO:
11572 gcc_assert (i2 && JUMP_P (i2));
11577 case REG_EH_REGION:
11578 /* These notes must remain with the call or trapping instruction. */
11581 else if (i2 && CALL_P (i2))
11585 gcc_assert (flag_non_call_exceptions);
11586 if (may_trap_p (i3))
11588 else if (i2 && may_trap_p (i2))
11590 /* ??? Otherwise assume we've combined things such that we
11591 can now prove that the instructions can't trap. Drop the
11592 note in this case. */
11598 /* These notes must remain with the call. It should not be
11599 possible for both I2 and I3 to be a call. */
11604 gcc_assert (i2 && CALL_P (i2));
11610 /* Any clobbers for i3 may still exist, and so we must process
11611 REG_UNUSED notes from that insn.
11613 Any clobbers from i2 or i1 can only exist if they were added by
11614 recog_for_combine. In that case, recog_for_combine created the
11615 necessary REG_UNUSED notes. Trying to keep any original
11616 REG_UNUSED notes from these insns can cause incorrect output
11617 if it is for the same register as the original i3 dest.
11618 In that case, we will notice that the register is set in i3,
11619 and then add a REG_UNUSED note for the destination of i3, which
11620 is wrong. However, it is possible to have REG_UNUSED notes from
11621 i2 or i1 for register which were both used and clobbered, so
11622 we keep notes from i2 or i1 if they will turn into REG_DEAD
11625 /* If this register is set or clobbered in I3, put the note there
11626 unless there is one already. */
11627 if (reg_set_p (XEXP (note, 0), PATTERN (i3)))
11629 if (from_insn != i3)
11632 if (! (REG_P (XEXP (note, 0))
11633 ? find_regno_note (i3, REG_UNUSED, REGNO (XEXP (note, 0)))
11634 : find_reg_note (i3, REG_UNUSED, XEXP (note, 0))))
11637 /* Otherwise, if this register is used by I3, then this register
11638 now dies here, so we must put a REG_DEAD note here unless there
11640 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3))
11641 && ! (REG_P (XEXP (note, 0))
11642 ? find_regno_note (i3, REG_DEAD,
11643 REGNO (XEXP (note, 0)))
11644 : find_reg_note (i3, REG_DEAD, XEXP (note, 0))))
11646 PUT_REG_NOTE_KIND (note, REG_DEAD);
11654 /* These notes say something about results of an insn. We can
11655 only support them if they used to be on I3 in which case they
11656 remain on I3. Otherwise they are ignored.
11658 If the note refers to an expression that is not a constant, we
11659 must also ignore the note since we cannot tell whether the
11660 equivalence is still true. It might be possible to do
11661 slightly better than this (we only have a problem if I2DEST
11662 or I1DEST is present in the expression), but it doesn't
11663 seem worth the trouble. */
11665 if (from_insn == i3
11666 && (XEXP (note, 0) == 0 || CONSTANT_P (XEXP (note, 0))))
11671 case REG_NO_CONFLICT:
11672 /* These notes say something about how a register is used. They must
11673 be present on any use of the register in I2 or I3. */
11674 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3)))
11677 if (i2 && reg_mentioned_p (XEXP (note, 0), PATTERN (i2)))
11687 /* This can show up in several ways -- either directly in the
11688 pattern, or hidden off in the constant pool with (or without?)
11689 a REG_EQUAL note. */
11690 /* ??? Ignore the without-reg_equal-note problem for now. */
11691 if (reg_mentioned_p (XEXP (note, 0), PATTERN (i3))
11692 || ((tem = find_reg_note (i3, REG_EQUAL, NULL_RTX))
11693 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11694 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0)))
11698 && (reg_mentioned_p (XEXP (note, 0), PATTERN (i2))
11699 || ((tem = find_reg_note (i2, REG_EQUAL, NULL_RTX))
11700 && GET_CODE (XEXP (tem, 0)) == LABEL_REF
11701 && XEXP (XEXP (tem, 0), 0) == XEXP (note, 0))))
11709 /* Don't attach REG_LABEL note to a JUMP_INSN. Add
11710 a JUMP_LABEL instead or decrement LABEL_NUSES. */
11711 if (place && JUMP_P (place))
11713 rtx label = JUMP_LABEL (place);
11716 JUMP_LABEL (place) = XEXP (note, 0);
11719 gcc_assert (label == XEXP (note, 0));
11720 if (LABEL_P (label))
11721 LABEL_NUSES (label)--;
11725 if (place2 && JUMP_P (place2))
11727 rtx label = JUMP_LABEL (place2);
11730 JUMP_LABEL (place2) = XEXP (note, 0);
11733 gcc_assert (label == XEXP (note, 0));
11734 if (LABEL_P (label))
11735 LABEL_NUSES (label)--;
11742 /* This note says something about the value of a register prior
11743 to the execution of an insn. It is too much trouble to see
11744 if the note is still correct in all situations. It is better
11745 to simply delete it. */
11749 /* If the insn previously containing this note still exists,
11750 put it back where it was. Otherwise move it to the previous
11751 insn. Adjust the corresponding REG_LIBCALL note. */
11752 if (!NOTE_P (from_insn))
11756 tem = find_reg_note (XEXP (note, 0), REG_LIBCALL, NULL_RTX);
11757 place = prev_real_insn (from_insn);
11759 XEXP (tem, 0) = place;
11760 /* If we're deleting the last remaining instruction of a
11761 libcall sequence, don't add the notes. */
11762 else if (XEXP (note, 0) == from_insn)
11764 /* Don't add the dangling REG_RETVAL note. */
11771 /* This is handled similarly to REG_RETVAL. */
11772 if (!NOTE_P (from_insn))
11776 tem = find_reg_note (XEXP (note, 0), REG_RETVAL, NULL_RTX);
11777 place = next_real_insn (from_insn);
11779 XEXP (tem, 0) = place;
11780 /* If we're deleting the last remaining instruction of a
11781 libcall sequence, don't add the notes. */
11782 else if (XEXP (note, 0) == from_insn)
11784 /* Don't add the dangling REG_LIBCALL note. */
11791 /* If the register is used as an input in I3, it dies there.
11792 Similarly for I2, if it is nonzero and adjacent to I3.
11794 If the register is not used as an input in either I3 or I2
11795 and it is not one of the registers we were supposed to eliminate,
11796 there are two possibilities. We might have a non-adjacent I2
11797 or we might have somehow eliminated an additional register
11798 from a computation. For example, we might have had A & B where
11799 we discover that B will always be zero. In this case we will
11800 eliminate the reference to A.
11802 In both cases, we must search to see if we can find a previous
11803 use of A and put the death note there. */
11806 && CALL_P (from_insn)
11807 && find_reg_fusage (from_insn, USE, XEXP (note, 0)))
11809 else if (reg_referenced_p (XEXP (note, 0), PATTERN (i3)))
11811 else if (i2 != 0 && next_nonnote_insn (i2) == i3
11812 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11816 && (rtx_equal_p (XEXP (note, 0), elim_i2)
11817 || rtx_equal_p (XEXP (note, 0), elim_i1)))
11822 basic_block bb = this_basic_block;
11824 /* You might think you could search back from FROM_INSN
11825 rather than from I3, but combine tries to split invalid
11826 combined instructions. This can result in the old I2
11827 or I1 moving later in the insn sequence. */
11828 for (tem = PREV_INSN (i3); place == 0; tem = PREV_INSN (tem))
11830 if (! INSN_P (tem))
11832 if (tem == BB_HEAD (bb))
11837 /* If the register is being set at TEM, see if that is all
11838 TEM is doing. If so, delete TEM. Otherwise, make this
11839 into a REG_UNUSED note instead. Don't delete sets to
11840 global register vars. */
11841 if ((REGNO (XEXP (note, 0)) >= FIRST_PSEUDO_REGISTER
11842 || !global_regs[REGNO (XEXP (note, 0))])
11843 && reg_set_p (XEXP (note, 0), PATTERN (tem)))
11845 rtx set = single_set (tem);
11846 rtx inner_dest = 0;
11848 rtx cc0_setter = NULL_RTX;
11852 for (inner_dest = SET_DEST (set);
11853 (GET_CODE (inner_dest) == STRICT_LOW_PART
11854 || GET_CODE (inner_dest) == SUBREG
11855 || GET_CODE (inner_dest) == ZERO_EXTRACT);
11856 inner_dest = XEXP (inner_dest, 0))
11859 /* Verify that it was the set, and not a clobber that
11860 modified the register.
11862 CC0 targets must be careful to maintain setter/user
11863 pairs. If we cannot delete the setter due to side
11864 effects, mark the user with an UNUSED note instead
11867 if (set != 0 && ! side_effects_p (SET_SRC (set))
11868 && rtx_equal_p (XEXP (note, 0), inner_dest)
11870 && (! reg_mentioned_p (cc0_rtx, SET_SRC (set))
11871 || ((cc0_setter = prev_cc0_setter (tem)) != NULL
11872 && sets_cc0_p (PATTERN (cc0_setter)) > 0))
11876 /* Move the notes and links of TEM elsewhere.
11877 This might delete other dead insns recursively.
11878 First set the pattern to something that won't use
11880 rtx old_notes = REG_NOTES (tem);
11882 PATTERN (tem) = pc_rtx;
11883 REG_NOTES (tem) = NULL;
11885 distribute_notes (old_notes, tem, tem, NULL_RTX,
11886 NULL_RTX, NULL_RTX);
11887 distribute_links (LOG_LINKS (tem));
11889 SET_INSN_DELETED (tem);
11892 /* Delete the setter too. */
11895 PATTERN (cc0_setter) = pc_rtx;
11896 old_notes = REG_NOTES (cc0_setter);
11897 REG_NOTES (cc0_setter) = NULL;
11899 distribute_notes (old_notes, cc0_setter,
11900 cc0_setter, NULL_RTX,
11901 NULL_RTX, NULL_RTX);
11902 distribute_links (LOG_LINKS (cc0_setter));
11904 SET_INSN_DELETED (cc0_setter);
11910 PUT_REG_NOTE_KIND (note, REG_UNUSED);
11912 /* If there isn't already a REG_UNUSED note, put one
11913 here. Do not place a REG_DEAD note, even if
11914 the register is also used here; that would not
11915 match the algorithm used in lifetime analysis
11916 and can cause the consistency check in the
11917 scheduler to fail. */
11918 if (! find_regno_note (tem, REG_UNUSED,
11919 REGNO (XEXP (note, 0))))
11924 else if (reg_referenced_p (XEXP (note, 0), PATTERN (tem))
11926 && find_reg_fusage (tem, USE, XEXP (note, 0))))
11928 /* This may not be the correct place for the death
11929 note if FROM_INSN is before TEM, and the reg is
11930 set between FROM_INSN and TEM. The reg might
11931 die two or more times. An existing death note
11932 means we are looking at the wrong live range. */
11934 && INSN_CUID (from_insn) < INSN_CUID (tem)
11935 && find_regno_note (tem, REG_DEAD,
11936 REGNO (XEXP (note, 0))))
11939 if (tem == BB_HEAD (bb))
11946 /* If we are doing a 3->2 combination, and we have a
11947 register which formerly died in i3 and was not used
11948 by i2, which now no longer dies in i3 and is used in
11949 i2 but does not die in i2, and place is between i2
11950 and i3, then we may need to move a link from place to
11952 if (i2 && INSN_UID (place) <= max_uid_cuid
11953 && INSN_CUID (place) > INSN_CUID (i2)
11955 && INSN_CUID (from_insn) > INSN_CUID (i2)
11956 && reg_referenced_p (XEXP (note, 0), PATTERN (i2)))
11958 rtx links = LOG_LINKS (place);
11959 LOG_LINKS (place) = 0;
11960 distribute_links (links);
11965 if (tem == BB_HEAD (bb))
11969 /* We haven't found an insn for the death note and it
11970 is still a REG_DEAD note, but we have hit the beginning
11971 of the block. If the existing life info says the reg
11972 was dead, there's nothing left to do. Otherwise, we'll
11973 need to do a global life update after combine. */
11974 if (REG_NOTE_KIND (note) == REG_DEAD && place == 0
11975 && REGNO_REG_SET_P (bb->il.rtl->global_live_at_start,
11976 REGNO (XEXP (note, 0))))
11977 SET_BIT (refresh_blocks, this_basic_block->index);
11980 /* If the register is set or already dead at PLACE, we needn't do
11981 anything with this note if it is still a REG_DEAD note.
11982 We check here if it is set at all, not if is it totally replaced,
11983 which is what `dead_or_set_p' checks, so also check for it being
11986 if (place && REG_NOTE_KIND (note) == REG_DEAD)
11988 unsigned int regno = REGNO (XEXP (note, 0));
11990 /* Similarly, if the instruction on which we want to place
11991 the note is a noop, we'll need do a global live update
11992 after we remove them in delete_noop_moves. */
11993 if (noop_move_p (place))
11994 SET_BIT (refresh_blocks, this_basic_block->index);
11996 if (dead_or_set_p (place, XEXP (note, 0))
11997 || reg_bitfield_target_p (XEXP (note, 0), PATTERN (place)))
11999 /* Unless the register previously died in PLACE, clear
12000 last_death. [I no longer understand why this is
12002 if (reg_stat[regno].last_death != place)
12003 reg_stat[regno].last_death = 0;
12007 reg_stat[regno].last_death = place;
12009 /* If this is a death note for a hard reg that is occupying
12010 multiple registers, ensure that we are still using all
12011 parts of the object. If we find a piece of the object
12012 that is unused, we must arrange for an appropriate REG_DEAD
12013 note to be added for it. However, we can't just emit a USE
12014 and tag the note to it, since the register might actually
12015 be dead; so we recourse, and the recursive call then finds
12016 the previous insn that used this register. */
12018 if (place && regno < FIRST_PSEUDO_REGISTER
12019 && hard_regno_nregs[regno][GET_MODE (XEXP (note, 0))] > 1)
12021 unsigned int endregno
12022 = regno + hard_regno_nregs[regno]
12023 [GET_MODE (XEXP (note, 0))];
12027 for (i = regno; i < endregno; i++)
12028 if ((! refers_to_regno_p (i, i + 1, PATTERN (place), 0)
12029 && ! find_regno_fusage (place, USE, i))
12030 || dead_or_set_regno_p (place, i))
12035 /* Put only REG_DEAD notes for pieces that are
12036 not already dead or set. */
12038 for (i = regno; i < endregno;
12039 i += hard_regno_nregs[i][reg_raw_mode[i]])
12041 rtx piece = regno_reg_rtx[i];
12042 basic_block bb = this_basic_block;
12044 if (! dead_or_set_p (place, piece)
12045 && ! reg_bitfield_target_p (piece,
12049 = gen_rtx_EXPR_LIST (REG_DEAD, piece, NULL_RTX);
12051 distribute_notes (new_note, place, place,
12052 NULL_RTX, NULL_RTX, NULL_RTX);
12054 else if (! refers_to_regno_p (i, i + 1,
12055 PATTERN (place), 0)
12056 && ! find_regno_fusage (place, USE, i))
12057 for (tem = PREV_INSN (place); ;
12058 tem = PREV_INSN (tem))
12060 if (! INSN_P (tem))
12062 if (tem == BB_HEAD (bb))
12064 SET_BIT (refresh_blocks,
12065 this_basic_block->index);
12070 if (dead_or_set_p (tem, piece)
12071 || reg_bitfield_target_p (piece,
12075 = gen_rtx_EXPR_LIST (REG_UNUSED, piece,
12090 /* Any other notes should not be present at this point in the
12092 gcc_unreachable ();
12097 XEXP (note, 1) = REG_NOTES (place);
12098 REG_NOTES (place) = note;
12100 else if ((REG_NOTE_KIND (note) == REG_DEAD
12101 || REG_NOTE_KIND (note) == REG_UNUSED)
12102 && REG_P (XEXP (note, 0)))
12103 REG_N_DEATHS (REGNO (XEXP (note, 0)))--;
12107 if ((REG_NOTE_KIND (note) == REG_DEAD
12108 || REG_NOTE_KIND (note) == REG_UNUSED)
12109 && REG_P (XEXP (note, 0)))
12110 REG_N_DEATHS (REGNO (XEXP (note, 0)))++;
12112 REG_NOTES (place2) = gen_rtx_fmt_ee (GET_CODE (note),
12113 REG_NOTE_KIND (note),
12115 REG_NOTES (place2));
12120 /* Similarly to above, distribute the LOG_LINKS that used to be present on
12121 I3, I2, and I1 to new locations. This is also called to add a link
12122 pointing at I3 when I3's destination is changed. */
12125 distribute_links (rtx links)
12127 rtx link, next_link;
12129 for (link = links; link; link = next_link)
12135 next_link = XEXP (link, 1);
12137 /* If the insn that this link points to is a NOTE or isn't a single
12138 set, ignore it. In the latter case, it isn't clear what we
12139 can do other than ignore the link, since we can't tell which
12140 register it was for. Such links wouldn't be used by combine
12143 It is not possible for the destination of the target of the link to
12144 have been changed by combine. The only potential of this is if we
12145 replace I3, I2, and I1 by I3 and I2. But in that case the
12146 destination of I2 also remains unchanged. */
12148 if (NOTE_P (XEXP (link, 0))
12149 || (set = single_set (XEXP (link, 0))) == 0)
12152 reg = SET_DEST (set);
12153 while (GET_CODE (reg) == SUBREG || GET_CODE (reg) == ZERO_EXTRACT
12154 || GET_CODE (reg) == STRICT_LOW_PART)
12155 reg = XEXP (reg, 0);
12157 /* A LOG_LINK is defined as being placed on the first insn that uses
12158 a register and points to the insn that sets the register. Start
12159 searching at the next insn after the target of the link and stop
12160 when we reach a set of the register or the end of the basic block.
12162 Note that this correctly handles the link that used to point from
12163 I3 to I2. Also note that not much searching is typically done here
12164 since most links don't point very far away. */
12166 for (insn = NEXT_INSN (XEXP (link, 0));
12167 (insn && (this_basic_block->next_bb == EXIT_BLOCK_PTR
12168 || BB_HEAD (this_basic_block->next_bb) != insn));
12169 insn = NEXT_INSN (insn))
12170 if (INSN_P (insn) && reg_overlap_mentioned_p (reg, PATTERN (insn)))
12172 if (reg_referenced_p (reg, PATTERN (insn)))
12176 else if (CALL_P (insn)
12177 && find_reg_fusage (insn, USE, reg))
12182 else if (INSN_P (insn) && reg_set_p (reg, insn))
12185 /* If we found a place to put the link, place it there unless there
12186 is already a link to the same insn as LINK at that point. */
12192 for (link2 = LOG_LINKS (place); link2; link2 = XEXP (link2, 1))
12193 if (XEXP (link2, 0) == XEXP (link, 0))
12198 XEXP (link, 1) = LOG_LINKS (place);
12199 LOG_LINKS (place) = link;
12201 /* Set added_links_insn to the earliest insn we added a
12203 if (added_links_insn == 0
12204 || INSN_CUID (added_links_insn) > INSN_CUID (place))
12205 added_links_insn = place;
12211 /* Subroutine of unmentioned_reg_p and callback from for_each_rtx.
12212 Check whether the expression pointer to by LOC is a register or
12213 memory, and if so return 1 if it isn't mentioned in the rtx EXPR.
12214 Otherwise return zero. */
12217 unmentioned_reg_p_1 (rtx *loc, void *expr)
12222 && (REG_P (x) || MEM_P (x))
12223 && ! reg_mentioned_p (x, (rtx) expr))
12228 /* Check for any register or memory mentioned in EQUIV that is not
12229 mentioned in EXPR. This is used to restrict EQUIV to "specializations"
12230 of EXPR where some registers may have been replaced by constants. */
12233 unmentioned_reg_p (rtx equiv, rtx expr)
12235 return for_each_rtx (&equiv, unmentioned_reg_p_1, expr);
12238 /* Compute INSN_CUID for INSN, which is an insn made by combine. */
12241 insn_cuid (rtx insn)
12243 while (insn != 0 && INSN_UID (insn) > max_uid_cuid
12244 && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE)
12245 insn = NEXT_INSN (insn);
12247 gcc_assert (INSN_UID (insn) <= max_uid_cuid);
12249 return INSN_CUID (insn);
12253 dump_combine_stats (FILE *file)
12257 ";; Combiner statistics: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n\n",
12258 combine_attempts, combine_merges, combine_extras, combine_successes);
12262 dump_combine_total_stats (FILE *file)
12266 "\n;; Combiner totals: %d attempts, %d substitutions (%d requiring new space),\n;; %d successes.\n",
12267 total_attempts, total_merges, total_extras, total_successes);
12272 gate_handle_combine (void)
12274 return (optimize > 0);
12277 /* Try combining insns through substitution. */
12279 rest_of_handle_combine (void)
12281 int rebuild_jump_labels_after_combine
12282 = combine_instructions (get_insns (), max_reg_num ());
12284 /* Combining insns may have turned an indirect jump into a
12285 direct jump. Rebuild the JUMP_LABEL fields of jumping
12287 if (rebuild_jump_labels_after_combine)
12289 timevar_push (TV_JUMP);
12290 rebuild_jump_labels (get_insns ());
12291 timevar_pop (TV_JUMP);
12293 delete_dead_jumptables ();
12294 cleanup_cfg (CLEANUP_EXPENSIVE | CLEANUP_UPDATE_LIFE);
12298 struct tree_opt_pass pass_combine =
12300 "combine", /* name */
12301 gate_handle_combine, /* gate */
12302 rest_of_handle_combine, /* execute */
12305 0, /* static_pass_number */
12306 TV_COMBINE, /* tv_id */
12307 0, /* properties_required */
12308 0, /* properties_provided */
12309 0, /* properties_destroyed */
12310 0, /* todo_flags_start */
12312 TODO_ggc_collect, /* todo_flags_finish */
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