/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:40 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:31:36 2012\r
Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
*/\r
\r
reg _reg_59;\r
reg _reg_60;\r
reg _reg_61;\r
- reg _reg_62;\r
+ wire _net_62;\r
wire _net_63;\r
wire _net_64;\r
wire _net_65;\r
- wire _net_66;\r
- wire _net_67;\r
- reg _reg_68;\r
- reg _reg_69;\r
- wire _net_70;\r
+ reg _reg_66;\r
+ reg _reg_67;\r
+ wire _net_68;\r
vga_ram u_FIFO (.o_rdack(_u_FIFO_o_rdack), .o_rddata(_u_FIFO_o_rddata), .i_re(_u_FIFO_i_re), .i_wrdata(_u_FIFO_i_wrdata), .i_we(_u_FIFO_i_we), .i_clk25(_u_FIFO_i_clk25), .i_clk50(_u_FIFO_i_clk50), .i_rst(_u_FIFO_i_rst));\r
\r
- assign fs_fifo_read = _net_63|_reg_60|_net_15;\r
+ assign fs_fifo_read = _reg_60|_net_15;\r
assign w_rddata = _u_FIFO_o_rddata;\r
- assign fs_fifo_ack = _reg_68;\r
+ assign fs_fifo_ack = _reg_66;\r
assign fs_initialize = _net_0;\r
assign _u_FIFO_i_rst = i_fifo_rst;\r
assign _u_FIFO_i_clk50 = i_clk50;\r
assign _net_55 = (r_vcnt)==(10'b0111101011);\r
assign _net_56 = (r_vcnt)==(10'b0111101001);\r
assign _net_57 = (r_vcnt)==(10'b0111100000);\r
- assign _net_63 = fs_initialize|_reg_62;\r
- assign _net_64 = fs_initialize|_reg_61|_reg_62;\r
- assign _net_65 = fs_initialize|_reg_60|_reg_61;\r
- assign _net_66 = fs_initialize|_reg_59|_reg_60;\r
- assign _net_67 = fs_initialize|_reg_58|_reg_59;\r
- assign _net_70 = fs_fifo_read|_reg_68|_reg_69;\r
+ assign _net_62 = fs_initialize|_reg_61;\r
+ assign _net_63 = fs_initialize|_reg_60|_reg_61;\r
+ assign _net_64 = fs_initialize|_reg_59|_reg_60;\r
+ assign _net_65 = fs_initialize|_reg_58|_reg_59;\r
+ assign _net_68 = fs_fifo_read|_reg_66|_reg_67;\r
assign o_vsync = r_vsync;\r
assign o_hsync = r_hsync;\r
assign o_vga_r = ((_net_45|_net_33)?4'b0000:4'b0)|\r
begin\r
if (p_reset)\r
r_data1 <= 8'b00000000;\r
-else if ((_reg_61)|(_net_51|_net_16)) \r
- r_data1 <= ((_reg_61) ?_u_FIFO_o_rddata:8'b0)|\r
+else if ((_net_62)|(_net_51|_net_16)) \r
+ r_data1 <= ((_net_62) ?_u_FIFO_o_rddata:8'b0)|\r
((_net_51|_net_16) ?w_rddata:8'b0);\r
\r
end\r
begin\r
if (p_reset)\r
_reg_58 <= 1'b0;\r
-else if ((_net_67)) \r
+else if ((_net_65)) \r
_reg_58 <= _reg_59;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_59 <= 1'b0;\r
-else if ((_net_66)) \r
+else if ((_net_64)) \r
_reg_59 <= _reg_60;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_60 <= 1'b0;\r
-else if ((_net_65)) \r
- _reg_60 <= _reg_61;\r
+else if ((_net_63)) \r
+ _reg_60 <= _reg_61|fs_initialize;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
_reg_61 <= 1'b0;\r
-else if ((_net_64)) \r
- _reg_61 <= _reg_62|fs_initialize;\r
+else if ((_reg_61)) \r
+ _reg_61 <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_62 <= 1'b0;\r
-else if ((_reg_62)) \r
- _reg_62 <= 1'b0;\r
+ _reg_66 <= 1'b0;\r
+else if ((_net_68)) \r
+ _reg_66 <= _reg_67|fs_fifo_read;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_68 <= 1'b0;\r
-else if ((_net_70)) \r
- _reg_68 <= _reg_69|fs_fifo_read;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_69 <= 1'b0;\r
-else if ((_reg_69)) \r
- _reg_69 <= 1'b0;\r
+ _reg_67 <= 1'b0;\r
+else if ((_reg_67)) \r
+ _reg_67 <= 1'b0;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:44 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:31:45 2012\r
Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r
\r
-module vram ( p_reset , m_clock , clock , data , rdaddress , wraddress , wren , q );\r
+module vram ( p_reset , m_clock , clock , data , rdaddress , wraddress , wren , rden , q );\r
input p_reset, m_clock;\r
input clock;\r
input [7:0] data;\r
input [12:0] rdaddress;\r
input [12:0] wraddress;\r
input wren;\r
+ input rden;\r
output [7:0] q;\r
reg [7:0] m_vram [0:8191];\r
reg [7:0] r_ram_data;\r
begin\r
if (p_reset)\r
r_ram_data <= 8'b00000000;\r
-else r_ram_data <= m_vram[rdaddress];\r
+else if ((rden)) \r
+ r_ram_data <= m_vram[rdaddress];\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:45 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:31:48 2012\r
Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r
\r
reg r_rise_flag;\r
reg r_sw_hld;\r
reg r_finish_flag;\r
+ wire _net_69;\r
+ wire _net_70;\r
wire _net_71;\r
wire _net_72;\r
wire _net_73;\r
wire _net_77;\r
wire _net_78;\r
wire _net_79;\r
- wire _net_80;\r
- wire _net_81;\r
\r
- assign _net_71 = i_sw&(~r_sw_hld);\r
- assign _net_72 = ~i_sw;\r
- assign _net_73 = ~_net_71;\r
- assign _net_74 = (~_net_71)&_net_72;\r
- assign _net_75 = (~_net_71)&_net_72;\r
- assign _net_76 = (r_rise_flag)==(1'b1);\r
- assign _net_77 = ((r_cnt)==(19'b1111010000100100000))&((r_finish_flag)==(1'b0));\r
- assign _net_78 = _net_76&_net_77;\r
- assign _net_79 = _net_76&_net_77;\r
- assign _net_80 = _net_76&(~_net_77);\r
- assign _net_81 = ~_net_76;\r
- assign fo_sw_enb = _net_79;\r
+ assign _net_69 = i_sw&(~r_sw_hld);\r
+ assign _net_70 = ~i_sw;\r
+ assign _net_71 = ~_net_69;\r
+ assign _net_72 = (~_net_69)&_net_70;\r
+ assign _net_73 = (~_net_69)&_net_70;\r
+ assign _net_74 = (r_rise_flag)==(1'b1);\r
+ assign _net_75 = ((r_cnt)==(19'b1111010000100100000))&((r_finish_flag)==(1'b0));\r
+ assign _net_76 = _net_74&_net_75;\r
+ assign _net_77 = _net_74&_net_75;\r
+ assign _net_78 = _net_74&(~_net_75);\r
+ assign _net_79 = ~_net_74;\r
+ assign fo_sw_enb = _net_77;\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_cnt <= 19'b0000000000000000000;\r
-else if ((_net_81)|(_net_80)) \r
- r_cnt <= ((_net_81) ?26'b00000000000000000000000000:19'b0)|\r
- ((_net_80) ?(r_cnt)+(19'b0000000000000000001):19'b0);\r
+else if ((_net_79)|(_net_78)) \r
+ r_cnt <= ((_net_79) ?26'b00000000000000000000000000:19'b0)|\r
+ ((_net_78) ?(r_cnt)+(19'b0000000000000000001):19'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_rise_flag <= 1'b0;\r
-else if ((_net_74)|(_net_71)) \r
- r_rise_flag <= ((_net_74) ?1'b0:1'b0)|\r
- ((_net_71) ?1'b1:1'b0);\r
+else if ((_net_72)|(_net_69)) \r
+ r_rise_flag <= ((_net_72) ?1'b0:1'b0)|\r
+ ((_net_69) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_finish_flag <= 1'b0;\r
-else if ((_net_78)|(_net_75)) \r
- r_finish_flag <= ((_net_78) ?1'b1:1'b0)|\r
- ((_net_75) ?1'b0:1'b0);\r
+else if ((_net_76)|(_net_73)) \r
+ r_finish_flag <= ((_net_76) ?1'b1:1'b0)|\r
+ ((_net_73) ?1'b0:1'b0);\r
\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:45 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:31:52 2012\r
Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r
\r
reg [25:0] r_sec_cnt;\r
reg r_LED;\r
reg [12:0] r_init_cnt;\r
- reg [13:0] r_vram_adrs;\r
- reg [13:0] r_vram_adrs_temp;\r
reg [15:0] r_vram_rddata;\r
- reg [12:0] r_vram_start_adrs;\r
- reg r_fifo_write_adrs;\r
reg r_fifo_rst;\r
reg r_vga_ack_hld;\r
+ reg [13:0] r_vram_adrs;\r
+ reg [13:0] r_vram_temp_adrs;\r
wire [7:0] w_data;\r
wire [15:0] w_exp_data;\r
+ wire [12:0] w_rdadrs;\r
+ wire [12:0] w_wradrs;\r
+ wire [7:0] w_wrdata;\r
wire fs_exp_exec;\r
wire fs_init;\r
- wire fs_fifo_write;\r
+ wire fs_vram_read;\r
+ wire fs_vram_write;\r
+ wire fs_vgagen_write;\r
reg r_out_sel;\r
wire test_write;\r
reg [25:0] r_wait_cnt;\r
reg [25:0] r_wait_val;\r
reg p_wait;\r
- wire [12:0] _net_84;\r
+ wire [12:0] _net_82;\r
+ wire [12:0] _net_85;\r
+ wire [12:0] _net_88;\r
wire _proc_p_wait_set;\r
wire _proc_p_wait_reset;\r
- wire _net_85;\r
+ wire _net_89;\r
wire _u_VGA_i_clk50;\r
wire _u_VGA_i_fifo_rst;\r
wire _u_VGA_m_clock;\r
wire [12:0] _u_VRAM_rdaddress;\r
wire [12:0] _u_VRAM_wraddress;\r
wire _u_VRAM_wren;\r
+ wire _u_VRAM_rden;\r
wire [7:0] _u_VRAM_q;\r
wire _u_VRAM_p_reset;\r
wire _u_VRAM_m_clock;\r
- wire _net_86;\r
- wire _net_87;\r
- wire _net_88;\r
- wire _net_89;\r
wire _net_90;\r
wire _net_91;\r
wire _net_92;\r
wire _net_93;\r
- reg _reg_94;\r
- reg _reg_95;\r
- reg _reg_96;\r
- reg _reg_97;\r
+ wire _net_94;\r
+ wire _net_95;\r
+ wire _net_96;\r
+ wire _net_97;\r
reg _reg_98;\r
reg _reg_99;\r
reg _reg_100;\r
reg _reg_103;\r
reg _reg_104;\r
reg _reg_105;\r
- wire _net_106;\r
- wire _net_107;\r
- wire _net_108;\r
- wire _net_109;\r
- wire _net_110;\r
- wire _net_111;\r
- wire _net_112;\r
- wire _net_113;\r
- wire _net_114;\r
- wire _net_115;\r
- wire _net_116;\r
- wire _net_117;\r
- wire _net_118;\r
- wire _net_119;\r
- wire _net_120;\r
- wire _net_121;\r
- wire _net_122;\r
+ reg _reg_106;\r
+ reg _reg_107;\r
+ reg _reg_108;\r
+ reg _reg_109;\r
+ reg _reg_110;\r
+ reg _reg_111;\r
+ reg _reg_112;\r
+ reg _reg_113;\r
+ reg _reg_114;\r
+ reg _reg_115;\r
+ reg _reg_116;\r
+ reg _reg_117;\r
+ reg _reg_118;\r
+ reg _reg_119;\r
+ reg _reg_120;\r
+ reg _reg_121;\r
+ reg _reg_122;\r
reg _reg_123;\r
- reg _reg_124;\r
- reg _reg_125;\r
- reg _reg_126;\r
+ wire _net_124;\r
+ wire _net_125;\r
+ wire _reg_114_goto;\r
+ wire _net_126;\r
+ wire _reg_113_goin;\r
wire _net_127;\r
- wire _reg_124_goto;\r
wire _net_128;\r
- wire _reg_125_goin;\r
wire _net_129;\r
wire _net_130;\r
- wire _reg_125_goto;\r
wire _net_131;\r
- wire _reg_123_goin;\r
wire _net_132;\r
+ wire _reg_114_goin;\r
wire _net_133;\r
wire _net_134;\r
wire _net_135;\r
wire _net_136;\r
wire _net_137;\r
wire _net_138;\r
-vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .wren(_u_VRAM_wren), .wraddress(_u_VRAM_wraddress), .rdaddress(_u_VRAM_rdaddress), .data(_u_VRAM_data), .clock(_u_VRAM_clock));\r
+ wire _net_139;\r
+ wire _net_140;\r
+ wire _net_141;\r
+ wire _net_142;\r
+ wire _net_143;\r
+ wire _net_144;\r
+ wire _net_145;\r
+ wire _net_146;\r
+ wire _net_147;\r
+ wire _net_148;\r
+ wire _net_149;\r
+ wire _net_150;\r
+ wire _net_151;\r
+ wire _net_152;\r
+ wire _net_153;\r
+ wire _net_154;\r
+ wire _net_155;\r
+ wire _net_156;\r
+ wire _net_157;\r
+ wire _net_158;\r
+ wire _net_159;\r
+ wire _net_160;\r
+ wire _net_161;\r
+ wire _net_162;\r
+ wire _net_163;\r
+ wire _net_164;\r
+ wire _net_165;\r
+ wire _net_166;\r
+ reg _reg_167;\r
+ reg _reg_168;\r
+ reg _reg_169;\r
+ reg _reg_170;\r
+ reg _reg_171;\r
+ reg _reg_172;\r
+ reg _reg_173;\r
+ reg _reg_174;\r
+ reg _reg_175;\r
+ reg _reg_176;\r
+ reg _reg_177;\r
+ reg _reg_178;\r
+ reg _reg_179;\r
+ reg _reg_180;\r
+ reg _reg_181;\r
+ wire _net_182;\r
+ wire _net_183;\r
+ wire _net_184;\r
+ wire _net_185;\r
+ wire _reg_168_goto;\r
+ wire _net_186;\r
+ wire _reg_172_goin;\r
+ wire _net_187;\r
+ wire _net_188;\r
+ wire _net_189;\r
+ wire _net_190;\r
+ wire _reg_172_goto;\r
+ wire _net_191;\r
+ wire _reg_167_goin;\r
+ wire _net_192;\r
+ wire _net_193;\r
+ wire _net_194;\r
+ wire _net_195;\r
+ wire _net_196;\r
+ wire _net_197;\r
+ wire _net_198;\r
+ wire _reg_175_goto;\r
+ wire _net_199;\r
+ wire _reg_179_goin;\r
+ wire _net_200;\r
+ wire _net_201;\r
+ wire _net_202;\r
+ wire _net_203;\r
+ wire _reg_179_goto;\r
+ wire _net_204;\r
+ wire _reg_174_goin;\r
+ wire _net_205;\r
+ wire _net_206;\r
+ wire _net_207;\r
+ wire _net_208;\r
+ wire _net_209;\r
+ wire _net_210;\r
+ wire _net_211;\r
+ wire _net_212;\r
+ wire _net_213;\r
+ wire _net_214;\r
+ wire _net_215;\r
+ wire _net_216;\r
+ wire _net_217;\r
+ wire _net_218;\r
+ wire _net_219;\r
+ wire _net_220;\r
+ wire _net_221;\r
+ wire _net_222;\r
+ wire _net_223;\r
+ wire _net_224;\r
+ wire _net_225;\r
+vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .rden(_u_VRAM_rden), .wren(_u_VRAM_wren), .wraddress(_u_VRAM_wraddress), .rdaddress(_u_VRAM_rdaddress), .data(_u_VRAM_data), .clock(_u_VRAM_clock));\r
push_sw u_BTN (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_fo_sw_enb), .i_sw(_u_BTN_i_sw));\r
push_sw u_BTN_3 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_3_fo_sw_enb), .i_sw(_u_BTN_3_i_sw));\r
push_sw u_BTN_2 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_2_fo_sw_enb), .i_sw(_u_BTN_2_i_sw));\r
push_sw u_BTN_1 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_1_fo_sw_enb), .i_sw(_u_BTN_1_i_sw));\r
vga_gen u_VGA (.o_led(_u_VGA_o_led), .o_rdack(_u_VGA_o_rdack), .fi_fifo_write(_u_VGA_fi_fifo_write), .i_wrdata(_u_VGA_i_wrdata), .o_vcnt(_u_VGA_o_vcnt), .o_dummy_rgb(_u_VGA_o_dummy_rgb), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_fifo_rst(_u_VGA_i_fifo_rst), .i_clk50(_u_VGA_i_clk50));\r
\r
+ assign w_data = _u_VRAM_q;\r
assign w_exp_data = {w_data[7],w_data[7],w_data[6],w_data[6],w_data[5],w_data[5],w_data[4],w_data[4],w_data[3],w_data[3],w_data[2],w_data[2],w_data[1],w_data[1],w_data[0],w_data[0]};\r
- assign fs_exp_exec = 1'b0;\r
- assign fs_init = _net_90;\r
- assign fs_fifo_write = _reg_97|_net_106|_net_93;\r
+ assign w_rdadrs = r_vram_temp_adrs[12:0];\r
+ assign w_wradrs = ((_net_136)?r_init_cnt:13'b0)|\r
+ ((_reg_113)?13'b0000000000000:13'b0)|\r
+ ((_reg_112)?13'b0000000101000:13'b0)|\r
+ ((_reg_111)?13'b0000001010000:13'b0)|\r
+ ((_reg_110)?13'b0000001111000:13'b0)|\r
+ ((_reg_109)?13'b0000010100000:13'b0)|\r
+ ((_reg_108)?13'b0000011001000:13'b0)|\r
+ ((_reg_107)?13'b0000011110000:13'b0)|\r
+ ((_reg_106)?13'b0000100011000:13'b0);\r
+ assign w_wrdata = ((_reg_113)?8'b00111100:8'b0)|\r
+ ((_reg_110)?8'b01111110:8'b0)|\r
+ ((_reg_112|_reg_111|_reg_109|_reg_108|_reg_107)?8'b01100110:8'b0)|\r
+ ((_net_135|_reg_106)?8'b00000000:8'b0);\r
+ assign fs_exp_exec = _net_202|_net_189;\r
+ assign fs_init = _net_94;\r
+ assign fs_vram_read = _net_208|_net_195;\r
+ assign fs_vram_write = _net_134|_reg_113|_reg_112|_reg_111|_reg_110|_reg_109|_reg_108|_reg_107|_reg_106;\r
+ assign fs_vgagen_write = _net_124|_reg_101|_net_97;\r
assign test_write = 1'b0;\r
- assign _net_84 = (r_init_cnt)+(13'b0000000000001);\r
- assign _proc_p_wait_set = _reg_96;\r
- assign _proc_p_wait_reset = _net_121;\r
- assign _net_85 = _proc_p_wait_set|_proc_p_wait_reset;\r
+ assign _net_82 = (r_init_cnt)+(13'b0000000000001);\r
+ assign _net_85 = (r_init_cnt)+(13'b0000000000001);\r
+ assign _net_88 = (r_init_cnt)+(13'b0000000000001);\r
+ assign _proc_p_wait_set = _reg_105|_reg_103|_reg_100;\r
+ assign _proc_p_wait_reset = _net_165;\r
+ assign _net_89 = _proc_p_wait_set|_proc_p_wait_reset;\r
assign _u_VGA_i_clk50 = m_clock;\r
assign _u_VGA_i_fifo_rst = r_fifo_rst;\r
assign _u_VGA_m_clock = r_cnt;\r
assign _u_VGA_p_reset = r_reset;\r
- assign _u_VGA_i_wrdata = ((_net_134)?{{7{r_fifo_write_adrs}},r_fifo_write_adrs}:8'b0)|\r
- ((_reg_124)?~({{7{r_fifo_write_adrs}},r_fifo_write_adrs}):8'b0);\r
- assign _u_VGA_fi_fifo_write = _net_133|_reg_124;\r
+ assign _u_VGA_i_wrdata = ((_reg_177|_reg_170)?r_vram_rddata[7:0]:8'b0)|\r
+ ((_reg_176|_reg_169)?r_vram_rddata[15:8]:8'b0);\r
+ assign _u_VGA_fi_fifo_write = _reg_177|_reg_176|_reg_170|_reg_169;\r
assign _u_BTN_i_sw = i_sw[0];\r
assign _u_BTN_3_i_sw = i_sw[3];\r
assign _u_BTN_2_i_sw = i_sw[2];\r
assign _u_BTN_1_i_sw = i_sw[1];\r
- assign _net_86 = (r_out_sel)==(1'b0);\r
- assign _net_87 = ~_net_86;\r
- assign _net_88 = ~_net_86;\r
- assign _net_89 = ~_net_86;\r
- assign _net_90 = (trigger)==(3'b011);\r
- assign _net_91 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
- assign _net_92 = ~_net_91;\r
- assign _net_93 = (~r_vga_ack_hld)&_u_VGA_o_rdack;\r
- assign _net_106 = _reg_95&p_wait&_proc_p_wait_reset;\r
- assign _net_107 = fs_init|_reg_105;\r
- assign _net_108 = fs_init|_reg_104|_reg_105;\r
- assign _net_109 = fs_init|_reg_103|_reg_104;\r
- assign _net_110 = fs_init|_reg_102|_reg_103;\r
- assign _net_111 = fs_init|_reg_101|_reg_102;\r
- assign _net_112 = fs_init|_reg_100|_reg_101;\r
- assign _net_113 = fs_init|_reg_99|_reg_100;\r
- assign _net_114 = fs_init|_reg_98|_reg_99;\r
- assign _net_115 = fs_init|_reg_97|_reg_98;\r
- assign _net_116 = fs_init|_reg_96|_reg_97;\r
- assign _net_117 = fs_init|_reg_95|_reg_96;\r
- assign _net_118 = fs_init|_reg_94|_reg_95;\r
- assign _net_119 = (r_wait_cnt)==(r_wait_val);\r
- assign _net_120 = p_wait&_net_119;\r
- assign _net_121 = p_wait&_net_119;\r
- assign _net_122 = p_wait&(~_net_119);\r
- assign _net_127 = (_net_84) < (13'b0000001010000);\r
- assign _reg_124_goto = _net_128;\r
- assign _net_128 = _reg_124&_net_127;\r
- assign _reg_125_goin = _net_129;\r
- assign _net_129 = _reg_124&_net_127;\r
- assign _net_130 = ~((r_init_cnt) < (13'b0000001010000));\r
- assign _reg_125_goto = _net_131;\r
- assign _net_131 = _reg_125&_net_130;\r
- assign _reg_123_goin = _net_132;\r
- assign _net_132 = _reg_125&_net_130;\r
- assign _net_133 = _reg_125&(~_net_130);\r
- assign _net_134 = _reg_125&(~_net_130);\r
- assign _net_135 = fs_fifo_write|_reg_126;\r
- assign _net_136 = (_reg_125_goin|fs_fifo_write)|_reg_125|_reg_126;\r
- assign _net_137 = (_reg_125_goin|fs_fifo_write)|_reg_124|_reg_125;\r
- assign _net_138 = _reg_123_goin|_reg_123|_reg_124;\r
+ assign _u_VRAM_data = w_wrdata;\r
+ assign _u_VRAM_rdaddress = w_rdadrs;\r
+ assign _u_VRAM_wraddress = w_wradrs;\r
+ assign _u_VRAM_wren = fs_vram_write;\r
+ assign _u_VRAM_rden = fs_vram_read;\r
+ assign _net_90 = (r_out_sel)==(1'b0);\r
+ assign _net_91 = ~_net_90;\r
+ assign _net_92 = ~_net_90;\r
+ assign _net_93 = ~_net_90;\r
+ assign _net_94 = (trigger)==(3'b011);\r
+ assign _net_95 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
+ assign _net_96 = ~_net_95;\r
+ assign _net_97 = (~r_vga_ack_hld)&_u_VGA_o_rdack;\r
+ assign _net_124 = _reg_104&p_wait&_proc_p_wait_reset;\r
+ assign _net_125 = ~((r_init_cnt) < (13'b1111111111111));\r
+ assign _reg_114_goto = _net_132|_net_126;\r
+ assign _net_126 = _reg_114&_net_125;\r
+ assign _reg_113_goin = _net_127;\r
+ assign _net_127 = _reg_114&_net_125;\r
+ assign _net_128 = _reg_114&(~_net_125);\r
+ assign _net_129 = _reg_114&(~_net_125);\r
+ assign _net_130 = (_net_82) < (13'b1111111111111);\r
+ assign _net_131 = _reg_114&(~_net_125);\r
+ assign _net_132 = (_reg_114&(~_net_125))&_net_130;\r
+ assign _reg_114_goin = _net_133;\r
+ assign _net_133 = (_reg_114&(~_net_125))&_net_130;\r
+ assign _net_134 = _reg_114&(~_net_125);\r
+ assign _net_135 = _reg_114&(~_net_125);\r
+ assign _net_136 = _reg_114&(~_net_125);\r
+ assign _net_137 = fs_init|_reg_123;\r
+ assign _net_138 = fs_init|_reg_122|_reg_123;\r
+ assign _net_139 = fs_init|_reg_121|_reg_122;\r
+ assign _net_140 = fs_init|_reg_120|_reg_121;\r
+ assign _net_141 = fs_init|_reg_119|_reg_120;\r
+ assign _net_142 = fs_init|_reg_118|_reg_119;\r
+ assign _net_143 = fs_init|_reg_117|_reg_118;\r
+ assign _net_144 = fs_init|_reg_116|_reg_117;\r
+ assign _net_145 = fs_init|_reg_115|_reg_116;\r
+ assign _net_146 = _reg_114_goin|_reg_114|_reg_115;\r
+ assign _net_147 = _reg_113_goin|_reg_113|_reg_114;\r
+ assign _net_148 = _reg_113_goin|_reg_112|_reg_113;\r
+ assign _net_149 = _reg_113_goin|_reg_111|_reg_112;\r
+ assign _net_150 = _reg_113_goin|_reg_110|_reg_111;\r
+ assign _net_151 = _reg_113_goin|_reg_109|_reg_110;\r
+ assign _net_152 = _reg_113_goin|_reg_108|_reg_109;\r
+ assign _net_153 = _reg_113_goin|_reg_107|_reg_108;\r
+ assign _net_154 = _reg_113_goin|_reg_106|_reg_107;\r
+ assign _net_155 = _reg_113_goin|_reg_105|_reg_106;\r
+ assign _net_156 = _reg_113_goin|_reg_104|_reg_105;\r
+ assign _net_157 = _reg_113_goin|_reg_103|_reg_104;\r
+ assign _net_158 = _reg_113_goin|_reg_102|_reg_103;\r
+ assign _net_159 = _reg_113_goin|_reg_101|_reg_102;\r
+ assign _net_160 = _reg_113_goin|_reg_100|_reg_101;\r
+ assign _net_161 = _reg_113_goin|_reg_99|_reg_100;\r
+ assign _net_162 = _reg_113_goin|_reg_98|_reg_99;\r
+ assign _net_163 = (r_wait_cnt)==(r_wait_val);\r
+ assign _net_164 = p_wait&_net_163;\r
+ assign _net_165 = p_wait&_net_163;\r
+ assign _net_166 = p_wait&(~_net_163);\r
+ assign _net_182 = (r_vram_adrs) >= (14'b10010101010111);\r
+ assign _net_183 = _reg_167&_net_182;\r
+ assign _net_184 = _reg_167&(~_net_182);\r
+ assign _net_185 = (_net_88) < (13'b0000000101000);\r
+ assign _reg_168_goto = _net_186;\r
+ assign _net_186 = _reg_168&_net_185;\r
+ assign _reg_172_goin = _net_187;\r
+ assign _net_187 = _reg_168&_net_185;\r
+ assign _net_188 = (r_vram_adrs) < (14'b01111000000000);\r
+ assign _net_189 = _reg_171&_net_188;\r
+ assign _net_190 = ~((r_init_cnt) < (13'b0000000101000));\r
+ assign _reg_172_goto = _net_191;\r
+ assign _net_191 = _reg_172&_net_190;\r
+ assign _reg_167_goin = _net_192;\r
+ assign _net_192 = _reg_172&_net_190;\r
+ assign _net_193 = (r_vram_adrs) < (14'b01111000000000);\r
+ assign _net_194 = _reg_172&(~_net_190);\r
+ assign _net_195 = (_reg_172&(~_net_190))&_net_193;\r
+ assign _net_196 = (_reg_172&(~_net_190))&_net_193;\r
+ assign _net_197 = (_reg_172&(~_net_190))&(~_net_193);\r
+ assign _net_198 = (_net_85) < (13'b0000000101000);\r
+ assign _reg_175_goto = _net_199;\r
+ assign _net_199 = _reg_175&_net_198;\r
+ assign _reg_179_goin = _net_200;\r
+ assign _net_200 = _reg_175&_net_198;\r
+ assign _net_201 = (r_vram_adrs) < (14'b01111000000000);\r
+ assign _net_202 = _reg_178&_net_201;\r
+ assign _net_203 = ~((r_init_cnt) < (13'b0000000101000));\r
+ assign _reg_179_goto = _net_204;\r
+ assign _net_204 = _reg_179&_net_203;\r
+ assign _reg_174_goin = _net_205;\r
+ assign _net_205 = _reg_179&_net_203;\r
+ assign _net_206 = (r_vram_adrs) < (14'b01111000000000);\r
+ assign _net_207 = _reg_179&(~_net_203);\r
+ assign _net_208 = (_reg_179&(~_net_203))&_net_206;\r
+ assign _net_209 = (_reg_179&(~_net_203))&_net_206;\r
+ assign _net_210 = (_reg_179&(~_net_203))&(~_net_206);\r
+ assign _net_211 = fs_vgagen_write|_reg_181;\r
+ assign _net_212 = fs_vgagen_write|_reg_180|_reg_181;\r
+ assign _net_213 = _reg_179_goin|_reg_179|_reg_180;\r
+ assign _net_214 = _reg_179_goin|_reg_178|_reg_179;\r
+ assign _net_215 = _reg_179_goin|_reg_177|_reg_178;\r
+ assign _net_216 = _reg_179_goin|_reg_176|_reg_177;\r
+ assign _net_217 = _reg_179_goin|_reg_175|_reg_176;\r
+ assign _net_218 = _reg_174_goin|_reg_174|_reg_175;\r
+ assign _net_219 = _reg_174_goin|_reg_173|_reg_174;\r
+ assign _net_220 = _reg_172_goin|_reg_172|_reg_173;\r
+ assign _net_221 = _reg_172_goin|_reg_171|_reg_172;\r
+ assign _net_222 = _reg_172_goin|_reg_170|_reg_171;\r
+ assign _net_223 = _reg_172_goin|_reg_169|_reg_170;\r
+ assign _net_224 = _reg_172_goin|_reg_168|_reg_169;\r
+ assign _net_225 = _reg_167_goin|_reg_167|_reg_168;\r
assign o_vsync = _u_VGA_o_vsync;\r
assign o_hsync = _u_VGA_o_hsync;\r
- assign o_vga_r = ((_net_87)?_u_VGA_o_vga_r:4'b0)|\r
- ((_net_86)?{{3{_u_VGA_o_dummy_rgb[2]}},_u_VGA_o_dummy_rgb[2]}:4'b0);\r
- assign o_vga_g = ((_net_88)?_u_VGA_o_vga_g:4'b0)|\r
- ((_net_86)?{{3{_u_VGA_o_dummy_rgb[1]}},_u_VGA_o_dummy_rgb[1]}:4'b0);\r
- assign o_vga_b = ((_net_89)?_u_VGA_o_vga_b:4'b0)|\r
- ((_net_86)?{{3{_u_VGA_o_dummy_rgb[0]}},_u_VGA_o_dummy_rgb[0]}:4'b0);\r
+ assign o_vga_r = ((_net_91)?_u_VGA_o_vga_r:4'b0)|\r
+ ((_net_90)?{{3{_u_VGA_o_dummy_rgb[2]}},_u_VGA_o_dummy_rgb[2]}:4'b0);\r
+ assign o_vga_g = ((_net_92)?_u_VGA_o_vga_g:4'b0)|\r
+ ((_net_90)?{{3{_u_VGA_o_dummy_rgb[1]}},_u_VGA_o_dummy_rgb[1]}:4'b0);\r
+ assign o_vga_b = ((_net_93)?_u_VGA_o_vga_b:4'b0)|\r
+ ((_net_90)?{{3{_u_VGA_o_dummy_rgb[0]}},_u_VGA_o_dummy_rgb[0]}:4'b0);\r
assign o_LED = {2'b00,i_sw,r_LED,_u_VGA_o_led};\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
begin\r
if (p_reset)\r
r_reset <= 1'b1;\r
-else if ((_reg_94)) \r
+else if ((_reg_98)) \r
r_reset <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_sec_cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_92)|(_net_91)) \r
- r_sec_cnt <= ((_net_92) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_91) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_96)|(_net_95)) \r
+ r_sec_cnt <= ((_net_96) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_95) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_LED <= 1'b0;\r
-else if ((_net_91)) \r
+else if ((_net_95)) \r
r_LED <= ~r_LED;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_init_cnt <= 13'b0000000000000;\r
-else if ((_net_135)|(_reg_124)) \r
- r_init_cnt <= ((_net_135) ?13'b0000000000000:13'b0)|\r
- ((_reg_124) ?_net_84:13'b0);\r
+else if ((_reg_175)|(_reg_168)|(_reg_180|_reg_173|_reg_115)|(_net_128)) \r
+ r_init_cnt <= ((_reg_175) ?_net_85:13'b0)|\r
+ ((_reg_168) ?_net_88:13'b0)|\r
+ ((_reg_180|_reg_173|_reg_115) ?13'b0000000000000:13'b0)|\r
+ ((_net_128) ?_net_82:13'b0);\r
\r
end\r
-always @(posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_vram_adrs <= 14'b00000000000000;\r
-end\r
-always @(posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_vram_adrs_temp <= 14'b00000000000000;\r
-end\r
-always @(posedge p_reset)\r
- begin\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
if (p_reset)\r
r_vram_rddata <= 16'b0000000000000000;\r
+else if ((_net_210|_net_197)|(_net_202|_net_189)) \r
+ r_vram_rddata <= ((_net_210|_net_197) ?16'b0000000000000000:16'b0)|\r
+ ((_net_202|_net_189) ?w_exp_data:16'b0);\r
+\r
end\r
-always @(posedge p_reset)\r
- begin\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
if (p_reset)\r
- r_vram_start_adrs <= 13'b0000000000000;\r
+ r_fifo_rst <= 1'b0;\r
+else if ((_net_137)|(_reg_119)) \r
+ r_fifo_rst <= ((_net_137) ?1'b1:1'b0)|\r
+ ((_reg_119) ?1'b0:1'b0);\r
+\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_fifo_write_adrs <= 1'b0;\r
-else if ((_reg_123)) \r
- r_fifo_write_adrs <= ~r_fifo_write_adrs;\r
+ r_vga_ack_hld <= 1'b0;\r
+else r_vga_ack_hld <= _u_VGA_o_rdack;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_fifo_rst <= 1'b0;\r
-else if ((_net_107)|(_reg_101)) \r
- r_fifo_rst <= ((_net_107) ?1'b1:1'b0)|\r
- ((_reg_101) ?1'b0:1'b0);\r
+ r_vram_adrs <= 14'b00000000000000;\r
+else if ((_net_184)|(_net_183)) \r
+ r_vram_adrs <= ((_net_184) ?(r_vram_adrs)+(14'b00000000101000):14'b0)|\r
+ ((_net_183) ?14'b00000000000000:14'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_vga_ack_hld <= 1'b0;\r
-else r_vga_ack_hld <= _u_VGA_o_rdack;\r
+ r_vram_temp_adrs <= 14'b00000000000000;\r
+else if ((_net_211|_reg_174)|(_reg_175|_reg_168)) \r
+ r_vram_temp_adrs <= ((_net_211|_reg_174) ?r_vram_adrs:14'b0)|\r
+ ((_reg_175|_reg_168) ?(r_vram_temp_adrs)+(14'b00000000000001):14'b0);\r
+\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
begin\r
if (p_reset)\r
r_wait_cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_122)|(_net_120)) \r
- r_wait_cnt <= ((_net_122) ?(r_wait_cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_120) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_166)|(_net_164)) \r
+ r_wait_cnt <= ((_net_166) ?(r_wait_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_164) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_wait_val <= 26'b00000000000000000000000000;\r
-else if ((_reg_96)) \r
+else if ((_reg_105|_reg_103|_reg_100)) \r
r_wait_val <= 26'b00000000000000000111110100;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
p_wait <= 1'b0;\r
-else if ((_net_85)) \r
+else if ((_net_89)) \r
p_wait <= _proc_p_wait_set;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_94 <= 1'b0;\r
-else if ((_net_118)) \r
- _reg_94 <= _reg_95&_proc_p_wait_reset;\r
+ _reg_98 <= 1'b0;\r
+else if ((_net_162)) \r
+ _reg_98 <= _reg_99&_proc_p_wait_reset;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_95 <= 1'b0;\r
-else if ((_net_117)) \r
- _reg_95 <= _reg_96|(p_wait&(~_proc_p_wait_reset));\r
+ _reg_99 <= 1'b0;\r
+else if ((_net_161)) \r
+ _reg_99 <= _reg_100|(p_wait&(~_proc_p_wait_reset));\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_96 <= 1'b0;\r
-else if ((_net_116)) \r
- _reg_96 <= _reg_97;\r
+ _reg_100 <= 1'b0;\r
+else if ((_net_160)) \r
+ _reg_100 <= _reg_101;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_97 <= 1'b0;\r
-else if ((_net_115)) \r
- _reg_97 <= _reg_98;\r
+ _reg_101 <= 1'b0;\r
+else if ((_net_159)) \r
+ _reg_101 <= _reg_102&_proc_p_wait_reset;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_98 <= 1'b0;\r
-else if ((_net_114)) \r
- _reg_98 <= _reg_99;\r
+ _reg_102 <= 1'b0;\r
+else if ((_net_158)) \r
+ _reg_102 <= _reg_103|(p_wait&(~_proc_p_wait_reset));\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_99 <= 1'b0;\r
-else if ((_net_113)) \r
- _reg_99 <= _reg_100;\r
+ _reg_103 <= 1'b0;\r
+else if ((_net_157)) \r
+ _reg_103 <= _reg_104&_proc_p_wait_reset;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_100 <= 1'b0;\r
-else if ((_net_112)) \r
- _reg_100 <= _reg_101;\r
+ _reg_104 <= 1'b0;\r
+else if ((_net_156)) \r
+ _reg_104 <= _reg_105|(p_wait&(~_proc_p_wait_reset));\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_101 <= 1'b0;\r
-else if ((_net_111)) \r
- _reg_101 <= _reg_102;\r
+ _reg_105 <= 1'b0;\r
+else if ((_net_155)) \r
+ _reg_105 <= _reg_106;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_102 <= 1'b0;\r
-else if ((_net_110)) \r
- _reg_102 <= _reg_103;\r
+ _reg_106 <= 1'b0;\r
+else if ((_net_154)) \r
+ _reg_106 <= _reg_107;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_103 <= 1'b0;\r
-else if ((_net_109)) \r
- _reg_103 <= _reg_104;\r
+ _reg_107 <= 1'b0;\r
+else if ((_net_153)) \r
+ _reg_107 <= _reg_108;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_104 <= 1'b0;\r
-else if ((_net_108)) \r
- _reg_104 <= _reg_105|fs_init;\r
+ _reg_108 <= 1'b0;\r
+else if ((_net_152)) \r
+ _reg_108 <= _reg_109;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_105 <= 1'b0;\r
-else if ((_reg_105)) \r
- _reg_105 <= 1'b0;\r
+ _reg_109 <= 1'b0;\r
+else if ((_net_151)) \r
+ _reg_109 <= _reg_110;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_123 <= 1'b0;\r
+ _reg_110 <= 1'b0;\r
+else if ((_net_150)) \r
+ _reg_110 <= _reg_111;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_111 <= 1'b0;\r
+else if ((_net_149)) \r
+ _reg_111 <= _reg_112;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_112 <= 1'b0;\r
+else if ((_net_148)) \r
+ _reg_112 <= _reg_113;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_113 <= 1'b0;\r
+else if ((_net_147)) \r
+ _reg_113 <= _reg_113_goin|(_reg_114&(~_reg_114_goto));\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_114 <= 1'b0;\r
+else if ((_net_146)) \r
+ _reg_114 <= _reg_114_goin|_reg_115;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_115 <= 1'b0;\r
+else if ((_net_145)) \r
+ _reg_115 <= _reg_116;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_116 <= 1'b0;\r
+else if ((_net_144)) \r
+ _reg_116 <= _reg_117;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_117 <= 1'b0;\r
+else if ((_net_143)) \r
+ _reg_117 <= _reg_118;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_118 <= 1'b0;\r
+else if ((_net_142)) \r
+ _reg_118 <= _reg_119;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_119 <= 1'b0;\r
+else if ((_net_141)) \r
+ _reg_119 <= _reg_120;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_120 <= 1'b0;\r
+else if ((_net_140)) \r
+ _reg_120 <= _reg_121;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_121 <= 1'b0;\r
+else if ((_net_139)) \r
+ _reg_121 <= _reg_122;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_122 <= 1'b0;\r
else if ((_net_138)) \r
- _reg_123 <= _reg_123_goin|(_reg_124&(~_reg_124_goto));\r
+ _reg_122 <= _reg_123|fs_init;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_123 <= 1'b0;\r
+else if ((_reg_123)) \r
+ _reg_123 <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_167 <= 1'b0;\r
+else if ((_net_225)) \r
+ _reg_167 <= _reg_167_goin|(_reg_168&(~_reg_168_goto));\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_168 <= 1'b0;\r
+else if ((_net_224)) \r
+ _reg_168 <= _reg_169;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_169 <= 1'b0;\r
+else if ((_net_223)) \r
+ _reg_169 <= _reg_170;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_170 <= 1'b0;\r
+else if ((_net_222)) \r
+ _reg_170 <= _reg_171;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_171 <= 1'b0;\r
+else if ((_net_221)) \r
+ _reg_171 <= _reg_172&(~_reg_172_goto);\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_172 <= 1'b0;\r
+else if ((_net_220)) \r
+ _reg_172 <= _reg_172_goin|_reg_173;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_173 <= 1'b0;\r
+else if ((_net_219)) \r
+ _reg_173 <= _reg_174;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_174 <= 1'b0;\r
+else if ((_net_218)) \r
+ _reg_174 <= _reg_174_goin|(_reg_175&(~_reg_175_goto));\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_175 <= 1'b0;\r
+else if ((_net_217)) \r
+ _reg_175 <= _reg_176;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_176 <= 1'b0;\r
+else if ((_net_216)) \r
+ _reg_176 <= _reg_177;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_177 <= 1'b0;\r
+else if ((_net_215)) \r
+ _reg_177 <= _reg_178;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_178 <= 1'b0;\r
+else if ((_net_214)) \r
+ _reg_178 <= _reg_179&(~_reg_179_goto);\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_124 <= 1'b0;\r
-else if ((_net_137)) \r
- _reg_124 <= _reg_125&(~_reg_125_goto);\r
+ _reg_179 <= 1'b0;\r
+else if ((_net_213)) \r
+ _reg_179 <= _reg_179_goin|_reg_180;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_125 <= 1'b0;\r
-else if ((_net_136)) \r
- _reg_125 <= (_reg_125_goin|_reg_126)|fs_fifo_write;\r
+ _reg_180 <= 1'b0;\r
+else if ((_net_212)) \r
+ _reg_180 <= _reg_181|fs_vgagen_write;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_126 <= 1'b0;\r
-else if ((_reg_126)) \r
- _reg_126 <= 1'b0;\r
+ _reg_181 <= 1'b0;\r
+else if ((_reg_181)) \r
+ _reg_181 <= 1'b0;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:49 2011\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Jan 08 12:31:59 2012\r
Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r
\r
#include "vga_gen.nsl"\r
#include "vram.nsl"\r
-//#include "from_ctrl.nsh"\r
#include "push_sw.nsl"\r
\r
#define CNT1S 26'd50000000 // 1 [s]\r
reg r_LED = 0 ;\r
\r
reg r_init_cnt[13] = 0 ;\r
- reg r_vram_adrs[14] = 0 ;\r
- reg r_vram_adrs_temp[14] = 0 ;\r
reg r_vram_rddata[16] = 0 ;\r
- reg r_vram_start_adrs[13] = 0 ;\r
- reg r_fifo_write_adrs = 0 ;\r
reg r_fifo_rst = 0 ;\r
reg r_vga_ack_hld = 0 ;\r
\r
- wire w_data[8], w_exp_data[16] ;\r
+ reg r_vram_adrs[14] = 0 ;\r
+ reg r_vram_temp_adrs[14] = 0 ;\r
+ \r
+ wire w_data[8], w_exp_data[16], w_rdadrs[13] ;\r
+ wire w_wradrs[13], w_wrdata[8] ;\r
func_self fs_exp_exec(w_data):w_exp_data ;\r
func_self fs_init() ;\r
- func_self fs_fifo_write() ;\r
+ func_self fs_vram_read(w_rdadrs) ;\r
+ func_self fs_vram_write(w_wradrs, w_wrdata) ;\r
+ \r
+ func_self fs_vgagen_write() ;\r
\r
reg r_out_sel = 0 ;\r
\r
vga_gen u_VGA ;\r
push_sw u_BTN[4] ;\r
vram u_VRAM ;\r
-// from_ctrl u_FROMC ;\r
\r
{\r
/* UI */\r
\r
r_vga_ack_hld := u_VGA.o_rdack ;\r
if(~r_vga_ack_hld & u_VGA.o_rdack) {\r
- fs_fifo_write() ;\r
+ fs_vgagen_write() ;\r
}\r
}\r
- \r
+\r
func fs_init seq {\r
r_fifo_rst := 1 ;\r
;;;\r
r_fifo_rst := 0 ;\r
;;;\r
+ \r
+ for(r_init_cnt:=0; r_init_cnt<13'd8191; r_init_cnt++) {\r
+ fs_vram_write(r_init_cnt, 8'h00) ;\r
+ }\r
+\r
+ fs_vram_write(13'd0, 8'h3C) ;\r
+ fs_vram_write(13'd40, 8'h66) ;\r
+ fs_vram_write(13'd80, 8'h66) ;\r
+ fs_vram_write(13'd120, 8'h7E) ;\r
+ fs_vram_write(13'd160, 8'h66) ;\r
+ fs_vram_write(13'd200, 8'h66) ;\r
+ fs_vram_write(13'd240, 8'h66) ;\r
+ fs_vram_write(13'd280, 8'h00) ;\r
+\r
+/*\r
+ fs_vram_write(13'd39, 8'h3C) ;\r
+ fs_vram_write(13'd79, 8'h66) ;\r
+ fs_vram_write(13'd119, 8'h66) ;\r
+ fs_vram_write(13'd159, 8'h7E) ;\r
+ fs_vram_write(13'd199, 8'h66) ;\r
+ fs_vram_write(13'd239, 8'h66) ;\r
+ fs_vram_write(13'd279, 8'h66) ;\r
+ fs_vram_write(13'd319, 8'h00) ;\r
+*/\r
+\r
+// fs_vram_write(13'd7360, 8'h3C) ;\r
+// fs_vram_write(13'd7400, 8'h66) ;\r
+// fs_vram_write(13'd7440, 8'h66) ;\r
+// fs_vram_write(13'd7480, 8'h7E) ;\r
+// fs_vram_write(13'd7520, 8'h66) ;\r
+// fs_vram_write(13'd7560, 8'h66) ;\r
+// fs_vram_write(13'd7600, 8'h66) ;\r
+// fs_vram_write(13'd7640, 8'h00) ;\r
+\r
+/*\r
+ fs_vram_write(13'd7399, 8'h3C) ;\r
+ fs_vram_write(13'd7439, 8'h66) ;\r
+ fs_vram_write(13'd7479, 8'h66) ;\r
+ fs_vram_write(13'd7519, 8'h7E) ;\r
+ fs_vram_write(13'd7559, 8'h66) ;\r
+ fs_vram_write(13'd7599, 8'h66) ;\r
+ fs_vram_write(13'd7639, 8'h66) ;\r
+ fs_vram_write(13'd7679, 8'h00) ;\r
+*/\r
\r
- fs_fifo_write() ;\r
p_wait(26'd500) ;\r
- fs_fifo_write() ;\r
+ fs_vgagen_write() ;\r
+ p_wait(26'd500) ; ;\r
+ fs_vgagen_write() ;\r
+ p_wait(26'd500) ; ;\r
\r
r_reset := 0 ; \r
}\r
}\r
\r
func fs_exp_exec {\r
- w_exp_data = {\r
+ return( {\r
w_data[7], w_data[7], w_data[6], w_data[6],\r
w_data[5], w_data[5], w_data[4], w_data[4],\r
w_data[3], w_data[3], w_data[2], w_data[2],\r
w_data[1], w_data[1], w_data[0], w_data[0]\r
- } ;\r
- }\r
-\r
- func fs_fifo_write seq {\r
- for(r_init_cnt:=0; r_init_cnt<80; r_init_cnt++) {\r
- u_VGA.fi_fifo_write( 8#r_fifo_write_adrs );\r
- u_VGA.fi_fifo_write( ~(8#r_fifo_write_adrs) );\r
- }\r
- \r
- r_fifo_write_adrs := ~r_fifo_write_adrs ;\r
+ } ) ;\r
}\r
\r
-/*\r
- param w_temp_vram_adrs[14]\r
-\r
- func fs_fifo_write seq {\r
- { // Initialize\r
- r_temp_vram_adrs := w_temp_vram_adrs ;\r
- r_vram_adrs := w_temp_vram_adrs ;\r
+ func fs_vgagen_write seq {\r
+ // \88ê\97ñ\96Ú\82Ì\8f\91\82«\8d\9e\82Ý\81B\r
+ r_vram_temp_adrs := r_vram_adrs ;\r
+ for(r_init_cnt:=0; r_init_cnt<40; r_init_cnt++) {\r
+ if(r_vram_adrs < 14'd7680) {\r
+ fs_vram_read( r_vram_temp_adrs[12:0] ) ;\r
+ } else {\r
+ r_vram_rddata := 16'h0000 ; \r
+ } \r
+ if(r_vram_adrs < 14'd7680) {\r
+ r_vram_rddata := fs_exp_exec( u_VRAM.q ) ;\r
+ }\r
+ u_VGA.fi_fifo_write( r_vram_rddata[7:0] );\r
+ u_VGA.fi_fifo_write( r_vram_rddata[15:8] );\r
+ r_vram_temp_adrs++ ;\r
}\r
\r
- // 1 Line Write\r
- for(r_init_cnt:=0; r_init_cnt<80; r_init_cnt++) {\r
- {\r
- u_VGA.fi_fifo_write(r_vram_adrs) ;\r
- r_vram_adrs++ ;\r
+ // \88ê\97ñ\96Ú\82Ì\8cJ\82è\95Ô\82µ\81B\r
+ r_vram_temp_adrs := r_vram_adrs ;\r
+ for(r_init_cnt:=0; r_init_cnt<40; r_init_cnt++) {\r
+ if(r_vram_adrs < 14'd7680) {\r
+ fs_vram_read( r_vram_temp_adrs[12:0] ) ;\r
+ } else {\r
+ r_vram_rddata := 16'h0000 ; \r
+ } \r
+ if(r_vram_adrs < 14'd7680) {\r
+ r_vram_rddata := fs_exp_exec( u_VRAM.q ) ;\r
}\r
+ u_VGA.fi_fifo_write( r_vram_rddata[7:0] );\r
+ u_VGA.fi_fifo_write( r_vram_rddata[15:8] ); \r
+ r_vram_temp_adrs++ ;\r
}\r
+\r
+ if(r_vram_adrs>=14'd9559) r_vram_adrs := 0 ;\r
+ else r_vram_adrs := r_vram_adrs + 14'd40 ;\r
+ }\r
\r
- r_vram_adrs := w_temp_vram_adrs ;\r
- // 1 Line Write\r
- for(r_init_cnt:=0; r_init_cnt<80; r_init_cnt++) {\r
- {\r
- u_VGA.fi_fifo_write(r_vram_adrs) ;\r
- r_vram_adrs++ ;\r
- }\r
- }\r
+ func fs_vram_read {\r
+ u_VRAM.rdaddress = w_rdadrs ;\r
+ u_VRAM.rden = 0b1 ;\r
}\r
\r
- func fs_fifo_brank_write seq {\r
- for(r_init_cnt:=0; r_init_cnt<80; r_init_cnt++) {\r
- u_VGA.fi_fifo_write( 8'b00000000 );\r
- u_VGA.fi_fifo_write( 8'b00000000 );\r
- } \r
+ func fs_vram_write {\r
+ u_VRAM.wraddress = w_wradrs ;\r
+ u_VRAM.wren = 0b1 ;\r
+ u_VRAM.data = w_wrdata ;\r
+ \r
}\r
-*/\r
}
\ No newline at end of file
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