+++ /dev/null
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Oct 15 11:16:52 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
-*/\r
-\r
-module SDRAMC ( p_reset , m_clock , o_ADRS , o_BA , io_DQ , o_RAS , o_CAS , o_WE , io_DQM , o_tLED );\r
- input p_reset;\r
- input m_clock;\r
- output [11:0] o_ADRS;\r
- output [1:0] o_BA;\r
-inout [15:0] io_DQ;\r
- output o_RAS;\r
- output o_CAS;\r
- output o_WE;\r
-inout [1:0] io_DQM;\r
- output o_tLED;\r
- wire [13:0] w_adrs;\r
- wire [15:0] w_wdata;\r
- wire [15:0] w_rdata;\r
- reg [26:0] r_tLED_cnt;\r
- reg r_tLED;\r
- wire fs_refresh;\r
- wire fs_SingleWrite;\r
- wire fs_SingleRead;\r
- wire fs_BurstWrite;\r
- wire fs_BurstRead;\r
- wire _net_0;\r
- wire _net_1;\r
-\r
- assign fs_refresh = 1'b0;\r
- assign fs_SingleWrite = 1'b0;\r
- assign fs_SingleRead = 1'b0;\r
- assign fs_BurstWrite = 1'b0;\r
- assign fs_BurstRead = 1'b0;\r
- assign _net_0 = (r_tLED_cnt)==(27'b101111101011110000100000000);\r
- assign _net_1 = ~_net_0;\r
- assign o_tLED = r_tLED;\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_tLED_cnt <= 27'b000000000000000000000000000;\r
-else if ((_net_1)|(_net_0)) \r
- r_tLED_cnt <= ((_net_1) ?(r_tLED_cnt)+(27'b000000000000000000000000001):27'b0)|\r
- ((_net_0) ?27'b000000000000000000000000000:27'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_tLED <= 1'b0;\r
-else if ((_net_0)) \r
- r_tLED <= ~r_tLED;\r
-end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Oct 15 11:16:53 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
-\r
-module btn_ctrl ( p_reset , m_clock , i_sw , fo_sw_enb );\r
- input p_reset, m_clock;\r
- input i_sw;\r
- output fo_sw_enb;\r
- reg [18:0] r_cnt;\r
- reg r_rise_flag;\r
- reg r_sw_hld;\r
- reg r_finish_flag;\r
- wire _net_2;\r
- wire _net_3;\r
- wire _net_4;\r
- wire _net_5;\r
- wire _net_6;\r
- wire _net_7;\r
- wire _net_8;\r
- wire _net_9;\r
- wire _net_10;\r
- wire _net_11;\r
- wire _net_12;\r
-\r
- assign _net_2 = i_sw&(~r_sw_hld);\r
- assign _net_3 = ~i_sw;\r
- assign _net_4 = ~_net_2;\r
- assign _net_5 = (~_net_2)&_net_3;\r
- assign _net_6 = (~_net_2)&_net_3;\r
- assign _net_7 = (r_rise_flag)==(1'b1);\r
- assign _net_8 = ((r_cnt)==(19'b1111010000100100000))&((r_finish_flag)==(1'b0));\r
- assign _net_9 = _net_7&_net_8;\r
- assign _net_10 = _net_7&_net_8;\r
- assign _net_11 = _net_7&(~_net_8);\r
- assign _net_12 = ~_net_7;\r
- assign fo_sw_enb = _net_10;\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_cnt <= 19'b0000000000000000000;\r
-else if ((_net_12)|(_net_11)) \r
- r_cnt <= ((_net_12) ?26'b00000000000000000000000000:19'b0)|\r
- ((_net_11) ?(r_cnt)+(19'b0000000000000000001):19'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_rise_flag <= 1'b0;\r
-else if ((_net_5)|(_net_2)) \r
- r_rise_flag <= ((_net_5) ?1'b0:1'b0)|\r
- ((_net_2) ?1'b1:1'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_sw_hld <= 1'b0;\r
-else r_sw_hld <= i_sw;\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_finish_flag <= 1'b0;\r
-else if ((_net_9)|(_net_6)) \r
- r_finish_flag <= ((_net_9) ?1'b1:1'b0)|\r
- ((_net_6) ?1'b0:1'b0);\r
-\r
-end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Oct 15 11:16:55 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
-\r
-module SDRAM_top ( p_reset , m_clock , o_ADRS , o_BA , io_DQ , o_CS , o_RAS , o_CAS , o_WE , io_DQM , o_CLK100 , o_tLED , o_tLED2 , o_locked );\r
- input p_reset, m_clock;\r
- output [11:0] o_ADRS;\r
- output [1:0] o_BA;\r
-inout [15:0] io_DQ;\r
- output o_CS;\r
- output o_RAS;\r
- output o_CAS;\r
- output o_WE;\r
-inout [1:0] io_DQM;\r
- output o_CLK100;\r
- output o_tLED;\r
- output o_tLED2;\r
- output o_locked;\r
- reg [25:0] cnt;\r
- reg tLED2;\r
- wire _u_SDRAMC_p_reset;\r
- wire _u_SDRAMC_m_clock;\r
- wire [11:0] _u_SDRAMC_o_ADRS;\r
- wire [1:0] _u_SDRAMC_o_BA;\r
- wire [15:0] _u_SDRAMC_io_DQ;\r
- wire _u_SDRAMC_o_RAS;\r
- wire _u_SDRAMC_o_CAS;\r
- wire _u_SDRAMC_o_WE;\r
- wire [1:0] _u_SDRAMC_io_DQM;\r
- wire _u_SDRAMC_o_tLED;\r
- wire _u_BTN_i_sw;\r
- wire _u_BTN_fo_sw_enb;\r
- wire _u_BTN_p_reset;\r
- wire _u_BTN_m_clock;\r
- wire _u_PLL_areset;\r
- wire _u_PLL_inclk0;\r
- wire _u_PLL_c0;\r
- wire _u_PLL_locked;\r
- wire _net_13;\r
- wire _net_14;\r
-PLLU u_PLL (.locked(_u_PLL_locked), .c0(_u_PLL_c0), .inclk0(_u_PLL_inclk0), .areset(_u_PLL_areset));\r
-btn_ctrl u_BTN (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_fo_sw_enb), .i_sw(_u_BTN_i_sw));\r
-SDRAMC u_SDRAMC (.o_tLED(_u_SDRAMC_o_tLED), .io_DQM(_u_SDRAMC_io_DQM), .o_WE(_u_SDRAMC_o_WE), .o_CAS(_u_SDRAMC_o_CAS), .o_RAS(_u_SDRAMC_o_RAS), .io_DQ(_u_SDRAMC_io_DQ), .o_BA(_u_SDRAMC_o_BA), .o_ADRS(_u_SDRAMC_o_ADRS), .m_clock(_u_SDRAMC_m_clock), .p_reset(_u_SDRAMC_p_reset));\r
-\r
- assign _u_SDRAMC_p_reset = 1'b0;\r
- assign _u_SDRAMC_m_clock = _u_PLL_c0;\r
- assign _u_PLL_areset = 1'b0;\r
- assign _u_PLL_inclk0 = m_clock;\r
- assign _net_13 = (cnt)==(50'b00000000000000000000000010111110101111000010000000);\r
- assign _net_14 = ~_net_13;\r
- assign o_tLED = _u_SDRAMC_o_tLED;\r
- assign o_tLED2 = tLED2;\r
- assign o_locked = _u_PLL_locked;\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_14)|(_net_13)) \r
- cnt <= ((_net_14) ?(cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_13) ?26'b00000000000000000000000000:26'b0);\r
-\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- tLED2 <= 1'b0;\r
-else if ((_net_13)) \r
- tLED2 <= ~tLED2;\r
-end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Oct 15 11:16:56 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
+++ /dev/null
-`timescale 1ns / 1ps
-
-//synthesis translate_off
-module tb ;
- parameter tCYC=2 ;
- parameter tPD=(tCYC/10) ;
-
- integer i ;
-
- reg p_reset, m_clock ;
- reg [13:0] iRadrs ;
- wire [15:0] oRdata ;
- reg fiRd_req ;
- wire foRd_ack ;
-
- reg [7:0] iWdata ;
- reg [13:0] iWadrs ;
- reg fiWr_req ;
-
- exp_ctrl uut(
- .p_reset(p_reset),
- .m_clock(m_clock),
- .iRadrs(iRadrs),
- .oRdata(oRdata),
- .fiRd_req(fiRd_req),
- .foRd_ack(foRd_ack),
- .iWdata(iWdata),
- .iWadrs(iWadrs),
- .fiWr_req(fiWr_req)
- ) ;
-
- initial forever #(tCYC/2) m_clock = ~m_clock ;
-
- initial begin
- #(tPD)
- p_reset = 1 ;
- m_clock = 0 ;
- // Initialize
- iRadrs <= 14'd0 ;
- fiRd_req <= 0 ;
- iWdata <= 8'd0 ;
- iWadrs <= 14'd0 ;
- fiWr_req <= 0 ;
- #(tCYC)
- p_reset = 0 ;
- #(tCYC*5) ;
- for(i=0; i<1000; i=i+1) begin
- fiWr_req <= 1 ;
- iWdata <= i[7:0] ;
- iWadrs <= i[13:0] ;
- #(tCYC) ;
- fiWr_req <= 0 ;
- #(tCYC) ;
- end
- #(tCYC*5) ;
- for(i=0; i<100; i=i+1) begin
- fiRd_req <= 1 ;
- iRadrs <= i[13:0] ;
- #(tCYC) ;
- fiRd_req <= 0 ;
- #(tCYC*2) ;
- end
- end
-
-endmodule
-
-//synthesis translate_on
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 15:57:59 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:48:34 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
*/\r
\r
module vga_gen ( i_clk50 , i_fifo_rst , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_dummy_rgb , o_vcnt , i_wrdata , fi_fifo_write , o_rdack , o_led );\r
reg r_led;\r
reg r_init_flg;\r
reg [2:0] r_trg;\r
+ reg [25:0] r_cnt1;\r
+ reg [25:0] r_cnt2;\r
+ reg [25:0] r_cnt3;\r
+ reg r_buff1;\r
wire _u_FIFO_i_rst;\r
wire _u_FIFO_i_clk50;\r
wire _u_FIFO_i_clk25;\r
wire _net_51;\r
wire _net_52;\r
wire _net_53;\r
- reg _reg_54;\r
- reg _reg_55;\r
- reg _reg_56;\r
- reg _reg_57;\r
+ wire _net_54;\r
+ wire _net_55;\r
+ wire _net_56;\r
+ wire _net_57;\r
reg _reg_58;\r
- wire _net_59;\r
- wire _net_60;\r
- wire _net_61;\r
- wire _net_62;\r
+ reg _reg_59;\r
+ reg _reg_60;\r
+ reg _reg_61;\r
+ reg _reg_62;\r
wire _net_63;\r
- reg _reg_64;\r
- reg _reg_65;\r
+ wire _net_64;\r
+ wire _net_65;\r
wire _net_66;\r
+ wire _net_67;\r
+ reg _reg_68;\r
+ reg _reg_69;\r
+ wire _net_70;\r
vga_ram u_FIFO (.o_rdack(_u_FIFO_o_rdack), .o_rddata(_u_FIFO_o_rddata), .i_re(_u_FIFO_i_re), .i_wrdata(_u_FIFO_i_wrdata), .i_we(_u_FIFO_i_we), .i_clk25(_u_FIFO_i_clk25), .i_clk50(_u_FIFO_i_clk50), .i_rst(_u_FIFO_i_rst));\r
\r
- assign fs_fifo_read = _net_59|_reg_56|_net_15;\r
+ assign fs_fifo_read = _net_63|_reg_60|_net_15;\r
assign w_rddata = _u_FIFO_o_rddata;\r
- assign fs_fifo_ack = _reg_64;\r
+ assign fs_fifo_ack = _reg_68;\r
assign fs_initialize = _net_0;\r
assign _u_FIFO_i_rst = i_fifo_rst;\r
assign _u_FIFO_i_clk50 = i_clk50;\r
assign _net_0 = (r_trg)==(3'b011);\r
assign _net_1 = (r_cnt)==(26'b01011111010111100001000000);\r
assign _net_2 = ~_net_1;\r
- assign _net_3 = (r_hcnt) < (10'b1100100000);\r
+ assign _net_3 = (r_hcnt) < (10'b1100011111);\r
assign _net_4 = r_init_flg&_net_3;\r
assign _net_5 = r_init_flg&(~_net_3);\r
- assign _net_6 = (r_vcnt) < (10'b1000001001);\r
+ assign _net_6 = (r_vcnt) < (10'b1000000111);\r
assign _net_7 = r_init_flg&(~_net_3);\r
assign _net_8 = (r_init_flg&(~_net_3))&_net_6;\r
assign _net_9 = (r_init_flg&(~_net_3))&(~_net_6);\r
- assign _net_10 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
+ assign _net_10 = (((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000)))&r_vsync;\r
assign _net_11 = _net_10&r_init_flg;\r
assign _net_12 = (r_bit_cnt)==(3'b111);\r
assign _net_13 = _net_10&r_init_flg;\r
assign _net_34 = ~(r_outclr[6]);\r
assign _net_35 = _net_10&_net_34;\r
assign _net_36 = _net_10&(~_net_34);\r
- assign _net_37 = (r_hcnt)==(10'b1011110000);\r
+ assign _net_37 = (r_hcnt)==(10'b1011101111);\r
assign _net_38 = ~_net_10;\r
assign _net_39 = (~_net_10)&_net_37;\r
- assign _net_40 = (r_hcnt)==(10'b1010010000);\r
+ assign _net_40 = (r_hcnt)==(10'b1010001111);\r
assign _net_41 = ~_net_10;\r
assign _net_42 = (~_net_10)&_net_40;\r
assign _net_43 = (r_hcnt)==(10'b1010000000);\r
assign _net_48 = (~_net_10)&_net_43;\r
assign _net_49 = (~_net_10)&_net_43;\r
assign _net_50 = (~_net_10)&_net_43;\r
- assign _net_51 = (r_vcnt)==(10'b0111101100);\r
- assign _net_52 = (r_vcnt)==(10'b0111101010);\r
- assign _net_53 = (r_vcnt)==(10'b0111100000);\r
- assign _net_59 = fs_initialize|_reg_58;\r
- assign _net_60 = fs_initialize|_reg_57|_reg_58;\r
- assign _net_61 = fs_initialize|_reg_56|_reg_57;\r
- assign _net_62 = fs_initialize|_reg_55|_reg_56;\r
- assign _net_63 = fs_initialize|_reg_54|_reg_55;\r
- assign _net_66 = fs_fifo_read|_reg_64|_reg_65;\r
+ assign _net_51 = ((~_net_10)&fs_fifo_ack)&r_reg_cnt;\r
+ assign _net_52 = ~r_reg_cnt;\r
+ assign _net_53 = (~_net_10)&fs_fifo_ack;\r
+ assign _net_54 = ((~_net_10)&fs_fifo_ack)&_net_52;\r
+ assign _net_55 = (r_vcnt)==(10'b0111101011);\r
+ assign _net_56 = (r_vcnt)==(10'b0111101001);\r
+ assign _net_57 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_63 = fs_initialize|_reg_62;\r
+ assign _net_64 = fs_initialize|_reg_61|_reg_62;\r
+ assign _net_65 = fs_initialize|_reg_60|_reg_61;\r
+ assign _net_66 = fs_initialize|_reg_59|_reg_60;\r
+ assign _net_67 = fs_initialize|_reg_58|_reg_59;\r
+ assign _net_70 = fs_fifo_read|_reg_68|_reg_69;\r
assign o_vsync = r_vsync;\r
assign o_hsync = r_hsync;\r
assign o_vga_r = ((_net_45|_net_33)?4'b0000:4'b0)|\r
begin\r
if (p_reset)\r
r_data1 <= 8'b00000000;\r
-else if ((_reg_57)|(_net_16)) \r
- r_data1 <= ((_reg_57) ?_u_FIFO_o_rddata:8'b0)|\r
- ((_net_16) ?w_rddata:8'b0);\r
+else if ((_reg_61)|(_net_51|_net_16)) \r
+ r_data1 <= ((_reg_61) ?_u_FIFO_o_rddata:8'b0)|\r
+ ((_net_51|_net_16) ?w_rddata:8'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_data2 <= 8'b00000000;\r
-else if ((_reg_55)|(_net_19)) \r
- r_data2 <= ((_reg_55) ?_u_FIFO_o_rddata:8'b0)|\r
- ((_net_19) ?w_rddata:8'b0);\r
+else if ((_reg_59)|(_net_54|_net_19)) \r
+ r_data2 <= ((_reg_59) ?_u_FIFO_o_rddata:8'b0)|\r
+ ((_net_54|_net_19) ?w_rddata:8'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_vsync <= 1'b0;\r
-else if ((_net_52)|(_net_51)) \r
- r_vsync <= ((_net_52) ?1'b0:1'b0)|\r
- ((_net_51) ?1'b1:1'b0);\r
+else if ((_net_56)|(_net_55)) \r
+ r_vsync <= ((_net_56) ?1'b0:1'b0)|\r
+ ((_net_55) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_init_flg <= 1'b0;\r
-else if ((_reg_54)) \r
+else if ((_reg_58)) \r
r_init_flg <= 1'b1;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
r_trg <= 3'b000;\r
else r_trg <= {r_trg[1:0],1'b1};\r
end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt1 <= 26'b00000000000000000000000000;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt2 <= 26'b00000000000000000000000000;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt3 <= 26'b00000000000000000000000000;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_buff1 <= 1'b0;\r
+end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_54 <= 1'b0;\r
-else if ((_net_63)) \r
- _reg_54 <= _reg_55;\r
+ _reg_58 <= 1'b0;\r
+else if ((_net_67)) \r
+ _reg_58 <= _reg_59;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_55 <= 1'b0;\r
-else if ((_net_62)) \r
- _reg_55 <= _reg_56;\r
+ _reg_59 <= 1'b0;\r
+else if ((_net_66)) \r
+ _reg_59 <= _reg_60;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_56 <= 1'b0;\r
-else if ((_net_61)) \r
- _reg_56 <= _reg_57;\r
+ _reg_60 <= 1'b0;\r
+else if ((_net_65)) \r
+ _reg_60 <= _reg_61;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_57 <= 1'b0;\r
-else if ((_net_60)) \r
- _reg_57 <= _reg_58|fs_initialize;\r
+ _reg_61 <= 1'b0;\r
+else if ((_net_64)) \r
+ _reg_61 <= _reg_62|fs_initialize;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_58 <= 1'b0;\r
-else if ((_reg_58)) \r
- _reg_58 <= 1'b0;\r
+ _reg_62 <= 1'b0;\r
+else if ((_reg_62)) \r
+ _reg_62 <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_64 <= 1'b0;\r
-else if ((_net_66)) \r
- _reg_64 <= _reg_65|fs_fifo_read;\r
+ _reg_68 <= 1'b0;\r
+else if ((_net_70)) \r
+ _reg_68 <= _reg_69|fs_fifo_read;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_65 <= 1'b0;\r
-else if ((_reg_65)) \r
- _reg_65 <= 1'b0;\r
+ _reg_69 <= 1'b0;\r
+else if ((_reg_69)) \r
+ _reg_69 <= 1'b0;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 15:58:02 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:48:39 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
*/\r
+++ /dev/null
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Aug 06 22:05:03 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
-*/\r
-\r
-module vga_generate ( i_50clk , i_wdata1 , i_wdata2 , fi_vgaram_write1 , fi_vgaram_write2 , fi_fifo1_rst , fi_fifo2_rst , p_reset , m_clock , o_v_sync , o_h_sync , o_vga_red , o_vga_green , o_vga_blue , o_h_cnt , o_scanline );\r
- input i_50clk;\r
- input [31:0] i_wdata1;\r
- input [31:0] i_wdata2;\r
- input fi_vgaram_write1;\r
- input fi_vgaram_write2;\r
- input fi_fifo1_rst;\r
- input fi_fifo2_rst;\r
- input p_reset;\r
- input m_clock;\r
- output o_v_sync;\r
- output o_h_sync;\r
- output [3:0] o_vga_red;\r
- output [3:0] o_vga_green;\r
- output [3:0] o_vga_blue;\r
- output [9:0] o_h_cnt;\r
- output [9:0] o_scanline;\r
- wire fs_disp_data;\r
- reg r_v_sync;\r
- reg r_h_sync;\r
- reg r_vdata_flg;\r
- reg r_hdata_flg;\r
- reg [9:0] r_h_cnt;\r
- reg [18:0] r_v_cnt;\r
- reg [4:0] r_bit32_cnt;\r
- reg r_flg;\r
- reg [31:0] r1;\r
- reg [31:0] r2;\r
- reg r_data_select_flag;\r
- reg [9:0] r_scanline_cnt;\r
- wire [3:0] w_red;\r
- wire [3:0] w_green;\r
- wire [3:0] w_blue;\r
- wire w_disp_data;\r
- reg r_cnt_flg;\r
- reg r_hld_h_sync;\r
- wire vgaram_read1;\r
- wire vgaram_read2;\r
- wire _u_VGARAM_p_reset;\r
- wire _u_VGARAM_m_clock;\r
- wire _u_VGARAM_i_we1;\r
- wire [7:0] _u_VGARAM_i_wdata1;\r
- wire _u_VGARAM_i_we2;\r
- wire [7:0] _u_VGARAM_i_wdata2;\r
- wire [7:0] _u_VGARAM_o_rddata1;\r
- wire [7:0] _u_VGARAM_o_rddata2;\r
- wire _u_VGARAM_i_clock;\r
- wire _u_VGARAM_i_re1;\r
- wire _u_VGARAM_i_re2;\r
- wire _u_VGARAM_i_fifo1_rst;\r
- wire _u_VGARAM_i_fifo2_rst;\r
- wire _u_VGARAM_o_rdack1;\r
- wire _u_VGARAM_o_rdack2;\r
- wire _net_0;\r
- wire _net_1;\r
- wire _net_2;\r
- wire _net_3;\r
- wire _net_4;\r
- wire _net_5;\r
- wire _net_6;\r
- wire _net_7;\r
- wire _net_8;\r
- wire _net_9;\r
- wire _net_10;\r
- wire _net_11;\r
- wire _net_12;\r
- wire _net_13;\r
- wire _net_14;\r
- wire _net_15;\r
- wire _net_16;\r
- wire _net_17;\r
- wire _net_18;\r
- wire _net_19;\r
- wire _net_20;\r
- wire _net_21;\r
- wire _net_22;\r
- wire _net_23;\r
- wire _net_24;\r
- wire _net_25;\r
- wire _net_26;\r
- wire _net_27;\r
- wire _net_28;\r
- wire _net_29;\r
- wire _net_30;\r
- wire _net_31;\r
- wire _net_32;\r
- wire _net_33;\r
- wire _net_34;\r
- wire _net_35;\r
- wire _net_36;\r
- wire _net_37;\r
- wire _net_38;\r
- wire _net_39;\r
- wire _net_40;\r
- wire _net_41;\r
- wire _net_42;\r
- wire _net_43;\r
- wire _net_44;\r
- wire _net_45;\r
- wire _net_46;\r
- wire _net_47;\r
- wire _net_48;\r
- wire _net_49;\r
- wire _net_50;\r
- wire _net_51;\r
- wire _net_52;\r
- wire _net_53;\r
- wire _net_54;\r
- wire _net_55;\r
- wire _net_56;\r
- wire _net_57;\r
- wire _net_58;\r
- wire _net_59;\r
- wire _net_60;\r
- wire _net_61;\r
- wire _net_62;\r
- wire _net_63;\r
- wire _net_64;\r
- wire _net_65;\r
- wire _net_66;\r
- wire _net_67;\r
- wire _net_68;\r
- wire _net_69;\r
- wire _net_70;\r
- wire _net_71;\r
- wire _net_72;\r
- wire _net_73;\r
- wire _net_74;\r
- wire _net_75;\r
- wire _net_76;\r
- wire _net_77;\r
- wire _net_78;\r
- wire _net_79;\r
- wire _net_80;\r
- wire _net_81;\r
- wire _net_82;\r
- wire _net_83;\r
- wire _net_84;\r
- wire _net_85;\r
- wire _net_86;\r
- wire _net_87;\r
- wire _net_88;\r
- wire _net_89;\r
- wire _net_90;\r
- wire _net_91;\r
- wire _net_92;\r
- wire _net_93;\r
- wire _net_94;\r
- wire _net_95;\r
- wire _net_96;\r
- wire _net_97;\r
- wire _net_98;\r
- wire _net_99;\r
- wire _net_100;\r
- wire _net_101;\r
- wire _net_102;\r
- wire _net_103;\r
- wire _net_104;\r
- wire _net_105;\r
- wire _net_106;\r
- wire _net_107;\r
- wire _net_108;\r
- wire _net_109;\r
- wire _net_110;\r
- wire _net_111;\r
- wire _net_112;\r
- wire _net_113;\r
- wire _net_114;\r
- wire _net_115;\r
- wire _net_116;\r
- wire _net_117;\r
- wire _net_118;\r
- wire _net_119;\r
- wire _net_120;\r
- wire _net_121;\r
- wire _net_122;\r
- wire _net_123;\r
- wire _net_124;\r
- wire _net_125;\r
- wire _net_126;\r
- wire _net_127;\r
- wire _net_128;\r
- wire _net_129;\r
- wire _net_130;\r
- wire _net_131;\r
- wire _net_132;\r
- wire _net_133;\r
- wire _net_134;\r
- wire _net_135;\r
- wire _net_136;\r
- wire _net_137;\r
- wire _net_138;\r
- wire _net_139;\r
- wire _net_140;\r
- wire _net_141;\r
- wire _net_142;\r
- wire _net_143;\r
- wire _net_144;\r
- wire _net_145;\r
- wire _net_146;\r
- wire _net_147;\r
- wire _net_148;\r
- wire _net_149;\r
- wire _net_150;\r
- wire _net_151;\r
- wire _net_152;\r
- wire _net_153;\r
- wire _net_154;\r
- wire _net_155;\r
- wire _net_156;\r
- wire _net_157;\r
- wire _net_158;\r
- wire _net_159;\r
- wire _net_160;\r
- wire _net_161;\r
- wire _net_162;\r
- wire _net_163;\r
- wire _net_164;\r
- wire _net_165;\r
- wire _net_166;\r
- wire _net_167;\r
- wire _net_168;\r
- wire _net_169;\r
- wire _net_170;\r
- wire _net_171;\r
- wire _net_172;\r
- wire _net_173;\r
- wire _net_174;\r
- wire _net_175;\r
- wire _net_176;\r
- wire _net_177;\r
- wire _net_178;\r
- wire _net_179;\r
- wire _net_180;\r
- wire _net_181;\r
- wire _net_182;\r
- wire _net_183;\r
- wire _net_184;\r
- wire _net_185;\r
- wire _net_186;\r
- wire _net_187;\r
- wire _net_188;\r
- wire _net_189;\r
- wire _net_190;\r
- wire _net_191;\r
- wire _net_192;\r
- wire _net_193;\r
- wire _net_194;\r
- wire _net_195;\r
- wire _net_196;\r
- wire _net_197;\r
- wire _net_198;\r
- wire _net_199;\r
- wire _net_200;\r
- wire _net_201;\r
- wire _net_202;\r
- wire _net_203;\r
- wire _net_204;\r
- wire _net_205;\r
- wire _net_206;\r
- wire _net_207;\r
- wire _net_208;\r
- wire _net_209;\r
- wire _net_210;\r
- wire _net_211;\r
- wire _net_212;\r
- wire _net_213;\r
- wire _net_214;\r
- wire _net_215;\r
- wire _net_216;\r
- wire _net_217;\r
- wire _net_218;\r
- wire _net_219;\r
- wire _net_220;\r
- wire _net_221;\r
- wire _net_222;\r
- wire _net_223;\r
- wire _net_224;\r
- wire _net_225;\r
- wire _net_226;\r
- wire _net_227;\r
- wire _net_228;\r
- wire _net_229;\r
- wire _net_230;\r
- wire _net_231;\r
- wire _net_232;\r
- wire _net_233;\r
- wire _net_234;\r
- wire _net_235;\r
- wire _net_236;\r
- wire _net_237;\r
- wire _net_238;\r
-vga_ram u_VGARAM (.o_rdack2(_u_VGARAM_o_rdack2), .o_rdack1(_u_VGARAM_o_rdack1), .i_fifo2_rst(_u_VGARAM_i_fifo2_rst), .i_fifo1_rst(_u_VGARAM_i_fifo1_rst), .i_re2(_u_VGARAM_i_re2), .i_re1(_u_VGARAM_i_re1), .i_clock(_u_VGARAM_i_clock), .o_rddata2(_u_VGARAM_o_rddata2), .o_rddata1(_u_VGARAM_o_rddata1), .i_wdata2(_u_VGARAM_i_wdata2), .i_we2(_u_VGARAM_i_we2), .i_wdata1(_u_VGARAM_i_wdata1), .i_we1(_u_VGARAM_i_we1), .m_clock(_u_VGARAM_m_clock), .p_reset(_u_VGARAM_p_reset));\r
-\r
- assign fs_disp_data = _net_17;\r
- assign w_red = ((_net_38)?4'b0000:4'b0)|\r
- ((_net_35|_net_32)?4'b1111:4'b0);\r
- assign w_green = ((_net_37)?4'b1111:4'b0)|\r
- ((_net_40|_net_34)?4'b0000:4'b0);\r
- assign w_blue = ((_net_36)?4'b1111:4'b0)|\r
- ((_net_39|_net_33)?4'b0000:4'b0);\r
- assign w_disp_data = ((_net_238)?r2[31]:1'b0)|\r
- ((_net_235)?r2[30]:1'b0)|\r
- ((_net_232)?r2[29]:1'b0)|\r
- ((_net_229)?r2[28]:1'b0)|\r
- ((_net_226)?r2[27]:1'b0)|\r
- ((_net_223)?r2[26]:1'b0)|\r
- ((_net_220)?r2[25]:1'b0)|\r
- ((_net_217)?r2[24]:1'b0)|\r
- ((_net_214)?r2[23]:1'b0)|\r
- ((_net_211)?r2[22]:1'b0)|\r
- ((_net_208)?r2[21]:1'b0)|\r
- ((_net_205)?r2[20]:1'b0)|\r
- ((_net_202)?r2[19]:1'b0)|\r
- ((_net_199)?r2[18]:1'b0)|\r
- ((_net_196)?r2[17]:1'b0)|\r
- ((_net_193)?r2[16]:1'b0)|\r
- ((_net_190)?r2[15]:1'b0)|\r
- ((_net_187)?r2[14]:1'b0)|\r
- ((_net_184)?r2[13]:1'b0)|\r
- ((_net_181)?r2[12]:1'b0)|\r
- ((_net_178)?r2[11]:1'b0)|\r
- ((_net_175)?r2[10]:1'b0)|\r
- ((_net_172)?r2[9]:1'b0)|\r
- ((_net_169)?r2[8]:1'b0)|\r
- ((_net_166)?r2[7]:1'b0)|\r
- ((_net_163)?r2[6]:1'b0)|\r
- ((_net_160)?r2[5]:1'b0)|\r
- ((_net_157)?r2[4]:1'b0)|\r
- ((_net_154)?r2[3]:1'b0)|\r
- ((_net_151)?r2[2]:1'b0)|\r
- ((_net_148)?r2[1]:1'b0)|\r
- ((_net_144)?r2[0]:1'b0)|\r
- ((_net_141)?r1[31]:1'b0)|\r
- ((_net_138)?r1[30]:1'b0)|\r
- ((_net_135)?r1[29]:1'b0)|\r
- ((_net_132)?r1[28]:1'b0)|\r
- ((_net_129)?r1[27]:1'b0)|\r
- ((_net_126)?r1[26]:1'b0)|\r
- ((_net_123)?r1[25]:1'b0)|\r
- ((_net_120)?r1[24]:1'b0)|\r
- ((_net_117)?r1[23]:1'b0)|\r
- ((_net_114)?r1[22]:1'b0)|\r
- ((_net_111)?r1[21]:1'b0)|\r
- ((_net_108)?r1[20]:1'b0)|\r
- ((_net_105)?r1[19]:1'b0)|\r
- ((_net_102)?r1[18]:1'b0)|\r
- ((_net_99)?r1[17]:1'b0)|\r
- ((_net_96)?r1[16]:1'b0)|\r
- ((_net_93)?r1[15]:1'b0)|\r
- ((_net_90)?r1[14]:1'b0)|\r
- ((_net_87)?r1[13]:1'b0)|\r
- ((_net_84)?r1[12]:1'b0)|\r
- ((_net_81)?r1[11]:1'b0)|\r
- ((_net_78)?r1[10]:1'b0)|\r
- ((_net_75)?r1[9]:1'b0)|\r
- ((_net_72)?r1[8]:1'b0)|\r
- ((_net_69)?r1[7]:1'b0)|\r
- ((_net_66)?r1[6]:1'b0)|\r
- ((_net_63)?r1[5]:1'b0)|\r
- ((_net_60)?r1[4]:1'b0)|\r
- ((_net_57)?r1[3]:1'b0)|\r
- ((_net_54)?r1[2]:1'b0)|\r
- ((_net_51)?r1[1]:1'b0)|\r
- ((_net_47)?r1[0]:1'b0);\r
- assign vgaram_read1 = _net_22;\r
- assign vgaram_read2 = _net_23;\r
- assign _u_VGARAM_p_reset = p_reset;\r
- assign _u_VGARAM_m_clock = m_clock;\r
- assign _u_VGARAM_i_we1 = fi_vgaram_write1;\r
- assign _u_VGARAM_i_wdata1 = i_wdata1;\r
- assign _u_VGARAM_i_we2 = fi_vgaram_write2;\r
- assign _u_VGARAM_i_wdata2 = i_wdata2;\r
- assign _u_VGARAM_i_clock = i_50clk;\r
- assign _u_VGARAM_i_re1 = ((_net_28)?1'b0:1'b0)|\r
- ((vgaram_read1)?1'b1:1'b0);\r
- assign _u_VGARAM_i_re2 = ((_net_29)?1'b0:1'b0)|\r
- ((vgaram_read2)?1'b1:1'b0);\r
- assign _u_VGARAM_i_fifo1_rst = fi_fifo1_rst;\r
- assign _u_VGARAM_i_fifo2_rst = fi_fifo2_rst;\r
- assign _net_0 = r_h_sync&(~r_hld_h_sync);\r
- assign _net_1 = ~r_cnt_flg;\r
- assign _net_2 = r_v_sync&_net_0;\r
- assign _net_3 = (r_v_sync&_net_0)&_net_1;\r
- assign _net_4 = (r_v_sync&_net_0)&(~_net_1);\r
- assign _net_5 = ~r_v_sync;\r
- assign _net_6 = ~r_v_sync;\r
- assign _net_7 = (r_h_cnt)==(10'b1100100000);\r
- assign _net_8 = (r_h_cnt)==(10'b1100001110);\r
- assign _net_9 = (r_h_cnt)==(10'b0010001110);\r
- assign _net_10 = (r_h_cnt)==(10'b0001100000);\r
- assign _net_11 = (((~_net_7)&(~_net_8))&(~_net_9))&(~_net_10);\r
- assign _net_12 = (r_v_cnt)==(19'b1100101110000011111);\r
- assign _net_13 = (r_v_cnt)==(19'b1100011110011011111);\r
- assign _net_14 = (r_v_cnt)==(19'b0000110000011011111);\r
- assign _net_15 = (r_v_cnt)==(19'b0000000011000111111);\r
- assign _net_16 = (((~_net_12)&(~_net_13))&(~_net_14))&(~_net_15);\r
- assign _net_17 = r_hdata_flg&r_vdata_flg;\r
- assign _net_18 = (((r_h_cnt) >= ((10'b0010001110)+(10'b1001100001)))&((r_h_cnt) <= (((10'b1100001110)+(10'b1001100001))+(10'b1111111111))))&((r_v_cnt) >= ((19'b0000110000011011111)+(19'b1111111111111100001)))&((r_v_cnt) <= (((19'b1100011110011011111)+(19'b1111111111111100001))+(19'b1111111111111111111)));\r
- assign _net_19 = (r_bit32_cnt)==(5'b00000);\r
- assign _net_20 = (r_scanline_cnt[0])==(1'b0);\r
- assign _net_21 = _net_18&_net_19;\r
- assign _net_22 = (_net_18&_net_19)&_net_20;\r
- assign _net_23 = (_net_18&_net_19)&(~_net_20);\r
- assign _net_24 = (r_bit32_cnt)==(5'b11111);\r
- assign _net_25 = _net_18&_net_24;\r
- assign _net_26 = _net_18&(~_net_24);\r
- assign _net_27 = ~_net_18;\r
- assign _net_28 = ~vgaram_read1;\r
- assign _net_29 = ~vgaram_read2;\r
- assign _net_30 = r_hdata_flg&r_vdata_flg;\r
- assign _net_31 = ~w_disp_data;\r
- assign _net_32 = _net_30&_net_31;\r
- assign _net_33 = _net_30&_net_31;\r
- assign _net_34 = _net_30&_net_31;\r
- assign _net_35 = _net_30&w_disp_data;\r
- assign _net_36 = _net_30&w_disp_data;\r
- assign _net_37 = _net_30&w_disp_data;\r
- assign _net_38 = ~_net_30;\r
- assign _net_39 = ~_net_30;\r
- assign _net_40 = ~_net_30;\r
- assign _net_41 = _u_VGARAM_o_rdack1&_u_VGARAM_o_rdack2;\r
- assign _net_42 = _net_41&r_data_select_flag;\r
- assign _net_43 = _net_41&(~r_data_select_flag);\r
- assign _net_44 = ~r_flg;\r
- assign _net_45 = (r_bit32_cnt)==(5'b11111);\r
- assign _net_46 = fs_disp_data&_net_44;\r
- assign _net_47 = (fs_disp_data&_net_44)&_net_45;\r
- assign _net_48 = (fs_disp_data&_net_44)&_net_45;\r
- assign _net_49 = (r_bit32_cnt)==(5'b11110);\r
- assign _net_50 = fs_disp_data&_net_44;\r
- assign _net_51 = (fs_disp_data&_net_44)&_net_49;\r
- assign _net_52 = (r_bit32_cnt)==(5'b11101);\r
- assign _net_53 = fs_disp_data&_net_44;\r
- assign _net_54 = (fs_disp_data&_net_44)&_net_52;\r
- assign _net_55 = (r_bit32_cnt)==(5'b11100);\r
- assign _net_56 = fs_disp_data&_net_44;\r
- assign _net_57 = (fs_disp_data&_net_44)&_net_55;\r
- assign _net_58 = (r_bit32_cnt)==(5'b11011);\r
- assign _net_59 = fs_disp_data&_net_44;\r
- assign _net_60 = (fs_disp_data&_net_44)&_net_58;\r
- assign _net_61 = (r_bit32_cnt)==(5'b11010);\r
- assign _net_62 = fs_disp_data&_net_44;\r
- assign _net_63 = (fs_disp_data&_net_44)&_net_61;\r
- assign _net_64 = (r_bit32_cnt)==(5'b11001);\r
- assign _net_65 = fs_disp_data&_net_44;\r
- assign _net_66 = (fs_disp_data&_net_44)&_net_64;\r
- assign _net_67 = (r_bit32_cnt)==(5'b11000);\r
- assign _net_68 = fs_disp_data&_net_44;\r
- assign _net_69 = (fs_disp_data&_net_44)&_net_67;\r
- assign _net_70 = (r_bit32_cnt)==(5'b10111);\r
- assign _net_71 = fs_disp_data&_net_44;\r
- assign _net_72 = (fs_disp_data&_net_44)&_net_70;\r
- assign _net_73 = (r_bit32_cnt)==(5'b10110);\r
- assign _net_74 = fs_disp_data&_net_44;\r
- assign _net_75 = (fs_disp_data&_net_44)&_net_73;\r
- assign _net_76 = (r_bit32_cnt)==(5'b10101);\r
- assign _net_77 = fs_disp_data&_net_44;\r
- assign _net_78 = (fs_disp_data&_net_44)&_net_76;\r
- assign _net_79 = (r_bit32_cnt)==(5'b10100);\r
- assign _net_80 = fs_disp_data&_net_44;\r
- assign _net_81 = (fs_disp_data&_net_44)&_net_79;\r
- assign _net_82 = (r_bit32_cnt)==(5'b10011);\r
- assign _net_83 = fs_disp_data&_net_44;\r
- assign _net_84 = (fs_disp_data&_net_44)&_net_82;\r
- assign _net_85 = (r_bit32_cnt)==(5'b10010);\r
- assign _net_86 = fs_disp_data&_net_44;\r
- assign _net_87 = (fs_disp_data&_net_44)&_net_85;\r
- assign _net_88 = (r_bit32_cnt)==(5'b10001);\r
- assign _net_89 = fs_disp_data&_net_44;\r
- assign _net_90 = (fs_disp_data&_net_44)&_net_88;\r
- assign _net_91 = (r_bit32_cnt)==(5'b10000);\r
- assign _net_92 = fs_disp_data&_net_44;\r
- assign _net_93 = (fs_disp_data&_net_44)&_net_91;\r
- assign _net_94 = (r_bit32_cnt)==(5'b01111);\r
- assign _net_95 = fs_disp_data&_net_44;\r
- assign _net_96 = (fs_disp_data&_net_44)&_net_94;\r
- assign _net_97 = (r_bit32_cnt)==(5'b01110);\r
- assign _net_98 = fs_disp_data&_net_44;\r
- assign _net_99 = (fs_disp_data&_net_44)&_net_97;\r
- assign _net_100 = (r_bit32_cnt)==(5'b01101);\r
- assign _net_101 = fs_disp_data&_net_44;\r
- assign _net_102 = (fs_disp_data&_net_44)&_net_100;\r
- assign _net_103 = (r_bit32_cnt)==(5'b01100);\r
- assign _net_104 = fs_disp_data&_net_44;\r
- assign _net_105 = (fs_disp_data&_net_44)&_net_103;\r
- assign _net_106 = (r_bit32_cnt)==(5'b01011);\r
- assign _net_107 = fs_disp_data&_net_44;\r
- assign _net_108 = (fs_disp_data&_net_44)&_net_106;\r
- assign _net_109 = (r_bit32_cnt)==(5'b01010);\r
- assign _net_110 = fs_disp_data&_net_44;\r
- assign _net_111 = (fs_disp_data&_net_44)&_net_109;\r
- assign _net_112 = (r_bit32_cnt)==(5'b01001);\r
- assign _net_113 = fs_disp_data&_net_44;\r
- assign _net_114 = (fs_disp_data&_net_44)&_net_112;\r
- assign _net_115 = (r_bit32_cnt)==(5'b01000);\r
- assign _net_116 = fs_disp_data&_net_44;\r
- assign _net_117 = (fs_disp_data&_net_44)&_net_115;\r
- assign _net_118 = (r_bit32_cnt)==(5'b00111);\r
- assign _net_119 = fs_disp_data&_net_44;\r
- assign _net_120 = (fs_disp_data&_net_44)&_net_118;\r
- assign _net_121 = (r_bit32_cnt)==(5'b00110);\r
- assign _net_122 = fs_disp_data&_net_44;\r
- assign _net_123 = (fs_disp_data&_net_44)&_net_121;\r
- assign _net_124 = (r_bit32_cnt)==(5'b00101);\r
- assign _net_125 = fs_disp_data&_net_44;\r
- assign _net_126 = (fs_disp_data&_net_44)&_net_124;\r
- assign _net_127 = (r_bit32_cnt)==(5'b00100);\r
- assign _net_128 = fs_disp_data&_net_44;\r
- assign _net_129 = (fs_disp_data&_net_44)&_net_127;\r
- assign _net_130 = (r_bit32_cnt)==(5'b00011);\r
- assign _net_131 = fs_disp_data&_net_44;\r
- assign _net_132 = (fs_disp_data&_net_44)&_net_130;\r
- assign _net_133 = (r_bit32_cnt)==(5'b00010);\r
- assign _net_134 = fs_disp_data&_net_44;\r
- assign _net_135 = (fs_disp_data&_net_44)&_net_133;\r
- assign _net_136 = (r_bit32_cnt)==(5'b00001);\r
- assign _net_137 = fs_disp_data&_net_44;\r
- assign _net_138 = (fs_disp_data&_net_44)&_net_136;\r
- assign _net_139 = (r_bit32_cnt)==(5'b00000);\r
- assign _net_140 = fs_disp_data&_net_44;\r
- assign _net_141 = (fs_disp_data&_net_44)&_net_139;\r
- assign _net_142 = (r_bit32_cnt)==(5'b11111);\r
- assign _net_143 = fs_disp_data&(~_net_44);\r
- assign _net_144 = (fs_disp_data&(~_net_44))&_net_142;\r
- assign _net_145 = (fs_disp_data&(~_net_44))&_net_142;\r
- assign _net_146 = (r_bit32_cnt)==(5'b11110);\r
- assign _net_147 = fs_disp_data&(~_net_44);\r
- assign _net_148 = (fs_disp_data&(~_net_44))&_net_146;\r
- assign _net_149 = (r_bit32_cnt)==(5'b11101);\r
- assign _net_150 = fs_disp_data&(~_net_44);\r
- assign _net_151 = (fs_disp_data&(~_net_44))&_net_149;\r
- assign _net_152 = (r_bit32_cnt)==(5'b11100);\r
- assign _net_153 = fs_disp_data&(~_net_44);\r
- assign _net_154 = (fs_disp_data&(~_net_44))&_net_152;\r
- assign _net_155 = (r_bit32_cnt)==(5'b11011);\r
- assign _net_156 = fs_disp_data&(~_net_44);\r
- assign _net_157 = (fs_disp_data&(~_net_44))&_net_155;\r
- assign _net_158 = (r_bit32_cnt)==(5'b11010);\r
- assign _net_159 = fs_disp_data&(~_net_44);\r
- assign _net_160 = (fs_disp_data&(~_net_44))&_net_158;\r
- assign _net_161 = (r_bit32_cnt)==(5'b11001);\r
- assign _net_162 = fs_disp_data&(~_net_44);\r
- assign _net_163 = (fs_disp_data&(~_net_44))&_net_161;\r
- assign _net_164 = (r_bit32_cnt)==(5'b11000);\r
- assign _net_165 = fs_disp_data&(~_net_44);\r
- assign _net_166 = (fs_disp_data&(~_net_44))&_net_164;\r
- assign _net_167 = (r_bit32_cnt)==(5'b10111);\r
- assign _net_168 = fs_disp_data&(~_net_44);\r
- assign _net_169 = (fs_disp_data&(~_net_44))&_net_167;\r
- assign _net_170 = (r_bit32_cnt)==(5'b10110);\r
- assign _net_171 = fs_disp_data&(~_net_44);\r
- assign _net_172 = (fs_disp_data&(~_net_44))&_net_170;\r
- assign _net_173 = (r_bit32_cnt)==(5'b10101);\r
- assign _net_174 = fs_disp_data&(~_net_44);\r
- assign _net_175 = (fs_disp_data&(~_net_44))&_net_173;\r
- assign _net_176 = (r_bit32_cnt)==(5'b10100);\r
- assign _net_177 = fs_disp_data&(~_net_44);\r
- assign _net_178 = (fs_disp_data&(~_net_44))&_net_176;\r
- assign _net_179 = (r_bit32_cnt)==(5'b10011);\r
- assign _net_180 = fs_disp_data&(~_net_44);\r
- assign _net_181 = (fs_disp_data&(~_net_44))&_net_179;\r
- assign _net_182 = (r_bit32_cnt)==(5'b10010);\r
- assign _net_183 = fs_disp_data&(~_net_44);\r
- assign _net_184 = (fs_disp_data&(~_net_44))&_net_182;\r
- assign _net_185 = (r_bit32_cnt)==(5'b10001);\r
- assign _net_186 = fs_disp_data&(~_net_44);\r
- assign _net_187 = (fs_disp_data&(~_net_44))&_net_185;\r
- assign _net_188 = (r_bit32_cnt)==(5'b10000);\r
- assign _net_189 = fs_disp_data&(~_net_44);\r
- assign _net_190 = (fs_disp_data&(~_net_44))&_net_188;\r
- assign _net_191 = (r_bit32_cnt)==(5'b01111);\r
- assign _net_192 = fs_disp_data&(~_net_44);\r
- assign _net_193 = (fs_disp_data&(~_net_44))&_net_191;\r
- assign _net_194 = (r_bit32_cnt)==(5'b01110);\r
- assign _net_195 = fs_disp_data&(~_net_44);\r
- assign _net_196 = (fs_disp_data&(~_net_44))&_net_194;\r
- assign _net_197 = (r_bit32_cnt)==(5'b01101);\r
- assign _net_198 = fs_disp_data&(~_net_44);\r
- assign _net_199 = (fs_disp_data&(~_net_44))&_net_197;\r
- assign _net_200 = (r_bit32_cnt)==(5'b01100);\r
- assign _net_201 = fs_disp_data&(~_net_44);\r
- assign _net_202 = (fs_disp_data&(~_net_44))&_net_200;\r
- assign _net_203 = (r_bit32_cnt)==(5'b01011);\r
- assign _net_204 = fs_disp_data&(~_net_44);\r
- assign _net_205 = (fs_disp_data&(~_net_44))&_net_203;\r
- assign _net_206 = (r_bit32_cnt)==(5'b01010);\r
- assign _net_207 = fs_disp_data&(~_net_44);\r
- assign _net_208 = (fs_disp_data&(~_net_44))&_net_206;\r
- assign _net_209 = (r_bit32_cnt)==(5'b01001);\r
- assign _net_210 = fs_disp_data&(~_net_44);\r
- assign _net_211 = (fs_disp_data&(~_net_44))&_net_209;\r
- assign _net_212 = (r_bit32_cnt)==(5'b01000);\r
- assign _net_213 = fs_disp_data&(~_net_44);\r
- assign _net_214 = (fs_disp_data&(~_net_44))&_net_212;\r
- assign _net_215 = (r_bit32_cnt)==(5'b00111);\r
- assign _net_216 = fs_disp_data&(~_net_44);\r
- assign _net_217 = (fs_disp_data&(~_net_44))&_net_215;\r
- assign _net_218 = (r_bit32_cnt)==(5'b00110);\r
- assign _net_219 = fs_disp_data&(~_net_44);\r
- assign _net_220 = (fs_disp_data&(~_net_44))&_net_218;\r
- assign _net_221 = (r_bit32_cnt)==(5'b00101);\r
- assign _net_222 = fs_disp_data&(~_net_44);\r
- assign _net_223 = (fs_disp_data&(~_net_44))&_net_221;\r
- assign _net_224 = (r_bit32_cnt)==(5'b00100);\r
- assign _net_225 = fs_disp_data&(~_net_44);\r
- assign _net_226 = (fs_disp_data&(~_net_44))&_net_224;\r
- assign _net_227 = (r_bit32_cnt)==(5'b00011);\r
- assign _net_228 = fs_disp_data&(~_net_44);\r
- assign _net_229 = (fs_disp_data&(~_net_44))&_net_227;\r
- assign _net_230 = (r_bit32_cnt)==(5'b00010);\r
- assign _net_231 = fs_disp_data&(~_net_44);\r
- assign _net_232 = (fs_disp_data&(~_net_44))&_net_230;\r
- assign _net_233 = (r_bit32_cnt)==(5'b00001);\r
- assign _net_234 = fs_disp_data&(~_net_44);\r
- assign _net_235 = (fs_disp_data&(~_net_44))&_net_233;\r
- assign _net_236 = (r_bit32_cnt)==(5'b00000);\r
- assign _net_237 = fs_disp_data&(~_net_44);\r
- assign _net_238 = (fs_disp_data&(~_net_44))&_net_236;\r
- assign o_v_sync = r_v_sync;\r
- assign o_h_sync = r_h_sync;\r
- assign o_vga_red = w_red;\r
- assign o_vga_green = w_green;\r
- assign o_vga_blue = w_blue;\r
- assign o_h_cnt = r_h_cnt;\r
- assign o_scanline = r_scanline_cnt;\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_v_sync <= 1'b0;\r
-else if ((_net_15|_net_12)) \r
- r_v_sync <= ~r_v_sync;\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_h_sync <= 1'b0;\r
-else if ((_net_10|_net_7)) \r
- r_h_sync <= ~r_h_sync;\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_vdata_flg <= 1'b0;\r
-else if ((_net_14)|(_net_13)) \r
- r_vdata_flg <= ((_net_14) ?1'b1:1'b0)|\r
- ((_net_13) ?1'b0:1'b0);\r
-\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_hdata_flg <= 1'b0;\r
-else if ((_net_9)|(_net_8)) \r
- r_hdata_flg <= ((_net_9) ?1'b1:1'b0)|\r
- ((_net_8) ?1'b0:1'b0);\r
-\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_h_cnt <= 10'b0000000000;\r
-else if ((_net_11|_net_10|_net_9|_net_8)|(_net_7)) \r
- r_h_cnt <= ((_net_11|_net_10|_net_9|_net_8) ?(r_h_cnt)+(10'b0000000001):10'b0)|\r
- ((_net_7) ?10'b0000000000:10'b0);\r
-\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_v_cnt <= 19'b0000000000000000000;\r
-else if ((_net_16|_net_15|_net_14|_net_13)|(_net_12)) \r
- r_v_cnt <= ((_net_16|_net_15|_net_14|_net_13) ?(r_v_cnt)+(19'b0000000000000000001):19'b0)|\r
- ((_net_12) ?19'b0000000000000000000:19'b0);\r
-\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_bit32_cnt <= 5'b00000;\r
-else if ((fs_disp_data)|(_net_26)|(_net_27|_net_25)) \r
- r_bit32_cnt <= ((fs_disp_data) ?(r_bit32_cnt)+(5'b00001):5'b0)|\r
- ((_net_26) ?(r_bit32_cnt)+(5'b00001):5'b0)|\r
- ((_net_27|_net_25) ?5'b00000:5'b0);\r
-\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_flg <= 1'b0;\r
-else if ((_net_145|_net_48)) \r
- r_flg <= ~r_flg;\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r1 <= 32'b00000000000000000000000000000000;\r
-else if ((_net_42)) \r
- r1 <= _u_VGARAM_o_rddata1;\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r2 <= 32'b00000000000000000000000000000000;\r
-else if ((_net_43)) \r
- r2 <= _u_VGARAM_o_rddata2;\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_data_select_flag <= 1'b0;\r
-else if ((_net_41)) \r
- r_data_select_flag <= ~r_data_select_flag;\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_scanline_cnt <= 10'b0000000000;\r
-else if ((_net_6)|(_net_4)) \r
- r_scanline_cnt <= ((_net_6) ?10'b0000000000:10'b0)|\r
- ((_net_4) ?(r_scanline_cnt)+(10'b0000000001):10'b0);\r
-\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_cnt_flg <= 1'b0;\r
-else if ((_net_5)|(_net_3)) \r
- r_cnt_flg <= ((_net_5) ?1'b0:1'b0)|\r
- ((_net_3) ?1'b1:1'b0);\r
-\r
-end\r
-always @(posedge m_clock or negedge p_reset)\r
- begin\r
-if (~p_reset)\r
- r_hld_h_sync <= 1'b0;\r
-else r_hld_h_sync <= r_h_sync;\r
-end\r
-endmodule\r
-/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Aug 06 22:05:10 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
-*/\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 16:37:27 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp :NON PROFIT USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:40 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
*/\r
\r
module vga_gen ( i_clk50 , i_fifo_rst , m_clock , p_reset , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_dummy_rgb , o_vcnt , i_wrdata , fi_fifo_write , o_rdack , o_led );\r
reg r_led;\r
reg r_init_flg;\r
reg [2:0] r_trg;\r
+ reg [25:0] r_cnt1;\r
+ reg [25:0] r_cnt2;\r
+ reg [25:0] r_cnt3;\r
+ reg r_buff1;\r
wire _u_FIFO_i_rst;\r
wire _u_FIFO_i_clk50;\r
wire _u_FIFO_i_clk25;\r
wire _net_51;\r
wire _net_52;\r
wire _net_53;\r
- reg _reg_54;\r
- reg _reg_55;\r
- reg _reg_56;\r
- reg _reg_57;\r
+ wire _net_54;\r
+ wire _net_55;\r
+ wire _net_56;\r
+ wire _net_57;\r
reg _reg_58;\r
- wire _net_59;\r
- wire _net_60;\r
- wire _net_61;\r
- wire _net_62;\r
+ reg _reg_59;\r
+ reg _reg_60;\r
+ reg _reg_61;\r
+ reg _reg_62;\r
wire _net_63;\r
- reg _reg_64;\r
- reg _reg_65;\r
+ wire _net_64;\r
+ wire _net_65;\r
wire _net_66;\r
+ wire _net_67;\r
+ reg _reg_68;\r
+ reg _reg_69;\r
+ wire _net_70;\r
vga_ram u_FIFO (.o_rdack(_u_FIFO_o_rdack), .o_rddata(_u_FIFO_o_rddata), .i_re(_u_FIFO_i_re), .i_wrdata(_u_FIFO_i_wrdata), .i_we(_u_FIFO_i_we), .i_clk25(_u_FIFO_i_clk25), .i_clk50(_u_FIFO_i_clk50), .i_rst(_u_FIFO_i_rst));\r
\r
- assign fs_fifo_read = _net_59|_reg_56|_net_15;\r
+ assign fs_fifo_read = _net_63|_reg_60|_net_15;\r
assign w_rddata = _u_FIFO_o_rddata;\r
- assign fs_fifo_ack = _reg_64;\r
+ assign fs_fifo_ack = _reg_68;\r
assign fs_initialize = _net_0;\r
assign _u_FIFO_i_rst = i_fifo_rst;\r
assign _u_FIFO_i_clk50 = i_clk50;\r
assign _net_0 = (r_trg)==(3'b011);\r
assign _net_1 = (r_cnt)==(26'b01011111010111100001000000);\r
assign _net_2 = ~_net_1;\r
- assign _net_3 = (r_hcnt) < (10'b1100100000);\r
+ assign _net_3 = (r_hcnt) < (10'b1100011111);\r
assign _net_4 = r_init_flg&_net_3;\r
assign _net_5 = r_init_flg&(~_net_3);\r
- assign _net_6 = (r_vcnt) < (10'b1000001001);\r
+ assign _net_6 = (r_vcnt) < (10'b1000000111);\r
assign _net_7 = r_init_flg&(~_net_3);\r
assign _net_8 = (r_init_flg&(~_net_3))&_net_6;\r
assign _net_9 = (r_init_flg&(~_net_3))&(~_net_6);\r
- assign _net_10 = ((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000));\r
+ assign _net_10 = (((r_hcnt) < (10'b1010000000))&((r_vcnt) < (10'b0111100000)))&r_vsync;\r
assign _net_11 = _net_10&r_init_flg;\r
assign _net_12 = (r_bit_cnt)==(3'b111);\r
assign _net_13 = _net_10&r_init_flg;\r
assign _net_34 = ~(r_outclr[6]);\r
assign _net_35 = _net_10&_net_34;\r
assign _net_36 = _net_10&(~_net_34);\r
- assign _net_37 = (r_hcnt)==(10'b1011110000);\r
+ assign _net_37 = (r_hcnt)==(10'b1011101111);\r
assign _net_38 = ~_net_10;\r
assign _net_39 = (~_net_10)&_net_37;\r
- assign _net_40 = (r_hcnt)==(10'b1010010000);\r
+ assign _net_40 = (r_hcnt)==(10'b1010001111);\r
assign _net_41 = ~_net_10;\r
assign _net_42 = (~_net_10)&_net_40;\r
assign _net_43 = (r_hcnt)==(10'b1010000000);\r
assign _net_48 = (~_net_10)&_net_43;\r
assign _net_49 = (~_net_10)&_net_43;\r
assign _net_50 = (~_net_10)&_net_43;\r
- assign _net_51 = (r_vcnt)==(10'b0111101100);\r
- assign _net_52 = (r_vcnt)==(10'b0111101010);\r
- assign _net_53 = (r_vcnt)==(10'b0111100000);\r
- assign _net_59 = fs_initialize|_reg_58;\r
- assign _net_60 = fs_initialize|_reg_57|_reg_58;\r
- assign _net_61 = fs_initialize|_reg_56|_reg_57;\r
- assign _net_62 = fs_initialize|_reg_55|_reg_56;\r
- assign _net_63 = fs_initialize|_reg_54|_reg_55;\r
- assign _net_66 = fs_fifo_read|_reg_64|_reg_65;\r
+ assign _net_51 = ((~_net_10)&fs_fifo_ack)&r_reg_cnt;\r
+ assign _net_52 = ~r_reg_cnt;\r
+ assign _net_53 = (~_net_10)&fs_fifo_ack;\r
+ assign _net_54 = ((~_net_10)&fs_fifo_ack)&_net_52;\r
+ assign _net_55 = (r_vcnt)==(10'b0111101011);\r
+ assign _net_56 = (r_vcnt)==(10'b0111101001);\r
+ assign _net_57 = (r_vcnt)==(10'b0111100000);\r
+ assign _net_63 = fs_initialize|_reg_62;\r
+ assign _net_64 = fs_initialize|_reg_61|_reg_62;\r
+ assign _net_65 = fs_initialize|_reg_60|_reg_61;\r
+ assign _net_66 = fs_initialize|_reg_59|_reg_60;\r
+ assign _net_67 = fs_initialize|_reg_58|_reg_59;\r
+ assign _net_70 = fs_fifo_read|_reg_68|_reg_69;\r
assign o_vsync = r_vsync;\r
assign o_hsync = r_hsync;\r
assign o_vga_r = ((_net_45|_net_33)?4'b0000:4'b0)|\r
begin\r
if (p_reset)\r
r_data1 <= 8'b00000000;\r
-else if ((_reg_57)|(_net_16)) \r
- r_data1 <= ((_reg_57) ?_u_FIFO_o_rddata:8'b0)|\r
- ((_net_16) ?w_rddata:8'b0);\r
+else if ((_reg_61)|(_net_51|_net_16)) \r
+ r_data1 <= ((_reg_61) ?_u_FIFO_o_rddata:8'b0)|\r
+ ((_net_51|_net_16) ?w_rddata:8'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_data2 <= 8'b00000000;\r
-else if ((_reg_55)|(_net_19)) \r
- r_data2 <= ((_reg_55) ?_u_FIFO_o_rddata:8'b0)|\r
- ((_net_19) ?w_rddata:8'b0);\r
+else if ((_reg_59)|(_net_54|_net_19)) \r
+ r_data2 <= ((_reg_59) ?_u_FIFO_o_rddata:8'b0)|\r
+ ((_net_54|_net_19) ?w_rddata:8'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_vsync <= 1'b0;\r
-else if ((_net_52)|(_net_51)) \r
- r_vsync <= ((_net_52) ?1'b0:1'b0)|\r
- ((_net_51) ?1'b1:1'b0);\r
+else if ((_net_56)|(_net_55)) \r
+ r_vsync <= ((_net_56) ?1'b0:1'b0)|\r
+ ((_net_55) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_init_flg <= 1'b0;\r
-else if ((_reg_54)) \r
+else if ((_reg_58)) \r
r_init_flg <= 1'b1;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
r_trg <= 3'b000;\r
else r_trg <= {r_trg[1:0],1'b1};\r
end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt1 <= 26'b00000000000000000000000000;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt2 <= 26'b00000000000000000000000000;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_cnt3 <= 26'b00000000000000000000000000;\r
+end\r
+always @(posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ r_buff1 <= 1'b0;\r
+end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_54 <= 1'b0;\r
-else if ((_net_63)) \r
- _reg_54 <= _reg_55;\r
+ _reg_58 <= 1'b0;\r
+else if ((_net_67)) \r
+ _reg_58 <= _reg_59;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_55 <= 1'b0;\r
-else if ((_net_62)) \r
- _reg_55 <= _reg_56;\r
+ _reg_59 <= 1'b0;\r
+else if ((_net_66)) \r
+ _reg_59 <= _reg_60;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_56 <= 1'b0;\r
-else if ((_net_61)) \r
- _reg_56 <= _reg_57;\r
+ _reg_60 <= 1'b0;\r
+else if ((_net_65)) \r
+ _reg_60 <= _reg_61;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_57 <= 1'b0;\r
-else if ((_net_60)) \r
- _reg_57 <= _reg_58|fs_initialize;\r
+ _reg_61 <= 1'b0;\r
+else if ((_net_64)) \r
+ _reg_61 <= _reg_62|fs_initialize;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_58 <= 1'b0;\r
-else if ((_reg_58)) \r
- _reg_58 <= 1'b0;\r
+ _reg_62 <= 1'b0;\r
+else if ((_reg_62)) \r
+ _reg_62 <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_64 <= 1'b0;\r
-else if ((_net_66)) \r
- _reg_64 <= _reg_65|fs_fifo_read;\r
+ _reg_68 <= 1'b0;\r
+else if ((_net_70)) \r
+ _reg_68 <= _reg_69|fs_fifo_read;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_69 <= 1'b0;\r
+else if ((_reg_69)) \r
+ _reg_69 <= 1'b0;\r
+end\r
+endmodule\r
+/*\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:44 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
+*/\r
+\r
+module vram ( p_reset , m_clock , clock , data , rdaddress , wraddress , wren , q );\r
+ input p_reset, m_clock;\r
+ input clock;\r
+ input [7:0] data;\r
+ input [12:0] rdaddress;\r
+ input [12:0] wraddress;\r
+ input wren;\r
+ output [7:0] q;\r
+ reg [7:0] m_vram [0:8191];\r
+ reg [7:0] r_ram_data;\r
+\r
+ assign q = r_ram_data;\r
+always @(posedge m_clock)\r
+ begin\r
+ if (wren )\r
+ m_vram[wraddress] <= data;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_65 <= 1'b0;\r
-else if ((_reg_65)) \r
- _reg_65 <= 1'b0;\r
+ r_ram_data <= 8'b00000000;\r
+else r_ram_data <= m_vram[rdaddress];\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 16:37:30 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:45 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r
\r
module push_sw ( p_reset , m_clock , i_sw , fo_sw_enb );\r
reg r_rise_flag;\r
reg r_sw_hld;\r
reg r_finish_flag;\r
- wire _net_67;\r
- wire _net_68;\r
- wire _net_69;\r
- wire _net_70;\r
wire _net_71;\r
wire _net_72;\r
wire _net_73;\r
wire _net_75;\r
wire _net_76;\r
wire _net_77;\r
+ wire _net_78;\r
+ wire _net_79;\r
+ wire _net_80;\r
+ wire _net_81;\r
\r
- assign _net_67 = i_sw&(~r_sw_hld);\r
- assign _net_68 = ~i_sw;\r
- assign _net_69 = ~_net_67;\r
- assign _net_70 = (~_net_67)&_net_68;\r
- assign _net_71 = (~_net_67)&_net_68;\r
- assign _net_72 = (r_rise_flag)==(1'b1);\r
- assign _net_73 = ((r_cnt)==(19'b1111010000100100000))&((r_finish_flag)==(1'b0));\r
- assign _net_74 = _net_72&_net_73;\r
- assign _net_75 = _net_72&_net_73;\r
- assign _net_76 = _net_72&(~_net_73);\r
- assign _net_77 = ~_net_72;\r
- assign fo_sw_enb = _net_75;\r
+ assign _net_71 = i_sw&(~r_sw_hld);\r
+ assign _net_72 = ~i_sw;\r
+ assign _net_73 = ~_net_71;\r
+ assign _net_74 = (~_net_71)&_net_72;\r
+ assign _net_75 = (~_net_71)&_net_72;\r
+ assign _net_76 = (r_rise_flag)==(1'b1);\r
+ assign _net_77 = ((r_cnt)==(19'b1111010000100100000))&((r_finish_flag)==(1'b0));\r
+ assign _net_78 = _net_76&_net_77;\r
+ assign _net_79 = _net_76&_net_77;\r
+ assign _net_80 = _net_76&(~_net_77);\r
+ assign _net_81 = ~_net_76;\r
+ assign fo_sw_enb = _net_79;\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_cnt <= 19'b0000000000000000000;\r
-else if ((_net_77)|(_net_76)) \r
- r_cnt <= ((_net_77) ?26'b00000000000000000000000000:19'b0)|\r
- ((_net_76) ?(r_cnt)+(19'b0000000000000000001):19'b0);\r
+else if ((_net_81)|(_net_80)) \r
+ r_cnt <= ((_net_81) ?26'b00000000000000000000000000:19'b0)|\r
+ ((_net_80) ?(r_cnt)+(19'b0000000000000000001):19'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_rise_flag <= 1'b0;\r
-else if ((_net_70)|(_net_67)) \r
- r_rise_flag <= ((_net_70) ?1'b0:1'b0)|\r
- ((_net_67) ?1'b1:1'b0);\r
+else if ((_net_74)|(_net_71)) \r
+ r_rise_flag <= ((_net_74) ?1'b0:1'b0)|\r
+ ((_net_71) ?1'b1:1'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_finish_flag <= 1'b0;\r
-else if ((_net_74)|(_net_71)) \r
- r_finish_flag <= ((_net_74) ?1'b1:1'b0)|\r
- ((_net_71) ?1'b0:1'b0);\r
+else if ((_net_78)|(_net_75)) \r
+ r_finish_flag <= ((_net_78) ?1'b1:1'b0)|\r
+ ((_net_75) ?1'b0:1'b0);\r
\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 16:37:31 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:45 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r
\r
module vga_top ( p_reset , m_clock , i_sw , o_vsync , o_hsync , o_vga_r , o_vga_g , o_vga_b , o_LED );\r
reg r_reset;\r
reg [25:0] r_sec_cnt;\r
reg r_LED;\r
- reg [13:0] r_init_cnt;\r
- reg [13:0] r_vram_adrs1;\r
- reg [13:0] r_vram_adrs2;\r
+ reg [12:0] r_init_cnt;\r
+ reg [13:0] r_vram_adrs;\r
+ reg [13:0] r_vram_adrs_temp;\r
reg [15:0] r_vram_rddata;\r
- reg [13:0] r_vram_start_adrs;\r
- reg r_hld_vram_start;\r
+ reg [12:0] r_vram_start_adrs;\r
+ reg r_fifo_write_adrs;\r
reg r_fifo_rst;\r
- wire [7:0] w_wrdata1;\r
- wire [7:0] w_wrdata2;\r
- wire [7:0] w_wradrs1;\r
- wire [7:0] w_wradrs2;\r
- wire fs_fifo1_write;\r
- wire fs_fifo2_write;\r
+ reg r_vga_ack_hld;\r
+ wire [7:0] w_data;\r
+ wire [15:0] w_exp_data;\r
+ wire fs_exp_exec;\r
wire fs_init;\r
- wire fs_fifo1_charge;\r
- wire fs_fifo2_charge;\r
- wire fs_vram_cnt_inc;\r
- reg [7:0] r_wradrs1;\r
- reg [7:0] r_wradrs2;\r
+ wire fs_fifo_write;\r
reg r_out_sel;\r
wire test_write;\r
reg [25:0] r_wait_cnt;\r
reg [25:0] r_wait_val;\r
reg p_wait;\r
- wire [13:0] _net_80;\r
+ wire [12:0] _net_84;\r
wire _proc_p_wait_set;\r
wire _proc_p_wait_reset;\r
- wire _net_81;\r
+ wire _net_85;\r
wire _u_VGA_i_clk50;\r
wire _u_VGA_i_fifo_rst;\r
wire _u_VGA_m_clock;\r
wire _u_BTN_1_fo_sw_enb;\r
wire _u_BTN_1_p_reset;\r
wire _u_BTN_1_m_clock;\r
- wire _net_82;\r
- wire _net_83;\r
- wire _net_84;\r
- wire _net_85;\r
+ wire _u_VRAM_clock;\r
+ wire [7:0] _u_VRAM_data;\r
+ wire [12:0] _u_VRAM_rdaddress;\r
+ wire [12:0] _u_VRAM_wraddress;\r
+ wire _u_VRAM_wren;\r
+ wire [7:0] _u_VRAM_q;\r
+ wire _u_VRAM_p_reset;\r
+ wire _u_VRAM_m_clock;\r
wire _net_86;\r
wire _net_87;\r
wire _net_88;\r
- reg _reg_89;\r
- reg _reg_90;\r
- reg _reg_91;\r
- reg _reg_92;\r
- reg _reg_93;\r
+ wire _net_89;\r
+ wire _net_90;\r
+ wire _net_91;\r
+ wire _net_92;\r
+ wire _net_93;\r
reg _reg_94;\r
reg _reg_95;\r
reg _reg_96;\r
reg _reg_98;\r
reg _reg_99;\r
reg _reg_100;\r
- wire _net_101;\r
- wire _reg_90_goto;\r
- wire _net_102;\r
- wire _reg_91_goin;\r
- wire _net_103;\r
- wire _net_104;\r
- wire _reg_91_goto;\r
- wire _net_105;\r
- wire _reg_89_goin;\r
+ reg _reg_101;\r
+ reg _reg_102;\r
+ reg _reg_103;\r
+ reg _reg_104;\r
+ reg _reg_105;\r
wire _net_106;\r
wire _net_107;\r
wire _net_108;\r
wire _net_120;\r
wire _net_121;\r
wire _net_122;\r
- wire _net_123;\r
- wire _net_124;\r
+ reg _reg_123;\r
+ reg _reg_124;\r
+ reg _reg_125;\r
+ reg _reg_126;\r
+ wire _net_127;\r
+ wire _reg_124_goto;\r
+ wire _net_128;\r
+ wire _reg_125_goin;\r
+ wire _net_129;\r
+ wire _net_130;\r
+ wire _reg_125_goto;\r
+ wire _net_131;\r
+ wire _reg_123_goin;\r
+ wire _net_132;\r
+ wire _net_133;\r
+ wire _net_134;\r
+ wire _net_135;\r
+ wire _net_136;\r
+ wire _net_137;\r
+ wire _net_138;\r
+vram u_VRAM (.p_reset(p_reset), .m_clock(m_clock), .q(_u_VRAM_q), .wren(_u_VRAM_wren), .wraddress(_u_VRAM_wraddress), .rdaddress(_u_VRAM_rdaddress), .data(_u_VRAM_data), .clock(_u_VRAM_clock));\r
push_sw u_BTN (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_fo_sw_enb), .i_sw(_u_BTN_i_sw));\r
push_sw u_BTN_3 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_3_fo_sw_enb), .i_sw(_u_BTN_3_i_sw));\r
push_sw u_BTN_2 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_2_fo_sw_enb), .i_sw(_u_BTN_2_i_sw));\r
push_sw u_BTN_1 (.p_reset(p_reset), .m_clock(m_clock), .fo_sw_enb(_u_BTN_1_fo_sw_enb), .i_sw(_u_BTN_1_i_sw));\r
vga_gen u_VGA (.o_led(_u_VGA_o_led), .o_rdack(_u_VGA_o_rdack), .fi_fifo_write(_u_VGA_fi_fifo_write), .i_wrdata(_u_VGA_i_wrdata), .o_vcnt(_u_VGA_o_vcnt), .o_dummy_rgb(_u_VGA_o_dummy_rgb), .o_vga_b(_u_VGA_o_vga_b), .o_vga_g(_u_VGA_o_vga_g), .o_vga_r(_u_VGA_o_vga_r), .o_hsync(_u_VGA_o_hsync), .o_vsync(_u_VGA_o_vsync), .p_reset(_u_VGA_p_reset), .m_clock(_u_VGA_m_clock), .i_fifo_rst(_u_VGA_i_fifo_rst), .i_clk50(_u_VGA_i_clk50));\r
\r
- assign fs_fifo1_write = 1'b0;\r
- assign fs_fifo2_write = 1'b0;\r
- assign fs_init = _net_86;\r
- assign fs_fifo1_charge = 1'b0;\r
- assign fs_fifo2_charge = 1'b0;\r
- assign fs_vram_cnt_inc = 1'b0;\r
+ assign w_exp_data = {w_data[7],w_data[7],w_data[6],w_data[6],w_data[5],w_data[5],w_data[4],w_data[4],w_data[3],w_data[3],w_data[2],w_data[2],w_data[1],w_data[1],w_data[0],w_data[0]};\r
+ assign fs_exp_exec = 1'b0;\r
+ assign fs_init = _net_90;\r
+ assign fs_fifo_write = _reg_97|_net_106|_net_93;\r
assign test_write = 1'b0;\r
- assign _net_80 = (r_init_cnt)+(14'b00000000000001);\r
- assign _proc_p_wait_set = 1'b0;\r
- assign _proc_p_wait_reset = _net_123;\r
- assign _net_81 = _proc_p_wait_set|_proc_p_wait_reset;\r
+ assign _net_84 = (r_init_cnt)+(13'b0000000000001);\r
+ assign _proc_p_wait_set = _reg_96;\r
+ assign _proc_p_wait_reset = _net_121;\r
+ assign _net_85 = _proc_p_wait_set|_proc_p_wait_reset;\r
assign _u_VGA_i_clk50 = m_clock;\r
assign _u_VGA_i_fifo_rst = r_fifo_rst;\r
assign _u_VGA_m_clock = r_cnt;\r
assign _u_VGA_p_reset = r_reset;\r
- assign _u_VGA_i_wrdata = r_init_cnt[7:0];\r
- assign _u_VGA_fi_fifo_write = _net_107|_reg_90;\r
+ assign _u_VGA_i_wrdata = ((_net_134)?{{7{r_fifo_write_adrs}},r_fifo_write_adrs}:8'b0)|\r
+ ((_reg_124)?~({{7{r_fifo_write_adrs}},r_fifo_write_adrs}):8'b0);\r
+ assign _u_VGA_fi_fifo_write = _net_133|_reg_124;\r
assign _u_BTN_i_sw = i_sw[0];\r
assign _u_BTN_3_i_sw = i_sw[3];\r
assign _u_BTN_2_i_sw = i_sw[2];\r
assign _u_BTN_1_i_sw = i_sw[1];\r
- assign _net_82 = (r_out_sel)==(1'b0);\r
- assign _net_83 = ~_net_82;\r
- assign _net_84 = ~_net_82;\r
- assign _net_85 = ~_net_82;\r
- assign _net_86 = (trigger)==(3'b011);\r
- assign _net_87 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
- assign _net_88 = ~_net_87;\r
- assign _net_101 = (_net_80) < (14'b00001000000000);\r
- assign _reg_90_goto = _net_102;\r
- assign _net_102 = _reg_90&_net_101;\r
- assign _reg_91_goin = _net_103;\r
- assign _net_103 = _reg_90&_net_101;\r
- assign _net_104 = ~((r_init_cnt) < (14'b00001000000000));\r
- assign _reg_91_goto = _net_105;\r
- assign _net_105 = _reg_91&_net_104;\r
- assign _reg_89_goin = _net_106;\r
- assign _net_106 = _reg_91&_net_104;\r
- assign _net_107 = _reg_91&(~_net_104);\r
- assign _net_108 = _reg_91&(~_net_104);\r
- assign _net_109 = fs_init|_reg_100;\r
- assign _net_110 = fs_init|_reg_99|_reg_100;\r
- assign _net_111 = fs_init|_reg_98|_reg_99;\r
- assign _net_112 = fs_init|_reg_97|_reg_98;\r
- assign _net_113 = fs_init|_reg_96|_reg_97;\r
- assign _net_114 = fs_init|_reg_95|_reg_96;\r
- assign _net_115 = fs_init|_reg_94|_reg_95;\r
- assign _net_116 = fs_init|_reg_93|_reg_94;\r
- assign _net_117 = fs_init|_reg_92|_reg_93;\r
- assign _net_118 = _reg_91_goin|_reg_91|_reg_92;\r
- assign _net_119 = _reg_91_goin|_reg_90|_reg_91;\r
- assign _net_120 = _reg_89_goin|_reg_89|_reg_90;\r
- assign _net_121 = (r_wait_cnt)==(r_wait_val);\r
- assign _net_122 = p_wait&_net_121;\r
- assign _net_123 = p_wait&_net_121;\r
- assign _net_124 = p_wait&(~_net_121);\r
+ assign _net_86 = (r_out_sel)==(1'b0);\r
+ assign _net_87 = ~_net_86;\r
+ assign _net_88 = ~_net_86;\r
+ assign _net_89 = ~_net_86;\r
+ assign _net_90 = (trigger)==(3'b011);\r
+ assign _net_91 = (r_sec_cnt)==(26'b10111110101111000010000000);\r
+ assign _net_92 = ~_net_91;\r
+ assign _net_93 = (~r_vga_ack_hld)&_u_VGA_o_rdack;\r
+ assign _net_106 = _reg_95&p_wait&_proc_p_wait_reset;\r
+ assign _net_107 = fs_init|_reg_105;\r
+ assign _net_108 = fs_init|_reg_104|_reg_105;\r
+ assign _net_109 = fs_init|_reg_103|_reg_104;\r
+ assign _net_110 = fs_init|_reg_102|_reg_103;\r
+ assign _net_111 = fs_init|_reg_101|_reg_102;\r
+ assign _net_112 = fs_init|_reg_100|_reg_101;\r
+ assign _net_113 = fs_init|_reg_99|_reg_100;\r
+ assign _net_114 = fs_init|_reg_98|_reg_99;\r
+ assign _net_115 = fs_init|_reg_97|_reg_98;\r
+ assign _net_116 = fs_init|_reg_96|_reg_97;\r
+ assign _net_117 = fs_init|_reg_95|_reg_96;\r
+ assign _net_118 = fs_init|_reg_94|_reg_95;\r
+ assign _net_119 = (r_wait_cnt)==(r_wait_val);\r
+ assign _net_120 = p_wait&_net_119;\r
+ assign _net_121 = p_wait&_net_119;\r
+ assign _net_122 = p_wait&(~_net_119);\r
+ assign _net_127 = (_net_84) < (13'b0000001010000);\r
+ assign _reg_124_goto = _net_128;\r
+ assign _net_128 = _reg_124&_net_127;\r
+ assign _reg_125_goin = _net_129;\r
+ assign _net_129 = _reg_124&_net_127;\r
+ assign _net_130 = ~((r_init_cnt) < (13'b0000001010000));\r
+ assign _reg_125_goto = _net_131;\r
+ assign _net_131 = _reg_125&_net_130;\r
+ assign _reg_123_goin = _net_132;\r
+ assign _net_132 = _reg_125&_net_130;\r
+ assign _net_133 = _reg_125&(~_net_130);\r
+ assign _net_134 = _reg_125&(~_net_130);\r
+ assign _net_135 = fs_fifo_write|_reg_126;\r
+ assign _net_136 = (_reg_125_goin|fs_fifo_write)|_reg_125|_reg_126;\r
+ assign _net_137 = (_reg_125_goin|fs_fifo_write)|_reg_124|_reg_125;\r
+ assign _net_138 = _reg_123_goin|_reg_123|_reg_124;\r
assign o_vsync = _u_VGA_o_vsync;\r
assign o_hsync = _u_VGA_o_hsync;\r
- assign o_vga_r = ((_net_83)?_u_VGA_o_vga_r:4'b0)|\r
- ((_net_82)?{{3{_u_VGA_o_dummy_rgb[2]}},_u_VGA_o_dummy_rgb[2]}:4'b0);\r
- assign o_vga_g = ((_net_84)?_u_VGA_o_vga_g:4'b0)|\r
- ((_net_82)?{{3{_u_VGA_o_dummy_rgb[1]}},_u_VGA_o_dummy_rgb[1]}:4'b0);\r
- assign o_vga_b = ((_net_85)?_u_VGA_o_vga_b:4'b0)|\r
- ((_net_82)?{{3{_u_VGA_o_dummy_rgb[0]}},_u_VGA_o_dummy_rgb[0]}:4'b0);\r
+ assign o_vga_r = ((_net_87)?_u_VGA_o_vga_r:4'b0)|\r
+ ((_net_86)?{{3{_u_VGA_o_dummy_rgb[2]}},_u_VGA_o_dummy_rgb[2]}:4'b0);\r
+ assign o_vga_g = ((_net_88)?_u_VGA_o_vga_g:4'b0)|\r
+ ((_net_86)?{{3{_u_VGA_o_dummy_rgb[1]}},_u_VGA_o_dummy_rgb[1]}:4'b0);\r
+ assign o_vga_b = ((_net_89)?_u_VGA_o_vga_b:4'b0)|\r
+ ((_net_86)?{{3{_u_VGA_o_dummy_rgb[0]}},_u_VGA_o_dummy_rgb[0]}:4'b0);\r
assign o_LED = {2'b00,i_sw,r_LED,_u_VGA_o_led};\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
begin\r
if (p_reset)\r
r_reset <= 1'b1;\r
-else if ((_reg_89)) \r
+else if ((_reg_94)) \r
r_reset <= 1'b0;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_sec_cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_88)|(_net_87)) \r
- r_sec_cnt <= ((_net_88) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_87) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_92)|(_net_91)) \r
+ r_sec_cnt <= ((_net_92) ?(r_sec_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_91) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_LED <= 1'b0;\r
-else if ((_net_87)) \r
+else if ((_net_91)) \r
r_LED <= ~r_LED;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_init_cnt <= 14'b00000000000000;\r
-else if ((_reg_92)|(_reg_90)) \r
- r_init_cnt <= ((_reg_92) ?14'b00000000000000:14'b0)|\r
- ((_reg_90) ?_net_80:14'b0);\r
+ r_init_cnt <= 13'b0000000000000;\r
+else if ((_net_135)|(_reg_124)) \r
+ r_init_cnt <= ((_net_135) ?13'b0000000000000:13'b0)|\r
+ ((_reg_124) ?_net_84:13'b0);\r
\r
end\r
always @(posedge p_reset)\r
begin\r
if (p_reset)\r
- r_vram_adrs1 <= 14'b00000000000000;\r
+ r_vram_adrs <= 14'b00000000000000;\r
end\r
always @(posedge p_reset)\r
begin\r
if (p_reset)\r
- r_vram_adrs2 <= 14'b00000000000000;\r
+ r_vram_adrs_temp <= 14'b00000000000000;\r
end\r
always @(posedge p_reset)\r
begin\r
always @(posedge p_reset)\r
begin\r
if (p_reset)\r
- r_vram_start_adrs <= 14'b00000000000000;\r
+ r_vram_start_adrs <= 13'b0000000000000;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- r_hld_vram_start <= 1'b0;\r
-else r_hld_vram_start <= _u_VGA_o_vcnt[0];\r
+ r_fifo_write_adrs <= 1'b0;\r
+else if ((_reg_123)) \r
+ r_fifo_write_adrs <= ~r_fifo_write_adrs;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
r_fifo_rst <= 1'b0;\r
-else if ((_net_109)|(_reg_96)) \r
- r_fifo_rst <= ((_net_109) ?1'b1:1'b0)|\r
- ((_reg_96) ?1'b0:1'b0);\r
+else if ((_net_107)|(_reg_101)) \r
+ r_fifo_rst <= ((_net_107) ?1'b1:1'b0)|\r
+ ((_reg_101) ?1'b0:1'b0);\r
\r
end\r
-always @(posedge p_reset)\r
- begin\r
-if (p_reset)\r
- r_wradrs1 <= 8'b00000000;\r
-end\r
-always @(posedge p_reset)\r
- begin\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
if (p_reset)\r
- r_wradrs2 <= 8'b00000000;\r
+ r_vga_ack_hld <= 1'b0;\r
+else r_vga_ack_hld <= _u_VGA_o_rdack;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
begin\r
if (p_reset)\r
r_wait_cnt <= 26'b00000000000000000000000000;\r
-else if ((_net_124)|(_net_122)) \r
- r_wait_cnt <= ((_net_124) ?(r_wait_cnt)+(26'b00000000000000000000000001):26'b0)|\r
- ((_net_122) ?26'b00000000000000000000000000:26'b0);\r
+else if ((_net_122)|(_net_120)) \r
+ r_wait_cnt <= ((_net_122) ?(r_wait_cnt)+(26'b00000000000000000000000001):26'b0)|\r
+ ((_net_120) ?26'b00000000000000000000000000:26'b0);\r
\r
end\r
-always @(posedge p_reset)\r
- begin\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
if (p_reset)\r
r_wait_val <= 26'b00000000000000000000000000;\r
+else if ((_reg_96)) \r
+ r_wait_val <= 26'b00000000000000000111110100;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
p_wait <= 1'b0;\r
-else if ((_net_81)) \r
+else if ((_net_85)) \r
p_wait <= _proc_p_wait_set;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_89 <= 1'b0;\r
-else if ((_net_120)) \r
- _reg_89 <= _reg_89_goin|(_reg_90&(~_reg_90_goto));\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_90 <= 1'b0;\r
-else if ((_net_119)) \r
- _reg_90 <= _reg_91&(~_reg_91_goto);\r
-end\r
-always @(posedge m_clock or posedge p_reset)\r
- begin\r
-if (p_reset)\r
- _reg_91 <= 1'b0;\r
+ _reg_94 <= 1'b0;\r
else if ((_net_118)) \r
- _reg_91 <= _reg_91_goin|_reg_92;\r
+ _reg_94 <= _reg_95&_proc_p_wait_reset;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_92 <= 1'b0;\r
+ _reg_95 <= 1'b0;\r
else if ((_net_117)) \r
- _reg_92 <= _reg_93;\r
+ _reg_95 <= _reg_96|(p_wait&(~_proc_p_wait_reset));\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_93 <= 1'b0;\r
+ _reg_96 <= 1'b0;\r
else if ((_net_116)) \r
- _reg_93 <= _reg_94;\r
+ _reg_96 <= _reg_97;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_94 <= 1'b0;\r
+ _reg_97 <= 1'b0;\r
else if ((_net_115)) \r
- _reg_94 <= _reg_95;\r
+ _reg_97 <= _reg_98;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_95 <= 1'b0;\r
+ _reg_98 <= 1'b0;\r
else if ((_net_114)) \r
- _reg_95 <= _reg_96;\r
+ _reg_98 <= _reg_99;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_96 <= 1'b0;\r
+ _reg_99 <= 1'b0;\r
else if ((_net_113)) \r
- _reg_96 <= _reg_97;\r
+ _reg_99 <= _reg_100;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_97 <= 1'b0;\r
+ _reg_100 <= 1'b0;\r
else if ((_net_112)) \r
- _reg_97 <= _reg_98;\r
+ _reg_100 <= _reg_101;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_98 <= 1'b0;\r
+ _reg_101 <= 1'b0;\r
else if ((_net_111)) \r
- _reg_98 <= _reg_99;\r
+ _reg_101 <= _reg_102;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_99 <= 1'b0;\r
+ _reg_102 <= 1'b0;\r
else if ((_net_110)) \r
- _reg_99 <= _reg_100|fs_init;\r
+ _reg_102 <= _reg_103;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
if (p_reset)\r
- _reg_100 <= 1'b0;\r
-else if ((_reg_100)) \r
- _reg_100 <= 1'b0;\r
+ _reg_103 <= 1'b0;\r
+else if ((_net_109)) \r
+ _reg_103 <= _reg_104;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_104 <= 1'b0;\r
+else if ((_net_108)) \r
+ _reg_104 <= _reg_105|fs_init;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_105 <= 1'b0;\r
+else if ((_reg_105)) \r
+ _reg_105 <= 1'b0;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_123 <= 1'b0;\r
+else if ((_net_138)) \r
+ _reg_123 <= _reg_123_goin|(_reg_124&(~_reg_124_goto));\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_124 <= 1'b0;\r
+else if ((_net_137)) \r
+ _reg_124 <= _reg_125&(~_reg_125_goto);\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_125 <= 1'b0;\r
+else if ((_net_136)) \r
+ _reg_125 <= (_reg_125_goin|_reg_126)|fs_fifo_write;\r
+end\r
+always @(posedge m_clock or posedge p_reset)\r
+ begin\r
+if (p_reset)\r
+ _reg_126 <= 1'b0;\r
+else if ((_reg_126)) \r
+ _reg_126 <= 1'b0;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Sun Nov 06 16:37:35 2011\r
- Licensed to Yujiro_Kaneko::yujiro.kaneko@overtone.co.jp \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 26 13:52:49 2011\r
+ Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
*/\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:08 2011\r
- Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:49:58 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
*/\r
\r
module vram ( p_reset , m_clock , clock , data , rdaddress , wraddress , wren , q );\r
input p_reset, m_clock;\r
input clock;\r
input [7:0] data;\r
- input [13:0] rdaddress;\r
- input [13:0] wraddress;\r
+ input [12:0] rdaddress;\r
+ input [12:0] wraddress;\r
input wren;\r
output [7:0] q;\r
- reg [7:0] m_vram [0:16383];\r
+ reg [7:0] m_vram [0:8191];\r
reg [7:0] r_ram_data;\r
\r
assign q = r_ram_data;\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:09 2011\r
- Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:49:59 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
*/\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:09 2011\r
- Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com :NON PROFIT USER:\r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:50:41 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
*/\r
\r
module vram_ctrl ( p_reset , m_clock , i_Wdata , i_Wadrs , i_Radrs , o_Rdata , fi_Wr_req , fi_Rd_req , fo_Rd_ack );\r
input p_reset, m_clock;\r
input [7:0] i_Wdata;\r
- input [13:0] i_Wadrs;\r
- input [13:0] i_Radrs;\r
+ input [12:0] i_Wadrs;\r
+ input [12:0] i_Radrs;\r
output [7:0] o_Rdata;\r
input fi_Wr_req;\r
input fi_Rd_req;\r
output fo_Rd_ack;\r
- reg [13:0] r_Radrs_hld;\r
+ reg [12:0] r_Radrs_hld;\r
wire _u_VRAM_clock;\r
wire [7:0] _u_VRAM_data;\r
- wire [13:0] _u_VRAM_rdaddress;\r
- wire [13:0] _u_VRAM_wraddress;\r
+ wire [12:0] _u_VRAM_rdaddress;\r
+ wire [12:0] _u_VRAM_wraddress;\r
wire _u_VRAM_wren;\r
wire [7:0] _u_VRAM_q;\r
wire _u_VRAM_p_reset;\r
\r
assign _u_VRAM_clock = m_clock;\r
assign _u_VRAM_data = i_Wdata;\r
- assign _u_VRAM_rdaddress = ((_net_3)?i_Radrs:14'b0)|\r
- ((_reg_1)?r_Radrs_hld:14'b0);\r
+ assign _u_VRAM_rdaddress = ((_net_3)?i_Radrs:13'b0)|\r
+ ((_reg_1)?r_Radrs_hld:13'b0);\r
assign _u_VRAM_wraddress = i_Wadrs;\r
assign _u_VRAM_wren = fi_Wr_req|\r
((_net_0)?1'b0:1'b0);\r
always @(posedge p_reset)\r
begin\r
if (p_reset)\r
- r_Radrs_hld <= 14'b00000000000000;\r
+ r_Radrs_hld <= 13'b0000000000000;\r
end\r
always @(posedge m_clock or posedge p_reset)\r
begin\r
end\r
endmodule\r
/*\r
- Produced by NSL Core(version=20110302), IP ARCH, Inc. Wed Sep 21 22:08:11 2011\r
- Licensed to Yujiro_Kaneko::zyangalianhamster01@gmail.com \r
+ Produced by NSL Core(version=20110302), IP ARCH, Inc. Sat Nov 19 16:50:42 2011\r
+ Licensed to :LIMITED EVALUATION USER:\r
*/\r
\r
reg r_init_cnt[13] = 0 ;\r
reg r_vram_adrs[14] = 0 ;\r
+ reg r_vram_adrs_temp[14] = 0 ;\r
reg r_vram_rddata[16] = 0 ;\r
reg r_vram_start_adrs[13] = 0 ;\r
reg r_fifo_write_adrs = 0 ;\r
\r
r_fifo_write_adrs := ~r_fifo_write_adrs ;\r
}\r
+ \r
+/*\r
+ param w_temp_vram_adrs[14]\r
+\r
+ func fs_fifo_write seq {\r
+ { // Initialize\r
+ r_temp_vram_adrs := w_temp_vram_adrs ;\r
+ r_vram_adrs := w_temp_vram_adrs ;\r
+ }\r
+\r
+ // 1 Line Write\r
+ for(r_init_cnt:=0; r_init_cnt<80; r_init_cnt++) {\r
+ {\r
+ u_VGA.fi_fifo_write(r_vram_adrs) ;\r
+ r_vram_adrs++ ;\r
+ }\r
+ }\r
+ \r
+ r_vram_adrs := w_temp_vram_adrs ;\r
+ // 1 Line Write\r
+ for(r_init_cnt:=0; r_init_cnt<80; r_init_cnt++) {\r
+ {\r
+ u_VGA.fi_fifo_write(r_vram_adrs) ;\r
+ r_vram_adrs++ ;\r
+ }\r
+ }\r
+ }\r
+ \r
+ func fs_fifo_brank_write seq {\r
+ for(r_init_cnt:=0; r_init_cnt<80; r_init_cnt++) {\r
+ u_VGA.fi_fifo_write( 8'b00000000 );\r
+ u_VGA.fi_fifo_write( 8'b00000000 );\r
+ } \r
+ }\r
+*/\r
}
\ No newline at end of file