9 #define SPREG_DRAM_ABWCR ((volatile uint8 *)0xfee020)
10 #define SPREG_DRAM_ASTCR ((volatile uint8 *)0xfee021)
11 #define SPREG_DRAM_RTCOR ((volatile uint8 *)0xfee02a)
12 #define SPREG_DRAM_RTMCSR ((volatile uint8 *)0xfee028)
13 #define SPREG_DRAM_DRCRB ((volatile uint8 *)0xfee027)
14 #define SPREG_DRAM_DRCRA ((volatile uint8 *)0xfee026)
15 #define SPREG_DRAM_WCRH ((volatile uint8 *)0xfee022)
16 #define SPREG_DRAM_WCRL ((volatile uint8 *)0xfee023)
21 #define SPREG_ITU_TMDR ((volatile uint8 *)0xFFFF62)
22 #define SPREG_ITU_TSTR ((volatile uint8 *)0xFFFF60)
23 #define SPREG_ITU_16TCNT2H ((volatile uint8 *)0xFFFF7A)
24 #define SPREG_ITU_16TCNT2L ((volatile uint8 *)0xFFFF7B)
26 #define SPREG_ITU_TSTR_BIT_STR2 (1 << 2)
27 #define SPREG_ITU_TMDR_BIT_MDF (1 << 6)
30 * Chip Select Control Register
32 #define SPREG_CSCR ((volatile uint8 *)0xFEE01F)
34 void spreg_itu_init(void)
36 *SPREG_ITU_TMDR = SPREG_ITU_TMDR_BIT_MDF;
37 *SPREG_ITU_TSTR = SPREG_ITU_TSTR_BIT_STR2;
40 void spreg_itu_counter(uint16 *value)
42 *value = ((*SPREG_ITU_16TCNT2H) << 8) | (*SPREG_ITU_16TCNT2L << 0);
45 void spreg_dram_init(void)
49 *SPREG_DRAM_ABWCR = 0xff;
50 *SPREG_DRAM_RTCOR = 0x03; /* リフレッシュ周期を短めに設定 */
51 *SPREG_DRAM_RTMCSR = 0x37;
52 *SPREG_DRAM_DRCRB = 0x8f; /* ウエイト挿入 */
53 *SPREG_DRAM_DRCRA = 0x20;
55 *PORTCONF_P1DDR = 0xff;
56 *PORTCONF_P2DDR = 0x07;
57 *PORTCONF_P8DDR = 0xee;
58 *PORTCONF_PBDDR = 0x6c;
60 for (i = 0; i < 200; i++) {
61 for (j = 0; j < 200; j++) {
69 *SPREG_DRAM_WCRH = 0xff;
70 *SPREG_DRAM_WCRL = 0xff;
75 *SPREG_DRAM_ASTCR = 0xff;
78 * チップセレクトコントロールレジスタもここで設定する。