1 ;; GCC machine description for SSE instructions
2 ;; Copyright (C) 2005, 2006, 2007, 2008, 2009
3 ;; Free Software Foundation, Inc.
5 ;; This file is part of GCC.
7 ;; GCC is free software; you can redistribute it and/or modify
8 ;; it under the terms of the GNU General Public License as published by
9 ;; the Free Software Foundation; either version 3, or (at your option)
12 ;; GCC is distributed in the hope that it will be useful,
13 ;; but WITHOUT ANY WARRANTY; without even the implied warranty of
14 ;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 ;; GNU General Public License for more details.
17 ;; You should have received a copy of the GNU General Public License
18 ;; along with GCC; see the file COPYING3. If not see
19 ;; <http://www.gnu.org/licenses/>.
22 ;; 16 byte integral modes handled by SSE, minus TImode, which gets
23 ;; special-cased for TARGET_64BIT.
24 (define_mode_iterator SSEMODEI [V16QI V8HI V4SI V2DI])
26 ;; All 16-byte vector modes handled by SSE
27 (define_mode_iterator SSEMODE [V16QI V8HI V4SI V2DI V4SF V2DF])
29 ;; 32 byte integral vector modes handled by AVX
30 (define_mode_iterator AVX256MODEI [V32QI V16HI V8SI V4DI])
32 ;; All 32-byte vector modes handled by AVX
33 (define_mode_iterator AVX256MODE [V32QI V16HI V8SI V4DI V8SF V4DF])
35 ;; All QI vector modes handled by AVX
36 (define_mode_iterator AVXMODEQI [V32QI V16QI])
38 ;; All DI vector modes handled by AVX
39 (define_mode_iterator AVXMODEDI [V4DI V2DI])
41 ;; All vector modes handled by AVX
42 (define_mode_iterator AVXMODE [V16QI V8HI V4SI V2DI V4SF V2DF V32QI V16HI V8SI V4DI V8SF V4DF])
45 (define_mode_iterator SSEMODE12 [V16QI V8HI])
46 (define_mode_iterator SSEMODE24 [V8HI V4SI])
47 (define_mode_iterator SSEMODE14 [V16QI V4SI])
48 (define_mode_iterator SSEMODE124 [V16QI V8HI V4SI])
49 (define_mode_iterator SSEMODE248 [V8HI V4SI V2DI])
50 (define_mode_iterator SSEMODE1248 [V16QI V8HI V4SI V2DI])
51 (define_mode_iterator SSEMODEF4 [SF DF V4SF V2DF])
52 (define_mode_iterator SSEMODEF2P [V4SF V2DF])
54 (define_mode_iterator AVX256MODEF2P [V8SF V4DF])
55 (define_mode_iterator AVX256MODE2P [V8SI V8SF V4DF])
56 (define_mode_iterator AVX256MODE4P [V4DI V4DF])
57 (define_mode_iterator AVX256MODE8P [V8SI V8SF])
58 (define_mode_iterator AVXMODEF2P [V4SF V2DF V8SF V4DF])
59 (define_mode_iterator AVXMODEF4P [V4SF V4DF])
60 (define_mode_iterator AVXMODEDCVTDQ2PS [V4SF V8SF])
61 (define_mode_iterator AVXMODEDCVTPS2DQ [V4SI V8SI])
63 ;; Int-float size matches
64 (define_mode_iterator SSEMODE4S [V4SF V4SI])
65 (define_mode_iterator SSEMODE2D [V2DF V2DI])
67 ;; Modes handled by integer vcond pattern
68 (define_mode_iterator SSEMODE124C8 [V16QI V8HI V4SI
69 (V2DI "TARGET_SSE4_2")])
71 ;; Mapping from float mode to required SSE level
72 (define_mode_attr sse [(SF "sse") (DF "sse2") (V4SF "sse") (V2DF "sse2")])
74 ;; Mapping from integer vector mode to mnemonic suffix
75 (define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
77 ;; Mapping of the avx suffix
78 (define_mode_attr ssemodesuffixf4 [(SF "ss") (DF "sd")
79 (V4SF "ps") (V2DF "pd")])
81 (define_mode_attr ssemodesuffixf2c [(V4SF "s") (V2DF "d")])
83 ;; Mapping of vector modes back to the scalar modes
84 (define_mode_attr ssescalarmode [(V4SF "SF") (V2DF "DF")
85 (V16QI "QI") (V8HI "HI")
86 (V4SI "SI") (V2DI "DI")])
88 ;; Mapping of vector modes to a vector mode of double size
89 (define_mode_attr ssedoublesizemode [(V2DF "V4DF") (V2DI "V4DI")
90 (V4SF "V8SF") (V4SI "V8SI")])
92 ;; Number of scalar elements in each vector type
93 (define_mode_attr ssescalarnum [(V4SF "4") (V2DF "2")
94 (V16QI "16") (V8HI "8")
95 (V4SI "4") (V2DI "2")])
98 (define_mode_attr avxvecmode
99 [(V16QI "TI") (V8HI "TI") (V4SI "TI") (V2DI "TI") (V4SF "V4SF")
100 (V2DF "V2DF") (V32QI "OI") (V16HI "OI") (V8SI "OI") (V4DI "OI")
101 (V8SF "V8SF") (V4DF "V4DF")])
102 (define_mode_attr avxvecpsmode
103 [(V16QI "V4SF") (V8HI "V4SF") (V4SI "V4SF") (V2DI "V4SF")
104 (V32QI "V8SF") (V16HI "V8SF") (V8SI "V8SF") (V4DI "V8SF")])
105 (define_mode_attr avxhalfvecmode
106 [(V4SF "V2SF") (V32QI "V16QI") (V16HI "V8HI") (V8SI "V4SI")
107 (V4DI "V2DI") (V8SF "V4SF") (V4DF "V2DF")])
108 (define_mode_attr avxscalarmode
109 [(V16QI "QI") (V8HI "HI") (V4SI "SI") (V4SF "SF") (V2DF "DF")
110 (V8SF "SF") (V4DF "DF")])
111 (define_mode_attr avxcvtvecmode
112 [(V4SF "V4SI") (V8SF "V8SI") (V4SI "V4SF") (V8SI "V8SF")])
113 (define_mode_attr avxpermvecmode
114 [(V2DF "V2DI") (V4SF "V4SI") (V4DF "V4DI") (V8SF "V8SI")])
115 (define_mode_attr avxmodesuffixf2c
116 [(V4SF "s") (V2DF "d") (V8SF "s") (V4DF "d")])
117 (define_mode_attr avxmodesuffixp
118 [(V2DF "pd") (V4SI "si") (V4SF "ps") (V8SF "ps") (V8SI "si")
120 (define_mode_attr avxmodesuffix
121 [(V16QI "") (V32QI "256") (V4SI "") (V4SF "") (V2DF "")
122 (V8SI "256") (V8SF "256") (V4DF "256")])
124 ;; Mapping of immediate bits for blend instructions
125 (define_mode_attr blendbits
126 [(V8SF "255") (V4SF "15") (V4DF "15") (V2DF "3")])
128 ;; Mapping of immediate bits for vpermil instructions
129 (define_mode_attr vpermilbits
130 [(V8SF "255") (V4SF "255") (V4DF "15") (V2DF "3")])
132 ;; Mapping of immediate bits for pinsr instructions
133 (define_mode_attr pinsrbits [(V16QI "32768") (V8HI "128") (V4SI "8")])
135 ;; Patterns whose name begins with "sse{,2,3}_" are invoked by intrinsics.
137 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
141 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
143 (define_expand "mov<mode>"
144 [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "")
145 (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))]
148 ix86_expand_vector_move (<MODE>mode, operands);
152 (define_insn "*avx_mov<mode>_internal"
153 [(set (match_operand:AVXMODE 0 "nonimmediate_operand" "=x,x ,m")
154 (match_operand:AVXMODE 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
156 && (register_operand (operands[0], <MODE>mode)
157 || register_operand (operands[1], <MODE>mode))"
159 switch (which_alternative)
162 return standard_sse_constant_opcode (insn, operands[1]);
165 switch (get_attr_mode (insn))
169 return "vmovaps\t{%1, %0|%0, %1}";
172 return "vmovapd\t{%1, %0|%0, %1}";
174 return "vmovdqa\t{%1, %0|%0, %1}";
180 [(set_attr "type" "sselog1,ssemov,ssemov")
181 (set_attr "prefix" "vex")
182 (set_attr "mode" "<avxvecmode>")])
184 ;; All of these patterns are enabled for SSE1 as well as SSE2.
185 ;; This is essential for maintaining stable calling conventions.
187 (define_expand "mov<mode>"
188 [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "")
189 (match_operand:SSEMODE 1 "nonimmediate_operand" ""))]
192 ix86_expand_vector_move (<MODE>mode, operands);
196 (define_insn "*mov<mode>_internal"
197 [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "=x,x ,m")
198 (match_operand:SSEMODE 1 "nonimmediate_or_sse_const_operand" "C ,xm,x"))]
200 && (register_operand (operands[0], <MODE>mode)
201 || register_operand (operands[1], <MODE>mode))"
203 switch (which_alternative)
206 return standard_sse_constant_opcode (insn, operands[1]);
209 switch (get_attr_mode (insn))
212 return "movaps\t{%1, %0|%0, %1}";
214 return "movapd\t{%1, %0|%0, %1}";
216 return "movdqa\t{%1, %0|%0, %1}";
222 [(set_attr "type" "sselog1,ssemov,ssemov")
224 (cond [(ior (ior (ne (symbol_ref "optimize_function_for_size_p (cfun)") (const_int 0))
225 (eq (symbol_ref "TARGET_SSE2") (const_int 0)))
226 (and (eq_attr "alternative" "2")
227 (ne (symbol_ref "TARGET_SSE_TYPELESS_STORES")
229 (const_string "V4SF")
230 (eq (const_string "<MODE>mode") (const_string "V4SFmode"))
231 (const_string "V4SF")
232 (eq (const_string "<MODE>mode") (const_string "V2DFmode"))
233 (const_string "V2DF")
235 (const_string "TI")))])
237 ;; Move a DI from a 32-bit register pair (e.g. %edx:%eax) to an xmm.
238 ;; We'd rather avoid this entirely; if the 32-bit reg pair was loaded
239 ;; from memory, we'd prefer to load the memory directly into the %xmm
240 ;; register. To facilitate this happy circumstance, this pattern won't
241 ;; split until after register allocation. If the 64-bit value didn't
242 ;; come from memory, this is the best we can do. This is much better
243 ;; than storing %edx:%eax into a stack temporary and loading an %xmm
246 (define_insn_and_split "movdi_to_sse"
248 [(set (match_operand:V4SI 0 "register_operand" "=?x,x")
249 (subreg:V4SI (match_operand:DI 1 "nonimmediate_operand" "r,m") 0))
250 (clobber (match_scratch:V4SI 2 "=&x,X"))])]
251 "!TARGET_64BIT && TARGET_SSE2 && TARGET_INTER_UNIT_MOVES"
253 "&& reload_completed"
256 if (register_operand (operands[1], DImode))
258 /* The DImode arrived in a pair of integral registers (e.g. %edx:%eax).
259 Assemble the 64-bit DImode value in an xmm register. */
260 emit_insn (gen_sse2_loadld (operands[0], CONST0_RTX (V4SImode),
261 gen_rtx_SUBREG (SImode, operands[1], 0)));
262 emit_insn (gen_sse2_loadld (operands[2], CONST0_RTX (V4SImode),
263 gen_rtx_SUBREG (SImode, operands[1], 4)));
264 emit_insn (gen_sse2_punpckldq (operands[0], operands[0], operands[2]));
266 else if (memory_operand (operands[1], DImode))
267 emit_insn (gen_vec_concatv2di (gen_lowpart (V2DImode, operands[0]), operands[1], const0_rtx));
273 [(set (match_operand:V4SF 0 "register_operand" "")
274 (match_operand:V4SF 1 "zero_extended_scalar_load_operand" ""))]
275 "TARGET_SSE && reload_completed"
278 (vec_duplicate:V4SF (match_dup 1))
282 operands[1] = simplify_gen_subreg (SFmode, operands[1], V4SFmode, 0);
283 operands[2] = CONST0_RTX (V4SFmode);
287 [(set (match_operand:V2DF 0 "register_operand" "")
288 (match_operand:V2DF 1 "zero_extended_scalar_load_operand" ""))]
289 "TARGET_SSE2 && reload_completed"
290 [(set (match_dup 0) (vec_concat:V2DF (match_dup 1) (match_dup 2)))]
292 operands[1] = simplify_gen_subreg (DFmode, operands[1], V2DFmode, 0);
293 operands[2] = CONST0_RTX (DFmode);
296 (define_expand "push<mode>1"
297 [(match_operand:AVX256MODE 0 "register_operand" "")]
300 ix86_expand_push (<MODE>mode, operands[0]);
304 (define_expand "push<mode>1"
305 [(match_operand:SSEMODE 0 "register_operand" "")]
308 ix86_expand_push (<MODE>mode, operands[0]);
312 (define_expand "movmisalign<mode>"
313 [(set (match_operand:AVX256MODE 0 "nonimmediate_operand" "")
314 (match_operand:AVX256MODE 1 "nonimmediate_operand" ""))]
317 ix86_expand_vector_move_misalign (<MODE>mode, operands);
321 (define_expand "movmisalign<mode>"
322 [(set (match_operand:SSEMODE 0 "nonimmediate_operand" "")
323 (match_operand:SSEMODE 1 "nonimmediate_operand" ""))]
326 ix86_expand_vector_move_misalign (<MODE>mode, operands);
330 (define_insn "avx_movup<avxmodesuffixf2c><avxmodesuffix>"
331 [(set (match_operand:AVXMODEF2P 0 "nonimmediate_operand" "=x,m")
333 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm,x")]
335 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
336 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
337 "vmovup<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
338 [(set_attr "type" "ssemov")
339 (set_attr "movu" "1")
340 (set_attr "prefix" "vex")
341 (set_attr "mode" "<MODE>")])
343 (define_insn "sse2_movq128"
344 [(set (match_operand:V2DI 0 "register_operand" "=x")
347 (match_operand:V2DI 1 "nonimmediate_operand" "xm")
348 (parallel [(const_int 0)]))
351 "%vmovq\t{%1, %0|%0, %1}"
352 [(set_attr "type" "ssemov")
353 (set_attr "prefix" "maybe_vex")
354 (set_attr "mode" "TI")])
356 (define_insn "<sse>_movup<ssemodesuffixf2c>"
357 [(set (match_operand:SSEMODEF2P 0 "nonimmediate_operand" "=x,m")
359 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm,x")]
361 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
362 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
363 "movup<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
364 [(set_attr "type" "ssemov")
365 (set_attr "movu" "1")
366 (set_attr "mode" "<MODE>")])
368 (define_insn "avx_movdqu<avxmodesuffix>"
369 [(set (match_operand:AVXMODEQI 0 "nonimmediate_operand" "=x,m")
371 [(match_operand:AVXMODEQI 1 "nonimmediate_operand" "xm,x")]
373 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
374 "vmovdqu\t{%1, %0|%0, %1}"
375 [(set_attr "type" "ssemov")
376 (set_attr "movu" "1")
377 (set_attr "prefix" "vex")
378 (set_attr "mode" "<avxvecmode>")])
380 (define_insn "sse2_movdqu"
381 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
382 (unspec:V16QI [(match_operand:V16QI 1 "nonimmediate_operand" "xm,x")]
384 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
385 "movdqu\t{%1, %0|%0, %1}"
386 [(set_attr "type" "ssemov")
387 (set_attr "movu" "1")
388 (set_attr "prefix_data16" "1")
389 (set_attr "mode" "TI")])
391 (define_insn "avx_movnt<mode>"
392 [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
394 [(match_operand:AVXMODEF2P 1 "register_operand" "x")]
396 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
397 "vmovntp<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
398 [(set_attr "type" "ssemov")
399 (set_attr "prefix" "vex")
400 (set_attr "mode" "<MODE>")])
402 (define_insn "<sse>_movnt<mode>"
403 [(set (match_operand:SSEMODEF2P 0 "memory_operand" "=m")
405 [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
407 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
408 "movntp<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
409 [(set_attr "type" "ssemov")
410 (set_attr "mode" "<MODE>")])
412 (define_insn "avx_movnt<mode>"
413 [(set (match_operand:AVXMODEDI 0 "memory_operand" "=m")
415 [(match_operand:AVXMODEDI 1 "register_operand" "x")]
418 "vmovntdq\t{%1, %0|%0, %1}"
419 [(set_attr "type" "ssecvt")
420 (set_attr "prefix" "vex")
421 (set_attr "mode" "<avxvecmode>")])
423 (define_insn "sse2_movntv2di"
424 [(set (match_operand:V2DI 0 "memory_operand" "=m")
425 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")]
428 "movntdq\t{%1, %0|%0, %1}"
429 [(set_attr "type" "ssemov")
430 (set_attr "prefix_data16" "1")
431 (set_attr "mode" "TI")])
433 (define_insn "sse2_movntsi"
434 [(set (match_operand:SI 0 "memory_operand" "=m")
435 (unspec:SI [(match_operand:SI 1 "register_operand" "r")]
438 "movnti\t{%1, %0|%0, %1}"
439 [(set_attr "type" "ssemov")
440 (set_attr "prefix_data16" "0")
441 (set_attr "mode" "V2DF")])
443 (define_insn "avx_lddqu<avxmodesuffix>"
444 [(set (match_operand:AVXMODEQI 0 "register_operand" "=x")
446 [(match_operand:AVXMODEQI 1 "memory_operand" "m")]
449 "vlddqu\t{%1, %0|%0, %1}"
450 [(set_attr "type" "ssecvt")
451 (set_attr "movu" "1")
452 (set_attr "prefix" "vex")
453 (set_attr "mode" "<avxvecmode>")])
455 (define_insn "sse3_lddqu"
456 [(set (match_operand:V16QI 0 "register_operand" "=x")
457 (unspec:V16QI [(match_operand:V16QI 1 "memory_operand" "m")]
460 "lddqu\t{%1, %0|%0, %1}"
461 [(set_attr "type" "ssemov")
462 (set_attr "movu" "1")
463 (set_attr "prefix_data16" "0")
464 (set_attr "prefix_rep" "1")
465 (set_attr "mode" "TI")])
467 ; Expand patterns for non-temporal stores. At the moment, only those
468 ; that directly map to insns are defined; it would be possible to
469 ; define patterns for other modes that would expand to several insns.
471 (define_expand "storent<mode>"
472 [(set (match_operand:SSEMODEF2P 0 "memory_operand" "")
474 [(match_operand:SSEMODEF2P 1 "register_operand" "")]
476 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
479 (define_expand "storent<mode>"
480 [(set (match_operand:MODEF 0 "memory_operand" "")
482 [(match_operand:MODEF 1 "register_operand" "")]
487 (define_expand "storentv2di"
488 [(set (match_operand:V2DI 0 "memory_operand" "")
489 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "")]
494 (define_expand "storentsi"
495 [(set (match_operand:SI 0 "memory_operand" "")
496 (unspec:SI [(match_operand:SI 1 "register_operand" "")]
501 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
503 ;; Parallel floating point arithmetic
505 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
507 (define_expand "<code><mode>2"
508 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
510 (match_operand:SSEMODEF2P 1 "register_operand" "")))]
511 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
512 "ix86_expand_fp_absneg_operator (<CODE>, <MODE>mode, operands); DONE;")
514 (define_expand "<plusminus_insn><mode>3"
515 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
516 (plusminus:AVX256MODEF2P
517 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
518 (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
519 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
520 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
522 (define_insn "*avx_<plusminus_insn><mode>3"
523 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
524 (plusminus:AVXMODEF2P
525 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "<comm>x")
526 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
527 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
528 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
529 "v<plusminus_mnemonic>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
530 [(set_attr "type" "sseadd")
531 (set_attr "prefix" "vex")
532 (set_attr "mode" "<avxvecmode>")])
534 (define_expand "<plusminus_insn><mode>3"
535 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
536 (plusminus:SSEMODEF2P
537 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
538 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
539 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
540 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
542 (define_insn "*<plusminus_insn><mode>3"
543 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
544 (plusminus:SSEMODEF2P
545 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "<comm>0")
546 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
547 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
548 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
549 "<plusminus_mnemonic>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
550 [(set_attr "type" "sseadd")
551 (set_attr "mode" "<MODE>")])
553 (define_insn "*avx_vm<plusminus_insn><mode>3"
554 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
555 (vec_merge:SSEMODEF2P
556 (plusminus:SSEMODEF2P
557 (match_operand:SSEMODEF2P 1 "register_operand" "x")
558 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
561 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
562 "v<plusminus_mnemonic>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
563 [(set_attr "type" "sseadd")
564 (set_attr "prefix" "vex")
565 (set_attr "mode" "<ssescalarmode>")])
567 (define_insn "<sse>_vm<plusminus_insn><mode>3"
568 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
569 (vec_merge:SSEMODEF2P
570 (plusminus:SSEMODEF2P
571 (match_operand:SSEMODEF2P 1 "register_operand" "0")
572 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
575 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
576 "<plusminus_mnemonic>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
577 [(set_attr "type" "sseadd")
578 (set_attr "mode" "<ssescalarmode>")])
580 (define_expand "mul<mode>3"
581 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
583 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
584 (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
585 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
586 "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
588 (define_insn "*avx_mul<mode>3"
589 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
591 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
592 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
593 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
594 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
595 "vmulp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
596 [(set_attr "type" "ssemul")
597 (set_attr "prefix" "vex")
598 (set_attr "mode" "<avxvecmode>")])
600 (define_expand "mul<mode>3"
601 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
603 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
604 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
605 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
606 "ix86_fixup_binary_operands_no_copy (MULT, <MODE>mode, operands);")
608 (define_insn "*mul<mode>3"
609 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
611 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
612 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
613 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
614 && ix86_binary_operator_ok (MULT, <MODE>mode, operands)"
615 "mulp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
616 [(set_attr "type" "ssemul")
617 (set_attr "mode" "<MODE>")])
619 (define_insn "*avx_vmmul<mode>3"
620 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
621 (vec_merge:SSEMODEF2P
623 (match_operand:SSEMODEF2P 1 "register_operand" "x")
624 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
627 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
628 "vmuls<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
629 [(set_attr "type" "ssemul")
630 (set_attr "prefix" "vex")
631 (set_attr "mode" "<ssescalarmode>")])
633 (define_insn "<sse>_vmmul<mode>3"
634 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
635 (vec_merge:SSEMODEF2P
637 (match_operand:SSEMODEF2P 1 "register_operand" "0")
638 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
641 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
642 "muls<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
643 [(set_attr "type" "ssemul")
644 (set_attr "mode" "<ssescalarmode>")])
646 (define_expand "divv8sf3"
647 [(set (match_operand:V8SF 0 "register_operand" "")
648 (div:V8SF (match_operand:V8SF 1 "register_operand" "")
649 (match_operand:V8SF 2 "nonimmediate_operand" "")))]
652 ix86_fixup_binary_operands_no_copy (DIV, V8SFmode, operands);
654 if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
655 && flag_finite_math_only && !flag_trapping_math
656 && flag_unsafe_math_optimizations)
658 ix86_emit_swdivsf (operands[0], operands[1],
659 operands[2], V8SFmode);
664 (define_expand "divv4df3"
665 [(set (match_operand:V4DF 0 "register_operand" "")
666 (div:V4DF (match_operand:V4DF 1 "register_operand" "")
667 (match_operand:V4DF 2 "nonimmediate_operand" "")))]
669 "ix86_fixup_binary_operands_no_copy (DIV, V4DFmode, operands);")
671 (define_insn "avx_div<mode>3"
672 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
674 (match_operand:AVXMODEF2P 1 "register_operand" "x")
675 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
676 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
677 "vdivp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
678 [(set_attr "type" "ssediv")
679 (set_attr "prefix" "vex")
680 (set_attr "mode" "<MODE>")])
682 (define_expand "divv4sf3"
683 [(set (match_operand:V4SF 0 "register_operand" "")
684 (div:V4SF (match_operand:V4SF 1 "register_operand" "")
685 (match_operand:V4SF 2 "nonimmediate_operand" "")))]
688 if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
689 && flag_finite_math_only && !flag_trapping_math
690 && flag_unsafe_math_optimizations)
692 ix86_emit_swdivsf (operands[0], operands[1],
693 operands[2], V4SFmode);
698 (define_expand "divv2df3"
699 [(set (match_operand:V2DF 0 "register_operand" "")
700 (div:V2DF (match_operand:V2DF 1 "register_operand" "")
701 (match_operand:V2DF 2 "nonimmediate_operand" "")))]
705 (define_insn "*avx_div<mode>3"
706 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
708 (match_operand:SSEMODEF2P 1 "register_operand" "x")
709 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
710 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
711 "vdivp<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
712 [(set_attr "type" "ssediv")
713 (set_attr "prefix" "vex")
714 (set_attr "mode" "<MODE>")])
716 (define_insn "<sse>_div<mode>3"
717 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
719 (match_operand:SSEMODEF2P 1 "register_operand" "0")
720 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
721 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
722 "divp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
723 [(set_attr "type" "ssediv")
724 (set_attr "mode" "<MODE>")])
726 (define_insn "*avx_vmdiv<mode>3"
727 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
728 (vec_merge:SSEMODEF2P
730 (match_operand:SSEMODEF2P 1 "register_operand" "x")
731 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
734 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
735 "vdivs<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
736 [(set_attr "type" "ssediv")
737 (set_attr "prefix" "vex")
738 (set_attr "mode" "<ssescalarmode>")])
740 (define_insn "<sse>_vmdiv<mode>3"
741 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
742 (vec_merge:SSEMODEF2P
744 (match_operand:SSEMODEF2P 1 "register_operand" "0")
745 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
748 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
749 "divs<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
750 [(set_attr "type" "ssediv")
751 (set_attr "mode" "<ssescalarmode>")])
753 (define_insn "avx_rcpv8sf2"
754 [(set (match_operand:V8SF 0 "register_operand" "=x")
756 [(match_operand:V8SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
758 "vrcpps\t{%1, %0|%0, %1}"
759 [(set_attr "type" "sse")
760 (set_attr "prefix" "vex")
761 (set_attr "mode" "V8SF")])
763 (define_insn "sse_rcpv4sf2"
764 [(set (match_operand:V4SF 0 "register_operand" "=x")
766 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RCP))]
768 "%vrcpps\t{%1, %0|%0, %1}"
769 [(set_attr "type" "sse")
770 (set_attr "atom_sse_attr" "rcp")
771 (set_attr "prefix" "maybe_vex")
772 (set_attr "mode" "V4SF")])
774 (define_insn "*avx_vmrcpv4sf2"
775 [(set (match_operand:V4SF 0 "register_operand" "=x")
777 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
779 (match_operand:V4SF 2 "register_operand" "x")
782 "vrcpss\t{%1, %2, %0|%0, %2, %1}"
783 [(set_attr "type" "sse")
784 (set_attr "prefix" "vex")
785 (set_attr "mode" "SF")])
787 (define_insn "sse_vmrcpv4sf2"
788 [(set (match_operand:V4SF 0 "register_operand" "=x")
790 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
792 (match_operand:V4SF 2 "register_operand" "0")
795 "rcpss\t{%1, %0|%0, %1}"
796 [(set_attr "type" "sse")
797 (set_attr "atom_sse_attr" "rcp")
798 (set_attr "mode" "SF")])
800 (define_expand "sqrtv8sf2"
801 [(set (match_operand:V8SF 0 "register_operand" "")
802 (sqrt:V8SF (match_operand:V8SF 1 "nonimmediate_operand" "")))]
805 if (TARGET_SSE_MATH && TARGET_RECIP && !optimize_insn_for_size_p ()
806 && flag_finite_math_only && !flag_trapping_math
807 && flag_unsafe_math_optimizations)
809 ix86_emit_swsqrtsf (operands[0], operands[1], V8SFmode, 0);
814 (define_insn "avx_sqrtv8sf2"
815 [(set (match_operand:V8SF 0 "register_operand" "=x")
816 (sqrt:V8SF (match_operand:V8SF 1 "nonimmediate_operand" "xm")))]
818 "vsqrtps\t{%1, %0|%0, %1}"
819 [(set_attr "type" "sse")
820 (set_attr "prefix" "vex")
821 (set_attr "mode" "V8SF")])
823 (define_expand "sqrtv4sf2"
824 [(set (match_operand:V4SF 0 "register_operand" "")
825 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "")))]
828 if (TARGET_SSE_MATH && TARGET_RECIP && optimize_insn_for_speed_p ()
829 && flag_finite_math_only && !flag_trapping_math
830 && flag_unsafe_math_optimizations)
832 ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 0);
837 (define_insn "sse_sqrtv4sf2"
838 [(set (match_operand:V4SF 0 "register_operand" "=x")
839 (sqrt:V4SF (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
841 "%vsqrtps\t{%1, %0|%0, %1}"
842 [(set_attr "type" "sse")
843 (set_attr "atom_sse_attr" "sqrt")
844 (set_attr "prefix" "maybe_vex")
845 (set_attr "mode" "V4SF")])
847 (define_insn "sqrtv4df2"
848 [(set (match_operand:V4DF 0 "register_operand" "=x")
849 (sqrt:V4DF (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
851 "vsqrtpd\t{%1, %0|%0, %1}"
852 [(set_attr "type" "sse")
853 (set_attr "prefix" "vex")
854 (set_attr "mode" "V4DF")])
856 (define_insn "sqrtv2df2"
857 [(set (match_operand:V2DF 0 "register_operand" "=x")
858 (sqrt:V2DF (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
860 "%vsqrtpd\t{%1, %0|%0, %1}"
861 [(set_attr "type" "sse")
862 (set_attr "prefix" "maybe_vex")
863 (set_attr "mode" "V2DF")])
865 (define_insn "*avx_vmsqrt<mode>2"
866 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
867 (vec_merge:SSEMODEF2P
869 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm"))
870 (match_operand:SSEMODEF2P 2 "register_operand" "x")
872 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
873 "vsqrts<ssemodesuffixf2c>\t{%1, %2, %0|%0, %2, %1}"
874 [(set_attr "type" "sse")
875 (set_attr "prefix" "vex")
876 (set_attr "mode" "<ssescalarmode>")])
878 (define_insn "<sse>_vmsqrt<mode>2"
879 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
880 (vec_merge:SSEMODEF2P
882 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm"))
883 (match_operand:SSEMODEF2P 2 "register_operand" "0")
885 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
886 "sqrts<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
887 [(set_attr "type" "sse")
888 (set_attr "atom_sse_attr" "sqrt")
889 (set_attr "mode" "<ssescalarmode>")])
891 (define_expand "rsqrtv8sf2"
892 [(set (match_operand:V8SF 0 "register_operand" "")
894 [(match_operand:V8SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
895 "TARGET_AVX && TARGET_SSE_MATH"
897 ix86_emit_swsqrtsf (operands[0], operands[1], V8SFmode, 1);
901 (define_insn "avx_rsqrtv8sf2"
902 [(set (match_operand:V8SF 0 "register_operand" "=x")
904 [(match_operand:V8SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
906 "vrsqrtps\t{%1, %0|%0, %1}"
907 [(set_attr "type" "sse")
908 (set_attr "prefix" "vex")
909 (set_attr "mode" "V8SF")])
911 (define_expand "rsqrtv4sf2"
912 [(set (match_operand:V4SF 0 "register_operand" "")
914 [(match_operand:V4SF 1 "nonimmediate_operand" "")] UNSPEC_RSQRT))]
917 ix86_emit_swsqrtsf (operands[0], operands[1], V4SFmode, 1);
921 (define_insn "sse_rsqrtv4sf2"
922 [(set (match_operand:V4SF 0 "register_operand" "=x")
924 [(match_operand:V4SF 1 "nonimmediate_operand" "xm")] UNSPEC_RSQRT))]
926 "%vrsqrtps\t{%1, %0|%0, %1}"
927 [(set_attr "type" "sse")
928 (set_attr "prefix" "maybe_vex")
929 (set_attr "mode" "V4SF")])
931 (define_insn "*avx_vmrsqrtv4sf2"
932 [(set (match_operand:V4SF 0 "register_operand" "=x")
934 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
936 (match_operand:V4SF 2 "register_operand" "x")
939 "vrsqrtss\t{%1, %2, %0|%0, %2, %1}"
940 [(set_attr "type" "sse")
941 (set_attr "prefix" "vex")
942 (set_attr "mode" "SF")])
944 (define_insn "sse_vmrsqrtv4sf2"
945 [(set (match_operand:V4SF 0 "register_operand" "=x")
947 (unspec:V4SF [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
949 (match_operand:V4SF 2 "register_operand" "0")
952 "rsqrtss\t{%1, %0|%0, %1}"
953 [(set_attr "type" "sse")
954 (set_attr "mode" "SF")])
956 ;; ??? For !flag_finite_math_only, the representation with SMIN/SMAX
957 ;; isn't really correct, as those rtl operators aren't defined when
958 ;; applied to NaNs. Hopefully the optimizers won't get too smart on us.
960 (define_expand "<code><mode>3"
961 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
962 (smaxmin:AVX256MODEF2P
963 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
964 (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
965 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
967 if (!flag_finite_math_only)
968 operands[1] = force_reg (<MODE>mode, operands[1]);
969 ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
972 (define_expand "<code><mode>3"
973 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
975 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
976 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
977 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
979 if (!flag_finite_math_only)
980 operands[1] = force_reg (<MODE>mode, operands[1]);
981 ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);
984 (define_insn "*avx_<code><mode>3_finite"
985 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
987 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
988 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
989 "AVX_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
990 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
991 "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
992 [(set_attr "type" "sseadd")
993 (set_attr "prefix" "vex")
994 (set_attr "mode" "<MODE>")])
996 (define_insn "*<code><mode>3_finite"
997 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
999 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
1000 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1001 "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && flag_finite_math_only
1002 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1003 "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1004 [(set_attr "type" "sseadd")
1005 (set_attr "mode" "<MODE>")])
1007 (define_insn "*avx_<code><mode>3"
1008 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1010 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
1011 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1012 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1013 "v<maxminfprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1014 [(set_attr "type" "sseadd")
1015 (set_attr "prefix" "vex")
1016 (set_attr "mode" "<avxvecmode>")])
1018 (define_insn "*<code><mode>3"
1019 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1021 (match_operand:SSEMODEF2P 1 "register_operand" "0")
1022 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1023 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1024 "<maxminfprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1025 [(set_attr "type" "sseadd")
1026 (set_attr "mode" "<MODE>")])
1028 (define_insn "*avx_vm<code><mode>3"
1029 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1030 (vec_merge:SSEMODEF2P
1032 (match_operand:SSEMODEF2P 1 "register_operand" "x")
1033 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
1036 "AVX128_VEC_FLOAT_MODE_P (<MODE>mode)"
1037 "v<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1038 [(set_attr "type" "sse")
1039 (set_attr "prefix" "vex")
1040 (set_attr "mode" "<ssescalarmode>")])
1042 (define_insn "<sse>_vm<code><mode>3"
1043 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1044 (vec_merge:SSEMODEF2P
1046 (match_operand:SSEMODEF2P 1 "register_operand" "0")
1047 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm"))
1050 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1051 "<maxminfprefix>s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1052 [(set_attr "type" "sseadd")
1053 (set_attr "mode" "<ssescalarmode>")])
1055 ;; These versions of the min/max patterns implement exactly the operations
1056 ;; min = (op1 < op2 ? op1 : op2)
1057 ;; max = (!(op1 < op2) ? op1 : op2)
1058 ;; Their operands are not commutative, and thus they may be used in the
1059 ;; presence of -0.0 and NaN.
1061 (define_insn "*avx_ieee_smin<mode>3"
1062 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1064 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
1065 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]
1067 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1068 "vminp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1069 [(set_attr "type" "sseadd")
1070 (set_attr "prefix" "vex")
1071 (set_attr "mode" "<avxvecmode>")])
1073 (define_insn "*avx_ieee_smax<mode>3"
1074 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1076 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
1077 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]
1079 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1080 "vmaxp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1081 [(set_attr "type" "sseadd")
1082 (set_attr "prefix" "vex")
1083 (set_attr "mode" "<avxvecmode>")])
1085 (define_insn "*ieee_smin<mode>3"
1086 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1088 [(match_operand:SSEMODEF2P 1 "register_operand" "0")
1089 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]
1091 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1092 "minp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1093 [(set_attr "type" "sseadd")
1094 (set_attr "mode" "<MODE>")])
1096 (define_insn "*ieee_smax<mode>3"
1097 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1099 [(match_operand:SSEMODEF2P 1 "register_operand" "0")
1100 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]
1102 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1103 "maxp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1104 [(set_attr "type" "sseadd")
1105 (set_attr "mode" "<MODE>")])
1107 (define_insn "avx_addsubv8sf3"
1108 [(set (match_operand:V8SF 0 "register_operand" "=x")
1111 (match_operand:V8SF 1 "register_operand" "x")
1112 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
1113 (minus:V8SF (match_dup 1) (match_dup 2))
1116 "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
1117 [(set_attr "type" "sseadd")
1118 (set_attr "prefix" "vex")
1119 (set_attr "mode" "V8SF")])
1121 (define_insn "avx_addsubv4df3"
1122 [(set (match_operand:V4DF 0 "register_operand" "=x")
1125 (match_operand:V4DF 1 "register_operand" "x")
1126 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
1127 (minus:V4DF (match_dup 1) (match_dup 2))
1130 "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
1131 [(set_attr "type" "sseadd")
1132 (set_attr "prefix" "vex")
1133 (set_attr "mode" "V4DF")])
1135 (define_insn "*avx_addsubv4sf3"
1136 [(set (match_operand:V4SF 0 "register_operand" "=x")
1139 (match_operand:V4SF 1 "register_operand" "x")
1140 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
1141 (minus:V4SF (match_dup 1) (match_dup 2))
1144 "vaddsubps\t{%2, %1, %0|%0, %1, %2}"
1145 [(set_attr "type" "sseadd")
1146 (set_attr "prefix" "vex")
1147 (set_attr "mode" "V4SF")])
1149 (define_insn "sse3_addsubv4sf3"
1150 [(set (match_operand:V4SF 0 "register_operand" "=x")
1153 (match_operand:V4SF 1 "register_operand" "0")
1154 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
1155 (minus:V4SF (match_dup 1) (match_dup 2))
1158 "addsubps\t{%2, %0|%0, %2}"
1159 [(set_attr "type" "sseadd")
1160 (set_attr "prefix_rep" "1")
1161 (set_attr "mode" "V4SF")])
1163 (define_insn "*avx_addsubv2df3"
1164 [(set (match_operand:V2DF 0 "register_operand" "=x")
1167 (match_operand:V2DF 1 "register_operand" "x")
1168 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1169 (minus:V2DF (match_dup 1) (match_dup 2))
1172 "vaddsubpd\t{%2, %1, %0|%0, %1, %2}"
1173 [(set_attr "type" "sseadd")
1174 (set_attr "prefix" "vex")
1175 (set_attr "mode" "V2DF")])
1177 (define_insn "sse3_addsubv2df3"
1178 [(set (match_operand:V2DF 0 "register_operand" "=x")
1181 (match_operand:V2DF 1 "register_operand" "0")
1182 (match_operand:V2DF 2 "nonimmediate_operand" "xm"))
1183 (minus:V2DF (match_dup 1) (match_dup 2))
1186 "addsubpd\t{%2, %0|%0, %2}"
1187 [(set_attr "type" "sseadd")
1188 (set_attr "atom_unit" "complex")
1189 (set_attr "mode" "V2DF")])
1191 (define_insn "avx_h<plusminus_insn>v4df3"
1192 [(set (match_operand:V4DF 0 "register_operand" "=x")
1197 (match_operand:V4DF 1 "register_operand" "x")
1198 (parallel [(const_int 0)]))
1199 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1201 (vec_select:DF (match_dup 1) (parallel [(const_int 2)]))
1202 (vec_select:DF (match_dup 1) (parallel [(const_int 3)]))))
1206 (match_operand:V4DF 2 "nonimmediate_operand" "xm")
1207 (parallel [(const_int 0)]))
1208 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))
1210 (vec_select:DF (match_dup 2) (parallel [(const_int 2)]))
1211 (vec_select:DF (match_dup 2) (parallel [(const_int 3)]))))))]
1213 "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
1214 [(set_attr "type" "sseadd")
1215 (set_attr "prefix" "vex")
1216 (set_attr "mode" "V4DF")])
1218 (define_insn "avx_h<plusminus_insn>v8sf3"
1219 [(set (match_operand:V8SF 0 "register_operand" "=x")
1225 (match_operand:V8SF 1 "register_operand" "x")
1226 (parallel [(const_int 0)]))
1227 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1229 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
1230 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
1234 (match_operand:V8SF 2 "nonimmediate_operand" "xm")
1235 (parallel [(const_int 0)]))
1236 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
1238 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
1239 (vec_select:SF (match_dup 2) (parallel [(const_int 3)])))))
1243 (vec_select:SF (match_dup 1) (parallel [(const_int 4)]))
1244 (vec_select:SF (match_dup 1) (parallel [(const_int 5)])))
1246 (vec_select:SF (match_dup 1) (parallel [(const_int 6)]))
1247 (vec_select:SF (match_dup 1) (parallel [(const_int 7)]))))
1250 (vec_select:SF (match_dup 2) (parallel [(const_int 4)]))
1251 (vec_select:SF (match_dup 2) (parallel [(const_int 5)])))
1253 (vec_select:SF (match_dup 2) (parallel [(const_int 6)]))
1254 (vec_select:SF (match_dup 2) (parallel [(const_int 7)])))))))]
1256 "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
1257 [(set_attr "type" "sseadd")
1258 (set_attr "prefix" "vex")
1259 (set_attr "mode" "V8SF")])
1261 (define_insn "*avx_h<plusminus_insn>v4sf3"
1262 [(set (match_operand:V4SF 0 "register_operand" "=x")
1267 (match_operand:V4SF 1 "register_operand" "x")
1268 (parallel [(const_int 0)]))
1269 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1271 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
1272 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
1276 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
1277 (parallel [(const_int 0)]))
1278 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
1280 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
1281 (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
1283 "vh<plusminus_mnemonic>ps\t{%2, %1, %0|%0, %1, %2}"
1284 [(set_attr "type" "sseadd")
1285 (set_attr "prefix" "vex")
1286 (set_attr "mode" "V4SF")])
1288 (define_insn "sse3_h<plusminus_insn>v4sf3"
1289 [(set (match_operand:V4SF 0 "register_operand" "=x")
1294 (match_operand:V4SF 1 "register_operand" "0")
1295 (parallel [(const_int 0)]))
1296 (vec_select:SF (match_dup 1) (parallel [(const_int 1)])))
1298 (vec_select:SF (match_dup 1) (parallel [(const_int 2)]))
1299 (vec_select:SF (match_dup 1) (parallel [(const_int 3)]))))
1303 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
1304 (parallel [(const_int 0)]))
1305 (vec_select:SF (match_dup 2) (parallel [(const_int 1)])))
1307 (vec_select:SF (match_dup 2) (parallel [(const_int 2)]))
1308 (vec_select:SF (match_dup 2) (parallel [(const_int 3)]))))))]
1310 "h<plusminus_mnemonic>ps\t{%2, %0|%0, %2}"
1311 [(set_attr "type" "sseadd")
1312 (set_attr "atom_unit" "complex")
1313 (set_attr "prefix_rep" "1")
1314 (set_attr "mode" "V4SF")])
1316 (define_insn "*avx_h<plusminus_insn>v2df3"
1317 [(set (match_operand:V2DF 0 "register_operand" "=x")
1321 (match_operand:V2DF 1 "register_operand" "x")
1322 (parallel [(const_int 0)]))
1323 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1326 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
1327 (parallel [(const_int 0)]))
1328 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
1330 "vh<plusminus_mnemonic>pd\t{%2, %1, %0|%0, %1, %2}"
1331 [(set_attr "type" "sseadd")
1332 (set_attr "prefix" "vex")
1333 (set_attr "mode" "V2DF")])
1335 (define_insn "sse3_h<plusminus_insn>v2df3"
1336 [(set (match_operand:V2DF 0 "register_operand" "=x")
1340 (match_operand:V2DF 1 "register_operand" "0")
1341 (parallel [(const_int 0)]))
1342 (vec_select:DF (match_dup 1) (parallel [(const_int 1)])))
1345 (match_operand:V2DF 2 "nonimmediate_operand" "xm")
1346 (parallel [(const_int 0)]))
1347 (vec_select:DF (match_dup 2) (parallel [(const_int 1)])))))]
1349 "h<plusminus_mnemonic>pd\t{%2, %0|%0, %2}"
1350 [(set_attr "type" "sseadd")
1351 (set_attr "mode" "V2DF")])
1353 (define_expand "reduc_splus_v4sf"
1354 [(match_operand:V4SF 0 "register_operand" "")
1355 (match_operand:V4SF 1 "register_operand" "")]
1360 rtx tmp = gen_reg_rtx (V4SFmode);
1361 emit_insn (gen_sse3_haddv4sf3 (tmp, operands[1], operands[1]));
1362 emit_insn (gen_sse3_haddv4sf3 (operands[0], tmp, tmp));
1365 ix86_expand_reduc_v4sf (gen_addv4sf3, operands[0], operands[1]);
1369 (define_expand "reduc_splus_v2df"
1370 [(match_operand:V2DF 0 "register_operand" "")
1371 (match_operand:V2DF 1 "register_operand" "")]
1374 emit_insn (gen_sse3_haddv2df3 (operands[0], operands[1], operands[1]));
1378 (define_expand "reduc_smax_v4sf"
1379 [(match_operand:V4SF 0 "register_operand" "")
1380 (match_operand:V4SF 1 "register_operand" "")]
1383 ix86_expand_reduc_v4sf (gen_smaxv4sf3, operands[0], operands[1]);
1387 (define_expand "reduc_smin_v4sf"
1388 [(match_operand:V4SF 0 "register_operand" "")
1389 (match_operand:V4SF 1 "register_operand" "")]
1392 ix86_expand_reduc_v4sf (gen_sminv4sf3, operands[0], operands[1]);
1396 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1398 ;; Parallel floating point comparisons
1400 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1402 (define_insn "avx_cmpp<avxmodesuffixf2c><mode>3"
1403 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1405 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
1406 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
1407 (match_operand:SI 3 "const_0_to_31_operand" "n")]
1410 "vcmpp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1411 [(set_attr "type" "ssecmp")
1412 (set_attr "length_immediate" "1")
1413 (set_attr "prefix" "vex")
1414 (set_attr "mode" "<MODE>")])
1416 (define_insn "avx_cmps<ssemodesuffixf2c><mode>3"
1417 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
1418 (vec_merge:SSEMODEF2P
1420 [(match_operand:SSEMODEF2P 1 "register_operand" "x")
1421 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
1422 (match_operand:SI 3 "const_0_to_31_operand" "n")]
1427 "vcmps<ssemodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
1428 [(set_attr "type" "ssecmp")
1429 (set_attr "length_immediate" "1")
1430 (set_attr "prefix" "vex")
1431 (set_attr "mode" "<ssescalarmode>")])
1433 ;; We don't promote 128bit vector compare intrinsics. But vectorizer
1434 ;; may generate 256bit vector compare instructions.
1435 (define_insn "*avx_maskcmp<mode>3"
1436 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1437 (match_operator:AVXMODEF2P 3 "avx_comparison_float_operator"
1438 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
1439 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")]))]
1440 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1441 "vcmp%D3p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1442 [(set_attr "type" "ssecmp")
1443 (set_attr "prefix" "vex")
1444 (set_attr "length_immediate" "1")
1445 (set_attr "mode" "<avxvecmode>")])
1447 (define_insn "<sse>_maskcmp<mode>3"
1448 [(set (match_operand:SSEMODEF4 0 "register_operand" "=x")
1449 (match_operator:SSEMODEF4 3 "sse_comparison_operator"
1450 [(match_operand:SSEMODEF4 1 "register_operand" "0")
1451 (match_operand:SSEMODEF4 2 "nonimmediate_operand" "xm")]))]
1452 "(SSE_FLOAT_MODE_P (<MODE>mode) || SSE_VEC_FLOAT_MODE_P (<MODE>mode))"
1453 "cmp%D3<ssemodesuffixf4>\t{%2, %0|%0, %2}"
1454 [(set_attr "type" "ssecmp")
1455 (set_attr "length_immediate" "1")
1456 (set_attr "mode" "<MODE>")])
1458 (define_insn "<sse>_vmmaskcmp<mode>3"
1459 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1460 (vec_merge:SSEMODEF2P
1461 (match_operator:SSEMODEF2P 3 "sse_comparison_operator"
1462 [(match_operand:SSEMODEF2P 1 "register_operand" "0")
1463 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")])
1466 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1467 "cmp%D3s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1468 [(set_attr "type" "ssecmp")
1469 (set_attr "length_immediate" "1")
1470 (set_attr "mode" "<ssescalarmode>")])
1472 (define_insn "<sse>_comi"
1473 [(set (reg:CCFP FLAGS_REG)
1476 (match_operand:<ssevecmode> 0 "register_operand" "x")
1477 (parallel [(const_int 0)]))
1479 (match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm")
1480 (parallel [(const_int 0)]))))]
1481 "SSE_FLOAT_MODE_P (<MODE>mode)"
1482 "%vcomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
1483 [(set_attr "type" "ssecomi")
1484 (set_attr "prefix" "maybe_vex")
1485 (set_attr "prefix_rep" "0")
1486 (set (attr "prefix_data16")
1487 (if_then_else (eq_attr "mode" "DF")
1489 (const_string "0")))
1490 (set_attr "mode" "<MODE>")])
1492 (define_insn "<sse>_ucomi"
1493 [(set (reg:CCFPU FLAGS_REG)
1496 (match_operand:<ssevecmode> 0 "register_operand" "x")
1497 (parallel [(const_int 0)]))
1499 (match_operand:<ssevecmode> 1 "nonimmediate_operand" "xm")
1500 (parallel [(const_int 0)]))))]
1501 "SSE_FLOAT_MODE_P (<MODE>mode)"
1502 "%vucomis<ssemodefsuffix>\t{%1, %0|%0, %1}"
1503 [(set_attr "type" "ssecomi")
1504 (set_attr "prefix" "maybe_vex")
1505 (set_attr "prefix_rep" "0")
1506 (set (attr "prefix_data16")
1507 (if_then_else (eq_attr "mode" "DF")
1509 (const_string "0")))
1510 (set_attr "mode" "<MODE>")])
1512 (define_expand "vcond<mode>"
1513 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
1514 (if_then_else:SSEMODEF2P
1515 (match_operator 3 ""
1516 [(match_operand:SSEMODEF2P 4 "nonimmediate_operand" "")
1517 (match_operand:SSEMODEF2P 5 "nonimmediate_operand" "")])
1518 (match_operand:SSEMODEF2P 1 "general_operand" "")
1519 (match_operand:SSEMODEF2P 2 "general_operand" "")))]
1520 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1522 bool ok = ix86_expand_fp_vcond (operands);
1527 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1529 ;; Parallel floating point logical operations
1531 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1533 (define_insn "avx_andnot<mode>3"
1534 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1537 (match_operand:AVXMODEF2P 1 "register_operand" "x"))
1538 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1539 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)"
1540 "vandnp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1541 [(set_attr "type" "sselog")
1542 (set_attr "prefix" "vex")
1543 (set_attr "mode" "<avxvecmode>")])
1545 (define_insn "<sse>_andnot<mode>3"
1546 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1549 (match_operand:SSEMODEF2P 1 "register_operand" "0"))
1550 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1551 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1552 "andnp<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1553 [(set_attr "type" "sselog")
1554 (set_attr "mode" "<MODE>")])
1556 (define_expand "<code><mode>3"
1557 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "")
1558 (plogic:AVX256MODEF2P
1559 (match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "")
1560 (match_operand:AVX256MODEF2P 2 "nonimmediate_operand" "")))]
1561 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
1562 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
1564 (define_insn "*avx_<code><mode>3"
1565 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
1567 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
1568 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")))]
1569 "AVX_VEC_FLOAT_MODE_P (<MODE>mode)
1570 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1571 "v<plogicprefix>p<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
1572 [(set_attr "type" "sselog")
1573 (set_attr "prefix" "vex")
1574 (set_attr "mode" "<avxvecmode>")])
1576 (define_expand "<code><mode>3"
1577 [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
1579 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")
1580 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))]
1581 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1582 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
1584 (define_insn "*<code><mode>3"
1585 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
1587 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
1588 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")))]
1589 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)
1590 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
1591 "<plogicprefix>p<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
1592 [(set_attr "type" "sselog")
1593 (set_attr "mode" "<MODE>")])
1595 (define_expand "copysign<mode>3"
1598 (not:SSEMODEF2P (match_dup 3))
1599 (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "")))
1601 (and:SSEMODEF2P (match_dup 3)
1602 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "")))
1603 (set (match_operand:SSEMODEF2P 0 "register_operand" "")
1604 (ior:SSEMODEF2P (match_dup 4) (match_dup 5)))]
1605 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
1607 operands[3] = ix86_build_signbit_mask (<ssescalarmode>mode, 1, 0);
1609 operands[4] = gen_reg_rtx (<MODE>mode);
1610 operands[5] = gen_reg_rtx (<MODE>mode);
1613 ;; Also define scalar versions. These are used for abs, neg, and
1614 ;; conditional move. Using subregs into vector modes causes register
1615 ;; allocation lossage. These patterns do not allow memory operands
1616 ;; because the native instructions read the full 128-bits.
1618 (define_insn "*avx_andnot<mode>3"
1619 [(set (match_operand:MODEF 0 "register_operand" "=x")
1622 (match_operand:MODEF 1 "register_operand" "x"))
1623 (match_operand:MODEF 2 "register_operand" "x")))]
1624 "AVX_FLOAT_MODE_P (<MODE>mode)"
1625 "vandnp<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
1626 [(set_attr "type" "sselog")
1627 (set_attr "prefix" "vex")
1628 (set_attr "mode" "<ssevecmode>")])
1630 (define_insn "*andnot<mode>3"
1631 [(set (match_operand:MODEF 0 "register_operand" "=x")
1634 (match_operand:MODEF 1 "register_operand" "0"))
1635 (match_operand:MODEF 2 "register_operand" "x")))]
1636 "SSE_FLOAT_MODE_P (<MODE>mode)"
1637 "andnp<ssemodefsuffix>\t{%2, %0|%0, %2}"
1638 [(set_attr "type" "sselog")
1639 (set_attr "mode" "<ssevecmode>")])
1641 (define_insn "*avx_<code><mode>3"
1642 [(set (match_operand:MODEF 0 "register_operand" "=x")
1644 (match_operand:MODEF 1 "register_operand" "x")
1645 (match_operand:MODEF 2 "register_operand" "x")))]
1646 "AVX_FLOAT_MODE_P (<MODE>mode)"
1647 "v<plogicprefix>p<ssemodefsuffix>\t{%2, %1, %0|%0, %1, %2}"
1648 [(set_attr "type" "sselog")
1649 (set_attr "prefix" "vex")
1650 (set_attr "mode" "<ssevecmode>")])
1652 (define_insn "*<code><mode>3"
1653 [(set (match_operand:MODEF 0 "register_operand" "=x")
1655 (match_operand:MODEF 1 "register_operand" "0")
1656 (match_operand:MODEF 2 "register_operand" "x")))]
1657 "SSE_FLOAT_MODE_P (<MODE>mode)"
1658 "<plogicprefix>p<ssemodefsuffix>\t{%2, %0|%0, %2}"
1659 [(set_attr "type" "sselog")
1660 (set_attr "mode" "<ssevecmode>")])
1662 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1664 ;; Parallel single-precision floating point conversion operations
1666 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1668 (define_insn "sse_cvtpi2ps"
1669 [(set (match_operand:V4SF 0 "register_operand" "=x")
1672 (float:V2SF (match_operand:V2SI 2 "nonimmediate_operand" "ym")))
1673 (match_operand:V4SF 1 "register_operand" "0")
1676 "cvtpi2ps\t{%2, %0|%0, %2}"
1677 [(set_attr "type" "ssecvt")
1678 (set_attr "mode" "V4SF")])
1680 (define_insn "sse_cvtps2pi"
1681 [(set (match_operand:V2SI 0 "register_operand" "=y")
1683 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
1685 (parallel [(const_int 0) (const_int 1)])))]
1687 "cvtps2pi\t{%1, %0|%0, %1}"
1688 [(set_attr "type" "ssecvt")
1689 (set_attr "unit" "mmx")
1690 (set_attr "mode" "DI")])
1692 (define_insn "sse_cvttps2pi"
1693 [(set (match_operand:V2SI 0 "register_operand" "=y")
1695 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm"))
1696 (parallel [(const_int 0) (const_int 1)])))]
1698 "cvttps2pi\t{%1, %0|%0, %1}"
1699 [(set_attr "type" "ssecvt")
1700 (set_attr "unit" "mmx")
1701 (set_attr "prefix_rep" "0")
1702 (set_attr "mode" "SF")])
1704 (define_insn "*avx_cvtsi2ss"
1705 [(set (match_operand:V4SF 0 "register_operand" "=x")
1708 (float:SF (match_operand:SI 2 "nonimmediate_operand" "rm")))
1709 (match_operand:V4SF 1 "register_operand" "x")
1712 "vcvtsi2ss\t{%2, %1, %0|%0, %1, %2}"
1713 [(set_attr "type" "sseicvt")
1714 (set_attr "prefix" "vex")
1715 (set_attr "mode" "SF")])
1717 (define_insn "sse_cvtsi2ss"
1718 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
1721 (float:SF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
1722 (match_operand:V4SF 1 "register_operand" "0,0")
1725 "cvtsi2ss\t{%2, %0|%0, %2}"
1726 [(set_attr "type" "sseicvt")
1727 (set_attr "athlon_decode" "vector,double")
1728 (set_attr "amdfam10_decode" "vector,double")
1729 (set_attr "mode" "SF")])
1731 (define_insn "*avx_cvtsi2ssq"
1732 [(set (match_operand:V4SF 0 "register_operand" "=x")
1735 (float:SF (match_operand:DI 2 "nonimmediate_operand" "rm")))
1736 (match_operand:V4SF 1 "register_operand" "x")
1738 "TARGET_AVX && TARGET_64BIT"
1739 "vcvtsi2ssq\t{%2, %1, %0|%0, %1, %2}"
1740 [(set_attr "type" "sseicvt")
1741 (set_attr "length_vex" "4")
1742 (set_attr "prefix" "vex")
1743 (set_attr "mode" "SF")])
1745 (define_insn "sse_cvtsi2ssq"
1746 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
1749 (float:SF (match_operand:DI 2 "nonimmediate_operand" "r,rm")))
1750 (match_operand:V4SF 1 "register_operand" "0,0")
1752 "TARGET_SSE && TARGET_64BIT"
1753 "cvtsi2ssq\t{%2, %0|%0, %2}"
1754 [(set_attr "type" "sseicvt")
1755 (set_attr "prefix_rex" "1")
1756 (set_attr "athlon_decode" "vector,double")
1757 (set_attr "amdfam10_decode" "vector,double")
1758 (set_attr "mode" "SF")])
1760 (define_insn "sse_cvtss2si"
1761 [(set (match_operand:SI 0 "register_operand" "=r,r")
1764 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
1765 (parallel [(const_int 0)]))]
1766 UNSPEC_FIX_NOTRUNC))]
1768 "%vcvtss2si\t{%1, %0|%0, %1}"
1769 [(set_attr "type" "sseicvt")
1770 (set_attr "athlon_decode" "double,vector")
1771 (set_attr "prefix_rep" "1")
1772 (set_attr "prefix" "maybe_vex")
1773 (set_attr "mode" "SI")])
1775 (define_insn "sse_cvtss2si_2"
1776 [(set (match_operand:SI 0 "register_operand" "=r,r")
1777 (unspec:SI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
1778 UNSPEC_FIX_NOTRUNC))]
1780 "%vcvtss2si\t{%1, %0|%0, %1}"
1781 [(set_attr "type" "sseicvt")
1782 (set_attr "athlon_decode" "double,vector")
1783 (set_attr "amdfam10_decode" "double,double")
1784 (set_attr "prefix_rep" "1")
1785 (set_attr "prefix" "maybe_vex")
1786 (set_attr "mode" "SI")])
1788 (define_insn "sse_cvtss2siq"
1789 [(set (match_operand:DI 0 "register_operand" "=r,r")
1792 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
1793 (parallel [(const_int 0)]))]
1794 UNSPEC_FIX_NOTRUNC))]
1795 "TARGET_SSE && TARGET_64BIT"
1796 "%vcvtss2siq\t{%1, %0|%0, %1}"
1797 [(set_attr "type" "sseicvt")
1798 (set_attr "athlon_decode" "double,vector")
1799 (set_attr "prefix_rep" "1")
1800 (set_attr "prefix" "maybe_vex")
1801 (set_attr "mode" "DI")])
1803 (define_insn "sse_cvtss2siq_2"
1804 [(set (match_operand:DI 0 "register_operand" "=r,r")
1805 (unspec:DI [(match_operand:SF 1 "nonimmediate_operand" "x,m")]
1806 UNSPEC_FIX_NOTRUNC))]
1807 "TARGET_SSE && TARGET_64BIT"
1808 "%vcvtss2siq\t{%1, %0|%0, %1}"
1809 [(set_attr "type" "sseicvt")
1810 (set_attr "athlon_decode" "double,vector")
1811 (set_attr "amdfam10_decode" "double,double")
1812 (set_attr "prefix_rep" "1")
1813 (set_attr "prefix" "maybe_vex")
1814 (set_attr "mode" "DI")])
1816 (define_insn "sse_cvttss2si"
1817 [(set (match_operand:SI 0 "register_operand" "=r,r")
1820 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
1821 (parallel [(const_int 0)]))))]
1823 "%vcvttss2si\t{%1, %0|%0, %1}"
1824 [(set_attr "type" "sseicvt")
1825 (set_attr "athlon_decode" "double,vector")
1826 (set_attr "amdfam10_decode" "double,double")
1827 (set_attr "prefix_rep" "1")
1828 (set_attr "prefix" "maybe_vex")
1829 (set_attr "mode" "SI")])
1831 (define_insn "sse_cvttss2siq"
1832 [(set (match_operand:DI 0 "register_operand" "=r,r")
1835 (match_operand:V4SF 1 "nonimmediate_operand" "x,m")
1836 (parallel [(const_int 0)]))))]
1837 "TARGET_SSE && TARGET_64BIT"
1838 "%vcvttss2siq\t{%1, %0|%0, %1}"
1839 [(set_attr "type" "sseicvt")
1840 (set_attr "athlon_decode" "double,vector")
1841 (set_attr "amdfam10_decode" "double,double")
1842 (set_attr "prefix_rep" "1")
1843 (set_attr "prefix" "maybe_vex")
1844 (set_attr "mode" "DI")])
1846 (define_insn "avx_cvtdq2ps<avxmodesuffix>"
1847 [(set (match_operand:AVXMODEDCVTDQ2PS 0 "register_operand" "=x")
1848 (float:AVXMODEDCVTDQ2PS
1849 (match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")))]
1851 "vcvtdq2ps\t{%1, %0|%0, %1}"
1852 [(set_attr "type" "ssecvt")
1853 (set_attr "prefix" "vex")
1854 (set_attr "mode" "<avxvecmode>")])
1856 (define_insn "sse2_cvtdq2ps"
1857 [(set (match_operand:V4SF 0 "register_operand" "=x")
1858 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
1860 "cvtdq2ps\t{%1, %0|%0, %1}"
1861 [(set_attr "type" "ssecvt")
1862 (set_attr "mode" "V4SF")])
1864 (define_expand "sse2_cvtudq2ps"
1866 (float:V4SF (match_operand:V4SI 1 "nonimmediate_operand" "")))
1868 (lt:V4SF (match_dup 5) (match_dup 3)))
1870 (and:V4SF (match_dup 6) (match_dup 4)))
1871 (set (match_operand:V4SF 0 "register_operand" "")
1872 (plus:V4SF (match_dup 5) (match_dup 7)))]
1875 REAL_VALUE_TYPE TWO32r;
1879 real_ldexp (&TWO32r, &dconst1, 32);
1880 x = const_double_from_real_value (TWO32r, SFmode);
1882 operands[3] = force_reg (V4SFmode, CONST0_RTX (V4SFmode));
1883 operands[4] = force_reg (V4SFmode, ix86_build_const_vector (SFmode, 1, x));
1885 for (i = 5; i < 8; i++)
1886 operands[i] = gen_reg_rtx (V4SFmode);
1889 (define_insn "avx_cvtps2dq<avxmodesuffix>"
1890 [(set (match_operand:AVXMODEDCVTPS2DQ 0 "register_operand" "=x")
1891 (unspec:AVXMODEDCVTPS2DQ
1892 [(match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")]
1893 UNSPEC_FIX_NOTRUNC))]
1895 "vcvtps2dq\t{%1, %0|%0, %1}"
1896 [(set_attr "type" "ssecvt")
1897 (set_attr "prefix" "vex")
1898 (set_attr "mode" "<avxvecmode>")])
1900 (define_insn "sse2_cvtps2dq"
1901 [(set (match_operand:V4SI 0 "register_operand" "=x")
1902 (unspec:V4SI [(match_operand:V4SF 1 "nonimmediate_operand" "xm")]
1903 UNSPEC_FIX_NOTRUNC))]
1905 "cvtps2dq\t{%1, %0|%0, %1}"
1906 [(set_attr "type" "ssecvt")
1907 (set_attr "prefix_data16" "1")
1908 (set_attr "mode" "TI")])
1910 (define_insn "avx_cvttps2dq<avxmodesuffix>"
1911 [(set (match_operand:AVXMODEDCVTPS2DQ 0 "register_operand" "=x")
1912 (fix:AVXMODEDCVTPS2DQ
1913 (match_operand:<avxcvtvecmode> 1 "nonimmediate_operand" "xm")))]
1915 "vcvttps2dq\t{%1, %0|%0, %1}"
1916 [(set_attr "type" "ssecvt")
1917 (set_attr "prefix" "vex")
1918 (set_attr "mode" "<avxvecmode>")])
1920 (define_insn "sse2_cvttps2dq"
1921 [(set (match_operand:V4SI 0 "register_operand" "=x")
1922 (fix:V4SI (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
1924 "cvttps2dq\t{%1, %0|%0, %1}"
1925 [(set_attr "type" "ssecvt")
1926 (set_attr "prefix_rep" "1")
1927 (set_attr "prefix_data16" "0")
1928 (set_attr "mode" "TI")])
1930 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1932 ;; Parallel double-precision floating point conversion operations
1934 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
1936 (define_insn "sse2_cvtpi2pd"
1937 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1938 (float:V2DF (match_operand:V2SI 1 "nonimmediate_operand" "y,m")))]
1940 "cvtpi2pd\t{%1, %0|%0, %1}"
1941 [(set_attr "type" "ssecvt")
1942 (set_attr "unit" "mmx,*")
1943 (set_attr "prefix_data16" "1,*")
1944 (set_attr "mode" "V2DF")])
1946 (define_insn "sse2_cvtpd2pi"
1947 [(set (match_operand:V2SI 0 "register_operand" "=y")
1948 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
1949 UNSPEC_FIX_NOTRUNC))]
1951 "cvtpd2pi\t{%1, %0|%0, %1}"
1952 [(set_attr "type" "ssecvt")
1953 (set_attr "unit" "mmx")
1954 (set_attr "prefix_data16" "1")
1955 (set_attr "mode" "DI")])
1957 (define_insn "sse2_cvttpd2pi"
1958 [(set (match_operand:V2SI 0 "register_operand" "=y")
1959 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm")))]
1961 "cvttpd2pi\t{%1, %0|%0, %1}"
1962 [(set_attr "type" "ssecvt")
1963 (set_attr "unit" "mmx")
1964 (set_attr "prefix_data16" "1")
1965 (set_attr "mode" "TI")])
1967 (define_insn "*avx_cvtsi2sd"
1968 [(set (match_operand:V2DF 0 "register_operand" "=x")
1971 (float:DF (match_operand:SI 2 "nonimmediate_operand" "rm")))
1972 (match_operand:V2DF 1 "register_operand" "x")
1975 "vcvtsi2sd\t{%2, %1, %0|%0, %1, %2}"
1976 [(set_attr "type" "sseicvt")
1977 (set_attr "prefix" "vex")
1978 (set_attr "mode" "DF")])
1980 (define_insn "sse2_cvtsi2sd"
1981 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
1984 (float:DF (match_operand:SI 2 "nonimmediate_operand" "r,m")))
1985 (match_operand:V2DF 1 "register_operand" "0,0")
1988 "cvtsi2sd\t{%2, %0|%0, %2}"
1989 [(set_attr "type" "sseicvt")
1990 (set_attr "mode" "DF")
1991 (set_attr "athlon_decode" "double,direct")
1992 (set_attr "amdfam10_decode" "vector,double")])
1994 (define_insn "*avx_cvtsi2sdq"
1995 [(set (match_operand:V2DF 0 "register_operand" "=x")
1998 (float:DF (match_operand:DI 2 "nonimmediate_operand" "rm")))
1999 (match_operand:V2DF 1 "register_operand" "x")
2001 "TARGET_AVX && TARGET_64BIT"
2002 "vcvtsi2sdq\t{%2, %1, %0|%0, %1, %2}"
2003 [(set_attr "type" "sseicvt")
2004 (set_attr "length_vex" "4")
2005 (set_attr "prefix" "vex")
2006 (set_attr "mode" "DF")])
2008 (define_insn "sse2_cvtsi2sdq"
2009 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2012 (float:DF (match_operand:DI 2 "nonimmediate_operand" "r,m")))
2013 (match_operand:V2DF 1 "register_operand" "0,0")
2015 "TARGET_SSE2 && TARGET_64BIT"
2016 "cvtsi2sdq\t{%2, %0|%0, %2}"
2017 [(set_attr "type" "sseicvt")
2018 (set_attr "prefix_rex" "1")
2019 (set_attr "mode" "DF")
2020 (set_attr "athlon_decode" "double,direct")
2021 (set_attr "amdfam10_decode" "vector,double")])
2023 (define_insn "sse2_cvtsd2si"
2024 [(set (match_operand:SI 0 "register_operand" "=r,r")
2027 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2028 (parallel [(const_int 0)]))]
2029 UNSPEC_FIX_NOTRUNC))]
2031 "%vcvtsd2si\t{%1, %0|%0, %1}"
2032 [(set_attr "type" "sseicvt")
2033 (set_attr "athlon_decode" "double,vector")
2034 (set_attr "prefix_rep" "1")
2035 (set_attr "prefix" "maybe_vex")
2036 (set_attr "mode" "SI")])
2038 (define_insn "sse2_cvtsd2si_2"
2039 [(set (match_operand:SI 0 "register_operand" "=r,r")
2040 (unspec:SI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
2041 UNSPEC_FIX_NOTRUNC))]
2043 "%vcvtsd2si\t{%1, %0|%0, %1}"
2044 [(set_attr "type" "sseicvt")
2045 (set_attr "athlon_decode" "double,vector")
2046 (set_attr "amdfam10_decode" "double,double")
2047 (set_attr "prefix_rep" "1")
2048 (set_attr "prefix" "maybe_vex")
2049 (set_attr "mode" "SI")])
2051 (define_insn "sse2_cvtsd2siq"
2052 [(set (match_operand:DI 0 "register_operand" "=r,r")
2055 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2056 (parallel [(const_int 0)]))]
2057 UNSPEC_FIX_NOTRUNC))]
2058 "TARGET_SSE2 && TARGET_64BIT"
2059 "%vcvtsd2siq\t{%1, %0|%0, %1}"
2060 [(set_attr "type" "sseicvt")
2061 (set_attr "athlon_decode" "double,vector")
2062 (set_attr "prefix_rep" "1")
2063 (set_attr "prefix" "maybe_vex")
2064 (set_attr "mode" "DI")])
2066 (define_insn "sse2_cvtsd2siq_2"
2067 [(set (match_operand:DI 0 "register_operand" "=r,r")
2068 (unspec:DI [(match_operand:DF 1 "nonimmediate_operand" "x,m")]
2069 UNSPEC_FIX_NOTRUNC))]
2070 "TARGET_SSE2 && TARGET_64BIT"
2071 "%vcvtsd2siq\t{%1, %0|%0, %1}"
2072 [(set_attr "type" "sseicvt")
2073 (set_attr "athlon_decode" "double,vector")
2074 (set_attr "amdfam10_decode" "double,double")
2075 (set_attr "prefix_rep" "1")
2076 (set_attr "prefix" "maybe_vex")
2077 (set_attr "mode" "DI")])
2079 (define_insn "sse2_cvttsd2si"
2080 [(set (match_operand:SI 0 "register_operand" "=r,r")
2083 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2084 (parallel [(const_int 0)]))))]
2086 "%vcvttsd2si\t{%1, %0|%0, %1}"
2087 [(set_attr "type" "sseicvt")
2088 (set_attr "prefix_rep" "1")
2089 (set_attr "prefix" "maybe_vex")
2090 (set_attr "mode" "SI")
2091 (set_attr "athlon_decode" "double,vector")
2092 (set_attr "amdfam10_decode" "double,double")])
2094 (define_insn "sse2_cvttsd2siq"
2095 [(set (match_operand:DI 0 "register_operand" "=r,r")
2098 (match_operand:V2DF 1 "nonimmediate_operand" "x,m")
2099 (parallel [(const_int 0)]))))]
2100 "TARGET_SSE2 && TARGET_64BIT"
2101 "%vcvttsd2siq\t{%1, %0|%0, %1}"
2102 [(set_attr "type" "sseicvt")
2103 (set_attr "prefix_rep" "1")
2104 (set_attr "prefix" "maybe_vex")
2105 (set_attr "mode" "DI")
2106 (set_attr "athlon_decode" "double,vector")
2107 (set_attr "amdfam10_decode" "double,double")])
2109 (define_insn "avx_cvtdq2pd256"
2110 [(set (match_operand:V4DF 0 "register_operand" "=x")
2111 (float:V4DF (match_operand:V4SI 1 "nonimmediate_operand" "xm")))]
2113 "vcvtdq2pd\t{%1, %0|%0, %1}"
2114 [(set_attr "type" "ssecvt")
2115 (set_attr "prefix" "vex")
2116 (set_attr "mode" "V4DF")])
2118 (define_insn "sse2_cvtdq2pd"
2119 [(set (match_operand:V2DF 0 "register_operand" "=x")
2122 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
2123 (parallel [(const_int 0) (const_int 1)]))))]
2125 "%vcvtdq2pd\t{%1, %0|%0, %1}"
2126 [(set_attr "type" "ssecvt")
2127 (set_attr "prefix" "maybe_vex")
2128 (set_attr "mode" "V2DF")])
2130 (define_insn "avx_cvtpd2dq256"
2131 [(set (match_operand:V4SI 0 "register_operand" "=x")
2132 (unspec:V4SI [(match_operand:V4DF 1 "nonimmediate_operand" "xm")]
2133 UNSPEC_FIX_NOTRUNC))]
2135 "vcvtpd2dq{y}\t{%1, %0|%0, %1}"
2136 [(set_attr "type" "ssecvt")
2137 (set_attr "prefix" "vex")
2138 (set_attr "mode" "OI")])
2140 (define_expand "sse2_cvtpd2dq"
2141 [(set (match_operand:V4SI 0 "register_operand" "")
2143 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "")]
2147 "operands[2] = CONST0_RTX (V2SImode);")
2149 (define_insn "*sse2_cvtpd2dq"
2150 [(set (match_operand:V4SI 0 "register_operand" "=x")
2152 (unspec:V2SI [(match_operand:V2DF 1 "nonimmediate_operand" "xm")]
2154 (match_operand:V2SI 2 "const0_operand" "")))]
2156 "* return TARGET_AVX ? \"vcvtpd2dq{x}\t{%1, %0|%0, %1}\"
2157 : \"cvtpd2dq\t{%1, %0|%0, %1}\";"
2158 [(set_attr "type" "ssecvt")
2159 (set_attr "prefix_rep" "1")
2160 (set_attr "prefix_data16" "0")
2161 (set_attr "prefix" "maybe_vex")
2162 (set_attr "mode" "TI")
2163 (set_attr "amdfam10_decode" "double")])
2165 (define_insn "avx_cvttpd2dq256"
2166 [(set (match_operand:V4SI 0 "register_operand" "=x")
2167 (fix:V4SI (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
2169 "vcvttpd2dq{y}\t{%1, %0|%0, %1}"
2170 [(set_attr "type" "ssecvt")
2171 (set_attr "prefix" "vex")
2172 (set_attr "mode" "OI")])
2174 (define_expand "sse2_cvttpd2dq"
2175 [(set (match_operand:V4SI 0 "register_operand" "")
2177 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" ""))
2180 "operands[2] = CONST0_RTX (V2SImode);")
2182 (define_insn "*sse2_cvttpd2dq"
2183 [(set (match_operand:V4SI 0 "register_operand" "=x")
2185 (fix:V2SI (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
2186 (match_operand:V2SI 2 "const0_operand" "")))]
2188 "* return TARGET_AVX ? \"vcvttpd2dq{x}\t{%1, %0|%0, %1}\"
2189 : \"cvttpd2dq\t{%1, %0|%0, %1}\";"
2190 [(set_attr "type" "ssecvt")
2191 (set_attr "prefix" "maybe_vex")
2192 (set_attr "mode" "TI")
2193 (set_attr "amdfam10_decode" "double")])
2195 (define_insn "*avx_cvtsd2ss"
2196 [(set (match_operand:V4SF 0 "register_operand" "=x")
2199 (float_truncate:V2SF
2200 (match_operand:V2DF 2 "nonimmediate_operand" "xm")))
2201 (match_operand:V4SF 1 "register_operand" "x")
2204 "vcvtsd2ss\t{%2, %1, %0|%0, %1, %2}"
2205 [(set_attr "type" "ssecvt")
2206 (set_attr "prefix" "vex")
2207 (set_attr "mode" "SF")])
2209 (define_insn "sse2_cvtsd2ss"
2210 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
2213 (float_truncate:V2SF
2214 (match_operand:V2DF 2 "nonimmediate_operand" "x,m")))
2215 (match_operand:V4SF 1 "register_operand" "0,0")
2218 "cvtsd2ss\t{%2, %0|%0, %2}"
2219 [(set_attr "type" "ssecvt")
2220 (set_attr "athlon_decode" "vector,double")
2221 (set_attr "amdfam10_decode" "vector,double")
2222 (set_attr "mode" "SF")])
2224 (define_insn "*avx_cvtss2sd"
2225 [(set (match_operand:V2DF 0 "register_operand" "=x")
2229 (match_operand:V4SF 2 "nonimmediate_operand" "xm")
2230 (parallel [(const_int 0) (const_int 1)])))
2231 (match_operand:V2DF 1 "register_operand" "x")
2234 "vcvtss2sd\t{%2, %1, %0|%0, %1, %2}"
2235 [(set_attr "type" "ssecvt")
2236 (set_attr "prefix" "vex")
2237 (set_attr "mode" "DF")])
2239 (define_insn "sse2_cvtss2sd"
2240 [(set (match_operand:V2DF 0 "register_operand" "=x,x")
2244 (match_operand:V4SF 2 "nonimmediate_operand" "x,m")
2245 (parallel [(const_int 0) (const_int 1)])))
2246 (match_operand:V2DF 1 "register_operand" "0,0")
2249 "cvtss2sd\t{%2, %0|%0, %2}"
2250 [(set_attr "type" "ssecvt")
2251 (set_attr "amdfam10_decode" "vector,double")
2252 (set_attr "mode" "DF")])
2254 (define_insn "avx_cvtpd2ps256"
2255 [(set (match_operand:V4SF 0 "register_operand" "=x")
2256 (float_truncate:V4SF
2257 (match_operand:V4DF 1 "nonimmediate_operand" "xm")))]
2259 "vcvtpd2ps{y}\t{%1, %0|%0, %1}"
2260 [(set_attr "type" "ssecvt")
2261 (set_attr "prefix" "vex")
2262 (set_attr "mode" "V4SF")])
2264 (define_expand "sse2_cvtpd2ps"
2265 [(set (match_operand:V4SF 0 "register_operand" "")
2267 (float_truncate:V2SF
2268 (match_operand:V2DF 1 "nonimmediate_operand" ""))
2271 "operands[2] = CONST0_RTX (V2SFmode);")
2273 (define_insn "*sse2_cvtpd2ps"
2274 [(set (match_operand:V4SF 0 "register_operand" "=x")
2276 (float_truncate:V2SF
2277 (match_operand:V2DF 1 "nonimmediate_operand" "xm"))
2278 (match_operand:V2SF 2 "const0_operand" "")))]
2280 "* return TARGET_AVX ? \"vcvtpd2ps{x}\t{%1, %0|%0, %1}\"
2281 : \"cvtpd2ps\t{%1, %0|%0, %1}\";"
2282 [(set_attr "type" "ssecvt")
2283 (set_attr "prefix_data16" "1")
2284 (set_attr "prefix" "maybe_vex")
2285 (set_attr "mode" "V4SF")
2286 (set_attr "amdfam10_decode" "double")])
2288 (define_insn "avx_cvtps2pd256"
2289 [(set (match_operand:V4DF 0 "register_operand" "=x")
2291 (match_operand:V4SF 1 "nonimmediate_operand" "xm")))]
2293 "vcvtps2pd\t{%1, %0|%0, %1}"
2294 [(set_attr "type" "ssecvt")
2295 (set_attr "prefix" "vex")
2296 (set_attr "mode" "V4DF")])
2298 (define_insn "sse2_cvtps2pd"
2299 [(set (match_operand:V2DF 0 "register_operand" "=x")
2302 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
2303 (parallel [(const_int 0) (const_int 1)]))))]
2305 "%vcvtps2pd\t{%1, %0|%0, %1}"
2306 [(set_attr "type" "ssecvt")
2307 (set_attr "prefix" "maybe_vex")
2308 (set_attr "mode" "V2DF")
2309 (set_attr "prefix_data16" "0")
2310 (set_attr "amdfam10_decode" "direct")])
2312 (define_expand "vec_unpacks_hi_v4sf"
2317 (match_operand:V4SF 1 "nonimmediate_operand" ""))
2318 (parallel [(const_int 6)
2322 (set (match_operand:V2DF 0 "register_operand" "")
2326 (parallel [(const_int 0) (const_int 1)]))))]
2329 operands[2] = gen_reg_rtx (V4SFmode);
2332 (define_expand "vec_unpacks_lo_v4sf"
2333 [(set (match_operand:V2DF 0 "register_operand" "")
2336 (match_operand:V4SF 1 "nonimmediate_operand" "")
2337 (parallel [(const_int 0) (const_int 1)]))))]
2340 (define_expand "vec_unpacks_float_hi_v8hi"
2341 [(match_operand:V4SF 0 "register_operand" "")
2342 (match_operand:V8HI 1 "register_operand" "")]
2345 rtx tmp = gen_reg_rtx (V4SImode);
2347 emit_insn (gen_vec_unpacks_hi_v8hi (tmp, operands[1]));
2348 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
2352 (define_expand "vec_unpacks_float_lo_v8hi"
2353 [(match_operand:V4SF 0 "register_operand" "")
2354 (match_operand:V8HI 1 "register_operand" "")]
2357 rtx tmp = gen_reg_rtx (V4SImode);
2359 emit_insn (gen_vec_unpacks_lo_v8hi (tmp, operands[1]));
2360 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
2364 (define_expand "vec_unpacku_float_hi_v8hi"
2365 [(match_operand:V4SF 0 "register_operand" "")
2366 (match_operand:V8HI 1 "register_operand" "")]
2369 rtx tmp = gen_reg_rtx (V4SImode);
2371 emit_insn (gen_vec_unpacku_hi_v8hi (tmp, operands[1]));
2372 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
2376 (define_expand "vec_unpacku_float_lo_v8hi"
2377 [(match_operand:V4SF 0 "register_operand" "")
2378 (match_operand:V8HI 1 "register_operand" "")]
2381 rtx tmp = gen_reg_rtx (V4SImode);
2383 emit_insn (gen_vec_unpacku_lo_v8hi (tmp, operands[1]));
2384 emit_insn (gen_sse2_cvtdq2ps (operands[0], tmp));
2388 (define_expand "vec_unpacks_float_hi_v4si"
2391 (match_operand:V4SI 1 "nonimmediate_operand" "")
2392 (parallel [(const_int 2)
2396 (set (match_operand:V2DF 0 "register_operand" "")
2400 (parallel [(const_int 0) (const_int 1)]))))]
2402 "operands[2] = gen_reg_rtx (V4SImode);")
2404 (define_expand "vec_unpacks_float_lo_v4si"
2405 [(set (match_operand:V2DF 0 "register_operand" "")
2408 (match_operand:V4SI 1 "nonimmediate_operand" "")
2409 (parallel [(const_int 0) (const_int 1)]))))]
2412 (define_expand "vec_unpacku_float_hi_v4si"
2415 (match_operand:V4SI 1 "nonimmediate_operand" "")
2416 (parallel [(const_int 2)
2424 (parallel [(const_int 0) (const_int 1)]))))
2426 (lt:V2DF (match_dup 6) (match_dup 3)))
2428 (and:V2DF (match_dup 7) (match_dup 4)))
2429 (set (match_operand:V2DF 0 "register_operand" "")
2430 (plus:V2DF (match_dup 6) (match_dup 8)))]
2433 REAL_VALUE_TYPE TWO32r;
2437 real_ldexp (&TWO32r, &dconst1, 32);
2438 x = const_double_from_real_value (TWO32r, DFmode);
2440 operands[3] = force_reg (V2DFmode, CONST0_RTX (V2DFmode));
2441 operands[4] = force_reg (V2DFmode, ix86_build_const_vector (DFmode, 1, x));
2443 operands[5] = gen_reg_rtx (V4SImode);
2445 for (i = 6; i < 9; i++)
2446 operands[i] = gen_reg_rtx (V2DFmode);
2449 (define_expand "vec_unpacku_float_lo_v4si"
2453 (match_operand:V4SI 1 "nonimmediate_operand" "")
2454 (parallel [(const_int 0) (const_int 1)]))))
2456 (lt:V2DF (match_dup 5) (match_dup 3)))
2458 (and:V2DF (match_dup 6) (match_dup 4)))
2459 (set (match_operand:V2DF 0 "register_operand" "")
2460 (plus:V2DF (match_dup 5) (match_dup 7)))]
2463 REAL_VALUE_TYPE TWO32r;
2467 real_ldexp (&TWO32r, &dconst1, 32);
2468 x = const_double_from_real_value (TWO32r, DFmode);
2470 operands[3] = force_reg (V2DFmode, CONST0_RTX (V2DFmode));
2471 operands[4] = force_reg (V2DFmode, ix86_build_const_vector (DFmode, 1, x));
2473 for (i = 5; i < 8; i++)
2474 operands[i] = gen_reg_rtx (V2DFmode);
2477 (define_expand "vec_pack_trunc_v2df"
2478 [(match_operand:V4SF 0 "register_operand" "")
2479 (match_operand:V2DF 1 "nonimmediate_operand" "")
2480 (match_operand:V2DF 2 "nonimmediate_operand" "")]
2485 r1 = gen_reg_rtx (V4SFmode);
2486 r2 = gen_reg_rtx (V4SFmode);
2488 emit_insn (gen_sse2_cvtpd2ps (r1, operands[1]));
2489 emit_insn (gen_sse2_cvtpd2ps (r2, operands[2]));
2490 emit_insn (gen_sse_movlhps (operands[0], r1, r2));
2494 (define_expand "vec_pack_sfix_trunc_v2df"
2495 [(match_operand:V4SI 0 "register_operand" "")
2496 (match_operand:V2DF 1 "nonimmediate_operand" "")
2497 (match_operand:V2DF 2 "nonimmediate_operand" "")]
2502 r1 = gen_reg_rtx (V4SImode);
2503 r2 = gen_reg_rtx (V4SImode);
2505 emit_insn (gen_sse2_cvttpd2dq (r1, operands[1]));
2506 emit_insn (gen_sse2_cvttpd2dq (r2, operands[2]));
2507 emit_insn (gen_sse2_punpcklqdq (gen_lowpart (V2DImode, operands[0]),
2508 gen_lowpart (V2DImode, r1),
2509 gen_lowpart (V2DImode, r2)));
2513 (define_expand "vec_pack_sfix_v2df"
2514 [(match_operand:V4SI 0 "register_operand" "")
2515 (match_operand:V2DF 1 "nonimmediate_operand" "")
2516 (match_operand:V2DF 2 "nonimmediate_operand" "")]
2521 r1 = gen_reg_rtx (V4SImode);
2522 r2 = gen_reg_rtx (V4SImode);
2524 emit_insn (gen_sse2_cvtpd2dq (r1, operands[1]));
2525 emit_insn (gen_sse2_cvtpd2dq (r2, operands[2]));
2526 emit_insn (gen_sse2_punpcklqdq (gen_lowpart (V2DImode, operands[0]),
2527 gen_lowpart (V2DImode, r1),
2528 gen_lowpart (V2DImode, r2)));
2532 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2534 ;; Parallel single-precision floating point element swizzling
2536 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
2538 (define_expand "sse_movhlps_exp"
2539 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
2542 (match_operand:V4SF 1 "nonimmediate_operand" "")
2543 (match_operand:V4SF 2 "nonimmediate_operand" ""))
2544 (parallel [(const_int 6)
2549 "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
2551 (define_insn "*avx_movhlps"
2552 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
2555 (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0")
2556 (match_operand:V4SF 2 "nonimmediate_operand" " x,o,x"))
2557 (parallel [(const_int 6)
2561 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
2563 vmovhlps\t{%2, %1, %0|%0, %1, %2}
2564 vmovlps\t{%H2, %1, %0|%0, %1, %H2}
2565 vmovhps\t{%2, %0|%0, %2}"
2566 [(set_attr "type" "ssemov")
2567 (set_attr "prefix" "vex")
2568 (set_attr "mode" "V4SF,V2SF,V2SF")])
2570 (define_insn "sse_movhlps"
2571 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
2574 (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
2575 (match_operand:V4SF 2 "nonimmediate_operand" " x,o,x"))
2576 (parallel [(const_int 6)
2580 "TARGET_SSE && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
2582 movhlps\t{%2, %0|%0, %2}
2583 movlps\t{%H2, %0|%0, %H2}
2584 movhps\t{%2, %0|%0, %2}"
2585 [(set_attr "type" "ssemov")
2586 (set_attr "mode" "V4SF,V2SF,V2SF")])
2588 (define_expand "sse_movlhps_exp"
2589 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
2592 (match_operand:V4SF 1 "nonimmediate_operand" "")
2593 (match_operand:V4SF 2 "nonimmediate_operand" ""))
2594 (parallel [(const_int 0)
2599 "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
2601 (define_insn "*avx_movlhps"
2602 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
2605 (match_operand:V4SF 1 "nonimmediate_operand" " x,x,0")
2606 (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
2607 (parallel [(const_int 0)
2611 "TARGET_AVX && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
2613 vmovlhps\t{%2, %1, %0|%0, %1, %2}
2614 vmovhps\t{%2, %1, %0|%0, %1, %2}
2615 vmovlps\t{%2, %H0|%H0, %2}"
2616 [(set_attr "type" "ssemov")
2617 (set_attr "prefix" "vex")
2618 (set_attr "mode" "V4SF,V2SF,V2SF")])
2620 (define_insn "sse_movlhps"
2621 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
2624 (match_operand:V4SF 1 "nonimmediate_operand" " 0,0,0")
2625 (match_operand:V4SF 2 "nonimmediate_operand" " x,m,x"))
2626 (parallel [(const_int 0)
2630 "TARGET_SSE && ix86_binary_operator_ok (UNKNOWN, V4SFmode, operands)"
2632 movlhps\t{%2, %0|%0, %2}
2633 movhps\t{%2, %0|%0, %2}
2634 movlps\t{%2, %H0|%H0, %2}"
2635 [(set_attr "type" "ssemov")
2636 (set_attr "mode" "V4SF,V2SF,V2SF")])
2638 (define_insn "avx_unpckhps256"
2639 [(set (match_operand:V8SF 0 "register_operand" "=x")
2642 (match_operand:V8SF 1 "register_operand" "x")
2643 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
2644 (parallel [(const_int 2) (const_int 10)
2645 (const_int 3) (const_int 11)
2646 (const_int 6) (const_int 14)
2647 (const_int 7) (const_int 15)])))]
2649 "vunpckhps\t{%2, %1, %0|%0, %1, %2}"
2650 [(set_attr "type" "sselog")
2651 (set_attr "prefix" "vex")
2652 (set_attr "mode" "V8SF")])
2654 (define_insn "*avx_unpckhps"
2655 [(set (match_operand:V4SF 0 "register_operand" "=x")
2658 (match_operand:V4SF 1 "register_operand" "x")
2659 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
2660 (parallel [(const_int 2) (const_int 6)
2661 (const_int 3) (const_int 7)])))]
2663 "vunpckhps\t{%2, %1, %0|%0, %1, %2}"
2664 [(set_attr "type" "sselog")
2665 (set_attr "prefix" "vex")
2666 (set_attr "mode" "V4SF")])
2668 (define_insn "sse_unpckhps"
2669 [(set (match_operand:V4SF 0 "register_operand" "=x")
2672 (match_operand:V4SF 1 "register_operand" "0")
2673 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
2674 (parallel [(const_int 2) (const_int 6)
2675 (const_int 3) (const_int 7)])))]
2677 "unpckhps\t{%2, %0|%0, %2}"
2678 [(set_attr "type" "sselog")
2679 (set_attr "mode" "V4SF")])
2681 (define_insn "avx_unpcklps256"
2682 [(set (match_operand:V8SF 0 "register_operand" "=x")
2685 (match_operand:V8SF 1 "register_operand" "x")
2686 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
2687 (parallel [(const_int 0) (const_int 8)
2688 (const_int 1) (const_int 9)
2689 (const_int 4) (const_int 12)
2690 (const_int 5) (const_int 13)])))]
2692 "vunpcklps\t{%2, %1, %0|%0, %1, %2}"
2693 [(set_attr "type" "sselog")
2694 (set_attr "prefix" "vex")
2695 (set_attr "mode" "V8SF")])
2697 (define_insn "*avx_unpcklps"
2698 [(set (match_operand:V4SF 0 "register_operand" "=x")
2701 (match_operand:V4SF 1 "register_operand" "x")
2702 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
2703 (parallel [(const_int 0) (const_int 4)
2704 (const_int 1) (const_int 5)])))]
2706 "vunpcklps\t{%2, %1, %0|%0, %1, %2}"
2707 [(set_attr "type" "sselog")
2708 (set_attr "prefix" "vex")
2709 (set_attr "mode" "V4SF")])
2711 (define_insn "sse_unpcklps"
2712 [(set (match_operand:V4SF 0 "register_operand" "=x")
2715 (match_operand:V4SF 1 "register_operand" "0")
2716 (match_operand:V4SF 2 "nonimmediate_operand" "xm"))
2717 (parallel [(const_int 0) (const_int 4)
2718 (const_int 1) (const_int 5)])))]
2720 "unpcklps\t{%2, %0|%0, %2}"
2721 [(set_attr "type" "sselog")
2722 (set_attr "mode" "V4SF")])
2724 ;; These are modeled with the same vec_concat as the others so that we
2725 ;; capture users of shufps that can use the new instructions
2726 (define_insn "avx_movshdup256"
2727 [(set (match_operand:V8SF 0 "register_operand" "=x")
2730 (match_operand:V8SF 1 "nonimmediate_operand" "xm")
2732 (parallel [(const_int 1) (const_int 1)
2733 (const_int 3) (const_int 3)
2734 (const_int 5) (const_int 5)
2735 (const_int 7) (const_int 7)])))]
2737 "vmovshdup\t{%1, %0|%0, %1}"
2738 [(set_attr "type" "sse")
2739 (set_attr "prefix" "vex")
2740 (set_attr "mode" "V8SF")])
2742 (define_insn "sse3_movshdup"
2743 [(set (match_operand:V4SF 0 "register_operand" "=x")
2746 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
2748 (parallel [(const_int 1)
2753 "%vmovshdup\t{%1, %0|%0, %1}"
2754 [(set_attr "type" "sse")
2755 (set_attr "prefix_rep" "1")
2756 (set_attr "prefix" "maybe_vex")
2757 (set_attr "mode" "V4SF")])
2759 (define_insn "avx_movsldup256"
2760 [(set (match_operand:V8SF 0 "register_operand" "=x")
2763 (match_operand:V8SF 1 "nonimmediate_operand" "xm")
2765 (parallel [(const_int 0) (const_int 0)
2766 (const_int 2) (const_int 2)
2767 (const_int 4) (const_int 4)
2768 (const_int 6) (const_int 6)])))]
2770 "vmovsldup\t{%1, %0|%0, %1}"
2771 [(set_attr "type" "sse")
2772 (set_attr "prefix" "vex")
2773 (set_attr "mode" "V8SF")])
2775 (define_insn "sse3_movsldup"
2776 [(set (match_operand:V4SF 0 "register_operand" "=x")
2779 (match_operand:V4SF 1 "nonimmediate_operand" "xm")
2781 (parallel [(const_int 0)
2786 "%vmovsldup\t{%1, %0|%0, %1}"
2787 [(set_attr "type" "sse")
2788 (set_attr "prefix_rep" "1")
2789 (set_attr "prefix" "maybe_vex")
2790 (set_attr "mode" "V4SF")])
2792 (define_expand "avx_shufps256"
2793 [(match_operand:V8SF 0 "register_operand" "")
2794 (match_operand:V8SF 1 "register_operand" "")
2795 (match_operand:V8SF 2 "nonimmediate_operand" "")
2796 (match_operand:SI 3 "const_int_operand" "")]
2799 int mask = INTVAL (operands[3]);
2800 emit_insn (gen_avx_shufps256_1 (operands[0], operands[1], operands[2],
2801 GEN_INT ((mask >> 0) & 3),
2802 GEN_INT ((mask >> 2) & 3),
2803 GEN_INT (((mask >> 4) & 3) + 8),
2804 GEN_INT (((mask >> 6) & 3) + 8),
2805 GEN_INT (((mask >> 0) & 3) + 4),
2806 GEN_INT (((mask >> 2) & 3) + 4),
2807 GEN_INT (((mask >> 4) & 3) + 12),
2808 GEN_INT (((mask >> 6) & 3) + 12)));
2812 ;; One bit in mask selects 2 elements.
2813 (define_insn "avx_shufps256_1"
2814 [(set (match_operand:V8SF 0 "register_operand" "=x")
2817 (match_operand:V8SF 1 "register_operand" "x")
2818 (match_operand:V8SF 2 "nonimmediate_operand" "xm"))
2819 (parallel [(match_operand 3 "const_0_to_3_operand" "")
2820 (match_operand 4 "const_0_to_3_operand" "")
2821 (match_operand 5 "const_8_to_11_operand" "")
2822 (match_operand 6 "const_8_to_11_operand" "")
2823 (match_operand 7 "const_4_to_7_operand" "")
2824 (match_operand 8 "const_4_to_7_operand" "")
2825 (match_operand 9 "const_12_to_15_operand" "")
2826 (match_operand 10 "const_12_to_15_operand" "")])))]
2828 && (INTVAL (operands[3]) == (INTVAL (operands[7]) - 4)
2829 && INTVAL (operands[4]) == (INTVAL (operands[8]) - 4)
2830 && INTVAL (operands[5]) == (INTVAL (operands[9]) - 4)
2831 && INTVAL (operands[6]) == (INTVAL (operands[10]) - 4))"
2834 mask = INTVAL (operands[3]);
2835 mask |= INTVAL (operands[4]) << 2;
2836 mask |= (INTVAL (operands[5]) - 8) << 4;
2837 mask |= (INTVAL (operands[6]) - 8) << 6;
2838 operands[3] = GEN_INT (mask);
2840 return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
2842 [(set_attr "type" "sselog")
2843 (set_attr "length_immediate" "1")
2844 (set_attr "prefix" "vex")
2845 (set_attr "mode" "V8SF")])
2847 (define_expand "sse_shufps"
2848 [(match_operand:V4SF 0 "register_operand" "")
2849 (match_operand:V4SF 1 "register_operand" "")
2850 (match_operand:V4SF 2 "nonimmediate_operand" "")
2851 (match_operand:SI 3 "const_int_operand" "")]
2854 int mask = INTVAL (operands[3]);
2855 emit_insn (gen_sse_shufps_v4sf (operands[0], operands[1], operands[2],
2856 GEN_INT ((mask >> 0) & 3),
2857 GEN_INT ((mask >> 2) & 3),
2858 GEN_INT (((mask >> 4) & 3) + 4),
2859 GEN_INT (((mask >> 6) & 3) + 4)));
2863 (define_insn "*avx_shufps_<mode>"
2864 [(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
2865 (vec_select:SSEMODE4S
2866 (vec_concat:<ssedoublesizemode>
2867 (match_operand:SSEMODE4S 1 "register_operand" "x")
2868 (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
2869 (parallel [(match_operand 3 "const_0_to_3_operand" "")
2870 (match_operand 4 "const_0_to_3_operand" "")
2871 (match_operand 5 "const_4_to_7_operand" "")
2872 (match_operand 6 "const_4_to_7_operand" "")])))]
2876 mask |= INTVAL (operands[3]) << 0;
2877 mask |= INTVAL (operands[4]) << 2;
2878 mask |= (INTVAL (operands[5]) - 4) << 4;
2879 mask |= (INTVAL (operands[6]) - 4) << 6;
2880 operands[3] = GEN_INT (mask);
2882 return "vshufps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
2884 [(set_attr "type" "sselog")
2885 (set_attr "length_immediate" "1")
2886 (set_attr "prefix" "vex")
2887 (set_attr "mode" "V4SF")])
2889 (define_insn "sse_shufps_<mode>"
2890 [(set (match_operand:SSEMODE4S 0 "register_operand" "=x")
2891 (vec_select:SSEMODE4S
2892 (vec_concat:<ssedoublesizemode>
2893 (match_operand:SSEMODE4S 1 "register_operand" "0")
2894 (match_operand:SSEMODE4S 2 "nonimmediate_operand" "xm"))
2895 (parallel [(match_operand 3 "const_0_to_3_operand" "")
2896 (match_operand 4 "const_0_to_3_operand" "")
2897 (match_operand 5 "const_4_to_7_operand" "")
2898 (match_operand 6 "const_4_to_7_operand" "")])))]
2902 mask |= INTVAL (operands[3]) << 0;
2903 mask |= INTVAL (operands[4]) << 2;
2904 mask |= (INTVAL (operands[5]) - 4) << 4;
2905 mask |= (INTVAL (operands[6]) - 4) << 6;
2906 operands[3] = GEN_INT (mask);
2908 return "shufps\t{%3, %2, %0|%0, %2, %3}";
2910 [(set_attr "type" "sselog")
2911 (set_attr "length_immediate" "1")
2912 (set_attr "mode" "V4SF")])
2914 (define_insn "sse_storehps"
2915 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
2917 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,o")
2918 (parallel [(const_int 2) (const_int 3)])))]
2921 %vmovhps\t{%1, %0|%0, %1}
2922 %vmovhlps\t{%1, %d0|%d0, %1}
2923 %vmovlps\t{%H1, %d0|%d0, %H1}"
2924 [(set_attr "type" "ssemov")
2925 (set_attr "prefix" "maybe_vex")
2926 (set_attr "mode" "V2SF,V4SF,V2SF")])
2928 (define_expand "sse_loadhps_exp"
2929 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
2932 (match_operand:V4SF 1 "nonimmediate_operand" "")
2933 (parallel [(const_int 0) (const_int 1)]))
2934 (match_operand:V2SF 2 "nonimmediate_operand" "")))]
2936 "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
2938 (define_insn "*avx_loadhps"
2939 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
2942 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
2943 (parallel [(const_int 0) (const_int 1)]))
2944 (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
2947 vmovhps\t{%2, %1, %0|%0, %1, %2}
2948 vmovlhps\t{%2, %1, %0|%0, %1, %2}
2949 vmovlps\t{%2, %H0|%H0, %2}"
2950 [(set_attr "type" "ssemov")
2951 (set_attr "prefix" "vex")
2952 (set_attr "mode" "V2SF,V4SF,V2SF")])
2954 (define_insn "sse_loadhps"
2955 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,o")
2958 (match_operand:V4SF 1 "nonimmediate_operand" "0,0,0")
2959 (parallel [(const_int 0) (const_int 1)]))
2960 (match_operand:V2SF 2 "nonimmediate_operand" "m,x,x")))]
2963 movhps\t{%2, %0|%0, %2}
2964 movlhps\t{%2, %0|%0, %2}
2965 movlps\t{%2, %H0|%H0, %2}"
2966 [(set_attr "type" "ssemov")
2967 (set_attr "mode" "V2SF,V4SF,V2SF")])
2969 (define_insn "*avx_storelps"
2970 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
2972 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
2973 (parallel [(const_int 0) (const_int 1)])))]
2976 vmovlps\t{%1, %0|%0, %1}
2977 vmovaps\t{%1, %0|%0, %1}
2978 vmovlps\t{%1, %0, %0|%0, %0, %1}"
2979 [(set_attr "type" "ssemov")
2980 (set_attr "prefix" "vex")
2981 (set_attr "mode" "V2SF,V2DF,V2SF")])
2983 (define_insn "sse_storelps"
2984 [(set (match_operand:V2SF 0 "nonimmediate_operand" "=m,x,x")
2986 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,m")
2987 (parallel [(const_int 0) (const_int 1)])))]
2990 movlps\t{%1, %0|%0, %1}
2991 movaps\t{%1, %0|%0, %1}
2992 movlps\t{%1, %0|%0, %1}"
2993 [(set_attr "type" "ssemov")
2994 (set_attr "mode" "V2SF,V4SF,V2SF")])
2996 (define_expand "sse_loadlps_exp"
2997 [(set (match_operand:V4SF 0 "nonimmediate_operand" "")
2999 (match_operand:V2SF 2 "nonimmediate_operand" "")
3001 (match_operand:V4SF 1 "nonimmediate_operand" "")
3002 (parallel [(const_int 2) (const_int 3)]))))]
3004 "ix86_fixup_binary_operands (UNKNOWN, V4SFmode, operands);")
3006 (define_insn "*avx_loadlps"
3007 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
3009 (match_operand:V2SF 2 "nonimmediate_operand" "x,m,x")
3011 (match_operand:V4SF 1 "nonimmediate_operand" "x,x,0")
3012 (parallel [(const_int 2) (const_int 3)]))))]
3015 shufps\t{$0xe4, %1, %2, %0|%0, %2, %1, 0xe4}
3016 vmovlps\t{%2, %1, %0|%0, %1, %2}
3017 vmovlps\t{%2, %0|%0, %2}"
3018 [(set_attr "type" "sselog,ssemov,ssemov")
3019 (set_attr "length_immediate" "1,*,*")
3020 (set_attr "prefix" "vex")
3021 (set_attr "mode" "V4SF,V2SF,V2SF")])
3023 (define_insn "sse_loadlps"
3024 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,m")
3026 (match_operand:V2SF 2 "nonimmediate_operand" "0,m,x")
3028 (match_operand:V4SF 1 "nonimmediate_operand" "x,0,0")
3029 (parallel [(const_int 2) (const_int 3)]))))]
3032 shufps\t{$0xe4, %1, %0|%0, %1, 0xe4}
3033 movlps\t{%2, %0|%0, %2}
3034 movlps\t{%2, %0|%0, %2}"
3035 [(set_attr "type" "sselog,ssemov,ssemov")
3036 (set_attr "length_immediate" "1,*,*")
3037 (set_attr "mode" "V4SF,V2SF,V2SF")])
3039 (define_insn "*avx_movss"
3040 [(set (match_operand:V4SF 0 "register_operand" "=x")
3042 (match_operand:V4SF 2 "register_operand" "x")
3043 (match_operand:V4SF 1 "register_operand" "x")
3046 "vmovss\t{%2, %1, %0|%0, %1, %2}"
3047 [(set_attr "type" "ssemov")
3048 (set_attr "prefix" "vex")
3049 (set_attr "mode" "SF")])
3051 (define_insn "sse_movss"
3052 [(set (match_operand:V4SF 0 "register_operand" "=x")
3054 (match_operand:V4SF 2 "register_operand" "x")
3055 (match_operand:V4SF 1 "register_operand" "0")
3058 "movss\t{%2, %0|%0, %2}"
3059 [(set_attr "type" "ssemov")
3060 (set_attr "mode" "SF")])
3062 (define_insn "*vec_dupv4sf_avx"
3063 [(set (match_operand:V4SF 0 "register_operand" "=x")
3065 (match_operand:SF 1 "register_operand" "x")))]
3067 "vshufps\t{$0, %1, %1, %0|%0, %1, %1, 0}"
3068 [(set_attr "type" "sselog1")
3069 (set_attr "length_immediate" "1")
3070 (set_attr "prefix" "vex")
3071 (set_attr "mode" "V4SF")])
3073 (define_insn "*vec_dupv4sf"
3074 [(set (match_operand:V4SF 0 "register_operand" "=x")
3076 (match_operand:SF 1 "register_operand" "0")))]
3078 "shufps\t{$0, %0, %0|%0, %0, 0}"
3079 [(set_attr "type" "sselog1")
3080 (set_attr "length_immediate" "1")
3081 (set_attr "mode" "V4SF")])
3083 (define_insn "*vec_concatv2sf_avx"
3084 [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y")
3086 (match_operand:SF 1 "nonimmediate_operand" " x,x,m, x , m")
3087 (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))]
3090 vunpcklps\t{%2, %1, %0|%0, %1, %2}
3091 vinsertps\t{$0x10, %2, %1, %0|%0, %1, %2, 0x10}
3092 vmovss\t{%1, %0|%0, %1}
3093 punpckldq\t{%2, %0|%0, %2}
3094 movd\t{%1, %0|%0, %1}"
3095 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
3096 (set_attr "length_immediate" "*,1,*,*,*")
3097 (set_attr "prefix_extra" "*,1,*,*,*")
3098 (set (attr "prefix")
3099 (if_then_else (eq_attr "alternative" "3,4")
3100 (const_string "orig")
3101 (const_string "vex")))
3102 (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
3104 ;; Although insertps takes register source, we prefer
3105 ;; unpcklps with register source since it is shorter.
3106 (define_insn "*vec_concatv2sf_sse4_1"
3107 [(set (match_operand:V2SF 0 "register_operand" "=x,x,x,*y ,*y")
3109 (match_operand:SF 1 "nonimmediate_operand" " 0,0,m, 0 , m")
3110 (match_operand:SF 2 "vector_move_operand" " x,m,C,*ym, C")))]
3113 unpcklps\t{%2, %0|%0, %2}
3114 insertps\t{$0x10, %2, %0|%0, %2, 0x10}
3115 movss\t{%1, %0|%0, %1}
3116 punpckldq\t{%2, %0|%0, %2}
3117 movd\t{%1, %0|%0, %1}"
3118 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
3119 (set_attr "prefix_data16" "*,1,*,*,*")
3120 (set_attr "prefix_extra" "*,1,*,*,*")
3121 (set_attr "length_immediate" "*,1,*,*,*")
3122 (set_attr "mode" "V4SF,V4SF,SF,DI,DI")])
3124 ;; ??? In theory we can match memory for the MMX alternative, but allowing
3125 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
3126 ;; alternatives pretty much forces the MMX alternative to be chosen.
3127 (define_insn "*vec_concatv2sf_sse"
3128 [(set (match_operand:V2SF 0 "register_operand" "=x,x,*y,*y")
3130 (match_operand:SF 1 "nonimmediate_operand" " 0,m, 0, m")
3131 (match_operand:SF 2 "reg_or_0_operand" " x,C,*y, C")))]
3134 unpcklps\t{%2, %0|%0, %2}
3135 movss\t{%1, %0|%0, %1}
3136 punpckldq\t{%2, %0|%0, %2}
3137 movd\t{%1, %0|%0, %1}"
3138 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
3139 (set_attr "mode" "V4SF,SF,DI,DI")])
3141 (define_insn "*vec_concatv4sf_avx"
3142 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
3144 (match_operand:V2SF 1 "register_operand" " x,x")
3145 (match_operand:V2SF 2 "nonimmediate_operand" " x,m")))]
3148 vmovlhps\t{%2, %1, %0|%0, %1, %2}
3149 vmovhps\t{%2, %1, %0|%0, %1, %2}"
3150 [(set_attr "type" "ssemov")
3151 (set_attr "prefix" "vex")
3152 (set_attr "mode" "V4SF,V2SF")])
3154 (define_insn "*vec_concatv4sf_sse"
3155 [(set (match_operand:V4SF 0 "register_operand" "=x,x")
3157 (match_operand:V2SF 1 "register_operand" " 0,0")
3158 (match_operand:V2SF 2 "nonimmediate_operand" " x,m")))]
3161 movlhps\t{%2, %0|%0, %2}
3162 movhps\t{%2, %0|%0, %2}"
3163 [(set_attr "type" "ssemov")
3164 (set_attr "mode" "V4SF,V2SF")])
3166 (define_expand "vec_init<mode>"
3167 [(match_operand:SSEMODE 0 "register_operand" "")
3168 (match_operand 1 "" "")]
3171 ix86_expand_vector_init (false, operands[0], operands[1]);
3175 (define_insn "*vec_setv4sf_0_avx"
3176 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,x,m")
3179 (match_operand:SF 2 "general_operand" " x,m,*r,x*rfF"))
3180 (match_operand:V4SF 1 "vector_move_operand" " x,C,C ,0")
3184 vmovss\t{%2, %1, %0|%0, %1, %2}
3185 vmovss\t{%2, %0|%0, %2}
3186 vmovd\t{%2, %0|%0, %2}
3188 [(set_attr "type" "ssemov")
3189 (set_attr "prefix" "vex")
3190 (set_attr "mode" "SF")])
3192 (define_insn "vec_setv4sf_0"
3193 [(set (match_operand:V4SF 0 "nonimmediate_operand" "=x,x,Y2,m")
3196 (match_operand:SF 2 "general_operand" " x,m,*r,x*rfF"))
3197 (match_operand:V4SF 1 "vector_move_operand" " 0,C,C ,0")
3201 movss\t{%2, %0|%0, %2}
3202 movss\t{%2, %0|%0, %2}
3203 movd\t{%2, %0|%0, %2}
3205 [(set_attr "type" "ssemov")
3206 (set_attr "mode" "SF")])
3208 ;; A subset is vec_setv4sf.
3209 (define_insn "*vec_setv4sf_avx"
3210 [(set (match_operand:V4SF 0 "register_operand" "=x")
3213 (match_operand:SF 2 "nonimmediate_operand" "xm"))
3214 (match_operand:V4SF 1 "register_operand" "x")
3215 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
3218 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
3219 return "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3221 [(set_attr "type" "sselog")
3222 (set_attr "prefix_extra" "1")
3223 (set_attr "length_immediate" "1")
3224 (set_attr "prefix" "vex")
3225 (set_attr "mode" "V4SF")])
3227 (define_insn "*vec_setv4sf_sse4_1"
3228 [(set (match_operand:V4SF 0 "register_operand" "=x")
3231 (match_operand:SF 2 "nonimmediate_operand" "xm"))
3232 (match_operand:V4SF 1 "register_operand" "0")
3233 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
3236 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])) << 4);
3237 return "insertps\t{%3, %2, %0|%0, %2, %3}";
3239 [(set_attr "type" "sselog")
3240 (set_attr "prefix_data16" "1")
3241 (set_attr "prefix_extra" "1")
3242 (set_attr "length_immediate" "1")
3243 (set_attr "mode" "V4SF")])
3245 (define_insn "*avx_insertps"
3246 [(set (match_operand:V4SF 0 "register_operand" "=x")
3247 (unspec:V4SF [(match_operand:V4SF 2 "nonimmediate_operand" "xm")
3248 (match_operand:V4SF 1 "register_operand" "x")
3249 (match_operand:SI 3 "const_0_to_255_operand" "n")]
3252 "vinsertps\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3253 [(set_attr "type" "sselog")
3254 (set_attr "prefix" "vex")
3255 (set_attr "prefix_extra" "1")
3256 (set_attr "length_immediate" "1")
3257 (set_attr "mode" "V4SF")])
3259 (define_insn "sse4_1_insertps"
3260 [(set (match_operand:V4SF 0 "register_operand" "=x")
3261 (unspec:V4SF [(match_operand:V4SF 2 "register_operand" "x")
3262 (match_operand:V4SF 1 "register_operand" "0")
3263 (match_operand:SI 3 "const_0_to_255_operand" "n")]
3266 "insertps\t{%3, %2, %0|%0, %2, %3}";
3267 [(set_attr "type" "sselog")
3268 (set_attr "prefix_data16" "1")
3269 (set_attr "prefix_extra" "1")
3270 (set_attr "length_immediate" "1")
3271 (set_attr "mode" "V4SF")])
3274 [(set (match_operand:V4SF 0 "memory_operand" "")
3277 (match_operand:SF 1 "nonmemory_operand" ""))
3280 "TARGET_SSE && reload_completed"
3283 emit_move_insn (adjust_address (operands[0], SFmode, 0), operands[1]);
3287 (define_expand "vec_set<mode>"
3288 [(match_operand:SSEMODE 0 "register_operand" "")
3289 (match_operand:<ssescalarmode> 1 "register_operand" "")
3290 (match_operand 2 "const_int_operand" "")]
3293 ix86_expand_vector_set (false, operands[0], operands[1],
3294 INTVAL (operands[2]));
3298 (define_insn_and_split "*vec_extractv4sf_0"
3299 [(set (match_operand:SF 0 "nonimmediate_operand" "=x,m,f,r")
3301 (match_operand:V4SF 1 "nonimmediate_operand" "xm,x,m,m")
3302 (parallel [(const_int 0)])))]
3303 "TARGET_SSE && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3305 "&& reload_completed"
3308 rtx op1 = operands[1];
3310 op1 = gen_rtx_REG (SFmode, REGNO (op1));
3312 op1 = gen_lowpart (SFmode, op1);
3313 emit_move_insn (operands[0], op1);
3317 (define_expand "avx_vextractf128<mode>"
3318 [(match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "")
3319 (match_operand:AVX256MODE 1 "register_operand" "")
3320 (match_operand:SI 2 "const_0_to_1_operand" "")]
3323 switch (INTVAL (operands[2]))
3326 emit_insn (gen_vec_extract_lo_<mode> (operands[0], operands[1]));
3329 emit_insn (gen_vec_extract_hi_<mode> (operands[0], operands[1]));
3337 (define_insn "vec_extract_lo_<mode>"
3338 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
3339 (vec_select:<avxhalfvecmode>
3340 (match_operand:AVX256MODE4P 1 "register_operand" "x,x")
3341 (parallel [(const_int 0) (const_int 1)])))]
3343 "vextractf128\t{$0x0, %1, %0|%0, %1, 0x0}"
3344 [(set_attr "type" "sselog")
3345 (set_attr "prefix_extra" "1")
3346 (set_attr "length_immediate" "1")
3347 (set_attr "memory" "none,store")
3348 (set_attr "prefix" "vex")
3349 (set_attr "mode" "V8SF")])
3351 (define_insn "vec_extract_hi_<mode>"
3352 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
3353 (vec_select:<avxhalfvecmode>
3354 (match_operand:AVX256MODE4P 1 "register_operand" "x,x")
3355 (parallel [(const_int 2) (const_int 3)])))]
3357 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3358 [(set_attr "type" "sselog")
3359 (set_attr "prefix_extra" "1")
3360 (set_attr "length_immediate" "1")
3361 (set_attr "memory" "none,store")
3362 (set_attr "prefix" "vex")
3363 (set_attr "mode" "V8SF")])
3365 (define_insn "vec_extract_lo_<mode>"
3366 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
3367 (vec_select:<avxhalfvecmode>
3368 (match_operand:AVX256MODE8P 1 "register_operand" "x,x")
3369 (parallel [(const_int 0) (const_int 1)
3370 (const_int 2) (const_int 3)])))]
3372 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3373 [(set_attr "type" "sselog")
3374 (set_attr "prefix_extra" "1")
3375 (set_attr "length_immediate" "1")
3376 (set_attr "memory" "none,store")
3377 (set_attr "prefix" "vex")
3378 (set_attr "mode" "V8SF")])
3380 (define_insn "vec_extract_hi_<mode>"
3381 [(set (match_operand:<avxhalfvecmode> 0 "nonimmediate_operand" "=x,m")
3382 (vec_select:<avxhalfvecmode>
3383 (match_operand:AVX256MODE8P 1 "register_operand" "x,x")
3384 (parallel [(const_int 4) (const_int 5)
3385 (const_int 6) (const_int 7)])))]
3387 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3388 [(set_attr "type" "sselog")
3389 (set_attr "prefix_extra" "1")
3390 (set_attr "length_immediate" "1")
3391 (set_attr "memory" "none,store")
3392 (set_attr "prefix" "vex")
3393 (set_attr "mode" "V8SF")])
3395 (define_insn "vec_extract_lo_v16hi"
3396 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
3398 (match_operand:V16HI 1 "register_operand" "x,x")
3399 (parallel [(const_int 0) (const_int 1)
3400 (const_int 2) (const_int 3)
3401 (const_int 4) (const_int 5)
3402 (const_int 6) (const_int 7)])))]
3404 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3405 [(set_attr "type" "sselog")
3406 (set_attr "prefix_extra" "1")
3407 (set_attr "length_immediate" "1")
3408 (set_attr "memory" "none,store")
3409 (set_attr "prefix" "vex")
3410 (set_attr "mode" "V8SF")])
3412 (define_insn "vec_extract_hi_v16hi"
3413 [(set (match_operand:V8HI 0 "nonimmediate_operand" "=x,m")
3415 (match_operand:V16HI 1 "register_operand" "x,x")
3416 (parallel [(const_int 8) (const_int 9)
3417 (const_int 10) (const_int 11)
3418 (const_int 12) (const_int 13)
3419 (const_int 14) (const_int 15)])))]
3421 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3422 [(set_attr "type" "sselog")
3423 (set_attr "prefix_extra" "1")
3424 (set_attr "length_immediate" "1")
3425 (set_attr "memory" "none,store")
3426 (set_attr "prefix" "vex")
3427 (set_attr "mode" "V8SF")])
3429 (define_insn "vec_extract_lo_v32qi"
3430 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
3432 (match_operand:V32QI 1 "register_operand" "x,x")
3433 (parallel [(const_int 0) (const_int 1)
3434 (const_int 2) (const_int 3)
3435 (const_int 4) (const_int 5)
3436 (const_int 6) (const_int 7)
3437 (const_int 8) (const_int 9)
3438 (const_int 10) (const_int 11)
3439 (const_int 12) (const_int 13)
3440 (const_int 14) (const_int 15)])))]
3442 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3443 [(set_attr "type" "sselog")
3444 (set_attr "prefix_extra" "1")
3445 (set_attr "length_immediate" "1")
3446 (set_attr "memory" "none,store")
3447 (set_attr "prefix" "vex")
3448 (set_attr "mode" "V8SF")])
3450 (define_insn "vec_extract_hi_v32qi"
3451 [(set (match_operand:V16QI 0 "nonimmediate_operand" "=x,m")
3453 (match_operand:V32QI 1 "register_operand" "x,x")
3454 (parallel [(const_int 16) (const_int 17)
3455 (const_int 18) (const_int 19)
3456 (const_int 20) (const_int 21)
3457 (const_int 22) (const_int 23)
3458 (const_int 24) (const_int 25)
3459 (const_int 26) (const_int 27)
3460 (const_int 28) (const_int 29)
3461 (const_int 30) (const_int 31)])))]
3463 "vextractf128\t{$0x1, %1, %0|%0, %1, 0x1}"
3464 [(set_attr "type" "sselog")
3465 (set_attr "prefix_extra" "1")
3466 (set_attr "length_immediate" "1")
3467 (set_attr "memory" "none,store")
3468 (set_attr "prefix" "vex")
3469 (set_attr "mode" "V8SF")])
3471 (define_insn "*sse4_1_extractps"
3472 [(set (match_operand:SF 0 "nonimmediate_operand" "=rm")
3474 (match_operand:V4SF 1 "register_operand" "x")
3475 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")])))]
3477 "%vextractps\t{%2, %1, %0|%0, %1, %2}"
3478 [(set_attr "type" "sselog")
3479 (set_attr "prefix_data16" "1")
3480 (set_attr "prefix_extra" "1")
3481 (set_attr "length_immediate" "1")
3482 (set_attr "prefix" "maybe_vex")
3483 (set_attr "mode" "V4SF")])
3485 (define_insn_and_split "*vec_extract_v4sf_mem"
3486 [(set (match_operand:SF 0 "register_operand" "=x*rf")
3488 (match_operand:V4SF 1 "memory_operand" "o")
3489 (parallel [(match_operand 2 "const_0_to_3_operand" "n")])))]
3495 int i = INTVAL (operands[2]);
3497 emit_move_insn (operands[0], adjust_address (operands[1], SFmode, i*4));
3501 (define_expand "vec_extract<mode>"
3502 [(match_operand:<ssescalarmode> 0 "register_operand" "")
3503 (match_operand:SSEMODE 1 "register_operand" "")
3504 (match_operand 2 "const_int_operand" "")]
3507 ix86_expand_vector_extract (false, operands[0], operands[1],
3508 INTVAL (operands[2]));
3512 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3514 ;; Parallel double-precision floating point element swizzling
3516 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
3518 (define_insn "avx_unpckhpd256"
3519 [(set (match_operand:V4DF 0 "register_operand" "=x")
3522 (match_operand:V4DF 1 "register_operand" "x")
3523 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
3524 (parallel [(const_int 1) (const_int 5)
3525 (const_int 3) (const_int 7)])))]
3527 "vunpckhpd\t{%2, %1, %0|%0, %1, %2}"
3528 [(set_attr "type" "sselog")
3529 (set_attr "prefix" "vex")
3530 (set_attr "mode" "V4DF")])
3532 (define_expand "sse2_unpckhpd_exp"
3533 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
3536 (match_operand:V2DF 1 "nonimmediate_operand" "")
3537 (match_operand:V2DF 2 "nonimmediate_operand" ""))
3538 (parallel [(const_int 1)
3541 "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
3543 (define_insn "*avx_unpckhpd"
3544 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
3547 (match_operand:V2DF 1 "nonimmediate_operand" " x,o,x")
3548 (match_operand:V2DF 2 "nonimmediate_operand" " x,x,0"))
3549 (parallel [(const_int 1)
3551 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3553 vunpckhpd\t{%2, %1, %0|%0, %1, %2}
3554 vmovlpd\t{%H1, %2, %0|%0, %2, %H1}
3555 vmovhpd\t{%1, %0|%0, %1}"
3556 [(set_attr "type" "sselog,ssemov,ssemov")
3557 (set_attr "prefix" "vex")
3558 (set_attr "mode" "V2DF,V1DF,V1DF")])
3560 (define_insn "sse2_unpckhpd"
3561 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m")
3564 (match_operand:V2DF 1 "nonimmediate_operand" " 0,o,x")
3565 (match_operand:V2DF 2 "nonimmediate_operand" " x,0,0"))
3566 (parallel [(const_int 1)
3568 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3570 unpckhpd\t{%2, %0|%0, %2}
3571 movlpd\t{%H1, %0|%0, %H1}
3572 movhpd\t{%1, %0|%0, %1}"
3573 [(set_attr "type" "sselog,ssemov,ssemov")
3574 (set_attr "prefix_data16" "*,1,1")
3575 (set_attr "mode" "V2DF,V1DF,V1DF")])
3577 (define_insn "avx_movddup256"
3578 [(set (match_operand:V4DF 0 "register_operand" "=x")
3581 (match_operand:V4DF 1 "nonimmediate_operand" "xm")
3583 (parallel [(const_int 0) (const_int 2)
3584 (const_int 4) (const_int 6)])))]
3586 "vmovddup\t{%1, %0|%0, %1}"
3587 [(set_attr "type" "sselog1")
3588 (set_attr "prefix" "vex")
3589 (set_attr "mode" "V4DF")])
3591 (define_insn "*avx_movddup"
3592 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,o")
3595 (match_operand:V2DF 1 "nonimmediate_operand" "xm,x")
3597 (parallel [(const_int 0)
3599 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3601 vmovddup\t{%1, %0|%0, %1}
3603 [(set_attr "type" "sselog1,ssemov")
3604 (set_attr "prefix" "vex")
3605 (set_attr "mode" "V2DF")])
3607 (define_insn "*sse3_movddup"
3608 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,o")
3611 (match_operand:V2DF 1 "nonimmediate_operand" "xm,x")
3613 (parallel [(const_int 0)
3615 "TARGET_SSE3 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3617 movddup\t{%1, %0|%0, %1}
3619 [(set_attr "type" "sselog1,ssemov")
3620 (set_attr "mode" "V2DF")])
3623 [(set (match_operand:V2DF 0 "memory_operand" "")
3626 (match_operand:V2DF 1 "register_operand" "")
3628 (parallel [(const_int 0)
3630 "TARGET_SSE3 && reload_completed"
3633 rtx low = gen_rtx_REG (DFmode, REGNO (operands[1]));
3634 emit_move_insn (adjust_address (operands[0], DFmode, 0), low);
3635 emit_move_insn (adjust_address (operands[0], DFmode, 8), low);
3639 (define_insn "avx_unpcklpd256"
3640 [(set (match_operand:V4DF 0 "register_operand" "=x")
3643 (match_operand:V4DF 1 "register_operand" "x")
3644 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
3645 (parallel [(const_int 0) (const_int 4)
3646 (const_int 2) (const_int 6)])))]
3648 "vunpcklpd\t{%2, %1, %0|%0, %1, %2}"
3649 [(set_attr "type" "sselog")
3650 (set_attr "prefix" "vex")
3651 (set_attr "mode" "V4DF")])
3653 (define_expand "sse2_unpcklpd_exp"
3654 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
3657 (match_operand:V2DF 1 "nonimmediate_operand" "")
3658 (match_operand:V2DF 2 "nonimmediate_operand" ""))
3659 (parallel [(const_int 0)
3662 "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
3664 (define_insn "*avx_unpcklpd"
3665 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o")
3668 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0")
3669 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x"))
3670 (parallel [(const_int 0)
3672 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3674 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
3675 vmovhpd\t{%2, %1, %0|%0, %1, %2}
3676 vmovlpd\t{%2, %H0|%H0, %2}"
3677 [(set_attr "type" "sselog,ssemov,ssemov")
3678 (set_attr "prefix" "vex")
3679 (set_attr "mode" "V2DF,V1DF,V1DF")])
3681 (define_insn "sse2_unpcklpd"
3682 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o")
3685 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0")
3686 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x"))
3687 (parallel [(const_int 0)
3689 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
3691 unpcklpd\t{%2, %0|%0, %2}
3692 movhpd\t{%2, %0|%0, %2}
3693 movlpd\t{%2, %H0|%H0, %2}"
3694 [(set_attr "type" "sselog,ssemov,ssemov")
3695 (set_attr "prefix_data16" "*,1,1")
3696 (set_attr "mode" "V2DF,V1DF,V1DF")])
3698 (define_expand "avx_shufpd256"
3699 [(match_operand:V4DF 0 "register_operand" "")
3700 (match_operand:V4DF 1 "register_operand" "")
3701 (match_operand:V4DF 2 "nonimmediate_operand" "")
3702 (match_operand:SI 3 "const_int_operand" "")]
3705 int mask = INTVAL (operands[3]);
3706 emit_insn (gen_avx_shufpd256_1 (operands[0], operands[1], operands[2],
3708 GEN_INT (mask & 2 ? 5 : 4),
3709 GEN_INT (mask & 4 ? 3 : 2),
3710 GEN_INT (mask & 8 ? 7 : 6)));
3714 (define_insn "avx_shufpd256_1"
3715 [(set (match_operand:V4DF 0 "register_operand" "=x")
3718 (match_operand:V4DF 1 "register_operand" "x")
3719 (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
3720 (parallel [(match_operand 3 "const_0_to_1_operand" "")
3721 (match_operand 4 "const_4_to_5_operand" "")
3722 (match_operand 5 "const_2_to_3_operand" "")
3723 (match_operand 6 "const_6_to_7_operand" "")])))]
3727 mask = INTVAL (operands[3]);
3728 mask |= (INTVAL (operands[4]) - 4) << 1;
3729 mask |= (INTVAL (operands[5]) - 2) << 2;
3730 mask |= (INTVAL (operands[6]) - 6) << 3;
3731 operands[3] = GEN_INT (mask);
3733 return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3735 [(set_attr "type" "sselog")
3736 (set_attr "length_immediate" "1")
3737 (set_attr "prefix" "vex")
3738 (set_attr "mode" "V4DF")])
3740 (define_expand "sse2_shufpd"
3741 [(match_operand:V2DF 0 "register_operand" "")
3742 (match_operand:V2DF 1 "register_operand" "")
3743 (match_operand:V2DF 2 "nonimmediate_operand" "")
3744 (match_operand:SI 3 "const_int_operand" "")]
3747 int mask = INTVAL (operands[3]);
3748 emit_insn (gen_sse2_shufpd_v2df (operands[0], operands[1], operands[2],
3750 GEN_INT (mask & 2 ? 3 : 2)));
3754 (define_expand "vec_extract_even<mode>"
3755 [(set (match_operand:SSEMODE4S 0 "register_operand" "")
3756 (vec_select:SSEMODE4S
3757 (vec_concat:<ssedoublesizemode>
3758 (match_operand:SSEMODE4S 1 "register_operand" "")
3759 (match_operand:SSEMODE4S 2 "nonimmediate_operand" ""))
3760 (parallel [(const_int 0)
3766 (define_expand "vec_extract_odd<mode>"
3767 [(set (match_operand:SSEMODE4S 0 "register_operand" "")
3768 (vec_select:SSEMODE4S
3769 (vec_concat:<ssedoublesizemode>
3770 (match_operand:SSEMODE4S 1 "register_operand" "")
3771 (match_operand:SSEMODE4S 2 "nonimmediate_operand" ""))
3772 (parallel [(const_int 1)
3778 (define_expand "vec_extract_even<mode>"
3779 [(set (match_operand:SSEMODE2D 0 "register_operand" "")
3780 (vec_select:SSEMODE2D
3781 (vec_concat:<ssedoublesizemode>
3782 (match_operand:SSEMODE2D 1 "register_operand" "")
3783 (match_operand:SSEMODE2D 2 "nonimmediate_operand" ""))
3784 (parallel [(const_int 0)
3788 (define_expand "vec_extract_odd<mode>"
3789 [(set (match_operand:SSEMODE2D 0 "register_operand" "")
3790 (vec_select:SSEMODE2D
3791 (vec_concat:<ssedoublesizemode>
3792 (match_operand:SSEMODE2D 1 "register_operand" "")
3793 (match_operand:SSEMODE2D 2 "nonimmediate_operand" ""))
3794 (parallel [(const_int 1)
3798 ;; punpcklqdq and punpckhqdq are shorter than shufpd.
3799 (define_insn "*avx_punpckhqdq"
3800 [(set (match_operand:V2DI 0 "register_operand" "=x")
3803 (match_operand:V2DI 1 "register_operand" "x")
3804 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
3805 (parallel [(const_int 1)
3808 "vpunpckhqdq\t{%2, %1, %0|%0, %1, %2}"
3809 [(set_attr "type" "sselog")
3810 (set_attr "prefix" "vex")
3811 (set_attr "mode" "TI")])
3813 (define_insn "sse2_punpckhqdq"
3814 [(set (match_operand:V2DI 0 "register_operand" "=x")
3817 (match_operand:V2DI 1 "register_operand" "0")
3818 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
3819 (parallel [(const_int 1)
3822 "punpckhqdq\t{%2, %0|%0, %2}"
3823 [(set_attr "type" "sselog")
3824 (set_attr "prefix_data16" "1")
3825 (set_attr "mode" "TI")])
3827 (define_insn "*avx_punpcklqdq"
3828 [(set (match_operand:V2DI 0 "register_operand" "=x")
3831 (match_operand:V2DI 1 "register_operand" "x")
3832 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
3833 (parallel [(const_int 0)
3836 "vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}"
3837 [(set_attr "type" "sselog")
3838 (set_attr "prefix" "vex")
3839 (set_attr "mode" "TI")])
3841 (define_insn "sse2_punpcklqdq"
3842 [(set (match_operand:V2DI 0 "register_operand" "=x")
3845 (match_operand:V2DI 1 "register_operand" "0")
3846 (match_operand:V2DI 2 "nonimmediate_operand" "xm"))
3847 (parallel [(const_int 0)
3850 "punpcklqdq\t{%2, %0|%0, %2}"
3851 [(set_attr "type" "sselog")
3852 (set_attr "prefix_data16" "1")
3853 (set_attr "mode" "TI")])
3855 (define_insn "*avx_shufpd_<mode>"
3856 [(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
3857 (vec_select:SSEMODE2D
3858 (vec_concat:<ssedoublesizemode>
3859 (match_operand:SSEMODE2D 1 "register_operand" "x")
3860 (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
3861 (parallel [(match_operand 3 "const_0_to_1_operand" "")
3862 (match_operand 4 "const_2_to_3_operand" "")])))]
3866 mask = INTVAL (operands[3]);
3867 mask |= (INTVAL (operands[4]) - 2) << 1;
3868 operands[3] = GEN_INT (mask);
3870 return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
3872 [(set_attr "type" "sselog")
3873 (set_attr "length_immediate" "1")
3874 (set_attr "prefix" "vex")
3875 (set_attr "mode" "V2DF")])
3877 (define_insn "sse2_shufpd_<mode>"
3878 [(set (match_operand:SSEMODE2D 0 "register_operand" "=x")
3879 (vec_select:SSEMODE2D
3880 (vec_concat:<ssedoublesizemode>
3881 (match_operand:SSEMODE2D 1 "register_operand" "0")
3882 (match_operand:SSEMODE2D 2 "nonimmediate_operand" "xm"))
3883 (parallel [(match_operand 3 "const_0_to_1_operand" "")
3884 (match_operand 4 "const_2_to_3_operand" "")])))]
3888 mask = INTVAL (operands[3]);
3889 mask |= (INTVAL (operands[4]) - 2) << 1;
3890 operands[3] = GEN_INT (mask);
3892 return "shufpd\t{%3, %2, %0|%0, %2, %3}";
3894 [(set_attr "type" "sselog")
3895 (set_attr "length_immediate" "1")
3896 (set_attr "mode" "V2DF")])
3898 ;; Avoid combining registers from different units in a single alternative,
3899 ;; see comment above inline_secondary_memory_needed function in i386.c
3900 (define_insn "*avx_storehpd"
3901 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
3903 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,o,o,o")
3904 (parallel [(const_int 1)])))]
3905 "TARGET_AVX && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3907 vmovhpd\t{%1, %0|%0, %1}
3908 vunpckhpd\t{%1, %1, %0|%0, %1, %1}
3912 [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
3913 (set_attr "prefix" "vex")
3914 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
3916 (define_insn "sse2_storehpd"
3917 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
3919 (match_operand:V2DF 1 "nonimmediate_operand" " x,0,o,o,o")
3920 (parallel [(const_int 1)])))]
3921 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3923 movhpd\t{%1, %0|%0, %1}
3928 [(set_attr "type" "ssemov,sselog1,ssemov,fmov,imov")
3929 (set_attr "prefix_data16" "1,*,*,*,*")
3930 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
3933 [(set (match_operand:DF 0 "register_operand" "")
3935 (match_operand:V2DF 1 "memory_operand" "")
3936 (parallel [(const_int 1)])))]
3937 "TARGET_SSE2 && reload_completed"
3938 [(set (match_dup 0) (match_dup 1))]
3940 operands[1] = adjust_address (operands[1], DFmode, 8);
3943 ;; Avoid combining registers from different units in a single alternative,
3944 ;; see comment above inline_secondary_memory_needed function in i386.c
3945 (define_insn "sse2_storelpd"
3946 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x,*f,r")
3948 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,m,m,m")
3949 (parallel [(const_int 0)])))]
3950 "TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
3952 %vmovlpd\t{%1, %0|%0, %1}
3957 [(set_attr "type" "ssemov,ssemov,ssemov,fmov,imov")
3958 (set_attr "prefix_data16" "1,*,*,*,*")
3959 (set_attr "prefix" "maybe_vex")
3960 (set_attr "mode" "V1DF,DF,DF,DF,DF")])
3963 [(set (match_operand:DF 0 "register_operand" "")
3965 (match_operand:V2DF 1 "nonimmediate_operand" "")
3966 (parallel [(const_int 0)])))]
3967 "TARGET_SSE2 && reload_completed"
3970 rtx op1 = operands[1];
3972 op1 = gen_rtx_REG (DFmode, REGNO (op1));
3974 op1 = gen_lowpart (DFmode, op1);
3975 emit_move_insn (operands[0], op1);
3979 (define_expand "sse2_loadhpd_exp"
3980 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
3983 (match_operand:V2DF 1 "nonimmediate_operand" "")
3984 (parallel [(const_int 0)]))
3985 (match_operand:DF 2 "nonimmediate_operand" "")))]
3987 "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
3989 ;; Avoid combining registers from different units in a single alternative,
3990 ;; see comment above inline_secondary_memory_needed function in i386.c
3991 (define_insn "*avx_loadhpd"
3992 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,o,o,o")
3995 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,0,0")
3996 (parallel [(const_int 0)]))
3997 (match_operand:DF 2 "nonimmediate_operand" " m,x,x,*f,r")))]
3998 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4000 vmovhpd\t{%2, %1, %0|%0, %1, %2}
4001 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
4005 [(set_attr "type" "ssemov,sselog,ssemov,fmov,imov")
4006 (set_attr "prefix" "vex")
4007 (set_attr "mode" "V1DF,V2DF,DF,DF,DF")])
4009 (define_insn "sse2_loadhpd"
4010 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,o,o,o")
4013 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,x,0,0,0")
4014 (parallel [(const_int 0)]))
4015 (match_operand:DF 2 "nonimmediate_operand" " m,x,0,x,*f,r")))]
4016 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4018 movhpd\t{%2, %0|%0, %2}
4019 unpcklpd\t{%2, %0|%0, %2}
4020 shufpd\t{$1, %1, %0|%0, %1, 1}
4024 [(set_attr "type" "ssemov,sselog,sselog,ssemov,fmov,imov")
4025 (set_attr "prefix_data16" "1,*,*,*,*,*")
4026 (set_attr "length_immediate" "*,*,1,*,*,*")
4027 (set_attr "mode" "V1DF,V2DF,V2DF,DF,DF,DF")])
4030 [(set (match_operand:V2DF 0 "memory_operand" "")
4032 (vec_select:DF (match_dup 0) (parallel [(const_int 0)]))
4033 (match_operand:DF 1 "register_operand" "")))]
4034 "TARGET_SSE2 && reload_completed"
4035 [(set (match_dup 0) (match_dup 1))]
4037 operands[0] = adjust_address (operands[0], DFmode, 8);
4040 (define_expand "sse2_loadlpd_exp"
4041 [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
4043 (match_operand:DF 2 "nonimmediate_operand" "")
4045 (match_operand:V2DF 1 "nonimmediate_operand" "")
4046 (parallel [(const_int 1)]))))]
4048 "ix86_fixup_binary_operands (UNKNOWN, V2DFmode, operands);")
4050 ;; Avoid combining registers from different units in a single alternative,
4051 ;; see comment above inline_secondary_memory_needed function in i386.c
4052 (define_insn "*avx_loadlpd"
4053 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,m,m,m")
4055 (match_operand:DF 2 "nonimmediate_operand" " m,m,x,x,x,*f,r")
4057 (match_operand:V2DF 1 "vector_move_operand" " C,x,x,o,0,0,0")
4058 (parallel [(const_int 1)]))))]
4059 "TARGET_AVX && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4061 vmovsd\t{%2, %0|%0, %2}
4062 vmovlpd\t{%2, %1, %0|%0, %1, %2}
4063 vmovsd\t{%2, %1, %0|%0, %1, %2}
4064 vmovhpd\t{%H1, %2, %0|%0, %2, %H1}
4068 [(set_attr "type" "ssemov,ssemov,ssemov,ssemov,ssemov,fmov,imov")
4069 (set_attr "prefix" "vex")
4070 (set_attr "mode" "DF,V1DF,V1DF,V1DF,DF,DF,DF")])
4072 (define_insn "sse2_loadlpd"
4073 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,x,x,x,m,m,m")
4075 (match_operand:DF 2 "nonimmediate_operand" " m,m,x,0,0,x,*f,r")
4077 (match_operand:V2DF 1 "vector_move_operand" " C,0,0,x,o,0,0,0")
4078 (parallel [(const_int 1)]))))]
4079 "TARGET_SSE2 && !(MEM_P (operands[1]) && MEM_P (operands[2]))"
4081 movsd\t{%2, %0|%0, %2}
4082 movlpd\t{%2, %0|%0, %2}
4083 movsd\t{%2, %0|%0, %2}
4084 shufpd\t{$2, %2, %0|%0, %2, 2}
4085 movhpd\t{%H1, %0|%0, %H1}
4089 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov,fmov,imov")
4090 (set_attr "prefix_data16" "*,1,*,*,1,*,*,*")
4091 (set_attr "length_immediate" "*,*,*,1,*,*,*,*")
4092 (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,DF,DF,DF")])
4095 [(set (match_operand:V2DF 0 "memory_operand" "")
4097 (match_operand:DF 1 "register_operand" "")
4098 (vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))]
4099 "TARGET_SSE2 && reload_completed"
4100 [(set (match_dup 0) (match_dup 1))]
4102 operands[0] = adjust_address (operands[0], DFmode, 8);
4105 ;; Not sure these two are ever used, but it doesn't hurt to have
4107 (define_insn "*vec_extractv2df_1_sse"
4108 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
4110 (match_operand:V2DF 1 "nonimmediate_operand" "x,x,o")
4111 (parallel [(const_int 1)])))]
4112 "!TARGET_SSE2 && TARGET_SSE
4113 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4115 movhps\t{%1, %0|%0, %1}
4116 movhlps\t{%1, %0|%0, %1}
4117 movlps\t{%H1, %0|%0, %H1}"
4118 [(set_attr "type" "ssemov")
4119 (set_attr "mode" "V2SF,V4SF,V2SF")])
4121 (define_insn "*vec_extractv2df_0_sse"
4122 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,x,x")
4124 (match_operand:V2DF 1 "nonimmediate_operand" "x,x,m")
4125 (parallel [(const_int 0)])))]
4126 "!TARGET_SSE2 && TARGET_SSE
4127 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
4129 movlps\t{%1, %0|%0, %1}
4130 movaps\t{%1, %0|%0, %1}
4131 movlps\t{%1, %0|%0, %1}"
4132 [(set_attr "type" "ssemov")
4133 (set_attr "mode" "V2SF,V4SF,V2SF")])
4135 (define_insn "*avx_movsd"
4136 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,o")
4138 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,x,0")
4139 (match_operand:V2DF 1 "nonimmediate_operand" " x,x,0,o,x")
4143 vmovsd\t{%2, %1, %0|%0, %1, %2}
4144 vmovlpd\t{%2, %1, %0|%0, %1, %2}
4145 vmovlpd\t{%2, %0|%0, %2}
4146 vmovhps\t{%H1, %2, %0|%0, %2, %H1}
4147 vmovhps\t{%1, %H0|%H0, %1}"
4148 [(set_attr "type" "ssemov,ssemov,ssemov,ssemov,ssemov")
4149 (set_attr "prefix" "vex")
4150 (set_attr "mode" "DF,V1DF,V1DF,V1DF,V1DF")])
4152 (define_insn "sse2_movsd"
4153 [(set (match_operand:V2DF 0 "nonimmediate_operand" "=x,x,m,x,x,o")
4155 (match_operand:V2DF 2 "nonimmediate_operand" " x,m,x,0,0,0")
4156 (match_operand:V2DF 1 "nonimmediate_operand" " 0,0,0,x,o,x")
4160 movsd\t{%2, %0|%0, %2}
4161 movlpd\t{%2, %0|%0, %2}
4162 movlpd\t{%2, %0|%0, %2}
4163 shufpd\t{$2, %2, %0|%0, %2, 2}
4164 movhps\t{%H1, %0|%0, %H1}
4165 movhps\t{%1, %H0|%H0, %1}"
4166 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
4167 (set_attr "prefix_data16" "*,1,1,*,*,*")
4168 (set_attr "length_immediate" "*,*,*,1,*,*")
4169 (set_attr "mode" "DF,V1DF,V1DF,V2DF,V1DF,V1DF")])
4171 (define_insn "*vec_dupv2df_sse3"
4172 [(set (match_operand:V2DF 0 "register_operand" "=x")
4174 (match_operand:DF 1 "nonimmediate_operand" "xm")))]
4176 "%vmovddup\t{%1, %0|%0, %1}"
4177 [(set_attr "type" "sselog1")
4178 (set_attr "prefix" "maybe_vex")
4179 (set_attr "mode" "DF")])
4181 (define_insn "vec_dupv2df"
4182 [(set (match_operand:V2DF 0 "register_operand" "=x")
4184 (match_operand:DF 1 "register_operand" "0")))]
4187 [(set_attr "type" "sselog1")
4188 (set_attr "mode" "V2DF")])
4190 (define_insn "*vec_concatv2df_sse3"
4191 [(set (match_operand:V2DF 0 "register_operand" "=x")
4193 (match_operand:DF 1 "nonimmediate_operand" "xm")
4196 "%vmovddup\t{%1, %0|%0, %1}"
4197 [(set_attr "type" "sselog1")
4198 (set_attr "prefix" "maybe_vex")
4199 (set_attr "mode" "DF")])
4201 (define_insn "*vec_concatv2df_avx"
4202 [(set (match_operand:V2DF 0 "register_operand" "=x,x,x")
4204 (match_operand:DF 1 "nonimmediate_operand" " x,x,m")
4205 (match_operand:DF 2 "vector_move_operand" " x,m,C")))]
4208 vunpcklpd\t{%2, %1, %0|%0, %1, %2}
4209 vmovhpd\t{%2, %1, %0|%0, %1, %2}
4210 vmovsd\t{%1, %0|%0, %1}"
4211 [(set_attr "type" "ssemov")
4212 (set_attr "prefix" "vex")
4213 (set_attr "mode" "DF,V1DF,DF")])
4215 (define_insn "*vec_concatv2df"
4216 [(set (match_operand:V2DF 0 "register_operand" "=Y2,Y2,Y2,x,x")
4218 (match_operand:DF 1 "nonimmediate_operand" " 0 ,0 ,m ,0,0")
4219 (match_operand:DF 2 "vector_move_operand" " Y2,m ,C ,x,m")))]
4222 unpcklpd\t{%2, %0|%0, %2}
4223 movhpd\t{%2, %0|%0, %2}
4224 movsd\t{%1, %0|%0, %1}
4225 movlhps\t{%2, %0|%0, %2}
4226 movhps\t{%2, %0|%0, %2}"
4227 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,ssemov")
4228 (set_attr "prefix_data16" "*,1,*,*,*")
4229 (set_attr "mode" "V2DF,V1DF,DF,V4SF,V2SF")])
4231 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4233 ;; Parallel integral arithmetic
4235 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
4237 (define_expand "neg<mode>2"
4238 [(set (match_operand:SSEMODEI 0 "register_operand" "")
4241 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")))]
4243 "operands[2] = force_reg (<MODE>mode, CONST0_RTX (<MODE>mode));")
4245 (define_expand "<plusminus_insn><mode>3"
4246 [(set (match_operand:SSEMODEI 0 "register_operand" "")
4248 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
4249 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
4251 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
4253 (define_insn "*avx_<plusminus_insn><mode>3"
4254 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
4256 (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>x")
4257 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
4258 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4259 "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
4260 [(set_attr "type" "sseiadd")
4261 (set_attr "prefix" "vex")
4262 (set_attr "mode" "TI")])
4264 (define_insn "*<plusminus_insn><mode>3"
4265 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
4267 (match_operand:SSEMODEI 1 "nonimmediate_operand" "<comm>0")
4268 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
4269 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4270 "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
4271 [(set_attr "type" "sseiadd")
4272 (set_attr "prefix_data16" "1")
4273 (set_attr "mode" "TI")])
4275 (define_expand "sse2_<plusminus_insn><mode>3"
4276 [(set (match_operand:SSEMODE12 0 "register_operand" "")
4277 (sat_plusminus:SSEMODE12
4278 (match_operand:SSEMODE12 1 "nonimmediate_operand" "")
4279 (match_operand:SSEMODE12 2 "nonimmediate_operand" "")))]
4281 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
4283 (define_insn "*avx_<plusminus_insn><mode>3"
4284 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
4285 (sat_plusminus:SSEMODE12
4286 (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>x")
4287 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
4288 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4289 "vp<plusminus_mnemonic><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
4290 [(set_attr "type" "sseiadd")
4291 (set_attr "prefix" "vex")
4292 (set_attr "mode" "TI")])
4294 (define_insn "*sse2_<plusminus_insn><mode>3"
4295 [(set (match_operand:SSEMODE12 0 "register_operand" "=x")
4296 (sat_plusminus:SSEMODE12
4297 (match_operand:SSEMODE12 1 "nonimmediate_operand" "<comm>0")
4298 (match_operand:SSEMODE12 2 "nonimmediate_operand" "xm")))]
4299 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
4300 "p<plusminus_mnemonic><ssevecsize>\t{%2, %0|%0, %2}"
4301 [(set_attr "type" "sseiadd")
4302 (set_attr "prefix_data16" "1")
4303 (set_attr "mode" "TI")])
4305 (define_insn_and_split "mulv16qi3"
4306 [(set (match_operand:V16QI 0 "register_operand" "")
4307 (mult:V16QI (match_operand:V16QI 1 "register_operand" "")
4308 (match_operand:V16QI 2 "register_operand" "")))]
4310 && can_create_pseudo_p ()"
4318 for (i = 0; i < 12; ++i)
4319 t[i] = gen_reg_rtx (V16QImode);
4321 /* Unpack data such that we've got a source byte in each low byte of
4322 each word. We don't care what goes into the high byte of each word.
4323 Rather than trying to get zero in there, most convenient is to let
4324 it be a copy of the low byte. */
4325 emit_insn (gen_sse2_punpckhbw (t[0], operands[1], operands[1]));
4326 emit_insn (gen_sse2_punpckhbw (t[1], operands[2], operands[2]));
4327 emit_insn (gen_sse2_punpcklbw (t[2], operands[1], operands[1]));
4328 emit_insn (gen_sse2_punpcklbw (t[3], operands[2], operands[2]));
4330 /* Multiply words. The end-of-line annotations here give a picture of what
4331 the output of that instruction looks like. Dot means don't care; the
4332 letters are the bytes of the result with A being the most significant. */
4333 emit_insn (gen_mulv8hi3 (gen_lowpart (V8HImode, t[4]), /* .A.B.C.D.E.F.G.H */
4334 gen_lowpart (V8HImode, t[0]),
4335 gen_lowpart (V8HImode, t[1])));
4336 emit_insn (gen_mulv8hi3 (gen_lowpart (V8HImode, t[5]), /* .I.J.K.L.M.N.O.P */
4337 gen_lowpart (V8HImode, t[2]),
4338 gen_lowpart (V8HImode, t[3])));
4340 /* Extract the relevant bytes and merge them back together. */
4341 emit_insn (gen_sse2_punpckhbw (t[6], t[5], t[4])); /* ..AI..BJ..CK..DL */
4342 emit_insn (gen_sse2_punpcklbw (t[7], t[5], t[4])); /* ..EM..FN..GO..HP */
4343 emit_insn (gen_sse2_punpckhbw (t[8], t[7], t[6])); /* ....AEIM....BFJN */
4344 emit_insn (gen_sse2_punpcklbw (t[9], t[7], t[6])); /* ....CGKO....DHLP */
4345 emit_insn (gen_sse2_punpckhbw (t[10], t[9], t[8])); /* ........ACEGIKMO */
4346 emit_insn (gen_sse2_punpcklbw (t[11], t[9], t[8])); /* ........BDFHJLNP */
4348 emit_insn (gen_sse2_punpcklbw (operands[0], t[11], t[10])); /* ABCDEFGHIJKLMNOP */
4352 (define_expand "mulv8hi3"
4353 [(set (match_operand:V8HI 0 "register_operand" "")
4354 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
4355 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
4357 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
4359 (define_insn "*avx_mulv8hi3"
4360 [(set (match_operand:V8HI 0 "register_operand" "=x")
4361 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x")
4362 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
4363 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4364 "vpmullw\t{%2, %1, %0|%0, %1, %2}"
4365 [(set_attr "type" "sseimul")
4366 (set_attr "prefix" "vex")
4367 (set_attr "mode" "TI")])
4369 (define_insn "*mulv8hi3"
4370 [(set (match_operand:V8HI 0 "register_operand" "=x")
4371 (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%0")
4372 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
4373 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4374 "pmullw\t{%2, %0|%0, %2}"
4375 [(set_attr "type" "sseimul")
4376 (set_attr "prefix_data16" "1")
4377 (set_attr "mode" "TI")])
4379 (define_expand "smulv8hi3_highpart"
4380 [(set (match_operand:V8HI 0 "register_operand" "")
4385 (match_operand:V8HI 1 "nonimmediate_operand" ""))
4387 (match_operand:V8HI 2 "nonimmediate_operand" "")))
4390 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
4392 (define_insn "*avxv8hi3_highpart"
4393 [(set (match_operand:V8HI 0 "register_operand" "=x")
4398 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
4400 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
4402 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4403 "vpmulhw\t{%2, %1, %0|%0, %1, %2}"
4404 [(set_attr "type" "sseimul")
4405 (set_attr "prefix" "vex")
4406 (set_attr "mode" "TI")])
4408 (define_insn "*smulv8hi3_highpart"
4409 [(set (match_operand:V8HI 0 "register_operand" "=x")
4414 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
4416 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
4418 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4419 "pmulhw\t{%2, %0|%0, %2}"
4420 [(set_attr "type" "sseimul")
4421 (set_attr "prefix_data16" "1")
4422 (set_attr "mode" "TI")])
4424 (define_expand "umulv8hi3_highpart"
4425 [(set (match_operand:V8HI 0 "register_operand" "")
4430 (match_operand:V8HI 1 "nonimmediate_operand" ""))
4432 (match_operand:V8HI 2 "nonimmediate_operand" "")))
4435 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
4437 (define_insn "*avx_umulv8hi3_highpart"
4438 [(set (match_operand:V8HI 0 "register_operand" "=x")
4443 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
4445 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
4447 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4448 "vpmulhuw\t{%2, %1, %0|%0, %1, %2}"
4449 [(set_attr "type" "sseimul")
4450 (set_attr "prefix" "vex")
4451 (set_attr "mode" "TI")])
4453 (define_insn "*umulv8hi3_highpart"
4454 [(set (match_operand:V8HI 0 "register_operand" "=x")
4459 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
4461 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
4463 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4464 "pmulhuw\t{%2, %0|%0, %2}"
4465 [(set_attr "type" "sseimul")
4466 (set_attr "prefix_data16" "1")
4467 (set_attr "mode" "TI")])
4469 (define_expand "sse2_umulv2siv2di3"
4470 [(set (match_operand:V2DI 0 "register_operand" "")
4474 (match_operand:V4SI 1 "nonimmediate_operand" "")
4475 (parallel [(const_int 0) (const_int 2)])))
4478 (match_operand:V4SI 2 "nonimmediate_operand" "")
4479 (parallel [(const_int 0) (const_int 2)])))))]
4481 "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
4483 (define_insn "*avx_umulv2siv2di3"
4484 [(set (match_operand:V2DI 0 "register_operand" "=x")
4488 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
4489 (parallel [(const_int 0) (const_int 2)])))
4492 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
4493 (parallel [(const_int 0) (const_int 2)])))))]
4494 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
4495 "vpmuludq\t{%2, %1, %0|%0, %1, %2}"
4496 [(set_attr "type" "sseimul")
4497 (set_attr "prefix" "vex")
4498 (set_attr "mode" "TI")])
4500 (define_insn "*sse2_umulv2siv2di3"
4501 [(set (match_operand:V2DI 0 "register_operand" "=x")
4505 (match_operand:V4SI 1 "nonimmediate_operand" "%0")
4506 (parallel [(const_int 0) (const_int 2)])))
4509 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
4510 (parallel [(const_int 0) (const_int 2)])))))]
4511 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
4512 "pmuludq\t{%2, %0|%0, %2}"
4513 [(set_attr "type" "sseimul")
4514 (set_attr "prefix_data16" "1")
4515 (set_attr "mode" "TI")])
4517 (define_expand "sse4_1_mulv2siv2di3"
4518 [(set (match_operand:V2DI 0 "register_operand" "")
4522 (match_operand:V4SI 1 "nonimmediate_operand" "")
4523 (parallel [(const_int 0) (const_int 2)])))
4526 (match_operand:V4SI 2 "nonimmediate_operand" "")
4527 (parallel [(const_int 0) (const_int 2)])))))]
4529 "ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);")
4531 (define_insn "*avx_mulv2siv2di3"
4532 [(set (match_operand:V2DI 0 "register_operand" "=x")
4536 (match_operand:V4SI 1 "nonimmediate_operand" "%x")
4537 (parallel [(const_int 0) (const_int 2)])))
4540 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
4541 (parallel [(const_int 0) (const_int 2)])))))]
4542 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
4543 "vpmuldq\t{%2, %1, %0|%0, %1, %2}"
4544 [(set_attr "type" "sseimul")
4545 (set_attr "prefix_extra" "1")
4546 (set_attr "prefix" "vex")
4547 (set_attr "mode" "TI")])
4549 (define_insn "*sse4_1_mulv2siv2di3"
4550 [(set (match_operand:V2DI 0 "register_operand" "=x")
4554 (match_operand:V4SI 1 "nonimmediate_operand" "%0")
4555 (parallel [(const_int 0) (const_int 2)])))
4558 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
4559 (parallel [(const_int 0) (const_int 2)])))))]
4560 "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
4561 "pmuldq\t{%2, %0|%0, %2}"
4562 [(set_attr "type" "sseimul")
4563 (set_attr "prefix_extra" "1")
4564 (set_attr "mode" "TI")])
4566 (define_expand "sse2_pmaddwd"
4567 [(set (match_operand:V4SI 0 "register_operand" "")
4572 (match_operand:V8HI 1 "nonimmediate_operand" "")
4573 (parallel [(const_int 0)
4579 (match_operand:V8HI 2 "nonimmediate_operand" "")
4580 (parallel [(const_int 0)
4586 (vec_select:V4HI (match_dup 1)
4587 (parallel [(const_int 1)
4592 (vec_select:V4HI (match_dup 2)
4593 (parallel [(const_int 1)
4596 (const_int 7)]))))))]
4598 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
4600 (define_insn "*avx_pmaddwd"
4601 [(set (match_operand:V4SI 0 "register_operand" "=x")
4606 (match_operand:V8HI 1 "nonimmediate_operand" "%x")
4607 (parallel [(const_int 0)
4613 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
4614 (parallel [(const_int 0)
4620 (vec_select:V4HI (match_dup 1)
4621 (parallel [(const_int 1)
4626 (vec_select:V4HI (match_dup 2)
4627 (parallel [(const_int 1)
4630 (const_int 7)]))))))]
4631 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4632 "vpmaddwd\t{%2, %1, %0|%0, %1, %2}"
4633 [(set_attr "type" "sseiadd")
4634 (set_attr "prefix" "vex")
4635 (set_attr "mode" "TI")])
4637 (define_insn "*sse2_pmaddwd"
4638 [(set (match_operand:V4SI 0 "register_operand" "=x")
4643 (match_operand:V8HI 1 "nonimmediate_operand" "%0")
4644 (parallel [(const_int 0)
4650 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
4651 (parallel [(const_int 0)
4657 (vec_select:V4HI (match_dup 1)
4658 (parallel [(const_int 1)
4663 (vec_select:V4HI (match_dup 2)
4664 (parallel [(const_int 1)
4667 (const_int 7)]))))))]
4668 "TARGET_SSE2 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
4669 "pmaddwd\t{%2, %0|%0, %2}"
4670 [(set_attr "type" "sseiadd")
4671 (set_attr "atom_unit" "simul")
4672 (set_attr "prefix_data16" "1")
4673 (set_attr "mode" "TI")])
4675 (define_expand "mulv4si3"
4676 [(set (match_operand:V4SI 0 "register_operand" "")
4677 (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
4678 (match_operand:V4SI 2 "register_operand" "")))]
4682 ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);
4685 (define_insn "*avx_mulv4si3"
4686 [(set (match_operand:V4SI 0 "register_operand" "=x")
4687 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x")
4688 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
4689 "TARGET_AVX && ix86_binary_operator_ok (MULT, V4SImode, operands)"
4690 "vpmulld\t{%2, %1, %0|%0, %1, %2}"
4691 [(set_attr "type" "sseimul")
4692 (set_attr "prefix_extra" "1")
4693 (set_attr "prefix" "vex")
4694 (set_attr "mode" "TI")])
4696 (define_insn "*sse4_1_mulv4si3"
4697 [(set (match_operand:V4SI 0 "register_operand" "=x")
4698 (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%0")
4699 (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
4700 "TARGET_SSE4_1 && ix86_binary_operator_ok (MULT, V4SImode, operands)"
4701 "pmulld\t{%2, %0|%0, %2}"
4702 [(set_attr "type" "sseimul")
4703 (set_attr "prefix_extra" "1")
4704 (set_attr "mode" "TI")])
4706 (define_insn_and_split "*sse2_mulv4si3"
4707 [(set (match_operand:V4SI 0 "register_operand" "")
4708 (mult:V4SI (match_operand:V4SI 1 "register_operand" "")
4709 (match_operand:V4SI 2 "register_operand" "")))]
4710 "TARGET_SSE2 && !TARGET_SSE4_1
4711 && can_create_pseudo_p ()"
4716 rtx t1, t2, t3, t4, t5, t6, thirtytwo;
4722 t1 = gen_reg_rtx (V4SImode);
4723 t2 = gen_reg_rtx (V4SImode);
4724 t3 = gen_reg_rtx (V4SImode);
4725 t4 = gen_reg_rtx (V4SImode);
4726 t5 = gen_reg_rtx (V4SImode);
4727 t6 = gen_reg_rtx (V4SImode);
4728 thirtytwo = GEN_INT (32);
4730 /* Multiply elements 2 and 0. */
4731 emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t1),
4734 /* Shift both input vectors down one element, so that elements 3
4735 and 1 are now in the slots for elements 2 and 0. For K8, at
4736 least, this is faster than using a shuffle. */
4737 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t2),
4738 gen_lowpart (TImode, op1),
4740 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t3),
4741 gen_lowpart (TImode, op2),
4743 /* Multiply elements 3 and 1. */
4744 emit_insn (gen_sse2_umulv2siv2di3 (gen_lowpart (V2DImode, t4),
4747 /* Move the results in element 2 down to element 1; we don't care
4748 what goes in elements 2 and 3. */
4749 emit_insn (gen_sse2_pshufd_1 (t5, t1, const0_rtx, const2_rtx,
4750 const0_rtx, const0_rtx));
4751 emit_insn (gen_sse2_pshufd_1 (t6, t4, const0_rtx, const2_rtx,
4752 const0_rtx, const0_rtx));
4754 /* Merge the parts back together. */
4755 emit_insn (gen_sse2_punpckldq (op0, t5, t6));
4759 (define_insn_and_split "mulv2di3"
4760 [(set (match_operand:V2DI 0 "register_operand" "")
4761 (mult:V2DI (match_operand:V2DI 1 "register_operand" "")
4762 (match_operand:V2DI 2 "register_operand" "")))]
4764 && can_create_pseudo_p ()"
4769 rtx t1, t2, t3, t4, t5, t6, thirtytwo;
4775 t1 = gen_reg_rtx (V2DImode);
4776 t2 = gen_reg_rtx (V2DImode);
4777 t3 = gen_reg_rtx (V2DImode);
4778 t4 = gen_reg_rtx (V2DImode);
4779 t5 = gen_reg_rtx (V2DImode);
4780 t6 = gen_reg_rtx (V2DImode);
4781 thirtytwo = GEN_INT (32);
4783 /* Multiply low parts. */
4784 emit_insn (gen_sse2_umulv2siv2di3 (t1, gen_lowpart (V4SImode, op1),
4785 gen_lowpart (V4SImode, op2)));
4787 /* Shift input vectors left 32 bits so we can multiply high parts. */
4788 emit_insn (gen_lshrv2di3 (t2, op1, thirtytwo));
4789 emit_insn (gen_lshrv2di3 (t3, op2, thirtytwo));
4791 /* Multiply high parts by low parts. */
4792 emit_insn (gen_sse2_umulv2siv2di3 (t4, gen_lowpart (V4SImode, op1),
4793 gen_lowpart (V4SImode, t3)));
4794 emit_insn (gen_sse2_umulv2siv2di3 (t5, gen_lowpart (V4SImode, op2),
4795 gen_lowpart (V4SImode, t2)));
4797 /* Shift them back. */
4798 emit_insn (gen_ashlv2di3 (t4, t4, thirtytwo));
4799 emit_insn (gen_ashlv2di3 (t5, t5, thirtytwo));
4801 /* Add the three parts together. */
4802 emit_insn (gen_addv2di3 (t6, t1, t4));
4803 emit_insn (gen_addv2di3 (op0, t6, t5));
4807 (define_expand "vec_widen_smult_hi_v8hi"
4808 [(match_operand:V4SI 0 "register_operand" "")
4809 (match_operand:V8HI 1 "register_operand" "")
4810 (match_operand:V8HI 2 "register_operand" "")]
4813 rtx op1, op2, t1, t2, dest;
4817 t1 = gen_reg_rtx (V8HImode);
4818 t2 = gen_reg_rtx (V8HImode);
4819 dest = gen_lowpart (V8HImode, operands[0]);
4821 emit_insn (gen_mulv8hi3 (t1, op1, op2));
4822 emit_insn (gen_smulv8hi3_highpart (t2, op1, op2));
4823 emit_insn (gen_vec_interleave_highv8hi (dest, t1, t2));
4827 (define_expand "vec_widen_smult_lo_v8hi"
4828 [(match_operand:V4SI 0 "register_operand" "")
4829 (match_operand:V8HI 1 "register_operand" "")
4830 (match_operand:V8HI 2 "register_operand" "")]
4833 rtx op1, op2, t1, t2, dest;
4837 t1 = gen_reg_rtx (V8HImode);
4838 t2 = gen_reg_rtx (V8HImode);
4839 dest = gen_lowpart (V8HImode, operands[0]);
4841 emit_insn (gen_mulv8hi3 (t1, op1, op2));
4842 emit_insn (gen_smulv8hi3_highpart (t2, op1, op2));
4843 emit_insn (gen_vec_interleave_lowv8hi (dest, t1, t2));
4847 (define_expand "vec_widen_umult_hi_v8hi"
4848 [(match_operand:V4SI 0 "register_operand" "")
4849 (match_operand:V8HI 1 "register_operand" "")
4850 (match_operand:V8HI 2 "register_operand" "")]
4853 rtx op1, op2, t1, t2, dest;
4857 t1 = gen_reg_rtx (V8HImode);
4858 t2 = gen_reg_rtx (V8HImode);
4859 dest = gen_lowpart (V8HImode, operands[0]);
4861 emit_insn (gen_mulv8hi3 (t1, op1, op2));
4862 emit_insn (gen_umulv8hi3_highpart (t2, op1, op2));
4863 emit_insn (gen_vec_interleave_highv8hi (dest, t1, t2));
4867 (define_expand "vec_widen_umult_lo_v8hi"
4868 [(match_operand:V4SI 0 "register_operand" "")
4869 (match_operand:V8HI 1 "register_operand" "")
4870 (match_operand:V8HI 2 "register_operand" "")]
4873 rtx op1, op2, t1, t2, dest;
4877 t1 = gen_reg_rtx (V8HImode);
4878 t2 = gen_reg_rtx (V8HImode);
4879 dest = gen_lowpart (V8HImode, operands[0]);
4881 emit_insn (gen_mulv8hi3 (t1, op1, op2));
4882 emit_insn (gen_umulv8hi3_highpart (t2, op1, op2));
4883 emit_insn (gen_vec_interleave_lowv8hi (dest, t1, t2));
4887 (define_expand "vec_widen_umult_hi_v4si"
4888 [(match_operand:V2DI 0 "register_operand" "")
4889 (match_operand:V4SI 1 "register_operand" "")
4890 (match_operand:V4SI 2 "register_operand" "")]
4893 rtx op1, op2, t1, t2;
4897 t1 = gen_reg_rtx (V4SImode);
4898 t2 = gen_reg_rtx (V4SImode);
4900 emit_insn (gen_vec_interleave_highv4si (t1, op1, op1));
4901 emit_insn (gen_vec_interleave_highv4si (t2, op2, op2));
4902 emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2));
4906 (define_expand "vec_widen_umult_lo_v4si"
4907 [(match_operand:V2DI 0 "register_operand" "")
4908 (match_operand:V4SI 1 "register_operand" "")
4909 (match_operand:V4SI 2 "register_operand" "")]
4912 rtx op1, op2, t1, t2;
4916 t1 = gen_reg_rtx (V4SImode);
4917 t2 = gen_reg_rtx (V4SImode);
4919 emit_insn (gen_vec_interleave_lowv4si (t1, op1, op1));
4920 emit_insn (gen_vec_interleave_lowv4si (t2, op2, op2));
4921 emit_insn (gen_sse2_umulv2siv2di3 (operands[0], t1, t2));
4925 (define_expand "sdot_prodv8hi"
4926 [(match_operand:V4SI 0 "register_operand" "")
4927 (match_operand:V8HI 1 "register_operand" "")
4928 (match_operand:V8HI 2 "register_operand" "")
4929 (match_operand:V4SI 3 "register_operand" "")]
4932 rtx t = gen_reg_rtx (V4SImode);
4933 emit_insn (gen_sse2_pmaddwd (t, operands[1], operands[2]));
4934 emit_insn (gen_addv4si3 (operands[0], operands[3], t));
4938 (define_expand "udot_prodv4si"
4939 [(match_operand:V2DI 0 "register_operand" "")
4940 (match_operand:V4SI 1 "register_operand" "")
4941 (match_operand:V4SI 2 "register_operand" "")
4942 (match_operand:V2DI 3 "register_operand" "")]
4947 t1 = gen_reg_rtx (V2DImode);
4948 emit_insn (gen_sse2_umulv2siv2di3 (t1, operands[1], operands[2]));
4949 emit_insn (gen_addv2di3 (t1, t1, operands[3]));
4951 t2 = gen_reg_rtx (V4SImode);
4952 t3 = gen_reg_rtx (V4SImode);
4953 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t2),
4954 gen_lowpart (TImode, operands[1]),
4956 emit_insn (gen_sse2_lshrti3 (gen_lowpart (TImode, t3),
4957 gen_lowpart (TImode, operands[2]),
4960 t4 = gen_reg_rtx (V2DImode);
4961 emit_insn (gen_sse2_umulv2siv2di3 (t4, t2, t3));
4963 emit_insn (gen_addv2di3 (operands[0], t1, t4));
4967 (define_insn "*avx_ashr<mode>3"
4968 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
4970 (match_operand:SSEMODE24 1 "register_operand" "x")
4971 (match_operand:SI 2 "nonmemory_operand" "xN")))]
4973 "vpsra<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
4974 [(set_attr "type" "sseishft")
4975 (set_attr "prefix" "vex")
4976 (set (attr "length_immediate")
4977 (if_then_else (match_operand 2 "const_int_operand" "")
4979 (const_string "0")))
4980 (set_attr "mode" "TI")])
4982 (define_insn "ashr<mode>3"
4983 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
4985 (match_operand:SSEMODE24 1 "register_operand" "0")
4986 (match_operand:SI 2 "nonmemory_operand" "xN")))]
4988 "psra<ssevecsize>\t{%2, %0|%0, %2}"
4989 [(set_attr "type" "sseishft")
4990 (set_attr "prefix_data16" "1")
4991 (set (attr "length_immediate")
4992 (if_then_else (match_operand 2 "const_int_operand" "")
4994 (const_string "0")))
4995 (set_attr "mode" "TI")])
4997 (define_insn "*avx_lshr<mode>3"
4998 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
4999 (lshiftrt:SSEMODE248
5000 (match_operand:SSEMODE248 1 "register_operand" "x")
5001 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5003 "vpsrl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5004 [(set_attr "type" "sseishft")
5005 (set_attr "prefix" "vex")
5006 (set (attr "length_immediate")
5007 (if_then_else (match_operand 2 "const_int_operand" "")
5009 (const_string "0")))
5010 (set_attr "mode" "TI")])
5012 (define_insn "lshr<mode>3"
5013 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
5014 (lshiftrt:SSEMODE248
5015 (match_operand:SSEMODE248 1 "register_operand" "0")
5016 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5018 "psrl<ssevecsize>\t{%2, %0|%0, %2}"
5019 [(set_attr "type" "sseishft")
5020 (set_attr "prefix_data16" "1")
5021 (set (attr "length_immediate")
5022 (if_then_else (match_operand 2 "const_int_operand" "")
5024 (const_string "0")))
5025 (set_attr "mode" "TI")])
5027 (define_insn "*avx_ashl<mode>3"
5028 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
5030 (match_operand:SSEMODE248 1 "register_operand" "x")
5031 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5033 "vpsll<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5034 [(set_attr "type" "sseishft")
5035 (set_attr "prefix" "vex")
5036 (set (attr "length_immediate")
5037 (if_then_else (match_operand 2 "const_int_operand" "")
5039 (const_string "0")))
5040 (set_attr "mode" "TI")])
5042 (define_insn "ashl<mode>3"
5043 [(set (match_operand:SSEMODE248 0 "register_operand" "=x")
5045 (match_operand:SSEMODE248 1 "register_operand" "0")
5046 (match_operand:SI 2 "nonmemory_operand" "xN")))]
5048 "psll<ssevecsize>\t{%2, %0|%0, %2}"
5049 [(set_attr "type" "sseishft")
5050 (set_attr "prefix_data16" "1")
5051 (set (attr "length_immediate")
5052 (if_then_else (match_operand 2 "const_int_operand" "")
5054 (const_string "0")))
5055 (set_attr "mode" "TI")])
5057 (define_expand "vec_shl_<mode>"
5058 [(set (match_operand:SSEMODEI 0 "register_operand" "")
5059 (ashift:TI (match_operand:SSEMODEI 1 "register_operand" "")
5060 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
5063 operands[0] = gen_lowpart (TImode, operands[0]);
5064 operands[1] = gen_lowpart (TImode, operands[1]);
5067 (define_expand "vec_shr_<mode>"
5068 [(set (match_operand:SSEMODEI 0 "register_operand" "")
5069 (lshiftrt:TI (match_operand:SSEMODEI 1 "register_operand" "")
5070 (match_operand:SI 2 "const_0_to_255_mul_8_operand" "")))]
5073 operands[0] = gen_lowpart (TImode, operands[0]);
5074 operands[1] = gen_lowpart (TImode, operands[1]);
5077 (define_insn "*avx_<code><mode>3"
5078 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
5080 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%x")
5081 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
5082 "TARGET_AVX && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5083 "vp<maxminiprefix><ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5084 [(set_attr "type" "sseiadd")
5085 (set (attr "prefix_extra")
5087 (ne (symbol_ref "<MODE>mode != ((<CODE> == SMAX || <CODE> == SMIN) ? V8HImode : V16QImode)")
5090 (const_string "0")))
5091 (set_attr "prefix" "vex")
5092 (set_attr "mode" "TI")])
5094 (define_expand "<code>v16qi3"
5095 [(set (match_operand:V16QI 0 "register_operand" "")
5097 (match_operand:V16QI 1 "nonimmediate_operand" "")
5098 (match_operand:V16QI 2 "nonimmediate_operand" "")))]
5100 "ix86_fixup_binary_operands_no_copy (<CODE>, V16QImode, operands);")
5102 (define_insn "*<code>v16qi3"
5103 [(set (match_operand:V16QI 0 "register_operand" "=x")
5105 (match_operand:V16QI 1 "nonimmediate_operand" "%0")
5106 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
5107 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V16QImode, operands)"
5108 "p<maxminiprefix>b\t{%2, %0|%0, %2}"
5109 [(set_attr "type" "sseiadd")
5110 (set_attr "prefix_data16" "1")
5111 (set_attr "mode" "TI")])
5113 (define_expand "<code>v8hi3"
5114 [(set (match_operand:V8HI 0 "register_operand" "")
5116 (match_operand:V8HI 1 "nonimmediate_operand" "")
5117 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
5119 "ix86_fixup_binary_operands_no_copy (<CODE>, V8HImode, operands);")
5121 (define_insn "*<code>v8hi3"
5122 [(set (match_operand:V8HI 0 "register_operand" "=x")
5124 (match_operand:V8HI 1 "nonimmediate_operand" "%0")
5125 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
5126 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, V8HImode, operands)"
5127 "p<maxminiprefix>w\t{%2, %0|%0, %2}"
5128 [(set_attr "type" "sseiadd")
5129 (set_attr "prefix_data16" "1")
5130 (set_attr "mode" "TI")])
5132 (define_expand "umaxv8hi3"
5133 [(set (match_operand:V8HI 0 "register_operand" "")
5134 (umax:V8HI (match_operand:V8HI 1 "register_operand" "")
5135 (match_operand:V8HI 2 "nonimmediate_operand" "")))]
5139 ix86_fixup_binary_operands_no_copy (UMAX, V8HImode, operands);
5142 rtx op0 = operands[0], op2 = operands[2], op3 = op0;
5143 if (rtx_equal_p (op3, op2))
5144 op3 = gen_reg_rtx (V8HImode);
5145 emit_insn (gen_sse2_ussubv8hi3 (op3, operands[1], op2));
5146 emit_insn (gen_addv8hi3 (op0, op3, op2));
5151 (define_expand "smax<mode>3"
5152 [(set (match_operand:SSEMODE14 0 "register_operand" "")
5153 (smax:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
5154 (match_operand:SSEMODE14 2 "register_operand" "")))]
5158 ix86_fixup_binary_operands_no_copy (SMAX, <MODE>mode, operands);
5164 xops[0] = operands[0];
5165 xops[1] = operands[1];
5166 xops[2] = operands[2];
5167 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
5168 xops[4] = operands[1];
5169 xops[5] = operands[2];
5170 ok = ix86_expand_int_vcond (xops);
5176 (define_insn "*sse4_1_<code><mode>3"
5177 [(set (match_operand:SSEMODE14 0 "register_operand" "=x")
5179 (match_operand:SSEMODE14 1 "nonimmediate_operand" "%0")
5180 (match_operand:SSEMODE14 2 "nonimmediate_operand" "xm")))]
5181 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5182 "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
5183 [(set_attr "type" "sseiadd")
5184 (set_attr "prefix_extra" "1")
5185 (set_attr "mode" "TI")])
5187 (define_expand "umaxv4si3"
5188 [(set (match_operand:V4SI 0 "register_operand" "")
5189 (umax:V4SI (match_operand:V4SI 1 "register_operand" "")
5190 (match_operand:V4SI 2 "register_operand" "")))]
5194 ix86_fixup_binary_operands_no_copy (UMAX, V4SImode, operands);
5200 xops[0] = operands[0];
5201 xops[1] = operands[1];
5202 xops[2] = operands[2];
5203 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
5204 xops[4] = operands[1];
5205 xops[5] = operands[2];
5206 ok = ix86_expand_int_vcond (xops);
5212 (define_insn "*sse4_1_<code><mode>3"
5213 [(set (match_operand:SSEMODE24 0 "register_operand" "=x")
5215 (match_operand:SSEMODE24 1 "nonimmediate_operand" "%0")
5216 (match_operand:SSEMODE24 2 "nonimmediate_operand" "xm")))]
5217 "TARGET_SSE4_1 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5218 "p<maxminiprefix><ssevecsize>\t{%2, %0|%0, %2}"
5219 [(set_attr "type" "sseiadd")
5220 (set_attr "prefix_extra" "1")
5221 (set_attr "mode" "TI")])
5223 (define_expand "smin<mode>3"
5224 [(set (match_operand:SSEMODE14 0 "register_operand" "")
5225 (smin:SSEMODE14 (match_operand:SSEMODE14 1 "register_operand" "")
5226 (match_operand:SSEMODE14 2 "register_operand" "")))]
5230 ix86_fixup_binary_operands_no_copy (SMIN, <MODE>mode, operands);
5236 xops[0] = operands[0];
5237 xops[1] = operands[2];
5238 xops[2] = operands[1];
5239 xops[3] = gen_rtx_GT (VOIDmode, operands[1], operands[2]);
5240 xops[4] = operands[1];
5241 xops[5] = operands[2];
5242 ok = ix86_expand_int_vcond (xops);
5248 (define_expand "umin<mode>3"
5249 [(set (match_operand:SSEMODE24 0 "register_operand" "")
5250 (umin:SSEMODE24 (match_operand:SSEMODE24 1 "register_operand" "")
5251 (match_operand:SSEMODE24 2 "register_operand" "")))]
5255 ix86_fixup_binary_operands_no_copy (UMIN, <MODE>mode, operands);
5261 xops[0] = operands[0];
5262 xops[1] = operands[2];
5263 xops[2] = operands[1];
5264 xops[3] = gen_rtx_GTU (VOIDmode, operands[1], operands[2]);
5265 xops[4] = operands[1];
5266 xops[5] = operands[2];
5267 ok = ix86_expand_int_vcond (xops);
5273 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5275 ;; Parallel integral comparisons
5277 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5279 (define_expand "sse2_eq<mode>3"
5280 [(set (match_operand:SSEMODE124 0 "register_operand" "")
5282 (match_operand:SSEMODE124 1 "nonimmediate_operand" "")
5283 (match_operand:SSEMODE124 2 "nonimmediate_operand" "")))]
5285 "ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
5287 (define_insn "*avx_eq<mode>3"
5288 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
5290 (match_operand:SSEMODE1248 1 "nonimmediate_operand" "%x")
5291 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
5292 "TARGET_AVX && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
5293 "vpcmpeq<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5294 [(set_attr "type" "ssecmp")
5295 (set (attr "prefix_extra")
5296 (if_then_else (match_operand:V2DI 0 "" "")
5298 (const_string "*")))
5299 (set_attr "prefix" "vex")
5300 (set_attr "mode" "TI")])
5302 (define_insn "*sse2_eq<mode>3"
5303 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
5305 (match_operand:SSEMODE124 1 "nonimmediate_operand" "%0")
5306 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
5308 && ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
5309 "pcmpeq<ssevecsize>\t{%2, %0|%0, %2}"
5310 [(set_attr "type" "ssecmp")
5311 (set_attr "prefix_data16" "1")
5312 (set_attr "mode" "TI")])
5314 (define_expand "sse4_1_eqv2di3"
5315 [(set (match_operand:V2DI 0 "register_operand" "")
5317 (match_operand:V2DI 1 "nonimmediate_operand" "")
5318 (match_operand:V2DI 2 "nonimmediate_operand" "")))]
5320 "ix86_fixup_binary_operands_no_copy (EQ, V2DImode, operands);")
5322 (define_insn "*sse4_1_eqv2di3"
5323 [(set (match_operand:V2DI 0 "register_operand" "=x")
5325 (match_operand:V2DI 1 "nonimmediate_operand" "%0")
5326 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
5327 "TARGET_SSE4_1 && ix86_binary_operator_ok (EQ, V2DImode, operands)"
5328 "pcmpeqq\t{%2, %0|%0, %2}"
5329 [(set_attr "type" "ssecmp")
5330 (set_attr "prefix_extra" "1")
5331 (set_attr "mode" "TI")])
5333 (define_insn "*avx_gt<mode>3"
5334 [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
5336 (match_operand:SSEMODE1248 1 "register_operand" "x")
5337 (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")))]
5339 "vpcmpgt<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
5340 [(set_attr "type" "ssecmp")
5341 (set (attr "prefix_extra")
5342 (if_then_else (match_operand:V2DI 0 "" "")
5344 (const_string "*")))
5345 (set_attr "prefix" "vex")
5346 (set_attr "mode" "TI")])
5348 (define_insn "sse2_gt<mode>3"
5349 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
5351 (match_operand:SSEMODE124 1 "register_operand" "0")
5352 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
5354 "pcmpgt<ssevecsize>\t{%2, %0|%0, %2}"
5355 [(set_attr "type" "ssecmp")
5356 (set_attr "prefix_data16" "1")
5357 (set_attr "mode" "TI")])
5359 (define_insn "sse4_2_gtv2di3"
5360 [(set (match_operand:V2DI 0 "register_operand" "=x")
5362 (match_operand:V2DI 1 "register_operand" "0")
5363 (match_operand:V2DI 2 "nonimmediate_operand" "xm")))]
5365 "pcmpgtq\t{%2, %0|%0, %2}"
5366 [(set_attr "type" "ssecmp")
5367 (set_attr "prefix_extra" "1")
5368 (set_attr "mode" "TI")])
5370 (define_expand "vcond<mode>"
5371 [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
5372 (if_then_else:SSEMODE124C8
5373 (match_operator 3 ""
5374 [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
5375 (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
5376 (match_operand:SSEMODE124C8 1 "general_operand" "")
5377 (match_operand:SSEMODE124C8 2 "general_operand" "")))]
5380 bool ok = ix86_expand_int_vcond (operands);
5385 (define_expand "vcondu<mode>"
5386 [(set (match_operand:SSEMODE124C8 0 "register_operand" "")
5387 (if_then_else:SSEMODE124C8
5388 (match_operator 3 ""
5389 [(match_operand:SSEMODE124C8 4 "nonimmediate_operand" "")
5390 (match_operand:SSEMODE124C8 5 "nonimmediate_operand" "")])
5391 (match_operand:SSEMODE124C8 1 "general_operand" "")
5392 (match_operand:SSEMODE124C8 2 "general_operand" "")))]
5395 bool ok = ix86_expand_int_vcond (operands);
5400 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5402 ;; Parallel bitwise logical operations
5404 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5406 (define_expand "one_cmpl<mode>2"
5407 [(set (match_operand:SSEMODEI 0 "register_operand" "")
5408 (xor:SSEMODEI (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
5412 int i, n = GET_MODE_NUNITS (<MODE>mode);
5413 rtvec v = rtvec_alloc (n);
5415 for (i = 0; i < n; ++i)
5416 RTVEC_ELT (v, i) = constm1_rtx;
5418 operands[2] = force_reg (<MODE>mode, gen_rtx_CONST_VECTOR (<MODE>mode, v));
5421 (define_insn "*avx_andnot<mode>3"
5422 [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
5424 (not:AVX256MODEI (match_operand:AVX256MODEI 1 "register_operand" "x"))
5425 (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
5427 "vandnps\t{%2, %1, %0|%0, %1, %2}"
5428 [(set_attr "type" "sselog")
5429 (set_attr "prefix" "vex")
5430 (set_attr "mode" "<avxvecpsmode>")])
5432 (define_insn "*sse_andnot<mode>3"
5433 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
5435 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
5436 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
5437 "(TARGET_SSE && !TARGET_SSE2)"
5438 "andnps\t{%2, %0|%0, %2}"
5439 [(set_attr "type" "sselog")
5440 (set_attr "mode" "V4SF")])
5442 (define_insn "*avx_andnot<mode>3"
5443 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
5445 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "x"))
5446 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
5448 "vpandn\t{%2, %1, %0|%0, %1, %2}"
5449 [(set_attr "type" "sselog")
5450 (set_attr "prefix" "vex")
5451 (set_attr "mode" "TI")])
5453 (define_insn "sse2_andnot<mode>3"
5454 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
5456 (not:SSEMODEI (match_operand:SSEMODEI 1 "register_operand" "0"))
5457 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
5459 "pandn\t{%2, %0|%0, %2}"
5460 [(set_attr "type" "sselog")
5461 (set_attr "prefix_data16" "1")
5462 (set_attr "mode" "TI")])
5464 (define_insn "*andnottf3"
5465 [(set (match_operand:TF 0 "register_operand" "=x")
5467 (not:TF (match_operand:TF 1 "register_operand" "0"))
5468 (match_operand:TF 2 "nonimmediate_operand" "xm")))]
5470 "pandn\t{%2, %0|%0, %2}"
5471 [(set_attr "type" "sselog")
5472 (set_attr "prefix_data16" "1")
5473 (set_attr "mode" "TI")])
5475 (define_expand "<code><mode>3"
5476 [(set (match_operand:SSEMODEI 0 "register_operand" "")
5478 (match_operand:SSEMODEI 1 "nonimmediate_operand" "")
5479 (match_operand:SSEMODEI 2 "nonimmediate_operand" "")))]
5481 "ix86_fixup_binary_operands_no_copy (<CODE>, <MODE>mode, operands);")
5483 (define_insn "*avx_<code><mode>3"
5484 [(set (match_operand:AVX256MODEI 0 "register_operand" "=x")
5486 (match_operand:AVX256MODEI 1 "nonimmediate_operand" "%x")
5487 (match_operand:AVX256MODEI 2 "nonimmediate_operand" "xm")))]
5489 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5490 "v<plogicprefix>ps\t{%2, %1, %0|%0, %1, %2}"
5491 [(set_attr "type" "sselog")
5492 (set_attr "prefix" "vex")
5493 (set_attr "mode" "<avxvecpsmode>")])
5495 (define_insn "*sse_<code><mode>3"
5496 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
5498 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
5499 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
5500 "(TARGET_SSE && !TARGET_SSE2)
5501 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5502 "<plogicprefix>ps\t{%2, %0|%0, %2}"
5503 [(set_attr "type" "sselog")
5504 (set_attr "mode" "V4SF")])
5506 (define_insn "*avx_<code><mode>3"
5507 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
5509 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%x")
5510 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
5512 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5513 "vp<plogicprefix>\t{%2, %1, %0|%0, %1, %2}"
5514 [(set_attr "type" "sselog")
5515 (set_attr "prefix" "vex")
5516 (set_attr "mode" "TI")])
5518 (define_insn "*sse2_<code><mode>3"
5519 [(set (match_operand:SSEMODEI 0 "register_operand" "=x")
5521 (match_operand:SSEMODEI 1 "nonimmediate_operand" "%0")
5522 (match_operand:SSEMODEI 2 "nonimmediate_operand" "xm")))]
5523 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
5524 "p<plogicprefix>\t{%2, %0|%0, %2}"
5525 [(set_attr "type" "sselog")
5526 (set_attr "prefix_data16" "1")
5527 (set_attr "mode" "TI")])
5529 (define_expand "<code>tf3"
5530 [(set (match_operand:TF 0 "register_operand" "")
5532 (match_operand:TF 1 "nonimmediate_operand" "")
5533 (match_operand:TF 2 "nonimmediate_operand" "")))]
5535 "ix86_fixup_binary_operands_no_copy (<CODE>, TFmode, operands);")
5537 (define_insn "*<code>tf3"
5538 [(set (match_operand:TF 0 "register_operand" "=x")
5540 (match_operand:TF 1 "nonimmediate_operand" "%0")
5541 (match_operand:TF 2 "nonimmediate_operand" "xm")))]
5542 "TARGET_SSE2 && ix86_binary_operator_ok (<CODE>, TFmode, operands)"
5543 "p<plogicprefix>\t{%2, %0|%0, %2}"
5544 [(set_attr "type" "sselog")
5545 (set_attr "prefix_data16" "1")
5546 (set_attr "mode" "TI")])
5548 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5550 ;; Parallel integral element swizzling
5552 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
5555 ;; op1 = abcdefghijklmnop
5556 ;; op2 = qrstuvwxyz012345
5557 ;; h1 = aqbrcsdteufvgwhx
5558 ;; l1 = iyjzk0l1m2n3o4p5
5559 ;; h2 = aiqybjrzcks0dlt1
5560 ;; l2 = emu2fnv3gow4hpx5
5561 ;; h3 = aeimquy2bfjnrvz3
5562 ;; l3 = cgkosw04dhlptx15
5563 ;; result = bdfhjlnprtvxz135
5564 (define_expand "vec_pack_trunc_v8hi"
5565 [(match_operand:V16QI 0 "register_operand" "")
5566 (match_operand:V8HI 1 "register_operand" "")
5567 (match_operand:V8HI 2 "register_operand" "")]
5570 rtx op1, op2, h1, l1, h2, l2, h3, l3;
5572 op1 = gen_lowpart (V16QImode, operands[1]);
5573 op2 = gen_lowpart (V16QImode, operands[2]);
5574 h1 = gen_reg_rtx (V16QImode);
5575 l1 = gen_reg_rtx (V16QImode);
5576 h2 = gen_reg_rtx (V16QImode);
5577 l2 = gen_reg_rtx (V16QImode);
5578 h3 = gen_reg_rtx (V16QImode);
5579 l3 = gen_reg_rtx (V16QImode);
5581 emit_insn (gen_vec_interleave_highv16qi (h1, op1, op2));
5582 emit_insn (gen_vec_interleave_lowv16qi (l1, op1, op2));
5583 emit_insn (gen_vec_interleave_highv16qi (h2, l1, h1));
5584 emit_insn (gen_vec_interleave_lowv16qi (l2, l1, h1));
5585 emit_insn (gen_vec_interleave_highv16qi (h3, l2, h2));
5586 emit_insn (gen_vec_interleave_lowv16qi (l3, l2, h2));
5587 emit_insn (gen_vec_interleave_lowv16qi (operands[0], l3, h3));
5598 ;; result = bdfhjlnp
5599 (define_expand "vec_pack_trunc_v4si"
5600 [(match_operand:V8HI 0 "register_operand" "")
5601 (match_operand:V4SI 1 "register_operand" "")
5602 (match_operand:V4SI 2 "register_operand" "")]
5605 rtx op1, op2, h1, l1, h2, l2;
5607 op1 = gen_lowpart (V8HImode, operands[1]);
5608 op2 = gen_lowpart (V8HImode, operands[2]);
5609 h1 = gen_reg_rtx (V8HImode);
5610 l1 = gen_reg_rtx (V8HImode);
5611 h2 = gen_reg_rtx (V8HImode);
5612 l2 = gen_reg_rtx (V8HImode);
5614 emit_insn (gen_vec_interleave_highv8hi (h1, op1, op2));
5615 emit_insn (gen_vec_interleave_lowv8hi (l1, op1, op2));
5616 emit_insn (gen_vec_interleave_highv8hi (h2, l1, h1));
5617 emit_insn (gen_vec_interleave_lowv8hi (l2, l1, h1));
5618 emit_insn (gen_vec_interleave_lowv8hi (operands[0], l2, h2));
5628 (define_expand "vec_pack_trunc_v2di"
5629 [(match_operand:V4SI 0 "register_operand" "")
5630 (match_operand:V2DI 1 "register_operand" "")
5631 (match_operand:V2DI 2 "register_operand" "")]
5634 rtx op1, op2, h1, l1;
5636 op1 = gen_lowpart (V4SImode, operands[1]);
5637 op2 = gen_lowpart (V4SImode, operands[2]);
5638 h1 = gen_reg_rtx (V4SImode);
5639 l1 = gen_reg_rtx (V4SImode);
5641 emit_insn (gen_vec_interleave_highv4si (h1, op1, op2));
5642 emit_insn (gen_vec_interleave_lowv4si (l1, op1, op2));
5643 emit_insn (gen_vec_interleave_lowv4si (operands[0], l1, h1));
5647 (define_expand "vec_interleave_highv16qi"
5648 [(set (match_operand:V16QI 0 "register_operand" "")
5651 (match_operand:V16QI 1 "register_operand" "")
5652 (match_operand:V16QI 2 "nonimmediate_operand" ""))
5653 (parallel [(const_int 8) (const_int 24)
5654 (const_int 9) (const_int 25)
5655 (const_int 10) (const_int 26)
5656 (const_int 11) (const_int 27)
5657 (const_int 12) (const_int 28)
5658 (const_int 13) (const_int 29)
5659 (const_int 14) (const_int 30)
5660 (const_int 15) (const_int 31)])))]
5663 emit_insn (gen_sse2_punpckhbw (operands[0], operands[1], operands[2]));
5667 (define_expand "vec_interleave_lowv16qi"
5668 [(set (match_operand:V16QI 0 "register_operand" "")
5671 (match_operand:V16QI 1 "register_operand" "")
5672 (match_operand:V16QI 2 "nonimmediate_operand" ""))
5673 (parallel [(const_int 0) (const_int 16)
5674 (const_int 1) (const_int 17)
5675 (const_int 2) (const_int 18)
5676 (const_int 3) (const_int 19)
5677 (const_int 4) (const_int 20)
5678 (const_int 5) (const_int 21)
5679 (const_int 6) (const_int 22)
5680 (const_int 7) (const_int 23)])))]
5683 emit_insn (gen_sse2_punpcklbw (operands[0], operands[1], operands[2]));
5687 (define_expand "vec_interleave_highv8hi"
5688 [(set (match_operand:V8HI 0 "register_operand" "=")
5691 (match_operand:V8HI 1 "register_operand" "")
5692 (match_operand:V8HI 2 "nonimmediate_operand" ""))
5693 (parallel [(const_int 4) (const_int 12)
5694 (const_int 5) (const_int 13)
5695 (const_int 6) (const_int 14)
5696 (const_int 7) (const_int 15)])))]
5699 emit_insn (gen_sse2_punpckhwd (operands[0], operands[1], operands[2]));
5703 (define_expand "vec_interleave_lowv8hi"
5704 [(set (match_operand:V8HI 0 "register_operand" "")
5707 (match_operand:V8HI 1 "register_operand" "")
5708 (match_operand:V8HI 2 "nonimmediate_operand" ""))
5709 (parallel [(const_int 0) (const_int 8)
5710 (const_int 1) (const_int 9)
5711 (const_int 2) (const_int 10)
5712 (const_int 3) (const_int 11)])))]
5715 emit_insn (gen_sse2_punpcklwd (operands[0], operands[1], operands[2]));
5719 (define_expand "vec_interleave_highv4si"
5720 [(set (match_operand:V4SI 0 "register_operand" "")
5723 (match_operand:V4SI 1 "register_operand" "")
5724 (match_operand:V4SI 2 "nonimmediate_operand" ""))
5725 (parallel [(const_int 2) (const_int 6)
5726 (const_int 3) (const_int 7)])))]
5729 emit_insn (gen_sse2_punpckhdq (operands[0], operands[1], operands[2]));
5733 (define_expand "vec_interleave_lowv4si"
5734 [(set (match_operand:V4SI 0 "register_operand" "")
5737 (match_operand:V4SI 1 "register_operand" "")
5738 (match_operand:V4SI 2 "nonimmediate_operand" ""))
5739 (parallel [(const_int 0) (const_int 4)
5740 (const_int 1) (const_int 5)])))]
5743 emit_insn (gen_sse2_punpckldq (operands[0], operands[1], operands[2]));
5747 (define_expand "vec_interleave_highv2di"
5748 [(set (match_operand:V2DI 0 "register_operand" "")
5751 (match_operand:V2DI 1 "register_operand" "")
5752 (match_operand:V2DI 2 "nonimmediate_operand" ""))
5753 (parallel [(const_int 1)
5757 emit_insn (gen_sse2_punpckhqdq (operands[0], operands[1], operands[2]));
5761 (define_expand "vec_interleave_lowv2di"
5762 [(set (match_operand:V2DI 0 "register_operand" "")
5765 (match_operand:V2DI 1 "register_operand" "")
5766 (match_operand:V2DI 2 "nonimmediate_operand" ""))
5767 (parallel [(const_int 0)
5771 emit_insn (gen_sse2_punpcklqdq (operands[0], operands[1], operands[2]));
5775 (define_expand "vec_interleave_highv4sf"
5776 [(set (match_operand:V4SF 0 "register_operand" "")
5779 (match_operand:V4SF 1 "register_operand" "")
5780 (match_operand:V4SF 2 "nonimmediate_operand" ""))
5781 (parallel [(const_int 2) (const_int 6)
5782 (const_int 3) (const_int 7)])))]
5785 (define_expand "vec_interleave_lowv4sf"
5786 [(set (match_operand:V4SF 0 "register_operand" "")
5789 (match_operand:V4SF 1 "register_operand" "")
5790 (match_operand:V4SF 2 "nonimmediate_operand" ""))
5791 (parallel [(const_int 0) (const_int 4)
5792 (const_int 1) (const_int 5)])))]
5795 (define_expand "vec_interleave_highv2df"
5796 [(set (match_operand:V2DF 0 "register_operand" "")
5799 (match_operand:V2DF 1 "register_operand" "")
5800 (match_operand:V2DF 2 "nonimmediate_operand" ""))
5801 (parallel [(const_int 1)
5805 (define_expand "vec_interleave_lowv2df"
5806 [(set (match_operand:V2DF 0 "register_operand" "")
5809 (match_operand:V2DF 1 "register_operand" "")
5810 (match_operand:V2DF 2 "nonimmediate_operand" ""))
5811 (parallel [(const_int 0)
5815 (define_insn "*avx_packsswb"
5816 [(set (match_operand:V16QI 0 "register_operand" "=x")
5819 (match_operand:V8HI 1 "register_operand" "x"))
5821 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
5823 "vpacksswb\t{%2, %1, %0|%0, %1, %2}"
5824 [(set_attr "type" "sselog")
5825 (set_attr "prefix" "vex")
5826 (set_attr "mode" "TI")])
5828 (define_insn "sse2_packsswb"
5829 [(set (match_operand:V16QI 0 "register_operand" "=x")
5832 (match_operand:V8HI 1 "register_operand" "0"))
5834 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
5836 "packsswb\t{%2, %0|%0, %2}"
5837 [(set_attr "type" "sselog")
5838 (set_attr "prefix_data16" "1")
5839 (set_attr "mode" "TI")])
5841 (define_insn "*avx_packssdw"
5842 [(set (match_operand:V8HI 0 "register_operand" "=x")
5845 (match_operand:V4SI 1 "register_operand" "x"))
5847 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
5849 "vpackssdw\t{%2, %1, %0|%0, %1, %2}"
5850 [(set_attr "type" "sselog")
5851 (set_attr "prefix" "vex")
5852 (set_attr "mode" "TI")])
5854 (define_insn "sse2_packssdw"
5855 [(set (match_operand:V8HI 0 "register_operand" "=x")
5858 (match_operand:V4SI 1 "register_operand" "0"))
5860 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
5862 "packssdw\t{%2, %0|%0, %2}"
5863 [(set_attr "type" "sselog")
5864 (set_attr "prefix_data16" "1")
5865 (set_attr "mode" "TI")])
5867 (define_insn "*avx_packuswb"
5868 [(set (match_operand:V16QI 0 "register_operand" "=x")
5871 (match_operand:V8HI 1 "register_operand" "x"))
5873 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
5875 "vpackuswb\t{%2, %1, %0|%0, %1, %2}"
5876 [(set_attr "type" "sselog")
5877 (set_attr "prefix" "vex")
5878 (set_attr "mode" "TI")])
5880 (define_insn "sse2_packuswb"
5881 [(set (match_operand:V16QI 0 "register_operand" "=x")
5884 (match_operand:V8HI 1 "register_operand" "0"))
5886 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))))]
5888 "packuswb\t{%2, %0|%0, %2}"
5889 [(set_attr "type" "sselog")
5890 (set_attr "prefix_data16" "1")
5891 (set_attr "mode" "TI")])
5893 (define_insn "*avx_punpckhbw"
5894 [(set (match_operand:V16QI 0 "register_operand" "=x")
5897 (match_operand:V16QI 1 "register_operand" "x")
5898 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
5899 (parallel [(const_int 8) (const_int 24)
5900 (const_int 9) (const_int 25)
5901 (const_int 10) (const_int 26)
5902 (const_int 11) (const_int 27)
5903 (const_int 12) (const_int 28)
5904 (const_int 13) (const_int 29)
5905 (const_int 14) (const_int 30)
5906 (const_int 15) (const_int 31)])))]
5908 "vpunpckhbw\t{%2, %1, %0|%0, %1, %2}"
5909 [(set_attr "type" "sselog")
5910 (set_attr "prefix" "vex")
5911 (set_attr "mode" "TI")])
5913 (define_insn "sse2_punpckhbw"
5914 [(set (match_operand:V16QI 0 "register_operand" "=x")
5917 (match_operand:V16QI 1 "register_operand" "0")
5918 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
5919 (parallel [(const_int 8) (const_int 24)
5920 (const_int 9) (const_int 25)
5921 (const_int 10) (const_int 26)
5922 (const_int 11) (const_int 27)
5923 (const_int 12) (const_int 28)
5924 (const_int 13) (const_int 29)
5925 (const_int 14) (const_int 30)
5926 (const_int 15) (const_int 31)])))]
5928 "punpckhbw\t{%2, %0|%0, %2}"
5929 [(set_attr "type" "sselog")
5930 (set_attr "prefix_data16" "1")
5931 (set_attr "mode" "TI")])
5933 (define_insn "*avx_punpcklbw"
5934 [(set (match_operand:V16QI 0 "register_operand" "=x")
5937 (match_operand:V16QI 1 "register_operand" "x")
5938 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
5939 (parallel [(const_int 0) (const_int 16)
5940 (const_int 1) (const_int 17)
5941 (const_int 2) (const_int 18)
5942 (const_int 3) (const_int 19)
5943 (const_int 4) (const_int 20)
5944 (const_int 5) (const_int 21)
5945 (const_int 6) (const_int 22)
5946 (const_int 7) (const_int 23)])))]
5948 "vpunpcklbw\t{%2, %1, %0|%0, %1, %2}"
5949 [(set_attr "type" "sselog")
5950 (set_attr "prefix" "vex")
5951 (set_attr "mode" "TI")])
5953 (define_insn "sse2_punpcklbw"
5954 [(set (match_operand:V16QI 0 "register_operand" "=x")
5957 (match_operand:V16QI 1 "register_operand" "0")
5958 (match_operand:V16QI 2 "nonimmediate_operand" "xm"))
5959 (parallel [(const_int 0) (const_int 16)
5960 (const_int 1) (const_int 17)
5961 (const_int 2) (const_int 18)
5962 (const_int 3) (const_int 19)
5963 (const_int 4) (const_int 20)
5964 (const_int 5) (const_int 21)
5965 (const_int 6) (const_int 22)
5966 (const_int 7) (const_int 23)])))]
5968 "punpcklbw\t{%2, %0|%0, %2}"
5969 [(set_attr "type" "sselog")
5970 (set_attr "prefix_data16" "1")
5971 (set_attr "mode" "TI")])
5973 (define_insn "*avx_punpckhwd"
5974 [(set (match_operand:V8HI 0 "register_operand" "=x")
5977 (match_operand:V8HI 1 "register_operand" "x")
5978 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
5979 (parallel [(const_int 4) (const_int 12)
5980 (const_int 5) (const_int 13)
5981 (const_int 6) (const_int 14)
5982 (const_int 7) (const_int 15)])))]
5984 "vpunpckhwd\t{%2, %1, %0|%0, %1, %2}"
5985 [(set_attr "type" "sselog")
5986 (set_attr "prefix" "vex")
5987 (set_attr "mode" "TI")])
5989 (define_insn "sse2_punpckhwd"
5990 [(set (match_operand:V8HI 0 "register_operand" "=x")
5993 (match_operand:V8HI 1 "register_operand" "0")
5994 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
5995 (parallel [(const_int 4) (const_int 12)
5996 (const_int 5) (const_int 13)
5997 (const_int 6) (const_int 14)
5998 (const_int 7) (const_int 15)])))]
6000 "punpckhwd\t{%2, %0|%0, %2}"
6001 [(set_attr "type" "sselog")
6002 (set_attr "prefix_data16" "1")
6003 (set_attr "mode" "TI")])
6005 (define_insn "*avx_punpcklwd"
6006 [(set (match_operand:V8HI 0 "register_operand" "=x")
6009 (match_operand:V8HI 1 "register_operand" "x")
6010 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
6011 (parallel [(const_int 0) (const_int 8)
6012 (const_int 1) (const_int 9)
6013 (const_int 2) (const_int 10)
6014 (const_int 3) (const_int 11)])))]
6016 "vpunpcklwd\t{%2, %1, %0|%0, %1, %2}"
6017 [(set_attr "type" "sselog")
6018 (set_attr "prefix" "vex")
6019 (set_attr "mode" "TI")])
6021 (define_insn "sse2_punpcklwd"
6022 [(set (match_operand:V8HI 0 "register_operand" "=x")
6025 (match_operand:V8HI 1 "register_operand" "0")
6026 (match_operand:V8HI 2 "nonimmediate_operand" "xm"))
6027 (parallel [(const_int 0) (const_int 8)
6028 (const_int 1) (const_int 9)
6029 (const_int 2) (const_int 10)
6030 (const_int 3) (const_int 11)])))]
6032 "punpcklwd\t{%2, %0|%0, %2}"
6033 [(set_attr "type" "sselog")
6034 (set_attr "prefix_data16" "1")
6035 (set_attr "mode" "TI")])
6037 (define_insn "*avx_punpckhdq"
6038 [(set (match_operand:V4SI 0 "register_operand" "=x")
6041 (match_operand:V4SI 1 "register_operand" "x")
6042 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
6043 (parallel [(const_int 2) (const_int 6)
6044 (const_int 3) (const_int 7)])))]
6046 "vpunpckhdq\t{%2, %1, %0|%0, %1, %2}"
6047 [(set_attr "type" "sselog")
6048 (set_attr "prefix" "vex")
6049 (set_attr "mode" "TI")])
6051 (define_insn "sse2_punpckhdq"
6052 [(set (match_operand:V4SI 0 "register_operand" "=x")
6055 (match_operand:V4SI 1 "register_operand" "0")
6056 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
6057 (parallel [(const_int 2) (const_int 6)
6058 (const_int 3) (const_int 7)])))]
6060 "punpckhdq\t{%2, %0|%0, %2}"
6061 [(set_attr "type" "sselog")
6062 (set_attr "prefix_data16" "1")
6063 (set_attr "mode" "TI")])
6065 (define_insn "*avx_punpckldq"
6066 [(set (match_operand:V4SI 0 "register_operand" "=x")
6069 (match_operand:V4SI 1 "register_operand" "x")
6070 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
6071 (parallel [(const_int 0) (const_int 4)
6072 (const_int 1) (const_int 5)])))]
6074 "vpunpckldq\t{%2, %1, %0|%0, %1, %2}"
6075 [(set_attr "type" "sselog")
6076 (set_attr "prefix" "vex")
6077 (set_attr "mode" "TI")])
6079 (define_insn "sse2_punpckldq"
6080 [(set (match_operand:V4SI 0 "register_operand" "=x")
6083 (match_operand:V4SI 1 "register_operand" "0")
6084 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))
6085 (parallel [(const_int 0) (const_int 4)
6086 (const_int 1) (const_int 5)])))]
6088 "punpckldq\t{%2, %0|%0, %2}"
6089 [(set_attr "type" "sselog")
6090 (set_attr "prefix_data16" "1")
6091 (set_attr "mode" "TI")])
6093 (define_insn "*avx_pinsr<ssevecsize>"
6094 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
6095 (vec_merge:SSEMODE124
6096 (vec_duplicate:SSEMODE124
6097 (match_operand:<avxscalarmode> 2 "nonimmediate_operand" "rm"))
6098 (match_operand:SSEMODE124 1 "register_operand" "x")
6099 (match_operand:SI 3 "const_pow2_1_to_<pinsrbits>_operand" "n")))]
6102 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6103 return "vpinsr<ssevecsize>\t{%3, %k2, %1, %0|%0, %1, %k2, %3}";
6105 [(set_attr "type" "sselog")
6106 (set (attr "prefix_extra")
6107 (if_then_else (match_operand:V8HI 0 "register_operand" "")
6109 (const_string "1")))
6110 (set_attr "length_immediate" "1")
6111 (set_attr "prefix" "vex")
6112 (set_attr "mode" "TI")])
6114 (define_insn "*sse4_1_pinsrb"
6115 [(set (match_operand:V16QI 0 "register_operand" "=x")
6117 (vec_duplicate:V16QI
6118 (match_operand:QI 2 "nonimmediate_operand" "rm"))
6119 (match_operand:V16QI 1 "register_operand" "0")
6120 (match_operand:SI 3 "const_pow2_1_to_32768_operand" "n")))]
6123 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6124 return "pinsrb\t{%3, %k2, %0|%0, %k2, %3}";
6126 [(set_attr "type" "sselog")
6127 (set_attr "prefix_extra" "1")
6128 (set_attr "length_immediate" "1")
6129 (set_attr "mode" "TI")])
6131 (define_insn "*sse2_pinsrw"
6132 [(set (match_operand:V8HI 0 "register_operand" "=x")
6135 (match_operand:HI 2 "nonimmediate_operand" "rm"))
6136 (match_operand:V8HI 1 "register_operand" "0")
6137 (match_operand:SI 3 "const_pow2_1_to_128_operand" "n")))]
6140 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6141 return "pinsrw\t{%3, %k2, %0|%0, %k2, %3}";
6143 [(set_attr "type" "sselog")
6144 (set_attr "prefix_data16" "1")
6145 (set_attr "length_immediate" "1")
6146 (set_attr "mode" "TI")])
6148 ;; It must come before sse2_loadld since it is preferred.
6149 (define_insn "*sse4_1_pinsrd"
6150 [(set (match_operand:V4SI 0 "register_operand" "=x")
6153 (match_operand:SI 2 "nonimmediate_operand" "rm"))
6154 (match_operand:V4SI 1 "register_operand" "0")
6155 (match_operand:SI 3 "const_pow2_1_to_8_operand" "n")))]
6158 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6159 return "pinsrd\t{%3, %2, %0|%0, %2, %3}";
6161 [(set_attr "type" "sselog")
6162 (set_attr "prefix_extra" "1")
6163 (set_attr "length_immediate" "1")
6164 (set_attr "mode" "TI")])
6166 (define_insn "*avx_pinsrq"
6167 [(set (match_operand:V2DI 0 "register_operand" "=x")
6170 (match_operand:DI 2 "nonimmediate_operand" "rm"))
6171 (match_operand:V2DI 1 "register_operand" "x")
6172 (match_operand:SI 3 "const_pow2_1_to_2_operand" "n")))]
6173 "TARGET_AVX && TARGET_64BIT"
6175 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6176 return "vpinsrq\t{%3, %2, %1, %0|%0, %1, %2, %3}";
6178 [(set_attr "type" "sselog")
6179 (set_attr "prefix_extra" "1")
6180 (set_attr "length_immediate" "1")
6181 (set_attr "prefix" "vex")
6182 (set_attr "mode" "TI")])
6184 (define_insn "*sse4_1_pinsrq"
6185 [(set (match_operand:V2DI 0 "register_operand" "=x")
6188 (match_operand:DI 2 "nonimmediate_operand" "rm"))
6189 (match_operand:V2DI 1 "register_operand" "0")
6190 (match_operand:SI 3 "const_pow2_1_to_2_operand" "n")))]
6191 "TARGET_SSE4_1 && TARGET_64BIT"
6193 operands[3] = GEN_INT (exact_log2 (INTVAL (operands[3])));
6194 return "pinsrq\t{%3, %2, %0|%0, %2, %3}";
6196 [(set_attr "type" "sselog")
6197 (set_attr "prefix_rex" "1")
6198 (set_attr "prefix_extra" "1")
6199 (set_attr "length_immediate" "1")
6200 (set_attr "mode" "TI")])
6202 (define_insn "*sse4_1_pextrb"
6203 [(set (match_operand:SI 0 "register_operand" "=r")
6206 (match_operand:V16QI 1 "register_operand" "x")
6207 (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")]))))]
6209 "%vpextrb\t{%2, %1, %0|%0, %1, %2}"
6210 [(set_attr "type" "sselog")
6211 (set_attr "prefix_extra" "1")
6212 (set_attr "length_immediate" "1")
6213 (set_attr "prefix" "maybe_vex")
6214 (set_attr "mode" "TI")])
6216 (define_insn "*sse4_1_pextrb_memory"
6217 [(set (match_operand:QI 0 "memory_operand" "=m")
6219 (match_operand:V16QI 1 "register_operand" "x")
6220 (parallel [(match_operand:SI 2 "const_0_to_15_operand" "n")])))]
6222 "%vpextrb\t{%2, %1, %0|%0, %1, %2}"
6223 [(set_attr "type" "sselog")
6224 (set_attr "prefix_extra" "1")
6225 (set_attr "length_immediate" "1")
6226 (set_attr "prefix" "maybe_vex")
6227 (set_attr "mode" "TI")])
6229 (define_insn "*sse2_pextrw"
6230 [(set (match_operand:SI 0 "register_operand" "=r")
6233 (match_operand:V8HI 1 "register_operand" "x")
6234 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))]
6236 "%vpextrw\t{%2, %1, %0|%0, %1, %2}"
6237 [(set_attr "type" "sselog")
6238 (set_attr "prefix_data16" "1")
6239 (set_attr "length_immediate" "1")
6240 (set_attr "prefix" "maybe_vex")
6241 (set_attr "mode" "TI")])
6243 (define_insn "*sse4_1_pextrw_memory"
6244 [(set (match_operand:HI 0 "memory_operand" "=m")
6246 (match_operand:V8HI 1 "register_operand" "x")
6247 (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")])))]
6249 "%vpextrw\t{%2, %1, %0|%0, %1, %2}"
6250 [(set_attr "type" "sselog")
6251 (set_attr "prefix_extra" "1")
6252 (set_attr "length_immediate" "1")
6253 (set_attr "prefix" "maybe_vex")
6254 (set_attr "mode" "TI")])
6256 (define_insn "*sse4_1_pextrd"
6257 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
6259 (match_operand:V4SI 1 "register_operand" "x")
6260 (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n")])))]
6262 "%vpextrd\t{%2, %1, %0|%0, %1, %2}"
6263 [(set_attr "type" "sselog")
6264 (set_attr "prefix_extra" "1")
6265 (set_attr "length_immediate" "1")
6266 (set_attr "prefix" "maybe_vex")
6267 (set_attr "mode" "TI")])
6269 ;; It must come before *vec_extractv2di_1_sse since it is preferred.
6270 (define_insn "*sse4_1_pextrq"
6271 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm")
6273 (match_operand:V2DI 1 "register_operand" "x")
6274 (parallel [(match_operand:SI 2 "const_0_to_1_operand" "n")])))]
6275 "TARGET_SSE4_1 && TARGET_64BIT"
6276 "%vpextrq\t{%2, %1, %0|%0, %1, %2}"
6277 [(set_attr "type" "sselog")
6278 (set_attr "prefix_rex" "1")
6279 (set_attr "prefix_extra" "1")
6280 (set_attr "length_immediate" "1")
6281 (set_attr "prefix" "maybe_vex")
6282 (set_attr "mode" "TI")])
6284 (define_expand "sse2_pshufd"
6285 [(match_operand:V4SI 0 "register_operand" "")
6286 (match_operand:V4SI 1 "nonimmediate_operand" "")
6287 (match_operand:SI 2 "const_int_operand" "")]
6290 int mask = INTVAL (operands[2]);
6291 emit_insn (gen_sse2_pshufd_1 (operands[0], operands[1],
6292 GEN_INT ((mask >> 0) & 3),
6293 GEN_INT ((mask >> 2) & 3),
6294 GEN_INT ((mask >> 4) & 3),
6295 GEN_INT ((mask >> 6) & 3)));
6299 (define_insn "sse2_pshufd_1"
6300 [(set (match_operand:V4SI 0 "register_operand" "=x")
6302 (match_operand:V4SI 1 "nonimmediate_operand" "xm")
6303 (parallel [(match_operand 2 "const_0_to_3_operand" "")
6304 (match_operand 3 "const_0_to_3_operand" "")
6305 (match_operand 4 "const_0_to_3_operand" "")
6306 (match_operand 5 "const_0_to_3_operand" "")])))]
6310 mask |= INTVAL (operands[2]) << 0;
6311 mask |= INTVAL (operands[3]) << 2;
6312 mask |= INTVAL (operands[4]) << 4;
6313 mask |= INTVAL (operands[5]) << 6;
6314 operands[2] = GEN_INT (mask);
6316 return "%vpshufd\t{%2, %1, %0|%0, %1, %2}";
6318 [(set_attr "type" "sselog1")
6319 (set_attr "prefix_data16" "1")
6320 (set_attr "prefix" "maybe_vex")
6321 (set_attr "length_immediate" "1")
6322 (set_attr "mode" "TI")])
6324 (define_expand "sse2_pshuflw"
6325 [(match_operand:V8HI 0 "register_operand" "")
6326 (match_operand:V8HI 1 "nonimmediate_operand" "")
6327 (match_operand:SI 2 "const_int_operand" "")]
6330 int mask = INTVAL (operands[2]);
6331 emit_insn (gen_sse2_pshuflw_1 (operands[0], operands[1],
6332 GEN_INT ((mask >> 0) & 3),
6333 GEN_INT ((mask >> 2) & 3),
6334 GEN_INT ((mask >> 4) & 3),
6335 GEN_INT ((mask >> 6) & 3)));
6339 (define_insn "sse2_pshuflw_1"
6340 [(set (match_operand:V8HI 0 "register_operand" "=x")
6342 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
6343 (parallel [(match_operand 2 "const_0_to_3_operand" "")
6344 (match_operand 3 "const_0_to_3_operand" "")
6345 (match_operand 4 "const_0_to_3_operand" "")
6346 (match_operand 5 "const_0_to_3_operand" "")
6354 mask |= INTVAL (operands[2]) << 0;
6355 mask |= INTVAL (operands[3]) << 2;
6356 mask |= INTVAL (operands[4]) << 4;
6357 mask |= INTVAL (operands[5]) << 6;
6358 operands[2] = GEN_INT (mask);
6360 return "%vpshuflw\t{%2, %1, %0|%0, %1, %2}";
6362 [(set_attr "type" "sselog")
6363 (set_attr "prefix_data16" "0")
6364 (set_attr "prefix_rep" "1")
6365 (set_attr "prefix" "maybe_vex")
6366 (set_attr "length_immediate" "1")
6367 (set_attr "mode" "TI")])
6369 (define_expand "sse2_pshufhw"
6370 [(match_operand:V8HI 0 "register_operand" "")
6371 (match_operand:V8HI 1 "nonimmediate_operand" "")
6372 (match_operand:SI 2 "const_int_operand" "")]
6375 int mask = INTVAL (operands[2]);
6376 emit_insn (gen_sse2_pshufhw_1 (operands[0], operands[1],
6377 GEN_INT (((mask >> 0) & 3) + 4),
6378 GEN_INT (((mask >> 2) & 3) + 4),
6379 GEN_INT (((mask >> 4) & 3) + 4),
6380 GEN_INT (((mask >> 6) & 3) + 4)));
6384 (define_insn "sse2_pshufhw_1"
6385 [(set (match_operand:V8HI 0 "register_operand" "=x")
6387 (match_operand:V8HI 1 "nonimmediate_operand" "xm")
6388 (parallel [(const_int 0)
6392 (match_operand 2 "const_4_to_7_operand" "")
6393 (match_operand 3 "const_4_to_7_operand" "")
6394 (match_operand 4 "const_4_to_7_operand" "")
6395 (match_operand 5 "const_4_to_7_operand" "")])))]
6399 mask |= (INTVAL (operands[2]) - 4) << 0;
6400 mask |= (INTVAL (operands[3]) - 4) << 2;
6401 mask |= (INTVAL (operands[4]) - 4) << 4;
6402 mask |= (INTVAL (operands[5]) - 4) << 6;
6403 operands[2] = GEN_INT (mask);
6405 return "%vpshufhw\t{%2, %1, %0|%0, %1, %2}";
6407 [(set_attr "type" "sselog")
6408 (set_attr "prefix_rep" "1")
6409 (set_attr "prefix_data16" "0")
6410 (set_attr "prefix" "maybe_vex")
6411 (set_attr "length_immediate" "1")
6412 (set_attr "mode" "TI")])
6414 (define_expand "sse2_loadd"
6415 [(set (match_operand:V4SI 0 "register_operand" "")
6418 (match_operand:SI 1 "nonimmediate_operand" ""))
6422 "operands[2] = CONST0_RTX (V4SImode);")
6424 (define_insn "*avx_loadld"
6425 [(set (match_operand:V4SI 0 "register_operand" "=x,Yi,x")
6428 (match_operand:SI 2 "nonimmediate_operand" "m ,r ,x"))
6429 (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,x")
6433 vmovd\t{%2, %0|%0, %2}
6434 vmovd\t{%2, %0|%0, %2}
6435 vmovss\t{%2, %1, %0|%0, %1, %2}"
6436 [(set_attr "type" "ssemov")
6437 (set_attr "prefix" "vex")
6438 (set_attr "mode" "TI,TI,V4SF")])
6440 (define_insn "sse2_loadld"
6441 [(set (match_operand:V4SI 0 "register_operand" "=Y2,Yi,x,x")
6444 (match_operand:SI 2 "nonimmediate_operand" "m ,r ,m,x"))
6445 (match_operand:V4SI 1 "reg_or_0_operand" "C ,C ,C,0")
6449 movd\t{%2, %0|%0, %2}
6450 movd\t{%2, %0|%0, %2}
6451 movss\t{%2, %0|%0, %2}
6452 movss\t{%2, %0|%0, %2}"
6453 [(set_attr "type" "ssemov")
6454 (set_attr "mode" "TI,TI,V4SF,SF")])
6456 (define_insn_and_split "sse2_stored"
6457 [(set (match_operand:SI 0 "nonimmediate_operand" "=mx,r")
6459 (match_operand:V4SI 1 "register_operand" "x,Yi")
6460 (parallel [(const_int 0)])))]
6463 "&& reload_completed
6464 && (TARGET_INTER_UNIT_MOVES
6465 || MEM_P (operands [0])
6466 || !GENERAL_REGNO_P (true_regnum (operands [0])))"
6467 [(set (match_dup 0) (match_dup 1))]
6469 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));
6472 (define_insn_and_split "*vec_ext_v4si_mem"
6473 [(set (match_operand:SI 0 "register_operand" "=r")
6475 (match_operand:V4SI 1 "memory_operand" "o")
6476 (parallel [(match_operand 2 "const_0_to_3_operand" "")])))]
6482 int i = INTVAL (operands[2]);
6484 emit_move_insn (operands[0], adjust_address (operands[1], SImode, i*4));
6488 (define_expand "sse_storeq"
6489 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6491 (match_operand:V2DI 1 "register_operand" "")
6492 (parallel [(const_int 0)])))]
6496 (define_insn "*sse2_storeq_rex64"
6497 [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,*r,r")
6499 (match_operand:V2DI 1 "nonimmediate_operand" "x,Yi,o")
6500 (parallel [(const_int 0)])))]
6501 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
6505 %vmov{q}\t{%1, %0|%0, %1}"
6506 [(set_attr "type" "*,*,imov")
6507 (set_attr "prefix" "*,*,maybe_vex")
6508 (set_attr "mode" "*,*,DI")])
6510 (define_insn "*sse2_storeq"
6511 [(set (match_operand:DI 0 "nonimmediate_operand" "=mx")
6513 (match_operand:V2DI 1 "register_operand" "x")
6514 (parallel [(const_int 0)])))]
6519 [(set (match_operand:DI 0 "nonimmediate_operand" "")
6521 (match_operand:V2DI 1 "register_operand" "")
6522 (parallel [(const_int 0)])))]
6525 && (TARGET_INTER_UNIT_MOVES
6526 || MEM_P (operands [0])
6527 || !GENERAL_REGNO_P (true_regnum (operands [0])))"
6528 [(set (match_dup 0) (match_dup 1))]
6530 operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
6533 (define_insn "*vec_extractv2di_1_rex64_avx"
6534 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
6536 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o,o")
6537 (parallel [(const_int 1)])))]
6540 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
6542 vmovhps\t{%1, %0|%0, %1}
6543 vpsrldq\t{$8, %1, %0|%0, %1, 8}
6544 vmovq\t{%H1, %0|%0, %H1}
6545 vmov{q}\t{%H1, %0|%0, %H1}"
6546 [(set_attr "type" "ssemov,sseishft,ssemov,imov")
6547 (set_attr "length_immediate" "*,1,*,*")
6548 (set_attr "memory" "*,none,*,*")
6549 (set_attr "prefix" "vex")
6550 (set_attr "mode" "V2SF,TI,TI,DI")])
6552 (define_insn "*vec_extractv2di_1_rex64"
6553 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
6555 (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o,o")
6556 (parallel [(const_int 1)])))]
6557 "TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
6559 movhps\t{%1, %0|%0, %1}
6560 psrldq\t{$8, %0|%0, 8}
6561 movq\t{%H1, %0|%0, %H1}
6562 mov{q}\t{%H1, %0|%0, %H1}"
6563 [(set_attr "type" "ssemov,sseishft,ssemov,imov")
6564 (set_attr "length_immediate" "*,1,*,*")
6565 (set_attr "atom_unit" "*,sishuf,*,*")
6566 (set_attr "memory" "*,none,*,*")
6567 (set_attr "mode" "V2SF,TI,TI,DI")])
6569 (define_insn "*vec_extractv2di_1_avx"
6570 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
6572 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
6573 (parallel [(const_int 1)])))]
6576 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
6578 vmovhps\t{%1, %0|%0, %1}
6579 vpsrldq\t{$8, %1, %0|%0, %1, 8}
6580 vmovq\t{%H1, %0|%0, %H1}"
6581 [(set_attr "type" "ssemov,sseishft,ssemov")
6582 (set_attr "length_immediate" "*,1,*")
6583 (set_attr "memory" "*,none,*")
6584 (set_attr "prefix" "vex")
6585 (set_attr "mode" "V2SF,TI,TI")])
6587 (define_insn "*vec_extractv2di_1_sse2"
6588 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
6590 (match_operand:V2DI 1 "nonimmediate_operand" "x,0,o")
6591 (parallel [(const_int 1)])))]
6593 && TARGET_SSE2 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
6595 movhps\t{%1, %0|%0, %1}
6596 psrldq\t{$8, %0|%0, 8}
6597 movq\t{%H1, %0|%0, %H1}"
6598 [(set_attr "type" "ssemov,sseishft,ssemov")
6599 (set_attr "length_immediate" "*,1,*")
6600 (set_attr "atom_unit" "*,sishuf,*")
6601 (set_attr "memory" "*,none,*")
6602 (set_attr "mode" "V2SF,TI,TI")])
6604 ;; Not sure this is ever used, but it doesn't hurt to have it. -aoliva
6605 (define_insn "*vec_extractv2di_1_sse"
6606 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x")
6608 (match_operand:V2DI 1 "nonimmediate_operand" "x,x,o")
6609 (parallel [(const_int 1)])))]
6610 "!TARGET_SSE2 && TARGET_SSE
6611 && !(MEM_P (operands[0]) && MEM_P (operands[1]))"
6613 movhps\t{%1, %0|%0, %1}
6614 movhlps\t{%1, %0|%0, %1}
6615 movlps\t{%H1, %0|%0, %H1}"
6616 [(set_attr "type" "ssemov")
6617 (set_attr "mode" "V2SF,V4SF,V2SF")])
6619 (define_insn "*vec_dupv4si"
6620 [(set (match_operand:V4SI 0 "register_operand" "=Y2,x")
6622 (match_operand:SI 1 "register_operand" " Y2,0")))]
6625 %vpshufd\t{$0, %1, %0|%0, %1, 0}
6626 shufps\t{$0, %0, %0|%0, %0, 0}"
6627 [(set_attr "type" "sselog1")
6628 (set_attr "prefix" "maybe_vex,orig")
6629 (set_attr "length_immediate" "1")
6630 (set_attr "mode" "TI,V4SF")])
6632 (define_insn "*vec_dupv2di_avx"
6633 [(set (match_operand:V2DI 0 "register_operand" "=x")
6635 (match_operand:DI 1 "register_operand" "x")))]
6637 "vpunpcklqdq\t{%1, %1, %0|%0, %1, %1}"
6638 [(set_attr "type" "sselog1")
6639 (set_attr "prefix" "vex")
6640 (set_attr "mode" "TI")])
6642 (define_insn "*vec_dupv2di"
6643 [(set (match_operand:V2DI 0 "register_operand" "=Y2,x")
6645 (match_operand:DI 1 "register_operand" " 0 ,0")))]
6650 [(set_attr "type" "sselog1,ssemov")
6651 (set_attr "mode" "TI,V4SF")])
6653 (define_insn "*vec_concatv2si_avx"
6654 [(set (match_operand:V2SI 0 "register_operand" "=x,x,x ,*y ,*y")
6656 (match_operand:SI 1 "nonimmediate_operand" "x ,x,rm, 0 ,rm")
6657 (match_operand:SI 2 "vector_move_operand" "rm,x,C ,*ym,C")))]
6660 vpinsrd\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
6661 vpunpckldq\t{%2, %1, %0|%0, %1, %2}
6662 vmovd\t{%1, %0|%0, %1}
6663 punpckldq\t{%2, %0|%0, %2}
6664 movd\t{%1, %0|%0, %1}"
6665 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
6666 (set_attr "prefix_extra" "1,*,*,*,*")
6667 (set_attr "length_immediate" "1,*,*,*,*")
6668 (set (attr "prefix")
6669 (if_then_else (eq_attr "alternative" "3,4")
6670 (const_string "orig")
6671 (const_string "vex")))
6672 (set_attr "mode" "TI,TI,TI,DI,DI")])
6674 (define_insn "*vec_concatv2si_sse4_1"
6675 [(set (match_operand:V2SI 0 "register_operand" "=x,x,x ,*y ,*y")
6677 (match_operand:SI 1 "nonimmediate_operand" "0 ,0,rm, 0 ,rm")
6678 (match_operand:SI 2 "vector_move_operand" "rm,x,C ,*ym,C")))]
6681 pinsrd\t{$0x1, %2, %0|%0, %2, 0x1}
6682 punpckldq\t{%2, %0|%0, %2}
6683 movd\t{%1, %0|%0, %1}
6684 punpckldq\t{%2, %0|%0, %2}
6685 movd\t{%1, %0|%0, %1}"
6686 [(set_attr "type" "sselog,sselog,ssemov,mmxcvt,mmxmov")
6687 (set_attr "prefix_extra" "1,*,*,*,*")
6688 (set_attr "length_immediate" "1,*,*,*,*")
6689 (set_attr "mode" "TI,TI,TI,DI,DI")])
6691 ;; ??? In theory we can match memory for the MMX alternative, but allowing
6692 ;; nonimmediate_operand for operand 2 and *not* allowing memory for the SSE
6693 ;; alternatives pretty much forces the MMX alternative to be chosen.
6694 (define_insn "*vec_concatv2si_sse2"
6695 [(set (match_operand:V2SI 0 "register_operand" "=x,x ,*y,*y")
6697 (match_operand:SI 1 "nonimmediate_operand" " 0,rm, 0,rm")
6698 (match_operand:SI 2 "reg_or_0_operand" " x,C ,*y, C")))]
6701 punpckldq\t{%2, %0|%0, %2}
6702 movd\t{%1, %0|%0, %1}
6703 punpckldq\t{%2, %0|%0, %2}
6704 movd\t{%1, %0|%0, %1}"
6705 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
6706 (set_attr "mode" "TI,TI,DI,DI")])
6708 (define_insn "*vec_concatv2si_sse"
6709 [(set (match_operand:V2SI 0 "register_operand" "=x,x,*y,*y")
6711 (match_operand:SI 1 "nonimmediate_operand" " 0,m, 0,*rm")
6712 (match_operand:SI 2 "reg_or_0_operand" " x,C,*y,C")))]
6715 unpcklps\t{%2, %0|%0, %2}
6716 movss\t{%1, %0|%0, %1}
6717 punpckldq\t{%2, %0|%0, %2}
6718 movd\t{%1, %0|%0, %1}"
6719 [(set_attr "type" "sselog,ssemov,mmxcvt,mmxmov")
6720 (set_attr "mode" "V4SF,V4SF,DI,DI")])
6722 (define_insn "*vec_concatv4si_1_avx"
6723 [(set (match_operand:V4SI 0 "register_operand" "=x,x")
6725 (match_operand:V2SI 1 "register_operand" " x,x")
6726 (match_operand:V2SI 2 "nonimmediate_operand" " x,m")))]
6729 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
6730 vmovhps\t{%2, %1, %0|%0, %1, %2}"
6731 [(set_attr "type" "sselog,ssemov")
6732 (set_attr "prefix" "vex")
6733 (set_attr "mode" "TI,V2SF")])
6735 (define_insn "*vec_concatv4si_1"
6736 [(set (match_operand:V4SI 0 "register_operand" "=Y2,x,x")
6738 (match_operand:V2SI 1 "register_operand" " 0 ,0,0")
6739 (match_operand:V2SI 2 "nonimmediate_operand" " Y2,x,m")))]
6742 punpcklqdq\t{%2, %0|%0, %2}
6743 movlhps\t{%2, %0|%0, %2}
6744 movhps\t{%2, %0|%0, %2}"
6745 [(set_attr "type" "sselog,ssemov,ssemov")
6746 (set_attr "mode" "TI,V4SF,V2SF")])
6748 (define_insn "*vec_concatv2di_avx"
6749 [(set (match_operand:V2DI 0 "register_operand" "=x,?x,x,x")
6751 (match_operand:DI 1 "nonimmediate_operand" " m,*y,x,x")
6752 (match_operand:DI 2 "vector_move_operand" " C, C,x,m")))]
6753 "!TARGET_64BIT && TARGET_AVX"
6755 vmovq\t{%1, %0|%0, %1}
6756 movq2dq\t{%1, %0|%0, %1}
6757 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
6758 vmovhps\t{%2, %1, %0|%0, %1, %2}"
6759 [(set_attr "type" "ssemov,ssemov,sselog,ssemov")
6760 (set (attr "prefix")
6761 (if_then_else (eq_attr "alternative" "1")
6762 (const_string "orig")
6763 (const_string "vex")))
6764 (set_attr "mode" "TI,TI,TI,V2SF")])
6766 (define_insn "vec_concatv2di"
6767 [(set (match_operand:V2DI 0 "register_operand" "=Y2 ,?Y2,Y2,x,x")
6769 (match_operand:DI 1 "nonimmediate_operand" " mY2,*y ,0 ,0,0")
6770 (match_operand:DI 2 "vector_move_operand" " C , C,Y2,x,m")))]
6771 "!TARGET_64BIT && TARGET_SSE"
6773 movq\t{%1, %0|%0, %1}
6774 movq2dq\t{%1, %0|%0, %1}
6775 punpcklqdq\t{%2, %0|%0, %2}
6776 movlhps\t{%2, %0|%0, %2}
6777 movhps\t{%2, %0|%0, %2}"
6778 [(set_attr "type" "ssemov,ssemov,sselog,ssemov,ssemov")
6779 (set_attr "mode" "TI,TI,TI,V4SF,V2SF")])
6781 (define_insn "*vec_concatv2di_rex64_avx"
6782 [(set (match_operand:V2DI 0 "register_operand" "=x,x,Yi,!x,x,x")
6784 (match_operand:DI 1 "nonimmediate_operand" " x,m,r ,*y,x,x")
6785 (match_operand:DI 2 "vector_move_operand" "rm,C,C ,C ,x,m")))]
6786 "TARGET_64BIT && TARGET_AVX"
6788 vpinsrq\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}
6789 vmovq\t{%1, %0|%0, %1}
6790 vmovq\t{%1, %0|%0, %1}
6791 movq2dq\t{%1, %0|%0, %1}
6792 vpunpcklqdq\t{%2, %1, %0|%0, %1, %2}
6793 vmovhps\t{%2, %1, %0|%0, %1, %2}"
6794 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov")
6795 (set_attr "prefix_extra" "1,*,*,*,*,*")
6796 (set_attr "length_immediate" "1,*,*,*,*,*")
6797 (set (attr "prefix")
6798 (if_then_else (eq_attr "alternative" "3")
6799 (const_string "orig")
6800 (const_string "vex")))
6801 (set_attr "mode" "TI,TI,TI,TI,TI,V2SF")])
6803 (define_insn "*vec_concatv2di_rex64_sse4_1"
6804 [(set (match_operand:V2DI 0 "register_operand" "=x ,x ,Yi,!x,x,x,x")
6806 (match_operand:DI 1 "nonimmediate_operand" " 0 ,mx,r ,*y,0,0,0")
6807 (match_operand:DI 2 "vector_move_operand" " rm,C ,C ,C ,x,x,m")))]
6808 "TARGET_64BIT && TARGET_SSE4_1"
6810 pinsrq\t{$0x1, %2, %0|%0, %2, 0x1}
6811 movq\t{%1, %0|%0, %1}
6812 movq\t{%1, %0|%0, %1}
6813 movq2dq\t{%1, %0|%0, %1}
6814 punpcklqdq\t{%2, %0|%0, %2}
6815 movlhps\t{%2, %0|%0, %2}
6816 movhps\t{%2, %0|%0, %2}"
6817 [(set_attr "type" "sselog,ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
6818 (set_attr "prefix_rex" "1,*,1,*,*,*,*")
6819 (set_attr "prefix_extra" "1,*,*,*,*,*,*")
6820 (set_attr "length_immediate" "1,*,*,*,*,*,*")
6821 (set_attr "mode" "TI,TI,TI,TI,TI,V4SF,V2SF")])
6823 (define_insn "*vec_concatv2di_rex64_sse"
6824 [(set (match_operand:V2DI 0 "register_operand" "=Y2 ,Yi,!Y2,Y2,x,x")
6826 (match_operand:DI 1 "nonimmediate_operand" " mY2,r ,*y ,0 ,0,0")
6827 (match_operand:DI 2 "vector_move_operand" " C ,C ,C ,Y2,x,m")))]
6828 "TARGET_64BIT && TARGET_SSE"
6830 movq\t{%1, %0|%0, %1}
6831 movq\t{%1, %0|%0, %1}
6832 movq2dq\t{%1, %0|%0, %1}
6833 punpcklqdq\t{%2, %0|%0, %2}
6834 movlhps\t{%2, %0|%0, %2}
6835 movhps\t{%2, %0|%0, %2}"
6836 [(set_attr "type" "ssemov,ssemov,ssemov,sselog,ssemov,ssemov")
6837 (set_attr "prefix_rex" "*,1,*,*,*,*")
6838 (set_attr "mode" "TI,TI,TI,TI,V4SF,V2SF")])
6840 (define_expand "vec_unpacku_hi_v16qi"
6841 [(match_operand:V8HI 0 "register_operand" "")
6842 (match_operand:V16QI 1 "register_operand" "")]
6846 ix86_expand_sse4_unpack (operands, true, true);
6848 ix86_expand_sse_unpack (operands, true, true);
6852 (define_expand "vec_unpacks_hi_v16qi"
6853 [(match_operand:V8HI 0 "register_operand" "")
6854 (match_operand:V16QI 1 "register_operand" "")]
6858 ix86_expand_sse4_unpack (operands, false, true);
6860 ix86_expand_sse_unpack (operands, false, true);
6864 (define_expand "vec_unpacku_lo_v16qi"
6865 [(match_operand:V8HI 0 "register_operand" "")
6866 (match_operand:V16QI 1 "register_operand" "")]
6870 ix86_expand_sse4_unpack (operands, true, false);
6872 ix86_expand_sse_unpack (operands, true, false);
6876 (define_expand "vec_unpacks_lo_v16qi"
6877 [(match_operand:V8HI 0 "register_operand" "")
6878 (match_operand:V16QI 1 "register_operand" "")]
6882 ix86_expand_sse4_unpack (operands, false, false);
6884 ix86_expand_sse_unpack (operands, false, false);
6888 (define_expand "vec_unpacku_hi_v8hi"
6889 [(match_operand:V4SI 0 "register_operand" "")
6890 (match_operand:V8HI 1 "register_operand" "")]
6894 ix86_expand_sse4_unpack (operands, true, true);
6896 ix86_expand_sse_unpack (operands, true, true);
6900 (define_expand "vec_unpacks_hi_v8hi"
6901 [(match_operand:V4SI 0 "register_operand" "")
6902 (match_operand:V8HI 1 "register_operand" "")]
6906 ix86_expand_sse4_unpack (operands, false, true);
6908 ix86_expand_sse_unpack (operands, false, true);
6912 (define_expand "vec_unpacku_lo_v8hi"
6913 [(match_operand:V4SI 0 "register_operand" "")
6914 (match_operand:V8HI 1 "register_operand" "")]
6918 ix86_expand_sse4_unpack (operands, true, false);
6920 ix86_expand_sse_unpack (operands, true, false);
6924 (define_expand "vec_unpacks_lo_v8hi"
6925 [(match_operand:V4SI 0 "register_operand" "")
6926 (match_operand:V8HI 1 "register_operand" "")]
6930 ix86_expand_sse4_unpack (operands, false, false);
6932 ix86_expand_sse_unpack (operands, false, false);
6936 (define_expand "vec_unpacku_hi_v4si"
6937 [(match_operand:V2DI 0 "register_operand" "")
6938 (match_operand:V4SI 1 "register_operand" "")]
6942 ix86_expand_sse4_unpack (operands, true, true);
6944 ix86_expand_sse_unpack (operands, true, true);
6948 (define_expand "vec_unpacks_hi_v4si"
6949 [(match_operand:V2DI 0 "register_operand" "")
6950 (match_operand:V4SI 1 "register_operand" "")]
6954 ix86_expand_sse4_unpack (operands, false, true);
6956 ix86_expand_sse_unpack (operands, false, true);
6960 (define_expand "vec_unpacku_lo_v4si"
6961 [(match_operand:V2DI 0 "register_operand" "")
6962 (match_operand:V4SI 1 "register_operand" "")]
6966 ix86_expand_sse4_unpack (operands, true, false);
6968 ix86_expand_sse_unpack (operands, true, false);
6972 (define_expand "vec_unpacks_lo_v4si"
6973 [(match_operand:V2DI 0 "register_operand" "")
6974 (match_operand:V4SI 1 "register_operand" "")]
6978 ix86_expand_sse4_unpack (operands, false, false);
6980 ix86_expand_sse_unpack (operands, false, false);
6984 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6988 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
6990 (define_expand "sse2_uavgv16qi3"
6991 [(set (match_operand:V16QI 0 "register_operand" "")
6997 (match_operand:V16QI 1 "nonimmediate_operand" ""))
6999 (match_operand:V16QI 2 "nonimmediate_operand" "")))
7000 (const_vector:V16QI [(const_int 1) (const_int 1)
7001 (const_int 1) (const_int 1)
7002 (const_int 1) (const_int 1)
7003 (const_int 1) (const_int 1)
7004 (const_int 1) (const_int 1)
7005 (const_int 1) (const_int 1)
7006 (const_int 1) (const_int 1)
7007 (const_int 1) (const_int 1)]))
7010 "ix86_fixup_binary_operands_no_copy (PLUS, V16QImode, operands);")
7012 (define_insn "*avx_uavgv16qi3"
7013 [(set (match_operand:V16QI 0 "register_operand" "=x")
7019 (match_operand:V16QI 1 "nonimmediate_operand" "%x"))
7021 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
7022 (const_vector:V16QI [(const_int 1) (const_int 1)
7023 (const_int 1) (const_int 1)
7024 (const_int 1) (const_int 1)
7025 (const_int 1) (const_int 1)
7026 (const_int 1) (const_int 1)
7027 (const_int 1) (const_int 1)
7028 (const_int 1) (const_int 1)
7029 (const_int 1) (const_int 1)]))
7031 "TARGET_AVX && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
7032 "vpavgb\t{%2, %1, %0|%0, %1, %2}"
7033 [(set_attr "type" "sseiadd")
7034 (set_attr "prefix" "vex")
7035 (set_attr "mode" "TI")])
7037 (define_insn "*sse2_uavgv16qi3"
7038 [(set (match_operand:V16QI 0 "register_operand" "=x")
7044 (match_operand:V16QI 1 "nonimmediate_operand" "%0"))
7046 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))
7047 (const_vector:V16QI [(const_int 1) (const_int 1)
7048 (const_int 1) (const_int 1)
7049 (const_int 1) (const_int 1)
7050 (const_int 1) (const_int 1)
7051 (const_int 1) (const_int 1)
7052 (const_int 1) (const_int 1)
7053 (const_int 1) (const_int 1)
7054 (const_int 1) (const_int 1)]))
7056 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V16QImode, operands)"
7057 "pavgb\t{%2, %0|%0, %2}"
7058 [(set_attr "type" "sseiadd")
7059 (set_attr "prefix_data16" "1")
7060 (set_attr "mode" "TI")])
7062 (define_expand "sse2_uavgv8hi3"
7063 [(set (match_operand:V8HI 0 "register_operand" "")
7069 (match_operand:V8HI 1 "nonimmediate_operand" ""))
7071 (match_operand:V8HI 2 "nonimmediate_operand" "")))
7072 (const_vector:V8HI [(const_int 1) (const_int 1)
7073 (const_int 1) (const_int 1)
7074 (const_int 1) (const_int 1)
7075 (const_int 1) (const_int 1)]))
7078 "ix86_fixup_binary_operands_no_copy (PLUS, V8HImode, operands);")
7080 (define_insn "*avx_uavgv8hi3"
7081 [(set (match_operand:V8HI 0 "register_operand" "=x")
7087 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
7089 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
7090 (const_vector:V8HI [(const_int 1) (const_int 1)
7091 (const_int 1) (const_int 1)
7092 (const_int 1) (const_int 1)
7093 (const_int 1) (const_int 1)]))
7095 "TARGET_AVX && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
7096 "vpavgw\t{%2, %1, %0|%0, %1, %2}"
7097 [(set_attr "type" "sseiadd")
7098 (set_attr "prefix" "vex")
7099 (set_attr "mode" "TI")])
7101 (define_insn "*sse2_uavgv8hi3"
7102 [(set (match_operand:V8HI 0 "register_operand" "=x")
7108 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
7110 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
7111 (const_vector:V8HI [(const_int 1) (const_int 1)
7112 (const_int 1) (const_int 1)
7113 (const_int 1) (const_int 1)
7114 (const_int 1) (const_int 1)]))
7116 "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, V8HImode, operands)"
7117 "pavgw\t{%2, %0|%0, %2}"
7118 [(set_attr "type" "sseiadd")
7119 (set_attr "prefix_data16" "1")
7120 (set_attr "mode" "TI")])
7122 ;; The correct representation for this is absolutely enormous, and
7123 ;; surely not generally useful.
7124 (define_insn "*avx_psadbw"
7125 [(set (match_operand:V2DI 0 "register_operand" "=x")
7126 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "x")
7127 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
7130 "vpsadbw\t{%2, %1, %0|%0, %1, %2}"
7131 [(set_attr "type" "sseiadd")
7132 (set_attr "prefix" "vex")
7133 (set_attr "mode" "TI")])
7135 (define_insn "sse2_psadbw"
7136 [(set (match_operand:V2DI 0 "register_operand" "=x")
7137 (unspec:V2DI [(match_operand:V16QI 1 "register_operand" "0")
7138 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
7141 "psadbw\t{%2, %0|%0, %2}"
7142 [(set_attr "type" "sseiadd")
7143 (set_attr "atom_unit" "simul")
7144 (set_attr "prefix_data16" "1")
7145 (set_attr "mode" "TI")])
7147 (define_insn "avx_movmskp<avxmodesuffixf2c>256"
7148 [(set (match_operand:SI 0 "register_operand" "=r")
7150 [(match_operand:AVX256MODEF2P 1 "register_operand" "x")]
7152 "AVX256_VEC_FLOAT_MODE_P (<MODE>mode)"
7153 "vmovmskp<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
7154 [(set_attr "type" "ssecvt")
7155 (set_attr "prefix" "vex")
7156 (set_attr "mode" "<MODE>")])
7158 (define_insn "<sse>_movmskp<ssemodesuffixf2c>"
7159 [(set (match_operand:SI 0 "register_operand" "=r")
7161 [(match_operand:SSEMODEF2P 1 "register_operand" "x")]
7163 "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
7164 "%vmovmskp<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
7165 [(set_attr "type" "ssemov")
7166 (set_attr "prefix" "maybe_vex")
7167 (set_attr "mode" "<MODE>")])
7169 (define_insn "sse2_pmovmskb"
7170 [(set (match_operand:SI 0 "register_operand" "=r")
7171 (unspec:SI [(match_operand:V16QI 1 "register_operand" "x")]
7174 "%vpmovmskb\t{%1, %0|%0, %1}"
7175 [(set_attr "type" "ssemov")
7176 (set_attr "prefix_data16" "1")
7177 (set_attr "prefix" "maybe_vex")
7178 (set_attr "mode" "SI")])
7180 (define_expand "sse2_maskmovdqu"
7181 [(set (match_operand:V16QI 0 "memory_operand" "")
7182 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "")
7183 (match_operand:V16QI 2 "register_operand" "")
7189 (define_insn "*sse2_maskmovdqu"
7190 [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
7191 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
7192 (match_operand:V16QI 2 "register_operand" "x")
7193 (mem:V16QI (match_dup 0))]
7195 "TARGET_SSE2 && !TARGET_64BIT"
7196 ;; @@@ check ordering of operands in intel/nonintel syntax
7197 "%vmaskmovdqu\t{%2, %1|%1, %2}"
7198 [(set_attr "type" "ssemov")
7199 (set_attr "prefix_data16" "1")
7200 ;; The implicit %rdi operand confuses default length_vex computation.
7201 (set_attr "length_vex" "3")
7202 (set_attr "prefix" "maybe_vex")
7203 (set_attr "mode" "TI")])
7205 (define_insn "*sse2_maskmovdqu_rex64"
7206 [(set (mem:V16QI (match_operand:DI 0 "register_operand" "D"))
7207 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
7208 (match_operand:V16QI 2 "register_operand" "x")
7209 (mem:V16QI (match_dup 0))]
7211 "TARGET_SSE2 && TARGET_64BIT"
7212 ;; @@@ check ordering of operands in intel/nonintel syntax
7213 "%vmaskmovdqu\t{%2, %1|%1, %2}"
7214 [(set_attr "type" "ssemov")
7215 (set_attr "prefix_data16" "1")
7216 ;; The implicit %rdi operand confuses default length_vex computation.
7217 (set (attr "length_vex")
7218 (symbol_ref ("REGNO (operands[2]) >= FIRST_REX_SSE_REG ? 3 + 1 : 2 + 1")))
7219 (set_attr "prefix" "maybe_vex")
7220 (set_attr "mode" "TI")])
7222 (define_insn "sse_ldmxcsr"
7223 [(unspec_volatile [(match_operand:SI 0 "memory_operand" "m")]
7227 [(set_attr "type" "sse")
7228 (set_attr "atom_sse_attr" "mxcsr")
7229 (set_attr "prefix" "maybe_vex")
7230 (set_attr "memory" "load")])
7232 (define_insn "sse_stmxcsr"
7233 [(set (match_operand:SI 0 "memory_operand" "=m")
7234 (unspec_volatile:SI [(const_int 0)] UNSPECV_STMXCSR))]
7237 [(set_attr "type" "sse")
7238 (set_attr "atom_sse_attr" "mxcsr")
7239 (set_attr "prefix" "maybe_vex")
7240 (set_attr "memory" "store")])
7242 (define_expand "sse_sfence"
7244 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
7245 "TARGET_SSE || TARGET_3DNOW_A"
7247 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7248 MEM_VOLATILE_P (operands[0]) = 1;
7251 (define_insn "*sse_sfence"
7252 [(set (match_operand:BLK 0 "" "")
7253 (unspec:BLK [(match_dup 0)] UNSPEC_SFENCE))]
7254 "TARGET_SSE || TARGET_3DNOW_A"
7256 [(set_attr "type" "sse")
7257 (set_attr "length_address" "0")
7258 (set_attr "atom_sse_attr" "fence")
7259 (set_attr "memory" "unknown")])
7261 (define_insn "sse2_clflush"
7262 [(unspec_volatile [(match_operand 0 "address_operand" "p")]
7266 [(set_attr "type" "sse")
7267 (set_attr "atom_sse_attr" "fence")
7268 (set_attr "memory" "unknown")])
7270 (define_expand "sse2_mfence"
7272 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
7275 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7276 MEM_VOLATILE_P (operands[0]) = 1;
7279 (define_insn "*sse2_mfence"
7280 [(set (match_operand:BLK 0 "" "")
7281 (unspec:BLK [(match_dup 0)] UNSPEC_MFENCE))]
7282 "TARGET_64BIT || TARGET_SSE2"
7284 [(set_attr "type" "sse")
7285 (set_attr "length_address" "0")
7286 (set_attr "atom_sse_attr" "fence")
7287 (set_attr "memory" "unknown")])
7289 (define_expand "sse2_lfence"
7291 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
7294 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
7295 MEM_VOLATILE_P (operands[0]) = 1;
7298 (define_insn "*sse2_lfence"
7299 [(set (match_operand:BLK 0 "" "")
7300 (unspec:BLK [(match_dup 0)] UNSPEC_LFENCE))]
7303 [(set_attr "type" "sse")
7304 (set_attr "length_address" "0")
7305 (set_attr "atom_sse_attr" "lfence")
7306 (set_attr "memory" "unknown")])
7308 (define_insn "sse3_mwait"
7309 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
7310 (match_operand:SI 1 "register_operand" "c")]
7313 ;; 64bit version is "mwait %rax,%rcx". But only lower 32bits are used.
7314 ;; Since 32bit register operands are implicitly zero extended to 64bit,
7315 ;; we only need to set up 32bit registers.
7317 [(set_attr "length" "3")])
7319 (define_insn "sse3_monitor"
7320 [(unspec_volatile [(match_operand:SI 0 "register_operand" "a")
7321 (match_operand:SI 1 "register_operand" "c")
7322 (match_operand:SI 2 "register_operand" "d")]
7324 "TARGET_SSE3 && !TARGET_64BIT"
7325 "monitor\t%0, %1, %2"
7326 [(set_attr "length" "3")])
7328 (define_insn "sse3_monitor64"
7329 [(unspec_volatile [(match_operand:DI 0 "register_operand" "a")
7330 (match_operand:SI 1 "register_operand" "c")
7331 (match_operand:SI 2 "register_operand" "d")]
7333 "TARGET_SSE3 && TARGET_64BIT"
7334 ;; 64bit version is "monitor %rax,%rcx,%rdx". But only lower 32bits in
7335 ;; RCX and RDX are used. Since 32bit register operands are implicitly
7336 ;; zero extended to 64bit, we only need to set up 32bit registers.
7338 [(set_attr "length" "3")])
7340 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7342 ;; SSSE3 instructions
7344 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
7346 (define_insn "*avx_phaddwv8hi3"
7347 [(set (match_operand:V8HI 0 "register_operand" "=x")
7353 (match_operand:V8HI 1 "register_operand" "x")
7354 (parallel [(const_int 0)]))
7355 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7357 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7358 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7361 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7362 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7364 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7365 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7370 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7371 (parallel [(const_int 0)]))
7372 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7374 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7375 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7378 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7379 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7381 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7382 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7384 "vphaddw\t{%2, %1, %0|%0, %1, %2}"
7385 [(set_attr "type" "sseiadd")
7386 (set_attr "prefix_extra" "1")
7387 (set_attr "prefix" "vex")
7388 (set_attr "mode" "TI")])
7390 (define_insn "ssse3_phaddwv8hi3"
7391 [(set (match_operand:V8HI 0 "register_operand" "=x")
7397 (match_operand:V8HI 1 "register_operand" "0")
7398 (parallel [(const_int 0)]))
7399 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7401 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7402 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7405 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7406 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7408 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7409 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7414 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7415 (parallel [(const_int 0)]))
7416 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7418 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7419 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7422 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7423 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7425 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7426 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7428 "phaddw\t{%2, %0|%0, %2}"
7429 [(set_attr "type" "sseiadd")
7430 (set_attr "atom_unit" "complex")
7431 (set_attr "prefix_data16" "1")
7432 (set_attr "prefix_extra" "1")
7433 (set_attr "mode" "TI")])
7435 (define_insn "ssse3_phaddwv4hi3"
7436 [(set (match_operand:V4HI 0 "register_operand" "=y")
7441 (match_operand:V4HI 1 "register_operand" "0")
7442 (parallel [(const_int 0)]))
7443 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7445 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7446 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7450 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
7451 (parallel [(const_int 0)]))
7452 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7454 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7455 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
7457 "phaddw\t{%2, %0|%0, %2}"
7458 [(set_attr "type" "sseiadd")
7459 (set_attr "atom_unit" "complex")
7460 (set_attr "prefix_extra" "1")
7461 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
7462 (set_attr "mode" "DI")])
7464 (define_insn "*avx_phadddv4si3"
7465 [(set (match_operand:V4SI 0 "register_operand" "=x")
7470 (match_operand:V4SI 1 "register_operand" "x")
7471 (parallel [(const_int 0)]))
7472 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
7474 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
7475 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
7479 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
7480 (parallel [(const_int 0)]))
7481 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
7483 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
7484 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
7486 "vphaddd\t{%2, %1, %0|%0, %1, %2}"
7487 [(set_attr "type" "sseiadd")
7488 (set_attr "prefix_extra" "1")
7489 (set_attr "prefix" "vex")
7490 (set_attr "mode" "TI")])
7492 (define_insn "ssse3_phadddv4si3"
7493 [(set (match_operand:V4SI 0 "register_operand" "=x")
7498 (match_operand:V4SI 1 "register_operand" "0")
7499 (parallel [(const_int 0)]))
7500 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
7502 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
7503 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
7507 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
7508 (parallel [(const_int 0)]))
7509 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
7511 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
7512 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
7514 "phaddd\t{%2, %0|%0, %2}"
7515 [(set_attr "type" "sseiadd")
7516 (set_attr "atom_unit" "complex")
7517 (set_attr "prefix_data16" "1")
7518 (set_attr "prefix_extra" "1")
7519 (set_attr "mode" "TI")])
7521 (define_insn "ssse3_phadddv2si3"
7522 [(set (match_operand:V2SI 0 "register_operand" "=y")
7526 (match_operand:V2SI 1 "register_operand" "0")
7527 (parallel [(const_int 0)]))
7528 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
7531 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
7532 (parallel [(const_int 0)]))
7533 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
7535 "phaddd\t{%2, %0|%0, %2}"
7536 [(set_attr "type" "sseiadd")
7537 (set_attr "atom_unit" "complex")
7538 (set_attr "prefix_extra" "1")
7539 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
7540 (set_attr "mode" "DI")])
7542 (define_insn "*avx_phaddswv8hi3"
7543 [(set (match_operand:V8HI 0 "register_operand" "=x")
7549 (match_operand:V8HI 1 "register_operand" "x")
7550 (parallel [(const_int 0)]))
7551 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7553 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7554 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7557 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7558 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7560 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7561 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7566 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7567 (parallel [(const_int 0)]))
7568 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7570 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7571 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7574 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7575 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7577 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7578 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7580 "vphaddsw\t{%2, %1, %0|%0, %1, %2}"
7581 [(set_attr "type" "sseiadd")
7582 (set_attr "prefix_extra" "1")
7583 (set_attr "prefix" "vex")
7584 (set_attr "mode" "TI")])
7586 (define_insn "ssse3_phaddswv8hi3"
7587 [(set (match_operand:V8HI 0 "register_operand" "=x")
7593 (match_operand:V8HI 1 "register_operand" "0")
7594 (parallel [(const_int 0)]))
7595 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7597 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7598 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7601 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7602 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7604 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7605 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7610 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7611 (parallel [(const_int 0)]))
7612 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7614 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7615 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7618 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7619 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7621 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7622 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7624 "phaddsw\t{%2, %0|%0, %2}"
7625 [(set_attr "type" "sseiadd")
7626 (set_attr "atom_unit" "complex")
7627 (set_attr "prefix_data16" "1")
7628 (set_attr "prefix_extra" "1")
7629 (set_attr "mode" "TI")])
7631 (define_insn "ssse3_phaddswv4hi3"
7632 [(set (match_operand:V4HI 0 "register_operand" "=y")
7637 (match_operand:V4HI 1 "register_operand" "0")
7638 (parallel [(const_int 0)]))
7639 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7641 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7642 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7646 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
7647 (parallel [(const_int 0)]))
7648 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7650 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7651 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
7653 "phaddsw\t{%2, %0|%0, %2}"
7654 [(set_attr "type" "sseiadd")
7655 (set_attr "atom_unit" "complex")
7656 (set_attr "prefix_extra" "1")
7657 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
7658 (set_attr "mode" "DI")])
7660 (define_insn "*avx_phsubwv8hi3"
7661 [(set (match_operand:V8HI 0 "register_operand" "=x")
7667 (match_operand:V8HI 1 "register_operand" "x")
7668 (parallel [(const_int 0)]))
7669 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7671 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7672 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7675 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7676 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7678 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7679 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7684 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7685 (parallel [(const_int 0)]))
7686 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7688 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7689 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7692 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7693 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7695 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7696 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7698 "vphsubw\t{%2, %1, %0|%0, %1, %2}"
7699 [(set_attr "type" "sseiadd")
7700 (set_attr "prefix_extra" "1")
7701 (set_attr "prefix" "vex")
7702 (set_attr "mode" "TI")])
7704 (define_insn "ssse3_phsubwv8hi3"
7705 [(set (match_operand:V8HI 0 "register_operand" "=x")
7711 (match_operand:V8HI 1 "register_operand" "0")
7712 (parallel [(const_int 0)]))
7713 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7715 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7716 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7719 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7720 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7722 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7723 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7728 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7729 (parallel [(const_int 0)]))
7730 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7732 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7733 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7736 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7737 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7739 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7740 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7742 "phsubw\t{%2, %0|%0, %2}"
7743 [(set_attr "type" "sseiadd")
7744 (set_attr "atom_unit" "complex")
7745 (set_attr "prefix_data16" "1")
7746 (set_attr "prefix_extra" "1")
7747 (set_attr "mode" "TI")])
7749 (define_insn "ssse3_phsubwv4hi3"
7750 [(set (match_operand:V4HI 0 "register_operand" "=y")
7755 (match_operand:V4HI 1 "register_operand" "0")
7756 (parallel [(const_int 0)]))
7757 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7759 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7760 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7764 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
7765 (parallel [(const_int 0)]))
7766 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7768 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7769 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
7771 "phsubw\t{%2, %0|%0, %2}"
7772 [(set_attr "type" "sseiadd")
7773 (set_attr "atom_unit" "complex")
7774 (set_attr "prefix_extra" "1")
7775 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
7776 (set_attr "mode" "DI")])
7778 (define_insn "*avx_phsubdv4si3"
7779 [(set (match_operand:V4SI 0 "register_operand" "=x")
7784 (match_operand:V4SI 1 "register_operand" "x")
7785 (parallel [(const_int 0)]))
7786 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
7788 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
7789 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
7793 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
7794 (parallel [(const_int 0)]))
7795 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
7797 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
7798 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
7800 "vphsubd\t{%2, %1, %0|%0, %1, %2}"
7801 [(set_attr "type" "sseiadd")
7802 (set_attr "prefix_extra" "1")
7803 (set_attr "prefix" "vex")
7804 (set_attr "mode" "TI")])
7806 (define_insn "ssse3_phsubdv4si3"
7807 [(set (match_operand:V4SI 0 "register_operand" "=x")
7812 (match_operand:V4SI 1 "register_operand" "0")
7813 (parallel [(const_int 0)]))
7814 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
7816 (vec_select:SI (match_dup 1) (parallel [(const_int 2)]))
7817 (vec_select:SI (match_dup 1) (parallel [(const_int 3)]))))
7821 (match_operand:V4SI 2 "nonimmediate_operand" "xm")
7822 (parallel [(const_int 0)]))
7823 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))
7825 (vec_select:SI (match_dup 2) (parallel [(const_int 2)]))
7826 (vec_select:SI (match_dup 2) (parallel [(const_int 3)]))))))]
7828 "phsubd\t{%2, %0|%0, %2}"
7829 [(set_attr "type" "sseiadd")
7830 (set_attr "atom_unit" "complex")
7831 (set_attr "prefix_data16" "1")
7832 (set_attr "prefix_extra" "1")
7833 (set_attr "mode" "TI")])
7835 (define_insn "ssse3_phsubdv2si3"
7836 [(set (match_operand:V2SI 0 "register_operand" "=y")
7840 (match_operand:V2SI 1 "register_operand" "0")
7841 (parallel [(const_int 0)]))
7842 (vec_select:SI (match_dup 1) (parallel [(const_int 1)])))
7845 (match_operand:V2SI 2 "nonimmediate_operand" "ym")
7846 (parallel [(const_int 0)]))
7847 (vec_select:SI (match_dup 2) (parallel [(const_int 1)])))))]
7849 "phsubd\t{%2, %0|%0, %2}"
7850 [(set_attr "type" "sseiadd")
7851 (set_attr "atom_unit" "complex")
7852 (set_attr "prefix_extra" "1")
7853 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
7854 (set_attr "mode" "DI")])
7856 (define_insn "*avx_phsubswv8hi3"
7857 [(set (match_operand:V8HI 0 "register_operand" "=x")
7863 (match_operand:V8HI 1 "register_operand" "x")
7864 (parallel [(const_int 0)]))
7865 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7867 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7868 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7871 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7872 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7874 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7875 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7880 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7881 (parallel [(const_int 0)]))
7882 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7884 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7885 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7888 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7889 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7891 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7892 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7894 "vphsubsw\t{%2, %1, %0|%0, %1, %2}"
7895 [(set_attr "type" "sseiadd")
7896 (set_attr "prefix_extra" "1")
7897 (set_attr "prefix" "vex")
7898 (set_attr "mode" "TI")])
7900 (define_insn "ssse3_phsubswv8hi3"
7901 [(set (match_operand:V8HI 0 "register_operand" "=x")
7907 (match_operand:V8HI 1 "register_operand" "0")
7908 (parallel [(const_int 0)]))
7909 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7911 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7912 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7915 (vec_select:HI (match_dup 1) (parallel [(const_int 4)]))
7916 (vec_select:HI (match_dup 1) (parallel [(const_int 5)])))
7918 (vec_select:HI (match_dup 1) (parallel [(const_int 6)]))
7919 (vec_select:HI (match_dup 1) (parallel [(const_int 7)])))))
7924 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
7925 (parallel [(const_int 0)]))
7926 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7928 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7929 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))
7932 (vec_select:HI (match_dup 2) (parallel [(const_int 4)]))
7933 (vec_select:HI (match_dup 2) (parallel [(const_int 5)])))
7935 (vec_select:HI (match_dup 2) (parallel [(const_int 6)]))
7936 (vec_select:HI (match_dup 2) (parallel [(const_int 7)])))))))]
7938 "phsubsw\t{%2, %0|%0, %2}"
7939 [(set_attr "type" "sseiadd")
7940 (set_attr "atom_unit" "complex")
7941 (set_attr "prefix_data16" "1")
7942 (set_attr "prefix_extra" "1")
7943 (set_attr "mode" "TI")])
7945 (define_insn "ssse3_phsubswv4hi3"
7946 [(set (match_operand:V4HI 0 "register_operand" "=y")
7951 (match_operand:V4HI 1 "register_operand" "0")
7952 (parallel [(const_int 0)]))
7953 (vec_select:HI (match_dup 1) (parallel [(const_int 1)])))
7955 (vec_select:HI (match_dup 1) (parallel [(const_int 2)]))
7956 (vec_select:HI (match_dup 1) (parallel [(const_int 3)]))))
7960 (match_operand:V4HI 2 "nonimmediate_operand" "ym")
7961 (parallel [(const_int 0)]))
7962 (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))
7964 (vec_select:HI (match_dup 2) (parallel [(const_int 2)]))
7965 (vec_select:HI (match_dup 2) (parallel [(const_int 3)]))))))]
7967 "phsubsw\t{%2, %0|%0, %2}"
7968 [(set_attr "type" "sseiadd")
7969 (set_attr "atom_unit" "complex")
7970 (set_attr "prefix_extra" "1")
7971 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
7972 (set_attr "mode" "DI")])
7974 (define_insn "*avx_pmaddubsw128"
7975 [(set (match_operand:V8HI 0 "register_operand" "=x")
7980 (match_operand:V16QI 1 "register_operand" "x")
7981 (parallel [(const_int 0)
7991 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
7992 (parallel [(const_int 0)
8002 (vec_select:V16QI (match_dup 1)
8003 (parallel [(const_int 1)
8012 (vec_select:V16QI (match_dup 2)
8013 (parallel [(const_int 1)
8020 (const_int 15)]))))))]
8022 "vpmaddubsw\t{%2, %1, %0|%0, %1, %2}"
8023 [(set_attr "type" "sseiadd")
8024 (set_attr "prefix_extra" "1")
8025 (set_attr "prefix" "vex")
8026 (set_attr "mode" "TI")])
8028 (define_insn "ssse3_pmaddubsw128"
8029 [(set (match_operand:V8HI 0 "register_operand" "=x")
8034 (match_operand:V16QI 1 "register_operand" "0")
8035 (parallel [(const_int 0)
8045 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
8046 (parallel [(const_int 0)
8056 (vec_select:V16QI (match_dup 1)
8057 (parallel [(const_int 1)
8066 (vec_select:V16QI (match_dup 2)
8067 (parallel [(const_int 1)
8074 (const_int 15)]))))))]
8076 "pmaddubsw\t{%2, %0|%0, %2}"
8077 [(set_attr "type" "sseiadd")
8078 (set_attr "atom_unit" "simul")
8079 (set_attr "prefix_data16" "1")
8080 (set_attr "prefix_extra" "1")
8081 (set_attr "mode" "TI")])
8083 (define_insn "ssse3_pmaddubsw"
8084 [(set (match_operand:V4HI 0 "register_operand" "=y")
8089 (match_operand:V8QI 1 "register_operand" "0")
8090 (parallel [(const_int 0)
8096 (match_operand:V8QI 2 "nonimmediate_operand" "ym")
8097 (parallel [(const_int 0)
8103 (vec_select:V8QI (match_dup 1)
8104 (parallel [(const_int 1)
8109 (vec_select:V8QI (match_dup 2)
8110 (parallel [(const_int 1)
8113 (const_int 7)]))))))]
8115 "pmaddubsw\t{%2, %0|%0, %2}"
8116 [(set_attr "type" "sseiadd")
8117 (set_attr "atom_unit" "simul")
8118 (set_attr "prefix_extra" "1")
8119 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8120 (set_attr "mode" "DI")])
8122 (define_expand "ssse3_pmulhrswv8hi3"
8123 [(set (match_operand:V8HI 0 "register_operand" "")
8130 (match_operand:V8HI 1 "nonimmediate_operand" ""))
8132 (match_operand:V8HI 2 "nonimmediate_operand" "")))
8134 (const_vector:V8HI [(const_int 1) (const_int 1)
8135 (const_int 1) (const_int 1)
8136 (const_int 1) (const_int 1)
8137 (const_int 1) (const_int 1)]))
8140 "ix86_fixup_binary_operands_no_copy (MULT, V8HImode, operands);")
8142 (define_insn "*avx_pmulhrswv8hi3"
8143 [(set (match_operand:V8HI 0 "register_operand" "=x")
8150 (match_operand:V8HI 1 "nonimmediate_operand" "%x"))
8152 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
8154 (const_vector:V8HI [(const_int 1) (const_int 1)
8155 (const_int 1) (const_int 1)
8156 (const_int 1) (const_int 1)
8157 (const_int 1) (const_int 1)]))
8159 "TARGET_AVX && ix86_binary_operator_ok (MULT, V8HImode, operands)"
8160 "vpmulhrsw\t{%2, %1, %0|%0, %1, %2}"
8161 [(set_attr "type" "sseimul")
8162 (set_attr "prefix_extra" "1")
8163 (set_attr "prefix" "vex")
8164 (set_attr "mode" "TI")])
8166 (define_insn "*ssse3_pmulhrswv8hi3"
8167 [(set (match_operand:V8HI 0 "register_operand" "=x")
8174 (match_operand:V8HI 1 "nonimmediate_operand" "%0"))
8176 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))
8178 (const_vector:V8HI [(const_int 1) (const_int 1)
8179 (const_int 1) (const_int 1)
8180 (const_int 1) (const_int 1)
8181 (const_int 1) (const_int 1)]))
8183 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V8HImode, operands)"
8184 "pmulhrsw\t{%2, %0|%0, %2}"
8185 [(set_attr "type" "sseimul")
8186 (set_attr "prefix_data16" "1")
8187 (set_attr "prefix_extra" "1")
8188 (set_attr "mode" "TI")])
8190 (define_expand "ssse3_pmulhrswv4hi3"
8191 [(set (match_operand:V4HI 0 "register_operand" "")
8198 (match_operand:V4HI 1 "nonimmediate_operand" ""))
8200 (match_operand:V4HI 2 "nonimmediate_operand" "")))
8202 (const_vector:V4HI [(const_int 1) (const_int 1)
8203 (const_int 1) (const_int 1)]))
8206 "ix86_fixup_binary_operands_no_copy (MULT, V4HImode, operands);")
8208 (define_insn "*ssse3_pmulhrswv4hi3"
8209 [(set (match_operand:V4HI 0 "register_operand" "=y")
8216 (match_operand:V4HI 1 "nonimmediate_operand" "%0"))
8218 (match_operand:V4HI 2 "nonimmediate_operand" "ym")))
8220 (const_vector:V4HI [(const_int 1) (const_int 1)
8221 (const_int 1) (const_int 1)]))
8223 "TARGET_SSSE3 && ix86_binary_operator_ok (MULT, V4HImode, operands)"
8224 "pmulhrsw\t{%2, %0|%0, %2}"
8225 [(set_attr "type" "sseimul")
8226 (set_attr "prefix_extra" "1")
8227 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8228 (set_attr "mode" "DI")])
8230 (define_insn "*avx_pshufbv16qi3"
8231 [(set (match_operand:V16QI 0 "register_operand" "=x")
8232 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
8233 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
8236 "vpshufb\t{%2, %1, %0|%0, %1, %2}";
8237 [(set_attr "type" "sselog1")
8238 (set_attr "prefix_extra" "1")
8239 (set_attr "prefix" "vex")
8240 (set_attr "mode" "TI")])
8242 (define_insn "ssse3_pshufbv16qi3"
8243 [(set (match_operand:V16QI 0 "register_operand" "=x")
8244 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
8245 (match_operand:V16QI 2 "nonimmediate_operand" "xm")]
8248 "pshufb\t{%2, %0|%0, %2}";
8249 [(set_attr "type" "sselog1")
8250 (set_attr "prefix_data16" "1")
8251 (set_attr "prefix_extra" "1")
8252 (set_attr "mode" "TI")])
8254 (define_insn "ssse3_pshufbv8qi3"
8255 [(set (match_operand:V8QI 0 "register_operand" "=y")
8256 (unspec:V8QI [(match_operand:V8QI 1 "register_operand" "0")
8257 (match_operand:V8QI 2 "nonimmediate_operand" "ym")]
8260 "pshufb\t{%2, %0|%0, %2}";
8261 [(set_attr "type" "sselog1")
8262 (set_attr "prefix_extra" "1")
8263 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8264 (set_attr "mode" "DI")])
8266 (define_insn "*avx_psign<mode>3"
8267 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
8269 [(match_operand:SSEMODE124 1 "register_operand" "x")
8270 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
8273 "vpsign<ssevecsize>\t{%2, %1, %0|%0, %1, %2}";
8274 [(set_attr "type" "sselog1")
8275 (set_attr "prefix_extra" "1")
8276 (set_attr "prefix" "vex")
8277 (set_attr "mode" "TI")])
8279 (define_insn "ssse3_psign<mode>3"
8280 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
8282 [(match_operand:SSEMODE124 1 "register_operand" "0")
8283 (match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")]
8286 "psign<ssevecsize>\t{%2, %0|%0, %2}";
8287 [(set_attr "type" "sselog1")
8288 (set_attr "prefix_data16" "1")
8289 (set_attr "prefix_extra" "1")
8290 (set_attr "mode" "TI")])
8292 (define_insn "ssse3_psign<mode>3"
8293 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
8295 [(match_operand:MMXMODEI 1 "register_operand" "0")
8296 (match_operand:MMXMODEI 2 "nonimmediate_operand" "ym")]
8299 "psign<mmxvecsize>\t{%2, %0|%0, %2}";
8300 [(set_attr "type" "sselog1")
8301 (set_attr "prefix_extra" "1")
8302 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8303 (set_attr "mode" "DI")])
8305 (define_insn "*avx_palignrti"
8306 [(set (match_operand:TI 0 "register_operand" "=x")
8307 (unspec:TI [(match_operand:TI 1 "register_operand" "x")
8308 (match_operand:TI 2 "nonimmediate_operand" "xm")
8309 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
8313 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
8314 return "vpalignr\t{%3, %2, %1, %0|%0, %1, %2, %3}";
8316 [(set_attr "type" "sseishft")
8317 (set_attr "prefix_extra" "1")
8318 (set_attr "length_immediate" "1")
8319 (set_attr "prefix" "vex")
8320 (set_attr "mode" "TI")])
8322 (define_insn "ssse3_palignrti"
8323 [(set (match_operand:TI 0 "register_operand" "=x")
8324 (unspec:TI [(match_operand:TI 1 "register_operand" "0")
8325 (match_operand:TI 2 "nonimmediate_operand" "xm")
8326 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
8330 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
8331 return "palignr\t{%3, %2, %0|%0, %2, %3}";
8333 [(set_attr "type" "sseishft")
8334 (set_attr "atom_unit" "sishuf")
8335 (set_attr "prefix_data16" "1")
8336 (set_attr "prefix_extra" "1")
8337 (set_attr "length_immediate" "1")
8338 (set_attr "mode" "TI")])
8340 (define_insn "ssse3_palignrdi"
8341 [(set (match_operand:DI 0 "register_operand" "=y")
8342 (unspec:DI [(match_operand:DI 1 "register_operand" "0")
8343 (match_operand:DI 2 "nonimmediate_operand" "ym")
8344 (match_operand:SI 3 "const_0_to_255_mul_8_operand" "n")]
8348 operands[3] = GEN_INT (INTVAL (operands[3]) / 8);
8349 return "palignr\t{%3, %2, %0|%0, %2, %3}";
8351 [(set_attr "type" "sseishft")
8352 (set_attr "atom_unit" "sishuf")
8353 (set_attr "prefix_extra" "1")
8354 (set_attr "length_immediate" "1")
8355 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8356 (set_attr "mode" "DI")])
8358 (define_insn "abs<mode>2"
8359 [(set (match_operand:SSEMODE124 0 "register_operand" "=x")
8360 (abs:SSEMODE124 (match_operand:SSEMODE124 1 "nonimmediate_operand" "xm")))]
8362 "%vpabs<ssevecsize>\t{%1, %0|%0, %1}"
8363 [(set_attr "type" "sselog1")
8364 (set_attr "prefix_data16" "1")
8365 (set_attr "prefix_extra" "1")
8366 (set_attr "prefix" "maybe_vex")
8367 (set_attr "mode" "TI")])
8369 (define_insn "abs<mode>2"
8370 [(set (match_operand:MMXMODEI 0 "register_operand" "=y")
8371 (abs:MMXMODEI (match_operand:MMXMODEI 1 "nonimmediate_operand" "ym")))]
8373 "pabs<mmxvecsize>\t{%1, %0|%0, %1}";
8374 [(set_attr "type" "sselog1")
8375 (set_attr "prefix_rep" "0")
8376 (set_attr "prefix_extra" "1")
8377 (set (attr "prefix_rex") (symbol_ref "x86_extended_reg_mentioned_p (insn)"))
8378 (set_attr "mode" "DI")])
8380 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8382 ;; AMD SSE4A instructions
8384 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8386 (define_insn "sse4a_movnt<mode>"
8387 [(set (match_operand:MODEF 0 "memory_operand" "=m")
8389 [(match_operand:MODEF 1 "register_operand" "x")]
8392 "movnts<ssemodefsuffix>\t{%1, %0|%0, %1}"
8393 [(set_attr "type" "ssemov")
8394 (set_attr "mode" "<MODE>")])
8396 (define_insn "sse4a_vmmovnt<mode>"
8397 [(set (match_operand:<ssescalarmode> 0 "memory_operand" "=m")
8398 (unspec:<ssescalarmode>
8399 [(vec_select:<ssescalarmode>
8400 (match_operand:SSEMODEF2P 1 "register_operand" "x")
8401 (parallel [(const_int 0)]))]
8404 "movnts<ssemodesuffixf2c>\t{%1, %0|%0, %1}"
8405 [(set_attr "type" "ssemov")
8406 (set_attr "mode" "<ssescalarmode>")])
8408 (define_insn "sse4a_extrqi"
8409 [(set (match_operand:V2DI 0 "register_operand" "=x")
8410 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
8411 (match_operand 2 "const_int_operand" "")
8412 (match_operand 3 "const_int_operand" "")]
8415 "extrq\t{%3, %2, %0|%0, %2, %3}"
8416 [(set_attr "type" "sse")
8417 (set_attr "prefix_data16" "1")
8418 (set_attr "length_immediate" "2")
8419 (set_attr "mode" "TI")])
8421 (define_insn "sse4a_extrq"
8422 [(set (match_operand:V2DI 0 "register_operand" "=x")
8423 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
8424 (match_operand:V16QI 2 "register_operand" "x")]
8427 "extrq\t{%2, %0|%0, %2}"
8428 [(set_attr "type" "sse")
8429 (set_attr "prefix_data16" "1")
8430 (set_attr "mode" "TI")])
8432 (define_insn "sse4a_insertqi"
8433 [(set (match_operand:V2DI 0 "register_operand" "=x")
8434 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
8435 (match_operand:V2DI 2 "register_operand" "x")
8436 (match_operand 3 "const_int_operand" "")
8437 (match_operand 4 "const_int_operand" "")]
8440 "insertq\t{%4, %3, %2, %0|%0, %2, %3, %4}"
8441 [(set_attr "type" "sseins")
8442 (set_attr "prefix_data16" "0")
8443 (set_attr "prefix_rep" "1")
8444 (set_attr "length_immediate" "2")
8445 (set_attr "mode" "TI")])
8447 (define_insn "sse4a_insertq"
8448 [(set (match_operand:V2DI 0 "register_operand" "=x")
8449 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
8450 (match_operand:V2DI 2 "register_operand" "x")]
8453 "insertq\t{%2, %0|%0, %2}"
8454 [(set_attr "type" "sseins")
8455 (set_attr "prefix_data16" "0")
8456 (set_attr "prefix_rep" "1")
8457 (set_attr "mode" "TI")])
8459 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8461 ;; Intel SSE4.1 instructions
8463 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
8465 (define_insn "avx_blendp<avxmodesuffixf2c><avxmodesuffix>"
8466 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
8467 (vec_merge:AVXMODEF2P
8468 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
8469 (match_operand:AVXMODEF2P 1 "register_operand" "x")
8470 (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
8472 "vblendp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
8473 [(set_attr "type" "ssemov")
8474 (set_attr "prefix_extra" "1")
8475 (set_attr "length_immediate" "1")
8476 (set_attr "prefix" "vex")
8477 (set_attr "mode" "<avxvecmode>")])
8479 (define_insn "avx_blendvp<avxmodesuffixf2c><avxmodesuffix>"
8480 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
8482 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
8483 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
8484 (match_operand:AVXMODEF2P 3 "register_operand" "x")]
8487 "vblendvp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
8488 [(set_attr "type" "ssemov")
8489 (set_attr "prefix_extra" "1")
8490 (set_attr "length_immediate" "1")
8491 (set_attr "prefix" "vex")
8492 (set_attr "mode" "<avxvecmode>")])
8494 (define_insn "sse4_1_blendp<ssemodesuffixf2c>"
8495 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
8496 (vec_merge:SSEMODEF2P
8497 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
8498 (match_operand:SSEMODEF2P 1 "register_operand" "0")
8499 (match_operand:SI 3 "const_0_to_<blendbits>_operand" "n")))]
8501 "blendp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
8502 [(set_attr "type" "ssemov")
8503 (set_attr "prefix_data16" "1")
8504 (set_attr "prefix_extra" "1")
8505 (set_attr "length_immediate" "1")
8506 (set_attr "mode" "<MODE>")])
8508 (define_insn "sse4_1_blendvp<ssemodesuffixf2c>"
8509 [(set (match_operand:SSEMODEF2P 0 "reg_not_xmm0_operand" "=x")
8511 [(match_operand:SSEMODEF2P 1 "reg_not_xmm0_operand" "0")
8512 (match_operand:SSEMODEF2P 2 "nonimm_not_xmm0_operand" "xm")
8513 (match_operand:SSEMODEF2P 3 "register_operand" "Yz")]
8516 "blendvp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
8517 [(set_attr "type" "ssemov")
8518 (set_attr "prefix_data16" "1")
8519 (set_attr "prefix_extra" "1")
8520 (set_attr "mode" "<MODE>")])
8522 (define_insn "avx_dpp<avxmodesuffixf2c><avxmodesuffix>"
8523 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
8525 [(match_operand:AVXMODEF2P 1 "nonimmediate_operand" "%x")
8526 (match_operand:AVXMODEF2P 2 "nonimmediate_operand" "xm")
8527 (match_operand:SI 3 "const_0_to_255_operand" "n")]
8530 "vdpp<avxmodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
8531 [(set_attr "type" "ssemul")
8532 (set_attr "prefix" "vex")
8533 (set_attr "prefix_extra" "1")
8534 (set_attr "length_immediate" "1")
8535 (set_attr "mode" "<avxvecmode>")])
8537 (define_insn "sse4_1_dpp<ssemodesuffixf2c>"
8538 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
8540 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0")
8541 (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
8542 (match_operand:SI 3 "const_0_to_255_operand" "n")]
8545 "dpp<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
8546 [(set_attr "type" "ssemul")
8547 (set_attr "prefix_data16" "1")
8548 (set_attr "prefix_extra" "1")
8549 (set_attr "length_immediate" "1")
8550 (set_attr "mode" "<MODE>")])
8552 (define_insn "sse4_1_movntdqa"
8553 [(set (match_operand:V2DI 0 "register_operand" "=x")
8554 (unspec:V2DI [(match_operand:V2DI 1 "memory_operand" "m")]
8557 "%vmovntdqa\t{%1, %0|%0, %1}"
8558 [(set_attr "type" "ssemov")
8559 (set_attr "prefix_extra" "1")
8560 (set_attr "prefix" "maybe_vex")
8561 (set_attr "mode" "TI")])
8563 (define_insn "*avx_mpsadbw"
8564 [(set (match_operand:V16QI 0 "register_operand" "=x")
8565 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
8566 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
8567 (match_operand:SI 3 "const_0_to_255_operand" "n")]
8570 "vmpsadbw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
8571 [(set_attr "type" "sselog1")
8572 (set_attr "prefix" "vex")
8573 (set_attr "prefix_extra" "1")
8574 (set_attr "length_immediate" "1")
8575 (set_attr "mode" "TI")])
8577 (define_insn "sse4_1_mpsadbw"
8578 [(set (match_operand:V16QI 0 "register_operand" "=x")
8579 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "0")
8580 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
8581 (match_operand:SI 3 "const_0_to_255_operand" "n")]
8584 "mpsadbw\t{%3, %2, %0|%0, %2, %3}"
8585 [(set_attr "type" "sselog1")
8586 (set_attr "prefix_extra" "1")
8587 (set_attr "length_immediate" "1")
8588 (set_attr "mode" "TI")])
8590 (define_insn "*avx_packusdw"
8591 [(set (match_operand:V8HI 0 "register_operand" "=x")
8594 (match_operand:V4SI 1 "register_operand" "x"))
8596 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
8598 "vpackusdw\t{%2, %1, %0|%0, %1, %2}"
8599 [(set_attr "type" "sselog")
8600 (set_attr "prefix_extra" "1")
8601 (set_attr "prefix" "vex")
8602 (set_attr "mode" "TI")])
8604 (define_insn "sse4_1_packusdw"
8605 [(set (match_operand:V8HI 0 "register_operand" "=x")
8608 (match_operand:V4SI 1 "register_operand" "0"))
8610 (match_operand:V4SI 2 "nonimmediate_operand" "xm"))))]
8612 "packusdw\t{%2, %0|%0, %2}"
8613 [(set_attr "type" "sselog")
8614 (set_attr "prefix_extra" "1")
8615 (set_attr "mode" "TI")])
8617 (define_insn "*avx_pblendvb"
8618 [(set (match_operand:V16QI 0 "register_operand" "=x")
8619 (unspec:V16QI [(match_operand:V16QI 1 "register_operand" "x")
8620 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
8621 (match_operand:V16QI 3 "register_operand" "x")]
8624 "vpblendvb\t{%3, %2, %1, %0|%0, %1, %2, %3}"
8625 [(set_attr "type" "ssemov")
8626 (set_attr "prefix_extra" "1")
8627 (set_attr "length_immediate" "1")
8628 (set_attr "prefix" "vex")
8629 (set_attr "mode" "TI")])
8631 (define_insn "sse4_1_pblendvb"
8632 [(set (match_operand:V16QI 0 "reg_not_xmm0_operand" "=x")
8633 (unspec:V16QI [(match_operand:V16QI 1 "reg_not_xmm0_operand" "0")
8634 (match_operand:V16QI 2 "nonimm_not_xmm0_operand" "xm")
8635 (match_operand:V16QI 3 "register_operand" "Yz")]
8638 "pblendvb\t{%3, %2, %0|%0, %2, %3}"
8639 [(set_attr "type" "ssemov")
8640 (set_attr "prefix_extra" "1")
8641 (set_attr "mode" "TI")])
8643 (define_insn "*avx_pblendw"
8644 [(set (match_operand:V8HI 0 "register_operand" "=x")
8646 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8647 (match_operand:V8HI 1 "register_operand" "x")
8648 (match_operand:SI 3 "const_0_to_255_operand" "n")))]
8650 "vpblendw\t{%3, %2, %1, %0|%0, %1, %2, %3}"
8651 [(set_attr "type" "ssemov")
8652 (set_attr "prefix" "vex")
8653 (set_attr "prefix_extra" "1")
8654 (set_attr "length_immediate" "1")
8655 (set_attr "mode" "TI")])
8657 (define_insn "sse4_1_pblendw"
8658 [(set (match_operand:V8HI 0 "register_operand" "=x")
8660 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
8661 (match_operand:V8HI 1 "register_operand" "0")
8662 (match_operand:SI 3 "const_0_to_255_operand" "n")))]
8664 "pblendw\t{%3, %2, %0|%0, %2, %3}"
8665 [(set_attr "type" "ssemov")
8666 (set_attr "prefix_extra" "1")
8667 (set_attr "length_immediate" "1")
8668 (set_attr "mode" "TI")])
8670 (define_insn "sse4_1_phminposuw"
8671 [(set (match_operand:V8HI 0 "register_operand" "=x")
8672 (unspec:V8HI [(match_operand:V8HI 1 "nonimmediate_operand" "xm")]
8673 UNSPEC_PHMINPOSUW))]
8675 "%vphminposuw\t{%1, %0|%0, %1}"
8676 [(set_attr "type" "sselog1")
8677 (set_attr "prefix_extra" "1")
8678 (set_attr "prefix" "maybe_vex")
8679 (set_attr "mode" "TI")])
8681 (define_insn "sse4_1_extendv8qiv8hi2"
8682 [(set (match_operand:V8HI 0 "register_operand" "=x")
8685 (match_operand:V16QI 1 "register_operand" "x")
8686 (parallel [(const_int 0)
8695 "%vpmovsxbw\t{%1, %0|%0, %1}"
8696 [(set_attr "type" "ssemov")
8697 (set_attr "prefix_extra" "1")
8698 (set_attr "prefix" "maybe_vex")
8699 (set_attr "mode" "TI")])
8701 (define_insn "*sse4_1_extendv8qiv8hi2"
8702 [(set (match_operand:V8HI 0 "register_operand" "=x")
8705 (vec_duplicate:V16QI
8706 (match_operand:V8QI 1 "nonimmediate_operand" "xm"))
8707 (parallel [(const_int 0)
8716 "%vpmovsxbw\t{%1, %0|%0, %1}"
8717 [(set_attr "type" "ssemov")
8718 (set_attr "prefix_extra" "1")
8719 (set_attr "prefix" "maybe_vex")
8720 (set_attr "mode" "TI")])
8722 (define_insn "sse4_1_extendv4qiv4si2"
8723 [(set (match_operand:V4SI 0 "register_operand" "=x")
8726 (match_operand:V16QI 1 "register_operand" "x")
8727 (parallel [(const_int 0)
8732 "%vpmovsxbd\t{%1, %0|%0, %1}"
8733 [(set_attr "type" "ssemov")
8734 (set_attr "prefix_extra" "1")
8735 (set_attr "prefix" "maybe_vex")
8736 (set_attr "mode" "TI")])
8738 (define_insn "*sse4_1_extendv4qiv4si2"
8739 [(set (match_operand:V4SI 0 "register_operand" "=x")
8742 (vec_duplicate:V16QI
8743 (match_operand:V4QI 1 "nonimmediate_operand" "xm"))
8744 (parallel [(const_int 0)
8749 "%vpmovsxbd\t{%1, %0|%0, %1}"
8750 [(set_attr "type" "ssemov")
8751 (set_attr "prefix_extra" "1")
8752 (set_attr "prefix" "maybe_vex")
8753 (set_attr "mode" "TI")])
8755 (define_insn "sse4_1_extendv2qiv2di2"
8756 [(set (match_operand:V2DI 0 "register_operand" "=x")
8759 (match_operand:V16QI 1 "register_operand" "x")
8760 (parallel [(const_int 0)
8763 "%vpmovsxbq\t{%1, %0|%0, %1}"
8764 [(set_attr "type" "ssemov")
8765 (set_attr "prefix_extra" "1")
8766 (set_attr "prefix" "maybe_vex")
8767 (set_attr "mode" "TI")])
8769 (define_insn "*sse4_1_extendv2qiv2di2"
8770 [(set (match_operand:V2DI 0 "register_operand" "=x")
8773 (vec_duplicate:V16QI
8774 (match_operand:V2QI 1 "nonimmediate_operand" "xm"))
8775 (parallel [(const_int 0)
8778 "%vpmovsxbq\t{%1, %0|%0, %1}"
8779 [(set_attr "type" "ssemov")
8780 (set_attr "prefix_extra" "1")
8781 (set_attr "prefix" "maybe_vex")
8782 (set_attr "mode" "TI")])
8784 (define_insn "sse4_1_extendv4hiv4si2"
8785 [(set (match_operand:V4SI 0 "register_operand" "=x")
8788 (match_operand:V8HI 1 "register_operand" "x")
8789 (parallel [(const_int 0)
8794 "%vpmovsxwd\t{%1, %0|%0, %1}"
8795 [(set_attr "type" "ssemov")
8796 (set_attr "prefix_extra" "1")
8797 (set_attr "prefix" "maybe_vex")
8798 (set_attr "mode" "TI")])
8800 (define_insn "*sse4_1_extendv4hiv4si2"
8801 [(set (match_operand:V4SI 0 "register_operand" "=x")
8805 (match_operand:V2HI 1 "nonimmediate_operand" "xm"))
8806 (parallel [(const_int 0)
8811 "%vpmovsxwd\t{%1, %0|%0, %1}"
8812 [(set_attr "type" "ssemov")
8813 (set_attr "prefix_extra" "1")
8814 (set_attr "prefix" "maybe_vex")
8815 (set_attr "mode" "TI")])
8817 (define_insn "sse4_1_extendv2hiv2di2"
8818 [(set (match_operand:V2DI 0 "register_operand" "=x")
8821 (match_operand:V8HI 1 "register_operand" "x")
8822 (parallel [(const_int 0)
8825 "%vpmovsxwq\t{%1, %0|%0, %1}"
8826 [(set_attr "type" "ssemov")
8827 (set_attr "prefix_extra" "1")
8828 (set_attr "prefix" "maybe_vex")
8829 (set_attr "mode" "TI")])
8831 (define_insn "*sse4_1_extendv2hiv2di2"
8832 [(set (match_operand:V2DI 0 "register_operand" "=x")
8836 (match_operand:V8HI 1 "nonimmediate_operand" "xm"))
8837 (parallel [(const_int 0)
8840 "%vpmovsxwq\t{%1, %0|%0, %1}"
8841 [(set_attr "type" "ssemov")
8842 (set_attr "prefix_extra" "1")
8843 (set_attr "prefix" "maybe_vex")
8844 (set_attr "mode" "TI")])
8846 (define_insn "sse4_1_extendv2siv2di2"
8847 [(set (match_operand:V2DI 0 "register_operand" "=x")
8850 (match_operand:V4SI 1 "register_operand" "x")
8851 (parallel [(const_int 0)
8854 "%vpmovsxdq\t{%1, %0|%0, %1}"
8855 [(set_attr "type" "ssemov")
8856 (set_attr "prefix_extra" "1")
8857 (set_attr "prefix" "maybe_vex")
8858 (set_attr "mode" "TI")])
8860 (define_insn "*sse4_1_extendv2siv2di2"
8861 [(set (match_operand:V2DI 0 "register_operand" "=x")
8865 (match_operand:V2SI 1 "nonimmediate_operand" "xm"))
8866 (parallel [(const_int 0)
8869 "%vpmovsxdq\t{%1, %0|%0, %1}"
8870 [(set_attr "type" "ssemov")
8871 (set_attr "prefix_extra" "1")
8872 (set_attr "prefix" "maybe_vex")
8873 (set_attr "mode" "TI")])
8875 (define_insn "sse4_1_zero_extendv8qiv8hi2"
8876 [(set (match_operand:V8HI 0 "register_operand" "=x")
8879 (match_operand:V16QI 1 "register_operand" "x")
8880 (parallel [(const_int 0)
8889 "%vpmovzxbw\t{%1, %0|%0, %1}"
8890 [(set_attr "type" "ssemov")
8891 (set_attr "prefix_extra" "1")
8892 (set_attr "prefix" "maybe_vex")
8893 (set_attr "mode" "TI")])
8895 (define_insn "*sse4_1_zero_extendv8qiv8hi2"
8896 [(set (match_operand:V8HI 0 "register_operand" "=x")
8899 (vec_duplicate:V16QI
8900 (match_operand:V8QI 1 "nonimmediate_operand" "xm"))
8901 (parallel [(const_int 0)
8910 "%vpmovzxbw\t{%1, %0|%0, %1}"
8911 [(set_attr "type" "ssemov")
8912 (set_attr "prefix_extra" "1")
8913 (set_attr "prefix" "maybe_vex")
8914 (set_attr "mode" "TI")])
8916 (define_insn "sse4_1_zero_extendv4qiv4si2"
8917 [(set (match_operand:V4SI 0 "register_operand" "=x")
8920 (match_operand:V16QI 1 "register_operand" "x")
8921 (parallel [(const_int 0)
8926 "%vpmovzxbd\t{%1, %0|%0, %1}"
8927 [(set_attr "type" "ssemov")
8928 (set_attr "prefix_extra" "1")
8929 (set_attr "prefix" "maybe_vex")
8930 (set_attr "mode" "TI")])
8932 (define_insn "*sse4_1_zero_extendv4qiv4si2"
8933 [(set (match_operand:V4SI 0 "register_operand" "=x")
8936 (vec_duplicate:V16QI
8937 (match_operand:V4QI 1 "nonimmediate_operand" "xm"))
8938 (parallel [(const_int 0)
8943 "%vpmovzxbd\t{%1, %0|%0, %1}"
8944 [(set_attr "type" "ssemov")
8945 (set_attr "prefix_extra" "1")
8946 (set_attr "prefix" "maybe_vex")
8947 (set_attr "mode" "TI")])
8949 (define_insn "sse4_1_zero_extendv2qiv2di2"
8950 [(set (match_operand:V2DI 0 "register_operand" "=x")
8953 (match_operand:V16QI 1 "register_operand" "x")
8954 (parallel [(const_int 0)
8957 "%vpmovzxbq\t{%1, %0|%0, %1}"
8958 [(set_attr "type" "ssemov")
8959 (set_attr "prefix_extra" "1")
8960 (set_attr "prefix" "maybe_vex")
8961 (set_attr "mode" "TI")])
8963 (define_insn "*sse4_1_zero_extendv2qiv2di2"
8964 [(set (match_operand:V2DI 0 "register_operand" "=x")
8967 (vec_duplicate:V16QI
8968 (match_operand:V2QI 1 "nonimmediate_operand" "xm"))
8969 (parallel [(const_int 0)
8972 "%vpmovzxbq\t{%1, %0|%0, %1}"
8973 [(set_attr "type" "ssemov")
8974 (set_attr "prefix_extra" "1")
8975 (set_attr "prefix" "maybe_vex")
8976 (set_attr "mode" "TI")])
8978 (define_insn "sse4_1_zero_extendv4hiv4si2"
8979 [(set (match_operand:V4SI 0 "register_operand" "=x")
8982 (match_operand:V8HI 1 "register_operand" "x")
8983 (parallel [(const_int 0)
8988 "%vpmovzxwd\t{%1, %0|%0, %1}"
8989 [(set_attr "type" "ssemov")
8990 (set_attr "prefix_extra" "1")
8991 (set_attr "prefix" "maybe_vex")
8992 (set_attr "mode" "TI")])
8994 (define_insn "*sse4_1_zero_extendv4hiv4si2"
8995 [(set (match_operand:V4SI 0 "register_operand" "=x")
8999 (match_operand:V4HI 1 "nonimmediate_operand" "xm"))
9000 (parallel [(const_int 0)
9005 "%vpmovzxwd\t{%1, %0|%0, %1}"
9006 [(set_attr "type" "ssemov")
9007 (set_attr "prefix_extra" "1")
9008 (set_attr "prefix" "maybe_vex")
9009 (set_attr "mode" "TI")])
9011 (define_insn "sse4_1_zero_extendv2hiv2di2"
9012 [(set (match_operand:V2DI 0 "register_operand" "=x")
9015 (match_operand:V8HI 1 "register_operand" "x")
9016 (parallel [(const_int 0)
9019 "%vpmovzxwq\t{%1, %0|%0, %1}"
9020 [(set_attr "type" "ssemov")
9021 (set_attr "prefix_extra" "1")
9022 (set_attr "prefix" "maybe_vex")
9023 (set_attr "mode" "TI")])
9025 (define_insn "*sse4_1_zero_extendv2hiv2di2"
9026 [(set (match_operand:V2DI 0 "register_operand" "=x")
9030 (match_operand:V2HI 1 "nonimmediate_operand" "xm"))
9031 (parallel [(const_int 0)
9034 "%vpmovzxwq\t{%1, %0|%0, %1}"
9035 [(set_attr "type" "ssemov")
9036 (set_attr "prefix_extra" "1")
9037 (set_attr "prefix" "maybe_vex")
9038 (set_attr "mode" "TI")])
9040 (define_insn "sse4_1_zero_extendv2siv2di2"
9041 [(set (match_operand:V2DI 0 "register_operand" "=x")
9044 (match_operand:V4SI 1 "register_operand" "x")
9045 (parallel [(const_int 0)
9048 "%vpmovzxdq\t{%1, %0|%0, %1}"
9049 [(set_attr "type" "ssemov")
9050 (set_attr "prefix_extra" "1")
9051 (set_attr "prefix" "maybe_vex")
9052 (set_attr "mode" "TI")])
9054 (define_insn "*sse4_1_zero_extendv2siv2di2"
9055 [(set (match_operand:V2DI 0 "register_operand" "=x")
9059 (match_operand:V2SI 1 "nonimmediate_operand" "xm"))
9060 (parallel [(const_int 0)
9063 "%vpmovzxdq\t{%1, %0|%0, %1}"
9064 [(set_attr "type" "ssemov")
9065 (set_attr "prefix_extra" "1")
9066 (set_attr "prefix" "maybe_vex")
9067 (set_attr "mode" "TI")])
9069 ;; ptestps/ptestpd are very similar to comiss and ucomiss when
9070 ;; setting FLAGS_REG. But it is not a really compare instruction.
9071 (define_insn "avx_vtestp<avxmodesuffixf2c><avxmodesuffix>"
9072 [(set (reg:CC FLAGS_REG)
9073 (unspec:CC [(match_operand:AVXMODEF2P 0 "register_operand" "x")
9074 (match_operand:AVXMODEF2P 1 "nonimmediate_operand" "xm")]
9077 "vtestp<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
9078 [(set_attr "type" "ssecomi")
9079 (set_attr "prefix_extra" "1")
9080 (set_attr "prefix" "vex")
9081 (set_attr "mode" "<MODE>")])
9083 ;; ptest is very similar to comiss and ucomiss when setting FLAGS_REG.
9084 ;; But it is not a really compare instruction.
9085 (define_insn "avx_ptest256"
9086 [(set (reg:CC FLAGS_REG)
9087 (unspec:CC [(match_operand:V4DI 0 "register_operand" "x")
9088 (match_operand:V4DI 1 "nonimmediate_operand" "xm")]
9091 "vptest\t{%1, %0|%0, %1}"
9092 [(set_attr "type" "ssecomi")
9093 (set_attr "prefix_extra" "1")
9094 (set_attr "prefix" "vex")
9095 (set_attr "mode" "OI")])
9097 (define_insn "sse4_1_ptest"
9098 [(set (reg:CC FLAGS_REG)
9099 (unspec:CC [(match_operand:V2DI 0 "register_operand" "x")
9100 (match_operand:V2DI 1 "nonimmediate_operand" "xm")]
9103 "%vptest\t{%1, %0|%0, %1}"
9104 [(set_attr "type" "ssecomi")
9105 (set_attr "prefix_extra" "1")
9106 (set_attr "prefix" "maybe_vex")
9107 (set_attr "mode" "TI")])
9109 (define_insn "avx_roundp<avxmodesuffixf2c>256"
9110 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x")
9111 (unspec:AVX256MODEF2P
9112 [(match_operand:AVX256MODEF2P 1 "nonimmediate_operand" "xm")
9113 (match_operand:SI 2 "const_0_to_15_operand" "n")]
9116 "vroundp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
9117 [(set_attr "type" "ssecvt")
9118 (set_attr "prefix_extra" "1")
9119 (set_attr "length_immediate" "1")
9120 (set_attr "prefix" "vex")
9121 (set_attr "mode" "<MODE>")])
9123 (define_insn "sse4_1_roundp<ssemodesuffixf2c>"
9124 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9126 [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")
9127 (match_operand:SI 2 "const_0_to_15_operand" "n")]
9130 "%vroundp<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
9131 [(set_attr "type" "ssecvt")
9132 (set_attr "prefix_data16" "1")
9133 (set_attr "prefix_extra" "1")
9134 (set_attr "length_immediate" "1")
9135 (set_attr "prefix" "maybe_vex")
9136 (set_attr "mode" "<MODE>")])
9138 (define_insn "*avx_rounds<ssemodesuffixf2c>"
9139 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9140 (vec_merge:SSEMODEF2P
9142 [(match_operand:SSEMODEF2P 2 "register_operand" "x")
9143 (match_operand:SI 3 "const_0_to_15_operand" "n")]
9145 (match_operand:SSEMODEF2P 1 "register_operand" "x")
9148 "vrounds<ssemodesuffixf2c>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9149 [(set_attr "type" "ssecvt")
9150 (set_attr "prefix_extra" "1")
9151 (set_attr "length_immediate" "1")
9152 (set_attr "prefix" "vex")
9153 (set_attr "mode" "<MODE>")])
9155 (define_insn "sse4_1_rounds<ssemodesuffixf2c>"
9156 [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
9157 (vec_merge:SSEMODEF2P
9159 [(match_operand:SSEMODEF2P 2 "register_operand" "x")
9160 (match_operand:SI 3 "const_0_to_15_operand" "n")]
9162 (match_operand:SSEMODEF2P 1 "register_operand" "0")
9165 "rounds<ssemodesuffixf2c>\t{%3, %2, %0|%0, %2, %3}"
9166 [(set_attr "type" "ssecvt")
9167 (set_attr "prefix_data16" "1")
9168 (set_attr "prefix_extra" "1")
9169 (set_attr "length_immediate" "1")
9170 (set_attr "mode" "<MODE>")])
9172 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9174 ;; Intel SSE4.2 string/text processing instructions
9176 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
9178 (define_insn_and_split "sse4_2_pcmpestr"
9179 [(set (match_operand:SI 0 "register_operand" "=c,c")
9181 [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
9182 (match_operand:SI 3 "register_operand" "a,a")
9183 (match_operand:V16QI 4 "nonimm_not_xmm0_operand" "x,m")
9184 (match_operand:SI 5 "register_operand" "d,d")
9185 (match_operand:SI 6 "const_0_to_255_operand" "n,n")]
9187 (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
9195 (set (reg:CC FLAGS_REG)
9204 && can_create_pseudo_p ()"
9209 int ecx = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0]));
9210 int xmm0 = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[1]));
9211 int flags = !find_regno_note (curr_insn, REG_UNUSED, FLAGS_REG);
9214 emit_insn (gen_sse4_2_pcmpestri (operands[0], operands[2],
9215 operands[3], operands[4],
9216 operands[5], operands[6]));
9218 emit_insn (gen_sse4_2_pcmpestrm (operands[1], operands[2],
9219 operands[3], operands[4],
9220 operands[5], operands[6]));
9221 if (flags && !(ecx || xmm0))
9222 emit_insn (gen_sse4_2_pcmpestr_cconly (NULL, NULL,
9223 operands[2], operands[3],
9224 operands[4], operands[5],
9228 [(set_attr "type" "sselog")
9229 (set_attr "prefix_data16" "1")
9230 (set_attr "prefix_extra" "1")
9231 (set_attr "length_immediate" "1")
9232 (set_attr "memory" "none,load")
9233 (set_attr "mode" "TI")])
9235 (define_insn "sse4_2_pcmpestri"
9236 [(set (match_operand:SI 0 "register_operand" "=c,c")
9238 [(match_operand:V16QI 1 "register_operand" "x,x")
9239 (match_operand:SI 2 "register_operand" "a,a")
9240 (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
9241 (match_operand:SI 4 "register_operand" "d,d")
9242 (match_operand:SI 5 "const_0_to_255_operand" "n,n")]
9244 (set (reg:CC FLAGS_REG)
9253 "%vpcmpestri\t{%5, %3, %1|%1, %3, %5}"
9254 [(set_attr "type" "sselog")
9255 (set_attr "prefix_data16" "1")
9256 (set_attr "prefix_extra" "1")
9257 (set_attr "prefix" "maybe_vex")
9258 (set_attr "length_immediate" "1")
9259 (set_attr "memory" "none,load")
9260 (set_attr "mode" "TI")])
9262 (define_insn "sse4_2_pcmpestrm"
9263 [(set (match_operand:V16QI 0 "register_operand" "=Yz,Yz")
9265 [(match_operand:V16QI 1 "register_operand" "x,x")
9266 (match_operand:SI 2 "register_operand" "a,a")
9267 (match_operand:V16QI 3 "nonimmediate_operand" "x,m")
9268 (match_operand:SI 4 "register_operand" "d,d")
9269 (match_operand:SI 5 "const_0_to_255_operand" "n,n")]
9271 (set (reg:CC FLAGS_REG)
9280 "%vpcmpestrm\t{%5, %3, %1|%1, %3, %5}"
9281 [(set_attr "type" "sselog")
9282 (set_attr "prefix_data16" "1")
9283 (set_attr "prefix_extra" "1")
9284 (set_attr "length_immediate" "1")
9285 (set_attr "prefix" "maybe_vex")
9286 (set_attr "memory" "none,load")
9287 (set_attr "mode" "TI")])
9289 (define_insn "sse4_2_pcmpestr_cconly"
9290 [(set (reg:CC FLAGS_REG)
9292 [(match_operand:V16QI 2 "register_operand" "x,x,x,x")
9293 (match_operand:SI 3 "register_operand" "a,a,a,a")
9294 (match_operand:V16QI 4 "nonimmediate_operand" "x,m,x,m")
9295 (match_operand:SI 5 "register_operand" "d,d,d,d")
9296 (match_operand:SI 6 "const_0_to_255_operand" "n,n,n,n")]
9298 (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X"))
9299 (clobber (match_scratch:SI 1 "= X, X,c,c"))]
9302 %vpcmpestrm\t{%6, %4, %2|%2, %4, %6}
9303 %vpcmpestrm\t{%6, %4, %2|%2, %4, %6}
9304 %vpcmpestri\t{%6, %4, %2|%2, %4, %6}
9305 %vpcmpestri\t{%6, %4, %2|%2, %4, %6}"
9306 [(set_attr "type" "sselog")
9307 (set_attr "prefix_data16" "1")
9308 (set_attr "prefix_extra" "1")
9309 (set_attr "length_immediate" "1")
9310 (set_attr "memory" "none,load,none,load")
9311 (set_attr "prefix" "maybe_vex")
9312 (set_attr "mode" "TI")])
9314 (define_insn_and_split "sse4_2_pcmpistr"
9315 [(set (match_operand:SI 0 "register_operand" "=c,c")
9317 [(match_operand:V16QI 2 "reg_not_xmm0_operand" "x,x")
9318 (match_operand:V16QI 3 "nonimm_not_xmm0_operand" "x,m")
9319 (match_operand:SI 4 "const_0_to_255_operand" "n,n")]
9321 (set (match_operand:V16QI 1 "register_operand" "=Yz,Yz")
9327 (set (reg:CC FLAGS_REG)
9334 && can_create_pseudo_p ()"
9339 int ecx = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[0]));
9340 int xmm0 = !find_regno_note (curr_insn, REG_UNUSED, REGNO (operands[1]));
9341 int flags = !find_regno_note (curr_insn, REG_UNUSED, FLAGS_REG);
9344 emit_insn (gen_sse4_2_pcmpistri (operands[0], operands[2],
9345 operands[3], operands[4]));
9347 emit_insn (gen_sse4_2_pcmpistrm (operands[1], operands[2],
9348 operands[3], operands[4]));
9349 if (flags && !(ecx || xmm0))
9350 emit_insn (gen_sse4_2_pcmpistr_cconly (NULL, NULL,
9351 operands[2], operands[3],
9355 [(set_attr "type" "sselog")
9356 (set_attr "prefix_data16" "1")
9357 (set_attr "prefix_extra" "1")
9358 (set_attr "length_immediate" "1")
9359 (set_attr "memory" "none,load")
9360 (set_attr "mode" "TI")])
9362 (define_insn "sse4_2_pcmpistri"
9363 [(set (match_operand:SI 0 "register_operand" "=c,c")
9365 [(match_operand:V16QI 1 "register_operand" "x,x")
9366 (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
9367 (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
9369 (set (reg:CC FLAGS_REG)
9376 "%vpcmpistri\t{%3, %2, %1|%1, %2, %3}"
9377 [(set_attr "type" "sselog")
9378 (set_attr "prefix_data16" "1")
9379 (set_attr "prefix_extra" "1")
9380 (set_attr "length_immediate" "1")
9381 (set_attr "prefix" "maybe_vex")
9382 (set_attr "memory" "none,load")
9383 (set_attr "mode" "TI")])
9385 (define_insn "sse4_2_pcmpistrm"
9386 [(set (match_operand:V16QI 0 "register_operand" "=Yz,Yz")
9388 [(match_operand:V16QI 1 "register_operand" "x,x")
9389 (match_operand:V16QI 2 "nonimmediate_operand" "x,m")
9390 (match_operand:SI 3 "const_0_to_255_operand" "n,n")]
9392 (set (reg:CC FLAGS_REG)
9399 "%vpcmpistrm\t{%3, %2, %1|%1, %2, %3}"
9400 [(set_attr "type" "sselog")
9401 (set_attr "prefix_data16" "1")
9402 (set_attr "prefix_extra" "1")
9403 (set_attr "length_immediate" "1")
9404 (set_attr "prefix" "maybe_vex")
9405 (set_attr "memory" "none,load")
9406 (set_attr "mode" "TI")])
9408 (define_insn "sse4_2_pcmpistr_cconly"
9409 [(set (reg:CC FLAGS_REG)
9411 [(match_operand:V16QI 2 "register_operand" "x,x,x,x")
9412 (match_operand:V16QI 3 "nonimmediate_operand" "x,m,x,m")
9413 (match_operand:SI 4 "const_0_to_255_operand" "n,n,n,n")]
9415 (clobber (match_scratch:V16QI 0 "=Yz,Yz,X,X"))
9416 (clobber (match_scratch:SI 1 "= X, X,c,c"))]
9419 %vpcmpistrm\t{%4, %3, %2|%2, %3, %4}
9420 %vpcmpistrm\t{%4, %3, %2|%2, %3, %4}
9421 %vpcmpistri\t{%4, %3, %2|%2, %3, %4}
9422 %vpcmpistri\t{%4, %3, %2|%2, %3, %4}"
9423 [(set_attr "type" "sselog")
9424 (set_attr "prefix_data16" "1")
9425 (set_attr "prefix_extra" "1")
9426 (set_attr "length_immediate" "1")
9427 (set_attr "memory" "none,load,none,load")
9428 (set_attr "prefix" "maybe_vex")
9429 (set_attr "mode" "TI")])
9431 (define_insn "*avx_aesenc"
9432 [(set (match_operand:V2DI 0 "register_operand" "=x")
9433 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
9434 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
9436 "TARGET_AES && TARGET_AVX"
9437 "vaesenc\t{%2, %1, %0|%0, %1, %2}"
9438 [(set_attr "type" "sselog1")
9439 (set_attr "prefix_extra" "1")
9440 (set_attr "prefix" "vex")
9441 (set_attr "mode" "TI")])
9443 (define_insn "aesenc"
9444 [(set (match_operand:V2DI 0 "register_operand" "=x")
9445 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9446 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
9449 "aesenc\t{%2, %0|%0, %2}"
9450 [(set_attr "type" "sselog1")
9451 (set_attr "prefix_extra" "1")
9452 (set_attr "mode" "TI")])
9454 (define_insn "*avx_aesenclast"
9455 [(set (match_operand:V2DI 0 "register_operand" "=x")
9456 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
9457 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
9458 UNSPEC_AESENCLAST))]
9459 "TARGET_AES && TARGET_AVX"
9460 "vaesenclast\t{%2, %1, %0|%0, %1, %2}"
9461 [(set_attr "type" "sselog1")
9462 (set_attr "prefix_extra" "1")
9463 (set_attr "prefix" "vex")
9464 (set_attr "mode" "TI")])
9466 (define_insn "aesenclast"
9467 [(set (match_operand:V2DI 0 "register_operand" "=x")
9468 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9469 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
9470 UNSPEC_AESENCLAST))]
9472 "aesenclast\t{%2, %0|%0, %2}"
9473 [(set_attr "type" "sselog1")
9474 (set_attr "prefix_extra" "1")
9475 (set_attr "mode" "TI")])
9477 (define_insn "*avx_aesdec"
9478 [(set (match_operand:V2DI 0 "register_operand" "=x")
9479 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
9480 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
9482 "TARGET_AES && TARGET_AVX"
9483 "vaesdec\t{%2, %1, %0|%0, %1, %2}"
9484 [(set_attr "type" "sselog1")
9485 (set_attr "prefix_extra" "1")
9486 (set_attr "prefix" "vex")
9487 (set_attr "mode" "TI")])
9489 (define_insn "aesdec"
9490 [(set (match_operand:V2DI 0 "register_operand" "=x")
9491 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9492 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
9495 "aesdec\t{%2, %0|%0, %2}"
9496 [(set_attr "type" "sselog1")
9497 (set_attr "prefix_extra" "1")
9498 (set_attr "mode" "TI")])
9500 (define_insn "*avx_aesdeclast"
9501 [(set (match_operand:V2DI 0 "register_operand" "=x")
9502 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
9503 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
9504 UNSPEC_AESDECLAST))]
9505 "TARGET_AES && TARGET_AVX"
9506 "vaesdeclast\t{%2, %1, %0|%0, %1, %2}"
9507 [(set_attr "type" "sselog1")
9508 (set_attr "prefix_extra" "1")
9509 (set_attr "prefix" "vex")
9510 (set_attr "mode" "TI")])
9512 (define_insn "aesdeclast"
9513 [(set (match_operand:V2DI 0 "register_operand" "=x")
9514 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9515 (match_operand:V2DI 2 "nonimmediate_operand" "xm")]
9516 UNSPEC_AESDECLAST))]
9518 "aesdeclast\t{%2, %0|%0, %2}"
9519 [(set_attr "type" "sselog1")
9520 (set_attr "prefix_extra" "1")
9521 (set_attr "mode" "TI")])
9523 (define_insn "aesimc"
9524 [(set (match_operand:V2DI 0 "register_operand" "=x")
9525 (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm")]
9528 "%vaesimc\t{%1, %0|%0, %1}"
9529 [(set_attr "type" "sselog1")
9530 (set_attr "prefix_extra" "1")
9531 (set_attr "prefix" "maybe_vex")
9532 (set_attr "mode" "TI")])
9534 (define_insn "aeskeygenassist"
9535 [(set (match_operand:V2DI 0 "register_operand" "=x")
9536 (unspec:V2DI [(match_operand:V2DI 1 "nonimmediate_operand" "xm")
9537 (match_operand:SI 2 "const_0_to_255_operand" "n")]
9538 UNSPEC_AESKEYGENASSIST))]
9540 "%vaeskeygenassist\t{%2, %1, %0|%0, %1, %2}"
9541 [(set_attr "type" "sselog1")
9542 (set_attr "prefix_extra" "1")
9543 (set_attr "length_immediate" "1")
9544 (set_attr "prefix" "maybe_vex")
9545 (set_attr "mode" "TI")])
9547 (define_insn "*vpclmulqdq"
9548 [(set (match_operand:V2DI 0 "register_operand" "=x")
9549 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
9550 (match_operand:V2DI 2 "nonimmediate_operand" "xm")
9551 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9553 "TARGET_PCLMUL && TARGET_AVX"
9554 "vpclmulqdq\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9555 [(set_attr "type" "sselog1")
9556 (set_attr "prefix_extra" "1")
9557 (set_attr "length_immediate" "1")
9558 (set_attr "prefix" "vex")
9559 (set_attr "mode" "TI")])
9561 (define_insn "pclmulqdq"
9562 [(set (match_operand:V2DI 0 "register_operand" "=x")
9563 (unspec:V2DI [(match_operand:V2DI 1 "register_operand" "0")
9564 (match_operand:V2DI 2 "nonimmediate_operand" "xm")
9565 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9568 "pclmulqdq\t{%3, %2, %0|%0, %2, %3}"
9569 [(set_attr "type" "sselog1")
9570 (set_attr "prefix_extra" "1")
9571 (set_attr "length_immediate" "1")
9572 (set_attr "mode" "TI")])
9574 (define_expand "avx_vzeroall"
9575 [(match_par_dup 0 [(const_int 0)])]
9578 int nregs = TARGET_64BIT ? 16 : 8;
9581 operands[0] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (nregs + 1));
9583 XVECEXP (operands[0], 0, 0)
9584 = gen_rtx_UNSPEC_VOLATILE (VOIDmode, gen_rtvec (1, const0_rtx),
9587 for (regno = 0; regno < nregs; regno++)
9588 XVECEXP (operands[0], 0, regno + 1)
9589 = gen_rtx_SET (VOIDmode,
9590 gen_rtx_REG (V8SImode, SSE_REGNO (regno)),
9591 CONST0_RTX (V8SImode));
9594 (define_insn "*avx_vzeroall"
9595 [(match_parallel 0 "vzeroall_operation"
9596 [(unspec_volatile [(const_int 0)] UNSPECV_VZEROALL)
9597 (set (match_operand 1 "register_operand" "=x")
9598 (match_operand 2 "const0_operand" "X"))])]
9601 [(set_attr "type" "sse")
9602 (set_attr "modrm" "0")
9603 (set_attr "memory" "none")
9604 (set_attr "prefix" "vex")
9605 (set_attr "mode" "OI")])
9607 ;; vzeroupper clobbers the upper 128bits of AVX registers.
9608 (define_insn "avx_vzeroupper"
9609 [(unspec_volatile [(const_int 0)] UNSPECV_VZEROUPPER)
9610 (clobber (reg:V8SI XMM0_REG))
9611 (clobber (reg:V8SI XMM1_REG))
9612 (clobber (reg:V8SI XMM2_REG))
9613 (clobber (reg:V8SI XMM3_REG))
9614 (clobber (reg:V8SI XMM4_REG))
9615 (clobber (reg:V8SI XMM5_REG))
9616 (clobber (reg:V8SI XMM6_REG))
9617 (clobber (reg:V8SI XMM7_REG))]
9618 "TARGET_AVX && !TARGET_64BIT"
9620 [(set_attr "type" "sse")
9621 (set_attr "modrm" "0")
9622 (set_attr "memory" "none")
9623 (set_attr "prefix" "vex")
9624 (set_attr "mode" "OI")])
9626 (define_insn "avx_vzeroupper_rex64"
9627 [(unspec_volatile [(const_int 0)] UNSPECV_VZEROUPPER)
9628 (clobber (reg:V8SI XMM0_REG))
9629 (clobber (reg:V8SI XMM1_REG))
9630 (clobber (reg:V8SI XMM2_REG))
9631 (clobber (reg:V8SI XMM3_REG))
9632 (clobber (reg:V8SI XMM4_REG))
9633 (clobber (reg:V8SI XMM5_REG))
9634 (clobber (reg:V8SI XMM6_REG))
9635 (clobber (reg:V8SI XMM7_REG))
9636 (clobber (reg:V8SI XMM8_REG))
9637 (clobber (reg:V8SI XMM9_REG))
9638 (clobber (reg:V8SI XMM10_REG))
9639 (clobber (reg:V8SI XMM11_REG))
9640 (clobber (reg:V8SI XMM12_REG))
9641 (clobber (reg:V8SI XMM13_REG))
9642 (clobber (reg:V8SI XMM14_REG))
9643 (clobber (reg:V8SI XMM15_REG))]
9644 "TARGET_AVX && TARGET_64BIT"
9646 [(set_attr "type" "sse")
9647 (set_attr "modrm" "0")
9648 (set_attr "memory" "none")
9649 (set_attr "prefix" "vex")
9650 (set_attr "mode" "OI")])
9652 (define_insn "avx_vpermil<mode>"
9653 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9655 [(match_operand:AVXMODEF2P 1 "register_operand" "xm")
9656 (match_operand:SI 2 "const_0_to_<vpermilbits>_operand" "n")]
9659 "vpermilp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
9660 [(set_attr "type" "sselog")
9661 (set_attr "prefix_extra" "1")
9662 (set_attr "length_immediate" "1")
9663 (set_attr "prefix" "vex")
9664 (set_attr "mode" "<MODE>")])
9666 (define_insn "avx_vpermilvar<mode>3"
9667 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9669 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
9670 (match_operand:<avxpermvecmode> 2 "nonimmediate_operand" "xm")]
9673 "vpermilp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
9674 [(set_attr "type" "sselog")
9675 (set_attr "prefix_extra" "1")
9676 (set_attr "prefix" "vex")
9677 (set_attr "mode" "<MODE>")])
9679 (define_insn "avx_vperm2f128<mode>3"
9680 [(set (match_operand:AVX256MODE2P 0 "register_operand" "=x")
9681 (unspec:AVX256MODE2P
9682 [(match_operand:AVX256MODE2P 1 "register_operand" "x")
9683 (match_operand:AVX256MODE2P 2 "nonimmediate_operand" "xm")
9684 (match_operand:SI 3 "const_0_to_255_operand" "n")]
9685 UNSPEC_VPERMIL2F128))]
9687 "vperm2f128\t{%3, %2, %1, %0|%0, %1, %2, %3}"
9688 [(set_attr "type" "sselog")
9689 (set_attr "prefix_extra" "1")
9690 (set_attr "length_immediate" "1")
9691 (set_attr "prefix" "vex")
9692 (set_attr "mode" "V8SF")])
9694 (define_insn "avx_vbroadcasts<avxmodesuffixf2c><avxmodesuffix>"
9695 [(set (match_operand:AVXMODEF4P 0 "register_operand" "=x")
9696 (vec_concat:AVXMODEF4P
9697 (vec_concat:<avxhalfvecmode>
9698 (match_operand:<avxscalarmode> 1 "memory_operand" "m")
9700 (vec_concat:<avxhalfvecmode>
9704 "vbroadcasts<avxmodesuffixf2c>\t{%1, %0|%0, %1}"
9705 [(set_attr "type" "ssemov")
9706 (set_attr "prefix_extra" "1")
9707 (set_attr "prefix" "vex")
9708 (set_attr "mode" "<avxscalarmode>")])
9710 (define_insn "avx_vbroadcastss256"
9711 [(set (match_operand:V8SF 0 "register_operand" "=x")
9715 (match_operand:SF 1 "memory_operand" "m")
9728 "vbroadcastss\t{%1, %0|%0, %1}"
9729 [(set_attr "type" "ssemov")
9730 (set_attr "prefix_extra" "1")
9731 (set_attr "prefix" "vex")
9732 (set_attr "mode" "SF")])
9734 (define_insn "avx_vbroadcastf128_p<avxmodesuffixf2c>256"
9735 [(set (match_operand:AVX256MODEF2P 0 "register_operand" "=x")
9736 (vec_concat:AVX256MODEF2P
9737 (match_operand:<avxhalfvecmode> 1 "memory_operand" "m")
9740 "vbroadcastf128\t{%1, %0|%0, %1}"
9741 [(set_attr "type" "ssemov")
9742 (set_attr "prefix_extra" "1")
9743 (set_attr "prefix" "vex")
9744 (set_attr "mode" "V4SF")])
9746 (define_expand "avx_vinsertf128<mode>"
9747 [(match_operand:AVX256MODE 0 "register_operand" "")
9748 (match_operand:AVX256MODE 1 "register_operand" "")
9749 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "")
9750 (match_operand:SI 3 "const_0_to_1_operand" "")]
9753 switch (INTVAL (operands[3]))
9756 emit_insn (gen_vec_set_lo_<mode> (operands[0], operands[1],
9760 emit_insn (gen_vec_set_hi_<mode> (operands[0], operands[1],
9769 (define_insn "vec_set_lo_<mode>"
9770 [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
9771 (vec_concat:AVX256MODE4P
9772 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")
9773 (vec_select:<avxhalfvecmode>
9774 (match_operand:AVX256MODE4P 1 "register_operand" "x")
9775 (parallel [(const_int 2) (const_int 3)]))))]
9777 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
9778 [(set_attr "type" "sselog")
9779 (set_attr "prefix_extra" "1")
9780 (set_attr "length_immediate" "1")
9781 (set_attr "prefix" "vex")
9782 (set_attr "mode" "V8SF")])
9784 (define_insn "vec_set_hi_<mode>"
9785 [(set (match_operand:AVX256MODE4P 0 "register_operand" "=x")
9786 (vec_concat:AVX256MODE4P
9787 (vec_select:<avxhalfvecmode>
9788 (match_operand:AVX256MODE4P 1 "register_operand" "x")
9789 (parallel [(const_int 0) (const_int 1)]))
9790 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")))]
9792 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
9793 [(set_attr "type" "sselog")
9794 (set_attr "prefix_extra" "1")
9795 (set_attr "length_immediate" "1")
9796 (set_attr "prefix" "vex")
9797 (set_attr "mode" "V8SF")])
9799 (define_insn "vec_set_lo_<mode>"
9800 [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
9801 (vec_concat:AVX256MODE8P
9802 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")
9803 (vec_select:<avxhalfvecmode>
9804 (match_operand:AVX256MODE8P 1 "register_operand" "x")
9805 (parallel [(const_int 4) (const_int 5)
9806 (const_int 6) (const_int 7)]))))]
9808 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
9809 [(set_attr "type" "sselog")
9810 (set_attr "prefix_extra" "1")
9811 (set_attr "length_immediate" "1")
9812 (set_attr "prefix" "vex")
9813 (set_attr "mode" "V8SF")])
9815 (define_insn "vec_set_hi_<mode>"
9816 [(set (match_operand:AVX256MODE8P 0 "register_operand" "=x")
9817 (vec_concat:AVX256MODE8P
9818 (vec_select:<avxhalfvecmode>
9819 (match_operand:AVX256MODE8P 1 "register_operand" "x")
9820 (parallel [(const_int 0) (const_int 1)
9821 (const_int 2) (const_int 3)]))
9822 (match_operand:<avxhalfvecmode> 2 "nonimmediate_operand" "xm")))]
9824 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
9825 [(set_attr "type" "sselog")
9826 (set_attr "prefix_extra" "1")
9827 (set_attr "length_immediate" "1")
9828 (set_attr "prefix" "vex")
9829 (set_attr "mode" "V8SF")])
9831 (define_insn "vec_set_lo_v16hi"
9832 [(set (match_operand:V16HI 0 "register_operand" "=x")
9834 (match_operand:V8HI 2 "nonimmediate_operand" "xm")
9836 (match_operand:V16HI 1 "register_operand" "x")
9837 (parallel [(const_int 8) (const_int 9)
9838 (const_int 10) (const_int 11)
9839 (const_int 12) (const_int 13)
9840 (const_int 14) (const_int 15)]))))]
9842 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
9843 [(set_attr "type" "sselog")
9844 (set_attr "prefix_extra" "1")
9845 (set_attr "length_immediate" "1")
9846 (set_attr "prefix" "vex")
9847 (set_attr "mode" "V8SF")])
9849 (define_insn "vec_set_hi_v16hi"
9850 [(set (match_operand:V16HI 0 "register_operand" "=x")
9853 (match_operand:V16HI 1 "register_operand" "x")
9854 (parallel [(const_int 0) (const_int 1)
9855 (const_int 2) (const_int 3)
9856 (const_int 4) (const_int 5)
9857 (const_int 6) (const_int 7)]))
9858 (match_operand:V8HI 2 "nonimmediate_operand" "xm")))]
9860 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
9861 [(set_attr "type" "sselog")
9862 (set_attr "prefix_extra" "1")
9863 (set_attr "length_immediate" "1")
9864 (set_attr "prefix" "vex")
9865 (set_attr "mode" "V8SF")])
9867 (define_insn "vec_set_lo_v32qi"
9868 [(set (match_operand:V32QI 0 "register_operand" "=x")
9870 (match_operand:V16QI 2 "nonimmediate_operand" "xm")
9872 (match_operand:V32QI 1 "register_operand" "x")
9873 (parallel [(const_int 16) (const_int 17)
9874 (const_int 18) (const_int 19)
9875 (const_int 20) (const_int 21)
9876 (const_int 22) (const_int 23)
9877 (const_int 24) (const_int 25)
9878 (const_int 26) (const_int 27)
9879 (const_int 28) (const_int 29)
9880 (const_int 30) (const_int 31)]))))]
9882 "vinsertf128\t{$0x0, %2, %1, %0|%0, %1, %2, 0x0}"
9883 [(set_attr "type" "sselog")
9884 (set_attr "prefix_extra" "1")
9885 (set_attr "length_immediate" "1")
9886 (set_attr "prefix" "vex")
9887 (set_attr "mode" "V8SF")])
9889 (define_insn "vec_set_hi_v32qi"
9890 [(set (match_operand:V32QI 0 "register_operand" "=x")
9893 (match_operand:V32QI 1 "register_operand" "x")
9894 (parallel [(const_int 0) (const_int 1)
9895 (const_int 2) (const_int 3)
9896 (const_int 4) (const_int 5)
9897 (const_int 6) (const_int 7)
9898 (const_int 8) (const_int 9)
9899 (const_int 10) (const_int 11)
9900 (const_int 12) (const_int 13)
9901 (const_int 14) (const_int 15)]))
9902 (match_operand:V16QI 2 "nonimmediate_operand" "xm")))]
9904 "vinsertf128\t{$0x1, %2, %1, %0|%0, %1, %2, 0x1}"
9905 [(set_attr "type" "sselog")
9906 (set_attr "prefix_extra" "1")
9907 (set_attr "length_immediate" "1")
9908 (set_attr "prefix" "vex")
9909 (set_attr "mode" "V8SF")])
9911 (define_insn "avx_maskloadp<avxmodesuffixf2c><avxmodesuffix>"
9912 [(set (match_operand:AVXMODEF2P 0 "register_operand" "=x")
9914 [(match_operand:AVXMODEF2P 1 "memory_operand" "m")
9915 (match_operand:AVXMODEF2P 2 "register_operand" "x")
9919 "vmaskmovp<avxmodesuffixf2c>\t{%1, %2, %0|%0, %2, %1}"
9920 [(set_attr "type" "sselog1")
9921 (set_attr "prefix_extra" "1")
9922 (set_attr "prefix" "vex")
9923 (set_attr "mode" "<MODE>")])
9925 (define_insn "avx_maskstorep<avxmodesuffixf2c><avxmodesuffix>"
9926 [(set (match_operand:AVXMODEF2P 0 "memory_operand" "=m")
9928 [(match_operand:AVXMODEF2P 1 "register_operand" "x")
9929 (match_operand:AVXMODEF2P 2 "register_operand" "x")
9933 "vmaskmovp<avxmodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}"
9934 [(set_attr "type" "sselog1")
9935 (set_attr "prefix_extra" "1")
9936 (set_attr "prefix" "vex")
9937 (set_attr "mode" "<MODE>")])
9939 (define_insn "avx_<avxmodesuffixp><avxmodesuffix>_<avxmodesuffixp>"
9940 [(set (match_operand:AVX256MODE2P 0 "register_operand" "=x,x")
9941 (unspec:AVX256MODE2P
9942 [(match_operand:<avxhalfvecmode> 1 "nonimmediate_operand" "0,xm")]
9946 switch (which_alternative)
9951 switch (get_attr_mode (insn))
9954 return "vmovaps\t{%1, %x0|%x0, %1}";
9956 return "vmovapd\t{%1, %x0|%x0, %1}";
9958 return "vmovdqa\t{%1, %x0|%x0, %1}";
9967 [(set_attr "type" "ssemov")
9968 (set_attr "prefix" "vex")
9969 (set_attr "mode" "<avxvecmode>")
9970 (set (attr "length")
9971 (if_then_else (eq_attr "alternative" "0")
9973 (const_string "*")))])
9975 (define_insn "avx_<avxmodesuffixp>_<avxmodesuffixp><avxmodesuffix>"
9976 [(set (match_operand:<avxhalfvecmode> 0 "register_operand" "=x,x")
9977 (unspec:<avxhalfvecmode>
9978 [(match_operand:AVX256MODE2P 1 "nonimmediate_operand" "0,xm")]
9982 switch (which_alternative)
9987 switch (get_attr_mode (insn))
9990 return "vmovaps\t{%x1, %0|%0, %x1}";
9992 return "vmovapd\t{%x1, %0|%0, %x1}";
9994 return "vmovdqa\t{%x1, %0|%0, %x1}";
10001 gcc_unreachable ();
10003 [(set_attr "type" "ssemov")
10004 (set_attr "prefix" "vex")
10005 (set_attr "mode" "<avxvecmode>")
10006 (set (attr "length")
10007 (if_then_else (eq_attr "alternative" "0")
10009 (const_string "*")))])
10011 (define_expand "vec_init<mode>"
10012 [(match_operand:AVX256MODE 0 "register_operand" "")
10013 (match_operand 1 "" "")]
10016 ix86_expand_vector_init (false, operands[0], operands[1]);
10020 (define_insn "*vec_concat<mode>_avx"
10021 [(set (match_operand:AVX256MODE 0 "register_operand" "=x,x")
10022 (vec_concat:AVX256MODE
10023 (match_operand:<avxhalfvecmode> 1 "register_operand" "x,x")
10024 (match_operand:<avxhalfvecmode> 2 "vector_move_operand" "xm,C")))]
10027 switch (which_alternative)
10030 return "vinsertf128\t{$0x1, %2, %t1, %0|%0, %t1, %2, 0x1}";
10032 switch (get_attr_mode (insn))
10035 return "vmovaps\t{%1, %x0|%x0, %1}";
10037 return "vmovapd\t{%1, %x0|%x0, %1}";
10039 return "vmovdqa\t{%1, %x0|%x0, %1}";
10042 gcc_unreachable ();
10045 [(set_attr "type" "sselog,ssemov")
10046 (set_attr "prefix_extra" "1,*")
10047 (set_attr "length_immediate" "1,*")
10048 (set_attr "prefix" "vex")
10049 (set_attr "mode" "<avxvecmode>")])