+2009-08-25 Jan Hubicka <jh@suse.cz>
+
+ * config/i386/bmmintrin.h: Replace by #error.
+
+ Revert:
+ Michael Meissner <michael.meissner@amd.com>
+ Dwarakanath Rajagopal <dwarak.rajagopal@amd.com>
+ Tony Linthicum <tony.linthicum@amd.com>
+
+ * config/i386/i386.h (TARGET_SSE5): New macro for SSE5.
+ (TARGET_ROUND): New macro for the round/ptest instructions which
+ are shared between SSE4.1 and SSE5.
+ (OPTION_MASK_ISA_ROUND): Ditto.
+ (OPTION_ISA_ROUND): Ditto.
+ (TARGET_FUSED_MADD): New macro for -mfused-madd swtich.
+ (TARGET_CPU_CPP_BUILTINS): Add SSE5 support.
+
+ * config/i386/i386.opt (-msse5): New switch for SSE5 support.
+ (-mfused-madd): New switch to give users control over whether the
+ compiler optimizes to use the multiply/add SSE5 instructions.
+
+ * config/i386/i386.c (enum pta_flags): Add PTA_SSE5.
+ (ix86_handle_option): Turn off 3dnow if -msse5.
+ (override_options): Add SSE5 support.
+ (print_operand): %Y prints comparison codes for SSE5 com/pcom
+ instructions.
+ (ix86_expand_sse_movcc): Add SSE5 support.
+ (ix86_expand_sse5_unpack): New function to use pperm to unpack a
+ vector type to the next largest size.
+ (ix86_expand_sse5_pack): New function to use pperm to pack a
+ vector type to the next smallest size.
+ (IX86_BUILTIN_FMADDSS): New for SSE5 intrinsic.
+ (IX86_BUILTIN_FMADDSD): Ditto.
+ (IX86_BUILTIN_FMADDPS): Ditto.
+ (IX86_BUILTIN_FMADDPD): Ditto.
+ (IX86_BUILTIN_FMSUBSS): Ditto.
+ (IX86_BUILTIN_FMSUBSD): Ditto.
+ (IX86_BUILTIN_FMSUBPS): Ditto.
+ (IX86_BUILTIN_FMSUBPD): Ditto.
+ (IX86_BUILTIN_FNMADDSS): Ditto.
+ (IX86_BUILTIN_FNMADDSD): Ditto.
+ (IX86_BUILTIN_FNMADDPS): Ditto.
+ (IX86_BUILTIN_FNMADDPD): Ditto.
+ (IX86_BUILTIN_FNMSUBSS): Ditto.
+ (IX86_BUILTIN_FNMSUBSD): Ditto.
+ (IX86_BUILTIN_FNMSUBPS): Ditto.
+ (IX86_BUILTIN_FNMSUBPD): Ditto.
+ (IX86_BUILTIN_PCMOV_V2DI): Ditto.
+ (IX86_BUILTIN_PCMOV_V4SI): Ditto.
+ (IX86_BUILTIN_PCMOV_V8HI): Ditto.
+ (IX86_BUILTIN_PCMOV_V16QI): Ditto.
+ (IX86_BUILTIN_PCMOV_V4SF): Ditto.
+ (IX86_BUILTIN_PCMOV_V2DF): Ditto.
+ (IX86_BUILTIN_PPERM): Ditto.
+ (IX86_BUILTIN_PERMPS): Ditto.
+ (IX86_BUILTIN_PERMPD): Ditto.
+ (IX86_BUILTIN_PMACSSWW): Ditto.
+ (IX86_BUILTIN_PMACSWW): Ditto.
+ (IX86_BUILTIN_PMACSSWD): Ditto.
+ (IX86_BUILTIN_PMACSWD): Ditto.
+ (IX86_BUILTIN_PMACSSDD): Ditto.
+ (IX86_BUILTIN_PMACSDD): Ditto.
+ (IX86_BUILTIN_PMACSSDQL): Ditto.
+ (IX86_BUILTIN_PMACSSDQH): Ditto.
+ (IX86_BUILTIN_PMACSDQL): Ditto.
+ (IX86_BUILTIN_PMACSDQH): Ditto.
+ (IX86_BUILTIN_PMADCSSWD): Ditto.
+ (IX86_BUILTIN_PMADCSWD): Ditto.
+ (IX86_BUILTIN_PHADDBW): Ditto.
+ (IX86_BUILTIN_PHADDBD): Ditto.
+ (IX86_BUILTIN_PHADDBQ): Ditto.
+ (IX86_BUILTIN_PHADDWD): Ditto.
+ (IX86_BUILTIN_PHADDWQ): Ditto.
+ (IX86_BUILTIN_PHADDDQ): Ditto.
+ (IX86_BUILTIN_PHADDUBW): Ditto.
+ (IX86_BUILTIN_PHADDUBD): Ditto.
+ (IX86_BUILTIN_PHADDUBQ): Ditto.
+ (IX86_BUILTIN_PHADDUWD): Ditto.
+ (IX86_BUILTIN_PHADDUWQ): Ditto.
+ (IX86_BUILTIN_PHADDUDQ): Ditto.
+ (IX86_BUILTIN_PHSUBBW): Ditto.
+ (IX86_BUILTIN_PHSUBWD): Ditto.
+ (IX86_BUILTIN_PHSUBDQ): Ditto.
+ (IX86_BUILTIN_PROTB): Ditto.
+ (IX86_BUILTIN_PROTW): Ditto.
+ (IX86_BUILTIN_PROTD): Ditto.
+ (IX86_BUILTIN_PROTQ): Ditto.
+ (IX86_BUILTIN_PROTB_IMM): Ditto.
+ (IX86_BUILTIN_PROTW_IMM): Ditto.
+ (IX86_BUILTIN_PROTD_IMM): Ditto.
+ (IX86_BUILTIN_PROTQ_IMM): Ditto.
+ (IX86_BUILTIN_PSHLB): Ditto.
+ (IX86_BUILTIN_PSHLW): Ditto.
+ (IX86_BUILTIN_PSHLD): Ditto.
+ (IX86_BUILTIN_PSHLQ): Ditto.
+ (IX86_BUILTIN_PSHAB): Ditto.
+ (IX86_BUILTIN_PSHAW): Ditto.
+ (IX86_BUILTIN_PSHAD): Ditto.
+ (IX86_BUILTIN_PSHAQ): Ditto.
+ (IX86_BUILTIN_FRCZSS): Ditto.
+ (IX86_BUILTIN_FRCZSD): Ditto.
+ (IX86_BUILTIN_FRCZPS): Ditto.
+ (IX86_BUILTIN_FRCZPD): Ditto.
+ (IX86_BUILTIN_CVTPH2PS): Ditto.
+ (IX86_BUILTIN_CVTPS2PH): Ditto.
+ (IX86_BUILTIN_COMEQSS): Ditto.
+ (IX86_BUILTIN_COMNESS): Ditto.
+ (IX86_BUILTIN_COMLTSS): Ditto.
+ (IX86_BUILTIN_COMLESS): Ditto.
+ (IX86_BUILTIN_COMGTSS): Ditto.
+ (IX86_BUILTIN_COMGESS): Ditto.
+ (IX86_BUILTIN_COMUEQSS): Ditto.
+ (IX86_BUILTIN_COMUNESS): Ditto.
+ (IX86_BUILTIN_COMULTSS): Ditto.
+ (IX86_BUILTIN_COMULESS): Ditto.
+ (IX86_BUILTIN_COMUGTSS): Ditto.
+ (IX86_BUILTIN_COMUGESS): Ditto.
+ (IX86_BUILTIN_COMORDSS): Ditto.
+ (IX86_BUILTIN_COMUNORDSS): Ditto.
+ (IX86_BUILTIN_COMFALSESS): Ditto.
+ (IX86_BUILTIN_COMTRUESS): Ditto.
+ (IX86_BUILTIN_COMEQSD): Ditto.
+ (IX86_BUILTIN_COMNESD): Ditto.
+ (IX86_BUILTIN_COMLTSD): Ditto.
+ (IX86_BUILTIN_COMLESD): Ditto.
+ (IX86_BUILTIN_COMGTSD): Ditto.
+ (IX86_BUILTIN_COMGESD): Ditto.
+ (IX86_BUILTIN_COMUEQSD): Ditto.
+ (IX86_BUILTIN_COMUNESD): Ditto.
+ (IX86_BUILTIN_COMULTSD): Ditto.
+ (IX86_BUILTIN_COMULESD): Ditto.
+ (IX86_BUILTIN_COMUGTSD): Ditto.
+ (IX86_BUILTIN_COMUGESD): Ditto.
+ (IX86_BUILTIN_COMORDSD): Ditto.
+ (IX86_BUILTIN_COMUNORDSD): Ditto.
+ (IX86_BUILTIN_COMFALSESD): Ditto.
+ (IX86_BUILTIN_COMTRUESD): Ditto.
+ (IX86_BUILTIN_COMEQPS): Ditto.
+ (IX86_BUILTIN_COMNEPS): Ditto.
+ (IX86_BUILTIN_COMLTPS): Ditto.
+ (IX86_BUILTIN_COMLEPS): Ditto.
+ (IX86_BUILTIN_COMGTPS): Ditto.
+ (IX86_BUILTIN_COMGEPS): Ditto.
+ (IX86_BUILTIN_COMUEQPS): Ditto.
+ (IX86_BUILTIN_COMUNEPS): Ditto.
+ (IX86_BUILTIN_COMULTPS): Ditto.
+ (IX86_BUILTIN_COMULEPS): Ditto.
+ (IX86_BUILTIN_COMUGTPS): Ditto.
+ (IX86_BUILTIN_COMUGEPS): Ditto.
+ (IX86_BUILTIN_COMORDPS): Ditto.
+ (IX86_BUILTIN_COMUNORDPS): Ditto.
+ (IX86_BUILTIN_COMFALSEPS): Ditto.
+ (IX86_BUILTIN_COMTRUEPS): Ditto.
+ (IX86_BUILTIN_COMEQPD): Ditto.
+ (IX86_BUILTIN_COMNEPD): Ditto.
+ (IX86_BUILTIN_COMLTPD): Ditto.
+ (IX86_BUILTIN_COMLEPD): Ditto.
+ (IX86_BUILTIN_COMGTPD): Ditto.
+ (IX86_BUILTIN_COMGEPD): Ditto.
+ (IX86_BUILTIN_COMUEQPD): Ditto.
+ (IX86_BUILTIN_COMUNEPD): Ditto.
+ (IX86_BUILTIN_COMULTPD): Ditto.
+ (IX86_BUILTIN_COMULEPD): Ditto.
+ (IX86_BUILTIN_COMUGTPD): Ditto.
+ (IX86_BUILTIN_COMUGEPD): Ditto.
+ (IX86_BUILTIN_COMORDPD): Ditto.
+ (IX86_BUILTIN_COMUNORDPD): Ditto.
+ (IX86_BUILTIN_COMFALSEPD): Ditto.
+ (IX86_BUILTIN_COMTRUEPD): Ditto.
+ (IX86_BUILTIN_PCOMEQUB): Ditto.
+ (IX86_BUILTIN_PCOMNEUB): Ditto.
+ (IX86_BUILTIN_PCOMLTUB): Ditto.
+ (IX86_BUILTIN_PCOMLEUB): Ditto.
+ (IX86_BUILTIN_PCOMGTUB): Ditto.
+ (IX86_BUILTIN_PCOMGEUB): Ditto.
+ (IX86_BUILTIN_PCOMFALSEUB): Ditto.
+ (IX86_BUILTIN_PCOMTRUEUB): Ditto.
+ (IX86_BUILTIN_PCOMEQUW): Ditto.
+ (IX86_BUILTIN_PCOMNEUW): Ditto.
+ (IX86_BUILTIN_PCOMLTUW): Ditto.
+ (IX86_BUILTIN_PCOMLEUW): Ditto.
+ (IX86_BUILTIN_PCOMGTUW): Ditto.
+ (IX86_BUILTIN_PCOMGEUW): Ditto.
+ (IX86_BUILTIN_PCOMFALSEUW): Ditto.
+ (IX86_BUILTIN_PCOMTRUEUW): Ditto.
+ (IX86_BUILTIN_PCOMEQUD): Ditto.
+ (IX86_BUILTIN_PCOMNEUD): Ditto.
+ (IX86_BUILTIN_PCOMLTUD): Ditto.
+ (IX86_BUILTIN_PCOMLEUD): Ditto.
+ (IX86_BUILTIN_PCOMGTUD): Ditto.
+ (IX86_BUILTIN_PCOMGEUD): Ditto.
+ (IX86_BUILTIN_PCOMFALSEUD): Ditto.
+ (IX86_BUILTIN_PCOMTRUEUD): Ditto.
+ (IX86_BUILTIN_PCOMEQUQ): Ditto.
+ (IX86_BUILTIN_PCOMNEUQ): Ditto.
+ (IX86_BUILTIN_PCOMLTUQ): Ditto.
+ (IX86_BUILTIN_PCOMLEUQ): Ditto.
+ (IX86_BUILTIN_PCOMGTUQ): Ditto.
+ (IX86_BUILTIN_PCOMGEUQ): Ditto.
+ (IX86_BUILTIN_PCOMFALSEUQ): Ditto.
+ (IX86_BUILTIN_PCOMTRUEUQ): Ditto.
+ (IX86_BUILTIN_PCOMEQB): Ditto.
+ (IX86_BUILTIN_PCOMNEB): Ditto.
+ (IX86_BUILTIN_PCOMLTB): Ditto.
+ (IX86_BUILTIN_PCOMLEB): Ditto.
+ (IX86_BUILTIN_PCOMGTB): Ditto.
+ (IX86_BUILTIN_PCOMGEB): Ditto.
+ (IX86_BUILTIN_PCOMFALSEB): Ditto.
+ (IX86_BUILTIN_PCOMTRUEB): Ditto.
+ (IX86_BUILTIN_PCOMEQW): Ditto.
+ (IX86_BUILTIN_PCOMNEW): Ditto.
+ (IX86_BUILTIN_PCOMLTW): Ditto.
+ (IX86_BUILTIN_PCOMLEW): Ditto.
+ (IX86_BUILTIN_PCOMGTW): Ditto.
+ (IX86_BUILTIN_PCOMGEW): Ditto.
+ (IX86_BUILTIN_PCOMFALSEW): Ditto.
+ (IX86_BUILTIN_PCOMTRUEW): Ditto.
+ (IX86_BUILTIN_PCOMEQD): Ditto.
+ (IX86_BUILTIN_PCOMNED): Ditto.
+ (IX86_BUILTIN_PCOMLTD): Ditto.
+ (IX86_BUILTIN_PCOMLED): Ditto.
+ (IX86_BUILTIN_PCOMGTD): Ditto.
+ (IX86_BUILTIN_PCOMGED): Ditto.
+ (IX86_BUILTIN_PCOMFALSED): Ditto.
+ (IX86_BUILTIN_PCOMTRUED): Ditto.
+ (IX86_BUILTIN_PCOMEQQ): Ditto.
+ (IX86_BUILTIN_PCOMNEQ): Ditto.
+ (IX86_BUILTIN_PCOMLTQ): Ditto.
+ (IX86_BUILTIN_PCOMLEQ): Ditto.
+ (IX86_BUILTIN_PCOMGTQ): Ditto.
+ (IX86_BUILTIN_PCOMGEQ): Ditto.
+ (IX86_BUILTIN_PCOMFALSEQ): Ditto.
+ (IX86_BUILTIN_PCOMTRUEQ): Ditto.
+ (enum multi_arg_type): New enum for describing the various SSE5
+ intrinsic argument types.
+ (bdesc_multi_arg): New table for SSE5 intrinsics.
+ (ix86_init_mmx_sse_builtins): Add SSE5 intrinsic support.
+ (ix86_expand_multi_arg_builtin): New function for creating SSE5
+ intrinsics.
+ (ix86_expand_builtin): Add SSE5 intrinsic support.
+ (ix86_sse5_valid_op_p): New function to validate SSE5 3 and 4
+ operand instructions.
+ (ix86_expand_sse5_multiple_memory): New function to split the
+ second memory reference from SSE5 instructions.
+ (type_has_variadic_args_p): Delete in favor of stdarg_p.
+ (ix86_return_pops_args): Use stdarg_p to determine if the function
+ has variable arguments.
+ (ix86_setup_incoming_varargs): Ditto.
+ (x86_this_parameter): Ditto.
+
+ * config/i386/i386-protos.h (ix86_expand_sse5_unpack): Add
+ declaration.
+ (ix86_expand_sse5_pack): Ditto.
+ (ix86_sse5_valid_op_p): Ditto.
+ (ix86_expand_sse5_multiple_memory): Ditto.
+
+ * config/i386/i386.md (UNSPEC_SSE5_INTRINSIC): Add new UNSPEC
+ constant for SSE5 support.
+ (UNSPEC_SSE5_UNSIGNED_CMP): Ditto.
+ (UNSPEC_SSE5_TRUEFALSE): Ditto.
+ (UNSPEC_SSE5_PERMUTE): Ditto.
+ (UNSPEC_SSE5_ASHIFT): Ditto.
+ (UNSPEC_SSE5_LSHIFT): Ditto.
+ (UNSPEC_FRCZ): Ditto.
+ (UNSPEC_CVTPH2PS): Ditto.
+ (UNSPEC_CVTPS2PH): Ditto.
+ (PCOM_FALSE): Add new constant for true/false SSE5 comparisons.
+ (PCOM_TRUE): Ditto.
+ (COM_FALSE_S): Ditto.
+ (COM_FALSE_P): Ditto.
+ (COM_TRUE_S): Ditto.
+ (COM_TRUE_P): Ditto.
+ (type attribute): Add ssemuladd, sseiadd1, ssecvt1, sse4arg types.
+ (unit attribute): Add support for ssemuladd, ssecvt1, sseiadd1 sse4arg
+ types.
+ (memory attribute): Ditto.
+ (sse4_1_round<mode>2): Use TARGET_ROUND instead of TARGET_SSE4_1.
+ Use SSE4_1_ROUND_* constants instead of hard coded numbers.
+ (rint<mode>2): Use TARGET_ROUND instead of TARGET_SSE4_1.
+ (floor<mode>2): Ditto.
+ (ceil<mode>2): Ditto.
+ (btrunc<mode>2): Ditto.
+ (nearbyintdf2): Ditto.
+ (nearbyintsf2): Ditto.
+ (sse_setccsf): Disable if SSE5.
+ (sse_setccdf): Ditto.
+ (sse5_setcc<mode>): New support for SSE5 conditional move.
+ (sse5_pcmov_<mode>): Ditto.
+
+ * config/i386/sse.md (SSEMODE1248): New mode iterator for SSE5.
+ (SSEMODEF4): Ditto.
+ (SSEMODEF2P): Ditto.
+ (ssemodesuffixf4): New mode attribute for SSE5.
+ (ssemodesuffixf2s): Ditto.
+ (ssemodesuffixf2c): Ditto.
+ (sserotatemax): Ditto.
+ (ssescalarmode): Ditto.
+ (sse_maskcmpv4sf3): Disable if SSE5.
+ (sse_maskcmpv2df3): Ditto.
+ (sse_vmmaskcmpv4sf3): Ditto.
+ (sse5_fmadd<mode>4): Add SSE5 floating point multiply/add
+ instructions.
+ (sse5_vmfmadd<mode>4): Ditto.
+ (sse5_fmsub<mode>4): Ditto.
+ (sse5_vmfmsub<mode>4): Ditto.
+ (sse5_fnmadd<mode>4): Ditto.
+ (sse5_vmfnmadd<mode>4): Ditto.
+ (sse5_fnmsub<mode>4): Ditto.
+ (sse5_vmfnmsub<mode>4): Ditto.
+ (sse5i_fmadd<mode>4): Ditto.
+ (sse5i_fmsub<mode>4): Ditto.
+ (sse5i_fnmadd<mode>4): Ditto.
+ (sse5i_fnmsub<mode>4): Ditto.
+ (sse5i_vmfmadd<mode>4): Ditto.
+ (sse5i_vmfmsub<mode>4): Ditto.
+ (sse5i_vmfnmadd<mode>4): Ditto.
+ (sse5i_vmfnmsub<mode>4): Ditto.
+ (mulv16qi3): Add SSE5 support.
+ (mulv4si3): Ditto.
+ (sse5_mulv4si3): New insn for 32-bit multiply support on SSE5.
+ (sse2_mulv4si3): Disable if SSE5.
+ (sse4_1_roundpd): Use TARGET_ROUND instead of TARGET_SSE4_1.
+ (sse4_1_roundps): Ditto.
+ (sse4_1_roundsd): Ditto.
+ (sse4_1_roundss): Ditto.
+ (sse_maskcmpv4sf3): Disable if SSE5 so the SSE5 instruction will
+ be generated.
+ (sse_maskcmpsf3): Ditto.
+ (sse_vmmaskcmpv4sf3): Ditto.
+ (sse2_maskcmpv2df3): Ditto.
+ (sse2_maskcmpdf3): Ditto.
+ (sse2_vmmaskcmpv2df3): Ditto.
+ (sse2_eq<mode>3): Ditto.
+ (sse2_gt<mode>3): Ditto.
+ (sse5_pcmov_<mode>): Add SSE5 support.
+ (vec_unpacku_hi_v16qi): Ditto.
+ (vec_unpacks_hi_v16qi): Ditto.
+ (vec_unpacku_lo_v16qi): Ditto.
+ (vec_unpacks_lo_v16qi): Ditto.
+ (vec_unpacku_hi_v8hi): Ditto.
+ (vec_unpacks_hi_v8hi): Ditto.
+ (vec_unpacku_lo_v8hi): Ditto.
+ (vec_unpacks_lo_v8hi): Ditto.
+ (vec_unpacku_hi_v4si): Ditto.
+ (vec_unpacks_hi_v4si): Ditto.
+ (vec_unpacku_lo_v4si): Ditto.
+ (vec_unpacks_lo_v4si): Ditto.
+ (sse5_pmacsww): New SSE5 intrinsic insn.
+ (sse5_pmacssww): Ditto.
+ (sse5_pmacsdd): Ditto.
+ (sse5_pmacssdd): Ditto.
+ (sse5_pmacssdql): Ditto.
+ (sse5_pmacssdqh): Ditto.
+ (sse5_pmacsdqh): Ditto.
+ (sse5_pmacsswd): Ditto.
+ (sse5_pmacswd): Ditto.
+ (sse5_pmadcsswd): Ditto.
+ (sse5_pmadcswd): Ditto.
+ (sse5_pcmov_<move>): Conditional move support on SSE5.
+ (sse5_phaddbw): New SSE5 intrinsic insn.
+ (sse5_phaddbd): Ditto.
+ (sse5_phaddbq): Ditto.
+ (sse5_phaddwd): Ditto.
+ (sse5_phaddwq): Ditto.
+ (sse5_phadddq): Ditto.
+ (sse5_phaddubw): Ditto.
+ (sse5_phaddubd): Ditto.
+ (sse5_phaddubq): Ditto.
+ (sse5_phadduwd): Ditto.
+ (sse5_phadduwq): Ditto.
+ (sse5_phaddudq): Ditto.
+ (sse5_phsubbw): Ditto.
+ (sse5_phsubwd): Ditto.
+ (sse5_phsubdq): Ditto.
+ (sse5_pperm): Ditto.
+ (sse5_pperm_sign_v16qi_v8hi): New insns for pack/unpack with SSE5.
+ (sse5_pperm_zero_v16qi_v8hi): Ditto.
+ (sse5_pperm_sign_v8hi_v4si): Ditto.
+ (sse5_pperm_zero_v8hi_v4si): Ditto.
+ (sse5_pperm_sign_v4si_v2di): Ditto.
+ (sse5_pperm_sign_v4si_v2di): Ditto.
+ (sse5_pperm_pack_v2di_v4si): Ditto.
+ (sse5_pperm_pack_v4si_v8hi): Ditto.
+ (sse5_pperm_pack_v8hi_v16qi): Ditto.
+ (sse5_perm<mode>): New SSE5 intrinsic insn.
+ (rotl<mode>3): Ditto.
+ (sse5_rotl<mode>3): Ditto.
+ (sse5_ashl<mode>3): Ditto.
+ (sse5_lshl<mode>3): Ditto.
+ (sse5_frcz<mode>2): Ditto.
+ (sse5s_frcz<mode>2): Ditto.
+ (sse5_cvtph2ps): Ditto.
+ (sse5_cvtps2ph): Ditto.
+ (sse5_vmmaskcmp<mode>3): Ditto.
+ (sse5_com_tf<mode>3): Ditto.
+ (sse5_maskcmp<mode>3): Ditto.
+ (sse5_maskcmp_uns<mode>3): Ditto.
+ (sse5_maskcmp_uns2<mode>3): Ditto.
+ (sse5_pcom_tf<mode>3): Ditto.
+
+ * config/i386/predicates.md (sse5_comparison_float_operator): New predicate to match the
+ comparison operators supported by the SSE5 com instruction.
+ (ix86_comparison_int_operator): New predicate to match just the
+ signed int comparisons.
+ (ix86_comparison_uns_operator): New predicate to match just the
+ unsigned int comparisons.
+
+ * doc/invoke.texi (-msse5): Add documentation.
+ (-mfused-madd): Ditto.
+
+ * doc/extend.texi (x86 intrinsics): Document new SSE5 intrinsics.
+
+ * config.gcc (i[34567]86-*-*): Include bmmintrin.h and
+ mmintrin-common.h.
+ (x86_64-*-*): Ditto.
+
+ * config/i386/cpuid.h (bit_SSE5): Define SSE5 bit.
+
+ * config/i386/bmmintrin.h: New file, provide common x86 compiler
+ intrinisics for SSE5.
+
+ * config/i386/smmintrin.h: Move instructions shared with SSE5 to
+ mmintrin-common.h.
+
+ * config/i386/mmintrin-common.h: New file, to contain common
+ instructions between SSE4.1 and SSE5.
+
+ * config/i386/netware.c (gen_stdcall_or_fastcall_decoration): Use
+ FOREACH_FUNCTION_ARGS to iterate over the argument list.
+ (gen_regparm_prefix): Ditto.
+
+ * config/i386/winnt.c (gen_stdcall_or_fastcall_suffix): Use
+ FOREACH_FUNCTION_ARGS to iterate over the argument list. Use
+ prototype_p to determine if a function is prototyped.
+
2009-08-25 Ville Voutilainen <ville.voutilainen@gmail.com>
* c-common.c (c_common_reswords) add the alignof keyword,
#ifndef _BMMINTRIN_H_INCLUDED
#define _BMMINTRIN_H_INCLUDED
-#ifndef __SSE5__
-# error "SSE5 instruction set not enabled"
-#else
-
-/* We need definitions from the SSE4A, SSE3, SSE2 and SSE header files. */
-#include <ammintrin.h>
-#include <mmintrin-common.h>
-
-/* Floating point multiply/add type instructions */
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_macc_ps(__m128 __A, __m128 __B, __m128 __C)
-{
- return (__m128) __builtin_ia32_fmaddps ((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_macc_pd(__m128d __A, __m128d __B, __m128d __C)
-{
- return (__m128d) __builtin_ia32_fmaddpd ((__v2df)__A, (__v2df)__B, (__v2df)__C);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_macc_ss(__m128 __A, __m128 __B, __m128 __C)
-{
- return (__m128) __builtin_ia32_fmaddss ((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_macc_sd(__m128d __A, __m128d __B, __m128d __C)
-{
- return (__m128d) __builtin_ia32_fmaddsd ((__v2df)__A, (__v2df)__B, (__v2df)__C);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_msub_ps(__m128 __A, __m128 __B, __m128 __C)
-{
- return (__m128) __builtin_ia32_fmsubps ((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_msub_pd(__m128d __A, __m128d __B, __m128d __C)
-{
- return (__m128d) __builtin_ia32_fmsubpd ((__v2df)__A, (__v2df)__B, (__v2df)__C);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_msub_ss(__m128 __A, __m128 __B, __m128 __C)
-{
- return (__m128) __builtin_ia32_fmsubss ((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_msub_sd(__m128d __A, __m128d __B, __m128d __C)
-{
- return (__m128d) __builtin_ia32_fmsubsd ((__v2df)__A, (__v2df)__B, (__v2df)__C);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_nmacc_ps(__m128 __A, __m128 __B, __m128 __C)
-{
- return (__m128) __builtin_ia32_fnmaddps ((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_nmacc_pd(__m128d __A, __m128d __B, __m128d __C)
-{
- return (__m128d) __builtin_ia32_fnmaddpd ((__v2df)__A, (__v2df)__B, (__v2df)__C);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_nmacc_ss(__m128 __A, __m128 __B, __m128 __C)
-{
- return (__m128) __builtin_ia32_fnmaddss ((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_nmacc_sd(__m128d __A, __m128d __B, __m128d __C)
-{
- return (__m128d) __builtin_ia32_fnmaddsd ((__v2df)__A, (__v2df)__B, (__v2df)__C);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_nmsub_ps(__m128 __A, __m128 __B, __m128 __C)
-{
- return (__m128) __builtin_ia32_fnmsubps ((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_nmsub_pd(__m128d __A, __m128d __B, __m128d __C)
-{
- return (__m128d) __builtin_ia32_fnmsubpd ((__v2df)__A, (__v2df)__B, (__v2df)__C);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_nmsub_ss(__m128 __A, __m128 __B, __m128 __C)
-{
- return (__m128) __builtin_ia32_fnmsubss ((__v4sf)__A, (__v4sf)__B, (__v4sf)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_nmsub_sd(__m128d __A, __m128d __B, __m128d __C)
-{
- return (__m128d) __builtin_ia32_fnmsubsd ((__v2df)__A, (__v2df)__B, (__v2df)__C);
-}
-
-/* Integer multiply/add intructions. */
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_maccs_epi16(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacssww ((__v8hi)__A,(__v8hi)__B, (__v8hi)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_macc_epi16(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacsww ((__v8hi)__A, (__v8hi)__B, (__v8hi)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_maccsd_epi16(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacsswd ((__v8hi)__A, (__v8hi)__B, (__v4si)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_maccd_epi16(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacswd ((__v8hi)__A, (__v8hi)__B, (__v4si)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_maccs_epi32(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacssdd ((__v4si)__A, (__v4si)__B, (__v4si)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_macc_epi32(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacsdd ((__v4si)__A, (__v4si)__B, (__v4si)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_maccslo_epi32(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacssdql ((__v4si)__A, (__v4si)__B, (__v2di)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_macclo_epi32(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacsdql ((__v4si)__A, (__v4si)__B, (__v2di)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_maccshi_epi32(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacssdqh ((__v4si)__A, (__v4si)__B, (__v2di)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_macchi_epi32(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmacsdqh ((__v4si)__A, (__v4si)__B, (__v2di)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_maddsd_epi16(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmadcsswd ((__v8hi)__A,(__v8hi)__B,(__v4si)__C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_maddd_epi16(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pmadcswd ((__v8hi)__A,(__v8hi)__B,(__v4si)__C);
-}
-
-/* Packed Integer Horizontal Add and Subtract */
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddw_epi8(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddbw ((__v16qi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddd_epi8(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddbd ((__v16qi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddq_epi8(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddbq ((__v16qi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddd_epi16(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddwd ((__v8hi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddq_epi16(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddwq ((__v8hi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddq_epi32(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phadddq ((__v4si)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddw_epu8(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddubw ((__v16qi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddd_epu8(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddubd ((__v16qi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddq_epu8(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddubq ((__v16qi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddd_epu16(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phadduwd ((__v8hi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddq_epu16(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phadduwq ((__v8hi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_haddq_epu32(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phaddudq ((__v4si)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_hsubw_epi8(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phsubbw ((__v16qi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_hsubd_epi16(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phsubwd ((__v8hi)__A);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_hsubq_epi32(__m128i __A)
-{
- return (__m128i) __builtin_ia32_phsubdq ((__v4si)__A);
-}
-
-/* Vector conditional move and permute */
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_cmov_si128(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pcmov (__A, __B, __C);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_perm_epi8(__m128i __A, __m128i __B, __m128i __C)
-{
- return (__m128i) __builtin_ia32_pperm ((__v16qi)__A, (__v16qi)__B, (__v16qi)__C);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_perm_ps(__m128 __A, __m128 __B, __m128i __C)
-{
- return (__m128) __builtin_ia32_permps ((__m128)__A, (__m128)__B, (__v16qi)__C);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_perm_pd(__m128d __A, __m128d __B, __m128i __C)
-{
- return (__m128d) __builtin_ia32_permpd ((__m128d)__A, (__m128d)__B, (__v16qi)__C);
-}
-
-/* Packed Integer Rotates and Shifts */
-
-/* Rotates - Non-Immediate form */
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_rot_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_protb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_rot_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_protw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_rot_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_protd ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_rot_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_protq ((__v2di)__A, (__v2di)__B);
-}
-
-
-/* Rotates - Immediate form */
-#ifdef __OPTIMIZE__
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_roti_epi8(__m128i __A, const int __B)
-{
- return (__m128i) __builtin_ia32_protbi ((__v16qi)__A, __B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_roti_epi16(__m128i __A, const int __B)
-{
- return (__m128i) __builtin_ia32_protwi ((__v8hi)__A, __B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_roti_epi32(__m128i __A, const int __B)
-{
- return (__m128i) __builtin_ia32_protdi ((__v4si)__A, __B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_roti_epi64(__m128i __A, const int __B)
-{
- return (__m128i) __builtin_ia32_protqi ((__v2di)__A, __B);
-}
-#else
-#define _mm_roti_epi8(A, N) \
- ((__m128i) __builtin_ia32_protbi ((__v16qi)(__m128i)(A), (int)(N)))
-#define _mm_roti_epi16(A, N) \
- ((__m128i) __builtin_ia32_protwi ((__v8hi)(__m128i)(A), (int)(N)))
-#define _mm_roti_epi32(A, N) \
- ((__m128i) __builtin_ia32_protdi ((__v4si)(__m128i)(A), (int)(N)))
-#define _mm_roti_epi64(A, N) \
- ((__m128i) __builtin_ia32_protqi ((__v2di)(__m128i)(A), (int)(N)))
-#endif
-
-/* pshl */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_shl_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pshlb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_shl_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pshlw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_shl_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pshld ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_shl_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pshlq ((__v2di)__A, (__v2di)__B);
-}
-
-/* psha */
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_sha_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pshab ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_sha_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pshaw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_sha_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pshad ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_sha_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pshaq ((__v2di)__A, (__v2di)__B);
-}
-
-/* Compare and Predicate Generation */
-
-/* com (floating point, packed single) */
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comeqps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comltps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comleps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comunord_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comunordps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comuneqps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnlt_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comunltps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnle_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comunleps ((__v4sf)__A, (__v4sf)__B);
-}
-
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comord_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comordps ((__v4sf)__A, (__v4sf)__B);
-}
-
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comueq_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comueqps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnge_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comungeps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comngt_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comungtps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comfalseps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comoneq_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comneqps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comgeps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comgtps ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_ps(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comtrueps ((__v4sf)__A, (__v4sf)__B);
-}
-
-/* com (floating point, packed double) */
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comeqpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comltpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comlepd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comunord_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comunordpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comuneqpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnlt_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comunltpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnle_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comunlepd ((__v2df)__A, (__v2df)__B);
-}
-
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comord_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comordpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comueq_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comueqpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnge_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comungepd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comngt_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comungtpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comfalsepd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comoneq_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comneqpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comgepd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comgtpd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_pd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comtruepd ((__v2df)__A, (__v2df)__B);
-}
-
-/* com (floating point, scalar single) */
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comeqss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comltss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comless ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comunord_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comunordss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comuneqss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnlt_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comunltss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnle_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comunless ((__v4sf)__A, (__v4sf)__B);
-}
-
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comord_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comordss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comueq_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comueqss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnge_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comungess ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comngt_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comungtss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comfalsess ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comoneq_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comneqss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comgess ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comgtss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_ss(__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_comtruess ((__v4sf)__A, (__v4sf)__B);
-}
-
-/* com (floating point, scalar double) */
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comeqsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comltsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comlesd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comunord_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comunordsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comuneqsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnlt_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comunltsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnle_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comunlesd ((__v2df)__A, (__v2df)__B);
-}
-
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comord_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comordsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comueq_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comueqsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comnge_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comungesd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comngt_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comungtsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comfalsesd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comoneq_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comneqsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comgesd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comgtsd ((__v2df)__A, (__v2df)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_sd(__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_comtruesd ((__v2df)__A, (__v2df)__B);
-}
-
-
-/*pcom (integer, unsinged bytes) */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_epu8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomltub ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_epu8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomleub ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_epu8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgtub ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_epu8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgeub ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_epu8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomequb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_epu8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomnequb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_epu8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomfalseub ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_epu8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomtrueub ((__v16qi)__A, (__v16qi)__B);
-}
-
-/*pcom (integer, unsinged words) */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_epu16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomltuw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_epu16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomleuw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_epu16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgtuw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_epu16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgeuw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_epu16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomequw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_epu16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomnequw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_epu16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomfalseuw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_epu16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomtrueuw ((__v8hi)__A, (__v8hi)__B);
-}
-
-/*pcom (integer, unsinged double words) */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_epu32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomltud ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_epu32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomleud ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_epu32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgtud ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_epu32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgeud ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_epu32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomequd ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_epu32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomnequd ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_epu32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomfalseud ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_epu32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomtrueud ((__v4si)__A, (__v4si)__B);
-}
-
-/*pcom (integer, unsinged quad words) */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_epu64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomltuq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_epu64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomleuq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_epu64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgtuq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_epu64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgeuq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_epu64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomequq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_epu64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomnequq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_epu64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomfalseuq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_epu64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomtrueuq ((__v2di)__A, (__v2di)__B);
-}
-
-/*pcom (integer, signed bytes) */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomltb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomleb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgtb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgeb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomeqb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomneqb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomfalseb ((__v16qi)__A, (__v16qi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_epi8(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomtrueb ((__v16qi)__A, (__v16qi)__B);
-}
-
-/*pcom (integer, signed words) */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomltw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomlew ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgtw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgew ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomeqw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomneqw ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomfalsew ((__v8hi)__A, (__v8hi)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_epi16(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomtruew ((__v8hi)__A, (__v8hi)__B);
-}
-
-/*pcom (integer, signed double words) */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomltd ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomled ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgtd ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomged ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomeqd ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomneqd ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomfalsed ((__v4si)__A, (__v4si)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_epi32(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomtrued ((__v4si)__A, (__v4si)__B);
-}
-
-/*pcom (integer, signed quad words) */
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comlt_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomltq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comle_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomleq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comgt_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgtq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comge_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomgeq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comeq_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomeqq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comneq_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomneqq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comfalse_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomfalseq ((__v2di)__A, (__v2di)__B);
-}
-
-extern __inline __m128i __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_comtrue_epi64(__m128i __A, __m128i __B)
-{
- return (__m128i) __builtin_ia32_pcomtrueq ((__v2di)__A, (__v2di)__B);
-}
-
-/* FRCZ */
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_frcz_ps (__m128 __A)
-{
- return (__m128) __builtin_ia32_frczps ((__v4sf)__A);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_frcz_pd (__m128d __A)
-{
- return (__m128d) __builtin_ia32_frczpd ((__v2df)__A);
-}
-
-extern __inline __m128 __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_frcz_ss (__m128 __A, __m128 __B)
-{
- return (__m128) __builtin_ia32_frczss ((__v4sf)__A, (__v4sf)__B);
-}
-
-extern __inline __m128d __attribute__((__gnu_inline__, __always_inline__, __artificial__))
-_mm_frcz_sd (__m128d __A, __m128d __B)
-{
- return (__m128d) __builtin_ia32_frczsd ((__v2df)__A, (__v2df)__B);
-}
-
-#endif /* __SSE5__ */
+# error "SSE5 instruction set removed from compiler"
#endif /* _BMMINTRIN_H_INCLUDED */
def_or_undef (parse_in, "__FMA__");
if (isa_flag & OPTION_MASK_ISA_SSE4A)
def_or_undef (parse_in, "__SSE4A__");
- if (isa_flag & OPTION_MASK_ISA_SSE5)
- def_or_undef (parse_in, "__SSE5__");
if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE))
def_or_undef (parse_in, "__SSE_MATH__");
if ((fpmath & FPMATH_SSE) && (isa_flag & OPTION_MASK_ISA_SSE2))
extern bool ix86_expand_int_vcond (rtx[]);
extern void ix86_expand_sse_unpack (rtx[], bool, bool);
extern void ix86_expand_sse4_unpack (rtx[], bool, bool);
-extern void ix86_expand_sse5_unpack (rtx[], bool, bool);
-extern void ix86_expand_sse5_pack (rtx[]);
extern int ix86_expand_int_addcc (rtx[]);
extern void ix86_expand_call (rtx, rtx, rtx, rtx, rtx, int);
extern void x86_initialize_trampoline (rtx, rtx, rtx);
extern void ix86_expand_vector_extract (bool, rtx, rtx, int);
extern void ix86_expand_reduc_v4sf (rtx (*)(rtx, rtx, rtx), rtx, rtx);
-extern bool ix86_sse5_valid_op_p (rtx [], rtx, int, bool, int, bool);
-extern void ix86_expand_sse5_multiple_memory (rtx [], int, enum machine_mode);
-
/* In i386-c.c */
extern void ix86_target_macros (void);
extern void ix86_register_pragmas (void);
#define OPTION_MASK_ISA_SSE4A_SET \
(OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE3_SET)
-#define OPTION_MASK_ISA_SSE5_SET \
- (OPTION_MASK_ISA_SSE5 | OPTION_MASK_ISA_SSE4A_SET)
/* AES and PCLMUL need SSE2 because they use xmm registers */
#define OPTION_MASK_ISA_AES_SET \
#define OPTION_MASK_ISA_SSE4_UNSET OPTION_MASK_ISA_SSE4_1_UNSET
#define OPTION_MASK_ISA_SSE4A_UNSET \
- (OPTION_MASK_ISA_SSE4A | OPTION_MASK_ISA_SSE5_UNSET)
-#define OPTION_MASK_ISA_SSE5_UNSET OPTION_MASK_ISA_SSE5
+ (OPTION_MASK_ISA_SSE4A)
#define OPTION_MASK_ISA_AES_UNSET OPTION_MASK_ISA_AES
#define OPTION_MASK_ISA_PCLMUL_UNSET OPTION_MASK_ISA_PCLMUL
#define OPTION_MASK_ISA_ABM_UNSET OPTION_MASK_ISA_ABM
}
return true;
- case OPT_msse5:
- if (value)
- {
- ix86_isa_flags |= OPTION_MASK_ISA_SSE5_SET;
- ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_SET;
- }
- else
- {
- ix86_isa_flags &= ~OPTION_MASK_ISA_SSE5_UNSET;
- ix86_isa_flags_explicit |= OPTION_MASK_ISA_SSE5_UNSET;
- }
- return true;
-
case OPT_mabm:
if (value)
{
int mask; /* isa mask options */
};
- /* This table is ordered so that options like -msse5 or -msse4.2 that imply
+ /* This table is ordered so that options like -msse4.2 that imply
preceding options while match those first. */
static struct ix86_target_opts isa_opts[] =
{
{ "-m64", OPTION_MASK_ISA_64BIT },
- { "-msse5", OPTION_MASK_ISA_SSE5 },
{ "-msse4a", OPTION_MASK_ISA_SSE4A },
{ "-msse4.2", OPTION_MASK_ISA_SSE4_2 },
{ "-msse4.1", OPTION_MASK_ISA_SSE4_1 },
{ "-mms-bitfields", MASK_MS_BITFIELD_LAYOUT },
{ "-mno-align-stringops", MASK_NO_ALIGN_STRINGOPS },
{ "-mno-fancy-math-387", MASK_NO_FANCY_MATH_387 },
- { "-mno-fused-madd", MASK_NO_FUSED_MADD },
{ "-mno-push-args", MASK_NO_PUSH_ARGS },
{ "-mno-red-zone", MASK_NO_RED_ZONE },
{ "-momit-leaf-frame-pointer", MASK_OMIT_LEAF_FRAME_POINTER },
PTA_NO_SAHF = 1 << 13,
PTA_SSE4_1 = 1 << 14,
PTA_SSE4_2 = 1 << 15,
- PTA_SSE5 = 1 << 16,
- PTA_AES = 1 << 17,
- PTA_PCLMUL = 1 << 18,
- PTA_AVX = 1 << 19,
- PTA_FMA = 1 << 20,
- PTA_MOVBE = 1 << 21
+ PTA_AES = 1 << 16,
+ PTA_PCLMUL = 1 << 17,
+ PTA_AVX = 1 << 18,
+ PTA_FMA = 1 << 19,
+ PTA_MOVBE = 1 << 20
};
static struct pta
if (processor_alias_table[i].flags & PTA_SSE4A
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE4A))
ix86_isa_flags |= OPTION_MASK_ISA_SSE4A;
- if (processor_alias_table[i].flags & PTA_SSE5
- && !(ix86_isa_flags_explicit & OPTION_MASK_ISA_SSE5))
- ix86_isa_flags |= OPTION_MASK_ISA_SSE5;
if (processor_alias_table[i].flags & PTA_ABM
&& !(ix86_isa_flags_explicit & OPTION_MASK_ISA_ABM))
ix86_isa_flags |= OPTION_MASK_ISA_ABM;
IX86_ATTR_ISA ("sse4.1", OPT_msse4_1),
IX86_ATTR_ISA ("sse4.2", OPT_msse4_2),
IX86_ATTR_ISA ("sse4a", OPT_msse4a),
- IX86_ATTR_ISA ("sse5", OPT_msse5),
IX86_ATTR_ISA ("ssse3", OPT_mssse3),
/* string options */
OPT_mfancy_math_387,
MASK_NO_FANCY_MATH_387),
- IX86_ATTR_NO ("fused-madd",
- OPT_mfused_madd,
- MASK_NO_FUSED_MADD),
-
IX86_ATTR_YES ("ieee-fp",
OPT_mieee_fp,
MASK_IEEE_FP),
struct cl_target_option *caller_opts = TREE_TARGET_OPTION (caller_tree);
struct cl_target_option *callee_opts = TREE_TARGET_OPTION (callee_tree);
- /* Callee's isa options should a subset of the caller's, i.e. a SSE5 function
- can inline a SSE2 function but a SSE2 function can't inline a SSE5
+ /* Callee's isa options should a subset of the caller's, i.e. a SSE4 function
+ can inline a SSE2 function but a SSE2 function can't inline a SSE4
function. */
if ((caller_opts->ix86_isa_flags & callee_opts->ix86_isa_flags)
!= callee_opts->ix86_isa_flags)
X -- don't print any sort of PIC '@' suffix for a symbol.
& -- print some in-use local-dynamic symbol name.
H -- print a memory address offset by 8; used for sse high-parts
- Y -- print condition for SSE5 com* instruction.
+ -- print a branch hint as 'cs' or 'ds' prefix
; -- print a semicolon (after prefixes due to bug in older gas).
*/
return;
}
- case 'Y':
- switch (GET_CODE (x))
- {
- case NE:
- fputs ("neq", file);
- break;
- case EQ:
- fputs ("eq", file);
- break;
- case GE:
- case GEU:
- fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "ge" : "unlt", file);
- break;
- case GT:
- case GTU:
- fputs (INTEGRAL_MODE_P (GET_MODE (x)) ? "gt" : "unle", file);
- break;
- case LE:
- case LEU:
- fputs ("le", file);
- break;
- case LT:
- case LTU:
- fputs ("lt", file);
- break;
- case UNORDERED:
- fputs ("unord", file);
- break;
- case ORDERED:
- fputs ("ord", file);
- break;
- case UNEQ:
- fputs ("ueq", file);
- break;
- case UNGE:
- fputs ("nlt", file);
- break;
- case UNGT:
- fputs ("nle", file);
- break;
- case UNLE:
- fputs ("ule", file);
- break;
- case UNLT:
- fputs ("ult", file);
- break;
- case LTGT:
- fputs ("une", file);
- break;
- default:
- output_operand_lossage ("operand is not a condition code, invalid operand code 'D'");
- return;
- }
- return;
-
case ';':
#if TARGET_MACHO
fputs (" ; ", file);
x = gen_rtx_AND (mode, x, op_false);
emit_insn (gen_rtx_SET (VOIDmode, dest, x));
}
- else if (TARGET_SSE5)
- {
- rtx pcmov = gen_rtx_SET (mode, dest,
- gen_rtx_IF_THEN_ELSE (mode, cmp,
- op_true,
- op_false));
- emit_insn (pcmov);
- }
else
{
op_true = force_reg (mode, op_true);
cop0 = operands[4];
cop1 = operands[5];
- /* SSE5 supports all of the comparisons on all vector int types. */
- if (!TARGET_SSE5)
+ /* Canonicalize the comparison to EQ, GT, GTU. */
+ switch (code)
+ {
+ case EQ:
+ case GT:
+ case GTU:
+ break;
+
+ case NE:
+ case LE:
+ case LEU:
+ code = reverse_condition (code);
+ negate = true;
+ break;
+
+ case GE:
+ case GEU:
+ code = reverse_condition (code);
+ negate = true;
+ /* FALLTHRU */
+
+ case LT:
+ case LTU:
+ code = swap_condition (code);
+ x = cop0, cop0 = cop1, cop1 = x;
+ break;
+
+ default:
+ gcc_unreachable ();
+ }
+
+ /* Only SSE4.1/SSE4.2 supports V2DImode. */
+ if (mode == V2DImode)
{
- /* Canonicalize the comparison to EQ, GT, GTU. */
switch (code)
{
case EQ:
- case GT:
- case GTU:
- break;
-
- case NE:
- case LE:
- case LEU:
- code = reverse_condition (code);
- negate = true;
+ /* SSE4.1 supports EQ. */
+ if (!TARGET_SSE4_1)
+ return false;
break;
- case GE:
- case GEU:
- code = reverse_condition (code);
- negate = true;
- /* FALLTHRU */
-
- case LT:
- case LTU:
- code = swap_condition (code);
- x = cop0, cop0 = cop1, cop1 = x;
+ case GT:
+ case GTU:
+ /* SSE4.2 supports GT/GTU. */
+ if (!TARGET_SSE4_2)
+ return false;
break;
default:
gcc_unreachable ();
}
+ }
- /* Only SSE4.1/SSE4.2 supports V2DImode. */
- if (mode == V2DImode)
- {
- switch (code)
- {
- case EQ:
- /* SSE4.1 supports EQ. */
- if (!TARGET_SSE4_1)
- return false;
- break;
-
- case GT:
- case GTU:
- /* SSE4.2 supports GT/GTU. */
- if (!TARGET_SSE4_2)
- return false;
- break;
-
- default:
- gcc_unreachable ();
- }
- }
+ /* Unsigned parallel compare is not supported by the hardware. Play some
+ tricks to turn this into a signed comparison against 0. */
+ if (code == GTU)
+ {
+ cop0 = force_reg (mode, cop0);
- /* Unsigned parallel compare is not supported by the hardware. Play some
- tricks to turn this into a signed comparison against 0. */
- if (code == GTU)
+ switch (mode)
{
- cop0 = force_reg (mode, cop0);
-
- switch (mode)
- {
- case V4SImode:
- case V2DImode:
- {
- rtx t1, t2, mask;
-
- /* Perform a parallel modulo subtraction. */
- t1 = gen_reg_rtx (mode);
- emit_insn ((mode == V4SImode
- ? gen_subv4si3
- : gen_subv2di3) (t1, cop0, cop1));
-
- /* Extract the original sign bit of op0. */
- mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
- true, false);
- t2 = gen_reg_rtx (mode);
- emit_insn ((mode == V4SImode
- ? gen_andv4si3
- : gen_andv2di3) (t2, cop0, mask));
-
- /* XOR it back into the result of the subtraction. This results
- in the sign bit set iff we saw unsigned underflow. */
- x = gen_reg_rtx (mode);
- emit_insn ((mode == V4SImode
- ? gen_xorv4si3
- : gen_xorv2di3) (x, t1, t2));
-
- code = GT;
- }
- break;
-
- case V16QImode:
- case V8HImode:
- /* Perform a parallel unsigned saturating subtraction. */
- x = gen_reg_rtx (mode);
- emit_insn (gen_rtx_SET (VOIDmode, x,
- gen_rtx_US_MINUS (mode, cop0, cop1)));
+ case V4SImode:
+ case V2DImode:
+ {
+ rtx t1, t2, mask;
+
+ /* Perform a parallel modulo subtraction. */
+ t1 = gen_reg_rtx (mode);
+ emit_insn ((mode == V4SImode
+ ? gen_subv4si3
+ : gen_subv2di3) (t1, cop0, cop1));
+
+ /* Extract the original sign bit of op0. */
+ mask = ix86_build_signbit_mask (GET_MODE_INNER (mode),
+ true, false);
+ t2 = gen_reg_rtx (mode);
+ emit_insn ((mode == V4SImode
+ ? gen_andv4si3
+ : gen_andv2di3) (t2, cop0, mask));
+
+ /* XOR it back into the result of the subtraction. This results
+ in the sign bit set iff we saw unsigned underflow. */
+ x = gen_reg_rtx (mode);
+ emit_insn ((mode == V4SImode
+ ? gen_xorv4si3
+ : gen_xorv2di3) (x, t1, t2));
+
+ code = GT;
+ }
+ break;
- code = EQ;
- negate = !negate;
- break;
+ case V16QImode:
+ case V8HImode:
+ /* Perform a parallel unsigned saturating subtraction. */
+ x = gen_reg_rtx (mode);
+ emit_insn (gen_rtx_SET (VOIDmode, x,
+ gen_rtx_US_MINUS (mode, cop0, cop1)));
- default:
- gcc_unreachable ();
- }
+ code = EQ;
+ negate = !negate;
+ break;
- cop0 = x;
- cop1 = CONST0_RTX (mode);
+ default:
+ gcc_unreachable ();
}
+
+ cop0 = x;
+ cop1 = CONST0_RTX (mode);
}
x = ix86_expand_sse_cmp (operands[0], code, cop0, cop1,
emit_insn (unpack (dest, src));
}
-/* This function performs the same task as ix86_expand_sse_unpack,
- but with sse5 instructions. */
-
-void
-ix86_expand_sse5_unpack (rtx operands[2], bool unsigned_p, bool high_p)
-{
- enum machine_mode imode = GET_MODE (operands[1]);
- int pperm_bytes[16];
- int i;
- int h = (high_p) ? 8 : 0;
- int h2;
- int sign_extend;
- rtvec v = rtvec_alloc (16);
- rtvec vs;
- rtx x, p;
- rtx op0 = operands[0], op1 = operands[1];
-
- switch (imode)
- {
- case V16QImode:
- vs = rtvec_alloc (8);
- h2 = (high_p) ? 8 : 0;
- for (i = 0; i < 8; i++)
- {
- pperm_bytes[2*i+0] = PPERM_SRC | PPERM_SRC2 | i | h;
- pperm_bytes[2*i+1] = ((unsigned_p)
- ? PPERM_ZERO
- : PPERM_SIGN | PPERM_SRC2 | i | h);
- }
-
- for (i = 0; i < 16; i++)
- RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
-
- for (i = 0; i < 8; i++)
- RTVEC_ELT (vs, i) = GEN_INT (i + h2);
-
- p = gen_rtx_PARALLEL (VOIDmode, vs);
- x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
- if (unsigned_p)
- emit_insn (gen_sse5_pperm_zero_v16qi_v8hi (op0, op1, p, x));
- else
- emit_insn (gen_sse5_pperm_sign_v16qi_v8hi (op0, op1, p, x));
- break;
-
- case V8HImode:
- vs = rtvec_alloc (4);
- h2 = (high_p) ? 4 : 0;
- for (i = 0; i < 4; i++)
- {
- sign_extend = ((unsigned_p)
- ? PPERM_ZERO
- : PPERM_SIGN | PPERM_SRC2 | ((2*i) + 1 + h));
- pperm_bytes[4*i+0] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 0 + h);
- pperm_bytes[4*i+1] = PPERM_SRC | PPERM_SRC2 | ((2*i) + 1 + h);
- pperm_bytes[4*i+2] = sign_extend;
- pperm_bytes[4*i+3] = sign_extend;
- }
-
- for (i = 0; i < 16; i++)
- RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
-
- for (i = 0; i < 4; i++)
- RTVEC_ELT (vs, i) = GEN_INT (i + h2);
-
- p = gen_rtx_PARALLEL (VOIDmode, vs);
- x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
- if (unsigned_p)
- emit_insn (gen_sse5_pperm_zero_v8hi_v4si (op0, op1, p, x));
- else
- emit_insn (gen_sse5_pperm_sign_v8hi_v4si (op0, op1, p, x));
- break;
-
- case V4SImode:
- vs = rtvec_alloc (2);
- h2 = (high_p) ? 2 : 0;
- for (i = 0; i < 2; i++)
- {
- sign_extend = ((unsigned_p)
- ? PPERM_ZERO
- : PPERM_SIGN | PPERM_SRC2 | ((4*i) + 3 + h));
- pperm_bytes[8*i+0] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 0 + h);
- pperm_bytes[8*i+1] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 1 + h);
- pperm_bytes[8*i+2] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 2 + h);
- pperm_bytes[8*i+3] = PPERM_SRC | PPERM_SRC2 | ((4*i) + 3 + h);
- pperm_bytes[8*i+4] = sign_extend;
- pperm_bytes[8*i+5] = sign_extend;
- pperm_bytes[8*i+6] = sign_extend;
- pperm_bytes[8*i+7] = sign_extend;
- }
-
- for (i = 0; i < 16; i++)
- RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
-
- for (i = 0; i < 2; i++)
- RTVEC_ELT (vs, i) = GEN_INT (i + h2);
-
- p = gen_rtx_PARALLEL (VOIDmode, vs);
- x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
- if (unsigned_p)
- emit_insn (gen_sse5_pperm_zero_v4si_v2di (op0, op1, p, x));
- else
- emit_insn (gen_sse5_pperm_sign_v4si_v2di (op0, op1, p, x));
- break;
-
- default:
- gcc_unreachable ();
- }
-
- return;
-}
-
-/* Pack the high bits from OPERANDS[1] and low bits from OPERANDS[2] into the
- next narrower integer vector type */
-void
-ix86_expand_sse5_pack (rtx operands[3])
-{
- enum machine_mode imode = GET_MODE (operands[0]);
- int pperm_bytes[16];
- int i;
- rtvec v = rtvec_alloc (16);
- rtx x;
- rtx op0 = operands[0];
- rtx op1 = operands[1];
- rtx op2 = operands[2];
-
- switch (imode)
- {
- case V16QImode:
- for (i = 0; i < 8; i++)
- {
- pperm_bytes[i+0] = PPERM_SRC | PPERM_SRC1 | (i*2);
- pperm_bytes[i+8] = PPERM_SRC | PPERM_SRC2 | (i*2);
- }
-
- for (i = 0; i < 16; i++)
- RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
-
- x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
- emit_insn (gen_sse5_pperm_pack_v8hi_v16qi (op0, op1, op2, x));
- break;
-
- case V8HImode:
- for (i = 0; i < 4; i++)
- {
- pperm_bytes[(2*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 0);
- pperm_bytes[(2*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*4) + 1);
- pperm_bytes[(2*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 0);
- pperm_bytes[(2*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*4) + 1);
- }
-
- for (i = 0; i < 16; i++)
- RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
-
- x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
- emit_insn (gen_sse5_pperm_pack_v4si_v8hi (op0, op1, op2, x));
- break;
-
- case V4SImode:
- for (i = 0; i < 2; i++)
- {
- pperm_bytes[(4*i)+0] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 0);
- pperm_bytes[(4*i)+1] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 1);
- pperm_bytes[(4*i)+2] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 2);
- pperm_bytes[(4*i)+3] = PPERM_SRC | PPERM_SRC1 | ((i*8) + 3);
- pperm_bytes[(4*i)+8] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 0);
- pperm_bytes[(4*i)+9] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 1);
- pperm_bytes[(4*i)+10] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 2);
- pperm_bytes[(4*i)+11] = PPERM_SRC | PPERM_SRC2 | ((i*8) + 3);
- }
-
- for (i = 0; i < 16; i++)
- RTVEC_ELT (v, i) = GEN_INT (pperm_bytes[i]);
-
- x = force_reg (V16QImode, gen_rtx_CONST_VECTOR (V16QImode, v));
- emit_insn (gen_sse5_pperm_pack_v2di_v4si (op0, op1, op2, x));
- break;
-
- default:
- gcc_unreachable ();
- }
-
- return;
-}
-
/* Expand conditional increment or decrement using adb/sbb instructions.
The default case using setcc followed by the conditional move can be
done by generic code. */
IX86_BUILTIN_CVTUDQ2PS,
- /* SSE5 instructions */
- IX86_BUILTIN_FMADDSS,
- IX86_BUILTIN_FMADDSD,
- IX86_BUILTIN_FMADDPS,
- IX86_BUILTIN_FMADDPD,
- IX86_BUILTIN_FMSUBSS,
- IX86_BUILTIN_FMSUBSD,
- IX86_BUILTIN_FMSUBPS,
- IX86_BUILTIN_FMSUBPD,
- IX86_BUILTIN_FNMADDSS,
- IX86_BUILTIN_FNMADDSD,
- IX86_BUILTIN_FNMADDPS,
- IX86_BUILTIN_FNMADDPD,
- IX86_BUILTIN_FNMSUBSS,
- IX86_BUILTIN_FNMSUBSD,
- IX86_BUILTIN_FNMSUBPS,
- IX86_BUILTIN_FNMSUBPD,
- IX86_BUILTIN_PCMOV,
- IX86_BUILTIN_PCMOV_V2DI,
- IX86_BUILTIN_PCMOV_V4SI,
- IX86_BUILTIN_PCMOV_V8HI,
- IX86_BUILTIN_PCMOV_V16QI,
- IX86_BUILTIN_PCMOV_V4SF,
- IX86_BUILTIN_PCMOV_V2DF,
- IX86_BUILTIN_PPERM,
- IX86_BUILTIN_PERMPS,
- IX86_BUILTIN_PERMPD,
- IX86_BUILTIN_PMACSSWW,
- IX86_BUILTIN_PMACSWW,
- IX86_BUILTIN_PMACSSWD,
- IX86_BUILTIN_PMACSWD,
- IX86_BUILTIN_PMACSSDD,
- IX86_BUILTIN_PMACSDD,
- IX86_BUILTIN_PMACSSDQL,
- IX86_BUILTIN_PMACSSDQH,
- IX86_BUILTIN_PMACSDQL,
- IX86_BUILTIN_PMACSDQH,
- IX86_BUILTIN_PMADCSSWD,
- IX86_BUILTIN_PMADCSWD,
- IX86_BUILTIN_PHADDBW,
- IX86_BUILTIN_PHADDBD,
- IX86_BUILTIN_PHADDBQ,
- IX86_BUILTIN_PHADDWD,
- IX86_BUILTIN_PHADDWQ,
- IX86_BUILTIN_PHADDDQ,
- IX86_BUILTIN_PHADDUBW,
- IX86_BUILTIN_PHADDUBD,
- IX86_BUILTIN_PHADDUBQ,
- IX86_BUILTIN_PHADDUWD,
- IX86_BUILTIN_PHADDUWQ,
- IX86_BUILTIN_PHADDUDQ,
- IX86_BUILTIN_PHSUBBW,
- IX86_BUILTIN_PHSUBWD,
- IX86_BUILTIN_PHSUBDQ,
- IX86_BUILTIN_PROTB,
- IX86_BUILTIN_PROTW,
- IX86_BUILTIN_PROTD,
- IX86_BUILTIN_PROTQ,
- IX86_BUILTIN_PROTB_IMM,
- IX86_BUILTIN_PROTW_IMM,
- IX86_BUILTIN_PROTD_IMM,
- IX86_BUILTIN_PROTQ_IMM,
- IX86_BUILTIN_PSHLB,
- IX86_BUILTIN_PSHLW,
- IX86_BUILTIN_PSHLD,
- IX86_BUILTIN_PSHLQ,
- IX86_BUILTIN_PSHAB,
- IX86_BUILTIN_PSHAW,
- IX86_BUILTIN_PSHAD,
- IX86_BUILTIN_PSHAQ,
- IX86_BUILTIN_FRCZSS,
- IX86_BUILTIN_FRCZSD,
- IX86_BUILTIN_FRCZPS,
- IX86_BUILTIN_FRCZPD,
- IX86_BUILTIN_CVTPH2PS,
- IX86_BUILTIN_CVTPS2PH,
-
- IX86_BUILTIN_COMEQSS,
- IX86_BUILTIN_COMNESS,
- IX86_BUILTIN_COMLTSS,
- IX86_BUILTIN_COMLESS,
- IX86_BUILTIN_COMGTSS,
- IX86_BUILTIN_COMGESS,
- IX86_BUILTIN_COMUEQSS,
- IX86_BUILTIN_COMUNESS,
- IX86_BUILTIN_COMULTSS,
- IX86_BUILTIN_COMULESS,
- IX86_BUILTIN_COMUGTSS,
- IX86_BUILTIN_COMUGESS,
- IX86_BUILTIN_COMORDSS,
- IX86_BUILTIN_COMUNORDSS,
- IX86_BUILTIN_COMFALSESS,
- IX86_BUILTIN_COMTRUESS,
-
- IX86_BUILTIN_COMEQSD,
- IX86_BUILTIN_COMNESD,
- IX86_BUILTIN_COMLTSD,
- IX86_BUILTIN_COMLESD,
- IX86_BUILTIN_COMGTSD,
- IX86_BUILTIN_COMGESD,
- IX86_BUILTIN_COMUEQSD,
- IX86_BUILTIN_COMUNESD,
- IX86_BUILTIN_COMULTSD,
- IX86_BUILTIN_COMULESD,
- IX86_BUILTIN_COMUGTSD,
- IX86_BUILTIN_COMUGESD,
- IX86_BUILTIN_COMORDSD,
- IX86_BUILTIN_COMUNORDSD,
- IX86_BUILTIN_COMFALSESD,
- IX86_BUILTIN_COMTRUESD,
-
- IX86_BUILTIN_COMEQPS,
- IX86_BUILTIN_COMNEPS,
- IX86_BUILTIN_COMLTPS,
- IX86_BUILTIN_COMLEPS,
- IX86_BUILTIN_COMGTPS,
- IX86_BUILTIN_COMGEPS,
- IX86_BUILTIN_COMUEQPS,
- IX86_BUILTIN_COMUNEPS,
- IX86_BUILTIN_COMULTPS,
- IX86_BUILTIN_COMULEPS,
- IX86_BUILTIN_COMUGTPS,
- IX86_BUILTIN_COMUGEPS,
- IX86_BUILTIN_COMORDPS,
- IX86_BUILTIN_COMUNORDPS,
- IX86_BUILTIN_COMFALSEPS,
- IX86_BUILTIN_COMTRUEPS,
-
- IX86_BUILTIN_COMEQPD,
- IX86_BUILTIN_COMNEPD,
- IX86_BUILTIN_COMLTPD,
- IX86_BUILTIN_COMLEPD,
- IX86_BUILTIN_COMGTPD,
- IX86_BUILTIN_COMGEPD,
- IX86_BUILTIN_COMUEQPD,
- IX86_BUILTIN_COMUNEPD,
- IX86_BUILTIN_COMULTPD,
- IX86_BUILTIN_COMULEPD,
- IX86_BUILTIN_COMUGTPD,
- IX86_BUILTIN_COMUGEPD,
- IX86_BUILTIN_COMORDPD,
- IX86_BUILTIN_COMUNORDPD,
- IX86_BUILTIN_COMFALSEPD,
- IX86_BUILTIN_COMTRUEPD,
-
- IX86_BUILTIN_PCOMEQUB,
- IX86_BUILTIN_PCOMNEUB,
- IX86_BUILTIN_PCOMLTUB,
- IX86_BUILTIN_PCOMLEUB,
- IX86_BUILTIN_PCOMGTUB,
- IX86_BUILTIN_PCOMGEUB,
- IX86_BUILTIN_PCOMFALSEUB,
- IX86_BUILTIN_PCOMTRUEUB,
- IX86_BUILTIN_PCOMEQUW,
- IX86_BUILTIN_PCOMNEUW,
- IX86_BUILTIN_PCOMLTUW,
- IX86_BUILTIN_PCOMLEUW,
- IX86_BUILTIN_PCOMGTUW,
- IX86_BUILTIN_PCOMGEUW,
- IX86_BUILTIN_PCOMFALSEUW,
- IX86_BUILTIN_PCOMTRUEUW,
- IX86_BUILTIN_PCOMEQUD,
- IX86_BUILTIN_PCOMNEUD,
- IX86_BUILTIN_PCOMLTUD,
- IX86_BUILTIN_PCOMLEUD,
- IX86_BUILTIN_PCOMGTUD,
- IX86_BUILTIN_PCOMGEUD,
- IX86_BUILTIN_PCOMFALSEUD,
- IX86_BUILTIN_PCOMTRUEUD,
- IX86_BUILTIN_PCOMEQUQ,
- IX86_BUILTIN_PCOMNEUQ,
- IX86_BUILTIN_PCOMLTUQ,
- IX86_BUILTIN_PCOMLEUQ,
- IX86_BUILTIN_PCOMGTUQ,
- IX86_BUILTIN_PCOMGEUQ,
- IX86_BUILTIN_PCOMFALSEUQ,
- IX86_BUILTIN_PCOMTRUEUQ,
-
- IX86_BUILTIN_PCOMEQB,
- IX86_BUILTIN_PCOMNEB,
- IX86_BUILTIN_PCOMLTB,
- IX86_BUILTIN_PCOMLEB,
- IX86_BUILTIN_PCOMGTB,
- IX86_BUILTIN_PCOMGEB,
- IX86_BUILTIN_PCOMFALSEB,
- IX86_BUILTIN_PCOMTRUEB,
- IX86_BUILTIN_PCOMEQW,
- IX86_BUILTIN_PCOMNEW,
- IX86_BUILTIN_PCOMLTW,
- IX86_BUILTIN_PCOMLEW,
- IX86_BUILTIN_PCOMGTW,
- IX86_BUILTIN_PCOMGEW,
- IX86_BUILTIN_PCOMFALSEW,
- IX86_BUILTIN_PCOMTRUEW,
- IX86_BUILTIN_PCOMEQD,
- IX86_BUILTIN_PCOMNED,
- IX86_BUILTIN_PCOMLTD,
- IX86_BUILTIN_PCOMLED,
- IX86_BUILTIN_PCOMGTD,
- IX86_BUILTIN_PCOMGED,
- IX86_BUILTIN_PCOMFALSED,
- IX86_BUILTIN_PCOMTRUED,
- IX86_BUILTIN_PCOMEQQ,
- IX86_BUILTIN_PCOMNEQ,
- IX86_BUILTIN_PCOMLTQ,
- IX86_BUILTIN_PCOMLEQ,
- IX86_BUILTIN_PCOMGTQ,
- IX86_BUILTIN_PCOMGEQ,
- IX86_BUILTIN_PCOMFALSEQ,
- IX86_BUILTIN_PCOMTRUEQ,
-
IX86_BUILTIN_MAX
};
{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_sse4_1_mulv2siv2di3, "__builtin_ia32_pmuldq128", IX86_BUILTIN_PMULDQ128, UNKNOWN, (int) V2DI_FTYPE_V4SI_V4SI },
{ OPTION_MASK_ISA_SSE4_1, CODE_FOR_mulv4si3, "__builtin_ia32_pmulld128", IX86_BUILTIN_PMULLD128, UNKNOWN, (int) V4SI_FTYPE_V4SI_V4SI },
- /* SSE4.1 and SSE5 */
+ /* SSE4.1 */
{ OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundpd, "__builtin_ia32_roundpd", IX86_BUILTIN_ROUNDPD, UNKNOWN, (int) V2DF_FTYPE_V2DF_INT },
{ OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundps, "__builtin_ia32_roundps", IX86_BUILTIN_ROUNDPS, UNKNOWN, (int) V4SF_FTYPE_V4SF_INT },
{ OPTION_MASK_ISA_ROUND, CODE_FOR_sse4_1_roundsd, "__builtin_ia32_roundsd", IX86_BUILTIN_ROUNDSD, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT },
{ OPTION_MASK_ISA_AVX, CODE_FOR_avx_movmskps256, "__builtin_ia32_movmskps256", IX86_BUILTIN_MOVMSKPS256, UNKNOWN, (int) INT_FTYPE_V8SF },
};
-/* SSE5 */
-enum multi_arg_type {
- MULTI_ARG_UNKNOWN,
- MULTI_ARG_3_SF,
- MULTI_ARG_3_DF,
- MULTI_ARG_3_DI,
- MULTI_ARG_3_SI,
- MULTI_ARG_3_SI_DI,
- MULTI_ARG_3_HI,
- MULTI_ARG_3_HI_SI,
- MULTI_ARG_3_QI,
- MULTI_ARG_3_PERMPS,
- MULTI_ARG_3_PERMPD,
- MULTI_ARG_2_SF,
- MULTI_ARG_2_DF,
- MULTI_ARG_2_DI,
- MULTI_ARG_2_SI,
- MULTI_ARG_2_HI,
- MULTI_ARG_2_QI,
- MULTI_ARG_2_DI_IMM,
- MULTI_ARG_2_SI_IMM,
- MULTI_ARG_2_HI_IMM,
- MULTI_ARG_2_QI_IMM,
- MULTI_ARG_2_SF_CMP,
- MULTI_ARG_2_DF_CMP,
- MULTI_ARG_2_DI_CMP,
- MULTI_ARG_2_SI_CMP,
- MULTI_ARG_2_HI_CMP,
- MULTI_ARG_2_QI_CMP,
- MULTI_ARG_2_DI_TF,
- MULTI_ARG_2_SI_TF,
- MULTI_ARG_2_HI_TF,
- MULTI_ARG_2_QI_TF,
- MULTI_ARG_2_SF_TF,
- MULTI_ARG_2_DF_TF,
- MULTI_ARG_1_SF,
- MULTI_ARG_1_DF,
- MULTI_ARG_1_DI,
- MULTI_ARG_1_SI,
- MULTI_ARG_1_HI,
- MULTI_ARG_1_QI,
- MULTI_ARG_1_SI_DI,
- MULTI_ARG_1_HI_DI,
- MULTI_ARG_1_HI_SI,
- MULTI_ARG_1_QI_DI,
- MULTI_ARG_1_QI_SI,
- MULTI_ARG_1_QI_HI,
- MULTI_ARG_1_PH2PS,
- MULTI_ARG_1_PS2PH
-};
-
-static const struct builtin_description bdesc_multi_arg[] =
-{
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv4sf4, "__builtin_ia32_fmaddss", IX86_BUILTIN_FMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmaddv2df4, "__builtin_ia32_fmaddsd", IX86_BUILTIN_FMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv4sf4, "__builtin_ia32_fmaddps", IX86_BUILTIN_FMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmaddv2df4, "__builtin_ia32_fmaddpd", IX86_BUILTIN_FMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv4sf4, "__builtin_ia32_fmsubss", IX86_BUILTIN_FMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfmsubv2df4, "__builtin_ia32_fmsubsd", IX86_BUILTIN_FMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv4sf4, "__builtin_ia32_fmsubps", IX86_BUILTIN_FMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fmsubv2df4, "__builtin_ia32_fmsubpd", IX86_BUILTIN_FMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv4sf4, "__builtin_ia32_fnmaddss", IX86_BUILTIN_FNMADDSS, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmaddv2df4, "__builtin_ia32_fnmaddsd", IX86_BUILTIN_FNMADDSD, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv4sf4, "__builtin_ia32_fnmaddps", IX86_BUILTIN_FNMADDPS, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmaddv2df4, "__builtin_ia32_fnmaddpd", IX86_BUILTIN_FNMADDPD, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv4sf4, "__builtin_ia32_fnmsubss", IX86_BUILTIN_FNMSUBSS, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_vmfnmsubv2df4, "__builtin_ia32_fnmsubsd", IX86_BUILTIN_FNMSUBSD, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv4sf4, "__builtin_ia32_fnmsubps", IX86_BUILTIN_FNMSUBPS, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5i_fnmsubv2df4, "__builtin_ia32_fnmsubpd", IX86_BUILTIN_FNMSUBPD, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov", IX86_BUILTIN_PCMOV, UNKNOWN, (int)MULTI_ARG_3_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2di, "__builtin_ia32_pcmov_v2di", IX86_BUILTIN_PCMOV_V2DI, UNKNOWN, (int)MULTI_ARG_3_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4si, "__builtin_ia32_pcmov_v4si", IX86_BUILTIN_PCMOV_V4SI, UNKNOWN, (int)MULTI_ARG_3_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v8hi, "__builtin_ia32_pcmov_v8hi", IX86_BUILTIN_PCMOV_V8HI, UNKNOWN, (int)MULTI_ARG_3_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v16qi, "__builtin_ia32_pcmov_v16qi",IX86_BUILTIN_PCMOV_V16QI,UNKNOWN, (int)MULTI_ARG_3_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v2df, "__builtin_ia32_pcmov_v2df", IX86_BUILTIN_PCMOV_V2DF, UNKNOWN, (int)MULTI_ARG_3_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcmov_v4sf, "__builtin_ia32_pcmov_v4sf", IX86_BUILTIN_PCMOV_V4SF, UNKNOWN, (int)MULTI_ARG_3_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pperm, "__builtin_ia32_pperm", IX86_BUILTIN_PPERM, UNKNOWN, (int)MULTI_ARG_3_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv4sf, "__builtin_ia32_permps", IX86_BUILTIN_PERMPS, UNKNOWN, (int)MULTI_ARG_3_PERMPS },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_permv2df, "__builtin_ia32_permpd", IX86_BUILTIN_PERMPD, UNKNOWN, (int)MULTI_ARG_3_PERMPD },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssww, "__builtin_ia32_pmacssww", IX86_BUILTIN_PMACSSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsww, "__builtin_ia32_pmacsww", IX86_BUILTIN_PMACSWW, UNKNOWN, (int)MULTI_ARG_3_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsswd, "__builtin_ia32_pmacsswd", IX86_BUILTIN_PMACSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacswd, "__builtin_ia32_pmacswd", IX86_BUILTIN_PMACSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdd, "__builtin_ia32_pmacssdd", IX86_BUILTIN_PMACSSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdd, "__builtin_ia32_pmacsdd", IX86_BUILTIN_PMACSDD, UNKNOWN, (int)MULTI_ARG_3_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdql, "__builtin_ia32_pmacssdql", IX86_BUILTIN_PMACSSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacssdqh, "__builtin_ia32_pmacssdqh", IX86_BUILTIN_PMACSSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdql, "__builtin_ia32_pmacsdql", IX86_BUILTIN_PMACSDQL, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmacsdqh, "__builtin_ia32_pmacsdqh", IX86_BUILTIN_PMACSDQH, UNKNOWN, (int)MULTI_ARG_3_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcsswd, "__builtin_ia32_pmadcsswd", IX86_BUILTIN_PMADCSSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pmadcswd, "__builtin_ia32_pmadcswd", IX86_BUILTIN_PMADCSWD, UNKNOWN, (int)MULTI_ARG_3_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv2di3, "__builtin_ia32_protq", IX86_BUILTIN_PROTQ, UNKNOWN, (int)MULTI_ARG_2_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv4si3, "__builtin_ia32_protd", IX86_BUILTIN_PROTD, UNKNOWN, (int)MULTI_ARG_2_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv8hi3, "__builtin_ia32_protw", IX86_BUILTIN_PROTW, UNKNOWN, (int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vrotlv16qi3, "__builtin_ia32_protb", IX86_BUILTIN_PROTB, UNKNOWN, (int)MULTI_ARG_2_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv2di3, "__builtin_ia32_protqi", IX86_BUILTIN_PROTQ_IMM, UNKNOWN, (int)MULTI_ARG_2_DI_IMM },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv4si3, "__builtin_ia32_protdi", IX86_BUILTIN_PROTD_IMM, UNKNOWN, (int)MULTI_ARG_2_SI_IMM },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv8hi3, "__builtin_ia32_protwi", IX86_BUILTIN_PROTW_IMM, UNKNOWN, (int)MULTI_ARG_2_HI_IMM },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_rotlv16qi3, "__builtin_ia32_protbi", IX86_BUILTIN_PROTB_IMM, UNKNOWN, (int)MULTI_ARG_2_QI_IMM },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv2di3, "__builtin_ia32_pshaq", IX86_BUILTIN_PSHAQ, UNKNOWN, (int)MULTI_ARG_2_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv4si3, "__builtin_ia32_pshad", IX86_BUILTIN_PSHAD, UNKNOWN, (int)MULTI_ARG_2_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv8hi3, "__builtin_ia32_pshaw", IX86_BUILTIN_PSHAW, UNKNOWN, (int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_ashlv16qi3, "__builtin_ia32_pshab", IX86_BUILTIN_PSHAB, UNKNOWN, (int)MULTI_ARG_2_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv2di3, "__builtin_ia32_pshlq", IX86_BUILTIN_PSHLQ, UNKNOWN, (int)MULTI_ARG_2_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv4si3, "__builtin_ia32_pshld", IX86_BUILTIN_PSHLD, UNKNOWN, (int)MULTI_ARG_2_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv8hi3, "__builtin_ia32_pshlw", IX86_BUILTIN_PSHLW, UNKNOWN, (int)MULTI_ARG_2_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_lshlv16qi3, "__builtin_ia32_pshlb", IX86_BUILTIN_PSHLB, UNKNOWN, (int)MULTI_ARG_2_QI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv4sf2, "__builtin_ia32_frczss", IX86_BUILTIN_FRCZSS, UNKNOWN, (int)MULTI_ARG_2_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmfrczv2df2, "__builtin_ia32_frczsd", IX86_BUILTIN_FRCZSD, UNKNOWN, (int)MULTI_ARG_2_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv4sf2, "__builtin_ia32_frczps", IX86_BUILTIN_FRCZPS, UNKNOWN, (int)MULTI_ARG_1_SF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_frczv2df2, "__builtin_ia32_frczpd", IX86_BUILTIN_FRCZPD, UNKNOWN, (int)MULTI_ARG_1_DF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtph2ps, "__builtin_ia32_cvtph2ps", IX86_BUILTIN_CVTPH2PS, UNKNOWN, (int)MULTI_ARG_1_PH2PS },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_cvtps2ph, "__builtin_ia32_cvtps2ph", IX86_BUILTIN_CVTPS2PH, UNKNOWN, (int)MULTI_ARG_1_PS2PH },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbw, "__builtin_ia32_phaddbw", IX86_BUILTIN_PHADDBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbd, "__builtin_ia32_phaddbd", IX86_BUILTIN_PHADDBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddbq, "__builtin_ia32_phaddbq", IX86_BUILTIN_PHADDBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwd, "__builtin_ia32_phaddwd", IX86_BUILTIN_PHADDWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddwq, "__builtin_ia32_phaddwq", IX86_BUILTIN_PHADDWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadddq, "__builtin_ia32_phadddq", IX86_BUILTIN_PHADDDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubw, "__builtin_ia32_phaddubw", IX86_BUILTIN_PHADDUBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubd, "__builtin_ia32_phaddubd", IX86_BUILTIN_PHADDUBD, UNKNOWN, (int)MULTI_ARG_1_QI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddubq, "__builtin_ia32_phaddubq", IX86_BUILTIN_PHADDUBQ, UNKNOWN, (int)MULTI_ARG_1_QI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwd, "__builtin_ia32_phadduwd", IX86_BUILTIN_PHADDUWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phadduwq, "__builtin_ia32_phadduwq", IX86_BUILTIN_PHADDUWQ, UNKNOWN, (int)MULTI_ARG_1_HI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phaddudq, "__builtin_ia32_phaddudq", IX86_BUILTIN_PHADDUDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubbw, "__builtin_ia32_phsubbw", IX86_BUILTIN_PHSUBBW, UNKNOWN, (int)MULTI_ARG_1_QI_HI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubwd, "__builtin_ia32_phsubwd", IX86_BUILTIN_PHSUBWD, UNKNOWN, (int)MULTI_ARG_1_HI_SI },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_phsubdq, "__builtin_ia32_phsubdq", IX86_BUILTIN_PHSUBDQ, UNKNOWN, (int)MULTI_ARG_1_SI_DI },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comeqss", IX86_BUILTIN_COMEQSS, EQ, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comness", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comneqss", IX86_BUILTIN_COMNESS, NE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comltss", IX86_BUILTIN_COMLTSS, LT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comless", IX86_BUILTIN_COMLESS, LE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgtss", IX86_BUILTIN_COMGTSS, GT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comgess", IX86_BUILTIN_COMGESS, GE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comueqss", IX86_BUILTIN_COMUEQSS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuness", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comuneqss", IX86_BUILTIN_COMUNESS, LTGT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunltss", IX86_BUILTIN_COMULTSS, UNLT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunless", IX86_BUILTIN_COMULESS, UNLE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungtss", IX86_BUILTIN_COMUGTSS, UNGT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comungess", IX86_BUILTIN_COMUGESS, UNGE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comordss", IX86_BUILTIN_COMORDSS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv4sf3, "__builtin_ia32_comunordss", IX86_BUILTIN_COMUNORDSS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comeqsd", IX86_BUILTIN_COMEQSD, EQ, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comnesd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comneqsd", IX86_BUILTIN_COMNESD, NE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comltsd", IX86_BUILTIN_COMLTSD, LT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comlesd", IX86_BUILTIN_COMLESD, LE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgtsd", IX86_BUILTIN_COMGTSD, GT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comgesd", IX86_BUILTIN_COMGESD, GE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comueqsd", IX86_BUILTIN_COMUEQSD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunesd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comuneqsd", IX86_BUILTIN_COMUNESD, LTGT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunltsd", IX86_BUILTIN_COMULTSD, UNLT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunlesd", IX86_BUILTIN_COMULESD, UNLE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungtsd", IX86_BUILTIN_COMUGTSD, UNGT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comungesd", IX86_BUILTIN_COMUGESD, UNGE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comordsd", IX86_BUILTIN_COMORDSD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_vmmaskcmpv2df3, "__builtin_ia32_comunordsd", IX86_BUILTIN_COMUNORDSD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comeqps", IX86_BUILTIN_COMEQPS, EQ, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comneqps", IX86_BUILTIN_COMNEPS, NE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comltps", IX86_BUILTIN_COMLTPS, LT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comleps", IX86_BUILTIN_COMLEPS, LE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgtps", IX86_BUILTIN_COMGTPS, GT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comgeps", IX86_BUILTIN_COMGEPS, GE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comueqps", IX86_BUILTIN_COMUEQPS, UNEQ, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comuneqps", IX86_BUILTIN_COMUNEPS, LTGT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunltps", IX86_BUILTIN_COMULTPS, UNLT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunleps", IX86_BUILTIN_COMULEPS, UNLE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungtps", IX86_BUILTIN_COMUGTPS, UNGT, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comungeps", IX86_BUILTIN_COMUGEPS, UNGE, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comordps", IX86_BUILTIN_COMORDPS, ORDERED, (int)MULTI_ARG_2_SF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4sf3, "__builtin_ia32_comunordps", IX86_BUILTIN_COMUNORDPS, UNORDERED, (int)MULTI_ARG_2_SF_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comeqpd", IX86_BUILTIN_COMEQPD, EQ, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comnepd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comneqpd", IX86_BUILTIN_COMNEPD, NE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comltpd", IX86_BUILTIN_COMLTPD, LT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comlepd", IX86_BUILTIN_COMLEPD, LE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgtpd", IX86_BUILTIN_COMGTPD, GT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comgepd", IX86_BUILTIN_COMGEPD, GE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comueqpd", IX86_BUILTIN_COMUEQPD, UNEQ, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunepd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comuneqpd", IX86_BUILTIN_COMUNEPD, LTGT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunltpd", IX86_BUILTIN_COMULTPD, UNLT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunlepd", IX86_BUILTIN_COMULEPD, UNLE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungtpd", IX86_BUILTIN_COMUGTPD, UNGT, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comungepd", IX86_BUILTIN_COMUGEPD, UNGE, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comordpd", IX86_BUILTIN_COMORDPD, ORDERED, (int)MULTI_ARG_2_DF_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2df3, "__builtin_ia32_comunordpd", IX86_BUILTIN_COMUNORDPD, UNORDERED, (int)MULTI_ARG_2_DF_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomeqb", IX86_BUILTIN_PCOMEQB, EQ, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomneqb", IX86_BUILTIN_PCOMNEB, NE, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomltb", IX86_BUILTIN_PCOMLTB, LT, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomleb", IX86_BUILTIN_PCOMLEB, LE, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgtb", IX86_BUILTIN_PCOMGTB, GT, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv16qi3, "__builtin_ia32_pcomgeb", IX86_BUILTIN_PCOMGEB, GE, (int)MULTI_ARG_2_QI_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomeqw", IX86_BUILTIN_PCOMEQW, EQ, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomnew", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomneqw", IX86_BUILTIN_PCOMNEW, NE, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomltw", IX86_BUILTIN_PCOMLTW, LT, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomlew", IX86_BUILTIN_PCOMLEW, LE, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgtw", IX86_BUILTIN_PCOMGTW, GT, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv8hi3, "__builtin_ia32_pcomgew", IX86_BUILTIN_PCOMGEW, GE, (int)MULTI_ARG_2_HI_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomeqd", IX86_BUILTIN_PCOMEQD, EQ, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomned", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomneqd", IX86_BUILTIN_PCOMNED, NE, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomltd", IX86_BUILTIN_PCOMLTD, LT, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomled", IX86_BUILTIN_PCOMLED, LE, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomgtd", IX86_BUILTIN_PCOMGTD, GT, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv4si3, "__builtin_ia32_pcomged", IX86_BUILTIN_PCOMGED, GE, (int)MULTI_ARG_2_SI_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomeqq", IX86_BUILTIN_PCOMEQQ, EQ, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomneqq", IX86_BUILTIN_PCOMNEQ, NE, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomltq", IX86_BUILTIN_PCOMLTQ, LT, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomleq", IX86_BUILTIN_PCOMLEQ, LE, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgtq", IX86_BUILTIN_PCOMGTQ, GT, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmpv2di3, "__builtin_ia32_pcomgeq", IX86_BUILTIN_PCOMGEQ, GE, (int)MULTI_ARG_2_DI_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomequb", IX86_BUILTIN_PCOMEQUB, EQ, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomneub", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v16qi3,"__builtin_ia32_pcomnequb", IX86_BUILTIN_PCOMNEUB, NE, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomltub", IX86_BUILTIN_PCOMLTUB, LTU, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomleub", IX86_BUILTIN_PCOMLEUB, LEU, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgtub", IX86_BUILTIN_PCOMGTUB, GTU, (int)MULTI_ARG_2_QI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv16qi3, "__builtin_ia32_pcomgeub", IX86_BUILTIN_PCOMGEUB, GEU, (int)MULTI_ARG_2_QI_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomequw", IX86_BUILTIN_PCOMEQUW, EQ, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomneuw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v8hi3, "__builtin_ia32_pcomnequw", IX86_BUILTIN_PCOMNEUW, NE, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomltuw", IX86_BUILTIN_PCOMLTUW, LTU, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomleuw", IX86_BUILTIN_PCOMLEUW, LEU, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgtuw", IX86_BUILTIN_PCOMGTUW, GTU, (int)MULTI_ARG_2_HI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv8hi3, "__builtin_ia32_pcomgeuw", IX86_BUILTIN_PCOMGEUW, GEU, (int)MULTI_ARG_2_HI_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomequd", IX86_BUILTIN_PCOMEQUD, EQ, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomneud", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v4si3, "__builtin_ia32_pcomnequd", IX86_BUILTIN_PCOMNEUD, NE, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomltud", IX86_BUILTIN_PCOMLTUD, LTU, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomleud", IX86_BUILTIN_PCOMLEUD, LEU, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgtud", IX86_BUILTIN_PCOMGTUD, GTU, (int)MULTI_ARG_2_SI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv4si3, "__builtin_ia32_pcomgeud", IX86_BUILTIN_PCOMGEUD, GEU, (int)MULTI_ARG_2_SI_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomequq", IX86_BUILTIN_PCOMEQUQ, EQ, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomneuq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_uns2v2di3, "__builtin_ia32_pcomnequq", IX86_BUILTIN_PCOMNEUQ, NE, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomltuq", IX86_BUILTIN_PCOMLTUQ, LTU, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomleuq", IX86_BUILTIN_PCOMLEUQ, LEU, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgtuq", IX86_BUILTIN_PCOMGTUQ, GTU, (int)MULTI_ARG_2_DI_CMP },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_maskcmp_unsv2di3, "__builtin_ia32_pcomgeuq", IX86_BUILTIN_PCOMGEUQ, GEU, (int)MULTI_ARG_2_DI_CMP },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalsess", IX86_BUILTIN_COMFALSESS, (enum rtx_code) COM_FALSE_S, (int)MULTI_ARG_2_SF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtruess", IX86_BUILTIN_COMTRUESS, (enum rtx_code) COM_TRUE_S, (int)MULTI_ARG_2_SF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comfalseps", IX86_BUILTIN_COMFALSEPS, (enum rtx_code) COM_FALSE_P, (int)MULTI_ARG_2_SF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv4sf3, "__builtin_ia32_comtrueps", IX86_BUILTIN_COMTRUEPS, (enum rtx_code) COM_TRUE_P, (int)MULTI_ARG_2_SF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsesd", IX86_BUILTIN_COMFALSESD, (enum rtx_code) COM_FALSE_S, (int)MULTI_ARG_2_DF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruesd", IX86_BUILTIN_COMTRUESD, (enum rtx_code) COM_TRUE_S, (int)MULTI_ARG_2_DF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comfalsepd", IX86_BUILTIN_COMFALSEPD, (enum rtx_code) COM_FALSE_P, (int)MULTI_ARG_2_DF_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_com_tfv2df3, "__builtin_ia32_comtruepd", IX86_BUILTIN_COMTRUEPD, (enum rtx_code) COM_TRUE_P, (int)MULTI_ARG_2_DF_TF },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseb", IX86_BUILTIN_PCOMFALSEB, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalsew", IX86_BUILTIN_PCOMFALSEW, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalsed", IX86_BUILTIN_PCOMFALSED, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseq", IX86_BUILTIN_PCOMFALSEQ, (enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomfalseub",IX86_BUILTIN_PCOMFALSEUB,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_QI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomfalseuw",IX86_BUILTIN_PCOMFALSEUW,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_HI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomfalseud",IX86_BUILTIN_PCOMFALSEUD,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_SI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomfalseuq",IX86_BUILTIN_PCOMFALSEUQ,(enum rtx_code) PCOM_FALSE, (int)MULTI_ARG_2_DI_TF },
-
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueb", IX86_BUILTIN_PCOMTRUEB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtruew", IX86_BUILTIN_PCOMTRUEW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrued", IX86_BUILTIN_PCOMTRUED, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueq", IX86_BUILTIN_PCOMTRUEQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv16qi3, "__builtin_ia32_pcomtrueub", IX86_BUILTIN_PCOMTRUEUB, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_QI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv8hi3, "__builtin_ia32_pcomtrueuw", IX86_BUILTIN_PCOMTRUEUW, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_HI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv4si3, "__builtin_ia32_pcomtrueud", IX86_BUILTIN_PCOMTRUEUD, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_SI_TF },
- { OPTION_MASK_ISA_SSE5, CODE_FOR_sse5_pcom_tfv2di3, "__builtin_ia32_pcomtrueuq", IX86_BUILTIN_PCOMTRUEUQ, (enum rtx_code) PCOM_TRUE, (int)MULTI_ARG_2_DI_TF },
-};
/* Set up all the MMX/SSE builtins, even builtins for instructions that are not
in the current target ISA to allow the user to compile particular modules
integer_type_node,
NULL_TREE);
- /* SSE5 instructions */
- tree v2di_ftype_v2di_v2di_v2di
- = build_function_type_list (V2DI_type_node,
- V2DI_type_node,
- V2DI_type_node,
- V2DI_type_node,
- NULL_TREE);
-
- tree v4si_ftype_v4si_v4si_v4si
- = build_function_type_list (V4SI_type_node,
- V4SI_type_node,
- V4SI_type_node,
- V4SI_type_node,
- NULL_TREE);
-
- tree v4si_ftype_v4si_v4si_v2di
- = build_function_type_list (V4SI_type_node,
- V4SI_type_node,
- V4SI_type_node,
- V2DI_type_node,
- NULL_TREE);
-
- tree v8hi_ftype_v8hi_v8hi_v8hi
- = build_function_type_list (V8HI_type_node,
- V8HI_type_node,
- V8HI_type_node,
- V8HI_type_node,
- NULL_TREE);
-
- tree v8hi_ftype_v8hi_v8hi_v4si
- = build_function_type_list (V8HI_type_node,
- V8HI_type_node,
- V8HI_type_node,
- V4SI_type_node,
- NULL_TREE);
-
- tree v2df_ftype_v2df_v2df_v16qi
- = build_function_type_list (V2DF_type_node,
- V2DF_type_node,
- V2DF_type_node,
- V16QI_type_node,
- NULL_TREE);
-
- tree v4sf_ftype_v4sf_v4sf_v16qi
- = build_function_type_list (V4SF_type_node,
- V4SF_type_node,
- V4SF_type_node,
- V16QI_type_node,
- NULL_TREE);
-
- tree v2di_ftype_v2di_si
- = build_function_type_list (V2DI_type_node,
- V2DI_type_node,
- integer_type_node,
- NULL_TREE);
-
- tree v4si_ftype_v4si_si
- = build_function_type_list (V4SI_type_node,
- V4SI_type_node,
- integer_type_node,
- NULL_TREE);
-
- tree v8hi_ftype_v8hi_si
- = build_function_type_list (V8HI_type_node,
- V8HI_type_node,
- integer_type_node,
- NULL_TREE);
-
- tree v16qi_ftype_v16qi_si
- = build_function_type_list (V16QI_type_node,
- V16QI_type_node,
- integer_type_node,
- NULL_TREE);
- tree v4sf_ftype_v4hi
- = build_function_type_list (V4SF_type_node,
- V4HI_type_node,
- NULL_TREE);
-
- tree v4hi_ftype_v4sf
- = build_function_type_list (V4HI_type_node,
- V4SF_type_node,
- NULL_TREE);
tree v2di_ftype_v2di
= build_function_type_list (V2DI_type_node, V2DI_type_node, NULL_TREE);
intQI_type_node,
integer_type_node, NULL_TREE);
def_builtin_const (OPTION_MASK_ISA_SSE4_1, "__builtin_ia32_vec_set_v16qi", ftype, IX86_BUILTIN_VEC_SET_V16QI);
-
- /* Add SSE5 multi-arg argument instructions */
- for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
- {
- tree mtype = NULL_TREE;
-
- if (d->name == 0)
- continue;
-
- switch ((enum multi_arg_type)d->flag)
- {
- case MULTI_ARG_3_SF: mtype = v4sf_ftype_v4sf_v4sf_v4sf; break;
- case MULTI_ARG_3_DF: mtype = v2df_ftype_v2df_v2df_v2df; break;
- case MULTI_ARG_3_DI: mtype = v2di_ftype_v2di_v2di_v2di; break;
- case MULTI_ARG_3_SI: mtype = v4si_ftype_v4si_v4si_v4si; break;
- case MULTI_ARG_3_SI_DI: mtype = v4si_ftype_v4si_v4si_v2di; break;
- case MULTI_ARG_3_HI: mtype = v8hi_ftype_v8hi_v8hi_v8hi; break;
- case MULTI_ARG_3_HI_SI: mtype = v8hi_ftype_v8hi_v8hi_v4si; break;
- case MULTI_ARG_3_QI: mtype = v16qi_ftype_v16qi_v16qi_v16qi; break;
- case MULTI_ARG_3_PERMPS: mtype = v4sf_ftype_v4sf_v4sf_v16qi; break;
- case MULTI_ARG_3_PERMPD: mtype = v2df_ftype_v2df_v2df_v16qi; break;
- case MULTI_ARG_2_SF: mtype = v4sf_ftype_v4sf_v4sf; break;
- case MULTI_ARG_2_DF: mtype = v2df_ftype_v2df_v2df; break;
- case MULTI_ARG_2_DI: mtype = v2di_ftype_v2di_v2di; break;
- case MULTI_ARG_2_SI: mtype = v4si_ftype_v4si_v4si; break;
- case MULTI_ARG_2_HI: mtype = v8hi_ftype_v8hi_v8hi; break;
- case MULTI_ARG_2_QI: mtype = v16qi_ftype_v16qi_v16qi; break;
- case MULTI_ARG_2_DI_IMM: mtype = v2di_ftype_v2di_si; break;
- case MULTI_ARG_2_SI_IMM: mtype = v4si_ftype_v4si_si; break;
- case MULTI_ARG_2_HI_IMM: mtype = v8hi_ftype_v8hi_si; break;
- case MULTI_ARG_2_QI_IMM: mtype = v16qi_ftype_v16qi_si; break;
- case MULTI_ARG_2_SF_CMP: mtype = v4sf_ftype_v4sf_v4sf; break;
- case MULTI_ARG_2_DF_CMP: mtype = v2df_ftype_v2df_v2df; break;
- case MULTI_ARG_2_DI_CMP: mtype = v2di_ftype_v2di_v2di; break;
- case MULTI_ARG_2_SI_CMP: mtype = v4si_ftype_v4si_v4si; break;
- case MULTI_ARG_2_HI_CMP: mtype = v8hi_ftype_v8hi_v8hi; break;
- case MULTI_ARG_2_QI_CMP: mtype = v16qi_ftype_v16qi_v16qi; break;
- case MULTI_ARG_2_SF_TF: mtype = v4sf_ftype_v4sf_v4sf; break;
- case MULTI_ARG_2_DF_TF: mtype = v2df_ftype_v2df_v2df; break;
- case MULTI_ARG_2_DI_TF: mtype = v2di_ftype_v2di_v2di; break;
- case MULTI_ARG_2_SI_TF: mtype = v4si_ftype_v4si_v4si; break;
- case MULTI_ARG_2_HI_TF: mtype = v8hi_ftype_v8hi_v8hi; break;
- case MULTI_ARG_2_QI_TF: mtype = v16qi_ftype_v16qi_v16qi; break;
- case MULTI_ARG_1_SF: mtype = v4sf_ftype_v4sf; break;
- case MULTI_ARG_1_DF: mtype = v2df_ftype_v2df; break;
- case MULTI_ARG_1_DI: mtype = v2di_ftype_v2di; break;
- case MULTI_ARG_1_SI: mtype = v4si_ftype_v4si; break;
- case MULTI_ARG_1_HI: mtype = v8hi_ftype_v8hi; break;
- case MULTI_ARG_1_QI: mtype = v16qi_ftype_v16qi; break;
- case MULTI_ARG_1_SI_DI: mtype = v2di_ftype_v4si; break;
- case MULTI_ARG_1_HI_DI: mtype = v2di_ftype_v8hi; break;
- case MULTI_ARG_1_HI_SI: mtype = v4si_ftype_v8hi; break;
- case MULTI_ARG_1_QI_DI: mtype = v2di_ftype_v16qi; break;
- case MULTI_ARG_1_QI_SI: mtype = v4si_ftype_v16qi; break;
- case MULTI_ARG_1_QI_HI: mtype = v8hi_ftype_v16qi; break;
- case MULTI_ARG_1_PH2PS: mtype = v4sf_ftype_v4hi; break;
- case MULTI_ARG_1_PS2PH: mtype = v4hi_ftype_v4sf; break;
- case MULTI_ARG_UNKNOWN:
- default:
- gcc_unreachable ();
- }
-
- if (mtype)
- def_builtin_const (d->mask, d->name, mtype, d->code);
- }
}
/* Internal method for ix86_init_builtins. */
return target;
}
-/* Subroutine of ix86_expand_builtin to take care of 2-4 argument insns. */
-
-static rtx
-ix86_expand_multi_arg_builtin (enum insn_code icode, tree exp, rtx target,
- enum multi_arg_type m_type,
- enum rtx_code sub_code)
-{
- rtx pat;
- int i;
- int nargs;
- bool comparison_p = false;
- bool tf_p = false;
- bool last_arg_constant = false;
- int num_memory = 0;
- struct {
- rtx op;
- enum machine_mode mode;
- } args[4];
-
- enum machine_mode tmode = insn_data[icode].operand[0].mode;
-
- switch (m_type)
- {
- case MULTI_ARG_3_SF:
- case MULTI_ARG_3_DF:
- case MULTI_ARG_3_DI:
- case MULTI_ARG_3_SI:
- case MULTI_ARG_3_SI_DI:
- case MULTI_ARG_3_HI:
- case MULTI_ARG_3_HI_SI:
- case MULTI_ARG_3_QI:
- case MULTI_ARG_3_PERMPS:
- case MULTI_ARG_3_PERMPD:
- nargs = 3;
- break;
-
- case MULTI_ARG_2_SF:
- case MULTI_ARG_2_DF:
- case MULTI_ARG_2_DI:
- case MULTI_ARG_2_SI:
- case MULTI_ARG_2_HI:
- case MULTI_ARG_2_QI:
- nargs = 2;
- break;
-
- case MULTI_ARG_2_DI_IMM:
- case MULTI_ARG_2_SI_IMM:
- case MULTI_ARG_2_HI_IMM:
- case MULTI_ARG_2_QI_IMM:
- nargs = 2;
- last_arg_constant = true;
- break;
-
- case MULTI_ARG_1_SF:
- case MULTI_ARG_1_DF:
- case MULTI_ARG_1_DI:
- case MULTI_ARG_1_SI:
- case MULTI_ARG_1_HI:
- case MULTI_ARG_1_QI:
- case MULTI_ARG_1_SI_DI:
- case MULTI_ARG_1_HI_DI:
- case MULTI_ARG_1_HI_SI:
- case MULTI_ARG_1_QI_DI:
- case MULTI_ARG_1_QI_SI:
- case MULTI_ARG_1_QI_HI:
- case MULTI_ARG_1_PH2PS:
- case MULTI_ARG_1_PS2PH:
- nargs = 1;
- break;
-
- case MULTI_ARG_2_SF_CMP:
- case MULTI_ARG_2_DF_CMP:
- case MULTI_ARG_2_DI_CMP:
- case MULTI_ARG_2_SI_CMP:
- case MULTI_ARG_2_HI_CMP:
- case MULTI_ARG_2_QI_CMP:
- nargs = 2;
- comparison_p = true;
- break;
-
- case MULTI_ARG_2_SF_TF:
- case MULTI_ARG_2_DF_TF:
- case MULTI_ARG_2_DI_TF:
- case MULTI_ARG_2_SI_TF:
- case MULTI_ARG_2_HI_TF:
- case MULTI_ARG_2_QI_TF:
- nargs = 2;
- tf_p = true;
- break;
-
- case MULTI_ARG_UNKNOWN:
- default:
- gcc_unreachable ();
- }
-
- if (optimize || !target
- || GET_MODE (target) != tmode
- || ! (*insn_data[icode].operand[0].predicate) (target, tmode))
- target = gen_reg_rtx (tmode);
-
- gcc_assert (nargs <= 4);
-
- for (i = 0; i < nargs; i++)
- {
- tree arg = CALL_EXPR_ARG (exp, i);
- rtx op = expand_normal (arg);
- int adjust = (comparison_p) ? 1 : 0;
- enum machine_mode mode = insn_data[icode].operand[i+adjust+1].mode;
-
- if (last_arg_constant && i == nargs-1)
- {
- if (!CONST_INT_P (op))
- {
- error ("last argument must be an immediate");
- return gen_reg_rtx (tmode);
- }
- }
- else
- {
- if (VECTOR_MODE_P (mode))
- op = safe_vector_operand (op, mode);
-
- /* If we aren't optimizing, only allow one memory operand to be
- generated. */
- if (memory_operand (op, mode))
- num_memory++;
-
- gcc_assert (GET_MODE (op) == mode || GET_MODE (op) == VOIDmode);
-
- if (optimize
- || ! (*insn_data[icode].operand[i+adjust+1].predicate) (op, mode)
- || num_memory > 1)
- op = force_reg (mode, op);
- }
-
- args[i].op = op;
- args[i].mode = mode;
- }
-
- switch (nargs)
- {
- case 1:
- pat = GEN_FCN (icode) (target, args[0].op);
- break;
-
- case 2:
- if (tf_p)
- pat = GEN_FCN (icode) (target, args[0].op, args[1].op,
- GEN_INT ((int)sub_code));
- else if (! comparison_p)
- pat = GEN_FCN (icode) (target, args[0].op, args[1].op);
- else
- {
- rtx cmp_op = gen_rtx_fmt_ee (sub_code, GET_MODE (target),
- args[0].op,
- args[1].op);
-
- pat = GEN_FCN (icode) (target, cmp_op, args[0].op, args[1].op);
- }
- break;
-
- case 3:
- pat = GEN_FCN (icode) (target, args[0].op, args[1].op, args[2].op);
- break;
-
- default:
- gcc_unreachable ();
- }
-
- if (! pat)
- return 0;
-
- emit_insn (pat);
- return target;
-}
-
/* Subroutine of ix86_expand_args_builtin to take care of scalar unop
insns with vec_merge. */
if (d->code == fcode)
return ix86_expand_sse_pcmpistr (d, exp, target);
- for (i = 0, d = bdesc_multi_arg; i < ARRAY_SIZE (bdesc_multi_arg); i++, d++)
- if (d->code == fcode)
- return ix86_expand_multi_arg_builtin (d->icode, exp, target,
- (enum multi_arg_type)d->flag,
- d->comparison);
-
gcc_unreachable ();
}
emit_move_insn (operand0, res);
}
-
-\f
-/* Validate whether a SSE5 instruction is valid or not.
- OPERANDS is the array of operands.
- NUM is the number of operands.
- USES_OC0 is true if the instruction uses OC0 and provides 4 variants.
- NUM_MEMORY is the maximum number of memory operands to accept.
- when COMMUTATIVE is set, operand 1 and 2 can be swapped. */
-
-bool
-ix86_sse5_valid_op_p (rtx operands[], rtx insn ATTRIBUTE_UNUSED, int num,
- bool uses_oc0, int num_memory, bool commutative)
-{
- int mem_mask;
- int mem_count;
- int i;
-
- /* Count the number of memory arguments */
- mem_mask = 0;
- mem_count = 0;
- for (i = 0; i < num; i++)
- {
- enum machine_mode mode = GET_MODE (operands[i]);
- if (register_operand (operands[i], mode))
- ;
-
- else if (memory_operand (operands[i], mode))
- {
- mem_mask |= (1 << i);
- mem_count++;
- }
-
- else
- {
- rtx pattern = PATTERN (insn);
-
- /* allow 0 for pcmov */
- if (GET_CODE (pattern) != SET
- || GET_CODE (SET_SRC (pattern)) != IF_THEN_ELSE
- || i < 2
- || operands[i] != CONST0_RTX (mode))
- return false;
- }
- }
-
- /* Special case pmacsdq{l,h} where we allow the 3rd argument to be
- a memory operation. */
- if (num_memory < 0)
- {
- num_memory = -num_memory;
- if ((mem_mask & (1 << (num-1))) != 0)
- {
- mem_mask &= ~(1 << (num-1));
- mem_count--;
- }
- }
-
- /* If there were no memory operations, allow the insn */
- if (mem_mask == 0)
- return true;
-
- /* Do not allow the destination register to be a memory operand. */
- else if (mem_mask & (1 << 0))
- return false;
-
- /* If there are too many memory operations, disallow the instruction. While
- the hardware only allows 1 memory reference, before register allocation
- for some insns, we allow two memory operations sometimes in order to allow
- code like the following to be optimized:
-
- float fmadd (float *a, float *b, float *c) { return (*a * *b) + *c; }
-
- or similar cases that are vectorized into using the fmaddss
- instruction. */
- else if (mem_count > num_memory)
- return false;
-
- /* Don't allow more than one memory operation if not optimizing. */
- else if (mem_count > 1 && !optimize)
- return false;
-
- else if (num == 4 && mem_count == 1)
- {
- /* formats (destination is the first argument), example fmaddss:
- xmm1, xmm1, xmm2, xmm3/mem
- xmm1, xmm1, xmm2/mem, xmm3
- xmm1, xmm2, xmm3/mem, xmm1
- xmm1, xmm2/mem, xmm3, xmm1 */
- if (uses_oc0)
- return ((mem_mask == (1 << 1))
- || (mem_mask == (1 << 2))
- || (mem_mask == (1 << 3)));
-
- /* format, example pmacsdd:
- xmm1, xmm2, xmm3/mem, xmm1 */
- if (commutative)
- return (mem_mask == (1 << 2) || mem_mask == (1 << 1));
- else
- return (mem_mask == (1 << 2));
- }
-
- else if (num == 4 && num_memory == 2)
- {
- /* If there are two memory operations, we can load one of the memory ops
- into the destination register. This is for optimizing the
- multiply/add ops, which the combiner has optimized both the multiply
- and the add insns to have a memory operation. We have to be careful
- that the destination doesn't overlap with the inputs. */
- rtx op0 = operands[0];
-
- if (reg_mentioned_p (op0, operands[1])
- || reg_mentioned_p (op0, operands[2])
- || reg_mentioned_p (op0, operands[3]))
- return false;
-
- /* formats (destination is the first argument), example fmaddss:
- xmm1, xmm1, xmm2, xmm3/mem
- xmm1, xmm1, xmm2/mem, xmm3
- xmm1, xmm2, xmm3/mem, xmm1
- xmm1, xmm2/mem, xmm3, xmm1
-
- For the oc0 case, we will load either operands[1] or operands[3] into
- operands[0], so any combination of 2 memory operands is ok. */
- if (uses_oc0)
- return true;
-
- /* format, example pmacsdd:
- xmm1, xmm2, xmm3/mem, xmm1
-
- For the integer multiply/add instructions be more restrictive and
- require operands[2] and operands[3] to be the memory operands. */
- if (commutative)
- return (mem_mask == ((1 << 1) | (1 << 3)) || ((1 << 2) | (1 << 3)));
- else
- return (mem_mask == ((1 << 2) | (1 << 3)));
- }
-
- else if (num == 3 && num_memory == 1)
- {
- /* formats, example protb:
- xmm1, xmm2, xmm3/mem
- xmm1, xmm2/mem, xmm3 */
- if (uses_oc0)
- return ((mem_mask == (1 << 1)) || (mem_mask == (1 << 2)));
-
- /* format, example comeq:
- xmm1, xmm2, xmm3/mem */
- else
- return (mem_mask == (1 << 2));
- }
-
- else
- gcc_unreachable ();
-
- return false;
-}
-
-\f
-/* Fixup an SSE5 instruction that has 2 memory input references into a form the
- hardware will allow by using the destination register to load one of the
- memory operations. Presently this is used by the multiply/add routines to
- allow 2 memory references. */
-
-void
-ix86_expand_sse5_multiple_memory (rtx operands[],
- int num,
- enum machine_mode mode)
-{
- rtx op0 = operands[0];
- if (num != 4
- || memory_operand (op0, mode)
- || reg_mentioned_p (op0, operands[1])
- || reg_mentioned_p (op0, operands[2])
- || reg_mentioned_p (op0, operands[3]))
- gcc_unreachable ();
-
- /* For 2 memory operands, pick either operands[1] or operands[3] to move into
- the destination register. */
- if (memory_operand (operands[1], mode))
- {
- emit_move_insn (op0, operands[1]);
- operands[1] = op0;
- }
- else if (memory_operand (operands[3], mode))
- {
- emit_move_insn (op0, operands[3]);
- operands[3] = op0;
- }
- else
- gcc_unreachable ();
-
- return;
-}
-
\f
/* Table of valid machine attributes. */
static const struct attribute_spec ix86_attribute_table[] =
#define TARGET_AVX OPTION_ISA_AVX
#define TARGET_FMA OPTION_ISA_FMA
#define TARGET_SSE4A OPTION_ISA_SSE4A
-#define TARGET_SSE5 OPTION_ISA_SSE5
#define TARGET_ROUND OPTION_ISA_ROUND
#define TARGET_ABM OPTION_ISA_ABM
#define TARGET_POPCNT OPTION_ISA_POPCNT
#define TARGET_CMPXCHG16B OPTION_ISA_CX16
-/* SSE5 and SSE4.1 define the same round instructions */
-#define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1 | OPTION_MASK_ISA_SSE5)
+/* SSE4.1 define round instructions */
+#define OPTION_MASK_ISA_ROUND (OPTION_MASK_ISA_SSE4_1)
#define OPTION_ISA_ROUND ((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)
#include "config/vxworks-dummy.h"
%<mcpu=* \
%{mintel-syntax:-masm=intel \
%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \
+%{msse5:-mavx \
+%n'-msse5' was removed.\n} \
+%{mfused-madd:-mavx \
+%n'-mfused-madd' was removed.\n} \
%{mno-intel-syntax:-masm=att \
%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"
;; X -- don't print any sort of PIC '@' suffix for a symbol.
;; & -- print some in-use local-dynamic symbol name.
;; H -- print a memory address offset by 8; used for sse high-parts
-;; Y -- print condition for SSE5 com* instruction.
;; + -- print a branch hint as 'cs' or 'ds' prefix
;; ; -- print a semicolon (after prefixes due to bug in older gas).
(UNSPEC_PCMPESTR 144)
(UNSPEC_PCMPISTR 145)
- ;; For SSE5
- (UNSPEC_SSE5_INTRINSIC 150)
- (UNSPEC_SSE5_UNSIGNED_CMP 151)
- (UNSPEC_SSE5_TRUEFALSE 152)
- (UNSPEC_SSE5_PERMUTE 153)
- (UNSPEC_FRCZ 154)
- (UNSPEC_CVTPH2PS 155)
- (UNSPEC_CVTPS2PH 156)
-
; For AES support
(UNSPEC_AESENC 159)
(UNSPEC_AESENCLAST 160)
(COM_TRUE_P 5)
])
-;; Constants used in the SSE5 pperm instruction
-(define_constants
- [(PPERM_SRC 0x00) /* copy source */
- (PPERM_INVERT 0x20) /* invert source */
- (PPERM_REVERSE 0x40) /* bit reverse source */
- (PPERM_REV_INV 0x60) /* bit reverse & invert src */
- (PPERM_ZERO 0x80) /* all 0's */
- (PPERM_ONES 0xa0) /* all 1's */
- (PPERM_SIGN 0xc0) /* propagate sign bit */
- (PPERM_INV_SIGN 0xe0) /* invert & propagate sign */
- (PPERM_SRC1 0x00) /* use first source byte */
- (PPERM_SRC2 0x10) /* use second source byte */
- ])
-
;; Registers by name.
(define_constants
[(AX_REG 0)
]
(const_int 0)))
-;; There are also additional prefixes in 3DNOW, SSSE3 or SSE5.
+;; There are also additional prefixes in 3DNOW, SSSE3.
;; ssemuladd,sse4arg default to 0f24/0f25 and DREX byte,
;; sseiadd1,ssecvt1 to 0f7a with no DREX byte.
;; 3DNOW has 0f0f prefix, SSSE3 and SSE4_{1,2} 0f38/0f3a.
|| (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
"")
-;; SSE5 scalar multiply/add instructions are defined in sse.md.
-
\f
;; Divide instructions
(match_operator:MODEF 1 "sse_comparison_operator"
[(match_operand:MODEF 2 "register_operand" "0")
(match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
- "SSE_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
+ "SSE_FLOAT_MODE_P (<MODE>mode)"
"cmp%D1s<ssemodefsuffix>\t{%3, %0|%0, %3}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
(set_attr "mode" "<MODE>")])
-
-(define_insn "*sse5_setcc<mode>"
- [(set (match_operand:MODEF 0 "register_operand" "=x")
- (match_operator:MODEF 1 "sse5_comparison_float_operator"
- [(match_operand:MODEF 2 "register_operand" "x")
- (match_operand:MODEF 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE5"
- "com%Y1s<ssemodefsuffix>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "<MODE>")])
-
\f
;; Basic conditional jump instructions.
;; We ignore the overflow flag for signed branch instructions.
[(set_attr "type" "fcmov")
(set_attr "mode" "XF")])
-;; All moves in SSE5 pcmov instructions are 128 bits and hence we restrict
-;; the scalar versions to have only XMM registers as operands.
-
-;; SSE5 conditional move
-(define_insn "*sse5_pcmov_<mode>"
- [(set (match_operand:MODEF 0 "register_operand" "=x,x")
- (if_then_else:MODEF
- (match_operand:MODEF 1 "register_operand" "x,0")
- (match_operand:MODEF 2 "register_operand" "0,x")
- (match_operand:MODEF 3 "register_operand" "x,x")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "pcmov\t{%1, %3, %2, %0|%0, %2, %3, %1}"
- [(set_attr "type" "sse4arg")])
-
;; These versions of the min/max patterns are intentionally ignorant of
;; their behavior wrt -0.0 and NaN (via the commutative operand mark).
;; Since both the tree-level MAX_EXPR and the rtl-level SMAX operator
Target Report Mask(CLD) Save
Generate cld instruction in the function prologue.
-mno-fused-madd
-Target RejectNegative Report Mask(NO_FUSED_MADD) Undocumented Save
-
-mfused-madd
-Target Report InverseMask(NO_FUSED_MADD, FUSED_MADD) Save
-Enable automatic generation of fused floating point multiply-add instructions
-if the ISA supports such instructions. The -mfused-madd option is on by
-default.
-
;; ISA support
m32
Target Report Mask(ISA_SSE4A) Var(ix86_isa_flags) VarExists Save
Support MMX, SSE, SSE2, SSE3 and SSE4A built-in functions and code generation
-msse5
-Target Report Mask(ISA_SSE5) Var(ix86_isa_flags) VarExists Save
-Support SSE5 built-in functions and code generation
-
mabm
Target Report Mask(ISA_ABM) Var(ix86_isa_flags) VarExists Save
Support code generation of Advanced Bit Manipulation (ABM) instructions.
see the files COPYING3 and COPYING.RUNTIME respectively. If not, see
<http://www.gnu.org/licenses/>. */
-/* Common definition of the ROUND and PTEST intrinsics that are shared
- between SSE4.1 and SSE5. */
+/* Common definition of the ROUND and PTEST intrinsics, SSE4.1. */
#ifndef _MMINTRIN_COMMON_H_INCLUDED
#define _MMINTRIN_COMMON_H_INCLUDED
-#if !defined(__SSE5__) && !defined(__SSE4_1__)
-# error "SSE5 or SSE4.1 instruction set not enabled"
+#if !defined(__SSE4_1__)
+# error "SSE4.1 instruction set not enabled"
#else
/* Rounding mode macros. */
#define _mm_floor_ps(V) _mm_round_ps ((V), _MM_FROUND_FLOOR)
#define _mm_floor_ss(D, V) _mm_round_ss ((D), (V), _MM_FROUND_FLOOR)
-#endif /* __SSE5__/__SSE4_1__ */
+#endif /* __SSE4_1__ */
#endif /* _MMINTRIN_COMMON_H_INCLUDED */
(define_predicate "avx_comparison_float_operator"
(match_code "ne,eq,ge,gt,le,lt,unordered,ordered,uneq,unge,ungt,unle,unlt,ltgt"))
-;; Return 1 if OP is a comparison operator that can be issued by sse predicate
-;; generation instructions
-(define_predicate "sse5_comparison_float_operator"
- (and (match_test "TARGET_SSE5")
- (match_code "ne,eq,ge,gt,le,lt,unordered,ordered,uneq,unge,ungt,unle,unlt,ltgt")))
-
(define_predicate "ix86_comparison_int_operator"
(match_code "ne,eq,ge,gt,le,lt"))
;; Modes handled by integer vcond pattern
(define_mode_iterator SSEMODE124C8 [V16QI V8HI V4SI
- (V2DI "TARGET_SSE4_2 || TARGET_SSE5")])
+ (V2DI "TARGET_SSE4_2")])
;; Mapping from float mode to required SSE level
(define_mode_attr sse [(SF "sse") (DF "sse2") (V4SF "sse") (V2DF "sse2")])
;; Mapping from integer vector mode to mnemonic suffix
(define_mode_attr ssevecsize [(V16QI "b") (V8HI "w") (V4SI "d") (V2DI "q")])
-;; Mapping of the sse5 suffix
+;; Mapping of the avx suffix
(define_mode_attr ssemodesuffixf4 [(SF "ss") (DF "sd")
(V4SF "ps") (V2DF "pd")])
-(define_mode_attr ssemodesuffixf2s [(SF "ss") (DF "sd")
- (V4SF "ss") (V2DF "sd")])
-(define_mode_attr ssemodesuffixf2c [(V4SF "s") (V2DF "d")])
-;; Mapping of the max integer size for sse5 rotate immediate constraint
-(define_mode_attr sserotatemax [(V16QI "7") (V8HI "15") (V4SI "31") (V2DI "63")])
+(define_mode_attr ssemodesuffixf2c [(V4SF "s") (V2DF "d")])
;; Mapping of vector modes back to the scalar modes
(define_mode_attr ssescalarmode [(V4SF "SF") (V2DF "DF")
(match_operator:SSEMODEF4 3 "sse_comparison_operator"
[(match_operand:SSEMODEF4 1 "register_operand" "0")
(match_operand:SSEMODEF4 2 "nonimmediate_operand" "xm")]))]
- "(SSE_FLOAT_MODE_P (<MODE>mode) || SSE_VEC_FLOAT_MODE_P (<MODE>mode))
- && !TARGET_SSE5"
+ "(SSE_FLOAT_MODE_P (<MODE>mode) || SSE_VEC_FLOAT_MODE_P (<MODE>mode))"
"cmp%D3<ssemodesuffixf4>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")])
(match_dup 1)
(const_int 1)))]
- "SSE_VEC_FLOAT_MODE_P (<MODE>mode) && !TARGET_SSE5"
+ "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
"cmp%D3s<ssemodesuffixf2c>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
(set_attr "length_immediate" "1")
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
-;; SSE5 floating point multiply/accumulate instructions This includes the
-;; scalar version of the instructions as well as the vector
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; In order to match (*a * *b) + *c, particularly when vectorizing, allow
-;; combine to generate a multiply/add with two memory references. We then
-;; split this insn, into loading up the destination register with one of the
-;; memory operations. If we don't manage to split the insn, reload will
-;; generate the appropriate moves. The reason this is needed, is that combine
-;; has already folded one of the memory references into both the multiply and
-;; add insns, and it can't generate a new pseudo. I.e.:
-;; (set (reg1) (mem (addr1)))
-;; (set (reg2) (mult (reg1) (mem (addr2))))
-;; (set (reg3) (plus (reg2) (mem (addr3))))
-
-(define_insn "sse5_fmadd<mode>4"
- [(set (match_operand:SSEMODEF4 0 "register_operand" "=x,x,x,x")
- (plus:SSEMODEF4
- (mult:SSEMODEF4
- (match_operand:SSEMODEF4 1 "nonimmediate_operand" "%0,0,x,xm")
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,xm,xm,x"))
- (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x,0,0")))]
- "TARGET_SSE5 && TARGET_FUSED_MADD
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, true)"
- "fmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Split fmadd with two memory operands into a load and the fmadd.
-(define_split
- [(set (match_operand:SSEMODEF4 0 "register_operand" "")
- (plus:SSEMODEF4
- (mult:SSEMODEF4
- (match_operand:SSEMODEF4 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" ""))
- (match_operand:SSEMODEF4 3 "nonimmediate_operand" "")))]
- "TARGET_SSE5
- && !ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, true)
- && !reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])
- && !reg_mentioned_p (operands[0], operands[3])"
- [(const_int 0)]
-{
- ix86_expand_sse5_multiple_memory (operands, 4, <MODE>mode);
- emit_insn (gen_sse5_fmadd<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
-})
-
-;; For the scalar operations, use operand1 for the upper words that aren't
-;; modified, so restrict the forms that are generated.
-;; Scalar version of fmadd
-(define_insn "sse5_vmfmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (plus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0,0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE5 && TARGET_FUSED_MADD
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)"
- "fmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Floating multiply and subtract
-;; Allow two memory operands the same as fmadd
-(define_insn "sse5_fmsub<mode>4"
- [(set (match_operand:SSEMODEF4 0 "register_operand" "=x,x,x,x")
- (minus:SSEMODEF4
- (mult:SSEMODEF4
- (match_operand:SSEMODEF4 1 "nonimmediate_operand" "%0,0,x,xm")
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,xm,xm,x"))
- (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x,0,0")))]
- "TARGET_SSE5 && TARGET_FUSED_MADD
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, true)"
- "fmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Split fmsub with two memory operands into a load and the fmsub.
-(define_split
- [(set (match_operand:SSEMODEF4 0 "register_operand" "")
- (minus:SSEMODEF4
- (mult:SSEMODEF4
- (match_operand:SSEMODEF4 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" ""))
- (match_operand:SSEMODEF4 3 "nonimmediate_operand" "")))]
- "TARGET_SSE5
- && !ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, true)
- && !reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])
- && !reg_mentioned_p (operands[0], operands[3])"
- [(const_int 0)]
-{
- ix86_expand_sse5_multiple_memory (operands, 4, <MODE>mode);
- emit_insn (gen_sse5_fmsub<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
-})
-
-;; For the scalar operations, use operand1 for the upper words that aren't
-;; modified, so restrict the forms that are generated.
-;; Scalar version of fmsub
-(define_insn "sse5_vmfmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0,0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE5 && TARGET_FUSED_MADD
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "fmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Floating point negative multiply and add
-;; Rewrite (- (a * b) + c) into the canonical form: c - (a * b)
-;; Note operands are out of order to simplify call to ix86_sse5_valid_p
-;; Allow two memory operands to help in optimizing.
-(define_insn "sse5_fnmadd<mode>4"
- [(set (match_operand:SSEMODEF4 0 "register_operand" "=x,x,x,x")
- (minus:SSEMODEF4
- (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x,0,0")
- (mult:SSEMODEF4
- (match_operand:SSEMODEF4 1 "nonimmediate_operand" "%0,0,x,xm")
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,xm,xm,x"))))]
- "TARGET_SSE5 && TARGET_FUSED_MADD
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, true)"
- "fnmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Split fnmadd with two memory operands into a load and the fnmadd.
-(define_split
- [(set (match_operand:SSEMODEF4 0 "register_operand" "")
- (minus:SSEMODEF4
- (match_operand:SSEMODEF4 3 "nonimmediate_operand" "")
- (mult:SSEMODEF4
- (match_operand:SSEMODEF4 1 "nonimmediate_operand" "")
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" ""))))]
- "TARGET_SSE5
- && !ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, true)
- && !reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])
- && !reg_mentioned_p (operands[0], operands[3])"
- [(const_int 0)]
-{
- ix86_expand_sse5_multiple_memory (operands, 4, <MODE>mode);
- emit_insn (gen_sse5_fnmadd<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
-})
-
-;; For the scalar operations, use operand1 for the upper words that aren't
-;; modified, so restrict the forms that are generated.
-;; Scalar version of fnmadd
-(define_insn "sse5_vmfnmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0,0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm")))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE5 && TARGET_FUSED_MADD
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)"
- "fnmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Floating point negative multiply and subtract
-;; Rewrite (- (a * b) - c) into the canonical form: ((-a) * b) - c
-;; Allow 2 memory operands to help with optimization
-(define_insn "sse5_fnmsub<mode>4"
- [(set (match_operand:SSEMODEF4 0 "register_operand" "=x,x")
- (minus:SSEMODEF4
- (mult:SSEMODEF4
- (neg:SSEMODEF4
- (match_operand:SSEMODEF4 1 "nonimmediate_operand" "0,0"))
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" "x,xm"))
- (match_operand:SSEMODEF4 3 "nonimmediate_operand" "xm,x")))]
- "TARGET_SSE5 && TARGET_FUSED_MADD
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, false)"
- "fnmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Split fnmsub with two memory operands into a load and the fmsub.
-(define_split
- [(set (match_operand:SSEMODEF4 0 "register_operand" "")
- (minus:SSEMODEF4
- (mult:SSEMODEF4
- (neg:SSEMODEF4
- (match_operand:SSEMODEF4 1 "nonimmediate_operand" ""))
- (match_operand:SSEMODEF4 2 "nonimmediate_operand" ""))
- (match_operand:SSEMODEF4 3 "nonimmediate_operand" "")))]
- "TARGET_SSE5
- && !ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, false)
- && !reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])
- && !reg_mentioned_p (operands[0], operands[3])"
- [(const_int 0)]
-{
- ix86_expand_sse5_multiple_memory (operands, 4, <MODE>mode);
- emit_insn (gen_sse5_fnmsub<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
-})
-
-;; For the scalar operations, use operand1 for the upper words that aren't
-;; modified, so restrict the forms that are generated.
-;; Scalar version of fnmsub
-(define_insn "sse5_vmfnmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0,0"))
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_dup 1)
- (const_int 1)))]
- "TARGET_SSE5 && TARGET_FUSED_MADD
- && ix86_sse5_valid_op_p (operands, insn, 4, true, 2, false)"
- "fnmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; The same instructions using an UNSPEC to allow the intrinsic to be used
-;; even if the user used -mno-fused-madd
-;; Parallel instructions. During instruction generation, just default
-;; to registers, and let combine later build the appropriate instruction.
-(define_expand "sse5i_fmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (unspec:SSEMODEF2P
- [(plus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "")
- (match_operand:SSEMODEF2P 2 "register_operand" ""))
- (match_operand:SSEMODEF2P 3 "register_operand" ""))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5"
-{
- /* If we have -mfused-madd, emit the normal insn rather than the UNSPEC */
- if (TARGET_FUSED_MADD)
- {
- emit_insn (gen_sse5_fmadd<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
- }
-})
-
-(define_insn "*sse5i_fmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x,x,x")
- (unspec:SSEMODEF2P
- [(plus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0,0,x,xm")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm,xm,x"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x,0,0"))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)"
- "fmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-(define_expand "sse5i_fmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (unspec:SSEMODEF2P
- [(minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "")
- (match_operand:SSEMODEF2P 2 "register_operand" ""))
- (match_operand:SSEMODEF2P 3 "register_operand" ""))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5"
-{
- /* If we have -mfused-madd, emit the normal insn rather than the UNSPEC */
- if (TARGET_FUSED_MADD)
- {
- emit_insn (gen_sse5_fmsub<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
- }
-})
-
-(define_insn "*sse5i_fmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x,x,x")
- (unspec:SSEMODEF2P
- [(minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0,0,x,xm")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm,xm,x"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x,0,0"))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)"
- "fmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Rewrite (- (a * b) + c) into the canonical form: c - (a * b)
-;; Note operands are out of order to simplify call to ix86_sse5_valid_p
-(define_expand "sse5i_fnmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (unspec:SSEMODEF2P
- [(minus:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "register_operand" "")
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "")
- (match_operand:SSEMODEF2P 2 "register_operand" "")))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5"
-{
- /* If we have -mfused-madd, emit the normal insn rather than the UNSPEC */
- if (TARGET_FUSED_MADD)
- {
- emit_insn (gen_sse5_fnmadd<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
- }
-})
-
-(define_insn "*sse5i_fnmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x,x,x")
- (unspec:SSEMODEF2P
- [(minus:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x,0,0")
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0,0,x,xm")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm,xm,x")))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)"
- "fnmadd<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Rewrite (- (a * b) - c) into the canonical form: ((-a) * b) - c
-(define_expand "sse5i_fnmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (unspec:SSEMODEF2P
- [(minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" ""))
- (match_operand:SSEMODEF2P 2 "register_operand" ""))
- (match_operand:SSEMODEF2P 3 "register_operand" ""))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5"
-{
- /* If we have -mfused-madd, emit the normal insn rather than the UNSPEC */
- if (TARGET_FUSED_MADD)
- {
- emit_insn (gen_sse5_fnmsub<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
- }
-})
-
-(define_insn "*sse5i_fnmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x,x,x")
- (unspec:SSEMODEF2P
- [(minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0,0,x,xm"))
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm,xm,x"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x,0,0"))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "fnmsub<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<MODE>")])
-
-;; Scalar instructions
-(define_expand "sse5i_vmfmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (unspec:SSEMODEF2P
- [(vec_merge:SSEMODEF2P
- (plus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "")
- (match_operand:SSEMODEF2P 2 "register_operand" ""))
- (match_operand:SSEMODEF2P 3 "register_operand" ""))
- (match_dup 1)
- (const_int 0))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5"
-{
- /* If we have -mfused-madd, emit the normal insn rather than the UNSPEC */
- if (TARGET_FUSED_MADD)
- {
- emit_insn (gen_sse5_vmfmadd<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
- }
-})
-
-;; For the scalar operations, use operand1 for the upper words that aren't
-;; modified, so restrict the forms that are accepted.
-(define_insn "*sse5i_vmfmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (unspec:SSEMODEF2P
- [(vec_merge:SSEMODEF2P
- (plus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0,0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_dup 0)
- (const_int 0))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "fmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<ssescalarmode>")])
-
-(define_expand "sse5i_vmfmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (unspec:SSEMODEF2P
- [(vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "")
- (match_operand:SSEMODEF2P 2 "register_operand" ""))
- (match_operand:SSEMODEF2P 3 "register_operand" ""))
- (match_dup 0)
- (const_int 1))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5"
-{
- /* If we have -mfused-madd, emit the normal insn rather than the UNSPEC */
- if (TARGET_FUSED_MADD)
- {
- emit_insn (gen_sse5_vmfmsub<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
- }
-})
-
-(define_insn "*sse5i_vmfmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (unspec:SSEMODEF2P
- [(vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0,0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_dup 1)
- (const_int 1))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "fmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<ssescalarmode>")])
-
-;; Note operands are out of order to simplify call to ix86_sse5_valid_p
-(define_expand "sse5i_vmfnmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (unspec:SSEMODEF2P
- [(vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "register_operand" "")
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "")
- (match_operand:SSEMODEF2P 2 "register_operand" "")))
- (match_dup 1)
- (const_int 1))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5"
-{
- /* If we have -mfused-madd, emit the normal insn rather than the UNSPEC */
- if (TARGET_FUSED_MADD)
- {
- emit_insn (gen_sse5_vmfnmadd<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
- }
-})
-
-(define_insn "*sse5i_vmfnmadd<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (unspec:SSEMODEF2P
- [(vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x")
- (mult:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "nonimmediate_operand" "%0,0")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm")))
- (match_dup 1)
- (const_int 1))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, true)"
- "fnmadd<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<ssescalarmode>")])
-
-(define_expand "sse5i_vmfnmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (unspec:SSEMODEF2P
- [(vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" ""))
- (match_operand:SSEMODEF2P 2 "register_operand" ""))
- (match_operand:SSEMODEF2P 3 "register_operand" ""))
- (match_dup 1)
- (const_int 1))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5"
-{
- /* If we have -mfused-madd, emit the normal insn rather than the UNSPEC */
- if (TARGET_FUSED_MADD)
- {
- emit_insn (gen_sse5_vmfnmsub<mode>4 (operands[0], operands[1],
- operands[2], operands[3]));
- DONE;
- }
-})
-
-(define_insn "*sse5i_vmfnmsub<mode>4"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x")
- (unspec:SSEMODEF2P
- [(vec_merge:SSEMODEF2P
- (minus:SSEMODEF2P
- (mult:SSEMODEF2P
- (neg:SSEMODEF2P
- (match_operand:SSEMODEF2P 1 "register_operand" "0,0"))
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm"))
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm,x"))
- (match_dup 1)
- (const_int 1))]
- UNSPEC_SSE5_INTRINSIC))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "fnmsub<ssemodesuffixf2s>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "<ssescalarmode>")])
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
;; Parallel single-precision floating point conversion operations
;;
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
"&& 1"
[(const_int 0)]
{
- rtx t[12], op0, op[3];
+ rtx t[12];
int i;
- if (TARGET_SSE5)
- {
- /* On SSE5, we can take advantage of the pperm instruction to pack and
- unpack the bytes. Unpack data such that we've got a source byte in
- each low byte of each word. We don't care what goes into the high
- byte, so put 0 there. */
- for (i = 0; i < 6; ++i)
- t[i] = gen_reg_rtx (V8HImode);
-
- for (i = 0; i < 2; i++)
- {
- op[0] = t[i];
- op[1] = operands[i+1];
- ix86_expand_sse5_unpack (op, true, true); /* high bytes */
-
- op[0] = t[i+2];
- ix86_expand_sse5_unpack (op, true, false); /* low bytes */
- }
-
- /* Multiply words. */
- emit_insn (gen_mulv8hi3 (t[4], t[0], t[1])); /* high bytes */
- emit_insn (gen_mulv8hi3 (t[5], t[2], t[3])); /* low bytes */
-
- /* Pack the low byte of each word back into a single xmm */
- op[0] = operands[0];
- op[1] = t[5];
- op[2] = t[4];
- ix86_expand_sse5_pack (op);
- DONE;
- }
-
for (i = 0; i < 12; ++i)
t[i] = gen_reg_rtx (V16QImode);
emit_insn (gen_sse2_punpckhbw (t[10], t[9], t[8])); /* ........ACEGIKMO */
emit_insn (gen_sse2_punpcklbw (t[11], t[9], t[8])); /* ........BDFHJLNP */
- op0 = operands[0];
- emit_insn (gen_sse2_punpcklbw (op0, t[11], t[10])); /* ABCDEFGHIJKLMNOP */
+ emit_insn (gen_sse2_punpcklbw (operands[0], t[11], t[10])); /* ABCDEFGHIJKLMNOP */
DONE;
})
(match_operand:V4SI 2 "register_operand" "")))]
"TARGET_SSE2"
{
- if (TARGET_SSE4_1 || TARGET_SSE5)
+ if (TARGET_SSE4_1)
ix86_fixup_binary_operands_no_copy (MULT, V4SImode, operands);
})
(set_attr "prefix_extra" "1")
(set_attr "mode" "TI")])
-;; We don't have a straight 32-bit parallel multiply on SSE5, so fake it with a
-;; multiply/add. In general, we expect the define_split to occur before
-;; register allocation, so we have to handle the corner case where the target
-;; is the same as one of the inputs.
-(define_insn_and_split "*sse5_mulv4si3"
- [(set (match_operand:V4SI 0 "register_operand" "=&x")
- (mult:V4SI (match_operand:V4SI 1 "register_operand" "%x")
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE5"
- "#"
- "&& (reload_completed
- || (!reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])))"
- [(set (match_dup 0)
- (match_dup 3))
- (set (match_dup 0)
- (plus:V4SI (mult:V4SI (match_dup 1)
- (match_dup 2))
- (match_dup 0)))]
-{
- operands[3] = CONST0_RTX (V4SImode);
-}
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
(define_insn_and_split "*sse2_mulv4si3"
[(set (match_operand:V4SI 0 "register_operand" "")
(mult:V4SI (match_operand:V4SI 1 "register_operand" "")
(match_operand:V4SI 2 "register_operand" "")))]
- "TARGET_SSE2 && !TARGET_SSE4_1 && !TARGET_SSE5
+ "TARGET_SSE2 && !TARGET_SSE4_1
&& can_create_pseudo_p ()"
"#"
"&& 1"
rtx t1, t2, t3, t4, t5, t6, thirtytwo;
rtx op0, op1, op2;
- if (TARGET_SSE5)
- {
- /* op1: A,B,C,D, op2: E,F,G,H */
- op0 = operands[0];
- op1 = gen_lowpart (V4SImode, operands[1]);
- op2 = gen_lowpart (V4SImode, operands[2]);
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
- t3 = gen_reg_rtx (V4SImode);
- t4 = gen_reg_rtx (V2DImode);
- t5 = gen_reg_rtx (V2DImode);
-
- /* t1: B,A,D,C */
- emit_insn (gen_sse2_pshufd_1 (t1, op1,
- GEN_INT (1),
- GEN_INT (0),
- GEN_INT (3),
- GEN_INT (2)));
-
- /* t2: 0 */
- emit_move_insn (t2, CONST0_RTX (V4SImode));
-
- /* t3: (B*E),(A*F),(D*G),(C*H) */
- emit_insn (gen_sse5_pmacsdd (t3, t1, op2, t2));
-
- /* t4: (B*E)+(A*F), (D*G)+(C*H) */
- emit_insn (gen_sse5_phadddq (t4, t3));
-
- /* t5: ((B*E)+(A*F))<<32, ((D*G)+(C*H))<<32 */
- emit_insn (gen_ashlv2di3 (t5, t4, GEN_INT (32)));
-
- /* op0: (((B*E)+(A*F))<<32)+(B*F), (((D*G)+(C*H))<<32)+(D*H) */
- emit_insn (gen_sse5_pmacsdql (op0, op1, op2, t5));
- DONE;
- }
-
op0 = operands[0];
op1 = operands[1];
op2 = operands[2];
DONE;
})
-(define_expand "vec_widen_smult_hi_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
- "TARGET_SSE5"
-{
- rtx t1, t2;
-
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
-
- emit_insn (gen_sse2_pshufd_1 (t1, operands[1],
- GEN_INT (0),
- GEN_INT (2),
- GEN_INT (1),
- GEN_INT (3)));
- emit_insn (gen_sse2_pshufd_1 (t2, operands[2],
- GEN_INT (0),
- GEN_INT (2),
- GEN_INT (1),
- GEN_INT (3)));
- emit_insn (gen_sse5_mulv2div2di3_high (operands[0], t1, t2));
- DONE;
-})
-
-(define_expand "vec_widen_smult_lo_v4si"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V4SI 1 "register_operand" "")
- (match_operand:V4SI 2 "register_operand" "")]
- "TARGET_SSE5"
-{
- rtx t1, t2;
-
- t1 = gen_reg_rtx (V4SImode);
- t2 = gen_reg_rtx (V4SImode);
-
- emit_insn (gen_sse2_pshufd_1 (t1, operands[1],
- GEN_INT (0),
- GEN_INT (2),
- GEN_INT (1),
- GEN_INT (3)));
- emit_insn (gen_sse2_pshufd_1 (t2, operands[2],
- GEN_INT (0),
- GEN_INT (2),
- GEN_INT (1),
- GEN_INT (3)));
- emit_insn (gen_sse5_mulv2div2di3_low (operands[0], t1, t2));
- DONE;
- DONE;
-})
-
(define_expand "vec_widen_umult_hi_v4si"
[(match_operand:V2DI 0 "register_operand" "")
(match_operand:V4SI 1 "register_operand" "")
(eq:SSEMODE124
(match_operand:SSEMODE124 1 "nonimmediate_operand" "")
(match_operand:SSEMODE124 2 "nonimmediate_operand" "")))]
- "TARGET_SSE2 && !TARGET_SSE5"
+ "TARGET_SSE2"
"ix86_fixup_binary_operands_no_copy (EQ, <MODE>mode, operands);")
(define_insn "*avx_eq<mode>3"
(eq:SSEMODE124
(match_operand:SSEMODE124 1 "nonimmediate_operand" "%0")
(match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && !TARGET_SSE5
+ "TARGET_SSE2
&& ix86_binary_operator_ok (EQ, <MODE>mode, operands)"
"pcmpeq<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
(gt:SSEMODE124
(match_operand:SSEMODE124 1 "register_operand" "0")
(match_operand:SSEMODE124 2 "nonimmediate_operand" "xm")))]
- "TARGET_SSE2 && !TARGET_SSE5"
+ "TARGET_SSE2"
"pcmpgt<ssevecsize>\t{%2, %0|%0, %2}"
[(set_attr "type" "ssecmp")
(set_attr "prefix_data16" "1")
{
rtx op1, op2, h1, l1, h2, l2, h3, l3;
- if (TARGET_SSE5)
- {
- ix86_expand_sse5_pack (operands);
- DONE;
- }
-
op1 = gen_lowpart (V16QImode, operands[1]);
op2 = gen_lowpart (V16QImode, operands[2]);
h1 = gen_reg_rtx (V16QImode);
{
rtx op1, op2, h1, l1, h2, l2;
- if (TARGET_SSE5)
- {
- ix86_expand_sse5_pack (operands);
- DONE;
- }
-
op1 = gen_lowpart (V8HImode, operands[1]);
op2 = gen_lowpart (V8HImode, operands[2]);
h1 = gen_reg_rtx (V8HImode);
{
rtx op1, op2, h1, l1;
- if (TARGET_SSE5)
- {
- ix86_expand_sse5_pack (operands);
- DONE;
- }
-
op1 = gen_lowpart (V4SImode, operands[1]);
op2 = gen_lowpart (V4SImode, operands[2]);
h1 = gen_reg_rtx (V4SImode);
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, true, true);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, true, true);
else
ix86_expand_sse_unpack (operands, true, true);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, false, true);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, false, true);
else
ix86_expand_sse_unpack (operands, false, true);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, true, false);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, true, false);
else
ix86_expand_sse_unpack (operands, true, false);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, false, false);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, false, false);
else
ix86_expand_sse_unpack (operands, false, false);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, true, true);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, true, true);
else
ix86_expand_sse_unpack (operands, true, true);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, false, true);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, false, true);
else
ix86_expand_sse_unpack (operands, false, true);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, true, false);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, true, false);
else
ix86_expand_sse_unpack (operands, true, false);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, false, false);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, false, false);
else
ix86_expand_sse_unpack (operands, false, false);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, true, true);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, true, true);
else
ix86_expand_sse_unpack (operands, true, true);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, false, true);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, false, true);
else
ix86_expand_sse_unpack (operands, false, true);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, true, false);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, true, false);
else
ix86_expand_sse_unpack (operands, true, false);
DONE;
{
if (TARGET_SSE4_1)
ix86_expand_sse4_unpack (operands, false, false);
- else if (TARGET_SSE5)
- ix86_expand_sse5_unpack (operands, false, false);
else
ix86_expand_sse_unpack (operands, false, false);
DONE;
(set_attr "prefix" "maybe_vex")
(set_attr "mode" "TI")])
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; SSE5 instructions
-;;
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-;; SSE5 parallel integer multiply/add instructions.
-;; Note the instruction does not allow the value being added to be a memory
-;; operation. However by pretending via the nonimmediate_operand predicate
-;; that it does and splitting it later allows the following to be recognized:
-;; a[i] = b[i] * c[i] + d[i];
-(define_insn "sse5_pmacsww"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x,x")
- (plus:V8HI
- (mult:V8HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x,x,xm")
- (match_operand:V8HI 2 "nonimmediate_operand" "x,xm,x"))
- (match_operand:V8HI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 2, true)"
- "@
- pmacsww\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsww\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsww\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-;; Split pmacsww with two memory operands into a load and the pmacsww.
-(define_split
- [(set (match_operand:V8HI 0 "register_operand" "")
- (plus:V8HI
- (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "")
- (match_operand:V8HI 2 "nonimmediate_operand" ""))
- (match_operand:V8HI 3 "nonimmediate_operand" "")))]
- "TARGET_SSE5
- && !ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)
- && ix86_sse5_valid_op_p (operands, insn, 4, false, 2, true)
- && !reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])
- && !reg_mentioned_p (operands[0], operands[3])"
- [(const_int 0)]
-{
- ix86_expand_sse5_multiple_memory (operands, 4, V8HImode);
- emit_insn (gen_sse5_pmacsww (operands[0], operands[1], operands[2],
- operands[3]));
- DONE;
-})
-
-(define_insn "sse5_pmacssww"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x,x")
- (ss_plus:V8HI
- (mult:V8HI (match_operand:V8HI 1 "nonimmediate_operand" "%x,x,m")
- (match_operand:V8HI 2 "nonimmediate_operand" "x,m,x"))
- (match_operand:V8HI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmacssww\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacssww\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacssww\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-;; Note the instruction does not allow the value being added to be a memory
-;; operation. However by pretending via the nonimmediate_operand predicate
-;; that it does and splitting it later allows the following to be recognized:
-;; a[i] = b[i] * c[i] + d[i];
-(define_insn "sse5_pmacsdd"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
- (plus:V4SI
- (mult:V4SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x,x,m")
- (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x"))
- (match_operand:V4SI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 2, true)"
- "@
- pmacsdd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsdd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsdd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-;; Split pmacsdd with two memory operands into a load and the pmacsdd.
-(define_split
- [(set (match_operand:V4SI 0 "register_operand" "")
- (plus:V4SI
- (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "")
- (match_operand:V4SI 2 "nonimmediate_operand" ""))
- (match_operand:V4SI 3 "nonimmediate_operand" "")))]
- "TARGET_SSE5
- && !ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)
- && ix86_sse5_valid_op_p (operands, insn, 4, false, 2, true)
- && !reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])
- && !reg_mentioned_p (operands[0], operands[3])"
- [(const_int 0)]
-{
- ix86_expand_sse5_multiple_memory (operands, 4, V4SImode);
- emit_insn (gen_sse5_pmacsdd (operands[0], operands[1], operands[2],
- operands[3]));
- DONE;
-})
-
-(define_insn "sse5_pmacssdd"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
- (ss_plus:V4SI
- (mult:V4SI (match_operand:V4SI 1 "nonimmediate_operand" "%x,x,m")
- (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x"))
- (match_operand:V4SI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmacssdd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacssdd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacssdd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pmacssdql"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x,x")
- (ss_plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 1)
- (const_int 3)])))
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 1)
- (const_int 3)])))
- (match_operand:V2DI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmacssdql\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacssdql\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacssdql\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pmacssdqh"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x,x")
- (ss_plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 0)
- (const_int 2)]))))
- (match_operand:V2DI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmacssdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacssdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacssdqh\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pmacsdql"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x,x")
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 1)
- (const_int 3)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 1)
- (const_int 3)]))))
- (match_operand:V2DI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmacsdql\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsdql\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsdql\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn_and_split "*sse5_pmacsdql_mem"
- [(set (match_operand:V2DI 0 "register_operand" "=&x,&x,&x")
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 1)
- (const_int 3)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 1)
- (const_int 3)]))))
- (match_operand:V2DI 3 "memory_operand" "m,m,m")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, -1, true)"
- "#"
- "&& (reload_completed
- || (!reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])))"
- [(set (match_dup 0)
- (match_dup 3))
- (set (match_dup 0)
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)]))))
- (match_dup 0)))])
-
-;; We don't have a straight 32-bit parallel multiply and extend on SSE5, so
-;; fake it with a multiply/add. In general, we expect the define_split to
-;; occur before register allocation, so we have to handle the corner case where
-;; the target is the same as operands 1/2
-(define_insn_and_split "sse5_mulv2div2di3_low"
- [(set (match_operand:V2DI 0 "register_operand" "=&x")
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 1)
- (const_int 3)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 1)
- (const_int 3)])))))]
- "TARGET_SSE5"
- "#"
- "&& (reload_completed
- || (!reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])))"
- [(set (match_dup 0)
- (match_dup 3))
- (set (match_dup 0)
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)]))))
- (match_dup 0)))]
-{
- operands[3] = CONST0_RTX (V2DImode);
-}
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pmacsdqh"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x,x")
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 0)
- (const_int 2)]))))
- (match_operand:V2DI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmacsdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsdqh\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsdqh\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn_and_split "*sse5_pmacsdqh_mem"
- [(set (match_operand:V2DI 0 "register_operand" "=&x,&x,&x")
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 0)
- (const_int 2)]))))
- (match_operand:V2DI 3 "memory_operand" "m,m,m")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, -1, true)"
- "#"
- "&& (reload_completed
- || (!reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])))"
- [(set (match_dup 0)
- (match_dup 3))
- (set (match_dup 0)
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 1)
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 2)
- (parallel [(const_int 0)
- (const_int 2)]))))
- (match_dup 0)))])
-
-;; We don't have a straight 32-bit parallel multiply and extend on SSE5, so
-;; fake it with a multiply/add. In general, we expect the define_split to
-;; occur before register allocation, so we have to handle the corner case where
-;; the target is the same as either operands[1] or operands[2]
-(define_insn_and_split "sse5_mulv2div2di3_high"
- [(set (match_operand:V2DI 0 "register_operand" "=&x")
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "%x")
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 2 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)])))))]
- "TARGET_SSE5"
- "#"
- "&& (reload_completed
- || (!reg_mentioned_p (operands[0], operands[1])
- && !reg_mentioned_p (operands[0], operands[2])))"
- [(set (match_dup 0)
- (match_dup 3))
- (set (match_dup 0)
- (plus:V2DI
- (mult:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 1)
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 2)
- (parallel [(const_int 0)
- (const_int 2)]))))
- (match_dup 0)))]
-{
- operands[3] = CONST0_RTX (V2DImode);
-}
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-;; SSE5 parallel integer multiply/add instructions for the intrinisics
-(define_insn "sse5_pmacsswd"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
- (ss_plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))
- (match_operand:V4SI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmacsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacsswd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pmacswd"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)]))))
- (match_operand:V4SI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmacswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmacswd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pmadcsswd"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
- (ss_plus:V4SI
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))
- (match_operand:V4SI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmadcsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmadcsswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmadcsswd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pmadcswd"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x,x")
- (plus:V4SI
- (plus:V4SI
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "%x,x,m")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 2 "nonimmediate_operand" "x,m,x")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)]))))
- (mult:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 2)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))
- (match_operand:V4SI 3 "register_operand" "0,0,0")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, false, 1, true)"
- "@
- pmadcswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmadcswd\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pmadcswd\t{%3, %1, %2, %0|%0, %2, %1, %3}"
- [(set_attr "type" "ssemuladd")
- (set_attr "mode" "TI")])
-
-;; SSE5 parallel XMM conditional moves
-(define_insn "sse5_pcmov_<mode>"
- [(set (match_operand:SSEMODE 0 "register_operand" "=x,x,x,x")
- (if_then_else:SSEMODE
- (match_operand:SSEMODE 3 "nonimmediate_operand" "0,0,xm,x")
- (match_operand:SSEMODE 1 "vector_move_operand" "x,xm,0,0")
- (match_operand:SSEMODE 2 "vector_move_operand" "xm,x,x,xm")))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "@
- pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}
- pcmov\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")])
-
-;; SSE5 horizontal add/subtract instructions
-(define_insn "sse5_phaddbw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (plus:V8HI
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))))]
- "TARGET_SSE5"
- "phaddbw\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phaddbd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (plus:V4SI
- (sign_extend:V4SI
- (vec_select:V4QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)
- (const_int 8)
- (const_int 12)])))
- (sign_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)
- (const_int 9)
- (const_int 13)]))))
- (plus:V4SI
- (sign_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)
- (const_int 10)
- (const_int 14)])))
- (sign_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)
- (const_int 11)
- (const_int 15)]))))))]
- "TARGET_SSE5"
- "phaddbd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phaddbq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (plus:V2DI
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)]))))
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)])))))
- (plus:V2DI
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 8)
- (const_int 12)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 9)
- (const_int 13)]))))
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 10)
- (const_int 14)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 11)
- (const_int 15)])))))))]
- "TARGET_SSE5"
- "phaddbq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phaddwd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))]
- "TARGET_SSE5"
- "phaddwd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phaddwq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)])))
- (sign_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)]))))
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)])))
- (sign_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)]))))))]
- "TARGET_SSE5"
- "phaddwq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phadddq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))))]
- "TARGET_SSE5"
- "phadddq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phaddubw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (plus:V8HI
- (zero_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
- (zero_extend:V8HI
- (vec_select:V8QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))))]
- "TARGET_SSE5"
- "phaddubw\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phaddubd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (plus:V4SI
- (zero_extend:V4SI
- (vec_select:V4QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)
- (const_int 8)
- (const_int 12)])))
- (zero_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)
- (const_int 9)
- (const_int 13)]))))
- (plus:V4SI
- (zero_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)
- (const_int 10)
- (const_int 14)])))
- (zero_extend:V4SI
- (vec_select:V4QI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)
- (const_int 11)
- (const_int 15)]))))))]
- "TARGET_SSE5"
- "phaddubd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phaddubq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (plus:V2DI
- (plus:V2DI
- (zero_extend:V2DI
- (vec_select:V2QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)]))))
- (plus:V2DI
- (zero_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)])))
- (zero_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)])))))
- (plus:V2DI
- (plus:V2DI
- (zero_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 8)
- (const_int 12)])))
- (sign_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 9)
- (const_int 13)]))))
- (plus:V2DI
- (zero_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 10)
- (const_int 14)])))
- (zero_extend:V2DI
- (vec_select:V2QI
- (match_dup 1)
- (parallel [(const_int 11)
- (const_int 15)])))))))]
- "TARGET_SSE5"
- "phaddubq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phadduwd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (plus:V4SI
- (zero_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (zero_extend:V4SI
- (vec_select:V4HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))]
- "TARGET_SSE5"
- "phadduwd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phadduwq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (plus:V2DI
- (zero_extend:V2DI
- (vec_select:V2HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 4)])))
- (zero_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 5)]))))
- (plus:V2DI
- (zero_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 2)
- (const_int 6)])))
- (zero_extend:V2DI
- (vec_select:V2HI
- (match_dup 1)
- (parallel [(const_int 3)
- (const_int 7)]))))))]
- "TARGET_SSE5"
- "phadduwq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phaddudq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (plus:V2DI
- (zero_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)])))
- (zero_extend:V2DI
- (vec_select:V2SI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))))]
- "TARGET_SSE5"
- "phaddudq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phsubbw"
- [(set (match_operand:V8HI 0 "register_operand" "=x")
- (minus:V8HI
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)
- (const_int 8)
- (const_int 10)
- (const_int 12)
- (const_int 14)])))
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)
- (const_int 9)
- (const_int 11)
- (const_int 13)
- (const_int 15)])))))]
- "TARGET_SSE5"
- "phsubbw\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phsubwd"
- [(set (match_operand:V4SI 0 "register_operand" "=x")
- (minus:V4SI
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)
- (const_int 4)
- (const_int 6)])))
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)
- (const_int 5)
- (const_int 7)])))))]
- "TARGET_SSE5"
- "phsubwd\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-(define_insn "sse5_phsubdq"
- [(set (match_operand:V2DI 0 "register_operand" "=x")
- (minus:V2DI
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "xm")
- (parallel [(const_int 0)
- (const_int 2)])))
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_dup 1)
- (parallel [(const_int 1)
- (const_int 3)])))))]
- "TARGET_SSE5"
- "phsubdq\t{%1, %0|%0, %1}"
- [(set_attr "type" "sseiadd1")])
-
-;; SSE5 permute instructions
-(define_insn "sse5_pperm"
- [(set (match_operand:V16QI 0 "register_operand" "=x,x,x,x")
- (unspec:V16QI
- [(match_operand:V16QI 1 "nonimmediate_operand" "0,0,x,xm")
- (match_operand:V16QI 2 "nonimmediate_operand" "x,xm,xm,x")
- (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,0,0")]
- UNSPEC_SSE5_PERMUTE))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "pperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "mode" "TI")])
-
-;; The following are for the various unpack insns which doesn't need the first
-;; source operand, so we can just use the output operand for the first operand.
-;; This allows either of the other two operands to be a memory operand. We
-;; can't just use the first operand as an argument to the normal pperm because
-;; then an output only argument, suddenly becomes an input operand.
-(define_insn "sse5_pperm_zero_v16qi_v8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x")
- (zero_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm,x")
- (match_operand 2 "" "")))) ;; parallel with const_int's
- (use (match_operand:V16QI 3 "nonimmediate_operand" "x,xm"))]
- "TARGET_SSE5
- && (register_operand (operands[1], V16QImode)
- || register_operand (operands[2], V16QImode))"
- "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pperm_sign_v16qi_v8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x")
- (sign_extend:V8HI
- (vec_select:V8QI
- (match_operand:V16QI 1 "nonimmediate_operand" "xm,x")
- (match_operand 2 "" "")))) ;; parallel with const_int's
- (use (match_operand:V16QI 3 "nonimmediate_operand" "x,xm"))]
- "TARGET_SSE5
- && (register_operand (operands[1], V16QImode)
- || register_operand (operands[2], V16QImode))"
- "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pperm_zero_v8hi_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x")
- (zero_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm,x")
- (match_operand 2 "" "")))) ;; parallel with const_int's
- (use (match_operand:V16QI 3 "nonimmediate_operand" "x,xm"))]
- "TARGET_SSE5
- && (register_operand (operands[1], V8HImode)
- || register_operand (operands[2], V16QImode))"
- "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pperm_sign_v8hi_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x")
- (sign_extend:V4SI
- (vec_select:V4HI
- (match_operand:V8HI 1 "nonimmediate_operand" "xm,x")
- (match_operand 2 "" "")))) ;; parallel with const_int's
- (use (match_operand:V16QI 3 "nonimmediate_operand" "x,xm"))]
- "TARGET_SSE5
- && (register_operand (operands[1], V8HImode)
- || register_operand (operands[2], V16QImode))"
- "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pperm_zero_v4si_v2di"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x")
- (zero_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "xm,x")
- (match_operand 2 "" "")))) ;; parallel with const_int's
- (use (match_operand:V16QI 3 "nonimmediate_operand" "x,xm"))]
- "TARGET_SSE5
- && (register_operand (operands[1], V4SImode)
- || register_operand (operands[2], V16QImode))"
- "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pperm_sign_v4si_v2di"
- [(set (match_operand:V2DI 0 "register_operand" "=x,x")
- (sign_extend:V2DI
- (vec_select:V2SI
- (match_operand:V4SI 1 "nonimmediate_operand" "xm,x")
- (match_operand 2 "" "")))) ;; parallel with const_int's
- (use (match_operand:V16QI 3 "nonimmediate_operand" "x,xm"))]
- "TARGET_SSE5
- && (register_operand (operands[1], V4SImode)
- || register_operand (operands[2], V16QImode))"
- "pperm\t{%3, %1, %0, %0|%0, %0, %1, %3}"
- [(set_attr "type" "sseadd")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-;; SSE5 pack instructions that combine two vectors into a smaller vector
-(define_insn "sse5_pperm_pack_v2di_v4si"
- [(set (match_operand:V4SI 0 "register_operand" "=x,x,x,x")
- (vec_concat:V4SI
- (truncate:V2SI
- (match_operand:V2DI 1 "nonimmediate_operand" "0,0,x,xm"))
- (truncate:V2SI
- (match_operand:V2DI 2 "nonimmediate_operand" "x,xm,xm,x"))))
- (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,0,0"))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "pperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pperm_pack_v4si_v8hi"
- [(set (match_operand:V8HI 0 "register_operand" "=x,x,x,x")
- (vec_concat:V8HI
- (truncate:V4HI
- (match_operand:V4SI 1 "nonimmediate_operand" "0,0,x,xm"))
- (truncate:V4HI
- (match_operand:V4SI 2 "nonimmediate_operand" "x,xm,xm,x"))))
- (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,0,0"))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "pperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_pperm_pack_v8hi_v16qi"
- [(set (match_operand:V16QI 0 "register_operand" "=x,x,x,x")
- (vec_concat:V16QI
- (truncate:V8QI
- (match_operand:V8HI 1 "nonimmediate_operand" "0,0,x,xm"))
- (truncate:V8QI
- (match_operand:V8HI 2 "nonimmediate_operand" "x,xm,xm,x"))))
- (use (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,0,0"))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "pperm\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "mode" "TI")])
-
-;; Floating point permutation (permps, permpd)
-(define_insn "sse5_perm<mode>"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x,x,x,x")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "0,0,x,xm")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "x,xm,xm,x")
- (match_operand:V16QI 3 "nonimmediate_operand" "xm,x,0,0")]
- UNSPEC_SSE5_PERMUTE))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 4, true, 1, false)"
- "perm<ssemodesuffixf4>\t{%3, %2, %1, %0|%0, %1, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "mode" "<MODE>")])
-
-;; SSE5 packed rotate instructions
-(define_expand "rotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "")
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand")))]
- "TARGET_SSE5"
-{
- /* If we were given a scalar, convert it to parallel */
- if (! const_0_to_<sserotatemax>_operand (operands[2], SImode))
- {
- rtvec vs = rtvec_alloc (<ssescalarnum>);
- rtx par = gen_rtx_PARALLEL (<MODE>mode, vs);
- rtx reg = gen_reg_rtx (<MODE>mode);
- rtx op2 = operands[2];
- int i;
-
- if (GET_MODE (op2) != <ssescalarmode>mode)
- {
- op2 = gen_reg_rtx (<ssescalarmode>mode);
- convert_move (op2, operands[2], false);
- }
-
- for (i = 0; i < <ssescalarnum>; i++)
- RTVEC_ELT (vs, i) = op2;
-
- emit_insn (gen_vec_init<mode> (reg, par));
- emit_insn (gen_sse5_vrotl<mode>3 (operands[0], operands[1], reg));
- DONE;
- }
-})
-
-(define_expand "rotr<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "")
- (rotatert:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "")
- (match_operand:SI 2 "general_operand")))]
- "TARGET_SSE5"
-{
- /* If we were given a scalar, convert it to parallel */
- if (! const_0_to_<sserotatemax>_operand (operands[2], SImode))
- {
- rtvec vs = rtvec_alloc (<ssescalarnum>);
- rtx par = gen_rtx_PARALLEL (<MODE>mode, vs);
- rtx neg = gen_reg_rtx (<MODE>mode);
- rtx reg = gen_reg_rtx (<MODE>mode);
- rtx op2 = operands[2];
- int i;
-
- if (GET_MODE (op2) != <ssescalarmode>mode)
- {
- op2 = gen_reg_rtx (<ssescalarmode>mode);
- convert_move (op2, operands[2], false);
- }
-
- for (i = 0; i < <ssescalarnum>; i++)
- RTVEC_ELT (vs, i) = op2;
-
- emit_insn (gen_vec_init<mode> (reg, par));
- emit_insn (gen_neg<mode>2 (neg, reg));
- emit_insn (gen_sse5_vrotl<mode>3 (operands[0], operands[1], neg));
- DONE;
- }
-})
-
-(define_insn "sse5_rotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
- (match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
- "TARGET_SSE5"
- "prot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_rotr<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (rotatert:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "xm")
- (match_operand:SI 2 "const_0_to_<sserotatemax>_operand" "n")))]
- "TARGET_SSE5"
-{
- operands[3] = GEN_INT ((<ssescalarnum> * 8) - INTVAL (operands[2]));
- return \"prot<ssevecsize>\t{%3, %1, %0|%0, %1, %3}\";
-}
- [(set_attr "type" "sseishft")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_expand "vrotr<mode>3"
- [(match_operand:SSEMODE1248 0 "register_operand" "")
- (match_operand:SSEMODE1248 1 "register_operand" "")
- (match_operand:SSEMODE1248 2 "register_operand" "")]
- "TARGET_SSE5"
-{
- rtx reg = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_neg<mode>2 (reg, operands[2]));
- emit_insn (gen_sse5_vrotl<mode>3 (operands[0], operands[1], reg));
- DONE;
-})
-
-(define_expand "vrotl<mode>3"
- [(match_operand:SSEMODE1248 0 "register_operand" "")
- (match_operand:SSEMODE1248 1 "register_operand" "")
- (match_operand:SSEMODE1248 2 "register_operand" "")]
- "TARGET_SSE5"
-{
- emit_insn (gen_sse5_vrotl<mode>3 (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_insn "sse5_vrotl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm,x")
- (const_int 0))
- (rotate:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "x,xm")
- (match_dup 2))
- (rotatert:SSEMODE1248
- (match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
- "prot<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-;; SSE5 packed shift instructions.
-;; FIXME: add V2DI back in
-(define_expand "vlshr<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
- "TARGET_SSE5"
-{
- rtx neg = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_neg<mode>2 (neg, operands[2]));
- emit_insn (gen_sse5_lshl<mode>3 (operands[0], operands[1], neg));
- DONE;
-})
-
-(define_expand "vashr<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
- "TARGET_SSE5"
-{
- rtx neg = gen_reg_rtx (<MODE>mode);
- emit_insn (gen_neg<mode>2 (neg, operands[2]));
- emit_insn (gen_sse5_ashl<mode>3 (operands[0], operands[1], neg));
- DONE;
-})
-
-(define_expand "vashl<mode>3"
- [(match_operand:SSEMODE124 0 "register_operand" "")
- (match_operand:SSEMODE124 1 "register_operand" "")
- (match_operand:SSEMODE124 2 "register_operand" "")]
- "TARGET_SSE5"
-{
- emit_insn (gen_sse5_ashl<mode>3 (operands[0], operands[1], operands[2]));
- DONE;
-})
-
-(define_insn "sse5_ashl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm,x")
- (const_int 0))
- (ashift:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "x,xm")
- (match_dup 2))
- (ashiftrt:SSEMODE1248
- (match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
- "psha<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_lshl<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x,x")
- (if_then_else:SSEMODE1248
- (ge:SSEMODE1248
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm,x")
- (const_int 0))
- (ashift:SSEMODE1248
- (match_operand:SSEMODE1248 1 "nonimmediate_operand" "x,xm")
- (match_dup 2))
- (lshiftrt:SSEMODE1248
- (match_dup 1)
- (neg:SSEMODE1248 (match_dup 2)))))]
- "TARGET_SSE5 && ix86_sse5_valid_op_p (operands, insn, 3, true, 1, false)"
- "pshl<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- [(set_attr "type" "sseishft")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "mode" "TI")])
-
-;; SSE2 doesn't have some shift varients, so define versions for SSE5
-(define_expand "ashlv16qi3"
- [(match_operand:V16QI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")]
- "TARGET_SSE5"
-{
- rtvec vs = rtvec_alloc (16);
- rtx par = gen_rtx_PARALLEL (V16QImode, vs);
- rtx reg = gen_reg_rtx (V16QImode);
- int i;
- for (i = 0; i < 16; i++)
- RTVEC_ELT (vs, i) = operands[2];
-
- emit_insn (gen_vec_initv16qi (reg, par));
- emit_insn (gen_sse5_ashlv16qi3 (operands[0], operands[1], reg));
- DONE;
-})
-
-(define_expand "lshlv16qi3"
- [(match_operand:V16QI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")]
- "TARGET_SSE5"
-{
- rtvec vs = rtvec_alloc (16);
- rtx par = gen_rtx_PARALLEL (V16QImode, vs);
- rtx reg = gen_reg_rtx (V16QImode);
- int i;
- for (i = 0; i < 16; i++)
- RTVEC_ELT (vs, i) = operands[2];
-
- emit_insn (gen_vec_initv16qi (reg, par));
- emit_insn (gen_sse5_lshlv16qi3 (operands[0], operands[1], reg));
- DONE;
-})
-
-(define_expand "ashrv16qi3"
- [(match_operand:V16QI 0 "register_operand" "")
- (match_operand:V16QI 1 "register_operand" "")
- (match_operand:SI 2 "nonmemory_operand" "")]
- "TARGET_SSE5"
-{
- rtvec vs = rtvec_alloc (16);
- rtx par = gen_rtx_PARALLEL (V16QImode, vs);
- rtx reg = gen_reg_rtx (V16QImode);
- int i;
- rtx ele = ((CONST_INT_P (operands[2]))
- ? GEN_INT (- INTVAL (operands[2]))
- : operands[2]);
-
- for (i = 0; i < 16; i++)
- RTVEC_ELT (vs, i) = ele;
-
- emit_insn (gen_vec_initv16qi (reg, par));
-
- if (!CONST_INT_P (operands[2]))
- {
- rtx neg = gen_reg_rtx (V16QImode);
- emit_insn (gen_negv16qi2 (neg, reg));
- emit_insn (gen_sse5_ashlv16qi3 (operands[0], operands[1], neg));
- }
- else
- emit_insn (gen_sse5_ashlv16qi3 (operands[0], operands[1], reg));
-
- DONE;
-})
-
-(define_expand "ashrv2di3"
- [(match_operand:V2DI 0 "register_operand" "")
- (match_operand:V2DI 1 "register_operand" "")
- (match_operand:DI 2 "nonmemory_operand" "")]
- "TARGET_SSE5"
-{
- rtvec vs = rtvec_alloc (2);
- rtx par = gen_rtx_PARALLEL (V2DImode, vs);
- rtx reg = gen_reg_rtx (V2DImode);
- rtx ele;
-
- if (CONST_INT_P (operands[2]))
- ele = GEN_INT (- INTVAL (operands[2]));
- else if (GET_MODE (operands[2]) != DImode)
- {
- rtx move = gen_reg_rtx (DImode);
- ele = gen_reg_rtx (DImode);
- convert_move (move, operands[2], false);
- emit_insn (gen_negdi2 (ele, move));
- }
- else
- {
- ele = gen_reg_rtx (DImode);
- emit_insn (gen_negdi2 (ele, operands[2]));
- }
-
- RTVEC_ELT (vs, 0) = ele;
- RTVEC_ELT (vs, 1) = ele;
- emit_insn (gen_vec_initv2di (reg, par));
- emit_insn (gen_sse5_ashlv2di3 (operands[0], operands[1], reg));
- DONE;
-})
-
-;; SSE5 FRCZ support
-;; parallel insns
-(define_insn "sse5_frcz<mode>2"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "nonimmediate_operand" "xm")]
- UNSPEC_FRCZ))]
- "TARGET_SSE5"
- "frcz<ssemodesuffixf4>\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt1")
- (set_attr "mode" "<MODE>")])
-
-;; scalar insns
-(define_insn "sse5_vmfrcz<mode>2"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")]
- UNSPEC_FRCZ)
- (match_operand:SSEMODEF2P 1 "register_operand" "0")
- (const_int 1)))]
- "TARGET_SSE5"
- "frcz<ssemodesuffixf2s>\t{%2, %0|%0, %2}"
- [(set_attr "type" "ssecvt1")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "sse5_cvtph2ps"
- [(set (match_operand:V4SF 0 "register_operand" "=x")
- (unspec:V4SF [(match_operand:V4HI 1 "nonimmediate_operand" "xm")]
- UNSPEC_CVTPH2PS))]
- "TARGET_SSE5"
- "cvtph2ps\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-(define_insn "sse5_cvtps2ph"
- [(set (match_operand:V4HI 0 "nonimmediate_operand" "=xm")
- (unspec:V4HI [(match_operand:V4SF 1 "register_operand" "x")]
- UNSPEC_CVTPS2PH))]
- "TARGET_SSE5"
- "cvtps2ph\t{%1, %0|%0, %1}"
- [(set_attr "type" "ssecvt")
- (set_attr "mode" "V4SF")])
-
-;; Scalar versions of the com instructions that use vector types that are
-;; called from the intrinsics. Unlike the the other s{s,d} instructions, the
-;; com instructions fill in 0's in the upper bits instead of leaving them
-;; unmodified, so we use const_vector of 0 instead of match_dup.
-(define_expand "sse5_vmmaskcmp<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "")
- (vec_merge:SSEMODEF2P
- (match_operator:SSEMODEF2P 1 "sse5_comparison_float_operator"
- [(match_operand:SSEMODEF2P 2 "register_operand" "")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "")])
- (match_dup 4)
- (const_int 1)))]
- "TARGET_SSE5"
-{
- operands[4] = CONST0_RTX (<MODE>mode);
-})
-
-(define_insn "*sse5_vmmaskcmp<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (vec_merge:SSEMODEF2P
- (match_operator:SSEMODEF2P 1 "sse5_comparison_float_operator"
- [(match_operand:SSEMODEF2P 2 "register_operand" "x")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm")])
- (match_operand:SSEMODEF2P 4 "")
- (const_int 1)))]
- "TARGET_SSE5"
- "com%Y1<ssemodesuffixf2s>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "<ssescalarmode>")])
-
-;; We don't have a comparison operator that always returns true/false, so
-;; handle comfalse and comtrue specially.
-(define_insn "sse5_com_tf<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (unspec:SSEMODEF2P
- [(match_operand:SSEMODEF2P 1 "register_operand" "x")
- (match_operand:SSEMODEF2P 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_int_operand" "n")]
- UNSPEC_SSE5_TRUEFALSE))]
- "TARGET_SSE5"
-{
- const char *ret = NULL;
-
- switch (INTVAL (operands[3]))
- {
- case COM_FALSE_S:
- ret = \"comfalses<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}\";
- break;
-
- case COM_FALSE_P:
- ret = \"comfalsep<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}\";
- break;
-
- case COM_TRUE_S:
- ret = \"comfalses<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}\";
- break;
-
- case COM_TRUE_P:
- ret = \"comfalsep<ssemodesuffixf2c>\t{%2, %1, %0|%0, %1, %2}\";
- break;
-
- default:
- gcc_unreachable ();
- }
-
- return ret;
-}
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "sse5_maskcmp<mode>3"
- [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
- (match_operator:SSEMODEF2P 1 "sse5_comparison_float_operator"
- [(match_operand:SSEMODEF2P 2 "register_operand" "x")
- (match_operand:SSEMODEF2P 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE5"
- "com%Y1<ssemodesuffixf4>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "<MODE>")])
-
-(define_insn "sse5_maskcmp<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (match_operator:SSEMODE1248 1 "ix86_comparison_int_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE5"
- "pcom%Y1<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "sse4arg")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-(define_insn "sse5_maskcmp_uns<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")]))]
- "TARGET_SSE5"
- "pcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_rep" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-;; Version of pcom*u* that is called from the intrinsics that allows pcomequ*
-;; and pcomneu* not to be converted to the signed ones in case somebody needs
-;; the exact instruction generated for the intrinsic.
-(define_insn "sse5_maskcmp_uns2<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (unspec:SSEMODE1248
- [(match_operator:SSEMODE1248 1 "ix86_comparison_uns_operator"
- [(match_operand:SSEMODE1248 2 "register_operand" "x")
- (match_operand:SSEMODE1248 3 "nonimmediate_operand" "xm")])]
- UNSPEC_SSE5_UNSIGNED_CMP))]
- "TARGET_SSE5"
- "pcom%Y1u<ssevecsize>\t{%3, %2, %0|%0, %2, %3}"
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
-;; Pcomtrue and pcomfalse support. These are useless instructions, but are
-;; being added here to be complete.
-(define_insn "sse5_pcom_tf<mode>3"
- [(set (match_operand:SSEMODE1248 0 "register_operand" "=x")
- (unspec:SSEMODE1248
- [(match_operand:SSEMODE1248 1 "register_operand" "x")
- (match_operand:SSEMODE1248 2 "nonimmediate_operand" "xm")
- (match_operand:SI 3 "const_int_operand" "n")]
- UNSPEC_SSE5_TRUEFALSE))]
- "TARGET_SSE5"
-{
- return ((INTVAL (operands[3]) != 0)
- ? "pcomtrue<ssevecsize>\t{%2, %1, %0|%0, %1, %2}"
- : "pcomfalse<ssevecsize>\t{%2, %1, %0|%0, %1, %2}");
-}
- [(set_attr "type" "ssecmp")
- (set_attr "prefix_data16" "0")
- (set_attr "prefix_extra" "2")
- (set_attr "length_immediate" "1")
- (set_attr "mode" "TI")])
-
(define_insn "*avx_aesenc"
[(set (match_operand:V2DI 0 "register_operand" "=x")
(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "x")
-mcld -mcx16 -msahf -mmovbe -mcrc32 -mrecip @gol
-mmmx -msse -msse2 -msse3 -mssse3 -msse4.1 -msse4.2 -msse4 -mavx @gol
-maes -mpclmul @gol
--msse4a -m3dnow -mpopcnt -mabm -msse5 @gol
+-msse4a -m3dnow -mpopcnt -mabm @gol
-mthreads -mno-align-stringops -minline-all-stringops @gol
-minline-stringops-dynamically -mstringop-strategy=@var{alg} @gol
-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
-momit-leaf-frame-pointer -mno-red-zone -mno-tls-direct-seg-refs @gol
-mcmodel=@var{code-model} -mabi=@var{name} @gol
-m32 -m64 -mlarge-data-threshold=@var{num} @gol
--mfused-madd -mno-fused-madd -msse2avx}
+-msse2avx}
@emph{IA-64 Options}
@gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol
@itemx -mno-pclmul
@itemx -msse4a
@itemx -mno-sse4a
-@itemx -msse5
-@itemx -mno-sse5
@itemx -m3dnow
@itemx -mno-3dnow
@itemx -mpopcnt
@opindex m3dnow
@opindex mno-3dnow
These switches enable or disable the use of instructions in the MMX,
-SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, SSE5, ABM or
+SSE, SSE2, SSE3, SSSE3, SSE4.1, AVX, AES, PCLMUL, SSE4A, ABM or
3DNow!@: extended instruction sets.
These extensions are also available as built-in functions: see
@ref{X86 Built-in Functions}, for details of the functions enabled and
For systems that use GNU libc, the default is on.
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-Enable automatic generation of fused floating point multiply-add instructions
-if the ISA supports such instructions. The -mfused-madd option is on by
-default. The fused multiply-add instructions have a different
-rounding behavior compared to executing a multiply followed by an add.
-
@item -msse2avx
@itemx -mno-sse2avx
@opindex msse2avx
+2009-08-25 Jan Hubicka <jh@suse.cz>
+
+ * gcc.target/i386/sse5-shift1-vector.c
+ * gcc.target/i386/isa-12.c
+ * gcc.target/i386/isa-12.cgcc.target/i386/isa-12.c
+ * gcc.target/i386/sse5-pcmov2.c
+ * gcc.target/i386/isa-3.c
+ * gcc.target/i386/sse5-shift2-vector.c
+ * gcc.target/i386/isa-7.c
+ * gcc.target/i386/funcspec-2.c
+ * gcc.target/i386/sse5-haddX.c
+ * gcc.target/i386/sse5-hadduX.c
+ * gcc.target/i386/isa-9.c
+ * gcc.target/i386/sse5-maccXX.c
+ * gcc.target/i386/sse5-shift3-vector.c
+ * gcc.target/i386/sse5-msubXX.c
+ * gcc.target/i386/sse5-permpX.c
+ * gcc.target/i386/sse5-check.h
+ * gcc.target/i386/sse-12.c
+ * gcc.target/i386/sse-11.c
+ * gcc.target/i386/sse-10.c
+ * gcc.target/i386/sse-13.c
+ * gcc.target/i386/sse-14.c
+ * gcc.target/i386/sse-22.c
+ * gcc.target/i386/sse-2.c
+ * gcc.target/i386/sse-13.c
+ * gcc.target/i386/avx-2.c
+ * gcc.target/i386/sse5-rotate1-vector.c
+ * gcc.target/i386/isa-4.c
+ * gcc.target/i386/sse5-hsubX.c
+ * gcc.target/i386/sse5-pcmov.c
+ * gcc.target/i386/sse5-fma.c
+ * gcc.target/i386/isa-8.c
+ * gcc.target/i386/sse5-rotate2-vector.c
+ * gcc.target/i386/sse5-nmaccXX.c
+ * gcc.target/i386/sse5-imul64-vector.c
+ * gcc.target/i386/sse5-nmsubXX.c
+ * gcc.target/i386/sse5-rotate3-vector.c
+ * gcc.target/i386/sse5-fma-vector.c
+ * gcc.target/i386/sse5-imul32widen-vector.c: Remove SSE5 related testcases
+ * gcc.target/i386/sse5-ima-vector.c
+
+ * gcc.target/i386/funcspec-8.c: Replace SSE5 by SSE4.
+ * gcc.target/i386/funcspec-5.c: Remove SSE5.
+ * gcc.target/i386/funcspec-6.c: Remove fused-add test.
+ * gcc.target/i386/avx-1.c: Remove SSE5.
+ * gcc.target/i386/avx-2.c: Remove SSE5.
+ * g++.dg/other/i386-2.C: Replace SSE5 by SSE4A.
+ * g++.dg/other/i386-3.C: Replace SSE5 by SSE4A.
+ * g++.dg/other/i386-6.C: Replace SSE5 by SSE4A.
+ * g++.dg/other/i386-5.C: Replace SSE5 by SSE4A.
+
2009-08-25 Uros Bizjak <ubizjak@gmail.com>
* gcc.c-torture/compile/limits-fndefn.c: Add dg-timeout-factor.
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h and mm_malloc.h are
usable with -O -pedantic-errors. */
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -msse4a -maes -mpclmul" } */
#include <x86intrin.h>
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h and mm_malloc.h are
usable with -O -fkeep-inline-functions. */
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -msse4a -maes -mpclmul" } */
#include <x86intrin.h>
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h and mm_malloc.h are
usable with -O -fkeep-inline-functions. */
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+/* { dg-options "-O -fkeep-inline-functions -march=k8 -m3dnow -mavx -msse4a -maes -mpclmul" } */
#include <x86intrin.h>
/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h and mm_malloc.h are
usable with -O -pedantic-errors. */
/* { dg-do compile { target i?86-*-* x86_64-*-* } } */
-/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+/* { dg-options "-O -pedantic-errors -march=k8 -m3dnow -mavx -msse4a -maes -mpclmul" } */
#include <x86intrin.h>
/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -maes -mpclmul" } */
#include <mm_malloc.h>
#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
-/* bmmintrin.h */
-#define __builtin_ia32_protbi(A, B) __builtin_ia32_protbi(A,1)
-#define __builtin_ia32_protwi(A, B) __builtin_ia32_protwi(A,1)
-#define __builtin_ia32_protdi(A, B) __builtin_ia32_protdi(A,1)
-#define __builtin_ia32_protqi(A, B) __builtin_ia32_protqi(A,1)
-
#include <wmmintrin.h>
-#include <bmmintrin.h>
#include <immintrin.h>
#include <mm3dnow.h>
/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
+/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse4a -maes -mpclmul" } */
#include <mm_malloc.h>
#define __inline
#include <wmmintrin.h>
-#include <bmmintrin.h>
#include <immintrin.h>
+#include <ammintrin.h>
#include <mm3dnow.h>
#define _CONCAT(x,y) x ## y
test_1 (_m_pshufw, __m64, __m64, 1)
test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
-/* bmmintrin.h */
-test_1 (_mm_roti_epi8, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi16, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi32, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi64, __m128i, __m128i, 1)
+++ /dev/null
-/* Test whether using target specific options, we can generate SSE5 code. */
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -march=k8" } */
-
-extern void exit (int);
-
-#define SSE5_ATTR __attribute__((__target__("sse5,fused-madd")))
-extern float flt_mul_add (float a, float b, float c) SSE5_ATTR;
-extern float flt_mul_sub (float a, float b, float c) SSE5_ATTR;
-extern float flt_neg_mul_add (float a, float b, float c) SSE5_ATTR;
-extern float flt_neg_mul_sub (float a, float b, float c) SSE5_ATTR;
-
-extern double dbl_mul_add (double a, double b, double c) SSE5_ATTR;
-extern double dbl_mul_sub (double a, double b, double c) SSE5_ATTR;
-extern double dbl_neg_mul_add (double a, double b, double c) SSE5_ATTR;
-extern double dbl_neg_mul_sub (double a, double b, double c) SSE5_ATTR;
-
-float
-flt_mul_add (float a, float b, float c)
-{
- return (a * b) + c;
-}
-
-double
-dbl_mul_add (double a, double b, double c)
-{
- return (a * b) + c;
-}
-
-float
-flt_mul_sub (float a, float b, float c)
-{
- return (a * b) - c;
-}
-
-double
-dbl_mul_sub (double a, double b, double c)
-{
- return (a * b) - c;
-}
-
-float
-flt_neg_mul_add (float a, float b, float c)
-{
- return (-(a * b)) + c;
-}
-
-double
-dbl_neg_mul_add (double a, double b, double c)
-{
- return (-(a * b)) + c;
-}
-
-float
-flt_neg_mul_sub (float a, float b, float c)
-{
- return (-(a * b)) - c;
-}
-
-double
-dbl_neg_mul_sub (double a, double b, double c)
-{
- return (-(a * b)) - c;
-}
-
-float f[10] = { 2, 3, 4 };
-double d[10] = { 2, 3, 4 };
-
-int main ()
-{
- f[3] = flt_mul_add (f[0], f[1], f[2]);
- f[4] = flt_mul_sub (f[0], f[1], f[2]);
- f[5] = flt_neg_mul_add (f[0], f[1], f[2]);
- f[6] = flt_neg_mul_sub (f[0], f[1], f[2]);
-
- d[3] = dbl_mul_add (d[0], d[1], d[2]);
- d[4] = dbl_mul_sub (d[0], d[1], d[2]);
- d[5] = dbl_neg_mul_add (d[0], d[1], d[2]);
- d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]);
- exit (0);
-}
-
-/* { dg-final { scan-assembler "fmaddss" } } */
-/* { dg-final { scan-assembler "fmaddsd" } } */
-/* { dg-final { scan-assembler "fmsubss" } } */
-/* { dg-final { scan-assembler "fmsubsd" } } */
-/* { dg-final { scan-assembler "fnmaddss" } } */
-/* { dg-final { scan-assembler "fnmaddsd" } } */
-/* { dg-final { scan-assembler "fnmsubss" } } */
-/* { dg-final { scan-assembler "fnmsubsd" } } */
-/* { dg-final { scan-assembler "call\t(.*)flt_mul_add" } } */
-/* { dg-final { scan-assembler "call\t(.*)flt_mul_sub" } } */
-/* { dg-final { scan-assembler "call\t(.*)flt_neg_mul_add" } } */
-/* { dg-final { scan-assembler "call\t(.*)flt_neg_mul_sub" } } */
-/* { dg-final { scan-assembler "call\t(.*)dbl_mul_add" } } */
-/* { dg-final { scan-assembler "call\t(.*)dbl_mul_sub" } } */
-/* { dg-final { scan-assembler "call\t(.*)dbl_neg_mul_add" } } */
-/* { dg-final { scan-assembler "call\t(.*)dbl_neg_mul_sub" } } */
extern void test_sse4_1 (void) __attribute__((__target__("sse4.1")));
extern void test_sse4_2 (void) __attribute__((__target__("sse4.2")));
extern void test_sse4a (void) __attribute__((__target__("sse4a")));
-extern void test_sse5 (void) __attribute__((__target__("sse5")));
extern void test_ssse3 (void) __attribute__((__target__("ssse3")));
extern void test_no_abm (void) __attribute__((__target__("no-abm")));
extern void test_no_sse4_1 (void) __attribute__((__target__("no-sse4.1")));
extern void test_no_sse4_2 (void) __attribute__((__target__("no-sse4.2")));
extern void test_no_sse4a (void) __attribute__((__target__("no-sse4a")));
-extern void test_no_sse5 (void) __attribute__((__target__("no-sse5")));
extern void test_no_ssse3 (void) __attribute__((__target__("no-ssse3")));
extern void test_arch_i386 (void) __attribute__((__target__("arch=i386")));
extern void test_abm (void) __attribute__((__target__("abm")));
extern void test_aes (void) __attribute__((__target__("aes")));
-extern void test_fused_madd (void) __attribute__((__target__("fused-madd")));
extern void test_mmx (void) __attribute__((__target__("mmx")));
extern void test_pclmul (void) __attribute__((__target__("pclmul")));
extern void test_popcnt (void) __attribute__((__target__("popcnt")));
extern void test_sse4_1 (void) __attribute__((__target__("sse4.1")));
extern void test_sse4_2 (void) __attribute__((__target__("sse4.2")));
extern void test_sse4a (void) __attribute__((__target__("sse4a")));
-extern void test_sse5 (void) __attribute__((__target__("sse5")));
extern void test_ssse3 (void) __attribute__((__target__("ssse3")));
extern void test_no_abm (void) __attribute__((__target__("no-abm")));
extern void test_no_aes (void) __attribute__((__target__("no-aes")));
-extern void test_no_fused_madd (void) __attribute__((__target__("no-fused-madd")));
extern void test_no_mmx (void) __attribute__((__target__("no-mmx")));
extern void test_no_pclmul (void) __attribute__((__target__("no-pclmul")));
extern void test_no_popcnt (void) __attribute__((__target__("no-popcnt")));
extern void test_no_sse4_1 (void) __attribute__((__target__("no-sse4.1")));
extern void test_no_sse4_2 (void) __attribute__((__target__("no-sse4.2")));
extern void test_no_sse4a (void) __attribute__((__target__("no-sse4a")));
-extern void test_no_sse5 (void) __attribute__((__target__("no-sse5")));
extern void test_no_ssse3 (void) __attribute__((__target__("no-ssse3")));
extern void test_arch_nocona (void) __attribute__((__target__("arch=nocona")));
return __builtin_ia32_insertq (a, b); /* { dg-error "needs isa option" } */
}
-#ifdef __SSE5__
-#error "-msse5 should not be set for this test"
-#endif
-
-__m128d sse5_fmaddpd (__m128d a, __m128d b, __m128d c) __attribute__((__target__("sse5")));
-__m128d generic_fmaddpd (__m128d a, __m128d b, __m128d c);
-
-__m128d
-sse5_fmaddpd (__m128d a, __m128d b, __m128d c)
-{
- return __builtin_ia32_fmaddpd (a, b, c);
-}
-
-__m128d
-generic_fmaddpd (__m128d a, __m128d b, __m128d c)
-{
- return __builtin_ia32_fmaddpd (a, b, c); /* { dg-error "needs isa option" } */
-}
-
#ifdef __AES__
#error "-maes should not be set for this test"
#endif
extern void exit (int);
-#ifdef __SSE5__
-#warning "__SSE5__ should not be defined before #pragma GCC target."
+#ifdef __SSE4A__
+#warning "__SSE4A__ should not be defined before #pragma GCC target."
#endif
#pragma GCC push_options
-#pragma GCC target ("sse5,fused-madd")
+#pragma GCC target ("sse4a")
-#ifndef __SSE5__
-#warning "__SSE5__ should have be defined after #pragma GCC target."
+#ifndef __SSE4A__
+#warning "__SSE4A__ should have be defined after #pragma GCC target."
#endif
float
}
#pragma GCC pop_options
-#ifdef __SSE5__
-#warning "__SSE5__ should not be defined after #pragma GCC pop target."
+#ifdef __SSE4A__
+#warning "__SSE4A__ should not be defined after #pragma GCC pop target."
#endif
double
return (a * b) + c;
}
-/* { dg-final { scan-assembler "fmaddss" } } */
+/* We used to generate fused-madd with SSE5 support, but don't do that anymore. */
/* { dg-final { scan-assembler "addsd" } } */
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=x86-64 -msse5 -mno-sse4" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if !defined __SSE3__
- abort ();
-#endif
-#if defined __SSSE3__
- abort ();
-#endif
-#if defined __SSE4_1__
- abort ();
-#endif
-#if defined __SSE4_2__
- abort ();
-#endif
-#if !defined __SSE4A__
- abort ();
-#endif
-#if !defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=x86-64 -msse5 -mno-ssse3" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if !defined __SSE3__
- abort ();
-#endif
-#if defined __SSSE3__
- abort ();
-#endif
-#if defined __SSE4_1__
- abort ();
-#endif
-#if defined __SSE4_2__
- abort ();
-#endif
-#if !defined __SSE4A__
- abort ();
-#endif
-#if !defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=x86-64 -msse5 -mno-sse3" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if defined __SSE3__
- abort ();
-#endif
-#if defined __SSSE3__
- abort ();
-#endif
-#if defined __SSE4_1__
- abort ();
-#endif
-#if defined __SSE4_2__
- abort ();
-#endif
-#if defined __SSE4A__
- abort ();
-#endif
-#if defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=x86-64 -msse5 -mno-sse2" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if defined __SSE2__
- abort ();
-#endif
-#if defined __SSE3__
- abort ();
-#endif
-#if defined __SSSE3__
- abort ();
-#endif
-#if defined __SSE4_1__
- abort ();
-#endif
-#if defined __SSE4_2__
- abort ();
-#endif
-#if defined __SSE4A__
- abort ();
-#endif
-#if defined __SSE5__
- abort ();
-#endif
- return 0;
-}
/* { dg-do run } */
-/* { dg-options "-march=x86-64 -msse5 -mno-sse" } */
+/* { dg-options "-march=x86-64 -msse4a -mno-sse" } */
extern void abort (void);
#if defined __SSE4A__
abort ();
#endif
-#if defined __SSE5__
- abort ();
-#endif
return 0;
}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=x86-64 -msse4 -msse5" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if !defined __SSE3__
- abort ();
-#endif
-#if !defined __SSSE3__
- abort ();
-#endif
-#if !defined __SSE4_1__
- abort ();
-#endif
-#if !defined __SSE4_2__
- abort ();
-#endif
-#if !defined __SSE4A__
- abort ();
-#endif
-#if !defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=x86-64 -msse4 -msse5 -msse4a" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if !defined __SSE3__
- abort ();
-#endif
-#if !defined __SSSE3__
- abort ();
-#endif
-#if !defined __SSE4_1__
- abort ();
-#endif
-#if !defined __SSE4_2__
- abort ();
-#endif
-#if !defined __SSE4A__
- abort ();
-#endif
-#if !defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=core2 -msse5 -mno-sse4" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if !defined __SSE3__
- abort ();
-#endif
-#if !defined __SSSE3__
- abort ();
-#endif
-#if defined __SSE4_1__
- abort ();
-#endif
-#if defined __SSE4_2__
- abort ();
-#endif
-#if !defined __SSE4A__
- abort ();
-#endif
-#if !defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=amdfam10 -msse5 -mno-sse4" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if !defined __SSE3__
- abort ();
-#endif
-#if defined __SSSE3__
- abort ();
-#endif
-#if defined __SSE4_1__
- abort ();
-#endif
-#if defined __SSE4_2__
- abort ();
-#endif
-#if !defined __SSE4A__
- abort ();
-#endif
-#if !defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=amdfam10 -msse5 -mno-sse4a" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if !defined __SSE3__
- abort ();
-#endif
-#if defined __SSSE3__
- abort ();
-#endif
-#if defined __SSE4_1__
- abort ();
-#endif
-#if defined __SSE4_2__
- abort ();
-#endif
-#if defined __SSE4A__
- abort ();
-#endif
-#if defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-options "-march=amdfam10 -mno-sse5" } */
-
-extern void abort (void);
-
-int
-main ()
-{
-#if !defined __SSE__
- abort ();
-#endif
-#if !defined __SSE2__
- abort ();
-#endif
-#if !defined __SSE3__
- abort ();
-#endif
-#if defined __SSSE3__
- abort ();
-#endif
-#if defined __SSE4_1__
- abort ();
-#endif
-#if defined __SSE4_2__
- abort ();
-#endif
-#if !defined __SSE4A__
- abort ();
-#endif
-#if defined __SSE5__
- abort ();
-#endif
- return 0;
-}
+++ /dev/null
-/* Test that the compiler properly optimizes vector SI->DI conversions. This
- was a bug in the initial SSE5 code. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-union {
- signed int si[SIZE];
- signed long sl[SIZE];
- __m128i align;
-} a, b;
-
-void conv_sign_int_sign_long (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.sl[i] = b.si[i];
-}
-
-/* { dg-final { scan-assembler "pperm" } } */
+++ /dev/null
-/* Test that {,x,e,p,t,s,w,a,b,i}mmintrin.h, mm3dnow.h and mm_malloc.h are
- usable with -O -std=c89 -pedantic-errors. */
-/* { dg-do compile } */
-/* { dg-options "-O -std=c89 -pedantic-errors -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
-
-#include <x86intrin.h>
-
-int dummy;
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-O2 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
-
-#include <mm_malloc.h>
-
-/* Test that the intrinsics compile with optimization. All of them are
- defined as inline functions in {,x,e,p,t,s,w,a,b,i}mmintrin.h and mm3dnow.h
- that reference the proper builtin functions. Defining away "extern" and
- "__inline" results in all of them being compiled as proper functions. */
-
-#define extern
-#define __inline
-
-/* Following intrinsics require immediate arguments. */
-
-/* ammintrin.h */
-#define __builtin_ia32_extrqi(X, I, L) __builtin_ia32_extrqi(X, 1, 1)
-#define __builtin_ia32_insertqi(X, Y, I, L) __builtin_ia32_insertqi(X, Y, 1, 1)
-
-/* immintrin.h */
-#define __builtin_ia32_blendpd256(X, Y, M) __builtin_ia32_blendpd256(X, Y, 1)
-#define __builtin_ia32_blendps256(X, Y, M) __builtin_ia32_blendps256(X, Y, 1)
-#define __builtin_ia32_dpps256(X, Y, M) __builtin_ia32_dpps256(X, Y, 1)
-#define __builtin_ia32_shufpd256(X, Y, M) __builtin_ia32_shufpd256(X, Y, 1)
-#define __builtin_ia32_shufps256(X, Y, M) __builtin_ia32_shufps256(X, Y, 1)
-#define __builtin_ia32_cmpsd(X, Y, O) __builtin_ia32_cmpsd(X, Y, 1)
-#define __builtin_ia32_cmpss(X, Y, O) __builtin_ia32_cmpss(X, Y, 1)
-#define __builtin_ia32_cmppd(X, Y, O) __builtin_ia32_cmppd(X, Y, 1)
-#define __builtin_ia32_cmpps(X, Y, O) __builtin_ia32_cmpps(X, Y, 1)
-#define __builtin_ia32_cmppd256(X, Y, O) __builtin_ia32_cmppd256(X, Y, 1)
-#define __builtin_ia32_cmpps256(X, Y, O) __builtin_ia32_cmpps256(X, Y, 1)
-#define __builtin_ia32_vextractf128_pd256(X, N) __builtin_ia32_vextractf128_pd256(X, 1)
-#define __builtin_ia32_vextractf128_ps256(X, N) __builtin_ia32_vextractf128_ps256(X, 1)
-#define __builtin_ia32_vextractf128_si256(X, N) __builtin_ia32_vextractf128_si256(X, 1)
-#define __builtin_ia32_vpermilpd(X, N) __builtin_ia32_vpermilpd(X, 1)
-#define __builtin_ia32_vpermilpd256(X, N) __builtin_ia32_vpermilpd256(X, 1)
-#define __builtin_ia32_vpermilps(X, N) __builtin_ia32_vpermilps(X, 1)
-#define __builtin_ia32_vpermilps256(X, N) __builtin_ia32_vpermilps256(X, 1)
-#define __builtin_ia32_vpermil2pd(X, Y, C, I) __builtin_ia32_vpermil2pd(X, Y, C, 1)
-#define __builtin_ia32_vpermil2pd256(X, Y, C, I) __builtin_ia32_vpermil2pd256(X, Y, C, 1)
-#define __builtin_ia32_vpermil2ps(X, Y, C, I) __builtin_ia32_vpermil2ps(X, Y, C, 1)
-#define __builtin_ia32_vpermil2ps256(X, Y, C, I) __builtin_ia32_vpermil2ps256(X, Y, C, 1)
-#define __builtin_ia32_vperm2f128_pd256(X, Y, C) __builtin_ia32_vperm2f128_pd256(X, Y, 1)
-#define __builtin_ia32_vperm2f128_ps256(X, Y, C) __builtin_ia32_vperm2f128_ps256(X, Y, 1)
-#define __builtin_ia32_vperm2f128_si256(X, Y, C) __builtin_ia32_vperm2f128_si256(X, Y, 1)
-#define __builtin_ia32_vinsertf128_pd256(X, Y, C) __builtin_ia32_vinsertf128_pd256(X, Y, 1)
-#define __builtin_ia32_vinsertf128_ps256(X, Y, C) __builtin_ia32_vinsertf128_ps256(X, Y, 1)
-#define __builtin_ia32_vinsertf128_si256(X, Y, C) __builtin_ia32_vinsertf128_si256(X, Y, 1)
-#define __builtin_ia32_roundpd256(V, M) __builtin_ia32_roundpd256(V, 1)
-#define __builtin_ia32_roundps256(V, M) __builtin_ia32_roundps256(V, 1)
-
-/* wmmintrin.h */
-#define __builtin_ia32_aeskeygenassist128(X, C) __builtin_ia32_aeskeygenassist128(X, 1)
-#define __builtin_ia32_pclmulqdq128(X, Y, I) __builtin_ia32_pclmulqdq128(X, Y, 1)
-
-/* mmintrin-common.h */
-#define __builtin_ia32_roundpd(V, M) __builtin_ia32_roundpd(V, 1)
-#define __builtin_ia32_roundsd(D, V, M) __builtin_ia32_roundsd(D, V, 1)
-#define __builtin_ia32_roundps(V, M) __builtin_ia32_roundps(V, 1)
-#define __builtin_ia32_roundss(D, V, M) __builtin_ia32_roundss(D, V, 1)
-
-/* smmintrin.h */
-#define __builtin_ia32_pblendw128(X, Y, M) __builtin_ia32_pblendw128 (X, Y, 1)
-#define __builtin_ia32_blendps(X, Y, M) __builtin_ia32_blendps(X, Y, 1)
-#define __builtin_ia32_blendpd(X, Y, M) __builtin_ia32_blendpd(X, Y, 1)
-#define __builtin_ia32_dpps(X, Y, M) __builtin_ia32_dpps(X, Y, 1)
-#define __builtin_ia32_dppd(X, Y, M) __builtin_ia32_dppd(X, Y, 1)
-#define __builtin_ia32_insertps128(D, S, N) __builtin_ia32_insertps128(D, S, 1)
-#define __builtin_ia32_vec_ext_v4sf(X, N) __builtin_ia32_vec_ext_v4sf(X, 1)
-#define __builtin_ia32_vec_set_v16qi(D, S, N) __builtin_ia32_vec_set_v16qi(D, S, 1)
-#define __builtin_ia32_vec_set_v4si(D, S, N) __builtin_ia32_vec_set_v4si(D, S, 1)
-#define __builtin_ia32_vec_set_v2di(D, S, N) __builtin_ia32_vec_set_v2di(D, S, 1)
-#define __builtin_ia32_vec_ext_v16qi(X, N) __builtin_ia32_vec_ext_v16qi(X, 1)
-#define __builtin_ia32_vec_ext_v4si(X, N) __builtin_ia32_vec_ext_v4si(X, 1)
-#define __builtin_ia32_vec_ext_v2di(X, N) __builtin_ia32_vec_ext_v2di(X, 1)
-#define __builtin_ia32_mpsadbw128(X, Y, M) __builtin_ia32_mpsadbw128(X, Y, 1)
-#define __builtin_ia32_pcmpistrm128(X, Y, M) \
- __builtin_ia32_pcmpistrm128(X, Y, 1)
-#define __builtin_ia32_pcmpistri128(X, Y, M) \
- __builtin_ia32_pcmpistri128(X, Y, 1)
-#define __builtin_ia32_pcmpestrm128(X, LX, Y, LY, M) \
- __builtin_ia32_pcmpestrm128(X, LX, Y, LY, 1)
-#define __builtin_ia32_pcmpestri128(X, LX, Y, LY, M) \
- __builtin_ia32_pcmpestri128(X, LX, Y, LY, 1)
-#define __builtin_ia32_pcmpistria128(X, Y, M) \
- __builtin_ia32_pcmpistria128(X, Y, 1)
-#define __builtin_ia32_pcmpistric128(X, Y, M) \
- __builtin_ia32_pcmpistric128(X, Y, 1)
-#define __builtin_ia32_pcmpistrio128(X, Y, M) \
- __builtin_ia32_pcmpistrio128(X, Y, 1)
-#define __builtin_ia32_pcmpistris128(X, Y, M) \
- __builtin_ia32_pcmpistris128(X, Y, 1)
-#define __builtin_ia32_pcmpistriz128(X, Y, M) \
- __builtin_ia32_pcmpistriz128(X, Y, 1)
-#define __builtin_ia32_pcmpestria128(X, LX, Y, LY, M) \
- __builtin_ia32_pcmpestria128(X, LX, Y, LY, 1)
-#define __builtin_ia32_pcmpestric128(X, LX, Y, LY, M) \
- __builtin_ia32_pcmpestric128(X, LX, Y, LY, 1)
-#define __builtin_ia32_pcmpestrio128(X, LX, Y, LY, M) \
- __builtin_ia32_pcmpestrio128(X, LX, Y, LY, 1)
-#define __builtin_ia32_pcmpestris128(X, LX, Y, LY, M) \
- __builtin_ia32_pcmpestris128(X, LX, Y, LY, 1)
-#define __builtin_ia32_pcmpestriz128(X, LX, Y, LY, M) \
- __builtin_ia32_pcmpestriz128(X, LX, Y, LY, 1)
-
-/* tmmintrin.h */
-#define __builtin_ia32_palignr128(X, Y, N) __builtin_ia32_palignr128(X, Y, 8)
-#define __builtin_ia32_palignr(X, Y, N) __builtin_ia32_palignr(X, Y, 8)
-
-/* emmintrin.h */
-#define __builtin_ia32_psrldqi128(A, B) __builtin_ia32_psrldqi128(A, 8)
-#define __builtin_ia32_pslldqi128(A, B) __builtin_ia32_pslldqi128(A, 8)
-#define __builtin_ia32_pshufhw(A, N) __builtin_ia32_pshufhw(A, 0)
-#define __builtin_ia32_pshuflw(A, N) __builtin_ia32_pshuflw(A, 0)
-#define __builtin_ia32_pshufd(A, N) __builtin_ia32_pshufd(A, 0)
-#define __builtin_ia32_vec_set_v8hi(A, D, N) \
- __builtin_ia32_vec_set_v8hi(A, D, 0)
-#define __builtin_ia32_vec_ext_v8hi(A, N) __builtin_ia32_vec_ext_v8hi(A, 0)
-#define __builtin_ia32_shufpd(A, B, N) __builtin_ia32_shufpd(A, B, 0)
-
-/* xmmintrin.h */
-#define __builtin_prefetch(P, A, I) __builtin_prefetch(P, A, _MM_HINT_NTA)
-#define __builtin_ia32_pshufw(A, N) __builtin_ia32_pshufw(A, 0)
-#define __builtin_ia32_vec_set_v4hi(A, D, N) \
- __builtin_ia32_vec_set_v4hi(A, D, 0)
-#define __builtin_ia32_vec_ext_v4hi(A, N) __builtin_ia32_vec_ext_v4hi(A, 0)
-#define __builtin_ia32_shufps(A, B, N) __builtin_ia32_shufps(A, B, 0)
-
-/* bmmintrin.h */
-#define __builtin_ia32_protbi(A, B) __builtin_ia32_protbi(A,1)
-#define __builtin_ia32_protwi(A, B) __builtin_ia32_protwi(A,1)
-#define __builtin_ia32_protdi(A, B) __builtin_ia32_protdi(A,1)
-#define __builtin_ia32_protqi(A, B) __builtin_ia32_protqi(A,1)
-
-#include <x86intrin.h>
+++ /dev/null
-/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration -march=k8 -m3dnow -mavx -msse5 -maes -mpclmul" } */
-
-#include <mm_malloc.h>
-
-/* Test that the intrinsics compile without optimization. All of them are
- defined as inline functions in {,x,e,p,t,s,w,a,b}mmintrin.h and mm3dnow.h
- that reference the proper builtin functions. Defining away "extern" and
- "__inline" results in all of them being compiled as proper functions. */
-
-#define extern
-#define __inline
-
-#include <x86intrin.h>
-
-#define _CONCAT(x,y) x ## y
-
-#define test_1(func, type, op1_type, imm) \
- type _CONCAT(_,func) (op1_type A, int const I) \
- { return func (A, imm); }
-
-#define test_1x(func, type, op1_type, imm1, imm2) \
- type _CONCAT(_,func) (op1_type A, int const I, int const L) \
- { return func (A, imm1, imm2); }
-
-#define test_2(func, type, op1_type, op2_type, imm) \
- type _CONCAT(_,func) (op1_type A, op2_type B, int const I) \
- { return func (A, B, imm); }
-
-#define test_2x(func, type, op1_type, op2_type, imm1, imm2) \
- type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
- { return func (A, B, imm1, imm2); }
-
-#define test_3(func, type, op1_type, op2_type, op3_type, imm) \
- type _CONCAT(_,func) (op1_type A, op2_type B, \
- op3_type C, int const I) \
- { return func (A, B, C, imm); }
-
-#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm) \
- type _CONCAT(_,func) (op1_type A, op2_type B, \
- op3_type C, op4_type D, int const I) \
- { return func (A, B, C, D, imm); }
-
-
-/* Following intrinsics require immediate arguments. They
- are defined as macros for non-optimized compilations. */
-
-/* ammintrin.h */
-test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
-test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
-
-/* immintrin.h */
-test_2 (_mm256_blend_pd, __m256d, __m256d, __m256d, 1)
-test_2 (_mm256_blend_ps, __m256, __m256, __m256, 1)
-test_2 (_mm256_dp_ps, __m256, __m256, __m256, 1)
-test_2 (_mm256_shuffle_pd, __m256d, __m256d, __m256d, 1)
-test_2 (_mm256_shuffle_ps, __m256, __m256, __m256, 1)
-test_2 (_mm_cmp_sd, __m128d, __m128d, __m128d, 1)
-test_2 (_mm_cmp_ss, __m128, __m128, __m128, 1)
-test_2 (_mm_cmp_pd, __m128d, __m128d, __m128d, 1)
-test_2 (_mm_cmp_ps, __m128, __m128, __m128, 1)
-test_2 (_mm256_cmp_pd, __m256d, __m256d, __m256d, 1)
-test_2 (_mm256_cmp_ps, __m256, __m256, __m256, 1)
-test_1 (_mm256_extractf128_pd, __m128d, __m256d, 1)
-test_1 (_mm256_extractf128_ps, __m128, __m256, 1)
-test_1 (_mm256_extractf128_si256, __m128i, __m256i, 1)
-test_1 (_mm256_extract_epi8, int, __m256i, 20)
-test_1 (_mm256_extract_epi16, int, __m256i, 13)
-test_1 (_mm256_extract_epi32, int, __m256i, 6)
-#ifdef __x86_64__
-test_1 (_mm256_extract_epi64, long long, __m256i, 2)
-#endif
-test_1 (_mm_permute_pd, __m128d, __m128d, 1)
-test_1 (_mm256_permute_pd, __m256d, __m256d, 1)
-test_1 (_mm_permute_ps, __m128, __m128, 1)
-test_1 (_mm256_permute_ps, __m256, __m256, 1)
-test_2 (_mm256_permute2f128_pd, __m256d, __m256d, __m256d, 1)
-test_2 (_mm256_permute2f128_ps, __m256, __m256, __m256, 1)
-test_2 (_mm256_permute2f128_si256, __m256i, __m256i, __m256i, 1)
-test_2 (_mm256_insertf128_pd, __m256d, __m256d, __m128d, 1)
-test_2 (_mm256_insertf128_ps, __m256, __m256, __m128, 1)
-test_2 (_mm256_insertf128_si256, __m256i, __m256i, __m128i, 1)
-test_2 (_mm256_insert_epi8, __m256i, __m256i, int, 30)
-test_2 (_mm256_insert_epi16, __m256i, __m256i, int, 7)
-test_2 (_mm256_insert_epi32, __m256i, __m256i, int, 3)
-#ifdef __x86_64__
-test_2 (_mm256_insert_epi64, __m256i, __m256i, long long, 1)
-#endif
-test_1 (_mm256_round_pd, __m256d, __m256d, 1)
-test_1 (_mm256_round_ps, __m256, __m256, 1)
-
-/* wmmintrin.h */
-test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
-test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
-
-/* mmintrin-common.h */
-test_1 (_mm_round_pd, __m128d, __m128d, 1)
-test_1 (_mm_round_ps, __m128, __m128, 1)
-test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1)
-test_2 (_mm_round_ss, __m128, __m128, __m128, 1)
-
-/* smmintrin.h */
-test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
-test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
-test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1)
-test_2 (_mm_dp_ps, __m128, __m128, __m128, 1)
-test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1)
-test_2 (_mm_insert_ps, __m128, __m128, __m128, 1)
-test_1 (_mm_extract_ps, int, __m128, 1)
-test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1)
-test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1)
-#ifdef __x86_64__
-test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1)
-#endif
-test_1 (_mm_extract_epi8, int, __m128i, 1)
-test_1 (_mm_extract_epi32, int, __m128i, 1)
-#ifdef __x86_64__
-test_1 (_mm_extract_epi64, long long, __m128i, 1)
-#endif
-test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1)
-test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1)
-test_2 (_mm_cmpistri, int, __m128i, __m128i, 1)
-test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1)
-test_2 (_mm_cmpistra, int, __m128i, __m128i, 1)
-test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1)
-test_2 (_mm_cmpistro, int, __m128i, __m128i, 1)
-test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1)
-test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1)
-test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
-
-/* tmmintrin.h */
-test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1)
-test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1)
-
-/* emmintrin.h */
-test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1)
-test_1 (_mm_srli_si128, __m128i, __m128i, 1)
-test_1 (_mm_slli_si128, __m128i, __m128i, 1)
-test_1 (_mm_extract_epi16, int, __m128i, 1)
-test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1)
-test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1)
-test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1)
-test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1)
-
-/* xmmintrin.h */
-test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1)
-test_1 (_mm_extract_pi16, int, __m64, 1)
-test_1 (_m_pextrw, int, __m64, 1)
-test_2 (_mm_insert_pi16, __m64, __m64, int, 1)
-test_2 (_m_pinsrw, __m64, __m64, int, 1)
-test_1 (_mm_shuffle_pi16, __m64, __m64, 1)
-test_1 (_m_pshufw, __m64, __m64, 1)
-test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
-
-/* bmmintrin.h */
-test_1 (_mm_roti_epi8, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi16, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi32, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi64, __m128i, __m128i, 1)
+++ /dev/null
-/* Same as sse-14, except converted to use #pragma GCC option. */
-/* { dg-do compile } */
-/* { dg-options "-O0 -Werror-implicit-function-declaration" } */
-
-#include <mm_malloc.h>
-
-/* Test that the intrinsics compile without optimization. All of them are
- defined as inline functions in {,x,e,p,t,s,w,a,b}mmintrin.h and mm3dnow.h
- that reference the proper builtin functions. Defining away "extern" and
- "__inline" results in all of them being compiled as proper functions. */
-
-#define extern
-#define __inline
-
-#define _CONCAT(x,y) x ## y
-
-#define test_1(func, type, op1_type, imm) \
- type _CONCAT(_,func) (op1_type A, int const I) \
- { return func (A, imm); }
-
-#define test_1x(func, type, op1_type, imm1, imm2) \
- type _CONCAT(_,func) (op1_type A, int const I, int const L) \
- { return func (A, imm1, imm2); }
-
-#define test_2(func, type, op1_type, op2_type, imm) \
- type _CONCAT(_,func) (op1_type A, op2_type B, int const I) \
- { return func (A, B, imm); }
-
-#define test_2x(func, type, op1_type, op2_type, imm1, imm2) \
- type _CONCAT(_,func) (op1_type A, op2_type B, int const I, int const L) \
- { return func (A, B, imm1, imm2); }
-
-#define test_4(func, type, op1_type, op2_type, op3_type, op4_type, imm) \
- type _CONCAT(_,func) (op1_type A, op2_type B, \
- op3_type C, op4_type D, int const I) \
- { return func (A, B, C, D, imm); }
-
-
-#ifndef DIFFERENT_PRAGMAS
-#pragma GCC target ("mmx,3dnow,sse,sse2,sse3,ssse3,sse4.1,sse4.2,sse5,aes,pclmul")
-#endif
-
-/* Following intrinsics require immediate arguments. They
- are defined as macros for non-optimized compilations. */
-
-/* mmintrin.h (MMX). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("mmx")
-#endif
-#include <mmintrin.h>
-
-/* mm3dnow.h (3DNOW). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("3dnow")
-#endif
-#include <mm3dnow.h>
-
-/* xmmintrin.h (SSE). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse")
-#endif
-#include <xmmintrin.h>
-test_2 (_mm_shuffle_ps, __m128, __m128, __m128, 1)
-test_1 (_mm_extract_pi16, int, __m64, 1)
-test_1 (_m_pextrw, int, __m64, 1)
-test_2 (_mm_insert_pi16, __m64, __m64, int, 1)
-test_2 (_m_pinsrw, __m64, __m64, int, 1)
-test_1 (_mm_shuffle_pi16, __m64, __m64, 1)
-test_1 (_m_pshufw, __m64, __m64, 1)
-test_1 (_mm_prefetch, void, void *, _MM_HINT_NTA)
-
-/* emmintrin.h (SSE2). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse2")
-#endif
-#include <emmintrin.h>
-test_2 (_mm_shuffle_pd, __m128d, __m128d, __m128d, 1)
-test_1 (_mm_srli_si128, __m128i, __m128i, 1)
-test_1 (_mm_slli_si128, __m128i, __m128i, 1)
-test_1 (_mm_extract_epi16, int, __m128i, 1)
-test_2 (_mm_insert_epi16, __m128i, __m128i, int, 1)
-test_1 (_mm_shufflehi_epi16, __m128i, __m128i, 1)
-test_1 (_mm_shufflelo_epi16, __m128i, __m128i, 1)
-test_1 (_mm_shuffle_epi32, __m128i, __m128i, 1)
-
-/* pmmintrin.h (SSE3). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse3")
-#endif
-#include <pmmintrin.h>
-
-/* tmmintrin.h (SSSE3). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("ssse3")
-#endif
-#include <tmmintrin.h>
-test_2 (_mm_alignr_epi8, __m128i, __m128i, __m128i, 1)
-test_2 (_mm_alignr_pi8, __m64, __m64, __m64, 1)
-
-/* ammintrin.h (SSE4A). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4a")
-#endif
-#include <ammintrin.h>
-test_1x (_mm_extracti_si64, __m128i, __m128i, 1, 1)
-test_2x (_mm_inserti_si64, __m128i, __m128i, __m128i, 1, 1)
-
-/* smmintrin.h (SSE4.1). */
-/* nmmintrin.h (SSE4.2). */
-/* Note, nmmintrin.h includes smmintrin.h, and smmintrin.h checks for the
- #ifdef. So just set the option to SSE4.2. */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse4.2")
-#endif
-#include <nmmintrin.h>
-test_2 (_mm_blend_epi16, __m128i, __m128i, __m128i, 1)
-test_2 (_mm_blend_ps, __m128, __m128, __m128, 1)
-test_2 (_mm_blend_pd, __m128d, __m128d, __m128d, 1)
-test_2 (_mm_dp_ps, __m128, __m128, __m128, 1)
-test_2 (_mm_dp_pd, __m128d, __m128d, __m128d, 1)
-test_2 (_mm_insert_ps, __m128, __m128, __m128, 1)
-test_1 (_mm_extract_ps, int, __m128, 1)
-test_2 (_mm_insert_epi8, __m128i, __m128i, int, 1)
-test_2 (_mm_insert_epi32, __m128i, __m128i, int, 1)
-#ifdef __x86_64__
-test_2 (_mm_insert_epi64, __m128i, __m128i, long long, 1)
-#endif
-test_1 (_mm_extract_epi8, int, __m128i, 1)
-test_1 (_mm_extract_epi32, int, __m128i, 1)
-#ifdef __x86_64__
-test_1 (_mm_extract_epi64, long long, __m128i, 1)
-#endif
-test_2 (_mm_mpsadbw_epu8, __m128i, __m128i, __m128i, 1)
-test_2 (_mm_cmpistrm, __m128i, __m128i, __m128i, 1)
-test_2 (_mm_cmpistri, int, __m128i, __m128i, 1)
-test_4 (_mm_cmpestrm, __m128i, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestri, int, __m128i, int, __m128i, int, 1)
-test_2 (_mm_cmpistra, int, __m128i, __m128i, 1)
-test_2 (_mm_cmpistrc, int, __m128i, __m128i, 1)
-test_2 (_mm_cmpistro, int, __m128i, __m128i, 1)
-test_2 (_mm_cmpistrs, int, __m128i, __m128i, 1)
-test_2 (_mm_cmpistrz, int, __m128i, __m128i, 1)
-test_4 (_mm_cmpestra, int, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestrc, int, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestro, int, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestrs, int, __m128i, int, __m128i, int, 1)
-test_4 (_mm_cmpestrz, int, __m128i, int, __m128i, int, 1)
-
-/* bmmintrin.h (SSE5). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("sse5")
-#endif
-#include <bmmintrin.h>
-test_1 (_mm_roti_epi8, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi16, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi32, __m128i, __m128i, 1)
-test_1 (_mm_roti_epi64, __m128i, __m128i, 1)
-
-/* wmmintrin.h (AES/PCLMUL). */
-#ifdef DIFFERENT_PRAGMAS
-#pragma GCC target ("aes,pclmul")
-#endif
-#include <wmmintrin.h>
-test_1 (_mm_aeskeygenassist_si128, __m128i, __m128i, 1)
-test_2 (_mm_clmulepi64_si128, __m128i, __m128i, __m128i, 1)
-
-/* mmintrin-common.h */
-test_1 (_mm_round_pd, __m128d, __m128d, 1)
-test_1 (_mm_round_ps, __m128, __m128, 1)
-test_2 (_mm_round_sd, __m128d, __m128d, __m128d, 1)
-test_2 (_mm_round_ss, __m128, __m128, __m128, 1)
#define __builtin_ia32_protqi(A, B) __builtin_ia32_protqi(A,1)
-#pragma GCC target ("3dnow,sse4,sse5,aes,pclmul")
+#pragma GCC target ("3dnow,sse4,sse4a,aes,pclmul")
#include <wmmintrin.h>
-#include <bmmintrin.h>
#include <smmintrin.h>
#include <mm3dnow.h>
+++ /dev/null
-#include <stdlib.h>
-
-#include "cpuid.h"
-
-static void sse5_test (void);
-
-int
-main ()
-{
- unsigned int eax, ebx, ecx, edx;
-
- if (!__get_cpuid (0x80000001, &eax, &ebx, &ecx, &edx))
- return 0;
-
- /* Run SSE5 test only if host has SSE5 support. */
- if (ecx & bit_SSE5)
- sse5_test ();
-
- exit (0);
-}
+++ /dev/null
-/* Test that the compiler properly optimizes floating point multiply and add
- instructions vector into fmaddps on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -mfused-madd -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef float __m128 __attribute__ ((__vector_size__ (16), __may_alias__));
-typedef double __m128d __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128 f_align;
- __m128d d_align;
- float f[SIZE];
- double d[SIZE];
-} a, b, c, d;
-
-void
-flt_mul_add (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.f[i] = (b.f[i] * c.f[i]) + d.f[i];
-}
-
-void
-dbl_mul_add (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.d[i] = (b.d[i] * c.d[i]) + d.d[i];
-}
-
-void
-flt_mul_sub (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.f[i] = (b.f[i] * c.f[i]) - d.f[i];
-}
-
-void
-dbl_mul_sub (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.d[i] = (b.d[i] * c.d[i]) - d.d[i];
-}
-
-void
-flt_neg_mul_add (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.f[i] = (-(b.f[i] * c.f[i])) + d.f[i];
-}
-
-void
-dbl_neg_mul_add (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.d[i] = (-(b.d[i] * c.d[i])) + d.d[i];
-}
-
-int main ()
-{
- flt_mul_add ();
- flt_mul_sub ();
- flt_neg_mul_add ();
-
- dbl_mul_add ();
- dbl_mul_sub ();
- dbl_neg_mul_add ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "fmaddps" } } */
-/* { dg-final { scan-assembler "fmaddpd" } } */
-/* { dg-final { scan-assembler "fmsubps" } } */
-/* { dg-final { scan-assembler "fmsubpd" } } */
-/* { dg-final { scan-assembler "fnmaddps" } } */
-/* { dg-final { scan-assembler "fnmaddpd" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes floating point multiply and add
- instructions into fmaddss, fmsubss, fnmaddss, fnmsubss on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -mfused-madd" } */
-
-extern void exit (int);
-
-float
-flt_mul_add (float a, float b, float c)
-{
- return (a * b) + c;
-}
-
-double
-dbl_mul_add (double a, double b, double c)
-{
- return (a * b) + c;
-}
-
-float
-flt_mul_sub (float a, float b, float c)
-{
- return (a * b) - c;
-}
-
-double
-dbl_mul_sub (double a, double b, double c)
-{
- return (a * b) - c;
-}
-
-float
-flt_neg_mul_add (float a, float b, float c)
-{
- return (-(a * b)) + c;
-}
-
-double
-dbl_neg_mul_add (double a, double b, double c)
-{
- return (-(a * b)) + c;
-}
-
-float
-flt_neg_mul_sub (float a, float b, float c)
-{
- return (-(a * b)) - c;
-}
-
-double
-dbl_neg_mul_sub (double a, double b, double c)
-{
- return (-(a * b)) - c;
-}
-
-float f[10] = { 2, 3, 4 };
-double d[10] = { 2, 3, 4 };
-
-int main ()
-{
- f[3] = flt_mul_add (f[0], f[1], f[2]);
- f[4] = flt_mul_sub (f[0], f[1], f[2]);
- f[5] = flt_neg_mul_add (f[0], f[1], f[2]);
- f[6] = flt_neg_mul_sub (f[0], f[1], f[2]);
-
- d[3] = dbl_mul_add (d[0], d[1], d[2]);
- d[4] = dbl_mul_sub (d[0], d[1], d[2]);
- d[5] = dbl_neg_mul_add (d[0], d[1], d[2]);
- d[6] = dbl_neg_mul_sub (d[0], d[1], d[2]);
- exit (0);
-}
-
-/* { dg-final { scan-assembler "fmaddss" } } */
-/* { dg-final { scan-assembler "fmaddsd" } } */
-/* { dg-final { scan-assembler "fmsubss" } } */
-/* { dg-final { scan-assembler "fmsubsd" } } */
-/* { dg-final { scan-assembler "fnmaddss" } } */
-/* { dg-final { scan-assembler "fnmaddsd" } } */
-/* { dg-final { scan-assembler "fnmsubss" } } */
-/* { dg-final { scan-assembler "fnmsubsd" } } */
+++ /dev/null
-/* { dg-do run } */
-/* { dg-require-effective-target sse5 } */
-/* { dg-options "-O2 -msse5" } */
-
-#include "sse5-check.h"
-
-#include <bmmintrin.h>
-#include <string.h>
-
-#define NUM 10
-
-union
-{
- __m128i x[NUM];
- signed char ssi[NUM * 16];
- short si[NUM * 8];
- int li[NUM * 4];
- long long lli[NUM * 2];
-} dst, res, src1;
-
-static void
-init_sbyte ()
-{
- int i;
- for (i=0; i < NUM * 16; i++)
- src1.ssi[i] = i;
-}
-
-static void
-init_sword ()
-{
- int i;
- for (i=0; i < NUM * 8; i++)
- src1.si[i] = i;
-}
-
-
-static void
-init_sdword ()
-{
- int i;
- for (i=0; i < NUM * 4; i++)
- src1.li[i] = i;
-}
-
-static int
-check_sbyte2word ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 16; i = i + 16)
- {
- for (j = 0; j < 8; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ;
- if (res.si[s] != dst.si[s])
- check_fails++;
- }
- }
-}
-
-static int
-check_sbyte2dword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 16; i = i + 16)
- {
- for (j = 0; j < 4; j++)
- {
- t = i + (4 * j);
- s = (i / 4) + j;
- res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2]
- + src1.ssi[t + 3]);
- if (res.li[s] != dst.li[s])
- check_fails++;
- }
- }
- return check_fails++;
-}
-
-static int
-check_sbyte2qword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 16; i = i + 16)
- {
- for (j = 0; j < 2; j++)
- {
- t = i + (8 * j);
- s = (i / 8) + j;
- res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2]
- + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5])
- + (src1.ssi[t + 6] + src1.ssi[t + 7]));
- if (res.lli[s] != dst.lli[s])
- check_fails++;
- }
- }
- return check_fails++;
-}
-
-static int
-check_sword2dword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < (NUM * 8); i = i + 8)
- {
- for (j = 0; j < 4; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.li[s] = src1.si[t] + src1.si[t + 1] ;
- if (res.li[s] != dst.li[s])
- check_fails++;
- }
- }
-}
-
-static int
-check_sword2qword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 8; i = i + 8)
- {
- for (j = 0; j < 2; j++)
- {
- t = i + (4 * j);
- s = (i / 4) + j;
- res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2]
- + src1.si[t + 3]);
- if (res.lli[s] != dst.lli[s])
- check_fails++;
- }
- }
- return check_fails++;
-}
-
-static int
-check_dword2qword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < (NUM * 4); i = i + 4)
- {
- for (j = 0; j < 2; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.lli[s] = src1.li[t] + src1.li[t + 1] ;
- if (res.lli[s] != dst.lli[s])
- check_fails++;
- }
- }
-}
-
-static void
-sse5_test (void)
-{
- int i;
-
- /* Check haddbw */
- init_sbyte ();
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_haddw_epi8 (src1.x[i]);
-
- if (check_sbyte2word())
- abort ();
-
- /* Check haddbd */
- for (i = 0; i < (NUM ); i++)
- dst.x[i] = _mm_haddd_epi8 (src1.x[i]);
-
- if (check_sbyte2dword())
- abort ();
-
- /* Check haddbq */
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_haddq_epi8 (src1.x[i]);
-
- if (check_sbyte2qword())
- abort ();
-
- /* Check haddwd */
- init_sword ();
-
- for (i = 0; i < (NUM ); i++)
- dst.x[i] = _mm_haddd_epi16 (src1.x[i]);
-
- if (check_sword2dword())
- abort ();
-
- /* Check haddbwq */
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_haddq_epi16 (src1.x[i]);
-
- if (check_sword2qword())
- abort ();
-
- /* Check haddq */
- init_sdword ();
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_haddq_epi32 (src1.x[i]);
-
- if (check_dword2qword())
- abort ();
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-require-effective-target sse5 } */
-/* { dg-options "-O2 -msse5" } */
-
-#include "sse5-check.h"
-
-#include <bmmintrin.h>
-#include <string.h>
-
-#define NUM 10
-
-union
-{
- __m128i x[NUM];
- unsigned char ssi[NUM * 16];
- unsigned short si[NUM * 8];
- unsigned int li[NUM * 4];
- unsigned long long lli[NUM * 2];
-} dst, res, src1;
-
-static void
-init_byte ()
-{
- int i;
- for (i=0; i < NUM * 16; i++)
- src1.ssi[i] = i;
-}
-
-static void
-init_word ()
-{
- int i;
- for (i=0; i < NUM * 8; i++)
- src1.si[i] = i;
-}
-
-
-static void
-init_dword ()
-{
- int i;
- for (i=0; i < NUM * 4; i++)
- src1.li[i] = i;
-}
-
-static int
-check_byte2word ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 16; i = i + 16)
- {
- for (j = 0; j < 8; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.si[s] = src1.ssi[t] + src1.ssi[t + 1] ;
- if (res.si[s] != dst.si[s])
- check_fails++;
- }
- }
-}
-
-static int
-check_byte2dword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 16; i = i + 16)
- {
- for (j = 0; j < 4; j++)
- {
- t = i + (4 * j);
- s = (i / 4) + j;
- res.li[s] = (src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2]
- + src1.ssi[t + 3]);
- if (res.li[s] != dst.li[s])
- check_fails++;
- }
- }
- return check_fails++;
-}
-
-static int
-check_byte2qword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 16; i = i + 16)
- {
- for (j = 0; j < 2; j++)
- {
- t = i + (8 * j);
- s = (i / 8) + j;
- res.lli[s] = ((src1.ssi[t] + src1.ssi[t + 1]) + (src1.ssi[t + 2]
- + src1.ssi[t + 3])) + ((src1.ssi[t + 4] + src1.ssi[t +5])
- + (src1.ssi[t + 6] + src1.ssi[t + 7]));
- if (res.lli[s] != dst.lli[s])
- check_fails++;
- }
- }
- return check_fails++;
-}
-
-static int
-check_word2dword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < (NUM * 8); i = i + 8)
- {
- for (j = 0; j < 4; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.li[s] = src1.si[t] + src1.si[t + 1] ;
- if (res.li[s] != dst.li[s])
- check_fails++;
- }
- }
-}
-
-static int
-check_word2qword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 8; i = i + 8)
- {
- for (j = 0; j < 2; j++)
- {
- t = i + (4 * j);
- s = (i / 4) + j;
- res.lli[s] = (src1.si[t] + src1.si[t + 1]) + (src1.si[t + 2]
- + src1.si[t + 3]);
- if (res.lli[s] != dst.lli[s])
- check_fails++;
- }
- }
- return check_fails++;
-}
-
-static int
-check_dword2qword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < (NUM * 4); i = i + 4)
- {
- for (j = 0; j < 2; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.lli[s] = src1.li[t] + src1.li[t + 1] ;
- if (res.lli[s] != dst.lli[s])
- check_fails++;
- }
- }
-}
-
-static void
-sse5_test (void)
-{
- int i;
-
- /* Check haddubw */
- init_byte ();
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_haddw_epu8 (src1.x[i]);
-
- if (check_byte2word())
- abort ();
-
- /* Check haddubd */
- for (i = 0; i < (NUM ); i++)
- dst.x[i] = _mm_haddd_epu8 (src1.x[i]);
-
- if (check_byte2dword())
- abort ();
-
- /* Check haddubq */
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_haddq_epu8 (src1.x[i]);
-
- if (check_byte2qword())
- abort ();
-
- /* Check hadduwd */
- init_word ();
-
- for (i = 0; i < (NUM ); i++)
- dst.x[i] = _mm_haddd_epu16 (src1.x[i]);
-
- if (check_word2dword())
- abort ();
-
- /* Check haddbuwq */
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_haddq_epu16 (src1.x[i]);
-
- if (check_word2qword())
- abort ();
-
- /* Check hadudq */
- init_dword ();
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_haddq_epu32 (src1.x[i]);
-
- if (check_dword2qword())
- abort ();
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-require-effective-target sse5 } */
-/* { dg-options "-O2 -msse5" } */
-
-#include "sse5-check.h"
-
-#include <bmmintrin.h>
-#include <string.h>
-
-#define NUM 10
-
-union
-{
- __m128i x[NUM];
- signed char ssi[NUM * 16];
- short si[NUM * 8];
- int li[NUM * 4];
- long long lli[NUM * 2];
-} dst, res, src1;
-
-static void
-init_sbyte ()
-{
- int i;
- for (i=0; i < NUM * 16; i++)
- src1.ssi[i] = i;
-}
-
-static void
-init_sword ()
-{
- int i;
- for (i=0; i < NUM * 8; i++)
- src1.si[i] = i;
-}
-
-
-static void
-init_sdword ()
-{
- int i;
- for (i=0; i < NUM * 4; i++)
- src1.li[i] = i;
-}
-
-static int
-check_sbyte2word ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < NUM * 16; i = i + 16)
- {
- for (j = 0; j < 8; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.si[s] = src1.ssi[t] - src1.ssi[t + 1] ;
- if (res.si[s] != dst.si[s])
- check_fails++;
- }
- }
-}
-
-static int
-check_sword2dword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < (NUM * 8); i = i + 8)
- {
- for (j = 0; j < 4; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.li[s] = src1.si[t] - src1.si[t + 1] ;
- if (res.li[s] != dst.li[s])
- check_fails++;
- }
- }
-}
-
-static int
-check_dword2qword ()
-{
- int i, j, s, t, check_fails = 0;
- for (i = 0; i < (NUM * 4); i = i + 4)
- {
- for (j = 0; j < 2; j++)
- {
- t = i + (2 * j);
- s = (i / 2) + j;
- res.lli[s] = src1.li[t] - src1.li[t + 1] ;
- if (res.lli[s] != dst.lli[s])
- check_fails++;
- }
- }
-}
-
-static void
-sse5_test (void)
-{
- int i;
-
- /* Check hsubbw */
- init_sbyte ();
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_hsubw_epi8 (src1.x[i]);
-
- if (check_sbyte2word())
- abort ();
-
-
- /* Check hsubwd */
- init_sword ();
-
- for (i = 0; i < (NUM ); i++)
- dst.x[i] = _mm_hsubd_epi16 (src1.x[i]);
-
- if (check_sword2dword())
- abort ();
-
- /* Check hsubdq */
- init_sdword ();
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_hsubq_epi32 (src1.x[i]);
-
- if (check_dword2qword())
- abort ();
-}
+++ /dev/null
-/* Test that the compiler properly optimizes vector 32-bit integer point
- multiply and add instructions vector into pmacsdd on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i align;
- int i[SIZE];
-} a, b, c, d;
-
-void
-int_mul_add (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.i[i] = (b.i[i] * c.i[i]) + d.i[i];
-}
-
-int main ()
-{
- int_mul_add ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "pmacsdd" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes floating point multiply and add
- instructions vector into pmacsdd/etc. on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i i_align;
- int i32[SIZE];
- long i64[SIZE];
-} a, b, c, d;
-
-void
-imul32_to_64 (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.i64[i] = ((long)b.i32[i]) * ((long)c.i32[i]);
-}
-
-int main ()
-{
- imul32_to_64 ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "pmacsdql" } } */
-/* { dg-final { scan-assembler "pmacsdqh" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes floating point multiply and add
- instructions vector into pmacsdd/etc. on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i i_align;
- long i64[SIZE];
-} a, b, c, d;
-
-void
-imul64 (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.i64[i] = b.i64[i] * c.i64[i];
-}
-
-int main ()
-{
- imul64 ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "pmacsdd" } } */
-/* { dg-final { scan-assembler "phadddq" } } */
-/* { dg-final { scan-assembler "pmacsdql" } } */
+++ /dev/null
-/* { dg-do run } */
-/* { dg-require-effective-target sse5 } */
-/* { dg-options "-O2 -msse5" } */
-
-#include "sse5-check.h"
-
-#include <bmmintrin.h>
-#include <string.h>
-
-#define NUM 20
-
-union
-{
- __m128 x[NUM];
- float f[NUM * 4];
- __m128d y[NUM];
- double d[NUM * 2];
-} dst, res, src1, src2, src3;
-
-
-/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate
- product is not rounded, only the addition is rounded. */
-
-static void
-init_maccps ()
-{
- int i;
- for (i = 0; i < NUM * 4; i++)
- {
- src1.f[i] = i;
- src2.f[i] = i + 10;
- src3.f[i] = i + 20;
- }
-}
-
-static void
-init_maccpd ()
-{
- int i;
- for (i = 0; i < NUM * 4; i++)
- {
- src1.d[i] = i;
- src2.d[i] = i + 10;
- src3.d[i] = i + 20;
- }
-}
-
-static int
-check_maccps ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 4; i = i + 4)
- for (j = 0; j < 4; j++)
- {
- res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j];
- if (dst.f[i + j] != res.f[i + j])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_maccpd ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 2; i = i + 2)
- for (j = 0; j < 2; j++)
- {
- res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j];
- if (dst.d[i + j] != res.d[i + j])
- check_fails++;
- }
- return check_fails++;
-}
-
-
-static int
-check_maccss ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 4; i= i + 4)
- {
- res.f[i] = (src1.f[i] * src2.f[i]) + src3.f[i];
- if (dst.f[i] != res.f[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_maccsd ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 2; i = i + 2)
- {
- res.d[i] = (src1.d[i] * src2.d[i]) + src3.d[i];
- if (dst.d[i] != res.d[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static void
-sse5_test (void)
-{
- int i;
-
- /* Check maccps */
- init_maccps ();
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_macc_ps (src1.x[i], src2.x[i], src3.x[i]);
-
- if (check_maccps ())
- abort ();
-
- /* check maccss */
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_macc_ss (src1.x[i], src2.x[i], src3.x[i]);
-
- if (check_maccss ())
- abort ();
-
- /* Check maccpd */
- init_maccpd ();
-
- for (i = 0; i < NUM; i++)
- dst.y[i] = _mm_macc_pd (src1.y[i], src2.y[i], src3.y[i]);
-
- if (check_maccpd ())
- abort ();
-
- /* Check maccps */
- for (i = 0; i < NUM; i++)
- dst.y[i] = _mm_macc_sd (src1.y[i], src2.y[i], src3.y[i]);
-
- if (check_maccsd ())
- abort ();
-
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-require-effective-target sse5 } */
-/* { dg-options "-O2 -msse5" } */
-
-#include "sse5-check.h"
-
-#include <bmmintrin.h>
-#include <string.h>
-
-#define NUM 20
-
-union
-{
- __m128 x[NUM];
- float f[NUM * 4];
- __m128d y[NUM];
- double d[NUM * 2];
-} dst, res, src1, src2, src3;
-
-/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate
- product is not rounded, only the addition is rounded. */
-
-static void
-init_msubps ()
-{
- int i;
- for (i = 0; i < NUM * 4; i++)
- {
- src1.f[i] = i;
- src2.f[i] = i + 10;
- src3.f[i] = i + 20;
- }
-}
-
-static void
-init_msubpd ()
-{
- int i;
- for (i = 0; i < NUM * 4; i++)
- {
- src1.d[i] = i;
- src2.d[i] = i + 10;
- src3.d[i] = i + 20;
- }
-}
-
-static int
-check_msubps ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 4; i = i + 4)
- for (j = 0; j < 4; j++)
- {
- res.f[i + j] = (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j];
- if (dst.f[i + j] != res.f[i + j])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_msubpd ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 2; i = i + 2)
- for (j = 0; j < 2; j++)
- {
- res.d[i + j] = (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j];
- if (dst.d[i + j] != res.d[i + j])
- check_fails++;
- }
- return check_fails++;
-}
-
-
-static int
-check_msubss ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 4; i = i + 4)
- {
- res.f[i] = (src1.f[i] * src2.f[i]) - src3.f[i];
- if (dst.f[i] != res.f[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_msubsd ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 2; i = i + 2)
- {
- res.d[i] = (src1.d[i] * src2.d[i]) - src3.d[i];
- if (dst.d[i] != res.d[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static void
-sse5_test (void)
-{
- int i;
-
- /* Check msubps */
- init_msubps ();
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_msub_ps (src1.x[i], src2.x[i], src3.x[i]);
-
- if (check_msubps ())
- abort ();
-
- /* check msubss */
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_msub_ss (src1.x[i], src2.x[i], src3.x[i]);
-
- if (check_msubss ())
- abort ();
-
- /* Check msubpd */
- init_msubpd ();
-
- for (i = 0; i < NUM; i++)
- dst.y[i] = _mm_msub_pd (src1.y[i], src2.y[i], src3.y[i]);
-
- if (check_msubpd ())
- abort ();
-
- /* Check msubps */
- for (i = 0; i < NUM; i++)
- dst.y[i] = _mm_msub_sd (src1.y[i], src2.y[i], src3.y[i]);
-
- if (check_msubsd ())
- abort ();
-
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-require-effective-target sse5 } */
-/* { dg-options "-O2 -msse5" } */
-
-#include "sse5-check.h"
-
-#include <bmmintrin.h>
-#include <string.h>
-
-#define NUM 20
-
-union
-{
- __m128 x[NUM];
- float f[NUM * 4];
- __m128d y[NUM];
- double d[NUM * 2];
-} dst, res, src1, src2, src3;
-
-/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate
- product is not rounded, only the addition is rounded. */
-
-static void
-init_nmaccps ()
-{
- int i;
- for (i = 0; i < NUM * 4; i++)
- {
- src1.f[i] = i;
- src2.f[i] = i + 10;
- src3.f[i] = i + 20;
- }
-}
-
-static void
-init_nmaccpd ()
-{
- int i;
- for (i = 0; i < NUM * 4; i++)
- {
- src1.d[i] = i;
- src2.d[i] = i + 10;
- src3.d[i] = i + 20;
- }
-}
-
-static int
-check_nmaccps ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 4; i = i + 4)
- for (j = 0; j < 4; j++)
- {
- res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) + src3.f[i + j];
- if (dst.f[i + j] != res.f[i + j])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_nmaccpd ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 2; i = i + 2)
- for (j = 0; j < 2; j++)
- {
- res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) + src3.d[i + j];
- if (dst.d[i + j] != res.d[i + j])
- check_fails++;
- }
- return check_fails++;
-}
-
-
-static int
-check_nmaccss ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 4; i = i + 4)
- {
- res.f[i] = - (src1.f[i] * src2.f[i]) + src3.f[i];
- if (dst.f[i] != res.f[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_nmaccsd ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 2; i = i + 2)
- {
- res.d[i] = - (src1.d[i] * src2.d[i]) + src3.d[i];
- if (dst.d[i] != res.d[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static void
-sse5_test (void)
-{
- int i;
-
- /* Check nmaccps */
- init_nmaccps ();
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_nmacc_ps (src1.x[i], src2.x[i], src3.x[i]);
-
- if (check_nmaccps ())
- abort ();
-
- /* check nmaccss */
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_nmacc_ss (src1.x[i], src2.x[i], src3.x[i]);
-
- if (check_nmaccss ())
- abort ();
-
- /* Check nmaccpd */
- init_nmaccpd ();
-
- for (i = 0; i < NUM; i++)
- dst.y[i] = _mm_nmacc_pd (src1.y[i], src2.y[i], src3.y[i]);
-
- if (check_nmaccpd ())
- abort ();
-
- /* Check nmaccps */
- for (i = 0; i < NUM; i++)
- dst.y[i] = _mm_nmacc_sd (src1.y[i], src2.y[i], src3.y[i]);
-
- if (check_nmaccsd ())
- abort ();
-
-}
+++ /dev/null
-/* { dg-do run } */
-/* { dg-require-effective-target sse5 } */
-/* { dg-options "-O2 -msse5" } */
-
-#include "sse5-check.h"
-
-#include <bmmintrin.h>
-#include <string.h>
-
-#define NUM 20
-
-union
-{
- __m128 x[NUM];
- float f[NUM * 4];
- __m128d y[NUM];
- double d[NUM * 2];
-} dst, res, src1, src2, src3;
-
-/* Note that in macc*,msub*,mnmacc* and mnsub* instructions, the intermdediate
- product is not rounded, only the addition is rounded. */
-
-static void
-init_nmsubps ()
-{
- int i;
- for (i = 0; i < NUM * 4; i++)
- {
- src1.f[i] = i;
- src2.f[i] = i + 10;
- src3.f[i] = i + 20;
- }
-}
-
-static void
-init_nmsubpd ()
-{
- int i;
- for (i = 0; i < NUM * 4; i++)
- {
- src1.d[i] = i;
- src2.d[i] = i + 10;
- src3.d[i] = i + 20;
- }
-}
-
-static int
-check_nmsubps ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 4; i = i + 4)
- for (j = 0; j < 4; j++)
- {
- res.f[i + j] = - (src1.f[i + j] * src2.f[i + j]) - src3.f[i + j];
- if (dst.f[i + j] != res.f[i + j])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_nmsubpd ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 2; i = i + 2)
- for (j = 0; j < 2; j++)
- {
- res.d[i + j] = - (src1.d[i + j] * src2.d[i + j]) - src3.d[i + j];
- if (dst.d[i + j] != res.d[i + j])
- check_fails++;
- }
- return check_fails++;
-}
-
-
-static int
-check_nmsubss ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 4; i = i + 4)
- {
- res.f[i] = - (src1.f[i] * src2.f[i]) - src3.f[i];
- if (dst.f[i] != res.f[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_nmsubsd ()
-{
- int i, j, check_fails = 0;
- for (i = 0; i < NUM * 2; i = i + 2)
- {
- res.d[i] = - (src1.d[i] * src2.d[i]) - src3.d[i];
- if (dst.d[i] != res.d[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static void
-sse5_test (void)
-{
- int i;
-
- /* Check nmsubps */
- init_nmsubps ();
-
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_nmsub_ps (src1.x[i], src2.x[i], src3.x[i]);
-
- if (check_nmsubps (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4]))
- abort ();
-
- /* check nmsubss */
- for (i = 0; i < NUM; i++)
- dst.x[i] = _mm_nmsub_ss (src1.x[i], src2.x[i], src3.x[i]);
-
- if (check_nmsubss (&dst.x[i], &src1.f[i * 4], &src2.f[i * 4], &src3.f[i * 4]))
- abort ();
-
- /* Check nmsubpd */
- init_nmsubpd ();
-
- for (i = 0; i < NUM; i++)
- dst.y[i] = _mm_nmsub_pd (src1.y[i], src2.y[i], src3.y[i]);
-
- if (check_nmsubpd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2]))
- abort ();
-
- /* Check nmsubps */
- for (i = 0; i < NUM; i++)
- dst.y[i] = _mm_nmsub_sd (src1.y[i], src2.y[i], src3.y[i]);
-
- if (check_nmsubsd (&dst.y[i], &src1.d[i * 2], &src2.d[i * 2], &src3.d[i * 2]))
- abort ();
-
-}
+++ /dev/null
-/* Test that the compiler properly optimizes conditional floating point moves
- into the pcmov instruction on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5" } */
-
-extern void exit (int);
-
-double dbl_test (double a, double b, double c, double d)
-{
- return (a > b) ? c : d;
-}
-
-double dbl_a = 1, dbl_b = 2, dbl_c = 3, dbl_d = 4, dbl_e;
-
-int main()
-{
- dbl_e = dbl_test (dbl_a, dbl_b, dbl_c, dbl_d);
- exit (0);
-}
-
-/* { dg-final { scan-assembler "pcmov" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes conditional floating point moves
- into the pcmov instruction on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5" } */
-
-extern void exit (int);
-
-float flt_test (float a, float b, float c, float d)
-{
- return (a > b) ? c : d;
-}
-
-float flt_a = 1, flt_b = 2, flt_c = 3, flt_d = 4, flt_e;
-
-int main()
-{
- flt_e = flt_test (flt_a, flt_b, flt_c, flt_d);
- exit (0);
-}
-
-/* { dg-final { scan-assembler "pcmov" } } */
+++ /dev/null
-/* { dg-do run } */
-/* { dg-require-effective-target sse5 } */
-/* { dg-options "-O2 -msse5" } */
-
-#include "sse5-check.h"
-
-#include <bmmintrin.h>
-#include <string.h>
-
-union
-{
- __m128 x[2];
- __m128d y[2];
- __m128i z[2];
- float f[8];
- double d[4];
- int i[8];
- long li[4];
-} dst, res, src1, src2, src3;
-
-
-static void
-init_ddata ()
-{
- int i;
- for (i = 0; i < 4; i++)
- {
- src1.d[i] = i;
- src2.d[i] = i + 2;
- }
-
- src3.li[0] = 3;
- src3.li[1] = 0;
- src3.li[2] = 1;
- src3.li[3] = 2;
-
- res.d[0] = 3.0;
- res.d[1] = 0.0;
- res.d[2] = 3.0;
- res.d[3] = 4.0;
-}
-
-
-static void
-init_fdata ()
-{
- int i;
- for (i = 0; i < 8; i++)
- {
- src1.f[i] = i;
- src2.f[i] = i + 2;
- }
-
- src3.i[0] = 7;
- src3.i[1] = 5;
- src3.i[2] = 1;
- src3.i[3] = 2;
- src3.i[4] = 0;
- src3.i[5] = 4;
- src3.i[6] = 3;
- src3.i[7] = 6;
-
- res.f[0] = 5.0;
- res.f[1] = 3.0;
- res.f[2] = 1.0;
- res.f[3] = 2.0;
- res.f[4] = 4.0;
- res.f[5] = 6.0;
- res.f[6] = 7.0;
- res.f[7] = 8.0;
-}
-
-static int
-check_permpd ()
-{
- int i, check_fails = 0;
-
- for (i = 0; i < 4; i++)
- {
- if (res.d[i] != dst.d[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static int
-check_permps ()
-{
- int i, check_fails = 0;
-
- for (i = 0; i < 8; i++)
- {
- if (res.f[i] != dst.f[i])
- check_fails++;
- }
- return check_fails++;
-}
-
-static void
-sse5_test (void)
-{
- int i;
- init_ddata();
-
- for (i = 0; i < 2; i++)
- dst.y[i] = _mm_perm_pd (src1.y[i], src2.y[i], src3.z[i]);
-
- if (check_permpd ())
- abort ();
-
- init_fdata();
-
- for (i = 0; i < 2; i++)
- dst.x[i] = _mm_perm_ps (src1.x[i], src2.x[i], src3.z[i]);
-
- if (check_permps ())
- abort ();
-}
-
-
+++ /dev/null
-/* Test that the compiler properly optimizes vector rotate instructions vector
- into prot on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i i_align;
- unsigned u32[SIZE];
-} a, b, c;
-
-void
-left_rotate32 (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.u32[i] = (b.u32[i] << ((sizeof (int) * 8) - 4)) | (b.u32[i] >> 4);
-}
-
-int
-main ()
-{
- left_rotate32 ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "protd" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes vector rotate instructions vector
- into prot on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i i_align;
- unsigned u32[SIZE];
-} a, b, c;
-
-void
-right_rotate32_b (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - 4)) | (b.u32[i] << 4);
-}
-
-int
-main ()
-{
- right_rotate ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "prot" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes vector rotate instructions vector
- into prot on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i i_align;
- unsigned u32[SIZE];
-} a, b, c;
-
-void
-vector_rotate32 (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.u32[i] = (b.u32[i] >> ((sizeof (int) * 8) - c.u32[i])) | (b.u32[i] << c.u32[i]);
-}
-
-int main ()
-{
- vector_rotate32 ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "protd" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes vector shift instructions into
- psha/pshl on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i i_align;
- int i32[SIZE];
- unsigned u32[SIZE];
-} a, b, c;
-
-void
-left_shift32 (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.i32[i] = b.i32[i] << c.i32[i];
-}
-
-int main ()
-{
- left_shfit32 ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "pshad" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes vector shift instructions into
- psha/pshl on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i i_align;
- int i32[SIZE];
- unsigned u32[SIZE];
-} a, b, c;
-
-void
-right_sign_shift32 (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.i32[i] = b.i32[i] >> c.i32[i];
-}
-
-int main ()
-{
- right_sign_shfit32 ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "pshad" } } */
+++ /dev/null
-/* Test that the compiler properly optimizes vector shift instructions into
- psha/pshl on SSE5 systems. */
-
-/* { dg-do compile } */
-/* { dg-require-effective-target lp64 } */
-/* { dg-options "-O2 -msse5 -ftree-vectorize" } */
-
-extern void exit (int);
-
-typedef long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
-
-#define SIZE 10240
-
-union {
- __m128i i_align;
- int i32[SIZE];
- unsigned u32[SIZE];
-} a, b, c;
-
-void
-right_uns_shift32 (void)
-{
- int i;
-
- for (i = 0; i < SIZE; i++)
- a.u32[i] = b.u32[i] >> c.i32[i];
-}
-
-int main ()
-{
- right_uns_shfit32 ();
- exit (0);
-}
-
-/* { dg-final { scan-assembler "pshld" } } */
if (gimple_in_ssa_p (cfun))
release_defs (stmt);
+ unlink_stmt_vdef (stmt);
gsi_remove (&i, true);
}
OSDN Git Service
