1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003, 2005, 2006, 2007, 2008, 2009, 2010, 2011
4 Free Software Foundation, Inc.
6 This file is part of GDB.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "solib-svr4.h"
32 #include "floatformat.h"
34 #include "reggroups.h"
37 #include "dummy-frame.h"
39 #include "dwarf2-frame.h"
40 #include "dwarf2loc.h"
42 #include "frame-base.h"
43 #include "frame-unwind.h"
45 #include "arch-utils.h"
52 #include "gdb_assert.h"
54 #include "xtensa-isa.h"
55 #include "xtensa-tdep.h"
56 #include "xtensa-config.h"
59 static int xtensa_debug_level = 0;
61 #define DEBUGWARN(args...) \
62 if (xtensa_debug_level > 0) \
63 fprintf_unfiltered (gdb_stdlog, "(warn ) " args)
65 #define DEBUGINFO(args...) \
66 if (xtensa_debug_level > 1) \
67 fprintf_unfiltered (gdb_stdlog, "(info ) " args)
69 #define DEBUGTRACE(args...) \
70 if (xtensa_debug_level > 2) \
71 fprintf_unfiltered (gdb_stdlog, "(trace) " args)
73 #define DEBUGVERB(args...) \
74 if (xtensa_debug_level > 3) \
75 fprintf_unfiltered (gdb_stdlog, "(verb ) " args)
78 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
79 #define SP_ALIGNMENT 16
82 /* On Windowed ABI, we use a6 through a11 for passing arguments
83 to a function called by GDB because CALL4 is used. */
84 #define ARGS_NUM_REGS 6
85 #define REGISTER_SIZE 4
88 /* Extract the call size from the return address or PS register. */
89 #define PS_CALLINC_SHIFT 16
90 #define PS_CALLINC_MASK 0x00030000
91 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
92 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
94 /* On TX, hardware can be configured without Exception Option.
95 There is no PS register in this case. Inside XT-GDB, let us treat
96 it as a virtual read-only register always holding the same value. */
99 /* ABI-independent macros. */
100 #define ARG_NOF(gdbarch) \
101 (gdbarch_tdep (gdbarch)->call_abi \
102 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
103 #define ARG_1ST(gdbarch) \
104 (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only \
105 ? (gdbarch_tdep (gdbarch)->a0_base + C0_ARGS) \
106 : (gdbarch_tdep (gdbarch)->a0_base + 6))
108 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
109 indicates that the instruction is an ENTRY instruction. */
111 #define XTENSA_IS_ENTRY(gdbarch, op1) \
112 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
113 ? ((op1) == 0x6c) : ((op1) == 0x36))
115 #define XTENSA_ENTRY_LENGTH 3
117 /* windowing_enabled() returns true, if windowing is enabled.
118 WOE must be set to 1; EXCM to 0.
119 Note: We assume that EXCM is always 0 for XEA1. */
121 #define PS_WOE (1<<18)
122 #define PS_EXC (1<<4)
125 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
127 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
128 if (gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
131 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
134 /* Convert a live A-register number to the corresponding AR-register
137 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
139 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
142 arreg = a_regnum - tdep->a0_base;
143 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
144 arreg &= tdep->num_aregs - 1;
146 return arreg + tdep->ar_base;
149 /* Convert a live AR-register number to the corresponding A-register order
150 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
152 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
154 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
157 areg = ar_regnum - tdep->ar_base;
158 if (areg < 0 || areg >= tdep->num_aregs)
160 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
161 return (areg > 15) ? -1 : areg;
164 /* Read Xtensa register directly from the hardware. */
165 static inline unsigned long
166 xtensa_read_register (int regnum)
170 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
171 return (unsigned long) value;
174 /* Write Xtensa register directly to the hardware. */
176 xtensa_write_register (int regnum, ULONGEST value)
178 regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
181 /* Return the window size of the previous call to the function from which we
184 This function is used to extract the return value after a called function
185 has returned to the caller. On Xtensa, the register that holds the return
186 value (from the perspective of the caller) depends on what call
187 instruction was used. For now, we are assuming that the call instruction
188 precedes the current address, so we simply analyze the call instruction.
189 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
190 method to call the inferior function. */
193 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
195 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
200 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
202 /* Read the previous instruction (should be a call[x]{4|8|12}. */
203 read_memory (pc-3, buf, 3);
204 insn = extract_unsigned_integer (buf, 3, byte_order);
206 /* Decode call instruction:
208 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
209 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
211 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
212 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
214 if (byte_order == BFD_ENDIAN_LITTLE)
216 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
217 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
221 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
222 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
228 /* REGISTER INFORMATION */
230 /* Find register by name. */
232 xtensa_find_register_by_name (struct gdbarch *gdbarch, char *name)
236 for (i = 0; i < gdbarch_num_regs (gdbarch)
237 + gdbarch_num_pseudo_regs (gdbarch);
240 if (strcasecmp (gdbarch_tdep (gdbarch)->regmap[i].name, name) == 0)
246 /* Returns the name of a register. */
248 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
250 /* Return the name stored in the register map. */
251 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
252 + gdbarch_num_pseudo_regs (gdbarch))
253 return gdbarch_tdep (gdbarch)->regmap[regnum].name;
255 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
259 /* Return the type of a register. Create a new type, if necessary. */
262 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
264 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch);
266 /* Return signed integer for ARx and Ax registers. */
267 if ((regnum >= tdep->ar_base
268 && regnum < tdep->ar_base + tdep->num_aregs)
269 || (regnum >= tdep->a0_base
270 && regnum < tdep->a0_base + 16))
271 return builtin_type (gdbarch)->builtin_int;
273 if (regnum == gdbarch_pc_regnum (gdbarch)
274 || regnum == tdep->a0_base + 1)
275 return builtin_type (gdbarch)->builtin_data_ptr;
277 /* Return the stored type for all other registers. */
278 else if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)
279 + gdbarch_num_pseudo_regs (gdbarch))
281 xtensa_register_t* reg = &tdep->regmap[regnum];
283 /* Set ctype for this register (only the first time). */
287 struct ctype_cache *tp;
288 int size = reg->byte_size;
290 /* We always use the memory representation,
291 even if the register width is smaller. */
295 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
299 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
303 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
307 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
311 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
315 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
316 if (tp->size == size)
321 char *name = xmalloc (16);
322 tp = xmalloc (sizeof (struct ctype_cache));
323 tp->next = tdep->type_entries;
324 tdep->type_entries = tp;
327 sprintf (name, "int%d", size * 8);
329 = arch_integer_type (gdbarch, size * 8, 1, xstrdup (name));
332 reg->ctype = tp->virtual_type;
338 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
343 /* Return the 'local' register number for stubs, dwarf2, etc.
344 The debugging information enumerates registers starting from 0 for A0
345 to n for An. So, we only have to add the base number for A0. */
348 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
352 if (regnum >= 0 && regnum < 16)
353 return gdbarch_tdep (gdbarch)->a0_base + regnum;
356 i < gdbarch_num_regs (gdbarch) + gdbarch_num_pseudo_regs (gdbarch);
358 if (regnum == gdbarch_tdep (gdbarch)->regmap[i].target_number)
361 internal_error (__FILE__, __LINE__,
362 _("invalid dwarf/stabs register number %d"), regnum);
367 /* Write the bits of a masked register to the various registers.
368 Only the masked areas of these registers are modified; the other
369 fields are untouched. The size of masked registers is always less
370 than or equal to 32 bits. */
373 xtensa_register_write_masked (struct regcache *regcache,
374 xtensa_register_t *reg, const gdb_byte *buffer)
376 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
377 const xtensa_mask_t *mask = reg->mask;
379 int shift = 0; /* Shift for next mask (mod 32). */
380 int start, size; /* Start bit and size of current mask. */
382 unsigned int *ptr = value;
383 unsigned int regval, m, mem = 0;
385 int bytesize = reg->byte_size;
386 int bitsize = bytesize * 8;
389 DEBUGTRACE ("xtensa_register_write_masked ()\n");
391 /* Copy the masked register to host byte-order. */
392 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
393 for (i = 0; i < bytesize; i++)
396 mem |= (buffer[bytesize - i - 1] << 24);
401 for (i = 0; i < bytesize; i++)
404 mem |= (buffer[i] << 24);
409 /* We might have to shift the final value:
410 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
411 bytesize & 3 == x -> shift (4-x) * 8. */
413 *ptr = mem >> (((0 - bytesize) & 3) * 8);
417 /* Write the bits to the masked areas of the other registers. */
418 for (i = 0; i < mask->count; i++)
420 start = mask->mask[i].bit_start;
421 size = mask->mask[i].bit_size;
422 regval = mem >> shift;
424 if ((shift += size) > bitsize)
425 error (_("size of all masks is larger than the register"));
434 regval |= mem << (size - shift);
437 /* Make sure we have a valid register. */
438 r = mask->mask[i].reg_num;
439 if (r >= 0 && size > 0)
441 /* Don't overwrite the unmasked areas. */
443 regcache_cooked_read_unsigned (regcache, r, &old_val);
444 m = 0xffffffff >> (32 - size) << start;
446 regval = (regval & m) | (old_val & ~m);
447 regcache_cooked_write_unsigned (regcache, r, regval);
453 /* Read a tie state or mapped registers. Read the masked areas
454 of the registers and assemble them into a single value. */
457 xtensa_register_read_masked (struct regcache *regcache,
458 xtensa_register_t *reg, gdb_byte *buffer)
460 unsigned int value[(MAX_REGISTER_SIZE + 3) / 4];
461 const xtensa_mask_t *mask = reg->mask;
466 unsigned int *ptr = value;
467 unsigned int regval, mem = 0;
469 int bytesize = reg->byte_size;
470 int bitsize = bytesize * 8;
473 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
474 reg->name == 0 ? "" : reg->name);
476 /* Assemble the register from the masked areas of other registers. */
477 for (i = 0; i < mask->count; i++)
479 int r = mask->mask[i].reg_num;
483 regcache_cooked_read_unsigned (regcache, r, &val);
484 regval = (unsigned int) val;
489 start = mask->mask[i].bit_start;
490 size = mask->mask[i].bit_size;
495 regval &= (0xffffffff >> (32 - size));
497 mem |= regval << shift;
499 if ((shift += size) > bitsize)
500 error (_("size of all masks is larger than the register"));
511 mem = regval >> (size - shift);
518 /* Copy value to target byte order. */
522 if (gdbarch_byte_order (get_regcache_arch (regcache)) == BFD_ENDIAN_BIG)
523 for (i = 0; i < bytesize; i++)
527 buffer[bytesize - i - 1] = mem & 0xff;
531 for (i = 0; i < bytesize; i++)
535 buffer[i] = mem & 0xff;
541 /* Read pseudo registers. */
544 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
545 struct regcache *regcache,
549 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
551 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
552 regnum, xtensa_register_name (gdbarch, regnum));
554 if (regnum == gdbarch_num_regs (gdbarch)
555 + gdbarch_num_pseudo_regs (gdbarch) - 1)
556 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
558 /* Read aliases a0..a15, if this is a Windowed ABI. */
559 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
560 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
561 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
563 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
565 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
566 regnum = arreg_number (gdbarch, regnum,
567 extract_unsigned_integer (buf, 4, byte_order));
570 /* We can always read non-pseudo registers. */
571 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
572 regcache_raw_read (regcache, regnum, buffer);
575 /* We have to find out how to deal with priveleged registers.
576 Let's treat them as pseudo-registers, but we cannot read/write them. */
578 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
580 buffer[0] = (gdb_byte)0;
581 buffer[1] = (gdb_byte)0;
582 buffer[2] = (gdb_byte)0;
583 buffer[3] = (gdb_byte)0;
585 /* Pseudo registers. */
587 && regnum < gdbarch_num_regs (gdbarch)
588 + gdbarch_num_pseudo_regs (gdbarch))
590 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
591 xtensa_register_type_t type = reg->type;
592 int flags = gdbarch_tdep (gdbarch)->target_flags;
594 /* We cannot read Unknown or Unmapped registers. */
595 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
597 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
599 warning (_("cannot read register %s"),
600 xtensa_register_name (gdbarch, regnum));
605 /* Some targets cannot read TIE register files. */
606 else if (type == xtRegisterTypeTieRegfile)
608 /* Use 'fetch' to get register? */
609 if (flags & xtTargetFlagsUseFetchStore)
611 warning (_("cannot read register"));
615 /* On some targets (esp. simulators), we can always read the reg. */
616 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
618 warning (_("cannot read register"));
623 /* We can always read mapped registers. */
624 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
626 xtensa_register_read_masked (regcache, reg, buffer);
630 /* Assume that we can read the register. */
631 regcache_raw_read (regcache, regnum, buffer);
634 internal_error (__FILE__, __LINE__,
635 _("invalid register number %d"), regnum);
639 /* Write pseudo registers. */
642 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
643 struct regcache *regcache,
645 const gdb_byte *buffer)
647 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
649 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
650 regnum, xtensa_register_name (gdbarch, regnum));
652 if (regnum == gdbarch_num_regs (gdbarch)
653 + gdbarch_num_pseudo_regs (gdbarch) -1)
654 regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
656 /* Renumber register, if aliase a0..a15 on Windowed ABI. */
657 if (gdbarch_tdep (gdbarch)->isa_use_windowed_registers
658 && (regnum >= gdbarch_tdep (gdbarch)->a0_base)
659 && (regnum <= gdbarch_tdep (gdbarch)->a0_base + 15))
661 gdb_byte *buf = (gdb_byte *) alloca (MAX_REGISTER_SIZE);
664 regcache_raw_read (regcache,
665 gdbarch_tdep (gdbarch)->wb_regnum, buf);
666 regnum = arreg_number (gdbarch, regnum,
667 extract_unsigned_integer (buf, 4, byte_order));
670 /* We can always write 'core' registers.
671 Note: We might have converted Ax->ARy. */
672 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
673 regcache_raw_write (regcache, regnum, buffer);
675 /* We have to find out how to deal with priveleged registers.
676 Let's treat them as pseudo-registers, but we cannot read/write them. */
678 else if (regnum < gdbarch_tdep (gdbarch)->a0_base)
682 /* Pseudo registers. */
684 && regnum < gdbarch_num_regs (gdbarch)
685 + gdbarch_num_pseudo_regs (gdbarch))
687 xtensa_register_t *reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
688 xtensa_register_type_t type = reg->type;
689 int flags = gdbarch_tdep (gdbarch)->target_flags;
691 /* On most targets, we cannot write registers
692 of type "Unknown" or "Unmapped". */
693 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
695 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
697 warning (_("cannot write register %s"),
698 xtensa_register_name (gdbarch, regnum));
703 /* Some targets cannot read TIE register files. */
704 else if (type == xtRegisterTypeTieRegfile)
706 /* Use 'store' to get register? */
707 if (flags & xtTargetFlagsUseFetchStore)
709 warning (_("cannot write register"));
713 /* On some targets (esp. simulators), we can always write
715 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
717 warning (_("cannot write register"));
722 /* We can always write mapped registers. */
723 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
725 xtensa_register_write_masked (regcache, reg, buffer);
729 /* Assume that we can write the register. */
730 regcache_raw_write (regcache, regnum, buffer);
733 internal_error (__FILE__, __LINE__,
734 _("invalid register number %d"), regnum);
737 /* Return a character representation of a hex-decimal digit.
738 The value of "xdigit" is assumed to be in a range [0..15]. */
741 char xtensa_hextochar (int xdigit)
746 static struct reggroup *xtensa_ar_reggroup;
747 static struct reggroup *xtensa_user_reggroup;
748 static struct reggroup *xtensa_vectra_reggroup;
749 static struct reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
752 xtensa_init_reggroups (void)
755 char cpname[] = "cp0";
757 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
758 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
759 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
761 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
763 cpname[2] = xtensa_hextochar (i);
764 xtensa_cp[i] = reggroup_new (cpname, USER_REGGROUP);
769 xtensa_add_reggroups (struct gdbarch *gdbarch)
773 /* Predefined groups. */
774 reggroup_add (gdbarch, all_reggroup);
775 reggroup_add (gdbarch, save_reggroup);
776 reggroup_add (gdbarch, restore_reggroup);
777 reggroup_add (gdbarch, system_reggroup);
778 reggroup_add (gdbarch, vector_reggroup);
779 reggroup_add (gdbarch, general_reggroup);
780 reggroup_add (gdbarch, float_reggroup);
782 /* Xtensa-specific groups. */
783 reggroup_add (gdbarch, xtensa_ar_reggroup);
784 reggroup_add (gdbarch, xtensa_user_reggroup);
785 reggroup_add (gdbarch, xtensa_vectra_reggroup);
787 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
788 reggroup_add (gdbarch, xtensa_cp[i]);
792 xtensa_coprocessor_register_group (struct reggroup *group)
796 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
797 if (group == xtensa_cp[i])
803 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
804 | XTENSA_REGISTER_FLAGS_WRITABLE \
805 | XTENSA_REGISTER_FLAGS_VOLATILE)
807 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
808 | XTENSA_REGISTER_FLAGS_WRITABLE)
811 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
813 struct reggroup *group)
815 xtensa_register_t* reg = &gdbarch_tdep (gdbarch)->regmap[regnum];
816 xtensa_register_type_t type = reg->type;
817 xtensa_register_group_t rg = reg->group;
820 if (group == save_reggroup)
821 /* Every single register should be included into the list of registers
822 to be watched for changes while using -data-list-changed-registers. */
825 /* First, skip registers that are not visible to this target
826 (unknown and unmapped registers when not using ISS). */
828 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
830 if (group == all_reggroup)
832 if (group == xtensa_ar_reggroup)
833 return rg & xtRegisterGroupAddrReg;
834 if (group == xtensa_user_reggroup)
835 return rg & xtRegisterGroupUser;
836 if (group == float_reggroup)
837 return rg & xtRegisterGroupFloat;
838 if (group == general_reggroup)
839 return rg & xtRegisterGroupGeneral;
840 if (group == system_reggroup)
841 return rg & xtRegisterGroupState;
842 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
843 return rg & xtRegisterGroupVectra;
844 if (group == restore_reggroup)
845 return (regnum < gdbarch_num_regs (gdbarch)
846 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
847 if ((cp_number = xtensa_coprocessor_register_group (group)) >= 0)
848 return rg & (xtRegisterGroupCP0 << cp_number);
854 /* Supply register REGNUM from the buffer specified by GREGS and LEN
855 in the general-purpose register set REGSET to register cache
856 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
859 xtensa_supply_gregset (const struct regset *regset,
865 const xtensa_elf_gregset_t *regs = gregs;
866 struct gdbarch *gdbarch = get_regcache_arch (rc);
869 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
871 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
872 regcache_raw_supply (rc, gdbarch_pc_regnum (gdbarch), (char *) ®s->pc);
873 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
874 regcache_raw_supply (rc, gdbarch_ps_regnum (gdbarch), (char *) ®s->ps);
875 if (regnum == gdbarch_tdep (gdbarch)->wb_regnum || regnum == -1)
876 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->wb_regnum,
877 (char *) ®s->windowbase);
878 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum || regnum == -1)
879 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ws_regnum,
880 (char *) ®s->windowstart);
881 if (regnum == gdbarch_tdep (gdbarch)->lbeg_regnum || regnum == -1)
882 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lbeg_regnum,
883 (char *) ®s->lbeg);
884 if (regnum == gdbarch_tdep (gdbarch)->lend_regnum || regnum == -1)
885 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lend_regnum,
886 (char *) ®s->lend);
887 if (regnum == gdbarch_tdep (gdbarch)->lcount_regnum || regnum == -1)
888 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->lcount_regnum,
889 (char *) ®s->lcount);
890 if (regnum == gdbarch_tdep (gdbarch)->sar_regnum || regnum == -1)
891 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->sar_regnum,
892 (char *) ®s->sar);
893 if (regnum >=gdbarch_tdep (gdbarch)->ar_base
894 && regnum < gdbarch_tdep (gdbarch)->ar_base
895 + gdbarch_tdep (gdbarch)->num_aregs)
896 regcache_raw_supply (rc, regnum,
897 (char *) ®s->ar[regnum - gdbarch_tdep
898 (gdbarch)->ar_base]);
899 else if (regnum == -1)
901 for (i = 0; i < gdbarch_tdep (gdbarch)->num_aregs; ++i)
902 regcache_raw_supply (rc, gdbarch_tdep (gdbarch)->ar_base + i,
903 (char *) ®s->ar[i]);
908 /* Xtensa register set. */
914 xtensa_supply_gregset
918 /* Return the appropriate register set for the core
919 section identified by SECT_NAME and SECT_SIZE. */
921 static const struct regset *
922 xtensa_regset_from_core_section (struct gdbarch *core_arch,
923 const char *sect_name,
926 DEBUGTRACE ("xtensa_regset_from_core_section "
927 "(..., sect_name==\"%s\", sect_size==%x)\n",
928 sect_name, (unsigned int) sect_size);
930 if (strcmp (sect_name, ".reg") == 0
931 && sect_size >= sizeof(xtensa_elf_gregset_t))
932 return &xtensa_gregset;
938 /* Handling frames. */
940 /* Number of registers to save in case of Windowed ABI. */
941 #define XTENSA_NUM_SAVED_AREGS 12
943 /* Frame cache part for Windowed ABI. */
944 typedef struct xtensa_windowed_frame_cache
946 int wb; /* WINDOWBASE of the previous frame. */
947 int callsize; /* Call size of this frame. */
948 int ws; /* WINDOWSTART of the previous frame. It keeps track of
949 life windows only. If there is no bit set for the
950 window, that means it had been already spilled
951 because of window overflow. */
953 /* Addresses of spilled A-registers.
954 AREGS[i] == -1, if corresponding AR is alive. */
955 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
956 } xtensa_windowed_frame_cache_t;
958 /* Call0 ABI Definitions. */
960 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
962 #define C0_NREGS 16 /* Number of A-registers to track. */
963 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
964 #define C0_SP 1 /* Register used as SP. */
965 #define C0_FP 15 /* Register used as FP. */
966 #define C0_RA 0 /* Register used as return address. */
967 #define C0_ARGS 2 /* Register used as first arg/retval. */
968 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
970 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
971 A-register where the current content of the reg came from (in terms
972 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
973 mean that the orignal content of the register was saved to the stack.
974 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
975 know where SP will end up until the entire prologue has been analyzed. */
977 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
978 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
979 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
981 extern xtensa_isa xtensa_default_isa;
983 typedef struct xtensa_c0reg
985 int fr_reg; /* original register from which register content
986 is derived, or C0_CONST, or C0_INEXP. */
987 int fr_ofs; /* constant offset from reg, or immediate value. */
988 int to_stk; /* offset from original SP to register (4-byte
989 aligned), or C0_NOSTK if register has not
994 /* Frame cache part for Call0 ABI. */
995 typedef struct xtensa_call0_frame_cache
997 int c0_frmsz; /* Stack frame size. */
998 int c0_hasfp; /* Current frame uses frame
1000 int fp_regnum; /* A-register used as FP. */
1001 int c0_fp; /* Actual value of frame pointer. */
1002 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
1003 } xtensa_call0_frame_cache_t;
1005 typedef struct xtensa_frame_cache
1007 CORE_ADDR base; /* Stack pointer of this frame. */
1008 CORE_ADDR pc; /* PC of this frame at the function entry point. */
1009 CORE_ADDR ra; /* The raw return address of this frame. */
1010 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
1011 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
1012 int call0; /* It's a call0 framework (else windowed). */
1015 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
1016 xtensa_call0_frame_cache_t c0; /* call0 == true. */
1018 } xtensa_frame_cache_t;
1021 static struct xtensa_frame_cache *
1022 xtensa_alloc_frame_cache (int windowed)
1024 xtensa_frame_cache_t *cache;
1027 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
1029 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
1036 cache->call0 = !windowed;
1039 cache->c0.c0_frmsz = -1;
1040 cache->c0.c0_hasfp = 0;
1041 cache->c0.fp_regnum = -1;
1042 cache->c0.c0_fp = -1;
1044 for (i = 0; i < C0_NREGS; i++)
1046 cache->c0.c0_rt[i].fr_reg = i;
1047 cache->c0.c0_rt[i].fr_ofs = 0;
1048 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1055 cache->wd.callsize = -1;
1057 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1058 cache->wd.aregs[i] = -1;
1065 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1067 return address & ~15;
1072 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1077 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1078 host_address_to_string (next_frame));
1080 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1081 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1083 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1089 static struct frame_id
1090 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1094 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1096 pc = get_frame_pc (this_frame);
1097 fp = get_frame_register_unsigned
1098 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1100 /* Make dummy frame ID unique by adding a constant. */
1101 return frame_id_build (fp + SP_ALIGNMENT, pc);
1104 /* Returns true, if instruction to execute next is unique to Xtensa Window
1105 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1108 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1110 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1111 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1114 if (byte_order == BFD_ENDIAN_BIG)
1116 /* Check, if this is L32E or S32E. */
1117 code = insn & 0xf000ff00;
1118 if ((code == 0x00009000) || (code == 0x00009400))
1120 /* Check, if this is RFWU or RFWO. */
1121 code = insn & 0xffffff00;
1122 return ((code == 0x00430000) || (code == 0x00530000));
1126 /* Check, if this is L32E or S32E. */
1127 code = insn & 0x00ff000f;
1128 if ((code == 0x090000) || (code == 0x490000))
1130 /* Check, if this is RFWU or RFWO. */
1131 code = insn & 0x00ffffff;
1132 return ((code == 0x00003400) || (code == 0x00003500));
1136 /* Returns the best guess about which register is a frame pointer
1137 for the function containing CURRENT_PC. */
1139 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1140 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1143 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1145 #define RETURN_FP goto done
1147 unsigned int fp_regnum = gdbarch_tdep (gdbarch)->a0_base + 1;
1148 CORE_ADDR start_addr;
1150 xtensa_insnbuf ins, slot;
1151 char ibuf[XTENSA_ISA_BSZ];
1152 CORE_ADDR ia, bt, ba;
1154 int ilen, islots, is;
1156 const char *opcname;
1158 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1159 if (start_addr == 0)
1162 if (!xtensa_default_isa)
1163 xtensa_default_isa = xtensa_isa_init (0, 0);
1164 isa = xtensa_default_isa;
1165 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1166 ins = xtensa_insnbuf_alloc (isa);
1167 slot = xtensa_insnbuf_alloc (isa);
1170 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1172 if (ia + xtensa_isa_maxlength (isa) > bt)
1175 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1176 ? ba + XTENSA_ISA_BSZ : current_pc;
1177 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1181 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1182 ifmt = xtensa_format_decode (isa, ins);
1183 if (ifmt == XTENSA_UNDEFINED)
1185 ilen = xtensa_format_length (isa, ifmt);
1186 if (ilen == XTENSA_UNDEFINED)
1188 islots = xtensa_format_num_slots (isa, ifmt);
1189 if (islots == XTENSA_UNDEFINED)
1192 for (is = 0; is < islots; ++is)
1194 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1197 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1198 if (opc == XTENSA_UNDEFINED)
1201 opcname = xtensa_opcode_name (isa, opc);
1203 if (strcasecmp (opcname, "mov.n") == 0
1204 || strcasecmp (opcname, "or") == 0)
1206 unsigned int register_operand;
1208 /* Possible candidate for setting frame pointer
1209 from A1. This is what we are looking for. */
1211 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1212 is, slot, ®ister_operand) != 0)
1214 if (xtensa_operand_decode (isa, opc, 1, ®ister_operand) != 0)
1216 if (register_operand == 1) /* Mov{.n} FP A1. */
1218 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1219 ®ister_operand) != 0)
1221 if (xtensa_operand_decode (isa, opc, 0,
1222 ®ister_operand) != 0)
1226 = gdbarch_tdep (gdbarch)->a0_base + register_operand;
1232 /* We have problems decoding the memory. */
1234 || strcasecmp (opcname, "ill") == 0
1235 || strcasecmp (opcname, "ill.n") == 0
1236 /* Hit planted breakpoint. */
1237 || strcasecmp (opcname, "break") == 0
1238 || strcasecmp (opcname, "break.n") == 0
1239 /* Flow control instructions finish prologue. */
1240 || xtensa_opcode_is_branch (isa, opc) > 0
1241 || xtensa_opcode_is_jump (isa, opc) > 0
1242 || xtensa_opcode_is_loop (isa, opc) > 0
1243 || xtensa_opcode_is_call (isa, opc) > 0
1244 || strcasecmp (opcname, "simcall") == 0
1245 || strcasecmp (opcname, "syscall") == 0)
1246 /* Can not continue analysis. */
1251 xtensa_insnbuf_free(isa, slot);
1252 xtensa_insnbuf_free(isa, ins);
1256 /* The key values to identify the frame using "cache" are
1258 cache->base = SP (or best guess about FP) of this frame;
1259 cache->pc = entry-PC (entry point of the frame function);
1260 cache->prev_sp = SP of the previous frame. */
1263 call0_frame_cache (struct frame_info *this_frame,
1264 xtensa_frame_cache_t *cache,
1265 CORE_ADDR pc, CORE_ADDR litbase);
1268 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
1269 xtensa_frame_cache_t *cache,
1272 static struct xtensa_frame_cache *
1273 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1275 xtensa_frame_cache_t *cache;
1276 CORE_ADDR ra, wb, ws, pc, sp, ps;
1277 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1278 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1279 unsigned int fp_regnum;
1280 int windowed, ps_regnum;
1285 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1286 ps_regnum = gdbarch_ps_regnum (gdbarch);
1287 ps = (ps_regnum >= 0
1288 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1290 windowed = windowing_enabled (gdbarch, ps);
1292 /* Get pristine xtensa-frame. */
1293 cache = xtensa_alloc_frame_cache (windowed);
1294 *this_cache = cache;
1300 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1301 wb = get_frame_register_unsigned (this_frame,
1302 gdbarch_tdep (gdbarch)->wb_regnum);
1303 ws = get_frame_register_unsigned (this_frame,
1304 gdbarch_tdep (gdbarch)->ws_regnum);
1306 op1 = read_memory_integer (pc, 1, byte_order);
1307 if (XTENSA_IS_ENTRY (gdbarch, op1))
1309 int callinc = CALLINC (ps);
1310 ra = get_frame_register_unsigned
1311 (this_frame, gdbarch_tdep (gdbarch)->a0_base + callinc * 4);
1313 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1314 cache->wd.callsize = 0;
1317 cache->prev_sp = get_frame_register_unsigned
1318 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1320 /* This only can be the outermost frame since we are
1321 just about to execute ENTRY. SP hasn't been set yet.
1322 We can assume any frame size, because it does not
1323 matter, and, let's fake frame base in cache. */
1324 cache->base = cache->prev_sp - 16;
1327 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1328 cache->ps = (ps & ~PS_CALLINC_MASK)
1329 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1335 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1336 ra = get_frame_register_unsigned (this_frame,
1337 gdbarch_tdep (gdbarch)->a0_base);
1338 cache->wd.callsize = WINSIZE (ra);
1339 cache->wd.wb = (wb - cache->wd.callsize / 4)
1340 & (gdbarch_tdep (gdbarch)->num_aregs / 4 - 1);
1341 cache->wd.ws = ws & ~(1 << wb);
1343 cache->pc = get_frame_func (this_frame);
1344 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1345 cache->ps = (ps & ~PS_CALLINC_MASK)
1346 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1349 if (cache->wd.ws == 0)
1354 sp = get_frame_register_unsigned
1355 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1) - 16;
1357 for (i = 0; i < 4; i++, sp += 4)
1359 cache->wd.aregs[i] = sp;
1362 if (cache->wd.callsize > 4)
1364 /* Set A4...A7/A11. */
1365 /* Get the SP of the frame previous to the previous one.
1366 To achieve this, we have to dereference SP twice. */
1367 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1368 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1369 sp -= cache->wd.callsize * 4;
1371 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1373 cache->wd.aregs[i] = sp;
1378 if ((cache->prev_sp == 0) && ( ra != 0 ))
1379 /* If RA is equal to 0 this frame is an outermost frame. Leave
1380 cache->prev_sp unchanged marking the boundary of the frame stack. */
1382 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1384 /* Register window overflow already happened.
1385 We can read caller's SP from the proper spill loction. */
1386 sp = get_frame_register_unsigned
1387 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
1388 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1392 /* Read caller's frame SP directly from the previous window. */
1393 int regnum = arreg_number
1394 (gdbarch, gdbarch_tdep (gdbarch)->a0_base + 1,
1397 cache->prev_sp = xtensa_read_register (regnum);
1401 else if (xtensa_window_interrupt_insn (gdbarch, pc))
1403 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1405 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1406 /* Everything was set already, including cache->base. */
1409 else /* Call0 framework. */
1411 unsigned int litbase_regnum = gdbarch_tdep (gdbarch)->litbase_regnum;
1412 CORE_ADDR litbase = (litbase_regnum == -1)
1413 ? 0 : get_frame_register_unsigned (this_frame, litbase_regnum);
1415 call0_frame_cache (this_frame, cache, pc, litbase);
1416 fp_regnum = cache->c0.fp_regnum;
1419 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1425 xtensa_frame_this_id (struct frame_info *this_frame,
1427 struct frame_id *this_id)
1429 struct xtensa_frame_cache *cache =
1430 xtensa_frame_cache (this_frame, this_cache);
1432 if (cache->prev_sp == 0)
1435 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1438 static struct value *
1439 xtensa_frame_prev_register (struct frame_info *this_frame,
1443 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1444 struct xtensa_frame_cache *cache;
1445 ULONGEST saved_reg = 0;
1448 if (*this_cache == NULL)
1449 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1450 cache = *this_cache;
1452 if (regnum ==gdbarch_pc_regnum (gdbarch))
1453 saved_reg = cache->ra;
1454 else if (regnum == gdbarch_tdep (gdbarch)->a0_base + 1)
1455 saved_reg = cache->prev_sp;
1456 else if (!cache->call0)
1458 if (regnum == gdbarch_tdep (gdbarch)->ws_regnum)
1459 saved_reg = cache->wd.ws;
1460 else if (regnum == gdbarch_tdep (gdbarch)->wb_regnum)
1461 saved_reg = cache->wd.wb;
1462 else if (regnum == gdbarch_ps_regnum (gdbarch))
1463 saved_reg = cache->ps;
1471 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1473 if (!cache->call0) /* Windowed ABI. */
1475 /* Convert A-register numbers to AR-register numbers,
1476 if we deal with A-register. */
1477 if (regnum >= gdbarch_tdep (gdbarch)->a0_base
1478 && regnum <= gdbarch_tdep (gdbarch)->a0_base + 15)
1479 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1481 /* Check, if we deal with AR-register saved on stack. */
1482 if (regnum >= gdbarch_tdep (gdbarch)->ar_base
1483 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1484 + gdbarch_tdep (gdbarch)->num_aregs))
1486 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1489 && areg < XTENSA_NUM_SAVED_AREGS
1490 && cache->wd.aregs[areg] != -1)
1491 return frame_unwind_got_memory (this_frame, regnum,
1492 cache->wd.aregs[areg]);
1495 else /* Call0 ABI. */
1497 int reg = (regnum >= gdbarch_tdep (gdbarch)->ar_base
1498 && regnum <= (gdbarch_tdep (gdbarch)->ar_base
1500 ? regnum - gdbarch_tdep (gdbarch)->ar_base : regnum;
1507 /* If register was saved in the prologue, retrieve it. */
1508 stkofs = cache->c0.c0_rt[reg].to_stk;
1509 if (stkofs != C0_NOSTK)
1511 /* Determine SP on entry based on FP. */
1512 spe = cache->c0.c0_fp
1513 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1515 return frame_unwind_got_memory (this_frame, regnum,
1521 /* All other registers have been either saved to
1522 the stack or are still alive in the processor. */
1524 return frame_unwind_got_register (this_frame, regnum, regnum);
1528 static const struct frame_unwind
1532 xtensa_frame_this_id,
1533 xtensa_frame_prev_register,
1535 default_frame_sniffer
1539 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1541 struct xtensa_frame_cache *cache =
1542 xtensa_frame_cache (this_frame, this_cache);
1547 static const struct frame_base
1551 xtensa_frame_base_address,
1552 xtensa_frame_base_address,
1553 xtensa_frame_base_address
1558 xtensa_extract_return_value (struct type *type,
1559 struct regcache *regcache,
1562 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1563 bfd_byte *valbuf = dst;
1564 int len = TYPE_LENGTH (type);
1569 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1571 gdb_assert(len > 0);
1573 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1575 /* First, we have to find the caller window in the register file. */
1576 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1577 callsize = extract_call_winsize (gdbarch, pc);
1579 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1580 if (len > (callsize > 8 ? 8 : 16))
1581 internal_error (__FILE__, __LINE__,
1582 _("cannot extract return value of %d bytes long"),
1585 /* Get the register offset of the return
1586 register (A2) in the caller window. */
1587 regcache_raw_read_unsigned
1588 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1589 areg = arreg_number (gdbarch,
1590 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1594 /* No windowing hardware - Call0 ABI. */
1595 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1598 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1600 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1603 for (; len > 0; len -= 4, areg++, valbuf += 4)
1606 regcache_raw_read_part (regcache, areg, offset, len, valbuf);
1608 regcache_raw_read (regcache, areg, valbuf);
1614 xtensa_store_return_value (struct type *type,
1615 struct regcache *regcache,
1618 struct gdbarch *gdbarch = get_regcache_arch (regcache);
1619 const bfd_byte *valbuf = dst;
1623 int len = TYPE_LENGTH (type);
1626 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1628 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1630 regcache_raw_read_unsigned
1631 (regcache, gdbarch_tdep (gdbarch)->wb_regnum, &wb);
1632 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1633 callsize = extract_call_winsize (gdbarch, pc);
1635 if (len > (callsize > 8 ? 8 : 16))
1636 internal_error (__FILE__, __LINE__,
1637 _("unimplemented for this length: %d"),
1638 TYPE_LENGTH (type));
1639 areg = arreg_number (gdbarch,
1640 gdbarch_tdep (gdbarch)->a0_base + 2 + callsize, wb);
1642 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1643 callsize, (int) wb);
1647 areg = gdbarch_tdep (gdbarch)->a0_base + C0_ARGS;
1650 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1653 for (; len > 0; len -= 4, areg++, valbuf += 4)
1656 regcache_raw_write_part (regcache, areg, offset, len, valbuf);
1658 regcache_raw_write (regcache, areg, valbuf);
1663 static enum return_value_convention
1664 xtensa_return_value (struct gdbarch *gdbarch,
1665 struct type *func_type,
1666 struct type *valtype,
1667 struct regcache *regcache,
1669 const gdb_byte *writebuf)
1671 /* Structures up to 16 bytes are returned in registers. */
1673 int struct_return = ((TYPE_CODE (valtype) == TYPE_CODE_STRUCT
1674 || TYPE_CODE (valtype) == TYPE_CODE_UNION
1675 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY)
1676 && TYPE_LENGTH (valtype) > 16);
1679 return RETURN_VALUE_STRUCT_CONVENTION;
1681 DEBUGTRACE ("xtensa_return_value(...)\n");
1683 if (writebuf != NULL)
1685 xtensa_store_return_value (valtype, regcache, writebuf);
1688 if (readbuf != NULL)
1690 gdb_assert (!struct_return);
1691 xtensa_extract_return_value (valtype, regcache, readbuf);
1693 return RETURN_VALUE_REGISTER_CONVENTION;
1700 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1701 struct value *function,
1702 struct regcache *regcache,
1705 struct value **args,
1708 CORE_ADDR struct_addr)
1710 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1712 int size, onstack_size;
1713 gdb_byte *buf = (gdb_byte *) alloca (16);
1715 struct argument_info
1717 const bfd_byte *contents;
1719 int onstack; /* onstack == 0 => in reg */
1720 int align; /* alignment */
1723 int offset; /* stack offset if on stack. */
1724 int regno; /* regno if in register. */
1728 struct argument_info *arg_info =
1729 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1733 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1735 if (xtensa_debug_level > 3)
1738 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1739 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, struct_return=%d, "
1740 "struct_addr=0x%x\n",
1741 (int) sp, (int) struct_return, (int) struct_addr);
1743 for (i = 0; i < nargs; i++)
1745 struct value *arg = args[i];
1746 struct type *arg_type = check_typedef (value_type (arg));
1747 fprintf_unfiltered (gdb_stdlog, "%2d: %s %3d ", i,
1748 host_address_to_string (arg),
1749 TYPE_LENGTH (arg_type));
1750 switch (TYPE_CODE (arg_type))
1753 fprintf_unfiltered (gdb_stdlog, "int");
1755 case TYPE_CODE_STRUCT:
1756 fprintf_unfiltered (gdb_stdlog, "struct");
1759 fprintf_unfiltered (gdb_stdlog, "%3d", TYPE_CODE (arg_type));
1762 fprintf_unfiltered (gdb_stdlog, " %s\n",
1763 host_address_to_string (value_contents (arg)));
1767 /* First loop: collect information.
1768 Cast into type_long. (This shouldn't happen often for C because
1769 GDB already does this earlier.) It's possible that GDB could
1770 do it all the time but it's harmless to leave this code here. */
1777 size = REGISTER_SIZE;
1779 for (i = 0; i < nargs; i++)
1781 struct argument_info *info = &arg_info[i];
1782 struct value *arg = args[i];
1783 struct type *arg_type = check_typedef (value_type (arg));
1785 switch (TYPE_CODE (arg_type))
1788 case TYPE_CODE_BOOL:
1789 case TYPE_CODE_CHAR:
1790 case TYPE_CODE_RANGE:
1791 case TYPE_CODE_ENUM:
1793 /* Cast argument to long if necessary as the mask does it too. */
1794 if (TYPE_LENGTH (arg_type)
1795 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1797 arg_type = builtin_type (gdbarch)->builtin_long;
1798 arg = value_cast (arg_type, arg);
1800 /* Aligment is equal to the type length for the basic types. */
1801 info->align = TYPE_LENGTH (arg_type);
1806 /* Align doubles correctly. */
1807 if (TYPE_LENGTH (arg_type)
1808 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1809 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1811 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1814 case TYPE_CODE_STRUCT:
1816 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1819 info->length = TYPE_LENGTH (arg_type);
1820 info->contents = value_contents (arg);
1822 /* Align size and onstack_size. */
1823 size = (size + info->align - 1) & ~(info->align - 1);
1824 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1826 if (size + info->length > REGISTER_SIZE * ARG_NOF (gdbarch))
1829 info->u.offset = onstack_size;
1830 onstack_size += info->length;
1835 info->u.regno = ARG_1ST (gdbarch) + size / REGISTER_SIZE;
1837 size += info->length;
1840 /* Adjust the stack pointer and align it. */
1841 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1843 /* Simulate MOVSP, if Windowed ABI. */
1844 if ((gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1847 read_memory (osp - 16, buf, 16);
1848 write_memory (sp - 16, buf, 16);
1851 /* Second Loop: Load arguments. */
1855 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1856 regcache_cooked_write (regcache, ARG_1ST (gdbarch), buf);
1859 for (i = 0; i < nargs; i++)
1861 struct argument_info *info = &arg_info[i];
1865 int n = info->length;
1866 CORE_ADDR offset = sp + info->u.offset;
1868 /* Odd-sized structs are aligned to the lower side of a memory
1869 word in big-endian mode and require a shift. This only
1870 applies for structures smaller than one word. */
1872 if (n < REGISTER_SIZE
1873 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1874 offset += (REGISTER_SIZE - n);
1876 write_memory (offset, info->contents, info->length);
1881 int n = info->length;
1882 const bfd_byte *cp = info->contents;
1883 int r = info->u.regno;
1885 /* Odd-sized structs are aligned to the lower side of registers in
1886 big-endian mode and require a shift. The odd-sized leftover will
1887 be at the end. Note that this is only true for structures smaller
1888 than REGISTER_SIZE; for larger odd-sized structures the excess
1889 will be left-aligned in the register on both endiannesses. */
1891 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1894 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1895 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1897 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1898 regcache_cooked_write (regcache, r, buf);
1900 cp += REGISTER_SIZE;
1907 regcache_cooked_write (regcache, r, cp);
1909 cp += REGISTER_SIZE;
1916 /* Set the return address of dummy frame to the dummy address.
1917 The return address for the current function (in A0) is
1918 saved in the dummy frame, so we can savely overwrite A0 here. */
1920 if (gdbarch_tdep (gdbarch)->call_abi != CallAbiCall0Only)
1924 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1925 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1926 ps = (unsigned long) val & ~0x00030000;
1927 regcache_cooked_write_unsigned
1928 (regcache, gdbarch_tdep (gdbarch)->a0_base + 4, ra);
1929 regcache_cooked_write_unsigned (regcache,
1930 gdbarch_ps_regnum (gdbarch),
1933 /* All the registers have been saved. After executing
1934 dummy call, they all will be restored. So it's safe
1935 to modify WINDOWSTART register to make it look like there
1936 is only one register window corresponding to WINDOWEBASE. */
1938 regcache_raw_read (regcache, gdbarch_tdep (gdbarch)->wb_regnum, buf);
1939 regcache_cooked_write_unsigned
1940 (regcache, gdbarch_tdep (gdbarch)->ws_regnum,
1941 1 << extract_unsigned_integer (buf, 4, byte_order));
1945 /* Simulate CALL0: write RA into A0 register. */
1946 regcache_cooked_write_unsigned
1947 (regcache, gdbarch_tdep (gdbarch)->a0_base, bp_addr);
1950 /* Set new stack pointer and return it. */
1951 regcache_cooked_write_unsigned (regcache,
1952 gdbarch_tdep (gdbarch)->a0_base + 1, sp);
1953 /* Make dummy frame ID unique by adding a constant. */
1954 return sp + SP_ALIGNMENT;
1958 /* Return a breakpoint for the current location of PC. We always use
1959 the density version if we have density instructions (regardless of the
1960 current instruction at PC), and use regular instructions otherwise. */
1962 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1963 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1964 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1965 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1967 static const unsigned char *
1968 xtensa_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1971 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1972 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1973 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1974 static unsigned char density_little_breakpoint[] = DENSITY_LITTLE_BREAKPOINT;
1976 DEBUGTRACE ("xtensa_breakpoint_from_pc (pc = 0x%08x)\n", (int) *pcptr);
1978 if (gdbarch_tdep (gdbarch)->isa_use_density_instructions)
1980 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1982 *lenptr = sizeof (density_big_breakpoint);
1983 return density_big_breakpoint;
1987 *lenptr = sizeof (density_little_breakpoint);
1988 return density_little_breakpoint;
1993 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1995 *lenptr = sizeof (big_breakpoint);
1996 return big_breakpoint;
2000 *lenptr = sizeof (little_breakpoint);
2001 return little_breakpoint;
2006 /* Call0 ABI support routines. */
2008 /* Return true, if PC points to "ret" or "ret.n". */
2011 call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
2013 #define RETURN_RET goto done
2015 xtensa_insnbuf ins, slot;
2016 char ibuf[XTENSA_ISA_BSZ];
2017 CORE_ADDR ia, bt, ba;
2019 int ilen, islots, is;
2021 const char *opcname;
2024 isa = xtensa_default_isa;
2025 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2026 ins = xtensa_insnbuf_alloc (isa);
2027 slot = xtensa_insnbuf_alloc (isa);
2030 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2032 if (ia + xtensa_isa_maxlength (isa) > bt)
2035 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2036 ? ba + XTENSA_ISA_BSZ : finish_pc;
2037 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2041 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2042 ifmt = xtensa_format_decode (isa, ins);
2043 if (ifmt == XTENSA_UNDEFINED)
2045 ilen = xtensa_format_length (isa, ifmt);
2046 if (ilen == XTENSA_UNDEFINED)
2048 islots = xtensa_format_num_slots (isa, ifmt);
2049 if (islots == XTENSA_UNDEFINED)
2052 for (is = 0; is < islots; ++is)
2054 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2057 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2058 if (opc == XTENSA_UNDEFINED)
2061 opcname = xtensa_opcode_name (isa, opc);
2063 if ((strcasecmp (opcname, "ret.n") == 0)
2064 || (strcasecmp (opcname, "ret") == 0))
2072 xtensa_insnbuf_free(isa, slot);
2073 xtensa_insnbuf_free(isa, ins);
2077 /* Call0 opcode class. Opcodes are preclassified according to what they
2078 mean for Call0 prologue analysis, and their number of significant operands.
2079 The purpose of this is to simplify prologue analysis by separating
2080 instruction decoding (libisa) from the semantics of prologue analysis. */
2084 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2085 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2086 c0opc_flow, /* Flow control insn. */
2087 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2088 c0opc_break, /* Debugger software breakpoints. */
2089 c0opc_add, /* Adding two registers. */
2090 c0opc_addi, /* Adding a register and an immediate. */
2091 c0opc_sub, /* Subtracting a register from a register. */
2092 c0opc_mov, /* Moving a register to a register. */
2093 c0opc_movi, /* Moving an immediate to a register. */
2094 c0opc_l32r, /* Loading a literal. */
2095 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2096 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2097 c0opc_l32e, /* L32E instruction. */
2098 c0opc_s32e, /* S32E instruction. */
2099 c0opc_rfwo, /* RFWO instruction. */
2100 c0opc_rfwu, /* RFWU instruction. */
2101 c0opc_NrOf /* Number of opcode classifications. */
2104 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2107 rwx_special_register (const char *opcname)
2109 char ch = *opcname++;
2111 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2113 if (*opcname++ != 's')
2115 if (*opcname++ != 'r')
2117 if (*opcname++ != '.')
2123 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2125 static xtensa_insn_kind
2126 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2128 const char *opcname;
2129 xtensa_insn_kind opclass = c0opc_uninteresting;
2131 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2133 /* Get opcode name and handle special classifications. */
2135 opcname = xtensa_opcode_name (isa, opc);
2138 || strcasecmp (opcname, "ill") == 0
2139 || strcasecmp (opcname, "ill.n") == 0)
2140 opclass = c0opc_illegal;
2141 else if (strcasecmp (opcname, "break") == 0
2142 || strcasecmp (opcname, "break.n") == 0)
2143 opclass = c0opc_break;
2144 else if (strcasecmp (opcname, "entry") == 0)
2145 opclass = c0opc_entry;
2146 else if (strcasecmp (opcname, "rfwo") == 0)
2147 opclass = c0opc_rfwo;
2148 else if (strcasecmp (opcname, "rfwu") == 0)
2149 opclass = c0opc_rfwu;
2150 else if (xtensa_opcode_is_branch (isa, opc) > 0
2151 || xtensa_opcode_is_jump (isa, opc) > 0
2152 || xtensa_opcode_is_loop (isa, opc) > 0
2153 || xtensa_opcode_is_call (isa, opc) > 0
2154 || strcasecmp (opcname, "simcall") == 0
2155 || strcasecmp (opcname, "syscall") == 0)
2156 opclass = c0opc_flow;
2158 /* Also, classify specific opcodes that need to be tracked. */
2159 else if (strcasecmp (opcname, "add") == 0
2160 || strcasecmp (opcname, "add.n") == 0)
2161 opclass = c0opc_add;
2162 else if (strcasecmp (opcname, "addi") == 0
2163 || strcasecmp (opcname, "addi.n") == 0
2164 || strcasecmp (opcname, "addmi") == 0)
2165 opclass = c0opc_addi;
2166 else if (strcasecmp (opcname, "sub") == 0)
2167 opclass = c0opc_sub;
2168 else if (strcasecmp (opcname, "mov.n") == 0
2169 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2170 opclass = c0opc_mov;
2171 else if (strcasecmp (opcname, "movi") == 0
2172 || strcasecmp (opcname, "movi.n") == 0)
2173 opclass = c0opc_movi;
2174 else if (strcasecmp (opcname, "l32r") == 0)
2175 opclass = c0opc_l32r;
2176 else if (strcasecmp (opcname, "s32i") == 0
2177 || strcasecmp (opcname, "s32i.n") == 0)
2178 opclass = c0opc_s32i;
2179 else if (strcasecmp (opcname, "l32e") == 0)
2180 opclass = c0opc_l32e;
2181 else if (strcasecmp (opcname, "s32e") == 0)
2182 opclass = c0opc_s32e;
2183 else if (rwx_special_register (opcname))
2184 opclass = c0opc_rwxsr;
2189 /* Tracks register movement/mutation for a given operation, which may
2190 be within a bundle. Updates the destination register tracking info
2191 accordingly. The pc is needed only for pc-relative load instructions
2192 (eg. l32r). The SP register number is needed to identify stores to
2196 call0_track_op (struct gdbarch *gdbarch,
2197 xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2198 xtensa_insn_kind opclass, int nods, unsigned odv[],
2199 CORE_ADDR pc, CORE_ADDR litbase, int spreg)
2201 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2202 unsigned litaddr, litval;
2207 /* 3 operands: dst, src, imm. */
2208 gdb_assert (nods == 3);
2209 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2210 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2213 /* 3 operands: dst, src1, src2. */
2214 gdb_assert (nods == 3);
2215 if (src[odv[1]].fr_reg == C0_CONST)
2217 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2218 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2220 else if (src[odv[2]].fr_reg == C0_CONST)
2222 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2223 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2225 else dst[odv[0]].fr_reg = C0_INEXP;
2228 /* 3 operands: dst, src1, src2. */
2229 gdb_assert (nods == 3);
2230 if (src[odv[2]].fr_reg == C0_CONST)
2232 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2233 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2235 else dst[odv[0]].fr_reg = C0_INEXP;
2238 /* 2 operands: dst, src [, src]. */
2239 gdb_assert (nods == 2);
2240 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2241 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2244 /* 2 operands: dst, imm. */
2245 gdb_assert (nods == 2);
2246 dst[odv[0]].fr_reg = C0_CONST;
2247 dst[odv[0]].fr_ofs = odv[1];
2250 /* 2 operands: dst, literal offset. */
2251 gdb_assert (nods == 2);
2252 litaddr = litbase & 1
2253 ? (litbase & ~1) + (signed)odv[1]
2254 : (pc + 3 + (signed)odv[1]) & ~3;
2255 litval = read_memory_integer (litaddr, 4, byte_order);
2256 dst[odv[0]].fr_reg = C0_CONST;
2257 dst[odv[0]].fr_ofs = litval;
2260 /* 3 operands: value, base, offset. */
2261 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2262 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2263 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2264 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2265 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2266 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2268 /* ISA encoding guarantees alignment. But, check it anyway. */
2269 gdb_assert ((odv[2] & 3) == 0);
2270 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2274 gdb_assert_not_reached ("unexpected instruction kind");
2278 /* Analyze prologue of the function at start address to determine if it uses
2279 the Call0 ABI, and if so track register moves and linear modifications
2280 in the prologue up to the PC or just beyond the prologue, whichever is first.
2281 An 'entry' instruction indicates non-Call0 ABI and the end of the prologue.
2282 The prologue may overlap non-prologue instructions but is guaranteed to end
2283 by the first flow-control instruction (jump, branch, call or return).
2284 Since an optimized function may move information around and change the
2285 stack frame arbitrarily during the prologue, the information is guaranteed
2286 valid only at the point in the function indicated by the PC.
2287 May be used to skip the prologue or identify the ABI, w/o tracking.
2289 Returns: Address of first instruction after prologue, or PC (whichever
2290 is first), or 0, if decoding failed (in libisa).
2292 start Start address of function/prologue.
2293 pc Program counter to stop at. Use 0 to continue to end of prologue.
2294 If 0, avoids infinite run-on in corrupt code memory by bounding
2295 the scan to the end of the function if that can be determined.
2296 nregs Number of general registers to track (size of rt[] array).
2298 rt[] Array[nregs] of xtensa_c0reg structures for register tracking info.
2299 If NULL, registers are not tracked.
2301 call0 If != NULL, *call0 is set non-zero if Call0 ABI used, else 0
2302 (more accurately, non-zero until 'entry' insn is encountered).
2304 Note that these may produce useful results even if decoding fails
2305 because they begin with default assumptions that analysis may change. */
2308 call0_analyze_prologue (struct gdbarch *gdbarch,
2309 CORE_ADDR start, CORE_ADDR pc, CORE_ADDR litbase,
2310 int nregs, xtensa_c0reg_t rt[], int *call0)
2312 CORE_ADDR ia; /* Current insn address in prologue. */
2313 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2314 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2315 char ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2316 xtensa_isa isa; /* libisa ISA handle. */
2317 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2318 xtensa_format ifmt; /* libisa instruction format. */
2319 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2320 xtensa_opcode opc; /* Opcode in current slot. */
2321 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2322 int nods; /* Opcode number of operands. */
2323 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2324 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2325 int j; /* General loop counter. */
2326 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2327 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2328 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2330 struct symtab_and_line prologue_sal;
2332 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2333 (int)start, (int)pc);
2335 /* Try to limit the scan to the end of the function if a non-zero pc
2336 arg was not supplied to avoid probing beyond the end of valid memory.
2337 If memory is full of garbage that classifies as c0opc_uninteresting.
2338 If this fails (eg. if no symbols) pc ends up 0 as it was.
2339 Intialize the Call0 frame and register tracking info.
2340 Assume it's Call0 until an 'entry' instruction is encountered.
2341 Assume we may be in the prologue until we hit a flow control instr. */
2347 /* Find out, if we have an information about the prologue from DWARF. */
2348 prologue_sal = find_pc_line (start, 0);
2349 if (prologue_sal.line != 0) /* Found debug info. */
2350 body_pc = prologue_sal.end;
2352 /* If we are going to analyze the prologue in general without knowing about
2353 the current PC, make the best assumtion for the end of the prologue. */
2356 find_pc_partial_function (start, 0, NULL, &end_pc);
2357 body_pc = min (end_pc, body_pc);
2360 body_pc = min (pc, body_pc);
2367 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2368 /* rt is already initialized in xtensa_alloc_frame_cache(). */
2372 if (!xtensa_default_isa)
2373 xtensa_default_isa = xtensa_isa_init (0, 0);
2374 isa = xtensa_default_isa;
2375 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2376 ins = xtensa_insnbuf_alloc (isa);
2377 slot = xtensa_insnbuf_alloc (isa);
2379 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2381 /* (Re)fill instruction buffer from memory if necessary, but do not
2382 read memory beyond PC to be sure we stay within text section
2383 (this protection only works if a non-zero pc is supplied). */
2385 if (ia + xtensa_isa_maxlength (isa) > bt)
2388 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2389 read_memory (ba, ibuf, bt - ba);
2390 /* If there is a memory reading error read_memory () will report it
2391 and then throw an exception, stopping command execution. */
2394 /* Decode format information. */
2396 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2397 ifmt = xtensa_format_decode (isa, ins);
2398 if (ifmt == XTENSA_UNDEFINED)
2403 ilen = xtensa_format_length (isa, ifmt);
2404 if (ilen == XTENSA_UNDEFINED)
2409 islots = xtensa_format_num_slots (isa, ifmt);
2410 if (islots == XTENSA_UNDEFINED)
2416 /* Analyze a bundle or a single instruction, using a snapshot of
2417 the register tracking info as input for the entire bundle so that
2418 register changes do not take effect within this bundle. */
2420 for (j = 0; j < nregs; ++j)
2423 for (is = 0; is < islots; ++is)
2425 /* Decode a slot and classify the opcode. */
2427 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2431 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2432 DEBUGVERB ("[call0_analyze_prologue] instr "
2433 "addr = 0x%08x, opc = %d\n",
2435 if (opc == XTENSA_UNDEFINED)
2436 opclass = c0opc_illegal;
2438 opclass = call0_classify_opcode (isa, opc);
2440 /* Decide whether to track this opcode, ignore it, or bail out. */
2449 case c0opc_uninteresting:
2458 ia += ilen; /* Skip over 'entry' insn. */
2466 /* Only expected opcodes should get this far. */
2470 /* Extract and decode the operands. */
2471 nods = xtensa_opcode_num_operands (isa, opc);
2472 if (nods == XTENSA_UNDEFINED)
2478 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2480 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2485 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2490 /* Check operands to verify use of 'mov' assembler macro. */
2491 if (opclass == c0opc_mov && nods == 3)
2493 if (odv[2] == odv[1])
2497 opclass = c0opc_uninteresting;
2502 /* Track register movement and modification for this operation. */
2503 call0_track_op (gdbarch, rt, rtmp, opclass,
2504 nods, odv, ia, litbase, 1);
2508 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2509 (unsigned)ia, fail ? "failed" : "succeeded");
2510 xtensa_insnbuf_free(isa, slot);
2511 xtensa_insnbuf_free(isa, ins);
2512 return fail ? XTENSA_ISA_BADPC : ia;
2515 /* Initialize frame cache for the current frame in CALL0 ABI. */
2518 call0_frame_cache (struct frame_info *this_frame,
2519 xtensa_frame_cache_t *cache,
2520 CORE_ADDR pc, CORE_ADDR litbase)
2522 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2523 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2524 CORE_ADDR start_pc; /* The beginning of the function. */
2525 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2526 CORE_ADDR sp, fp, ra;
2527 int fp_regnum, c0_hasfp, c0_frmsz, prev_sp, to_stk;
2529 /* Find the beginning of the prologue of the function containing the PC
2530 and analyze it up to the PC or the end of the prologue. */
2532 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2534 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, litbase,
2536 &cache->c0.c0_rt[0],
2539 if (body_pc == XTENSA_ISA_BADPC)
2540 error (_("Xtensa-specific internal error: CALL0 prologue \
2541 analysis failed in this frame. GDB command execution stopped."));
2544 sp = get_frame_register_unsigned
2545 (this_frame, gdbarch_tdep (gdbarch)->a0_base + 1);
2546 fp = sp; /* Assume FP == SP until proven otherwise. */
2548 /* Get the frame information and FP (if used) at the current PC.
2549 If PC is in the prologue, the prologue analysis is more reliable
2550 than DWARF info. We don't not know for sure if PC is in the prologue,
2551 but we know no calls have yet taken place, so we can almost
2552 certainly rely on the prologue analysis. */
2556 /* Prologue analysis was successful up to the PC.
2557 It includes the cases when PC == START_PC. */
2558 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2559 /* c0_hasfp == true means there is a frame pointer because
2560 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2561 was derived from SP. Otherwise, it would be C0_FP. */
2562 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2563 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2564 fp_regnum += gdbarch_tdep (gdbarch)->a0_base;
2566 else /* No data from the prologue analysis. */
2569 fp_regnum = gdbarch_tdep (gdbarch)->a0_base + C0_SP;
2574 prev_sp = fp + c0_frmsz;
2576 /* Frame size from debug info or prologue tracking does not account for
2577 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2580 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2582 /* Recalculate previous SP. */
2583 prev_sp = fp + c0_frmsz;
2584 /* Update the stack frame size. */
2585 c0_frmsz += fp - sp;
2588 /* Get the return address (RA) from the stack if saved,
2589 or try to get it from a register. */
2591 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2592 if (to_stk != C0_NOSTK)
2594 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2597 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2598 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2600 /* Special case for terminating backtrace at a function that
2601 wants to be seen as the outermost. Such a function will
2602 clear it's RA (A0) register to 0 in the prologue instead of
2603 saving its original value. */
2608 /* RA was copied to another register or (before any function
2609 call) may still be in the original RA register. This is not
2610 always reliable: even in a leaf function, register tracking
2611 stops after prologue, and even in prologue, non-prologue
2612 instructions (not tracked) may overwrite RA or any register
2613 it was copied to. If likely in prologue or before any call,
2614 use retracking info and hope for the best (compiler should
2615 have saved RA in stack if not in a leaf function). If not in
2616 prologue, too bad. */
2621 (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2623 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2627 ra = get_frame_register_unsigned
2629 gdbarch_tdep (gdbarch)->a0_base + cache->c0.c0_rt[i].fr_reg);
2634 cache->pc = start_pc;
2636 /* RA == 0 marks the outermost frame. Do not go past it. */
2637 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2638 cache->c0.fp_regnum = fp_regnum;
2639 cache->c0.c0_frmsz = c0_frmsz;
2640 cache->c0.c0_hasfp = c0_hasfp;
2641 cache->c0.c0_fp = fp;
2644 static CORE_ADDR a0_saved;
2645 static CORE_ADDR a7_saved;
2646 static CORE_ADDR a11_saved;
2647 static int a0_was_saved;
2648 static int a7_was_saved;
2649 static int a11_was_saved;
2651 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2653 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2655 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2656 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2657 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2658 unsigned int spilled_value
2659 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2661 if ((at == 0) && !a0_was_saved)
2663 a0_saved = xtensa_read_register (atreg);
2666 else if ((at == 7) && !a7_was_saved)
2668 a7_saved = xtensa_read_register (atreg);
2671 else if ((at == 11) && !a11_was_saved)
2673 a11_saved = xtensa_read_register (atreg);
2677 xtensa_write_register (atreg, spilled_value);
2680 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2682 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2684 int atreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + at, wb);
2685 int asreg = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base + as, wb);
2686 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2687 ULONGEST spilled_value = xtensa_read_register (atreg);
2689 write_memory_unsigned_integer (addr, 4,
2690 gdbarch_byte_order (gdbarch),
2694 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2700 xtNoExceptionHandler
2701 } xtensa_exception_handler_t;
2703 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2704 Return type of Xtensa Window Interrupt Handler on success. */
2705 static xtensa_exception_handler_t
2706 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2709 xtensa_insnbuf ins, slot;
2710 char ibuf[XTENSA_ISA_BSZ];
2711 CORE_ADDR ia, bt, ba;
2713 int ilen, islots, is;
2717 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2722 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2723 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2725 isa = xtensa_default_isa;
2726 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2727 ins = xtensa_insnbuf_alloc (isa);
2728 slot = xtensa_insnbuf_alloc (isa);
2737 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2739 if (ia + xtensa_isa_maxlength (isa) > bt)
2742 bt = (ba + XTENSA_ISA_BSZ);
2743 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2744 return xtNoExceptionHandler;
2746 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2747 ifmt = xtensa_format_decode (isa, ins);
2748 if (ifmt == XTENSA_UNDEFINED)
2749 return xtNoExceptionHandler;
2750 ilen = xtensa_format_length (isa, ifmt);
2751 if (ilen == XTENSA_UNDEFINED)
2752 return xtNoExceptionHandler;
2753 islots = xtensa_format_num_slots (isa, ifmt);
2754 if (islots == XTENSA_UNDEFINED)
2755 return xtNoExceptionHandler;
2756 for (is = 0; is < islots; ++is)
2758 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2759 return xtNoExceptionHandler;
2760 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2761 if (opc == XTENSA_UNDEFINED)
2762 return xtNoExceptionHandler;
2763 switch (call0_classify_opcode (isa, opc))
2769 /* We expect none of them here. */
2770 return xtNoExceptionHandler;
2772 func = execute_l32e;
2775 func = execute_s32e;
2777 case c0opc_rfwo: /* RFWO. */
2778 /* Here, we return from WindowOverflow handler and,
2779 if we stopped at the very beginning, which means
2780 A0 was saved, we have to restore it now. */
2783 int arreg = arreg_number (gdbarch,
2784 gdbarch_tdep (gdbarch)->a0_base,
2786 xtensa_write_register (arreg, a0_saved);
2788 return xtWindowOverflow;
2789 case c0opc_rfwu: /* RFWU. */
2790 /* Here, we return from WindowUnderflow handler.
2791 Let's see if either A7 or A11 has to be restored. */
2792 if (WindowUnderflow12)
2796 int arreg = arreg_number (gdbarch,
2797 gdbarch_tdep (gdbarch)->a0_base + 11,
2799 xtensa_write_register (arreg, a11_saved);
2802 else if (a7_was_saved)
2804 int arreg = arreg_number (gdbarch,
2805 gdbarch_tdep (gdbarch)->a0_base + 7,
2807 xtensa_write_register (arreg, a7_saved);
2809 return xtWindowUnderflow;
2810 default: /* Simply skip this insns. */
2814 /* Decode arguments for L32E / S32E and simulate their execution. */
2815 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2816 return xtNoExceptionHandler;
2817 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2818 return xtNoExceptionHandler;
2819 if (xtensa_operand_decode (isa, opc, 0, &at))
2820 return xtNoExceptionHandler;
2821 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2822 return xtNoExceptionHandler;
2823 if (xtensa_operand_decode (isa, opc, 1, &as))
2824 return xtNoExceptionHandler;
2825 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2826 return xtNoExceptionHandler;
2827 if (xtensa_operand_decode (isa, opc, 2, &offset))
2828 return xtNoExceptionHandler;
2830 (*func) (gdbarch, at, as, offset, wb);
2835 return xtNoExceptionHandler;
2838 /* Handle Window Overflow / Underflow exception frames. */
2841 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
2842 xtensa_frame_cache_t *cache,
2845 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2846 CORE_ADDR ps, wb, ws, ra;
2847 int epc1_regnum, i, regnum;
2848 xtensa_exception_handler_t eh_type;
2850 /* Read PS, WB, and WS from the hardware. Note that PS register
2851 must be present, if Windowed ABI is supported. */
2852 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2853 wb = xtensa_read_register (gdbarch_tdep (gdbarch)->wb_regnum);
2854 ws = xtensa_read_register (gdbarch_tdep (gdbarch)->ws_regnum);
2856 /* Execute all the remaining instructions from Window Interrupt Handler
2857 by simulating them on the remote protocol level. On return, set the
2858 type of Xtensa Window Interrupt Handler, or report an error. */
2859 eh_type = execute_code (gdbarch, pc, wb);
2860 if (eh_type == xtNoExceptionHandler)
2862 Unable to decode Xtensa Window Interrupt Handler's code."));
2864 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2865 cache->call0 = 0; /* It's Windowed ABI. */
2867 /* All registers for the cached frame will be alive. */
2868 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2869 cache->wd.aregs[i] = -1;
2871 if (eh_type == xtWindowOverflow)
2872 cache->wd.ws = ws ^ (1 << wb);
2873 else /* eh_type == xtWindowUnderflow. */
2874 cache->wd.ws = ws | (1 << wb);
2876 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2877 regnum = arreg_number (gdbarch, gdbarch_tdep (gdbarch)->a0_base,
2879 ra = xtensa_read_register (regnum);
2880 cache->wd.callsize = WINSIZE (ra);
2881 cache->prev_sp = xtensa_read_register (regnum + 1);
2882 /* Set regnum to a frame pointer of the frame being cached. */
2883 regnum = xtensa_scan_prologue (gdbarch, pc);
2884 regnum = arreg_number (gdbarch,
2885 gdbarch_tdep (gdbarch)->a0_base + regnum,
2887 cache->base = get_frame_register_unsigned (this_frame, regnum);
2889 /* Read PC of interrupted function from EPC1 register. */
2890 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2891 if (epc1_regnum < 0)
2892 error(_("Unable to read Xtensa register EPC1"));
2893 cache->ra = xtensa_read_register (epc1_regnum);
2894 cache->pc = get_frame_func (this_frame);
2898 /* Skip function prologue.
2900 Return the pc of the first instruction after prologue. GDB calls this to
2901 find the address of the first line of the function or (if there is no line
2902 number information) to skip the prologue for planting breakpoints on
2903 function entries. Use debug info (if present) or prologue analysis to skip
2904 the prologue to achieve reliable debugging behavior. For windowed ABI,
2905 only the 'entry' instruction is skipped. It is not strictly necessary to
2906 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2907 backtrace at any point in the prologue, however certain potential hazards
2908 are avoided and a more "normal" debugging experience is ensured by
2909 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2910 For example, if we don't skip the prologue:
2911 - Some args may not yet have been saved to the stack where the debug
2912 info expects to find them (true anyway when only 'entry' is skipped);
2913 - Software breakpoints ('break' instrs) may not have been unplanted
2914 when the prologue analysis is done on initializing the frame cache,
2915 and breaks in the prologue will throw off the analysis.
2917 If we have debug info ( line-number info, in particular ) we simply skip
2918 the code associated with the first function line effectively skipping
2919 the prologue code. It works even in cases like
2922 { int local_var = 1;
2926 because, for this source code, both Xtensa compilers will generate two
2927 separate entries ( with the same line number ) in dwarf line-number
2928 section to make sure there is a boundary between the prologue code and
2929 the rest of the function.
2931 If there is no debug info, we need to analyze the code. */
2933 /* #define DONT_SKIP_PROLOGUE */
2936 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2938 struct symtab_and_line prologue_sal;
2941 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
2943 #if DONT_SKIP_PROLOGUE
2947 /* Try to find first body line from debug info. */
2949 prologue_sal = find_pc_line (start_pc, 0);
2950 if (prologue_sal.line != 0) /* Found debug info. */
2952 /* In Call0, it is possible to have a function with only one instruction
2953 ('ret') resulting from a one-line optimized function that does nothing.
2954 In that case, prologue_sal.end may actually point to the start of the
2955 next function in the text section, causing a breakpoint to be set at
2956 the wrong place. Check, if the end address is within a different
2957 function, and if so return the start PC. We know we have symbol
2962 if ((gdbarch_tdep (gdbarch)->call_abi == CallAbiCall0Only)
2963 && call0_ret (start_pc, prologue_sal.end))
2966 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
2967 if (end_func != start_pc)
2970 return prologue_sal.end;
2973 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
2974 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0, 0, NULL, NULL);
2975 return body_pc != 0 ? body_pc : start_pc;
2978 /* Verify the current configuration. */
2980 xtensa_verify_config (struct gdbarch *gdbarch)
2982 struct ui_file *log;
2983 struct cleanup *cleanups;
2984 struct gdbarch_tdep *tdep;
2988 tdep = gdbarch_tdep (gdbarch);
2989 log = mem_fileopen ();
2990 cleanups = make_cleanup_ui_file_delete (log);
2992 /* Verify that we got a reasonable number of AREGS. */
2993 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
2994 fprintf_unfiltered (log, _("\
2995 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
2998 /* Verify that certain registers exist. */
3000 if (tdep->pc_regnum == -1)
3001 fprintf_unfiltered (log, _("\n\tpc_regnum: No PC register"));
3002 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3003 fprintf_unfiltered (log, _("\n\tps_regnum: No PS register"));
3005 if (tdep->isa_use_windowed_registers)
3007 if (tdep->wb_regnum == -1)
3008 fprintf_unfiltered (log, _("\n\twb_regnum: No WB register"));
3009 if (tdep->ws_regnum == -1)
3010 fprintf_unfiltered (log, _("\n\tws_regnum: No WS register"));
3011 if (tdep->ar_base == -1)
3012 fprintf_unfiltered (log, _("\n\tar_base: No AR registers"));
3015 if (tdep->a0_base == -1)
3016 fprintf_unfiltered (log, _("\n\ta0_base: No Ax registers"));
3018 buf = ui_file_xstrdup (log, &length);
3019 make_cleanup (xfree, buf);
3021 internal_error (__FILE__, __LINE__,
3022 _("the following are invalid: %s"), buf);
3023 do_cleanups (cleanups);
3027 /* Derive specific register numbers from the array of registers. */
3030 xtensa_derive_tdep (struct gdbarch_tdep *tdep)
3032 xtensa_register_t* rmap;
3033 int n, max_size = 4;
3036 tdep->num_nopriv_regs = 0;
3038 /* Special registers 0..255 (core). */
3039 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3041 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3043 if (rmap->target_number == 0x0020)
3044 tdep->pc_regnum = n;
3045 else if (rmap->target_number == 0x0100)
3047 else if (rmap->target_number == 0x0000)
3049 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3050 tdep->wb_regnum = n;
3051 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3052 tdep->ws_regnum = n;
3053 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3054 tdep->debugcause_regnum = n;
3055 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3056 tdep->exccause_regnum = n;
3057 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3058 tdep->excvaddr_regnum = n;
3059 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3060 tdep->lbeg_regnum = n;
3061 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3062 tdep->lend_regnum = n;
3063 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3064 tdep->lcount_regnum = n;
3065 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3066 tdep->sar_regnum = n;
3067 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3068 tdep->litbase_regnum = n;
3069 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3070 tdep->ps_regnum = n;
3072 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3073 tdep->interrupt_regnum = n;
3074 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3075 tdep->interrupt2_regnum = n;
3076 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3077 tdep->cpenable_regnum = n;
3080 if (rmap->byte_size > max_size)
3081 max_size = rmap->byte_size;
3082 if (rmap->mask != 0 && tdep->num_regs == 0)
3084 /* Find out out how to deal with priveleged registers.
3086 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3087 && tdep->num_nopriv_regs == 0)
3088 tdep->num_nopriv_regs = n;
3090 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3091 && tdep->num_regs == 0)
3095 /* Number of pseudo registers. */
3096 tdep->num_pseudo_regs = n - tdep->num_regs;
3098 /* Empirically determined maximum sizes. */
3099 tdep->max_register_raw_size = max_size;
3100 tdep->max_register_virtual_size = max_size;
3103 /* Module "constructor" function. */
3105 extern struct gdbarch_tdep xtensa_tdep;
3107 static struct gdbarch *
3108 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3110 struct gdbarch_tdep *tdep;
3111 struct gdbarch *gdbarch;
3112 struct xtensa_abi_handler *abi_handler;
3114 DEBUGTRACE ("gdbarch_init()\n");
3116 /* We have to set the byte order before we call gdbarch_alloc. */
3117 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3119 tdep = &xtensa_tdep;
3120 gdbarch = gdbarch_alloc (&info, tdep);
3121 xtensa_derive_tdep (tdep);
3123 /* Verify our configuration. */
3124 xtensa_verify_config (gdbarch);
3126 /* Pseudo-Register read/write. */
3127 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
3128 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
3130 /* Set target information. */
3131 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3132 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
3133 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3134 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3135 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3137 /* Renumber registers for known formats (stabs and dwarf2). */
3138 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3139 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3141 /* We provide our own function to get register information. */
3142 set_gdbarch_register_name (gdbarch, xtensa_register_name);
3143 set_gdbarch_register_type (gdbarch, xtensa_register_type);
3145 /* To call functions from GDB using dummy frame. */
3146 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
3148 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3150 set_gdbarch_return_value (gdbarch, xtensa_return_value);
3152 /* Advance PC across any prologue instructions to reach "real" code. */
3153 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
3155 /* Stack grows downward. */
3156 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3158 /* Set breakpoints. */
3159 set_gdbarch_breakpoint_from_pc (gdbarch, xtensa_breakpoint_from_pc);
3161 /* After breakpoint instruction or illegal instruction, pc still
3162 points at break instruction, so don't decrement. */
3163 set_gdbarch_decr_pc_after_break (gdbarch, 0);
3165 /* We don't skip args. */
3166 set_gdbarch_frame_args_skip (gdbarch, 0);
3168 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
3170 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
3172 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
3174 /* Frame handling. */
3175 frame_base_set_default (gdbarch, &xtensa_frame_base);
3176 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3177 dwarf2_append_unwinders (gdbarch);
3179 set_gdbarch_print_insn (gdbarch, print_insn_xtensa);
3181 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3183 xtensa_add_reggroups (gdbarch);
3184 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
3186 set_gdbarch_regset_from_core_section (gdbarch,
3187 xtensa_regset_from_core_section);
3189 set_solib_svr4_fetch_link_map_offsets
3190 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
3196 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3198 error (_("xtensa_dump_tdep(): not implemented"));
3201 /* Provide a prototype to silence -Wmissing-prototypes. */
3202 extern initialize_file_ftype _initialize_xtensa_tdep;
3205 _initialize_xtensa_tdep (void)
3207 struct cmd_list_element *c;
3209 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
3210 xtensa_init_reggroups ();
3212 add_setshow_zinteger_cmd ("xtensa",
3214 &xtensa_debug_level,
3215 _("Set Xtensa debugging."),
3216 _("Show Xtensa debugging."), _("\
3217 When non-zero, Xtensa-specific debugging is enabled. \
3218 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3221 &setdebuglist, &showdebuglist);