Support for Toshiba MeP.

diff --git a/utils/mep/testsuite/cfgs/cop-data-bus-width.cfg b/utils/mep/testsuite/cfgs/cop-data-bus-width.cfg
new file mode 100644 (file)
index 0000000..41eb820
--- /dev/null
+++ b/utils/mep/testsuite/cfgs/cop-data-bus-width.cfg
@@ -0,0 +1,21 @@
+GLOBAL_MAP = "$CFG_ROOT/gmap/test.map";
+
+ME_MODULE[mm_def] {
+       COP[cop_def] {
+               CGEN_DEFINE = "$CFG_ROOT/option_unit/cop1.cpu";
+       };
+};
+
+ME_MODULE[mm_32] {
+       COP[cop_32] {
+               CGEN_DEFINE = "$CFG_ROOT/option_unit/cop2.cpu";
+               DATA_BUS_WIDTH = 32;
+       };
+};
+
+ME_MODULE[mm_64] {
+       COP[cop_64] {
+               CGEN_DEFINE = "$CFG_ROOT/option_unit/cop3.cpu";
+               DATA_BUS_WIDTH = 64;
+       };
+};

diff --git a/utils/mep/testsuite/cfgs/test.cfg b/utils/mep/testsuite/cfgs/test.cfg
new file mode 100644 (file)
index 0000000..eeac666
--- /dev/null
+++ b/utils/mep/testsuite/cfgs/test.cfg
@@ -0,0 +1,79 @@
+GLOBAL_MAP = "$CFG_ROOT/gmap/test.map";
+
+ME_MODULE[mm_test] {
+       ME_ENGINE {
+               CORE {
+                       ID = 0;
+                       MUL = ON;
+                       DIV = ON;
+                       BIT = ON;
+                       LDZ = ON;
+                       ABS = ON;
+                       AVE = ON;
+                       MIN = ON;
+                       CLP = ON;
+                       SAT = ON;
+                       ENDIAN = BIG;
+               };
+               IMEM {
+                       SIZE = 16;
+               };
+               DMEM {
+                       SIZE = 32;
+                       BANK_NUM = 2;
+               };
+               ICACHE {
+                       SIZE = 16;
+               };
+               DCACHE {
+                       SIZE = 16;
+               };
+               INTC {
+                       CHANNEL_BITW = 32;
+               };
+               DSU {};
+       };
+       DSP[test_dsp] {
+               CGEN_DEFINE = "$CFG_ROOT/option_unit/byteswap_dsp.cpu";
+               SIM = "$CFG_ROOT/option_unit/byteswap_function.cxx";
+       };
+       UCI[test_uci] {
+               CGEN_DEFINE = "$CFG_ROOT/option_unit/square_uci.cpu";
+               SIM = "$CFG_ROOT/option_unit/square_function.cxx";
+       };
+       DMAC[dmac_max] { };
+       HW_ENGINE[timeofday_engine] {
+               SIM = "$CFG_ROOT/option_unit/timeofday_engine.cxx";
+               CBUS_ADDRESS = 0x4000;
+       };
+       LOCAL_MEM [lcm1] {
+               ADDRESS = 0x00600000;
+               SIZE = 1024;
+       };
+       LOCAL_MEM [lcm2] {
+               ADDRESS = 0x00610000;
+               SIZE = 256;
+       };
+};
+
+ME_MODULE[mm_min] {
+       ME_ENGINE {
+               CORE {
+                       ID = 1;
+                       MUL = OFF;
+                       DIV = OFF;
+                       BIT = OFF;
+                       LDZ = OFF;
+                       ABS = OFF;
+                       AVE = OFF;
+                       MIN = OFF;
+                       CLP = OFF;
+                       SAT = OFF;
+                       ENDIAN = BIG;
+               };
+               INTC {
+                       CHANNEL_BITW = 8;
+               };
+       };
+};
+