1 /* Misc. entries in the sh description file.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2009 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
15 #include "cgen/bitset.h"
21 /* Enum declaration for . */
22 typedef enum frc_names {
23 H_FRC_FR0, H_FRC_FR1, H_FRC_FR2, H_FRC_FR3
24 , H_FRC_FR4, H_FRC_FR5, H_FRC_FR6, H_FRC_FR7
25 , H_FRC_FR8, H_FRC_FR9, H_FRC_FR10, H_FRC_FR11
26 , H_FRC_FR12, H_FRC_FR13, H_FRC_FR14, H_FRC_FR15
29 /* Enum declaration for . */
30 typedef enum drc_names {
31 H_DRC_DR0 = 0, H_DRC_DR2 = 2, H_DRC_DR4 = 4, H_DRC_DR6 = 6
32 , H_DRC_DR8 = 8, H_DRC_DR10 = 10, H_DRC_DR12 = 12, H_DRC_DR14 = 14
35 /* Enum declaration for . */
36 typedef enum xf_names {
37 H_XF_XF0, H_XF_XF1, H_XF_XF2, H_XF_XF3
38 , H_XF_XF4, H_XF_XF5, H_XF_XF6, H_XF_XF7
39 , H_XF_XF8, H_XF_XF9, H_XF_XF10, H_XF_XF11
40 , H_XF_XF12, H_XF_XF13, H_XF_XF14, H_XF_XF15
43 // Insn attribute indices.
45 /* Enum declaration for cgen_insn attrs. */
46 typedef enum cgen_insn_attr {
47 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
48 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED
49 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_ILLSLOT, CGEN_INSN_FP_INSN
50 , CGEN_INSN_32_BIT_INSN, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH
51 , CGEN_INSN_ISA, CGEN_INSN_SH4_GROUP, CGEN_INSN_SH4A_GROUP, CGEN_INSN_END_NBOOLS
54 /* Number of non-boolean elements in cgen_insn_attr. */
55 #define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
59 /* Enum declaration for machine type selection. */
60 typedef enum mach_attr {
61 MACH_BASE, MACH_SH2, MACH_SH2E, MACH_SH2A_FPU
62 , MACH_SH2A_NOFPU, MACH_SH3, MACH_SH3E, MACH_SH4_NOFPU
63 , MACH_SH4, MACH_SH4A_NOFPU, MACH_SH4A, MACH_SH4AL
67 /* Enum declaration for instruction set selection. */
68 typedef enum isa_attr {
69 ISA_COMPACT, ISA_MEDIA, ISA_MAX
72 /* Enum declaration for sh4 insn groups. */
73 typedef enum sh4_group_attr {
74 SH4_GROUP_NONE, SH4_GROUP_MT, SH4_GROUP_EX, SH4_GROUP_BR
75 , SH4_GROUP_LS, SH4_GROUP_FE, SH4_GROUP_CO, SH4_GROUP_MAX
78 /* Enum declaration for sh4a insn groups. */
79 typedef enum sh4a_group_attr {
80 SH4A_GROUP_NONE, SH4A_GROUP_MT, SH4A_GROUP_EX, SH4A_GROUP_BR
81 , SH4A_GROUP_LS, SH4A_GROUP_FE, SH4A_GROUP_CO, SH4A_GROUP_MAX
90 enum sh4_group_attr sh4_group;
91 enum sh4a_group_attr sh4a_group;
92 inline unsigned int get_mach_attr () { return mach; }
93 inline CGEN_BITSET get_isa_attr () { return isa; }
94 inline enum sh4_group_attr get_sh4_group_attr () { return sh4_group; }
95 inline enum sh4a_group_attr get_sh4a_group_attr () { return sh4a_group; }
96 inline int get_alias_attr () { return (bools & (1<<CGEN_INSN_ALIAS)) != 0; }
97 inline int get_virtual_attr () { return (bools & (1<<CGEN_INSN_VIRTUAL)) != 0; }
98 inline int get_uncond_cti_attr () { return (bools & (1<<CGEN_INSN_UNCOND_CTI)) != 0; }
99 inline int get_cond_cti_attr () { return (bools & (1<<CGEN_INSN_COND_CTI)) != 0; }
100 inline int get_skip_cti_attr () { return (bools & (1<<CGEN_INSN_SKIP_CTI)) != 0; }
101 inline int get_delay_slot_attr () { return (bools & (1<<CGEN_INSN_DELAY_SLOT)) != 0; }
102 inline int get_relaxable_attr () { return (bools & (1<<CGEN_INSN_RELAXABLE)) != 0; }
103 inline int get_relaxed_attr () { return (bools & (1<<CGEN_INSN_RELAXED)) != 0; }
104 inline int get_no_dis_attr () { return (bools & (1<<CGEN_INSN_NO_DIS)) != 0; }
105 inline int get_pbb_attr () { return (bools & (1<<CGEN_INSN_PBB)) != 0; }
106 inline int get_illslot_attr () { return (bools & (1<<CGEN_INSN_ILLSLOT)) != 0; }
107 inline int get_fp_insn_attr () { return (bools & (1<<CGEN_INSN_FP_INSN)) != 0; }
108 inline int get_32_bit_insn_attr () { return (bools & (1<<CGEN_INSN_32_BIT_INSN)) != 0; }
111 #define MACH_SH2_INSN_CHUNK_BITSIZE 0
112 #define MACH_SH2E_INSN_CHUNK_BITSIZE 0
113 #define MACH_SH2A_FPU_INSN_CHUNK_BITSIZE 0
114 #define MACH_SH2A_NOFPU_INSN_CHUNK_BITSIZE 0
115 #define MACH_SH3_INSN_CHUNK_BITSIZE 0
116 #define MACH_SH3E_INSN_CHUNK_BITSIZE 0
117 #define MACH_SH4_NOFPU_INSN_CHUNK_BITSIZE 0
118 #define MACH_SH4_INSN_CHUNK_BITSIZE 0
119 #define MACH_SH4A_NOFPU_INSN_CHUNK_BITSIZE 0
120 #define MACH_SH4A_INSN_CHUNK_BITSIZE 0
121 #define MACH_SH4AL_INSN_CHUNK_BITSIZE 0
122 #define MACH_SH5_INSN_CHUNK_BITSIZE 0
124 } // end sh namespace
126 #endif /* DESC_SH_H */