1 /* CPU class elements for mep.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2010 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
12 // This file is included in the middle of the cpu class struct.
16 // CPU state information.
22 /* General purpose registers */
24 /* Control/special registers */
26 /* 64-bit coprocessor registers */
28 /* 64-bit coprocessor registers, pending writes */
30 /* Coprocessor control registers */
32 /* Coprocessor control registers, pending writes */
36 void stream_cgen_hardware (std::ostream &ost) const
38 ost << hardware.h_pc << ' ';
39 for (int i = 0; i < 16; i++)
40 ost << hardware.h_gpr[i] << ' ';
41 for (int i = 0; i < 32; i++)
42 ost << hardware.h_csr[i] << ' ';
43 for (int i = 0; i < 32; i++)
44 ost << hardware.h_cr64[i] << ' ';
45 for (int i = 0; i < 32; i++)
46 ost << hardware.h_cr64_w[i] << ' ';
47 for (int i = 0; i < 64; i++)
48 ost << hardware.h_ccr[i] << ' ';
49 for (int i = 0; i < 64; i++)
50 ost << hardware.h_ccr_w[i] << ' ';
52 void destream_cgen_hardware (std::istream &ist)
55 for (int i = 0; i < 16; i++)
56 ist >> hardware.h_gpr[i];
57 for (int i = 0; i < 32; i++)
58 ist >> hardware.h_csr[i];
59 for (int i = 0; i < 32; i++)
60 ist >> hardware.h_cr64[i];
61 for (int i = 0; i < 32; i++)
62 ist >> hardware.h_cr64_w[i];
63 for (int i = 0; i < 64; i++)
64 ist >> hardware.h_ccr[i];
65 for (int i = 0; i < 64; i++)
66 ist >> hardware.h_ccr_w[i];
68 // C++ register access function templates
69 #define current_cpu this
71 inline USI h_pc_get () const { return this->hardware.h_pc; }
72 inline void h_pc_set (USI newval) { this->hardware.h_pc = newval; }
74 inline SI h_gpr_get (UINT regno) const { return this->hardware.h_gpr[regno]; }
75 inline void h_gpr_set (UINT regno, SI newval) { this->hardware.h_gpr[regno] = newval; }
77 inline SI h_csr_get (UINT regno) const { return current_cpu->cgen_get_csr_value (regno); }
78 inline void h_csr_set (UINT regno, SI newval) { current_cpu->cgen_set_csr_value (regno, newval);
81 inline DI h_cr64_get (UINT regno) const { return this->hardware.h_cr64[regno]; }
82 inline void h_cr64_set (UINT regno, DI newval) { current_cpu->h_cr64_queue_set (regno, newval);
85 inline DI h_cr64_w_get (UINT regno) const { return this->hardware.h_cr64_w[regno]; }
86 inline void h_cr64_w_set (UINT regno, DI newval) { this->hardware.h_cr64_w[regno] = newval; }
88 inline SI h_cr_get (UINT regno) const { return TRUNCDISI (current_cpu->h_cr64_get (regno)); }
89 inline void h_cr_set (UINT regno, SI newval) { current_cpu->h_cr64_set (regno, EXTSIDI (newval));
92 inline SI h_ccr_get (UINT regno) const { return this->hardware.h_ccr[regno]; }
93 inline void h_ccr_set (UINT regno, SI newval) { current_cpu->h_ccr_queue_set (regno, newval);
96 inline SI h_ccr_w_get (UINT regno) const { return this->hardware.h_ccr_w[regno]; }
97 inline void h_ccr_w_set (UINT regno, SI newval) { this->hardware.h_ccr_w[regno] = newval; }
99 inline DI h_cr_ivc2_get (UINT regno) const { return current_cpu->h_cr64_get (regno); }
100 inline void h_cr_ivc2_set (UINT regno, DI newval) { current_cpu->h_cr64_set (regno, newval);
103 inline SI h_ccr_ivc2_get (UINT regno) const { return current_cpu->h_ccr_get (regno); }
104 inline void h_ccr_ivc2_set (UINT regno, SI newval) { current_cpu->h_ccr_set (regno, newval);