1 /* Simulator model support for mepcop1_48.
3 THIS FILE IS MACHINE GENERATED WITH CGEN.
5 Copyright (C) 2000-2010 Red Hat, Inc.
7 This file is part of the Red Hat simulators.
12 #ifndef MEPCOP1_48_MODEL_H
13 #define MEPCOP1_48_MODEL_H
16 #include "cgen-model.h"
22 class mepcop1_48_mep_model : public cgen_model
25 mepcop1_48_mep_model (mep_ext1_cpu *cpu);
27 // Call the proper unit modelling function for the given insn.
28 UINT model_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache* sem)
30 return (this->*(timing[sem->idesc->sem_index].model_before)) (current_cpu, sem);
32 UINT model_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache* sem)
34 return (this->*(timing[sem->idesc->sem_index].model_after)) (current_cpu, sem);
37 // Function unit handlers
38 // To be overridden as needed.
39 virtual UINT model_u_store_ctrl_reg_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, INT /*storereg*/)
43 virtual UINT model_u_store_ctrl_reg_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced, INT /*storereg*/)
45 return timing[idesc->sem_index].units[unit_num].done;
47 virtual UINT model_u_use_ctrl_reg_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, INT /*usereg*/)
51 virtual UINT model_u_use_ctrl_reg_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced, INT /*usereg*/)
53 return timing[idesc->sem_index].units[unit_num].done;
55 virtual UINT model_u_use_gpr_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, INT /*usereg*/)
59 virtual UINT model_u_use_gpr_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced, INT /*usereg*/)
61 return timing[idesc->sem_index].units[unit_num].done;
63 virtual UINT model_u_mul_gpr_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, INT /*resultreg*/)
67 virtual UINT model_u_mul_gpr_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced, INT /*resultreg*/)
69 return timing[idesc->sem_index].units[unit_num].done;
71 virtual UINT model_u_ldcb_gpr_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, INT /*loadreg*/)
75 virtual UINT model_u_ldcb_gpr_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced, INT /*loadreg*/)
77 return timing[idesc->sem_index].units[unit_num].done;
79 virtual UINT model_u_load_gpr_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, INT /*loadreg*/)
83 virtual UINT model_u_load_gpr_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced, INT /*loadreg*/)
85 return timing[idesc->sem_index].units[unit_num].done;
87 virtual UINT model_u_ldcb_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num)
91 virtual UINT model_u_ldcb_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced)
93 return timing[idesc->sem_index].units[unit_num].done;
95 virtual UINT model_u_stcb_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num)
99 virtual UINT model_u_stcb_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced)
101 return timing[idesc->sem_index].units[unit_num].done;
103 virtual UINT model_u_divide_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num)
107 virtual UINT model_u_divide_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced)
109 return timing[idesc->sem_index].units[unit_num].done;
111 virtual UINT model_u_multiply_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num)
115 virtual UINT model_u_multiply_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced)
117 return timing[idesc->sem_index].units[unit_num].done;
119 virtual UINT model_u_branch_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num)
123 virtual UINT model_u_branch_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced)
125 return timing[idesc->sem_index].units[unit_num].done;
127 virtual UINT model_u_exec_before (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num)
131 virtual UINT model_u_exec_after (mep_ext1_cpu *cpu, const struct mepcop1_48_idesc *idesc, int unit_num, unsigned long long referenced)
133 return timing[idesc->sem_index].units[unit_num].done;
137 // These methods call the appropriate unit modeller(s) for each insn.
138 UINT model_cmov_crn_rm_p0_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
139 UINT model_cmov_crn_rm_p0_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
140 UINT model_cmov_rn_crm_p0_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
141 UINT model_cmov_rn_crm_p0_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
142 UINT model_cmovc_ccrn_rm_p0_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
143 UINT model_cmovc_ccrn_rm_p0_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
144 UINT model_cmovc_rn_ccrm_p0_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
145 UINT model_cmovc_rn_ccrm_p0_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
146 UINT model_cmovh_crn_rm_p0_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
147 UINT model_cmovh_crn_rm_p0_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
148 UINT model_cmovh_rn_crm_p0_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
149 UINT model_cmovh_rn_crm_p0_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
150 UINT model_c0nop_P0_P0S_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
151 UINT model_c0nop_P0_P0S_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
152 UINT model_cpfsftbi_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
153 UINT model_cpfsftbi_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
154 UINT model_cpacmpeq_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
155 UINT model_cpacmpeq_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
156 UINT model_cpacmpeq_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
157 UINT model_cpacmpeq_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
158 UINT model_cpacmpeq_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
159 UINT model_cpacmpeq_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
160 UINT model_cpacmpne_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
161 UINT model_cpacmpne_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
162 UINT model_cpacmpne_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
163 UINT model_cpacmpne_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
164 UINT model_cpacmpne_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
165 UINT model_cpacmpne_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
166 UINT model_cpacmpgtu_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
167 UINT model_cpacmpgtu_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
168 UINT model_cpacmpgt_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
169 UINT model_cpacmpgt_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
170 UINT model_cpacmpgt_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
171 UINT model_cpacmpgt_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
172 UINT model_cpacmpgtu_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
173 UINT model_cpacmpgtu_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
174 UINT model_cpacmpgt_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
175 UINT model_cpacmpgt_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
176 UINT model_cpacmpgeu_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
177 UINT model_cpacmpgeu_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
178 UINT model_cpacmpge_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
179 UINT model_cpacmpge_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
180 UINT model_cpacmpge_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
181 UINT model_cpacmpge_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
182 UINT model_cpacmpgeu_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
183 UINT model_cpacmpgeu_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
184 UINT model_cpacmpge_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
185 UINT model_cpacmpge_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
186 UINT model_cpocmpeq_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
187 UINT model_cpocmpeq_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
188 UINT model_cpocmpeq_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
189 UINT model_cpocmpeq_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
190 UINT model_cpocmpeq_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
191 UINT model_cpocmpeq_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
192 UINT model_cpocmpne_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
193 UINT model_cpocmpne_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
194 UINT model_cpocmpne_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
195 UINT model_cpocmpne_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
196 UINT model_cpocmpne_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
197 UINT model_cpocmpne_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
198 UINT model_cpocmpgtu_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
199 UINT model_cpocmpgtu_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
200 UINT model_cpocmpgt_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
201 UINT model_cpocmpgt_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
202 UINT model_cpocmpgt_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
203 UINT model_cpocmpgt_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
204 UINT model_cpocmpgtu_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
205 UINT model_cpocmpgtu_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
206 UINT model_cpocmpgt_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
207 UINT model_cpocmpgt_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
208 UINT model_cpocmpgeu_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
209 UINT model_cpocmpgeu_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
210 UINT model_cpocmpge_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
211 UINT model_cpocmpge_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
212 UINT model_cpocmpge_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
213 UINT model_cpocmpge_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
214 UINT model_cpocmpgeu_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
215 UINT model_cpocmpgeu_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
216 UINT model_cpocmpge_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
217 UINT model_cpocmpge_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
218 UINT model_cdadd3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
219 UINT model_cdadd3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
220 UINT model_cpsub3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
221 UINT model_cpsub3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
222 UINT model_cpsub3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
223 UINT model_cpsub3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
224 UINT model_cpsub3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
225 UINT model_cpsub3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
226 UINT model_cdsub3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
227 UINT model_cdsub3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
228 UINT model_cpsadd3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
229 UINT model_cpsadd3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
230 UINT model_cpsadd3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
231 UINT model_cpsadd3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
232 UINT model_cpssub3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
233 UINT model_cpssub3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
234 UINT model_cpssub3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
235 UINT model_cpssub3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
236 UINT model_cpextuaddu3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
237 UINT model_cpextuaddu3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
238 UINT model_cpextuadd3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
239 UINT model_cpextuadd3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
240 UINT model_cpextladdu3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
241 UINT model_cpextladdu3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
242 UINT model_cpextladd3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
243 UINT model_cpextladd3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
244 UINT model_cpextusubu3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
245 UINT model_cpextusubu3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
246 UINT model_cpextusub3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
247 UINT model_cpextusub3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
248 UINT model_cpextlsubu3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
249 UINT model_cpextlsubu3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
250 UINT model_cpextlsub3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
251 UINT model_cpextlsub3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
252 UINT model_cpaveu3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
253 UINT model_cpaveu3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
254 UINT model_cpave3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
255 UINT model_cpave3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
256 UINT model_cpave3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
257 UINT model_cpave3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
258 UINT model_cpave3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
259 UINT model_cpave3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
260 UINT model_cpaddsru3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
261 UINT model_cpaddsru3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
262 UINT model_cpaddsr3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
263 UINT model_cpaddsr3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
264 UINT model_cpaddsr3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
265 UINT model_cpaddsr3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
266 UINT model_cpaddsr3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
267 UINT model_cpaddsr3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
268 UINT model_cpabsu3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
269 UINT model_cpabsu3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
270 UINT model_cpabs3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
271 UINT model_cpabs3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
272 UINT model_cpabs3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
273 UINT model_cpabs3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
274 UINT model_cpand3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
275 UINT model_cpand3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
276 UINT model_cpor3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
277 UINT model_cpor3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
278 UINT model_cpnor3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
279 UINT model_cpnor3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
280 UINT model_cpxor3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
281 UINT model_cpxor3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
282 UINT model_cppacku_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
283 UINT model_cppacku_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
284 UINT model_cppack_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
285 UINT model_cppack_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
286 UINT model_cppack_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
287 UINT model_cppack_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
288 UINT model_cpmaxu3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
289 UINT model_cpmaxu3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
290 UINT model_cpmax3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
291 UINT model_cpmax3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
292 UINT model_cpmax3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
293 UINT model_cpmax3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
294 UINT model_cpmaxu3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
295 UINT model_cpmaxu3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
296 UINT model_cpmax3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
297 UINT model_cpmax3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
298 UINT model_cpminu3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
299 UINT model_cpminu3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
300 UINT model_cpmin3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
301 UINT model_cpmin3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
302 UINT model_cpmin3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
303 UINT model_cpmin3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
304 UINT model_cpminu3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
305 UINT model_cpminu3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
306 UINT model_cpmin3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
307 UINT model_cpmin3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
308 UINT model_cpsrl3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
309 UINT model_cpsrl3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
310 UINT model_cpssrl3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
311 UINT model_cpssrl3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
312 UINT model_cpsrl3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
313 UINT model_cpsrl3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
314 UINT model_cpssrl3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
315 UINT model_cpssrl3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
316 UINT model_cpsrl3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
317 UINT model_cpsrl3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
318 UINT model_cpssrl3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
319 UINT model_cpssrl3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
320 UINT model_cdsrl3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
321 UINT model_cdsrl3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
322 UINT model_cpsra3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
323 UINT model_cpsra3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
324 UINT model_cpssra3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
325 UINT model_cpssra3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
326 UINT model_cpsra3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
327 UINT model_cpsra3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
328 UINT model_cpssra3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
329 UINT model_cpssra3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
330 UINT model_cpsra3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
331 UINT model_cpsra3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
332 UINT model_cpssra3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
333 UINT model_cpssra3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
334 UINT model_cdsra3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
335 UINT model_cdsra3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
336 UINT model_cpsll3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
337 UINT model_cpsll3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
338 UINT model_cpssll3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
339 UINT model_cpssll3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
340 UINT model_cpsll3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
341 UINT model_cpsll3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
342 UINT model_cpssll3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
343 UINT model_cpssll3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
344 UINT model_cpsll3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
345 UINT model_cpsll3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
346 UINT model_cpssll3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
347 UINT model_cpssll3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
348 UINT model_cdsll3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
349 UINT model_cdsll3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
350 UINT model_cpsla3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
351 UINT model_cpsla3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
352 UINT model_cpsla3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
353 UINT model_cpsla3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
354 UINT model_cpsrli3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
355 UINT model_cpsrli3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
356 UINT model_cpsrli3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
357 UINT model_cpsrli3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
358 UINT model_cpsrli3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
359 UINT model_cpsrli3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
360 UINT model_cdsrli3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
361 UINT model_cdsrli3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
362 UINT model_cpsrai3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
363 UINT model_cpsrai3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
364 UINT model_cpsrai3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
365 UINT model_cpsrai3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
366 UINT model_cpsrai3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
367 UINT model_cpsrai3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
368 UINT model_cdsrai3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
369 UINT model_cdsrai3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
370 UINT model_cpslli3_b_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
371 UINT model_cpslli3_b_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
372 UINT model_cpslli3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
373 UINT model_cpslli3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
374 UINT model_cpslli3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
375 UINT model_cpslli3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
376 UINT model_cdslli3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
377 UINT model_cdslli3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
378 UINT model_cpslai3_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
379 UINT model_cpslai3_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
380 UINT model_cpslai3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
381 UINT model_cpslai3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
382 UINT model_cpclipiu3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
383 UINT model_cpclipiu3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
384 UINT model_cpclipi3_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
385 UINT model_cpclipi3_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
386 UINT model_cdclipiu3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
387 UINT model_cdclipiu3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
388 UINT model_cdclipi3_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
389 UINT model_cdclipi3_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
390 UINT model_cpmovi_h_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
391 UINT model_cpmovi_h_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
392 UINT model_cpmoviu_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
393 UINT model_cpmoviu_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
394 UINT model_cpmovi_w_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
395 UINT model_cpmovi_w_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
396 UINT model_cdmoviu_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
397 UINT model_cdmoviu_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
398 UINT model_cdmovi_P0_P1_before (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
399 UINT model_cdmovi_P0_P1_after (mep_ext1_cpu *current_cpu, mepcop1_48_scache *sem);
401 /* Enum declaration for unit types. */
402 typedef enum unit_number {
403 UNIT_NONE, UNIT_U_STORE_CTRL_REG, UNIT_U_USE_CTRL_REG, UNIT_U_USE_GPR
404 , UNIT_U_MUL_GPR, UNIT_U_LDCB_GPR, UNIT_U_LOAD_GPR, UNIT_U_LDCB
405 , UNIT_U_STCB, UNIT_U_DIVIDE, UNIT_U_MULTIPLY, UNIT_U_BRANCH
406 , UNIT_U_EXEC, UNIT_MAX
415 static const int MAX_UNITS = 1;
417 typedef UINT (mepcop1_48_mep_model::*model_function) (mep_ext1_cpu* current_cpu, mepcop1_48_scache* sem);
420 // This is an integer that identifies this insn.
422 // Functions to handle insn-specific profiling.
423 model_function model_before;
424 model_function model_after;
425 // Array of function units used by this insn.
426 unit units[MAX_UNITS];
429 static const insn_timing timing[];
432 } // namespace mep_ext1
434 #endif // MEPCOP1_48_MODEL_H