* config/i386/i386.h (FIRST_PSEUDO_REGISTER): Define to 54.

        (FIXED_REGISTERS, CALL_USED_REGISTERS): Add fpcr register.
        (REG_ALLOC_ORDER): Add one element to allocate fpcr register.
        (FRAME_POINTER_REGNUM): Update register number to 21.
        (REG_CLASS_CONTENTS): Update contents for added fpcr register.
        (HI_REGISTER_NAMES): Add "fpcr" for fpcr register.

        * config/i386/i386.c (regclass_map): Add fpcr entry.
        (dbx_register_map, dbx64_register_map, svr4_dbx_register_map):
        Add fpcr entry.
        (print_reg): Assert REGNO (x) != FPCR_REG.

        * config/i386/i386.md (FPCR_REG, R11_REG): New constants.
        (DIRFLAG_REG): Renumber.
        (x86_fnstcw_1, x86_fldcw_1): Use FPCR_REG instead of FPSR_REG.
        (*sibcall_1_rex64_v, *sibcall_value_1_rex64_v): Use R11_REG.
        (sse_prologue_save, *sse_prologue_save_insn): Renumber
        hardcoded SSE register numbers.

        * config/i386/mmx.md (mmx_emms, mmx_femms): Renumber
        hardcoded MMX register numbers.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@118014 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index d47b94b..65be7f1 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,27 @@
+2006-10-24  Uros Bizjak  <uros@kss-loka.si>
+
+       * config/i386/i386.h (FIRST_PSEUDO_REGISTER): Define to 54.
+       (FIXED_REGISTERS, CALL_USED_REGISTERS): Add fpcr register.
+       (REG_ALLOC_ORDER): Add one element to allocate fpcr register.
+       (FRAME_POINTER_REGNUM): Update register number to 21.
+       (REG_CLASS_CONTENTS): Update contents for added fpcr register.
+       (HI_REGISTER_NAMES): Add "fpcr" for fpcr register.
+
+       * config/i386/i386.c (regclass_map): Add fpcr entry.
+       (dbx_register_map, dbx64_register_map, svr4_dbx_register_map):
+       Add fpcr entry.
+       (print_reg): Assert REGNO (x) != FPCR_REG.
+
+       * config/i386/i386.md (FPCR_REG, R11_REG): New constants.
+       (DIRFLAG_REG): Renumber.
+       (x86_fnstcw_1, x86_fldcw_1): Use FPCR_REG instead of FPSR_REG.
+       (*sibcall_1_rex64_v, *sibcall_value_1_rex64_v): Use R11_REG.
+       (sse_prologue_save, *sse_prologue_save_insn): Renumber
+       hardcoded SSE register numbers.
+
+       * config/i386/mmx.md (mmx_emms, mmx_femms): Renumber
+       hardcoded MMX register numbers.
+
 2006-10-24  Kaveh R. Ghazi  <ghazi@caip.rutgers.edu>
 
        PR middle-end/29335

diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index d3223a4..0738169 100644 (file)
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -855,8 +855,8 @@ enum reg_class const regclass_map[FIRST_PSEUDO_REGISTER] =
   FLOAT_REGS, FLOAT_REGS, FLOAT_REGS, FLOAT_REGS,
   /* arg pointer */
   NON_Q_REGS,
-  /* flags, fpsr, dirflag, frame */
-  NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
+  /* flags, fpsr, fpcr, dirflag, frame */
+  NO_REGS, NO_REGS, NO_REGS, NO_REGS, NON_Q_REGS,
   SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS, SSE_REGS,
   SSE_REGS, SSE_REGS,
   MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS, MMX_REGS,
@@ -873,7 +873,7 @@ int const dbx_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 2, 1, 3, 6, 7, 4, 5,              /* general regs */
   12, 13, 14, 15, 16, 17, 18, 19,      /* fp regs */
-  -1, -1, -1, -1, -1,                  /* arg, flags, fpsr, dir, frame */
+  -1, -1, -1, -1, -1, -1,              /* arg, flags, fpsr, fpcr, dir, frame */
   21, 22, 23, 24, 25, 26, 27, 28,      /* SSE */
   29, 30, 31, 32, 33, 34, 35, 36,       /* MMX */
   -1, -1, -1, -1, -1, -1, -1, -1,      /* extended integer registers */
@@ -896,7 +896,7 @@ int const dbx64_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 1, 2, 3, 4, 5, 6, 7,              /* general regs */
   33, 34, 35, 36, 37, 38, 39, 40,      /* fp regs */
-  -1, -1, -1, -1, -1,                  /* arg, flags, fpsr, dir, frame */
+  -1, -1, -1, -1, -1, -1,              /* arg, flags, fpsr, fpcr, dir, frame */
   17, 18, 19, 20, 21, 22, 23, 24,      /* SSE */
   41, 42, 43, 44, 45, 46, 47, 48,       /* MMX */
   8,9,10,11,12,13,14,15,               /* extended integer registers */
@@ -961,7 +961,7 @@ int const svr4_dbx_register_map[FIRST_PSEUDO_REGISTER] =
 {
   0, 2, 1, 3, 6, 7, 5, 4,              /* general regs */
   11, 12, 13, 14, 15, 16, 17, 18,      /* fp regs */
-  -1, 9, -1, -1, -1,                   /* arg, flags, fpsr, dir, frame */
+  -1, 9, -1, -1, -1, -1,               /* arg, flags, fpsr, fpcr, dir, frame */
   21, 22, 23, 24, 25, 26, 27, 28,      /* SSE registers */
   29, 30, 31, 32, 33, 34, 35, 36,      /* MMX registers */
   -1, -1, -1, -1, -1, -1, -1, -1,      /* extended integer registers */
@@ -7443,7 +7443,8 @@ print_reg (rtx x, int code, FILE *file)
   gcc_assert (REGNO (x) != ARG_POINTER_REGNUM
              && REGNO (x) != FRAME_POINTER_REGNUM
              && REGNO (x) != FLAGS_REG
-             && REGNO (x) != FPSR_REG);
+             && REGNO (x) != FPSR_REG
+             && REGNO (x) != FPCR_REG);
 
   if (ASSEMBLER_DIALECT == ASM_ATT || USER_LABEL_PREFIX[0] == 0)
     putc ('%', file);

diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
index bebc91e..8df94ac 100644 (file)
--- a/gcc/config/i386/i386.h
+++ b/gcc/config/i386/i386.h
@@ -711,7 +711,7 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
    eliminated during reloading in favor of either the stack or frame
    pointer.  */
 
-#define FIRST_PSEUDO_REGISTER 53
+#define FIRST_PSEUDO_REGISTER 54
 
 /* Number of hardware registers that go into the DWARF-2 unwind info.
    If not defined, equals FIRST_PSEUDO_REGISTER.  */
@@ -731,8 +731,8 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 #define FIXED_REGISTERS                                                \
 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/     \
 {  0, 0, 0, 0, 0, 0, 0, 1, 0,  0,  0,  0,  0,  0,  0,  0,      \
-/*arg,flags,fpsr,dir,frame*/                                   \
-    1,    1,   1,  1,    1,                                    \
+/*arg,flags,fpsr,fpcr,dir,frame*/                              \
+    1,    1,   1,   1,  1,    1,                               \
 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/                    \
      0,   0,   0,   0,   0,   0,   0,   0,                     \
 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/                    \
@@ -759,10 +759,10 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 #define CALL_USED_REGISTERS                                    \
 /*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/     \
 {  1, 1, 1, 0, 3, 3, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,      \
-/*arg,flags,fpsr,dir,frame*/                                   \
-     1,   1,   1,  1,    1,                                    \
+/*arg,flags,fpsr,fpcr,dir,frame*/                              \
+    1,   1,    1,   1,  1,    1,                               \
 /*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/                    \
-     1,   1,   1,   1,   1,  1,    1,   1,                     \
+     1,   1,   1,   1,   1,   1,   1,   1,                     \
 /*mmx0,mmx1,mmx2,mmx3,mmx4,mmx5,mmx6,mmx7*/                    \
      1,   1,   1,   1,   1,   1,   1,   1,                     \
 /*  r8,  r9, r10, r11, r12, r13, r14, r15*/                    \
@@ -783,11 +783,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv);
 {  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\
    18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, \
    33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,  \
-   48, 49, 50, 51, 52 }
+   48, 49, 50, 51, 52, 53 }
 
 /* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order
    to be rearranged based on a particular function.  When using sse math,
-   we want to allocate SSE before x87 registers and vice vera.  */
+   we want to allocate SSE before x87 registers and vice versa.  */
 
 #define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()
 
@@ -940,7 +940,7 @@ do {                                                                        \
 #define HARD_FRAME_POINTER_REGNUM 6
 
 /* Base register for access to local variables of the function.  */
-#define FRAME_POINTER_REGNUM 20
+#define FRAME_POINTER_REGNUM 21
 
 /* First floating point reg */
 #define FIRST_FLOAT_REG 8
@@ -1053,7 +1053,7 @@ do {                                                                      \
    opcode needs reg %ebx.  But some systems pass args to the OS in ebx,
    and the "b" register constraint is useful in asms for syscalls.
 
-   The flags and fpsr registers are in no class.  */
+   The flags, fpsr and fpcr registers are in no class.  */
 
 enum reg_class
 {
@@ -1134,21 +1134,21 @@ enum reg_class
       { 0x10,     0x0 }, { 0x20, 0x0 },        /* SIREG, DIREG */              \
       { 0x03,     0x0 },               /* AD_REGS */                   \
       { 0x0f,     0x0 },               /* Q_REGS */                    \
-  { 0x1100f0,  0x1fe0 },               /* NON_Q_REGS */                \
-      { 0x7f,  0x1fe0 },               /* INDEX_REGS */                \
-  { 0x1100ff,  0x0 },                  /* LEGACY_REGS */               \
-  { 0x1100ff,  0x1fe0 },               /* GENERAL_REGS */              \
+  { 0x2100f0,  0x3fc0 },               /* NON_Q_REGS */                \
+      { 0x7f,  0x3fc0 },               /* INDEX_REGS */                \
+  { 0x2100ff,     0x0 },               /* LEGACY_REGS */               \
+  { 0x2100ff,  0x3fc0 },               /* GENERAL_REGS */              \
      { 0x100,     0x0 }, { 0x0200, 0x0 },/* FP_TOP_REG, FP_SECOND_REG */\
     { 0xff00,     0x0 },               /* FLOAT_REGS */                \
-{ 0x1fe00000,0x1fe000 },               /* SSE_REGS */                  \
-{ 0xe0000000,    0x1f },               /* MMX_REGS */                  \
-{ 0x1fe00100,0x1fe000 },               /* FP_TOP_SSE_REG */            \
-{ 0x1fe00200,0x1fe000 },               /* FP_SECOND_SSE_REG */         \
-{ 0x1fe0ff00,0x1fe000 },               /* FLOAT_SSE_REGS */            \
-   { 0x1ffff,  0x1fe0 },               /* FLOAT_INT_REGS */            \
-{ 0x1fe100ff,0x1fffe0 },               /* INT_SSE_REGS */              \
-{ 0x1fe1ffff,0x1fffe0 },               /* FLOAT_INT_SSE_REGS */        \
-{ 0xffffffff,0x1fffff }                                                        \
+{ 0x3fc00000,0x3fc000 },               /* SSE_REGS */                  \
+{ 0xc0000000,    0x3f },               /* MMX_REGS */                  \
+{ 0x3fc00100,0x3fc000 },               /* FP_TOP_SSE_REG */            \
+{ 0x3fc00200,0x3fc000 },               /* FP_SECOND_SSE_REG */         \
+{ 0x3fc0ff00,0x3fc000 },               /* FLOAT_SSE_REGS */            \
+   { 0x1ffff,  0x3fc0 },               /* FLOAT_INT_REGS */            \
+{ 0x3fc100ff,0x3fffc0 },               /* INT_SSE_REGS */              \
+{ 0x3fc1ffff,0x3fffc0 },               /* FLOAT_INT_SSE_REGS */        \
+{ 0xffffffff,0x3fffff }                                                        \
 }
 
 /* The same information, inverted:
@@ -1908,9 +1908,9 @@ do {                                                      \
 #define HI_REGISTER_NAMES                                              \
 {"ax","dx","cx","bx","si","di","bp","sp",                              \
  "st","st(1)","st(2)","st(3)","st(4)","st(5)","st(6)","st(7)",         \
- "argp", "flags", "fpsr", "dirflag", "frame",                          \
+ "argp", "flags", "fpsr", "fpcr", "dirflag", "frame",                  \
  "xmm0","xmm1","xmm2","xmm3","xmm4","xmm5","xmm6","xmm7",              \
- "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7"        ,               \
+ "mm0", "mm1", "mm2", "mm3", "mm4", "mm5", "mm6", "mm7",               \
  "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",                 \
  "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15"}
 

diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 049b86a..ac26aab 100644 (file)
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -178,7 +178,9 @@
    (SP_REG                      7)
    (FLAGS_REG                  17)
    (FPSR_REG                   18)
-   (DIRFLAG_REG                        19)
+   (FPCR_REG                   19)
+   (DIRFLAG_REG                        20)
+   (R11_REG                    41)
   ])
 
 ;; Insns whose names begin with "x86_" are emitted by gen_FOO calls
@@ -4429,7 +4431,7 @@
 
 (define_insn "x86_fnstcw_1"
   [(set (match_operand:HI 0 "memory_operand" "=m")
-       (unspec:HI [(reg:HI FPSR_REG)] UNSPEC_FSTCW))]
+       (unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
   "TARGET_80387"
   "fnstcw\t%0"
   [(set_attr "length" "2")
@@ -4437,7 +4439,7 @@
    (set_attr "unit" "i387")])
 
 (define_insn "x86_fldcw_1"
-  [(set (reg:HI FPSR_REG)
+  [(set (reg:HI FPCR_REG)
        (unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
   "TARGET_80387"
   "fldcw\t%0"
@@ -14162,7 +14164,7 @@
   [(set_attr "type" "call")])
 
 (define_insn "*sibcall_1_rex64_v"
-  [(call (mem:QI (reg:DI 40))
+  [(call (mem:QI (reg:DI R11_REG))
         (match_operand 0 "" ""))]
   "SIBLING_CALL_P (insn) && TARGET_64BIT"
   "jmp\t*%%r11"
@@ -20652,7 +20654,7 @@
 
 (define_insn "*sibcall_value_1_rex64_v"
   [(set (match_operand 0 "" "")
-       (call (mem:QI (reg:DI 40))
+       (call (mem:QI (reg:DI R11_REG))
              (match_operand:DI 1 "" "")))]
   "SIBLING_CALL_P (insn) && TARGET_64BIT"
   "jmp\t*%%r11"
@@ -20671,14 +20673,14 @@
 
 (define_expand "sse_prologue_save"
   [(parallel [(set (match_operand:BLK 0 "" "")
-                  (unspec:BLK [(reg:DI 21)
-                               (reg:DI 22)
+                  (unspec:BLK [(reg:DI 22)
                                (reg:DI 23)
                                (reg:DI 24)
                                (reg:DI 25)
                                (reg:DI 26)
                                (reg:DI 27)
-                               (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
+                               (reg:DI 28)
+                               (reg:DI 29)] UNSPEC_SSE_PROLOGUE_SAVE))
              (use (match_operand:DI 1 "register_operand" ""))
              (use (match_operand:DI 2 "immediate_operand" ""))
              (use (label_ref:DI (match_operand 3 "" "")))])]
@@ -20688,14 +20690,14 @@
 (define_insn "*sse_prologue_save_insn"
   [(set (mem:BLK (plus:DI (match_operand:DI 0 "register_operand" "R")
                          (match_operand:DI 4 "const_int_operand" "n")))
-       (unspec:BLK [(reg:DI 21)
-                    (reg:DI 22)
+       (unspec:BLK [(reg:DI 22)
                     (reg:DI 23)
                     (reg:DI 24)
                     (reg:DI 25)
                     (reg:DI 26)
                     (reg:DI 27)
-                    (reg:DI 28)] UNSPEC_SSE_PROLOGUE_SAVE))
+                    (reg:DI 28)
+                    (reg:DI 29)] UNSPEC_SSE_PROLOGUE_SAVE))
    (use (match_operand:DI 1 "register_operand" "r"))
    (use (match_operand:DI 2 "const_int_operand" "i"))
    (use (label_ref:DI (match_operand 3 "" "X")))]

diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md
index 4f0ab2c..6fc9da4 100644 (file)
--- a/gcc/config/i386/mmx.md
+++ b/gcc/config/i386/mmx.md
@@ -1396,14 +1396,14 @@
    (clobber (reg:XF 13))
    (clobber (reg:XF 14))
    (clobber (reg:XF 15))
-   (clobber (reg:DI 29))
    (clobber (reg:DI 30))
    (clobber (reg:DI 31))
    (clobber (reg:DI 32))
    (clobber (reg:DI 33))
    (clobber (reg:DI 34))
    (clobber (reg:DI 35))
-   (clobber (reg:DI 36))]
+   (clobber (reg:DI 36))
+   (clobber (reg:DI 37))]
   "TARGET_MMX"
   "emms"
   [(set_attr "type" "mmx")
@@ -1419,14 +1419,14 @@
    (clobber (reg:XF 13))
    (clobber (reg:XF 14))
    (clobber (reg:XF 15))
-   (clobber (reg:DI 29))
    (clobber (reg:DI 30))
    (clobber (reg:DI 31))
    (clobber (reg:DI 32))
    (clobber (reg:DI 33))
    (clobber (reg:DI 34))
    (clobber (reg:DI 35))
-   (clobber (reg:DI 36))]
+   (clobber (reg:DI 36))
+   (clobber (reg:DI 37))]
   "TARGET_3DNOW"
   "femms"
   [(set_attr "type" "mmx")