gcc/

	* doc/md.texi: Document the MIPS "v" constraint.
	* config/mips/mips.h (reg_class): Revert last change.
	(REG_CLASS_NAMES): Likewise.
	(REG_CLASS_CONTENTS): Likewise.
	* config/mips/mips.c (mips_regno_to_class): Likewise.
	* config/mips/constraints.md (v): Likewise, but add documentation.
	Add a comment to say that this constraint should not be used in
	gcc code.

git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@137734 138bc75d-0d04-0410-961f-82ee72b054a4

diff --git a/gcc/ChangeLog b/gcc/ChangeLog
index 1faa2a1..895d683 100644 (file)
--- a/gcc/ChangeLog
+++ b/gcc/ChangeLog
@@ -1,3 +1,14 @@
+2008-07-12  Richard Sandiford  <rdsandiford@googlemail.com>
+
+       * doc/md.texi: Document the MIPS "v" constraint.
+       * config/mips/mips.h (reg_class): Revert last change.
+       (REG_CLASS_NAMES): Likewise.
+       (REG_CLASS_CONTENTS): Likewise.
+       * config/mips/mips.c (mips_regno_to_class): Likewise.
+       * config/mips/constraints.md (v): Likewise, but add documentation.
+       Add a comment to say that this constraint should not be used in
+       gcc code.
+
 2008-07-11  DJ Delorie  <dj@redhat.com>
 
        * config/h8300/h8300.md (length): Fix branch offset limit.

diff --git a/gcc/config/mips/constraints.md b/gcc/config/mips/constraints.md
index ee44783..88fcbf6 100644 (file)
--- a/gcc/config/mips/constraints.md
+++ b/gcc/config/mips/constraints.md
@@ -55,6 +55,12 @@
 (define_register_constraint "j" "PIC_FN_ADDR_REG"
   "@internal")
 
+;; Don't use this constraint in gcc code!  It runs the risk of
+;; introducing a spill failure; see tls_get_tp_<mode>.
+(define_register_constraint "v" "V1_REG"
+  "Register @code{$3}.  Do not use this constraint in new code;
+   it is retained only for compatibility with glibc.")
+
 (define_register_constraint "y" "GR_REGS"
   "Equivalent to @code{r}; retained for backwards compatibility.")
 

diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c
index 3bbae44..d1def42 100644 (file)
--- a/gcc/config/mips/mips.c
+++ b/gcc/config/mips/mips.c
@@ -479,7 +479,7 @@ static const char *mips_hi_relocs[NUM_SYMBOL_TYPES];
 
 /* Index R is the smallest register class that contains register R.  */
 const enum reg_class mips_regno_to_class[FIRST_PSEUDO_REGISTER] = {
-  LEA_REGS,    LEA_REGS,       M16_NA_REGS,    M16_NA_REGS,
+  LEA_REGS,    LEA_REGS,       M16_NA_REGS,    V1_REG,
   M16_REGS,    M16_REGS,       M16_REGS,       M16_REGS,
   LEA_REGS,    LEA_REGS,       LEA_REGS,       LEA_REGS,
   LEA_REGS,    LEA_REGS,       LEA_REGS,       LEA_REGS,

diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h
index c29a5e8..8518a86 100644 (file)
--- a/gcc/config/mips/mips.h
+++ b/gcc/config/mips/mips.h
@@ -1690,6 +1690,7 @@ enum reg_class
   T_REG,                       /* mips16 T register ($24) */
   M16_T_REGS,                  /* mips16 registers plus T register */
   PIC_FN_ADDR_REG,             /* SVR4 PIC function address register */
+  V1_REG,                      /* Register $v1 ($3) used for TLS access.  */
   LEA_REGS,                    /* Every GPR except $25 */
   GR_REGS,                     /* integer registers */
   FP_REGS,                     /* floating point registers */
@@ -1730,6 +1731,7 @@ enum reg_class
   "T_REG",                                                             \
   "M16_T_REGS",                                                                \
   "PIC_FN_ADDR_REG",                                                   \
+  "V1_REG",                                                            \
   "LEA_REGS",                                                          \
   "GR_REGS",                                                           \
   "FP_REGS",                                                           \
@@ -1773,6 +1775,7 @@ enum reg_class
   { 0x01000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },  /* mips16 T register */ \
   { 0x010300fc, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },  /* mips16 and T regs */ \
   { 0x02000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },  /* SVR4 PIC function address register */ \
+  { 0x00000008, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },  /* only $v1 */ \
   { 0xfdffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },  /* Every other GPR except $25 */   \
   { 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },  /* integer registers */ \
   { 0x00000000, 0xffffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000 },  /* floating registers*/ \

diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi
index c96fd56..66ca3e9 100644 (file)
--- a/gcc/doc/md.texi
+++ b/gcc/doc/md.texi
@@ -2483,6 +2483,10 @@ to store doubleword values.
 A register suitable for use in an indirect jump.  This will always be
 @code{$25} for @option{-mabicalls}.
 
+@item v
+Register @code{$3}.  Do not use this constraint in new code;
+it is retained only for compatibility with glibc.
+
 @item y
 Equivalent to @code{r}; retained for backwards compatibility.