when generating cltd insn.
(*ashl<mode>3_1): Remove special handling for register operand 2.
(*ashlsi3_1_zext): Ditto.
(*ashlhi3_1): Ditto.
(*ashlhi3_1_lea): Ditto.
(*ashlqi3_1): Ditto.
(*ashlqi3_1_lea): Ditto.
(*<shiftrt_insn><mode>3_1): Ditto.
(*<shiftrt_insn>si3_1_zext): Ditto.
(*<shiftrt_insn>qi3_1_slp): Ditto.
(*<rotate_insn><mode>3_1): Ditto.
(*<rotate_insn>si3_1_zext): Ditto.
(*<rotate_insn>qi3_1_slp): Ditto.
git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/trunk@158261
138bc75d-0d04-0410-961f-
82ee72b054a4
+2010-04-13 Uros Bizjak <ubizjak@gmail.com>
+
+ * config/i386/i386.md (extendsidi2 splitter): Also check for DX_REG
+ when generating cltd insn.
+
+ (*ashl<mode>3_1): Remove special handling for register operand 2.
+ (*ashlsi3_1_zext): Ditto.
+ (*ashlhi3_1): Ditto.
+ (*ashlhi3_1_lea): Ditto.
+ (*ashlqi3_1): Ditto.
+ (*ashlqi3_1_lea): Ditto.
+ (*<shiftrt_insn><mode>3_1): Ditto.
+ (*<shiftrt_insn>si3_1_zext): Ditto.
+ (*<shiftrt_insn>qi3_1_slp): Ditto.
+ (*<rotate_insn><mode>3_1): Ditto.
+ (*<rotate_insn>si3_1_zext): Ditto.
+ (*<rotate_insn>qi3_1_slp): Ditto.
+
2010-04-13 Richard Guenther <rguenther@suse.de>
* tree-ssa-structalias.c (callused_id): Remove.
2010-04-13 Richard Guenther <rguenther@suse.de>
* tree-ssa-structalias.c (callused_id): Remove.
plugin name.
(default_plugin_dir_name): Added new function.
plugin name.
(default_plugin_dir_name): Added new function.
- * common.opt (iplugindir): New option to set the plugin
- directory.
+ * common.opt (iplugindir): New option to set the plugin directory.
2010-04-12 Uros Bizjak <ubizjak@gmail.com>
2010-04-12 Uros Bizjak <ubizjak@gmail.com>
gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "add{<imodesuffix>}\t%0, %0";
gcc_assert (rtx_equal_p (operands[0], operands[1]));
return "add{<imodesuffix>}\t%0, %0";
- case TYPE_LEA:
- return "#";
-
- if (REG_P (operands[2]))
- return "sal{<imodesuffix>}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{<imodesuffix>}\t%0";
else
return "sal{<imodesuffix>}\t{%2, %0|%0, %2}";
return "sal{<imodesuffix>}\t%0";
else
return "sal{<imodesuffix>}\t{%2, %0|%0, %2}";
gcc_assert (operands[2] == const1_rtx);
return "add{l}\t%k0, %k0";
gcc_assert (operands[2] == const1_rtx);
return "add{l}\t%k0, %k0";
- case TYPE_LEA:
- return "#";
-
- if (REG_P (operands[2]))
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{l}\t%k0";
else
return "sal{l}\t{%2, %k0|%k0, %2}";
return "sal{l}\t%k0";
else
return "sal{l}\t{%2, %k0|%k0, %2}";
return "add{w}\t%0, %0";
default:
return "add{w}\t%0, %0";
default:
- if (REG_P (operands[2]))
- return "sal{w}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
{
case TYPE_LEA:
return "#";
{
case TYPE_LEA:
return "#";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{w}\t%0, %0";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
return "add{w}\t%0, %0";
return "add{w}\t%0, %0";
default:
return "add{w}\t%0, %0";
default:
- if (REG_P (operands[2]))
- return "sal{w}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
return "sal{w}\t%0";
else
return "sal{w}\t{%2, %0|%0, %2}";
return "add{b}\t%0, %0";
default:
return "add{b}\t%0, %0";
default:
- if (REG_P (operands[2]))
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else
- return "sal{b}\t{%b2, %0|%0, %b2}";
- }
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
{
if (get_attr_mode (insn) == MODE_SI)
{
if (get_attr_mode (insn) == MODE_SI)
else
return "sal{b}\t%0";
}
else
return "sal{b}\t%0";
}
{
case TYPE_LEA:
return "#";
{
case TYPE_LEA:
return "#";
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
case TYPE_ALU:
gcc_assert (operands[2] == const1_rtx);
if (REG_P (operands[1]) && !ANY_QI_REG_P (operands[1]))
return "add{b}\t%0, %0";
default:
return "add{b}\t%0, %0";
default:
- if (REG_P (operands[2]))
- {
- if (get_attr_mode (insn) == MODE_SI)
- return "sal{l}\t{%b2, %k0|%k0, %b2}";
- else
- return "sal{b}\t{%b2, %0|%0, %b2}";
- }
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
{
if (get_attr_mode (insn) == MODE_SI)
{
if (get_attr_mode (insn) == MODE_SI)
else
return "sal{b}\t%0";
}
else
return "sal{b}\t%0";
}
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
- if (REG_P (operands[2]))
- return "<shiftrt>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<shiftrt>{<imodesuffix>}\t%0";
else
return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
return "<shiftrt>{<imodesuffix>}\t%0";
else
return "<shiftrt>{<imodesuffix>}\t{%2, %0|%0, %2}";
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
- if (REG_P (operands[2]))
- return "<shiftrt>{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<shiftrt>{l}\t%k0";
else
return "<shiftrt>{l}\t{%2, %k0|%k0, %2}";
return "<shiftrt>{l}\t%k0";
else
return "<shiftrt>{l}\t{%2, %k0|%k0, %2}";
|| (operands[1] == const1_rtx
&& TARGET_SHIFT1))"
{
|| (operands[1] == const1_rtx
&& TARGET_SHIFT1))"
{
- if (REG_P (operands[1]))
- return "<shiftrt>{b}\t{%b1, %0|%0, %b1}";
- else if (operands[1] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[1] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<shiftrt>{b}\t%0";
else
return "<shiftrt>{b}\t{%1, %0|%0, %1}";
return "<shiftrt>{b}\t%0";
else
return "<shiftrt>{b}\t{%1, %0|%0, %1}";
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
(clobber (reg:CC FLAGS_REG))]
"ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
{
- if (REG_P (operands[2]))
- return "<rotate>{<imodesuffix>}\t{%b2, %0|%0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<rotate>{<imodesuffix>}\t%0";
else
return "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
return "<rotate>{<imodesuffix>}\t%0";
else
return "<rotate>{<imodesuffix>}\t{%2, %0|%0, %2}";
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
(clobber (reg:CC FLAGS_REG))]
"TARGET_64BIT && ix86_binary_operator_ok (<CODE>, SImode, operands)"
{
- if (REG_P (operands[2]))
- return "<rotate>{l}\t{%b2, %k0|%k0, %b2}";
- else if (operands[2] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[2] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<rotate>{l}\t%k0";
else
return "<rotate>{l}\t{%2, %k0|%k0, %2}";
return "<rotate>{l}\t%k0";
else
return "<rotate>{l}\t{%2, %k0|%k0, %2}";
|| (operands[1] == const1_rtx
&& TARGET_SHIFT1))"
{
|| (operands[1] == const1_rtx
&& TARGET_SHIFT1))"
{
- if (REG_P (operands[1]))
- return "<rotate>{b}\t{%b1, %0|%0, %b1}";
- else if (operands[1] == const1_rtx
- && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
+ if (operands[1] == const1_rtx
+ && (TARGET_SHIFT1 || optimize_function_for_size_p (cfun)))
return "<rotate>{b}\t%0";
else
return "<rotate>{b}\t{%1, %0|%0, %1}";
return "<rotate>{b}\t%0";
else
return "<rotate>{b}\t{%1, %0|%0, %1}";