#include "tree.h"
#include "c-tree.h"
#include "expr.h"
-#include "hard-reg-set.h"
#include "flags.h"
extern char *version_string;
extern int flag_traditional;
extern FILE *asm_out_file;
-static char out_sccs_id[] = "@(#)m88k.c 2.1.2.2 27 Mar 1992 08:37:28";
+static char out_sccs_id[] = "@(#)m88k.c 2.1.3.1 07 Apr 1992 17:23:59";
static char tm_sccs_id [] = TM_SCCS_ID;
char *m88k_pound_sign = ""; /* Either # for SVR4 or empty for SVR3 */
/* Output an ascii string. */
void
-output_ascii (file, p, size)
+output_ascii (file, opcode, max, p, size)
FILE *file;
+ char *opcode;
+ int max;
unsigned char *p;
int size;
{
register int num = 0;
- fprintf (file, "\t%s\t \"", ASCII_DATA_ASM_OP);
+ fprintf (file, "\t%s\t \"", opcode);
for (i = 0; i < size; i++)
{
register int c = p[i];
- if (num > 48)
+ if (num > max)
{
- fprintf (file, "\"\n\t%s\t \"", ASCII_DATA_ASM_OP);
+ fprintf (file, "\"\n\t%s\t \"", opcode);
num = 0;
}
after three digits, so this is the only way we
can get it to parse the data properly. */
if (i < size - 1 && p[i + 1] >= '0' && p[i + 1] <= '9')
- num = 32767; /* next pass will start a new string */
+ num = max + 1; /* next pass will start a new string */
}
}
fprintf (file, "\"\n");
| [previous frame pointer (r30)] |
|==============================================| <- fp
| [preserved registers (r25..r14)] |
+ |----------------------------------------------|
+ | [preserved registers (x29..x22)] |
|==============================================|
| [dynamically allocated space (alloca)] |
|==============================================|
static void output_tdesc ();
static int nregs;
+static int nxregs;
static char save_regs[FIRST_PSEUDO_REGISTER];
static int frame_laid_out;
static int frame_size;
#define FIRST_OCS_PRESERVE_REGISTER 14
#define LAST_OCS_PRESERVE_REGISTER 30
+#define FIRST_OCS_EXTENDED_PRESERVE_REGISTER (32 + 22)
+#define LAST_OCS_EXTENDED_PRESERVE_REGISTER (32 + 31)
+
#define STACK_UNIT_BOUNDARY (STACK_BOUNDARY / BITS_PER_UNIT)
#define ROUND_CALL_BLOCK_SIZE(BYTES) \
(((BYTES) + (STACK_UNIT_BOUNDARY - 1)) & ~(STACK_UNIT_BOUNDARY - 1))
frame_laid_out++;
bzero ((char *) &save_regs[0], sizeof (save_regs));
- sp_size = nregs = 0;
+ sp_size = nregs = nxregs = 0;
frame_size = get_frame_size ();
/* Since profiling requires a call, make sure r1 is saved. */
if (frame_pointer_needed)
save_regs[FRAME_POINTER_REGNUM] = save_regs[1] = 1;
+ /* Figure out which extended register(s) needs to be saved. */
+ for (regno = FIRST_EXTENDED_REGISTER + 1; regno < FIRST_PSEUDO_REGISTER;
+ regno++)
+ if (regs_ever_live[regno] && ! call_used_regs[regno])
+ {
+ save_regs[regno] = 1;
+ nxregs++;
+ }
+
/* Figure out which normal register(s) needs to be saved. */
for (regno = 2; regno < FRAME_POINTER_REGNUM; regno++)
if (regs_ever_live[regno] && ! call_used_regs[regno])
sp_size += 4;
nregs += save_regs[1] + save_regs[FRAME_POINTER_REGNUM];
+ /* if we need to align extended registers, add a word */
+ if (nxregs > 0 && (nregs & 1) != 0)
+ sp_size +=4;
sp_size += 4 * nregs;
+ sp_size += 8 * nxregs;
sp_size += current_function_outgoing_args_size;
/* The first two saved registers are placed above the new frame pointer
m88k_layout_frame ();
return (! frame_pointer_needed
&& nregs == 0
+ && nxregs == 0
&& m88k_stack_size == 0);
}
if (m88k_stack_size)
output_reg_adjust (stream, 31, 31, -m88k_stack_size, 0);
- if (nregs)
+ if (nregs || nxregs)
preserve_registers (stream, m88k_fp_offset + 4, 1);
if (frame_pointer_needed)
if (frame_pointer_needed)
output_reg_adjust (stream, 31, 30, -m88k_fp_offset, 0);
- if (nregs)
+ if (nregs || nxregs)
preserve_registers (stream, m88k_fp_offset + 4, 0);
output_reg_adjust (stream, 31, 31, m88k_stack_size, 1);
offset -= 2*4;
}
}
+
+ /* Walk the extended registers to record all memory operations. */
+ /* Be sure the offset is double word aligned. */
+ offset = (offset - 1) & ~7;
+ for (regno = FIRST_PSEUDO_REGISTER - 1; regno > FIRST_EXTENDED_REGISTER;
+ regno--)
+ if (save_regs[regno])
+ {
+ mo_ptr->nregs = 2;
+ mo_ptr->regno = regno;
+ mo_ptr->offset = offset;
+ mo_ptr++;
+ offset -= 2*4;
+ }
+
mo_ptr->regno = 0;
/* Output the delay insns interleaved with the memory operations. */
{
if (mo_ptr->nregs)
{
+ int nregs = (mo_ptr->regno < FIRST_EXTENDED_REGISTER
+ ? mo_ptr->nregs : 1);
rtx ok_insns = delay_insns;
int i;
- for (i = 0; i < mo_ptr->nregs; i++)
+ for (i = 0; i < nregs; i++)
epilogue_dead_regs[mo_ptr->regno + i] = 1;
while (ok_insns)
if (! ok_for_epilogue_p (PATTERN (insn)))
{
- for (i = 0; i < mo_ptr->nregs; i++)
+ for (i = 0; i < nregs; i++)
epilogue_dead_regs[mo_ptr->regno + i] = 0;
insn = 0;
break; /* foreach delay insn */
/* Output the 88open OCS proscribed text description information.
The information is:
0 8: zero
- 0 22: info-byte-length (16 bytes)
+ 0 22: info-byte-length (16 or 20 bytes)
0 2: info-alignment (word 2)
- 1 32: info-protocol (version 1)
+ 1 32: info-protocol (version 1 or 2(pic))
2 32: starting-address (inclusive, not counting prologue)
3 32: ending-address (exclusive, not counting epilog)
- 4 8: info-variant (version 1)
+ 4 8: info-variant (version 1 or 3(extended registers))
4 17: register-save-mask (from register 14 to 30)
4 1: zero
4 1: return-address-info-discriminant
4 5: frame-address-register
5 32: frame-address-offset
6 32: return-address-info
- 7 32: register-save-offset */
+ 7 32: register-save-offset
+ 8 16: extended-register-save-mask (x16 - x31)
+ 8 16: extended-register-save-offset (WORDS from register-save-offset) */
static void
output_tdesc (file, offset)
FILE *file;
int offset;
{
- int regno, i;
+ int regno, i, j;
long mask, return_address_info, register_save_offset;
+ long xmask, xregister_save_offset;
char buf[256];
for (mask = 0, i = 0, regno = FIRST_OCS_PRESERVE_REGISTER;
}
}
+ for (xmask = 0, j = 0, regno = FIRST_OCS_EXTENDED_PRESERVE_REGISTER;
+ regno <= LAST_OCS_EXTENDED_PRESERVE_REGISTER;
+ regno++)
+ {
+ xmask <<= 1;
+ if (save_regs[regno])
+ {
+ xmask |= 1;
+ j++;
+ }
+ }
+
if (save_regs[1])
{
- if (nregs > 2 && !save_regs[FRAME_POINTER_REGNUM])
+ if ((nxregs > 0 || nregs > 2) && !save_regs[FRAME_POINTER_REGNUM])
offset -= 4;
return_address_info = - m88k_stack_size + offset;
register_save_offset = return_address_info - i*4;
register_save_offset = - m88k_stack_size + offset + 4 - i*4;
}
+ xregister_save_offset = - (j * 2 + ((register_save_offset >> 2) & 1));
+
tdesc_section ();
- fprintf (file, "\t%s\t %d", INT_ASM_OP, (16 << 2) | 2 /* 8:0,22:16,2:2 */);
- fprintf (file, ",%d", flag_pic ? 2 : 1);
+ fprintf (file, "\t%s\t %d,%d", INT_ASM_OP, /* 8:0,22:(20 or 16),2:2 */
+ (((xmask != 0) ? 20 : 16) << 2) | 2,
+ flag_pic ? 2 : 1);
ASM_GENERATE_INTERNAL_LABEL (buf, OCS_START_PREFIX, m88k_function_number);
fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : "");
ASM_GENERATE_INTERNAL_LABEL (buf, OCS_END_PREFIX, m88k_function_number);
fprintf (file, ",%s%s", buf+1, flag_pic ? "#rel" : "");
- fprintf (file, ",0x%x", /* 8:1,17:0x%.3x,1:0,1:%d,5:%d */
- (1 << (17+1+1+5)) |
- (mask << (1+1+5)) |
- ((!!save_regs[1]) << 5) |
- ((frame_pointer_needed
- ? FRAME_POINTER_REGNUM
- : STACK_POINTER_REGNUM)));
-
- fprintf (file, ",0x%x", (m88k_stack_size
- - (frame_pointer_needed ? m88k_fp_offset : 0)));
- fprintf (file, ",0x%x", return_address_info);
- fprintf (file, ",0x%x\n", register_save_offset);
+ fprintf (file, ",0x%x,0x%x,0x%x,0x%x",
+ /* 8:1,17:0x%.3x,1:0,1:%d,5:%d */
+ (((xmask ? 3 : 1) << (17+1+1+5))
+ | (mask << (1+1+5))
+ | ((!!save_regs[1]) << 5)
+ | (frame_pointer_needed
+ ? FRAME_POINTER_REGNUM
+ : STACK_POINTER_REGNUM)),
+ (m88k_stack_size - (frame_pointer_needed ? m88k_fp_offset : 0)),
+ return_address_info,
+ register_save_offset);
+ if (xmask)
+ fprintf (file, ",0x%x%04x", xmask, (0xffff & xregister_save_offset));
+ fputc ('\n', file);
text_section ();
}
/* Print subsidiary information on the compiler version in use.
Redefined in m88kv4.h, and m88kluna.h. */
#define VERSION_INFO1 "88open OCS/BCS, "
-#define VERSION_INFO2 "01 Apr 1992"
+#define VERSION_INFO2 "07 Apr 1992"
#define VERSION_STRING version_string
-#define TM_SCCS_ID "@(#)m88k.h 2.1.2.2 01 Apr 1992 06:40:42"
+#define TM_SCCS_ID "@(#)m88k.h 2.1.3.1 07 Apr 1992 17:24:45"
/* Run-time compilation parameters selecting different hardware subsets. */
All registers that the compiler knows about must be given numbers,
even those that are not normally considered general registers.
- The m88100 has 32 fullword registers.
-
- The pseudo argument pointer is said to be register 0. This prohibits
- the use of r0 as a general register and causes no trouble.
- Using register 0 is useful, in that it keeps the number of
- registers down to 32, and GNU can use a long as a bitmask
- for the registers. */
-#define FIRST_PSEUDO_REGISTER 32
-
-/* 1 for registers that have pervasive standard uses
- and are not available for the register allocator.
- Registers 14-25 are expected to be preserved across
- function calls.
-
- On the 88000, these are:
+ The m88100 has a General Register File (GRF) of 32 32-bit registers.
+ The m88110 adds an Extended Register File (XRF) of 32 80-bit registers. */
+#define FIRST_PSEUDO_REGISTER 64
+#define FIRST_EXTENDED_REGISTER 32
+
+/* General notes on extended registers, their use and misuse.
+
+ Possible good uses:
+
+ spill area instead of memory.
+ -waste if only used once
+
+ floating point caluclations
+ -probably a waste unless we have run out of general purpose registers
+
+ freeing up general purpose registers
+ -e.g. may be able to have more loop invariants if floating
+ point is moved into extended registers.
+
+
+ I've noticed wasteful moves into and out of extended registers; e.g. a load
+ into x21, then inside a loop a move into r24, then r24 used as input to
+ an fadd. Why not just load into r24 to begin with? Maybe the new cse.c
+ will address this. This wastes a move, but the load,store and move could
+ have been saved had extended registers been used throughout.
+ E.g. in the code following code, if z and xz are placed in extended
+ registers, there is no need to save preserve registers.
+
+ long c=1,d=1,e=1,f=1,g=1,h=1,i=1,j=1,k;
+
+ double z=0,xz=4.5;
+
+ foo(a,b)
+ long a,b;
+ {
+ while (a < b)
+ {
+ k = b + c + d + e + f + g + h + a + i + j++;
+ z += xz;
+ a++;
+ }
+ printf("k= %d; z=%f;\n", k, z);
+ }
+
+ I've found that it is possible to change the constraints (putting * before
+ the 'r' constraints int the fadd.ddd instruction) and get the entire
+ addition and store to go into extended registers. However, this also
+ forces simple addition and return of floating point arguments to a
+ function into extended registers. Not the correct solution.
+
+ Found the following note in local-alloc.c which may explain why I can't
+ get both registers to be in extended registers since two are allocated in
+ local-alloc and one in global-alloc. Doesn't explain (I don't believe)
+ why an extended register is used instead of just using the preserve
+ register.
+
+ from local-alloc.c:
+ We have provision to exempt registers, even when they are contained
+ within the block, that can be tied to others that are not contained in it.
+ This is so that global_alloc could process them both and tie them then.
+ But this is currently disabled since tying in global_alloc is not
+ yet implemented.
+
+ The explaination of why the preserved register is not used is as follows,
+ I believe. The registers are being allocated in order. Tieing is not
+ done so efficiently, so when it comes time to do the first allocation,
+ there are no registers left to use without spilling except extended
+ registers. Then when the next pseudo register needs a hard reg, there
+ are still no registers to be had for free, but this one must be a GRF
+ reg instead of an extended reg, so a preserve register is spilled. Thus
+ the move from extended to GRF is necessitated. I do not believe this can
+ be 'fixed' through the config/*m88k* files.
+
+ gcc seems to sometimes make worse use of register allocation -- not counting
+ moves -- whenever extended registers are present. For example in the
+ whetstone, the simple for loop (slightly modified)
+ for(i = 1; i <= n1; i++)
+ {
+ x1 = (x1 + x2 + x3 - x4) * t;
+ x2 = (x1 + x2 - x3 + x4) * t;
+ x3 = (x1 - x2 + x3 + x4) * t;
+ x4 = (x1 + x2 + x3 + x4) * t;
+ }
+ in general loads the high bits of the addresses of x2-x4 and i into registers
+ outside the loop. Whenever extended registers are used, it loads all of
+ these inside the loop. My conjecture is that since the 88110 has so many
+ registers, and gcc makes no distinction at this point -- just that they are
+ not fixed, that in loop.c it believes it can expect a number of registers
+ to be available. Then it allocates 'too many' in local-alloc which causes
+ problems later. 'Too many' are allocated because a large portion of the
+ registers are extended registers and cannot be used for certain purposes
+ ( e.g. hold the address of a variable). When this loop is compiled on its
+ own, the problem does not occur. I don't know the solution yet, though it
+ is probably in the base sources. Possibly a different way to calculate
+ "threshold". */
+
+/* 1 for registers that have pervasive standard uses and are not available
+ for the register allocator. Registers r14-r25 and x22-x29 are expected
+ to be preserved across function calls.
+
+ On the 88000, the standard uses of the General Register File (GRF) are:
Reg 0 = Pseudo argument pointer (hardware fixed to 0).
Reg 1 = Subroutine return pointer (hardware).
Reg 2-9 = Parameter registers (OCS).
Reg 14-25 = Preserved register set.
Reg 26-29 = Reserved by OCS and ABI.
Reg 30 = Frame pointer (Common use).
- Reg 31 = Stack pointer. */
+ Reg 31 = Stack pointer.
+
+ The following follows the current 88open UCS specification for the
+ Extended Register File (XRF):
+ Reg 32 = x0 Always equal to zero
+ Reg 33-53 = x1-x21 Tempory registers (Caller Save)
+ Reg 54-61 = x22-x29 Preserver registers (Callee Save)
+ Reg 62-63 = x30-x31 Reserved for future ABI use.
+
+ Note: The current 88110 extended register mapping is subject to change.
+ The bias towards caller-save registers is based on the
+ presumption that memory traffic can potentially be reduced by
+ allowing the "caller" to save only that part of the register
+ which is actually being used. (i.e. don't do a st.x if a st.d
+ is sufficient). Also, in scientific code (a.k.a. Fortran), the
+ large number of variables defined in common blocks may require
+ that almost all registers be saved across calls anyway. */
#define FIXED_REGISTERS \
{1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1}
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
+ 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
/* 1 for registers not available across function calls.
These must include the FIXED_REGISTERS and also any
#define CALL_USED_REGISTERS \
{1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \
- 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1}
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, \
+ 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1}
/* Macro to conditionally modify fixed_regs/call_used_regs. */
#define CONDITIONAL_REGISTER_USAGE \
{ \
+ if (! TARGET_88110) \
+ { \
+ register int i; \
+ for (i = FIRST_EXTENDED_REGISTER; i < FIRST_PSEUDO_REGISTER; i++) \
+ { \
+ fixed_regs[i] = 1; \
+ call_used_regs[i] = 1; \
+ } \
+ } \
if (flag_pic) \
- fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
+ { \
+ /* Current hack to deal with -fpic -O2 problems. */ \
+ fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
+ call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
+ global_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \
+ } \
}
/* These interfaces that don't apply to the m88000. */
This is ordinarily the length in words of a value of mode MODE
but can be less for certain modes in special long registers.
- On the m88000, ordinary registers hold 32 bits worth;
- a single floating point register is always enough for
- anything that can be stored in them at all. */
-#define HARD_REGNO_NREGS(REGNO, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+ On the m88000, GRF registers hold 32-bits and XRF registers hold 80-bits.
+ An XRF register can hold any mode, but two GRF registers are required
+ for larger modes. */
+#define HARD_REGNO_NREGS(REGNO, MODE) \
+ ((REGNO < FIRST_PSEUDO_REGISTER && REGNO >= FIRST_EXTENDED_REGISTER) \
+ ? 1 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.
For double integers, we never put the value into an odd register so that
the operators don't run into the situation where the high part of one of
- the inputs is the low part of the result register (it's ok if the output
- registers are the same as the input registers. */
-#define HARD_REGNO_MODE_OK(REGNO, MODE) \
- (((MODE) != DImode && (MODE) != DFmode && (MODE) != DCmode) || \
- ((REGNO) & 1) == 0)
+ the inputs is the low part of the result register. (It's ok if the output
+ registers are the same as the input registers.) The XRF registers can
+ hold all modes, but only DF and SF modes can be manipulated in these
+ registers. The compiler should be allowed to use these as a fast spill
+ area. */
+#define HARD_REGNO_MODE_OK(REGNO, MODE) \
+ ((REGNO < FIRST_PSEUDO_REGISTER && REGNO >= FIRST_EXTENDED_REGISTER) \
+ ? TARGET_88110 \
+ : (((MODE) != DImode && (MODE) != DFmode && (MODE) != DCmode) \
+ || ((REGNO) & 1) == 0))
/* Value is 1 if it is a good idea to tie two pseudo registers
when one has mode MODE1 and one has mode MODE2.
/* Order in which registers are preferred (most to least). Use temp
registers, then param registers top down. Preserve registers are
top down to maximize use of double memory ops for register save.
- The 88open reserved registers (26-29) may commonly be used in most
- environments with the -fcall-used- or -fcall-saved- options. */
-#define REG_ALLOC_ORDER \
- {13, 12, 11, 10, 29, 28, 27, 26, \
- 1, 9, 8, 7, 6, 5, 4, 3, \
- 2, 25, 24, 23, 22, 21, 20, 19, \
- 18, 17, 16, 15, 14, 30, 31, 0}
+ The 88open reserved registers (r26-r29 and x30-x31) may commonly be used
+ in most environments with the -fcall-used- or -fcall-saved- options. */
+#define REG_ALLOC_ORDER \
+ { \
+ 13, 12, 11, 10, 29, 28, 27, 26, \
+ 1, 62, 63, 9, 8, 7, 6, 5, \
+ 4, 3, 2, 53, 52, 51, 50, 49, \
+ 48, 47, 46, 45, 44, 43, 42, 41, \
+ 40, 39, 38, 37, 36, 35, 34, 33, \
+ 25, 24, 23, 22, 21, 20, 19, 18, \
+ 17, 16, 15, 14, 61, 60, 59, 58, \
+ 57, 56, 55, 54, 30, 31, 0, 32}
\f
/*** Register Classes ***/
For any two classes, it is very desirable that there be another
class that represents their union. */
-/* The m88100 hardware has one kind of register. However, we denote
+/* The m88000 hardware has two kinds of registers. In addition, we denote
the arg pointer as a separate class. */
-enum reg_class { NO_REGS, AP_REG, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES };
+enum reg_class { NO_REGS, AP_REG, XRF_REGS, GENERAL_REGS, AGRF_REGS,
+ XGRF_REGS, ALL_REGS, LIM_REG_CLASSES };
#define N_REG_CLASSES (int) LIM_REG_CLASSES
/* Give names of register classes as strings for dump file. */
-#define REG_CLASS_NAMES {"NO_REGS", "AP_REG", "GENERAL_REGS", "ALL_REGS" }
+#define REG_CLASS_NAMES {"NO_REGS", "AP_REG", "XRF_REGS", "GENERAL_REGS", \
+ "AGRF_REGS", "XGRF_REGS", "ALL_REGS" }
/* Define which registers fit in which classes.
This is an initializer for a vector of HARD_REG_SET
of length N_REG_CLASSES. */
-#define REG_CLASS_CONTENTS {0, 1, -2, -1}
+#define REG_CLASS_CONTENTS {{0x00000000, 0x00000000}, \
+ {0x00000001, 0x00000000}, \
+ {0x00000000, 0xffffffff}, \
+ {0xfffffffe, 0x00000000}, \
+ {0xffffffff, 0x00000000}, \
+ {0xfffffffe, 0xffffffff}, \
+ {0xffffffff, 0xffffffff}}
/* The same information, inverted:
Return the class number of the smallest class containing
reg number REGNO. This could be a conditional expression
or could index an array. */
-#define REGNO_REG_CLASS(REGNO) ((REGNO) ? GENERAL_REGS : AP_REG)
+#define REGNO_REG_CLASS(REGNO) \
+ ((REGNO) ? ((REGNO < 32) ? GENERAL_REGS : XRF_REGS) : AP_REG)
/* The class value for index registers, and the one for base regs. */
-#define BASE_REG_CLASS ALL_REGS
+#define BASE_REG_CLASS AGRF_REGS
#define INDEX_REG_CLASS GENERAL_REGS
-/* Get reg_class from a letter such as appears in the machine description. */
-
-#define REG_CLASS_FROM_LETTER(C) NO_REGS
+/* Get reg_class from a letter such as appears in the machine description.
+ For the 88000, the following class/letter is defined for the XRF:
+ x - Extended register file */
+#define REG_CLASS_FROM_LETTER(C) \
+ (((C) == 'x') ? XRF_REGS : NO_REGS)
/* Macros to check register numbers against specific register classes.
These assume that REGNO is a hard or pseudo reg number.
or a pseudo reg currently allocated to a suitable hard reg.
Since they use reg_renumber, they are safe only once reg_renumber
has been allocated, which happens in local-alloc.c. */
-#define REGNO_OK_FOR_BASE_P(REGNO) \
- ((REGNO) < FIRST_PSEUDO_REGISTER || \
- (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER)
-#define REGNO_OK_FOR_INDEX_P(REGNO) \
- (((REGNO) && (REGNO) < FIRST_PSEUDO_REGISTER) || \
- (unsigned) reg_renumber[REGNO] < FIRST_PSEUDO_REGISTER)
+#define REGNO_OK_FOR_BASE_P(REGNO) \
+ ((REGNO) < FIRST_EXTENDED_REGISTER \
+ || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER)
+#define REGNO_OK_FOR_INDEX_P(REGNO) \
+ (((REGNO) && (REGNO) < FIRST_EXTENDED_REGISTER) \
+ || (unsigned) reg_renumber[REGNO] < FIRST_EXTENDED_REGISTER)
/* Given an rtx X being reloaded into a reg required to be
in class CLASS, return the class of reg to actually use.
In general this is just CLASS; but on some machines
in some cases it is preferable to use a more restrictive class.
Double constants should be in a register iff they can be made cheaply. */
-#define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS)
+#define PREFERRED_RELOAD_CLASS(X,CLASS) \
+ (CONSTANT_P(X) && (CLASS == XRF_REGS) ? NO_REGS : (CLASS))
/* Return the maximum number of consecutive registers
needed to represent mode MODE in a register of class CLASS. */
-#define CLASS_MAX_NREGS(CLASS, MODE) \
- ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)
+#define CLASS_MAX_NREGS(CLASS, MODE) \
+ ((((CLASS) == XRF_REGS) ? 1 \
+ : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))
/* Letters in the range `I' through `P' in a register constraint string can
be used to stand for particular ranges of immediate operands. The C
/* These are specific to version 03.00 assembler syntax. */
#define INTERNAL_ASM_OP "local"
#define VERSION_ASM_OP "version"
-#define ASM_DWARF_POP_SECTION(FILE) fputs ("\tprevious\n", FILE)
#define UNALIGNED_SHORT_ASM_OP "uahalf"
#define UNALIGNED_INT_ASM_OP "uaword"
+#define PUSHSECTION_ASM_OP "section"
+#define POPSECTION_ASM_OP "previous"
/* Output any initial stuff to the assembly file. Always put out
a file directive, even if not debugging.
#define ASM_OUTPUT_IDENT(FILE, NAME)
#else
#define ASM_OUTPUT_IDENT(FILE, NAME) \
- fprintf (FILE, "\t%s\t \"%s\"\n", IDENT_ASM_OP, NAME)
+ output_ascii (FILE, IDENT_ASM_OP, 4000, NAME, strlen (NAME));
#endif
/* Output to assembler file text saying following lines
{"#r0"+1, "#r1"+1, "#r2"+1, "#r3"+1, "#r4"+1, "#r5"+1, "#r6"+1, "#r7"+1, \
"#r8"+1, "#r9"+1, "#r10"+1,"#r11"+1,"#r12"+1,"#r13"+1,"#r14"+1,"#r15"+1,\
"#r16"+1,"#r17"+1,"#r18"+1,"#r19"+1,"#r20"+1,"#r21"+1,"#r22"+1,"#r23"+1,\
- "#r24"+1,"#r25"+1,"#r26"+1,"#r27"+1,"#r28"+1,"#r29"+1,"#r30"+1,"#r31"+1}
+ "#r24"+1,"#r25"+1,"#r26"+1,"#r27"+1,"#r28"+1,"#r29"+1,"#r30"+1,"#r31"+1,\
+ "#x0"+1, "#x1"+1, "#x2"+1, "#x3"+1, "#x4"+1, "#x5"+1, "#x6"+1, "#x7"+1, \
+ "#x8"+1, "#x9"+1, "#x10"+1,"#x11"+1,"#x12"+1,"#x13"+1,"#x14"+1,"#x15"+1,\
+ "#x16"+1,"#x17"+1,"#x18"+1,"#x19"+1,"#x20"+1,"#x21"+1,"#x22"+1,"#x23"+1,\
+ "#x24"+1,"#x25"+1,"#x26"+1,"#x27"+1,"#x28"+1,"#x29"+1,"#x30"+1,"#x31"+1}
/* How to renumber registers for dbx and gdb. */
#define DBX_REGISTER_NUMBER(REGNO) (REGNO)
#define ASM_BYTE_OP "\tbyte"
#undef ASM_OUTPUT_ASCII
#define ASM_OUTPUT_ASCII(FILE, P, SIZE) \
- output_ascii ((FILE), (P), (SIZE))
+ output_ascii (FILE, ASCII_DATA_ASM_OP, 48, P, SIZE)
/* Epilogue for case labels. This jump instruction is called by casesi
to transfer to the appropriate branch instruction within the table.
(define_expand "m88k_sccs_id"
[(match_operand:SI 0 "" "")]
""
- "{ static char sccs_id[] = \"@(#)m88k.md 2.0.3.4 20 Mar 1992 15:09:03\";
+ "{ static char sccs_id[] = \"@(#)m88k.md 2.1.3.1 07 Apr 1992 17:25:37\";
FAIL; }")
\f
;; Attribute specifications
;
; "branch,jump,call, ; flow-control instructions
; load,store,loada, ; data unit instructions
-; spadd,dpadd,spdiv,dpdiv,idiv, ; FPU add instructions
+; spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv, ; FPU add instructions
; spmul,dpmul,imul, ; FPU multiply instructions
-; arith, ; integer unit instructions
-; marith,mstore,mfp,weird" ; multi-word instructions
+; arith,bit,mov ; integer unit instructions
+; marith,mbit,mstore,mfp,weird" ; multi-word instructions
; Classification of each insn. Some insns of TYPE_BRANCH are multi-word.
(define_attr "type"
- "branch,jump,call,load,store,loada,spadd,dpadd,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,marith,mstore,mfp,weird"
+ "branch,jump,call,load,store,loada,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,spmul,dpmul,imul,arith,bit,mov,marith,mbit,mstore,mfp,weird"
(const_string "arith"))
; Convenience attributes.
(define_attr "fpu" "yes,no"
(if_then_else
- (eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spdiv,dpdiv,idiv,mfp")
+ (eq_attr "type" "spmul,dpmul,imul,spadd,dpadd,spcmp,dpcmp,spdiv,dpdiv,idiv,mfp")
(const_string "yes") (const_string "no")))
; Length in # of instructions of each insn. The values are not exact, but
; are safe.
(define_attr "length" ""
- (cond [(eq_attr "type" "marith,mstore,mfp")
+ (cond [(eq_attr "type" "marith,mbit,mstore,mfp")
(const_int 2)]
(const_int 1)))
(define_delay (eq_attr "type" "branch,jump")
[(and
(and
- (eq_attr "type" "!branch,jump,call,marith,mstore,mfp,weird") ; required.
+ (eq_attr "type" "!branch,jump,call,marith,mbit,mstore,mfp,weird") ; required.
(eq_attr "type" "!load")) ; issue as-soon-as-possible.
(eq_attr "fpu" "no")) ; issue as-soon-as-possible.
(eq_attr "type" "!call,branch,jump") (nil)]) ; @@ was (const_int 1)
; a call. (@@ Support for this case is expected in reorg.c soon.)
(define_delay (eq_attr "type" "call")
- [(eq_attr "type" "!branch,call,marith,mstore,mfp,weird") ; required.
+ [(eq_attr "type" "!branch,call,marith,mbit,mstore,mfp,weird") ; required.
(nil) (nil)])
\f
; An abstract block diagram of the function units for the m88100.
; Describing the alu is currently not useful.
;(define_function_unit "alu" 1 0 (eq_attr "type"
-; "!store,mstore,marith,mfp,weird") 1 0)
-;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,weird") 2 0)
+; "!store,mstore,marith,mbit,mfp,weird") 1 0)
+;(define_function_unit "alu" 1 0 (eq_attr "type" "marith,mbit,weird") 2 0)
-(define_function_unit "memory" 1 3 (eq_attr "type" "load") 3 2)
+(define_function_unit "memory" 1 3
+ (and (eq_attr "type" "load") (eq_attr "cpu" "m88100")) 3 2)
+(define_function_unit "memory" 1 3
+ (and (eq_attr "type" "load") (eq_attr "cpu" "!m88100")) 2 2)
; The fp1 and fplast descriptions currently have no effect.
;(define_function_unit "fp1" 1 1 (eq_attr "fpu" "yes") 1 2)
; adjusted based on the actual generated code. The notation to the right
; is the total latency. A range denotes a group of instructions and/or
; conditions (the extra clock of fplast time with some sequences).
-(define_function_unit "fpmul" 1 4 (eq_attr "type" "spmul") 4 2) ; 6-8
-(define_function_unit "fpmul" 1 4 (eq_attr "type" "dpmul,mfp") 7 2) ; 9-10
-(define_function_unit "fpmul" 1 4 (eq_attr "type" "imul") 3 2) ; 4
-
-(define_function_unit "fpadd" 1 3 (eq_attr "type" "spadd") 3 2) ; 5-6
-(define_function_unit "fpadd" 1 3 (eq_attr "type" "dpadd") 4 2) ; 6-7
-(define_function_unit "fpadd" 1 3 (eq_attr "type" "spdiv") 30 2) ; 30-31
-(define_function_unit "fpadd" 1 3 (eq_attr "type" "dpdiv") 60 2) ; 60-61
-(define_function_unit "fpadd" 1 3 (eq_attr "type" "idiv") 38 2) ; 38
+(define_function_unit "fpmul" 1 4
+ (and (eq_attr "type" "spmul") (eq_attr "cpu" "m88100")) 4 2) ; 6-8
+(define_function_unit "fpmul" 1 4
+ (and (eq_attr "type" "dpmul,mfp") (eq_attr "cpu" "m88100")) 7 2) ; 9-10
+(define_function_unit "fpmul" 1 4
+ (and (eq_attr "type" "imul") (eq_attr "cpu" "m88100")) 3 2) ; 4
+
+(define_function_unit "fpmul" 1 4
+ (and (eq_attr "type" "imul,spmul,dpmul,mfp")
+ (eq_attr "cpu" "!m88100")) 3 2) ; 3
+
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "spadd,spcmp") (eq_attr "cpu" "m88100")) 3 2) ; 5-6
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "dpadd,dpcmp") (eq_attr "cpu" "m88100")) 4 2) ; 6-7
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "spdiv") (eq_attr "cpu" "m88100")) 30 2) ; 30-31
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "m88100")) 60 2) ; 60-61
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "m88100")) 38 2) ; 38
+
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "spadd,dpadd") (eq_attr "cpu" "!m88100")) 3 2) ; 3
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "spcmp,dpcmp") (eq_attr "cpu" "!m88100")) 1 2) ; 3
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "spdiv") (eq_attr "cpu" "!m88100")) 13 2) ; 13
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "dpdiv") (eq_attr "cpu" "!m88100")) 23 2) ; 23
+(define_function_unit "fpadd" 1 3
+ (and (eq_attr "type" "idiv") (eq_attr "cpu" "!m88100")) 18 2) ; 18
;(define_function_unit "fplast" 1 1 (eq_attr "fpu" "yes") 1 2)
operands[4] = gen_rtx (CONST_INT, SImode,
INTVAL (operands[3]) - INTVAL (operands[2]));
return \"ext %0,%1,%w3<%4>\"; /* <(%3-%2)> */
-}")
+}"
+ [(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
operands[4] = gen_rtx (CONST_INT, SImode,
INTVAL (operands[3]) - INTVAL (operands[2]));
return \"extu %0,%1,%w3<%4>\"; /* <(%3-%2)> */
-}")
+}"
+ [(set_attr "type" "bit")])
;; Optimize possible cases of the set instruction.
(ashift:SI (const_int -1)
(match_operand:SI 1 "register_operand" "r")))]
""
- "set %0,%#r0,%1")
+ "set %0,%#r0,%1"
+ [(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(match_operand:SI 1 "register_operand" "r"))
(match_operand:SI 2 "register_operand" "r")))]
""
- "set %0,%2,%1")
+ "set %0,%2,%1"
+ [(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
(ashift:SI (const_int -1)
(match_operand:SI 2 "register_operand" "r"))))]
""
- "set %0,%1,%2")
+ "set %0,%1,%2"
+ [(set_attr "type" "bit")])
;; Optimize possible cases of the mak instruction.
exact_log2 (1 + (INTVAL (operands[3])
>> INTVAL(operands[2]))));
return \"mak %0,%1,%4<%2>\";
-}")
+}"
+ [(set_attr "type" "bit")])
;; Optimize possible cases of output_and.
((1 << INTVAL (operands[2])) - 1) << INTVAL (operands[4]));
return output_and (operands);
}"
- [(set_attr "type" "marith")]) ; length is 1 or 2.
+ [(set_attr "type" "marith")]) ; arith,bit,marith. length is 1 or 2.
\f
;; Recognize bcnd instructions for integer values. This is distinguished
;; from a conditional branch instruction (below) with SImode instead of
"cmp %0,%r1,%2")
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r,r")
- (compare:CC (match_operand:SF 1 "register_operand" "r,r")
- (match_operand:SF 2 "real_or_0_operand" "r,G")))]
+ [(set (match_operand:CC 0 "register_operand" "=r,r,r,r")
+ (compare:CC (match_operand:SF 1 "register_operand" "r,r,x,x")
+ (match_operand:SF 2 "real_or_0_operand" "r,G,x,G")))]
""
"@
fcmp.sss %0,%1,%2
- fcmp.sss %0,%1,%#r0"
- [(set_attr "type" "spadd")])
+ fcmp.sss %0,%1,%#r0
+ fcmp.sss %0,%1,%2
+ fcmp.sss %0,%1,%#x0"
+ [(set_attr "type" "spcmp")])
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
- (compare:CC (match_operand:DF 1 "register_operand" "r")
+ [(set (match_operand:CC 0 "register_operand" "=r,r")
+ (compare:CC (match_operand:DF 1 "register_operand" "r,x")
(float_extend:DF
- (match_operand:SF 2 "register_operand" "r"))))]
+ (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fcmp.sds %0,%1,%2"
- [(set_attr "type" "dpadd")])
+ [(set_attr "type" "dpcmp")])
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r")
+ [(set (match_operand:CC 0 "register_operand" "=r,r")
(compare:CC (float_extend:DF
- (match_operand:SF 1 "register_operand" "r"))
- (match_operand:DF 2 "register_operand" "r")))]
+ (match_operand:SF 1 "register_operand" "r,x"))
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fcmp.ssd %0,%1,%2"
- [(set_attr "type" "dpadd")])
+ [(set_attr "type" "dpcmp")])
(define_insn ""
- [(set (match_operand:CC 0 "register_operand" "=r,r")
- (compare:CC (match_operand:DF 1 "register_operand" "r,r")
- (match_operand:DF 2 "real_or_0_operand" "r,G")))]
+ [(set (match_operand:CC 0 "register_operand" "=r,r,r,r")
+ (compare:CC (match_operand:DF 1 "register_operand" "r,r,x,x")
+ (match_operand:DF 2 "real_or_0_operand" "r,G,x,G")))]
""
"@
fcmp.sdd %0,%1,%2
- fcmp.sds %0,%1,%#r0"
- [(set_attr "type" "dpadd")])
+ fcmp.sds %0,%1,%#r0
+ fcmp.sdd %0,%1,%2
+ fcmp.sds %0,%1,%#x0"
+ [(set_attr "type" "dpcmp")])
\f
;; Store condition code insns. The compare insns set a register
;; rather than cc0 and record that register for use here. See above
;; for the special treatment of cmpsi with a constant operand.
+;; @@ For the m88110, use fcmpu for bxx sxx inequality comparisons.
+
(define_expand "seq"
[(set (match_operand:SI 0 "register_operand" "")
(match_dup 1))]
[(match_operand:CC 2 "register_operand" "r")
(const_int 0)]))]
""
- "ext %0,%2,1<%C1>")
+ "ext %0,%2,1<%C1>"
+ [(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
[(match_operand:CC 2 "register_operand" "r")
(const_int 0)])))]
""
- "extu %0,%2,1<%C1>")
+ "extu %0,%2,1<%C1>"
+ [(set_attr "type" "bit")])
\f
;; Conditional branch insns. The compare insns set a register
;; rather than cc0 and record that register for use here. See above
}")
(define_insn ""
- [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r")
- (match_operand:SI 1 "move_operand" "rI,m,rO,J,M"))]
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,m,r,r,r,x,x,x,m")
+ (match_operand:SI 1 "move_operand" "rI,m,rO,J,M,x,r,x,m,x"))]
"(register_operand (operands[0], SImode)
|| register_operand (operands[1], SImode)
|| operands[1] == const0_rtx)"
ld %0,%1
st %r1,%0
subu %0,%#r0,%n1
- set %0,%#r0,%s1"
- [(set_attr "type" "arith,load,store,arith,arith")])
+ set %0,%#r0,%s1
+ mov.s %0,%1
+ mov.s %0,%1
+ mov %0,%1
+ ld %0,%1
+ st %1,%0"
+ [(set_attr "type" "arith,load,store,arith,bit,mov,mov,mov,load,store")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r,r,r,r,r")
or.u %0,%#r0,%X1
set %0,%#r0,%s1
or.u %0,%#r0,%X1\;or %0,%0,%x1"
- [(set_attr "type" "arith,arith,arith,arith,marith")])
+ [(set_attr "type" "arith,arith,arith,bit,marith")])
;; @@ Why the constraint "in"? Doesn't `i' include `n'?
(define_insn ""
}")
(define_insn ""
- [(set (match_operand:DI 0 "register_operand" "=r")
+ [(set (match_operand:DI 0 "register_operand" "=r,x")
(const_int 0))]
""
- "or %0,%#r0,0\;or %d0,%#r0,0"
- [(set_attr "type" "marith")])
+ "@
+ or %0,%#r0,0\;or %d0,%#r0,0
+ mov %0,%#x0"
+ [(set_attr "type" "marith,mov")])
(define_insn ""
- [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m")
- (match_operand:DI 1 "nonimmediate_operand" "r,m,r"))]
+ [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,m,r,x,x,x,m")
+ (match_operand:DI 1 "nonimmediate_operand" "r,m,r,x,r,x,m,x"))]
""
"@
or %0,%#r0,%1\;or %d0,%#r0,%d1
ld.d %0,%1
+ st.d %1,%0
+ mov.d %0,%1
+ mov.d %0,%1
+ mov %0,%1
+ ld.d %0,%1
st.d %1,%0"
- [(set_attr "type" "marith,load,store")])
+ [(set_attr "type" "marith,load,store,mov,mov,mov,load,store")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
;}")
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
(const_int 0))]
""
- "or %0,%#r0,0\;or %d0,%#r0,0"
- [(set_attr "type" "marith")])
+ "@
+ or %0,%#r0,0\;or %d0,%#r0,0
+ mov %0,%#x0"
+ [(set_attr "type" "marith,mov")])
(define_insn ""
- [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m")
- (match_operand:DF 1 "nonimmediate_operand" "r,m,r"))]
+ [(set (match_operand:DF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m")
+ (match_operand:DF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))]
""
"@
or %0,%#r0,%1\;or %d0,%#r0,%d1
ld.d %0,%1
+ st.d %1,%0
+ mov.d %0,%1
+ mov.d %0,%1
+ mov %0,%1
+ ld.d %0,%1
st.d %1,%0"
- [(set_attr "type" "marith,load,store")])
+ [(set_attr "type" "marith,load,store,mov,mov,mov,load,store")])
(define_insn ""
[(set (match_operand:DF 0 "register_operand" "=r")
;; @@ What happens to fconst0_rtx?
(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r")
+ [(set (match_operand:SF 0 "register_operand" "=r,x")
(const_int 0))]
""
- "or %0,%#r0,0")
+ "@
+ or %0,%#r0,0
+ mov %0,%#x0"
+ [(set_attr "type" "arith,mov")])
(define_insn ""
- [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m")
- (match_operand:SF 1 "nonimmediate_operand" "r,m,r"))]
+ [(set (match_operand:SF 0 "nonimmediate_operand" "=r,r,m,x,r,x,x,m")
+ (match_operand:SF 1 "nonimmediate_operand" "r,m,r,r,x,x,m,x"))]
""
"@
or %0,%#r0,%1
ld %0,%1
+ st %r1,%0
+ mov.s %0,%1
+ mov.s %0,%1
+ mov %0,%1
+ ld %0,%1
st %r1,%0"
- [(set_attr "type" "arith,load,store")])
+ [(set_attr "type" "arith,load,store,mov,mov,mov,load,store")])
(define_insn ""
[(set (match_operand:SF 0 "register_operand" "=r")
or %0,%#r0,%h1
subu %0,%#r0,%H1
ld.h %0,%1"
- [(set_attr "type" "arith,arith,arith,load")])
+ [(set_attr "type" "bit,arith,arith,load")])
(define_expand "extendqihi2"
[(set (match_operand:HI 0 "register_operand" "")
or %0,%#r0,%q1
subu %0,%#r0,%Q1
ld.b %0,%1"
- [(set_attr "type" "arith,arith,arith,load")])
+ [(set_attr "type" "bit,arith,arith,load")])
(define_expand "extendqisi2"
[(set (match_operand:SI 0 "register_operand" "")
or %0,%#r0,%q1
subu %0,%#r0,%Q1
ld.b %0,%1"
- [(set_attr "type" "arith,arith,arith,load")])
+ [(set_attr "type" "bit,arith,arith,load")])
\f
;; Conversions between float and double.
;; convert between float and double. In particular, the sign of -0 is
;; not preserved. Interestingly, fsub does conform.
-(define_insn "extendsfdf2"
+(define_expand "extendsfdf2"
[(set (match_operand:DF 0 "register_operand" "=r")
(float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
""
+ "")
+
+(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=r")
+ (float_extend:DF (match_operand:SF 1 "register_operand" "r")))]
+ "! TARGET_88110"
"fsub.dss %0,%1,%#r0"
[(set_attr "type" "spadd")])
-(define_insn "truncdfsf2"
+(define_insn ""
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (float_extend:DF (match_operand:SF 1 "register_operand" "r,x")))]
+ "TARGET_88110"
+ "fcvt.ds %0,%1"
+ [(set_attr "type" "spadd")])
+
+(define_expand "truncdfsf2"
[(set (match_operand:SF 0 "register_operand" "=r")
(float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
""
+ "")
+
+(define_insn ""
+ [(set (match_operand:SF 0 "register_operand" "=r")
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "r")))]
+ "! TARGET_88110"
"fsub.sds %0,%1,%#r0"
[(set_attr "type" "dpadd")])
+(define_insn ""
+ [(set (match_operand:SF 0 "register_operand" "=r,x")
+ (float_truncate:SF (match_operand:DF 1 "register_operand" "r,x")))]
+ "TARGET_88110"
+ "fcvt.sd %0,%1"
+ [(set_attr "type" "dpadd")])
+
;; Conversions between floating point and integer
(define_insn "floatsidf2"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (float:DF (match_operand:SI 1 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (float:DF (match_operand:SI 1 "register_operand" "r,r")))]
""
"flt.ds %0,%1"
- [(set_attr "type" "spadd")])
+ [(set_attr "type" "spadd,dpadd")])
(define_insn "floatsisf2"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (float:SF (match_operand:SI 1 "register_operand" "r")))]
+ [(set (match_operand:SF 0 "register_operand" "=r,x")
+ (float:SF (match_operand:SI 1 "register_operand" "r,r")))]
""
"flt.ss %0,%1"
- [(set_attr "type" "spadd")])
+ [(set_attr "type" "spadd,spadd")])
(define_insn "fix_truncdfsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (fix:SI (match_operand:DF 1 "register_operand" "r")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,x")
+ (fix:SI (match_operand:DF 1 "register_operand" "r,r")))]
""
"trnc.sd %0,%1"
- [(set_attr "type" "dpadd")])
+ [(set_attr "type" "dpadd,dpadd")])
(define_insn "fix_truncsfsi2"
- [(set (match_operand:SI 0 "register_operand" "=r")
- (fix:SI (match_operand:SF 1 "register_operand" "r")))]
+ [(set (match_operand:SI 0 "register_operand" "=r,x")
+ (fix:SI (match_operand:SF 1 "register_operand" "r,r")))]
""
"trnc.ss %0,%1"
- [(set_attr "type" "spadd")])
+ [(set_attr "type" "spadd,dpadd")])
\f
;;- arithmetic instructions
;; requires double rounding, whereas the 88000 instruction only rounds once.
(define_expand "adddf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (plus:DF (match_operand:DF 1 "general_operand" "%r")
- (match_operand:DF 2 "general_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (plus:DF (match_operand:DF 1 "general_operand" "%r,x")
+ (match_operand:DF 2 "general_operand" "r,x")))]
""
"
{
}")
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r"))
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
+ (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fadd.dss %0,%1,%2"
[(set_attr "type" "spadd")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (plus:DF (match_operand:DF 1 "register_operand" "r")
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (plus:DF (match_operand:DF 1 "register_operand" "r,x")
+ (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fadd.dds %0,%1,%2"
[(set_attr "type" "dpadd")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:DF 2 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (plus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fadd.dsd %0,%1,%2"
[(set_attr "type" "dpadd")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (plus:DF (match_operand:DF 1 "register_operand" "%r")
- (match_operand:DF 2 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (plus:DF (match_operand:DF 1 "register_operand" "%r,x")
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fadd.ddd %0,%1,%2"
[(set_attr "type" "dpadd")])
(define_insn "addsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (plus:SF (match_operand:SF 1 "register_operand" "%r")
- (match_operand:SF 2 "register_operand" "r")))]
+ [(set (match_operand:SF 0 "register_operand" "=r,x")
+ (plus:SF (match_operand:SF 1 "register_operand" "%r,x")
+ (match_operand:SF 2 "register_operand" "r,x")))]
""
"fadd.sss %0,%1,%2"
[(set_attr "type" "spadd")])
;; requires double rounding, whereas the 88000 instruction only rounds once.
(define_expand "subdf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (minus:DF (match_operand:DF 1 "general_operand" "r")
- (match_operand:DF 2 "general_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (minus:DF (match_operand:DF 1 "general_operand" "r,x")
+ (match_operand:DF 2 "general_operand" "r,x")))]
""
"
{
}")
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r"))
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
+ (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fsub.dss %0,%1,%2"
[(set_attr "type" "spadd")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (minus:DF (match_operand:DF 1 "register_operand" "r")
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (minus:DF (match_operand:DF 1 "register_operand" "r,x")
+ (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fsub.dds %0,%1,%2"
[(set_attr "type" "dpadd")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:DF 2 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (minus:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fsub.dsd %0,%1,%2"
[(set_attr "type" "dpadd")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (minus:DF (match_operand:DF 1 "register_operand" "r")
- (match_operand:DF 2 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (minus:DF (match_operand:DF 1 "register_operand" "r,x")
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fsub.ddd %0,%1,%2"
[(set_attr "type" "dpadd")])
(define_insn "subsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (minus:SF (match_operand:SF 1 "register_operand" "r")
- (match_operand:SF 2 "register_operand" "r")))]
+ [(set (match_operand:SF 0 "register_operand" "=r,x")
+ (minus:SF (match_operand:SF 1 "register_operand" "r,x")
+ (match_operand:SF 2 "register_operand" "r,x")))]
""
"fsub.sss %0,%1,%2"
[(set_attr "type" "spadd")])
"mul %0,%1,%2"
[(set_attr "type" "imul")])
+;; @@ This isn't fully implemented yet.
+
+(define_insn ""
+ [(set (match_operand:DI 0 "register_operand" "=r")
+ (mult:DI (match_operand:SI 1 "arith32_operand" "%r")
+ (match_operand:SI 2 "arith32_operand" "rI")))]
+ "TARGET_88110"
+ "mulu.d %0,%1,%2"
+ [(set_attr "type" "imul")])
+
;; patterns for mixed mode floating point
;; Do not define patterns that utilize mixed mode arithmetic that result
;; in narrowing the precision, because it loses accuracy, since the standard
;; requires double rounding, whereas the 88000 instruction only rounds once.
(define_expand "muldf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (mult:DF (match_operand:DF 1 "general_operand" "%r")
- (match_operand:DF 2 "general_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (mult:DF (match_operand:DF 1 "general_operand" "%r,x")
+ (match_operand:DF 2 "general_operand" "r,x")))]
""
"
{
}")
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r"))
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
+ (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fmul.dss %0,%1,%2"
[(set_attr "type" "spmul")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (mult:DF (match_operand:DF 1 "register_operand" "r")
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (mult:DF (match_operand:DF 1 "register_operand" "r,x")
+ (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fmul.dds %0,%1,%2"
[(set_attr "type" "spmul")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:DF 2 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (mult:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fmul.dsd %0,%1,%2"
[(set_attr "type" "spmul")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (mult:DF (match_operand:DF 1 "register_operand" "%r")
- (match_operand:DF 2 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (mult:DF (match_operand:DF 1 "register_operand" "%r,x")
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fmul.ddd %0,%1,%2"
[(set_attr "type" "dpmul")])
(define_insn "mulsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (mult:SF (match_operand:SF 1 "register_operand" "%r")
- (match_operand:SF 2 "register_operand" "r")))]
+ [(set (match_operand:SF 0 "register_operand" "=r,x")
+ (mult:SF (match_operand:SF 1 "register_operand" "%r,x")
+ (match_operand:SF 2 "register_operand" "r,x")))]
""
"fmul.sss %0,%1,%2"
[(set_attr "type" "spmul")])
;; requires double rounding, whereas the 88000 instruction only rounds once.
(define_expand "divdf3"
- [(set (match_operand:DF 0 "register_operand" "=r")
- (div:DF (match_operand:DF 1 "general_operand" "r")
- (match_operand:DF 2 "general_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (div:DF (match_operand:DF 1 "general_operand" "r,x")
+ (match_operand:DF 2 "general_operand" "r,x")))]
""
"
{
}")
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r"))
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
+ (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fdiv.dss %0,%1,%2"
[(set_attr "type" "dpdiv")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (div:DF (match_operand:DF 1 "register_operand" "r")
- (float_extend:DF (match_operand:SF 2 "register_operand" "r"))))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (div:DF (match_operand:DF 1 "register_operand" "r,x")
+ (float_extend:DF (match_operand:SF 2 "register_operand" "r,x"))))]
""
"fdiv.dds %0,%1,%2"
[(set_attr "type" "dpdiv")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r"))
- (match_operand:DF 2 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (div:DF (float_extend:DF (match_operand:SF 1 "register_operand" "r,x"))
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fdiv.dsd %0,%1,%2"
[(set_attr "type" "dpdiv")])
(define_insn "divsf3"
- [(set (match_operand:SF 0 "register_operand" "=r")
- (div:SF (match_operand:SF 1 "register_operand" "r")
- (match_operand:SF 2 "register_operand" "r")))]
+ [(set (match_operand:SF 0 "register_operand" "=r,x")
+ (div:SF (match_operand:SF 1 "register_operand" "r,x")
+ (match_operand:SF 2 "register_operand" "r,x")))]
""
"fdiv.sss %0,%1,%2"
[(set_attr "type" "spdiv")])
(define_insn ""
- [(set (match_operand:DF 0 "register_operand" "=r")
- (div:DF (match_operand:DF 1 "register_operand" "r")
- (match_operand:DF 2 "register_operand" "r")))]
+ [(set (match_operand:DF 0 "register_operand" "=r,x")
+ (div:DF (match_operand:DF 1 "register_operand" "r,x")
+ (match_operand:DF 2 "register_operand" "r,x")))]
""
"fdiv.ddd %0,%1,%2"
[(set_attr "type" "dpdiv")])
or.u %0,%1,%X2
set %0,%1,%s2
or.u %0,%1,%X2\;or %0,%0,%x2"
- [(set_attr "type" "arith,arith,arith,marith")])
+ [(set_attr "type" "arith,arith,bit,marith")])
(define_insn ""
[(set (match_operand:DI 0 "register_operand" "=r")
""
"@
mak %0,%1,%2
- mak %0,%1,0<%2>")
+ mak %0,%1,0<%2>"
+ [(set_attr "type" "bit")])
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "register_operand" "")
""
"@
ext %0,%1,%2
- ext %0,%1,0<%2>")
+ ext %0,%1,0<%2>"
+ [(set_attr "type" "bit")])
\f
;;- logical shift instructions. Logical shift left becomes arithmetic
;; shift left. LSHIFT is not normally produced, but is supported.
""
"@
mak %0,%1,%2
- mak %0,%1,0<%2>")
+ mak %0,%1,0<%2>"
+ [(set_attr "type" "bit")])
(define_expand "lshrsi3"
[(set (match_operand:SI 0 "register_operand" "")
""
"@
extu %0,%1,%2
- extu %0,%1,0<%2>")
+ extu %0,%1,0<%2>"
+ [(set_attr "type" "bit")])
\f
;;- rotate instructions
(rotatert:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "arith_operand" "rI")))]
""
- "rot %0,%1,%2")
+ "rot %0,%1,%2"
+ [(set_attr "type" "bit")])
\f
;; Bit field instructions.
operands[4] = gen_rtx (CONST_INT, SImode,
(32 - INTVAL (operands[2])) - INTVAL (operands[3]));
return \"ext %0,%1,%2<%4>\"; /* <(32-%2-%3)> */
-}")
+}"
+ [(set_attr "type" "bit")])
(define_insn ""
[(set (match_operand:SI 0 "register_operand" "=r")
operands[4] = gen_rtx (CONST_INT, SImode,
(32 - INTVAL (operands[2])) - INTVAL (operands[3]));
return \"extu %0,%1,%2<%4>\"; /* <(32-%2-%3)> */
-}")
+}"
+ [(set_attr "type" "bit")])
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
operands[3] = gen_rtx (CONST_INT, SImode,
(32 - INTVAL (operands[1])) - INTVAL (operands[2]));
return \"clr %0,%0,%1<%3>\"; /* <(32-%1-%2)> */
-}")
+}"
+ [(set_attr "type" "bit")])
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
operands[3] = gen_rtx (CONST_INT, SImode,
(32 - INTVAL (operands[1])) - INTVAL (operands[2]));
return \"set %0,%0,%1<%3>\"; /* <(32-%1-%2)> */
-}")
+}"
+ [(set_attr "type" "bit")])
(define_insn ""
[(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
"subu %0,%#r0,%1")
(define_insn ""
- [(set (match_operand:SF 0 "register_operand" "=r")
- (float_truncate:SF (neg:DF (match_operand:DF 1 "register_operand" "r"))))]
+ [(set (match_operand:SF 0 "register_operand" "=r,x")
+ (float_truncate:SF (neg:DF (match_operand:DF 1 "register_operand" "r,x"))))]
""
- "fsub.ssd %0,%#r0,%1"
+ "@
+ fsub.ssd %0,%#r0,%1
+ fsub.ssd %0,%#x0,%1"
[(set_attr "type" "dpadd")])
(define_insn ""
(define_insn "nop"
[(const_int 0)]
""
- "ff0 %#r0,%#r0")
+ "ff0 %#r0,%#r0"
+ [(set_attr "type" "bit")])
(define_insn "return"
[(return)]
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