"* return output_move_qimode (operands);")
(define_insn ""
- [(set (match_operand:QI 0 "general_operand" "=d<>,dm")
- (match_operand:QI 1 "general_operand" "dmi,d<>"))]
+ [(set (match_operand:QI 0 "general_operand" "=d*a<>,d*am")
+ (match_operand:QI 1 "general_operand" "d*ami,d*a<>"))]
"TARGET_5200"
"* return output_move_qimode (operands);")
(define_insn ""
[(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>")
(match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))]
- "! TARGET_68881"
+ "! TARGET_68881 && ! TARGET_5200"
"*
{
if (FP_REG_P (operands[0]))
}
")
+(define_insn ""
+ [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g")
+ (match_operand:XF 1 "nonimmediate_operand" "g,r"))]
+ "! TARGET_68881 && TARGET_5200"
+ "* return output_move_double (operands);")
+
(define_expand "movdi"
;; Let's see if it really still needs to handle fp regs, and, if so, why.
[(set (match_operand:DI 0 "general_operand" "")
return \"\";
}")
+(define_expand "addsi3"
+ [(set (match_operand:SI 0 "general_operand" "")
+ (plus:SI (match_operand:SI 1 "general_operand" "")
+ (match_operand:SI 2 "general_operand" "")))]
+ ""
+ "")
+
;; Note that the middle two alternatives are near-duplicates
;; in order to handle insns generated by reload.
;; This is needed since they are not themselves reloaded,
;; so commutativity won't apply to them.
-(define_insn "addsi3"
+(define_insn "*addsi3_internal"
[(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
(plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
(match_operand:SI 2 "general_operand" "dIKLs,rJK,a,mrIKLs")))]
- ""
- "*
-{
- if (! operands_match_p (operands[0], operands[1]))
- {
- if (!ADDRESS_REG_P (operands[1]))
- {
- rtx tmp = operands[1];
-
- operands[1] = operands[2];
- operands[2] = tmp;
- }
+ "! TARGET_5200"
+ "* return output_addsi3 (operands);")
- /* These insns can result from reloads to access
- stack slots over 64k from the frame pointer. */
- if (GET_CODE (operands[2]) == CONST_INT
- && INTVAL (operands[2]) + 0x8000 >= (unsigned) 0x10000)
- return \"move%.l %2,%0\;add%.l %1,%0\";
-#ifdef SGS
- if (GET_CODE (operands[2]) == REG)
- return \"lea 0(%1,%2.l),%0\";
- else
- return \"lea %c2(%1),%0\";
-#else /* not SGS */
-#ifdef MOTOROLA
- if (GET_CODE (operands[2]) == REG)
- return \"lea (%1,%2.l),%0\";
- else
- return \"lea (%c2,%1),%0\";
-#else /* not MOTOROLA (MIT syntax) */
- if (GET_CODE (operands[2]) == REG)
- return \"lea %1@(0,%2:l),%0\";
- else
- return \"lea %1@(%c2),%0\";
-#endif /* not MOTOROLA */
-#endif /* not SGS */
- }
- if (GET_CODE (operands[2]) == CONST_INT)
- {
-#ifndef NO_ADDSUB_Q
- if (INTVAL (operands[2]) > 0
- && INTVAL (operands[2]) <= 8)
- return \"addq%.l %2,%0\";
- if (INTVAL (operands[2]) < 0
- && INTVAL (operands[2]) >= -8)
- {
- operands[2] = gen_rtx (CONST_INT, VOIDmode,
- - INTVAL (operands[2]));
- return \"subq%.l %2,%0\";
- }
- /* On the CPU32 it is faster to use two addql instructions to
- add a small integer (8 < N <= 16) to a register.
- Likewise for subql. */
- if (TARGET_CPU32 && REG_P (operands[0]))
- {
- if (INTVAL (operands[2]) > 8
- && INTVAL (operands[2]) <= 16)
- {
- operands[2] = gen_rtx (CONST_INT, VOIDmode,
- INTVAL (operands[2]) - 8);
- return \"addq%.l %#8,%0\;addq%.l %2,%0\";
- }
- if (INTVAL (operands[2]) < -8
- && INTVAL (operands[2]) >= -16)
- {
- operands[2] = gen_rtx (CONST_INT, VOIDmode,
- - INTVAL (operands[2]) - 8);
- return \"subq%.l %#8,%0\;subq%.l %2,%0\";
- }
- }
-#endif
- if (ADDRESS_REG_P (operands[0])
- && INTVAL (operands[2]) >= -0x8000
- && INTVAL (operands[2]) < 0x8000)
- {
- if (TARGET_68040)
- return \"add%.w %2,%0\";
- else
-#ifdef MOTOROLA
- return \"lea (%c2,%0),%0\";
-#else
- return \"lea %0@(%c2),%0\";
-#endif
- }
- }
- return \"add%.l %2,%0\";
-}")
+(define_insn "*addsi3_5200"
+ [(set (match_operand:SI 0 "general_operand" "=m,?a,?a,r")
+ (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0")
+ (match_operand:SI 2 "general_operand" "d,rJK,a,mrIKLs")))]
+ "TARGET_5200"
+ "* return output_addsi3 (operands);")
(define_insn ""
[(set (match_operand:SI 0 "general_operand" "=a")