else return \"movd %1,%0\";
}")
-(define_insn ""
+(define_insn "*movti"
[(set (match_operand:TI 0 "memory_operand" "=m")
(match_operand:TI 1 "memory_operand" "m"))]
""
}")
;; This special case must precede movsi.
-(define_insn ""
+(define_insn "*ldsp"
[(set (reg:SI 25)
(match_operand:SI 0 "general_operand" "g"))]
""
"truncld %1,%0")
\f
;; Multiply-add instructions
-(define_insn ""
+(define_insn "*madddf"
[(set (match_operand:DF 0 "nonimmediate_operand" "=v,v,lm")
(plus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0,0")
(match_operand:DF 2 "general_operand" "lmF,lmF,lmF"))
polyl %2,%3
mull %2,%0\;addl %3,%0")
-(define_insn ""
+(define_insn "*maddsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "=u,u,fm")
(plus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0,0")
(match_operand:SF 2 "general_operand" "fmF,fmF,fmF"))
;; Multiply-sub instructions
-(define_insn ""
+(define_insn "*msubdf"
[(set (match_operand:DF 0 "nonimmediate_operand" "=v,lm")
(minus:DF (mult:DF (match_operand:DF 1 "general_operand" "%lmF,0")
(match_operand:DF 2 "general_operand" "lmF,lmF"))
negl %3,%0\;dotl %1,%2
mull %2,%0\;subl %3,%0")
-(define_insn ""
+(define_insn "*msubsf"
[(set (match_operand:SF 0 "nonimmediate_operand" "=u,fm")
(minus:SF (mult:SF (match_operand:SF 1 "general_operand" "%fmF,0")
(match_operand:SF 2 "general_operand" "fmF,fmF"))
"TARGET_32081"
"addf %2,%0")
-(define_insn ""
+(define_insn "*add_to_sp"
[(set (reg:SI 25)
(plus:SI (reg:SI 25)
(match_operand:SI 0 "immediate_operand" "i")))]
return \"adjspd %n0\";
}")
-(define_insn ""
+(define_insn "*frame_addr"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(plus:SI (reg:SI 24)
(match_operand:SI 1 "immediate_operand" "i")))]
"GET_CODE (operands[1]) == CONST_INT"
"addr %c1(fp),%0")
-(define_insn ""
+(define_insn "*stack_addr"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(plus:SI (reg:SI 25)
(match_operand:SI 1 "immediate_operand" "i")))]
return \"addw %2,%0\";
}")
-(define_insn ""
+(define_insn "*addhi_strict_low3"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
(plus:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))]
return \"addb %2,%0\";
}")
-(define_insn ""
+(define_insn "*addqi_strict_low3"
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
(plus:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
"TARGET_32081"
"subf %2,%0")
-(define_insn ""
+(define_insn "*sub_from_sp"
[(set (reg:SI 25)
(minus:SI (reg:SI 25)
(match_operand:SI 0 "immediate_operand" "i")))]
return \"subw %2,%0\";
}")
-(define_insn ""
+(define_insn "*subhi_strict_low3"
[(set (strict_low_part (match_operand:HI 0 "register_operand" "+r"))
(minus:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:HI 2 "general_operand" "g")))]
return \"subb %2,%0\";
}")
-(define_insn ""
+(define_insn "*subqi_strict_low3"
[(set (strict_low_part (match_operand:QI 0 "register_operand" "+r"))
(minus:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:QI 2 "general_operand" "g")))]
""
"deid %2,%0")
-;; Part word variants. These seem to never be used at the moment (gcc
-;; 2.7.2.2). The code generation prefers to zero extend hi's and qi's
-;; and use signed div and mod. Keep these insns incase that changes.
-;; divmod should have an advantage when both div and mod are needed. However,
-;; divmod uses two registers, so maybe the compiler knows best.
-
-(define_expand "udivmodhi4"
- [(parallel
- [(set (match_operand:HI 0 "nonimmediate_operand" "")
- (udiv:HI (match_operand:HI 1 "general_operand" "")
- (match_operand:HI 2 "general_operand" "")))
- (set (match_operand:HI 3 "nonimmediate_operand" "")
- (umod:HI (match_dup 1) (match_dup 2)))])]
- ""
- "
-{
- rtx temp = gen_reg_rtx(DImode);
- rtx insn, first, last;
- first = emit_move_insn(gen_lowpart(HImode, temp), operands[1]);
- emit_move_insn(gen_highpart (HImode, temp), const0_rtx);
- operands[2] = force_reg(HImode, operands[2]);
- emit_insn(gen_udivmoddihi4_internal(temp, temp, operands[2]));
- last = emit_move_insn(temp, temp);
- {
- rtx divdi, moddi, divhi, modhi;
- divhi = gen_rtx (UDIV, HImode, operands[1], operands[2]);
- modhi = gen_rtx (UMOD, HImode, operands[1], operands[2]);
- divdi = gen_rtx (ZERO_EXTEND, DImode, divhi);
- moddi = gen_rtx (ZERO_EXTEND, DImode, modhi);
- REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
- REG_NOTES (first));
- REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
- gen_rtx (EXPR_LIST, REG_EQUAL,
- gen_rtx(IOR, DImode, moddi,
- gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
- REG_NOTES (last)));
- }
-
- insn = emit_move_insn(operands[0], gen_highpart(HImode, temp));
- insn = emit_move_insn(operands[3], gen_lowpart(HImode, temp));
- DONE;
-}")
-
-;; deiw wants two hi's in separate registers or else they can be adjacent
-;; in memory. DI mode will ensure two registers are available, but if we
-;; want to allow memory as an operand we would need SI mode. There is no
-;; way to do this, so just restrict operand 0 and 1 to be in registers.
-(define_insn "udivmoddihi4_internal"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "register_operand" "0")
- (match_operand:HI 2 "general_operand" "g")] 0))]
- ""
- "deiw %2,%0")
-
-(define_insn "udivmoddihi4"
- [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 2)
- (truncate:HI (udiv:DI (match_operand:DI 1 "register_operand" "0")
- (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "rm")))))
- (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
- (truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
- ""
- "deiw %2,%0")
-
-(define_expand "udivmodqi4"
- [(parallel
- [(set (match_operand:QI 0 "nonimmediate_operand" "")
- (udiv:QI (match_operand:QI 1 "general_operand" "")
- (match_operand:QI 2 "general_operand" "")))
- (set (match_operand:QI 3 "nonimmediate_operand" "")
- (umod:QI (match_dup 1) (match_dup 2)))])]
- ""
- "
-{
- rtx temp = gen_reg_rtx(DImode);
- rtx insn, first, last;
- first = emit_move_insn(gen_lowpart(QImode, temp), operands[1]);
- emit_move_insn(gen_highpart(QImode, temp), const0_rtx);
- operands[2] = force_reg(QImode, operands[2]);
- emit_insn(gen_udivmoddiqi4_internal(temp, temp, operands[2]));
- last = emit_move_insn(temp, temp);
- {
- rtx divdi, moddi, divqi, modqi;
- divqi = gen_rtx (UDIV, QImode, operands[1], operands[2]);
- modqi = gen_rtx (UMOD, QImode, operands[1], operands[2]);
- divdi = gen_rtx (ZERO_EXTEND, DImode, divqi);
- moddi = gen_rtx (ZERO_EXTEND, DImode, modqi);
- REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
- REG_NOTES (first));
- REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
- gen_rtx (EXPR_LIST, REG_EQUAL,
- gen_rtx(IOR, DImode, moddi,
- gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
- REG_NOTES (last)));
- }
-
- insn = emit_move_insn(operands[0], gen_highpart(QImode, temp));
- insn = emit_move_insn(operands[3], gen_lowpart(QImode, temp));
- DONE;
-}")
-
-;; deib wants two qi's in separate registers or else they can be adjacent
-;; in memory. DI mode will ensure two registers are available, but if we
-;; want to allow memory as an operand we would need HI mode. There is no
-;; way to do this, so just restrict operand 0 and 1 to be in registers.
-(define_insn "udivmoddiqi4_internal"
- [(set (match_operand:DI 0 "register_operand" "=r")
- (unspec:DI [(match_operand:DI 1 "register_operand" "0")
- (match_operand:QI 2 "general_operand" "g")] 0))]
- ""
- "deib %2,%0")
-
-(define_insn "udivmoddiqi4"
- [(set (subreg:QI (match_operand:DI 0 "register_operand" "=r") 1)
- (truncate:QI (udiv:DI (match_operand:DI 1 "register_operand" "0")
- (zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "rm")))))
- (set (subreg:QI (match_operand:DI 3 "register_operand" "=0") 0)
- (truncate:QI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
- ""
- "deib %2,%0")
+;;;; Part word variants. These seem to never be used at the moment (gcc
+;;;; 2.7.2.2). The code generation prefers to zero extend hi's and qi's
+;;;; and use signed div and mod. Keep these insns incase that changes.
+;;;; divmod should have an advantage when both div and mod are needed. However,
+;;;; divmod uses two registers, so maybe the compiler knows best.
+;;
+;;(define_expand "udivmodhi4"
+;; [(parallel
+;; [(set (match_operand:HI 0 "nonimmediate_operand" "")
+;; (udiv:HI (match_operand:HI 1 "general_operand" "")
+;; (match_operand:HI 2 "general_operand" "")))
+;; (set (match_operand:HI 3 "nonimmediate_operand" "")
+;; (umod:HI (match_dup 1) (match_dup 2)))])]
+;; ""
+;; "
+;;{
+;; rtx temp = gen_reg_rtx(DImode);
+;; rtx insn, first, last;
+;; first = emit_move_insn(gen_lowpart(HImode, temp), operands[1]);
+;; emit_move_insn(gen_highpart (HImode, temp), const0_rtx);
+;; operands[2] = force_reg(HImode, operands[2]);
+;; emit_insn(gen_udivmoddihi4_internal(temp, temp, operands[2]));
+;; last = emit_move_insn(temp, temp);
+;; {
+;; rtx divdi, moddi, divhi, modhi;
+;; divhi = gen_rtx (UDIV, HImode, operands[1], operands[2]);
+;; modhi = gen_rtx (UMOD, HImode, operands[1], operands[2]);
+;; divdi = gen_rtx (ZERO_EXTEND, DImode, divhi);
+;; moddi = gen_rtx (ZERO_EXTEND, DImode, modhi);
+;; REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
+;; REG_NOTES (first));
+;; REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
+;; gen_rtx (EXPR_LIST, REG_EQUAL,
+;; gen_rtx(IOR, DImode, moddi,
+;; gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
+;; REG_NOTES (last)));
+;; }
+;;
+;; insn = emit_move_insn(operands[0], gen_highpart(HImode, temp));
+;; insn = emit_move_insn(operands[3], gen_lowpart(HImode, temp));
+;; DONE;
+;;}")
+;;
+;;;; deiw wants two hi's in separate registers or else they can be adjacent
+;;;; in memory. DI mode will ensure two registers are available, but if we
+;;;; want to allow memory as an operand we would need SI mode. There is no
+;;;; way to do this, so just restrict operand 0 and 1 to be in registers.
+;;(define_insn "udivmoddihi4_internal"
+;; [(set (match_operand:DI 0 "register_operand" "=r")
+;; (unspec:DI [(match_operand:DI 1 "register_operand" "0")
+;; (match_operand:HI 2 "general_operand" "g")] 0))]
+;; ""
+;; "deiw %2,%0")
+;;
+;;(define_insn "udivmoddihi4"
+;; [(set (subreg:HI (match_operand:DI 0 "register_operand" "=r") 2)
+;; (truncate:HI (udiv:DI (match_operand:DI 1 "register_operand" "0")
+;; (zero_extend:DI (match_operand:HI 2 "nonimmediate_operand" "rm")))))
+;; (set (subreg:HI (match_operand:DI 3 "register_operand" "=0") 0)
+;; (truncate:HI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
+;; ""
+;; "deiw %2,%0")
+;;
+;;(define_expand "udivmodqi4"
+;; [(parallel
+;; [(set (match_operand:QI 0 "nonimmediate_operand" "")
+;; (udiv:QI (match_operand:QI 1 "general_operand" "")
+;; (match_operand:QI 2 "general_operand" "")))
+;; (set (match_operand:QI 3 "nonimmediate_operand" "")
+;; (umod:QI (match_dup 1) (match_dup 2)))])]
+;; ""
+;; "
+;;{
+;; rtx temp = gen_reg_rtx(DImode);
+;; rtx insn, first, last;
+;; first = emit_move_insn(gen_lowpart(QImode, temp), operands[1]);
+;; emit_move_insn(gen_highpart(QImode, temp), const0_rtx);
+;; operands[2] = force_reg(QImode, operands[2]);
+;; emit_insn(gen_udivmoddiqi4_internal(temp, temp, operands[2]));
+;; last = emit_move_insn(temp, temp);
+;; {
+;; rtx divdi, moddi, divqi, modqi;
+;; divqi = gen_rtx (UDIV, QImode, operands[1], operands[2]);
+;; modqi = gen_rtx (UMOD, QImode, operands[1], operands[2]);
+;; divdi = gen_rtx (ZERO_EXTEND, DImode, divqi);
+;; moddi = gen_rtx (ZERO_EXTEND, DImode, modqi);
+;; REG_NOTES (first) = gen_rtx (INSN_LIST, REG_LIBCALL, last,
+;; REG_NOTES (first));
+;; REG_NOTES (last) = gen_rtx (INSN_LIST, REG_RETVAL, first,
+;; gen_rtx (EXPR_LIST, REG_EQUAL,
+;; gen_rtx(IOR, DImode, moddi,
+;; gen_rtx(ASHIFT, DImode, divdi, GEN_INT(32))),
+;; REG_NOTES (last)));
+;; }
+;;
+;; insn = emit_move_insn(operands[0], gen_highpart(QImode, temp));
+;; insn = emit_move_insn(operands[3], gen_lowpart(QImode, temp));
+;; DONE;
+;;}")
+;;
+;;;; deib wants two qi's in separate registers or else they can be adjacent
+;;;; in memory. DI mode will ensure two registers are available, but if we
+;;;; want to allow memory as an operand we would need HI mode. There is no
+;;;; way to do this, so just restrict operand 0 and 1 to be in registers.
+;;(define_insn "udivmoddiqi4_internal"
+;; [(set (match_operand:DI 0 "register_operand" "=r")
+;; (unspec:DI [(match_operand:DI 1 "register_operand" "0")
+;; (match_operand:QI 2 "general_operand" "g")] 0))]
+;; ""
+;; "deib %2,%0")
+;;
+;;(define_insn "udivmoddiqi4"
+;; [(set (subreg:QI (match_operand:DI 0 "register_operand" "=r") 1)
+;; (truncate:QI (udiv:DI (match_operand:DI 1 "register_operand" "0")
+;; (zero_extend:DI (match_operand:QI 2 "nonimmediate_operand" "rm")))))
+;; (set (subreg:QI (match_operand:DI 3 "register_operand" "=0") 0)
+;; (truncate:QI (umod:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))]
+;; ""
+;; "deib %2,%0")
\f
;;- Divide instructions.
"andb %2,%0")
;; See note 1
-(define_insn ""
+(define_insn "*bicsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(and:SI (not:SI (match_operand:SI 1 "general_operand" "g"))
(match_operand:SI 2 "general_operand" "0")))]
""
"bicd %1,%0")
-(define_insn ""
+(define_insn "*bichi"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(and:HI (not:HI (match_operand:HI 1 "general_operand" "g"))
(match_operand:HI 2 "general_operand" "0")))]
""
"bicw %1,%0")
-(define_insn ""
+(define_insn "*bicqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(and:QI (not:QI (match_operand:QI 1 "general_operand" "g"))
(match_operand:QI 2 "general_operand" "0")))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*ashrisi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"ashd %n2,%0")
-(define_insn ""
+(define_insn "*ashrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(ashiftrt:SI (match_operand:SI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*ashrihi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"ashw %n2,%0")
-(define_insn ""
+(define_insn "*ashrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(ashiftrt:HI (match_operand:HI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*ashriqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"ashb %n2,%0")
-(define_insn ""
+(define_insn "*ashrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(ashiftrt:QI (match_operand:QI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*lshrisi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"lshd %n2,%0")
-(define_insn ""
+(define_insn "*lshrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(lshiftrt:SI (match_operand:SI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*lshrihi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"lshw %n2,%0")
-(define_insn ""
+(define_insn "*lshrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(lshiftrt:HI (match_operand:HI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*lshriqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"lshb %n2,%0")
-(define_insn ""
+(define_insn "*lshrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(lshiftrt:QI (match_operand:QI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*rotrisi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(rotatert:SI (match_operand:SI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"rotd %n2,%0")
-(define_insn ""
+(define_insn "*rotrsi3"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm")
(rotatert:SI (match_operand:SI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*rotrihi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(rotatert:HI (match_operand:HI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"rotw %n2,%0")
-(define_insn ""
+(define_insn "*rotrhi3"
[(set (match_operand:HI 0 "nonimmediate_operand" "=rm")
(rotatert:HI (match_operand:HI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
operands[2] = gen_rtx_NEG (SImode, negate_rtx (SImode, operands[2]));
}")
-(define_insn ""
+(define_insn "*rotriqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(rotatert:QI (match_operand:QI 1 "general_operand" "0")
(match_operand:SI 2 "immediate_operand" "i")))]
""
"rotb %n2,%0")
-(define_insn ""
+(define_insn "*rotrqi3"
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(rotatert:QI (match_operand:QI 1 "general_operand" "0")
(neg:SI (match_operand:SI 2 "register_operand" "r"))))]
;; These come after the move, add, and multiply patterns
;; because we don't want pushl $1 turned into pushad 1.
-(define_insn ""
+(define_insn "*addrsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(match_operand:QI 1 "address_operand" "p"))]
""
;; Set, Clear, and Invert bit
;; See note 1
-(define_insn ""
+(define_insn "*sbitsi"
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
(const_int 1)
(match_operand:SI 1 "general_operand" "g"))
"sbitd %1,%0")
;; See note 1
-(define_insn ""
+(define_insn "*cbitsi"
[(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "+rm")
(const_int 1)
(match_operand:SI 1 "general_operand" "g"))
"cbitd %1,%0")
;; See note 1
-(define_insn ""
+(define_insn "*ibitsi"
[(set (match_operand:SI 0 "nonimmediate_operand" "+rm")
(xor:SI (ashift:SI (const_int 1)
(match_operand:SI 1 "general_operand" "g"))
"ibitd %1,%0")
;; See note 1
-(define_insn ""
+(define_insn "*ibitqi"
[(set (match_operand:QI 0 "nonimmediate_operand" "=rm")
(xor:QI (subreg:QI
(ashift:SI (const_int 1)
;; Recognize jbs and jbc instructions.
-(define_insn ""
+(define_insn "*tbit"
[(set (cc0)
(zero_extract (match_operand:SI 0 "nonimmediate_operand" "rm")
(const_int 1)
;; we cannot use it for a destination. Perhaps things are fast
;; enough on the 32532 that such hacks are not needed.
-(define_insn ""
+(define_insn "*extract_bytes"
[(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
(zero_extract:SI (match_operand:SI 1 "register_operand" "r")
(match_operand:SI 2 "const_int_operand" "i")
;; A machine specific option (-mbitfield/-mnobitfield) is used
;; to allow/disallow the use of these instructions.
-(define_insn ""
+(define_insn "*bitfield_ext"
[(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
(zero_extract:SI (match_operand:SI 1 "register_operand" "g")
(match_operand:SI 2 "const_int_operand" "i")
else return \"extd %3,%1,%0,%2\";
}")
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o")
- (match_operand:SI 1 "const_int_operand" "i")
- (match_operand:SI 2 "nonmemory_operand" "rn"))
- (match_operand:SI 3 "nonimmediate_operand" "rm"))]
+(define_insn "*bitfield_set"
+ [(set (zero_extract:SI (match_operand:SI 0 "memory_operand" "+o,+r")
+ (match_operand:SI 1 "const_int_operand" "i,i")
+ (match_operand:SI 2 "nonmemory_operand" "rn,rK"))
+ (match_operand:SI 3 "nonimmediate_operand" "rm,rm"))]
"TARGET_BITFIELD"
"*
{ if (GET_CODE (operands[2]) == CONST_INT)
{
- if (INTVAL (operands[2]) >= 8)
+ if (which_alternative == 0 && INTVAL (operands[2]) >= 8)
{
operands[0] = adjust_address (operands[0], QImode,
INTVAL (operands[2]) / 8);
return \"insd %2,%3,%0,%1\";
}")
-(define_insn ""
- [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r")
- (match_operand:SI 1 "const_int_operand" "i")
- (match_operand:SI 2 "nonmemory_operand" "rK"))
- (match_operand:SI 3 "nonimmediate_operand" "rm"))]
- "TARGET_BITFIELD"
- "*
-{ if (GET_CODE (operands[2]) == CONST_INT)
- {
- if (INTVAL (operands[1]) <= 8)
- return \"inssb %3,%0,%2,%1\";
- else if (INTVAL (operands[1]) <= 16)
- return \"inssw %3,%0,%2,%1\";
- else
- return \"inssd %3,%0,%2,%1\";
- }
- return \"insd %2,%3,%0,%1\";
-}")
(define_insn "insv"
[(set (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "+rm")
""
"bls %l0")
\f
-(define_insn ""
+;; "Reversed" jump instructions. Are these ever generated?
+
+(define_insn "*bne"
[(set (pc)
(if_then_else (eq (cc0)
(const_int 0))
else return \"bne %l0\";
}")
-(define_insn ""
+(define_insn "*beq"
[(set (pc)
(if_then_else (ne (cc0)
(const_int 0))
else return \"beq %l0\";
}")
-(define_insn ""
+(define_insn "*ble"
[(set (pc)
(if_then_else (gt (cc0)
(const_int 0))
""
"ble %l0")
-(define_insn ""
+(define_insn "*bleu"
[(set (pc)
(if_then_else (gtu (cc0)
(const_int 0))
""
"bls %l0")
-(define_insn ""
+(define_insn "*bge"
[(set (pc)
(if_then_else (lt (cc0)
(const_int 0))
""
"bge %l0")
-(define_insn ""
+(define_insn "*bgeu"
[(set (pc)
(if_then_else (ltu (cc0)
(const_int 0))
""
"bhs %l0")
-(define_insn ""
+(define_insn "*blt"
[(set (pc)
(if_then_else (ge (cc0)
(const_int 0))
""
"blt %l0")
-(define_insn ""
+(define_insn "*bltu"
[(set (pc)
(if_then_else (geu (cc0)
(const_int 0))
""
"blo %l0")
-(define_insn ""
+(define_insn "*bgt"
[(set (pc)
(if_then_else (le (cc0)
(const_int 0))
""
"bgt %l0")
-(define_insn ""
+(define_insn "*bgtu"
[(set (pc)
(if_then_else (leu (cc0)
(const_int 0))
;; Subtract-and-jump and Add-and-jump insns.
;; These can actually be used for adding numbers in the range -8 to 7
-(define_insn ""
+(define_insn "*sub_br"
[(set (pc)
(if_then_else
(ne (match_operand:SI 0 "nonimmediate_operand" "+rm")
"INTVAL (operands[1]) > -8 && INTVAL (operands[1]) <= 8"
"acbd %n1,%0,%l2")
-(define_insn ""
+(define_insn "*add_br"
[(set (pc)
(if_then_else
(ne (match_operand:SI 0 "nonimmediate_operand" "+rm")
\f
(define_insn "call"
[(call (match_operand:QI 0 "memory_operand" "m")
- (match_operand:QI 1 "general_operand" "g"))]
+ (match_operand 1 "" ""))]
+ ;; Operand 1 is not used
""
"*
{
(define_insn "call_value"
[(set (match_operand 0 "" "=rf")
(call (match_operand:QI 1 "memory_operand" "m")
- (match_operand:QI 2 "general_operand" "g")))]
+ (match_operand 2 "" "")))]
+ ;; Operand 2 is not used
""
"*
{
;; Scondi instructions
(define_insn "seq"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(eq:SI (cc0) (const_int 0)))]
""
"*
else return \"seqd %0\";
}")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*seqhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(eq:HI (cc0) (const_int 0)))]
""
"*
else return \"seqw %0\";
}")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*seqqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(eq:QI (cc0) (const_int 0)))]
""
"*
}")
(define_insn "sne"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(ne:SI (cc0) (const_int 0)))]
""
"*
else return \"sned %0\";
}")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*snehi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(ne:HI (cc0) (const_int 0)))]
""
"*
else return \"snew %0\";
}")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sneqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(ne:QI (cc0) (const_int 0)))]
""
"*
}")
(define_insn "sgt"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(gt:SI (cc0) (const_int 0)))]
""
"sgtd %0")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sgthi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(gt:HI (cc0) (const_int 0)))]
""
"sgtw %0")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sgtqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(gt:QI (cc0) (const_int 0)))]
""
"sgtb %0")
(define_insn "sgtu"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(gtu:SI (cc0) (const_int 0)))]
""
"shid %0")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sgtuhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(gtu:HI (cc0) (const_int 0)))]
""
"shiw %0")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sgtuqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(gtu:QI (cc0) (const_int 0)))]
""
"shib %0")
(define_insn "slt"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(lt:SI (cc0) (const_int 0)))]
""
"sltd %0")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*slthi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(lt:HI (cc0) (const_int 0)))]
""
"sltw %0")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sltqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(lt:QI (cc0) (const_int 0)))]
""
"sltb %0")
(define_insn "sltu"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(ltu:SI (cc0) (const_int 0)))]
""
"slod %0")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sltuhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(ltu:HI (cc0) (const_int 0)))]
""
"slow %0")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sltuqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(ltu:QI (cc0) (const_int 0)))]
""
"slob %0")
(define_insn "sge"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(ge:SI (cc0) (const_int 0)))]
""
"sged %0")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sgehi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(ge:HI (cc0) (const_int 0)))]
""
"sgew %0")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sgeqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(ge:QI (cc0) (const_int 0)))]
""
"sgeb %0")
(define_insn "sgeu"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(geu:SI (cc0) (const_int 0)))]
""
"shsd %0")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sgeuhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(geu:HI (cc0) (const_int 0)))]
""
"shsw %0")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sgeuqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(geu:QI (cc0) (const_int 0)))]
""
"shsb %0")
(define_insn "sle"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(le:SI (cc0) (const_int 0)))]
""
"sled %0")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*slehi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(le:HI (cc0) (const_int 0)))]
""
"slew %0")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sleqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(le:QI (cc0) (const_int 0)))]
""
"sleb %0")
(define_insn "sleu"
- [(set (match_operand:SI 0 "nonimmediate_operand" "=rm<")
+ [(set (match_operand:SI 0 "nonimmediate_operand" "=r<")
(leu:SI (cc0) (const_int 0)))]
""
"slsd %0")
-(define_insn ""
- [(set (match_operand:HI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sleuhi"
+ [(set (match_operand:HI 0 "nonimmediate_operand" "=r<")
(leu:HI (cc0) (const_int 0)))]
""
"slsw %0")
-(define_insn ""
- [(set (match_operand:QI 0 "nonimmediate_operand" "=rm<")
+(define_insn "*sleuqi"
+ [(set (match_operand:QI 0 "nonimmediate_operand" "=r<")
(leu:QI (cc0) (const_int 0)))]
""
"slsb %0")
\f
;; ffs instructions
-(define_insn ""
+(define_insn "*ffs"
[(set (match_operand:SI 0 "nonimmediate_operand" "=ro")
(minus:SI
(plus:SI (ffs:SI (zero_extract:SI
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