@c man end
@c man begin SEEALSO
gpl(7), gfdl(7), fsf-funding(7),
-cpp(1), gcov(1), g77(1), as(1), ld(1), gdb(1), adb(1), dbx(1), sdb(1)
-and the Info entries for @file{gcc}, @file{cpp}, @file{g77}, @file{as},
+cpp(1), gcov(1), as(1), ld(1), gdb(1), adb(1), dbx(1), sdb(1)
+and the Info entries for @file{gcc}, @file{cpp}, @file{as},
@file{ld}, @file{binutils} and @file{gdb}.
@c man end
@c man begin BUGS
@table @emph
@item Overall Options
@xref{Overall Options,,Options Controlling the Kind of Output}.
-@gccoptlist{-c -S -E -o @var{file} -pipe -pass-exit-codes @gol
+@gccoptlist{-c -S -E -o @var{file} -combine -pipe -pass-exit-codes @gol
-x @var{language} -v -### --help --target-help --version}
@item C Language Options
-Wconversion -Wno-deprecated-declarations @gol
-Wdisabled-optimization -Wno-div-by-zero -Wendif-labels @gol
-Werror -Werror-implicit-function-declaration @gol
--Wfloat-equal -Wformat -Wformat=2 @gol
+-Wfatal-errors -Wfloat-equal -Wformat -Wformat=2 @gol
-Wno-format-extra-args -Wformat-nonliteral @gol
-Wformat-security -Wformat-y2k @gol
-Wimplicit -Wimplicit-function-declaration -Wimplicit-int @gol
-Wno-invalid-offsetof -Winvalid-pch @gol
-Wlarger-than-@var{len} -Wlong-long @gol
-Wmain -Wmissing-braces @gol
--Wmissing-format-attribute -Wmissing-noreturn @gol
+-Wmissing-format-attribute -Wmissing-include-dirs @gol
+-Wmissing-noreturn @gol
-Wno-multichar -Wnonnull -Wpacked -Wpadded @gol
-Wparentheses -Wpointer-arith -Wredundant-decls @gol
-Wreturn-type -Wsequence-point -Wshadow @gol
@gccoptlist{-d@var{letters} -dumpspecs -dumpmachine -dumpversion @gol
-fdump-unnumbered -fdump-translation-unit@r{[}-@var{n}@r{]} @gol
-fdump-class-hierarchy@r{[}-@var{n}@r{]} @gol
+-fdump-tree-all @gol
-fdump-tree-original@r{[}-@var{n}@r{]} @gol
-fdump-tree-optimized@r{[}-@var{n}@r{]} @gol
-fdump-tree-inlined@r{[}-@var{n}@r{]} @gol
+-fdump-tree-cfg -fdump-tree-vcg -fdump-tree-alias @gol
+-fdump-tree-ch @gol
+-fdump-tree-ssa@r{[}-@var{n}@r{]} -fdump-tree-pre@r{[}-@var{n}@r{]} @gol
+-fdump-tree-ccp@r{[}-@var{n}@r{]} -fdump-tree-dce@r{[}-@var{n}@r{]} @gol
+-fdump-tree-gimple@r{[}-raw@r{]} -fdump-tree-mudflap@r{[}-@var{n}@r{]} @gol
+-fdump-tree-dom@r{[}-@var{n}@r{]} @gol
+-fdump-tree-dse@r{[}-@var{n}@r{]} @gol
+-fdump-tree-phiopt@r{[}-@var{n}@r{]} @gol
+-fdump-tree-forwprop@r{[}-@var{n}@r{]} @gol
+-fdump-tree-copyrename@r{[}-@var{n}@r{]} @gol
+-fdump-tree-nrv @gol
+-fdump-tree-sra@r{[}-@var{n}@r{]} @gol
+-fdump-tree-fre@r{[}-@var{n}@r{]} @gol
-feliminate-dwarf2-dups -feliminate-unused-debug-types @gol
--feliminate-unused-debug-symbols -fmem-report -fprofile-arcs @gol
+-feliminate-unused-debug-symbols -fmem-report -fprofile-arcs -ftree-based-profiling @gol
-frandom-seed=@var{string} -fsched-verbose=@var{n} @gol
-ftest-coverage -ftime-report -fvar-tracking @gol
-g -g@var{level} -gcoff -gdwarf-2 @gol
@xref{Optimize Options,,Options that Control Optimization}.
@gccoptlist{-falign-functions=@var{n} -falign-jumps=@var{n} @gol
-falign-labels=@var{n} -falign-loops=@var{n} @gol
+-fbounds-check -fmudflap -fmudflapth -fmudflapir @gol
-fbranch-probabilities -fprofile-values -fvpt -fbranch-target-load-optimize @gol
-fbranch-target-load-optimize2 -fbtr-bb-exclusive @gol
-fcaller-saves -fcprop-registers @gol
-fdelayed-branch -fdelete-null-pointer-checks @gol
-fexpensive-optimizations -ffast-math -ffloat-store @gol
-fforce-addr -fforce-mem -ffunction-sections @gol
--fgcse -fgcse-lm -fgcse-sm -fgcse-las -floop-optimize @gol
--fcrossjumping -fif-conversion -fif-conversion2 @gol
+-fgcse -fgcse-lm -fgcse-sm -fgcse-las -fgcse-after-reload @gol
+-floop-optimize -fcrossjumping -fif-conversion -fif-conversion2 @gol
-finline-functions -finline-limit=@var{n} -fkeep-inline-functions @gol
-fkeep-static-consts -fmerge-constants -fmerge-all-constants @gol
--fmove-all-movables -fnew-ra -fno-branch-count-reg @gol
--fno-default-inline -fno-defer-pop @gol
+-fmodulo-sched -fmove-all-movables -fnew-ra -fno-branch-count-reg @gol
+-fno-default-inline -fno-defer-pop -floop-optimize2 -fmove-loop-invariants @gol
-fno-function-cse -fno-guess-branch-probability @gol
-fno-inline -fno-math-errno -fno-peephole -fno-peephole2 @gol
-funsafe-math-optimizations -ffinite-math-only @gol
-foptimize-sibling-calls -fprefetch-loop-arrays @gol
-fprofile-generate -fprofile-use @gol
-freduce-all-givs -fregmove -frename-registers @gol
--freorder-blocks -freorder-functions @gol
+-freorder-blocks -freorder-blocks-and-partition -freorder-functions @gol
-frerun-cse-after-loop -frerun-loop-opt @gol
-frounding-math -fschedule-insns -fschedule-insns2 @gol
-fno-sched-interblock -fno-sched-spec -fsched-spec-load @gol
-fstrength-reduce -fstrict-aliasing -ftracer -fthread-jumps @gol
-funroll-all-loops -funroll-loops -fpeel-loops @gol
-funswitch-loops -fold-unroll-loops -fold-unroll-all-loops @gol
+-ftree-pre -ftree-ccp -ftree-dce -ftree-loop-optimize @gol
+-ftree-dominator-opts -ftree-dse -ftree-copyrename @gol
+-ftree-ch -ftree-sra -ftree-ter -ftree-lrs -ftree-fre @gol
--param @var{name}=@var{value}
-O -O0 -O1 -O2 -O3 -Os}
@item Directory Options
@xref{Directory Options,,Options for Directory Search}.
-@gccoptlist{-B@var{prefix} -I@var{dir} -I- -L@var{dir} -specs=@var{file}}
+@gccoptlist{-B@var{prefix} -I@var{dir} -iquote@var{dir} -L@var{dir} -specs=@var{file} -I-}
@item Target Options
@c I wrote this xref this way to avoid overfull hbox. -- rms
@item Machine Dependent Options
@xref{Submodel Options,,Hardware Models and Configurations}.
+@c This list is ordered alphanumerically by subsection name.
+@c Try and put the significant identifier (CPU or system) first,
+@c so users have a clue at guessing where the ones they want will be.
-@emph{M680x0 Options}
-@gccoptlist{-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 @gol
--m68060 -mcpu32 -m5200 -m68881 -mbitfield -mc68000 -mc68020 @gol
--mnobitfield -mrtd -mshort -msoft-float -mpcrel @gol
--malign-int -mstrict-align -msep-data -mno-sep-data @gol
--mshared-library-id=n -mid-shared-library -mno-id-shared-library}
-
-@emph{M68hc1x Options}
-@gccoptlist{-m6811 -m6812 -m68hc11 -m68hc12 -m68hcs12 @gol
--mauto-incdec -minmax -mlong-calls -mshort @gol
--msoft-reg-count=@var{count}}
-
-@emph{VAX Options}
-@gccoptlist{-mg -mgnu -munix}
-
-@emph{SPARC Options}
-@gccoptlist{-mcpu=@var{cpu-type} @gol
--mtune=@var{cpu-type} @gol
--mcmodel=@var{code-model} @gol
--m32 -m64 -mapp-regs -mno-app-regs @gol
--mfaster-structs -mno-faster-structs @gol
--mfpu -mno-fpu -mhard-float -msoft-float @gol
--mhard-quad-float -msoft-quad-float @gol
--mimpure-text -mno-impure-text -mlittle-endian @gol
--mstack-bias -mno-stack-bias @gol
--munaligned-doubles -mno-unaligned-doubles @gol
--mv8plus -mno-v8plus -mvis -mno-vis}
+@emph{ARC Options}
+@gccoptlist{-EB -EL @gol
+-mmangle-cpu -mcpu=@var{cpu} -mtext=@var{text-section} @gol
+-mdata=@var{data-section} -mrodata=@var{readonly-data-section}}
@emph{ARM Options}
@gccoptlist{-mapcs-frame -mno-apcs-frame @gol
-mabi=@var{name} @gol
--mapcs-26 -mapcs-32 @gol
-mapcs-stack-check -mno-apcs-stack-check @gol
-mapcs-float -mno-apcs-float @gol
-mapcs-reentrant -mno-apcs-reentrant @gol
-msched-prolog -mno-sched-prolog @gol
-mlittle-endian -mbig-endian -mwords-little-endian @gol
--malignment-traps -mno-alignment-traps @gol
--mfloat-abi=@var{name} soft-float -mhard-float -mfpe @gol
+-mfloat-abi=@var{name} -msoft-float -mhard-float -mfpe @gol
-mthumb-interwork -mno-thumb-interwork @gol
-mcpu=@var{name} -march=@var{name} -mfpu=@var{name} @gol
-mstructure-size-boundary=@var{n} @gol
-mtpcs-frame -mtpcs-leaf-frame @gol
-mcaller-super-interworking -mcallee-super-interworking}
-@emph{MN10300 Options}
-@gccoptlist{-mmult-bug -mno-mult-bug @gol
--mam33 -mno-am33 @gol
--mam33-2 -mno-am33-2 @gol
--mno-crt0 -mrelax}
-
-@emph{M32R/D Options}
-@gccoptlist{-m32r2 -m32rx -m32r @gol
--mdebug @gol
--malign-loops -mno-align-loops @gol
--missue-rate=@var{number} @gol
--mbranch-cost=@var{number} @gol
--mmodel=@var{code-size-model-type} @gol
--msdata=@var{sdata-type} @gol
--mno-flush-func -mflush-func=@var{name} @gol
--mno-flush-trap -mflush-trap=@var{number} @gol
--G @var{num}}
+@emph{AVR Options}
+@gccoptlist{-mmcu=@var{mcu} -msize -minit-stack=@var{n} -mno-interrupts @gol
+-mcall-prologues -mno-tablejump -mtiny-stack -mint8}
-@emph{RS/6000 and PowerPC Options}
-@gccoptlist{-mcpu=@var{cpu-type} @gol
--mtune=@var{cpu-type} @gol
--mpower -mno-power -mpower2 -mno-power2 @gol
--mpowerpc -mpowerpc64 -mno-powerpc @gol
--maltivec -mno-altivec @gol
--mpowerpc-gpopt -mno-powerpc-gpopt @gol
--mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
--mnew-mnemonics -mold-mnemonics @gol
--mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
--m64 -m32 -mxl-call -mno-xl-call -mpe @gol
--malign-power -malign-natural @gol
--msoft-float -mhard-float -mmultiple -mno-multiple @gol
--mstring -mno-string -mupdate -mno-update @gol
--mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol
--mstrict-align -mno-strict-align -mrelocatable @gol
--mno-relocatable -mrelocatable-lib -mno-relocatable-lib @gol
--mtoc -mno-toc -mlittle -mlittle-endian -mbig -mbig-endian @gol
--mdynamic-no-pic @gol
--mprioritize-restricted-insns=@var{priority} @gol
--msched-costly-dep=@var{dependence_type} @gol
--minsert-sched-nops=@var{scheme} @gol
--mcall-sysv -mcall-netbsd @gol
--maix-struct-return -msvr4-struct-return @gol
--mabi=altivec -mabi=no-altivec @gol
--mabi=spe -mabi=no-spe @gol
--misel=yes -misel=no @gol
--mspe=yes -mspe=no @gol
--mfloat-gprs=yes -mfloat-gprs=no @gol
--mprototype -mno-prototype @gol
--msim -mmvme -mads -myellowknife -memb -msdata @gol
--msdata=@var{opt} -mvxworks -mwindiss -G @var{num} -pthread}
+@emph{CRIS Options}
+@gccoptlist{-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol
+-mmax-stack-frame=@var{n} -melinux-stacksize=@var{n} @gol
+-metrax4 -metrax100 -mpdebug -mcc-init -mno-side-effects @gol
+-mstack-align -mdata-align -mconst-align @gol
+-m32-bit -m16-bit -m8-bit -mno-prologue-epilogue -mno-gotplt @gol
+-melf -maout -melinux -mlinux -sim -sim2 @gol
+-mmul-bug-workaround -mno-mul-bug-workaround}
@emph{Darwin Options}
@gccoptlist{-all_load -allowable_client -arch -arch_errors_fatal @gol
-single_module -static -sub_library -sub_umbrella @gol
-twolevel_namespace -umbrella -undefined @gol
-unexported_symbols_list -weak_reference_mismatches @gol
--whatsloaded}
-
-@emph{MIPS Options}
-@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol
--mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips64 @gol
--mips16 -mno-mips16 -mabi=@var{abi} -mabicalls -mno-abicalls @gol
--mxgot -mno-xgot -membedded-pic -mno-embedded-pic @gol
--mgp32 -mgp64 -mfp32 -mfp64 -mhard-float -msoft-float @gol
--msingle-float -mdouble-float -mint64 -mlong64 -mlong32 @gol
--G@var{num} -membedded-data -mno-embedded-data @gol
--muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
--msplit-addresses -mno-split-addresses @gol
--mexplicit-relocs -mno-explicit-relocs @gol
--mrnames -mno-rnames @gol
--mcheck-zero-division -mno-check-zero-division @gol
--mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol
--mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol
--mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol
--mfix-vr4122-bugs -mno-fix-vr4122-bugs -mfix-sb1 -mno-fix-sb1 @gol
--mflush-func=@var{func} -mno-flush-func @gol
--mbranch-likely -mno-branch-likely}
-
-@emph{i386 and x86-64 Options}
-@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
--mfpmath=@var{unit} @gol
--masm=@var{dialect} -mno-fancy-math-387 @gol
--mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
--mno-wide-multiply -mrtd -malign-double @gol
--mpreferred-stack-boundary=@var{num} @gol
--mmmx -msse -msse2 -msse3 -m3dnow @gol
--mthreads -mno-align-stringops -minline-all-stringops @gol
--mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
--m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
--mno-red-zone -mno-tls-direct-seg-refs @gol
--mcmodel=@var{code-model} @gol
--m32 -m64}
-
-@emph{HPPA Options}
-@gccoptlist{-march=@var{architecture-type} @gol
--mbig-switch -mdisable-fpregs -mdisable-indexing @gol
--mfast-indirect-calls -mgas -mgnu-ld -mhp-ld @gol
--mjump-in-delay -mlinker-opt -mlong-calls @gol
--mlong-load-store -mno-big-switch -mno-disable-fpregs @gol
--mno-disable-indexing -mno-fast-indirect-calls -mno-gas @gol
--mno-jump-in-delay -mno-long-load-store @gol
--mno-portable-runtime -mno-soft-float @gol
--mno-space-regs -msoft-float -mpa-risc-1-0 @gol
--mpa-risc-1-1 -mpa-risc-2-0 -mportable-runtime @gol
--mschedule=@var{cpu-type} -mspace-regs -msio -mwsio @gol
--nolibdld -static -threads}
+-whatsloaded -F}
@emph{DEC Alpha Options}
@gccoptlist{-mno-fp-regs -msoft-float -malpha-as -mgas @gol
@emph{DEC Alpha/VMS Options}
@gccoptlist{-mvms-return-codes}
-@emph{H8/300 Options}
-@gccoptlist{-mrelax -mh -ms -mn -mint32 -malign-300}
-
-@emph{SH Options}
-@gccoptlist{-m1 -m2 -m2e -m3 -m3e @gol
--m4-nofpu -m4-single-only -m4-single -m4 @gol
--m5-64media -m5-64media-nofpu @gol
--m5-32media -m5-32media-nofpu @gol
--m5-compact -m5-compact-nofpu @gol
--mb -ml -mdalign -mrelax @gol
--mbigtable -mfmovd -mhitachi -mnomacsave @gol
--mieee -misize -mpadstruct -mspace @gol
--mprefergot -musermode}
-
-@emph{System V Options}
-@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
-
-@emph{ARC Options}
-@gccoptlist{-EB -EL @gol
--mmangle-cpu -mcpu=@var{cpu} -mtext=@var{text-section} @gol
--mdata=@var{data-section} -mrodata=@var{readonly-data-section}}
-
-@emph{TMS320C3x/C4x Options}
-@gccoptlist{-mcpu=@var{cpu} -mbig -msmall -mregparm -mmemparm @gol
--mfast-fix -mmpyi -mbk -mti -mdp-isr-reload @gol
--mrpts=@var{count} -mrptb -mdb -mloop-unsigned @gol
--mparallel-insns -mparallel-mpy -mpreserve-float}
-
-@emph{V850 Options}
-@gccoptlist{-mlong-calls -mno-long-calls -mep -mno-ep @gol
--mprolog-function -mno-prolog-function -mspace @gol
--mtda=@var{n} -msda=@var{n} -mzda=@var{n} @gol
--mapp-regs -mno-app-regs @gol
--mdisable-callt -mno-disable-callt @gol
--mv850e1 @gol
--mv850e @gol
--mv850 -mbig-switch}
-
-@emph{NS32K Options}
-@gccoptlist{-m32032 -m32332 -m32532 -m32081 -m32381 @gol
--mmult-add -mnomult-add -msoft-float -mrtd -mnortd @gol
--mregparam -mnoregparam -msb -mnosb @gol
--mbitfield -mnobitfield -mhimem -mnohimem}
-
-@emph{AVR Options}
-@gccoptlist{-mmcu=@var{mcu} -msize -minit-stack=@var{n} -mno-interrupts @gol
--mcall-prologues -mno-tablejump -mtiny-stack}
-
-@emph{MCore Options}
-@gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @gol
--mno-relax-immediates -mwide-bitfields -mno-wide-bitfields @gol
--m4byte-functions -mno-4byte-functions -mcallgraph-data @gol
--mno-callgraph-data -mslow-bytes -mno-slow-bytes -mno-lsim @gol
--mlittle-endian -mbig-endian -m210 -m340 -mstack-increment}
-
-@emph{MMIX Options}
-@gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @gol
--mabi=mmixware -mzero-extend -mknuthdiv -mtoplevel-symbols @gol
--melf -mbranch-predict -mno-branch-predict -mbase-addresses @gol
--mno-base-addresses -msingle-exit -mno-single-exit}
-
-@emph{IA-64 Options}
-@gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol
--mvolatile-asm-stop -mb-step -mregister-names -mno-sdata @gol
--mconstant-gp -mauto-pic -minline-float-divide-min-latency @gol
--minline-float-divide-max-throughput @gol
--minline-int-divide-min-latency @gol
--minline-int-divide-max-throughput -mno-dwarf2-asm @gol
--mfixed-range=@var{register-range}}
-
-@emph{S/390 and zSeries Options}
-@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
--mhard-float -msoft-float -mbackchain -mno-backchain @gol
--msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol
--m64 -m31 -mdebug -mno-debug -mesa -mzarch -mfused-madd -mno-fused-madd}
-
-@emph{CRIS Options}
-@gccoptlist{-mcpu=@var{cpu} -march=@var{cpu} -mtune=@var{cpu} @gol
--mmax-stack-frame=@var{n} -melinux-stacksize=@var{n} @gol
--metrax4 -metrax100 -mpdebug -mcc-init -mno-side-effects @gol
--mstack-align -mdata-align -mconst-align @gol
--m32-bit -m16-bit -m8-bit -mno-prologue-epilogue -mno-gotplt @gol
--melf -maout -melinux -mlinux -sim -sim2 @gol
--mmul-bug-workaround -mno-mul-bug-workaround}
-
-@emph{PDP-11 Options}
-@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
--mbcopy -mbcopy-builtin -mint32 -mno-int16 @gol
--mint16 -mno-int32 -mfloat32 -mno-float64 @gol
--mfloat64 -mno-float32 -mabshi -mno-abshi @gol
--mbranch-expensive -mbranch-cheap @gol
--msplit -mno-split -munix-asm -mdec-asm}
-
-@emph{Xstormy16 Options}
-@gccoptlist{-msim}
-
-@emph{Xtensa Options}
-@gccoptlist{-mconst16 -mno-const16 @gol
--mfused-madd -mno-fused-madd @gol
--mtext-section-literals -mno-text-section-literals @gol
--mtarget-align -mno-target-align @gol
--mlongcalls -mno-longcalls}
-
@emph{FRV Options}
@gccoptlist{-mgpr-32 -mgpr-64 -mfpr-32 -mfpr-64 @gol
-mhard-float -msoft-float @gol
-mno-nested-cond-exec -mtomcat-stats @gol
-mcpu=@var{cpu}}
-@item Code Generation Options
-@xref{Code Gen Options,,Options for Code Generation Conventions}.
-@gccoptlist{-fcall-saved-@var{reg} -fcall-used-@var{reg} @gol
--ffixed-@var{reg} -fexceptions @gol
--fnon-call-exceptions -funwind-tables @gol
--fasynchronous-unwind-tables @gol
--finhibit-size-directive -finstrument-functions @gol
--fno-common -fno-ident @gol
--fpcc-struct-return -fpic -fPIC -fpie -fPIE @gol
--freg-struct-return -fshared-data -fshort-enums @gol
--fshort-double -fshort-wchar @gol
--fverbose-asm -fpack-struct -fstack-check @gol
--fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol
--fargument-alias -fargument-noalias @gol
--fargument-noalias-global -fleading-underscore @gol
--ftls-model=@var{model} @gol
--ftrapv -fwrapv -fbounds-check}
-@end table
+@emph{H8/300 Options}
+@gccoptlist{-mrelax -mh -ms -mn -mint32 -malign-300}
+
+@emph{HPPA Options}
+@gccoptlist{-march=@var{architecture-type} @gol
+-mbig-switch -mdisable-fpregs -mdisable-indexing @gol
+-mfast-indirect-calls -mgas -mgnu-ld -mhp-ld @gol
+-mjump-in-delay -mlinker-opt -mlong-calls @gol
+-mlong-load-store -mno-big-switch -mno-disable-fpregs @gol
+-mno-disable-indexing -mno-fast-indirect-calls -mno-gas @gol
+-mno-jump-in-delay -mno-long-load-store @gol
+-mno-portable-runtime -mno-soft-float @gol
+-mno-space-regs -msoft-float -mpa-risc-1-0 @gol
+-mpa-risc-1-1 -mpa-risc-2-0 -mportable-runtime @gol
+-mschedule=@var{cpu-type} -mspace-regs -msio -mwsio @gol
+-nolibdld -static -threads}
+
+@emph{i386 and x86-64 Options}
+@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
+-mfpmath=@var{unit} @gol
+-masm=@var{dialect} -mno-fancy-math-387 @gol
+-mno-fp-ret-in-387 -msoft-float -msvr3-shlib @gol
+-mno-wide-multiply -mrtd -malign-double @gol
+-mpreferred-stack-boundary=@var{num} @gol
+-mmmx -msse -msse2 -msse3 -m3dnow @gol
+-mthreads -mno-align-stringops -minline-all-stringops @gol
+-mpush-args -maccumulate-outgoing-args -m128bit-long-double @gol
+-m96bit-long-double -mregparm=@var{num} -momit-leaf-frame-pointer @gol
+-mno-red-zone -mno-tls-direct-seg-refs @gol
+-mcmodel=@var{code-model} @gol
+-m32 -m64}
+
+@emph{IA-64 Options}
+@gccoptlist{-mbig-endian -mlittle-endian -mgnu-as -mgnu-ld -mno-pic @gol
+-mvolatile-asm-stop -mb-step -mregister-names -mno-sdata @gol
+-mconstant-gp -mauto-pic -minline-float-divide-min-latency @gol
+-minline-float-divide-max-throughput @gol
+-minline-int-divide-min-latency @gol
+-minline-int-divide-max-throughput -mno-dwarf2-asm @gol
+-mfixed-range=@var{register-range}}
+
+@emph{M32R/D Options}
+@gccoptlist{-m32r2 -m32rx -m32r @gol
+-mdebug @gol
+-malign-loops -mno-align-loops @gol
+-missue-rate=@var{number} @gol
+-mbranch-cost=@var{number} @gol
+-mmodel=@var{code-size-model-type} @gol
+-msdata=@var{sdata-type} @gol
+-mno-flush-func -mflush-func=@var{name} @gol
+-mno-flush-trap -mflush-trap=@var{number} @gol
+-G @var{num}}
+
+@emph{M680x0 Options}
+@gccoptlist{-m68000 -m68020 -m68020-40 -m68020-60 -m68030 -m68040 @gol
+-m68060 -mcpu32 -m5200 -m68881 -mbitfield -mc68000 -mc68020 @gol
+-mnobitfield -mrtd -mshort -msoft-float -mpcrel @gol
+-malign-int -mstrict-align -msep-data -mno-sep-data @gol
+-mshared-library-id=n -mid-shared-library -mno-id-shared-library}
+
+@emph{M68hc1x Options}
+@gccoptlist{-m6811 -m6812 -m68hc11 -m68hc12 -m68hcs12 @gol
+-mauto-incdec -minmax -mlong-calls -mshort @gol
+-msoft-reg-count=@var{count}}
+
+@emph{MCore Options}
+@gccoptlist{-mhardlit -mno-hardlit -mdiv -mno-div -mrelax-immediates @gol
+-mno-relax-immediates -mwide-bitfields -mno-wide-bitfields @gol
+-m4byte-functions -mno-4byte-functions -mcallgraph-data @gol
+-mno-callgraph-data -mslow-bytes -mno-slow-bytes -mno-lsim @gol
+-mlittle-endian -mbig-endian -m210 -m340 -mstack-increment}
+
+@emph{MIPS Options}
+@gccoptlist{-EL -EB -march=@var{arch} -mtune=@var{arch} @gol
+-mips1 -mips2 -mips3 -mips4 -mips32 -mips32r2 -mips64 @gol
+-mips16 -mno-mips16 -mabi=@var{abi} -mabicalls -mno-abicalls @gol
+-mxgot -mno-xgot -mgp32 -mgp64 -mfp32 -mfp64 @gol
+-mhard-float -msoft-float -msingle-float -mdouble-float @gol
+-mint64 -mlong64 -mlong32 @gol
+-G@var{num} -membedded-data -mno-embedded-data @gol
+-muninit-const-in-rodata -mno-uninit-const-in-rodata @gol
+-msplit-addresses -mno-split-addresses @gol
+-mexplicit-relocs -mno-explicit-relocs @gol
+-mrnames -mno-rnames @gol
+-mcheck-zero-division -mno-check-zero-division @gol
+-mmemcpy -mno-memcpy -mlong-calls -mno-long-calls @gol
+-mmad -mno-mad -mfused-madd -mno-fused-madd -nocpp @gol
+-mfix-r4000 -mno-fix-r4000 -mfix-r4400 -mno-fix-r4400 @gol
+-mfix-vr4120 -mno-fix-vr4120 -mfix-sb1 -mno-fix-sb1 @gol
+-mflush-func=@var{func} -mno-flush-func @gol
+-mbranch-likely -mno-branch-likely @gol
+-mfp-exceptions -mno-fp-exceptions @gol
+-mvr4130-align -mno-vr4130-align}
+
+@emph{MMIX Options}
+@gccoptlist{-mlibfuncs -mno-libfuncs -mepsilon -mno-epsilon -mabi=gnu @gol
+-mabi=mmixware -mzero-extend -mknuthdiv -mtoplevel-symbols @gol
+-melf -mbranch-predict -mno-branch-predict -mbase-addresses @gol
+-mno-base-addresses -msingle-exit -mno-single-exit}
+
+@emph{MN10300 Options}
+@gccoptlist{-mmult-bug -mno-mult-bug @gol
+-mam33 -mno-am33 @gol
+-mam33-2 -mno-am33-2 @gol
+-mno-crt0 -mrelax}
+
+@emph{NS32K Options}
+@gccoptlist{-m32032 -m32332 -m32532 -m32081 -m32381 @gol
+-mmult-add -mnomult-add -msoft-float -mrtd -mnortd @gol
+-mregparam -mnoregparam -msb -mnosb @gol
+-mbitfield -mnobitfield -mhimem -mnohimem}
+
+@emph{PDP-11 Options}
+@gccoptlist{-mfpu -msoft-float -mac0 -mno-ac0 -m40 -m45 -m10 @gol
+-mbcopy -mbcopy-builtin -mint32 -mno-int16 @gol
+-mint16 -mno-int32 -mfloat32 -mno-float64 @gol
+-mfloat64 -mno-float32 -mabshi -mno-abshi @gol
+-mbranch-expensive -mbranch-cheap @gol
+-msplit -mno-split -munix-asm -mdec-asm}
+
+@emph{PowerPC Options}
+See RS/6000 and PowerPC Options.
+
+@emph{RS/6000 and PowerPC Options}
+@gccoptlist{-mcpu=@var{cpu-type} @gol
+-mtune=@var{cpu-type} @gol
+-mpower -mno-power -mpower2 -mno-power2 @gol
+-mpowerpc -mpowerpc64 -mno-powerpc @gol
+-maltivec -mno-altivec @gol
+-mpowerpc-gpopt -mno-powerpc-gpopt @gol
+-mpowerpc-gfxopt -mno-powerpc-gfxopt @gol
+-mnew-mnemonics -mold-mnemonics @gol
+-mfull-toc -mminimal-toc -mno-fp-in-toc -mno-sum-in-toc @gol
+-m64 -m32 -mxl-call -mno-xl-call -mpe @gol
+-malign-power -malign-natural @gol
+-msoft-float -mhard-float -mmultiple -mno-multiple @gol
+-mstring -mno-string -mupdate -mno-update @gol
+-mfused-madd -mno-fused-madd -mbit-align -mno-bit-align @gol
+-mstrict-align -mno-strict-align -mrelocatable @gol
+-mno-relocatable -mrelocatable-lib -mno-relocatable-lib @gol
+-mtoc -mno-toc -mlittle -mlittle-endian -mbig -mbig-endian @gol
+-mdynamic-no-pic @gol
+-mprioritize-restricted-insns=@var{priority} @gol
+-msched-costly-dep=@var{dependence_type} @gol
+-minsert-sched-nops=@var{scheme} @gol
+-mcall-sysv -mcall-netbsd @gol
+-maix-struct-return -msvr4-struct-return @gol
+-mabi=altivec -mabi=no-altivec @gol
+-mabi=spe -mabi=no-spe @gol
+-misel=yes -misel=no @gol
+-mspe=yes -mspe=no @gol
+-mfloat-gprs=yes -mfloat-gprs=no @gol
+-mprototype -mno-prototype @gol
+-msim -mmvme -mads -myellowknife -memb -msdata @gol
+-msdata=@var{opt} -mvxworks -mwindiss -G @var{num} -pthread}
+
+@emph{S/390 and zSeries Options}
+@gccoptlist{-mtune=@var{cpu-type} -march=@var{cpu-type} @gol
+-mhard-float -msoft-float -mbackchain -mno-backchain @gol
+-msmall-exec -mno-small-exec -mmvcle -mno-mvcle @gol
+-m64 -m31 -mdebug -mno-debug -mesa -mzarch @gol
+-mtpf-trace -mno-tpf-trace -mfused-madd -mno-fused-madd}
+
+@emph{SH Options}
+@gccoptlist{-m1 -m2 -m2e -m3 -m3e @gol
+-m4-nofpu -m4-single-only -m4-single -m4 @gol
+-m5-64media -m5-64media-nofpu @gol
+-m5-32media -m5-32media-nofpu @gol
+-m5-compact -m5-compact-nofpu @gol
+-mb -ml -mdalign -mrelax @gol
+-mbigtable -mfmovd -mhitachi -mnomacsave @gol
+-mieee -misize -mpadstruct -mspace @gol
+-mprefergot -musermode}
+
+@emph{SPARC Options}
+@gccoptlist{-mcpu=@var{cpu-type} @gol
+-mtune=@var{cpu-type} @gol
+-mcmodel=@var{code-model} @gol
+-m32 -m64 -mapp-regs -mno-app-regs @gol
+-mfaster-structs -mno-faster-structs @gol
+-mfpu -mno-fpu -mhard-float -msoft-float @gol
+-mhard-quad-float -msoft-quad-float @gol
+-mimpure-text -mno-impure-text -mlittle-endian @gol
+-mstack-bias -mno-stack-bias @gol
+-munaligned-doubles -mno-unaligned-doubles @gol
+-mv8plus -mno-v8plus -mvis -mno-vis}
+
+@emph{System V Options}
+@gccoptlist{-Qy -Qn -YP,@var{paths} -Ym,@var{dir}}
+
+@emph{TMS320C3x/C4x Options}
+@gccoptlist{-mcpu=@var{cpu} -mbig -msmall -mregparm -mmemparm @gol
+-mfast-fix -mmpyi -mbk -mti -mdp-isr-reload @gol
+-mrpts=@var{count} -mrptb -mdb -mloop-unsigned @gol
+-mparallel-insns -mparallel-mpy -mpreserve-float}
+
+@emph{V850 Options}
+@gccoptlist{-mlong-calls -mno-long-calls -mep -mno-ep @gol
+-mprolog-function -mno-prolog-function -mspace @gol
+-mtda=@var{n} -msda=@var{n} -mzda=@var{n} @gol
+-mapp-regs -mno-app-regs @gol
+-mdisable-callt -mno-disable-callt @gol
+-mv850e1 @gol
+-mv850e @gol
+-mv850 -mbig-switch}
+
+@emph{VAX Options}
+@gccoptlist{-mg -mgnu -munix}
+
+@emph{x86-64 Options}
+See i386 and x86-64 Options.
+
+@emph{Xstormy16 Options}
+@gccoptlist{-msim}
+
+@emph{Xtensa Options}
+@gccoptlist{-mconst16 -mno-const16 @gol
+-mfused-madd -mno-fused-madd @gol
+-mtext-section-literals -mno-text-section-literals @gol
+-mtarget-align -mno-target-align @gol
+-mlongcalls -mno-longcalls}
+
+@emph{zSeries Options}
+See S/390 and zSeries Options.
+
+@item Code Generation Options
+@xref{Code Gen Options,,Options for Code Generation Conventions}.
+@gccoptlist{-fcall-saved-@var{reg} -fcall-used-@var{reg} @gol
+-ffixed-@var{reg} -fexceptions @gol
+-fnon-call-exceptions -funwind-tables @gol
+-fasynchronous-unwind-tables @gol
+-finhibit-size-directive -finstrument-functions @gol
+-fno-common -fno-ident @gol
+-fpcc-struct-return -fpic -fPIC -fpie -fPIE @gol
+-freg-struct-return -fshared-data -fshort-enums @gol
+-fshort-double -fshort-wchar @gol
+-fverbose-asm -fpack-struct -fstack-check @gol
+-fstack-limit-register=@var{reg} -fstack-limit-symbol=@var{sym} @gol
+-fargument-alias -fargument-noalias @gol
+-fargument-noalias-global -fleading-underscore @gol
+-ftls-model=@var{model} @gol
+-ftrapv -fwrapv -fbounds-check}
+@end table
@menu
* Overall Options:: Controlling the kind of output:
Fortran source code which must be preprocessed with a RATFOR
preprocessor (not included with GCC)@.
-@xref{Overall Options,,Options Controlling the Kind of Output, g77,
-Using and Porting GNU Fortran}, for more details of the handling of
-Fortran input files.
+@item @var{file}.f90
+@itemx @var{file}.f95
+Fortran 90/95 source code which should not be preprocessed.
@c FIXME: Descriptions of Java file types.
@c @var{file}.java
assembler assembler-with-cpp
ada
f77 f77-cpp-input ratfor
+f95
java
treelang
@end smallexample
sort of output is being produced, whether it be an executable file,
an object file, an assembler file or preprocessed C code.
-If you specify @option{-o} when compiling more than one input file, or
-you are producing an executable file as output, all the source files
-on the command line will be compiled at once.
-
-If @option{-o} is not specified, the default is to put an executable file
-in @file{a.out}, the object file for @file{@var{source}.@var{suffix}} in
-@file{@var{source}.o}, its assembler file in @file{@var{source}.s}, and
-all preprocessed C source on standard output.
+If @option{-o} is not specified, the default is to put an executable
+file in @file{a.out}, the object file for
+@file{@var{source}.@var{suffix}} in @file{@var{source}.o}, its
+assembler file in @file{@var{source}.s}, a precompiled header file in
+@file{@var{source}.@var{suffix}.gch}, and all preprocessed C source on
+standard output.
@item -v
@opindex v
the assembler is unable to read from a pipe; but the GNU assembler has
no trouble.
+@item -combine
+@opindex combine
+If you are compiling multiple source files, this option tells the driver
+to pass all the source files to the compiler at once (for those
+languages for which the compiler can handle this). This will allow
+intermodule analysis (IMA) to be performed by the compiler. Currently the only
+language for which this is supported is C. If you pass source files for
+multiple languages to the driver, using this option, the driver will invoke
+the compiler(s) that support IMA once each, passing each compiler all the
+source files appropriate for it. For those languages that do not support
+IMA this option will be ignored, and the compiler will be invoked once for
+each source file in that language. If you use this option in conjunction
+with -save-temps, the compiler will generate multiple pre-processed files
+(one for each source file), but only one (combined) .o or .s file.
+
@item --help
@opindex help
Print (on the standard output) a description of the command line options
@item -Wsign-promo @r{(C++ only)}
@opindex Wsign-promo
Warn when overload resolution chooses a promotion from unsigned or
-enumeral type to a signed type, over a conversion to an unsigned type of
+enumerated type to a signed type, over a conversion to an unsigned type of
the same size. Previous versions of G++ would try to preserve
unsignedness, but the standard mandates the current behavior.
used.
@item -fno-nil-receivers
-@opindex -fno-nil-receivers
+@opindex fno-nil-receivers
Assume that all Objective-C message dispatches (e.g.,
@code{[receiver message:arg]}) in this translation unit ensure that the receiver
is not @code{nil}. This allows for more efficient entry points in the runtime to be
the NeXT runtime on Mac OS X 10.3 and later.
@item -fobjc-exceptions
-@opindex -fobjc-exceptions
+@opindex fobjc-exceptions
Enable syntactic support for structured exception handling in Objective-C,
similar to what is offered by C++ and Java. Currently, this option is only
available in conjunction with the NeXT runtime on Mac OS X 10.3 and later.
to be unlocked properly.
@item -freplace-objc-classes
-@opindex -freplace-objc-classes
+@opindex freplace-objc-classes
Emit a special marker instructing @command{ld(1)} not to statically link in
the resulting object file, and allow @command{dyld(1)} to load it in at
run time instead. This is used in conjunction with the Fix-and-Continue
and later.
@item -fzero-link
-@opindex -fzero-link
+@opindex fzero-link
When compiling for the NeXT runtime, the compiler ordinarily replaces calls
to @code{objc_getClass("@dots{}")} (when the name of the class is known at
compile time) with static class references that get initialized at load time,
that methods and selectors must be declared before being used.
@item -print-objc-runtime-info
-@opindex -print-objc-runtime-info
+@opindex print-objc-runtime-info
Generate C header describing the largest structure that is passed by
value, if any.
Warn whenever a comment-start sequence @samp{/*} appears in a @samp{/*}
comment, or whenever a Backslash-Newline appears in a @samp{//} comment.
+@item -Wfatal-errors
+@opindex Wfatal-errors
+This option causes the compiler to abort compilation on the first error
+occurred rather than trying to keep going and printing further error
+messages.
+
@item -Wformat
@opindex Wformat
Check calls to @code{printf} and @code{scanf}, etc., to make sure that
int b[2][2] = @{ @{ 0, 1 @}, @{ 2, 3 @} @};
@end smallexample
+@item -Wmissing-include-dirs @r{(C, C++, and Objective-C only)}
+@opindex Wmissing-include-dirs
+Warn if a user-supplied include directory does not exist.
+
@item -Wparentheses
@opindex Wparentheses
Warn if parentheses are omitted in certain contexts, such
The C standard is worded confusingly, therefore there is some debate
over the precise meaning of the sequence point rules in subtle cases.
Links to discussions of the problem, including proposed formal
-definitions, may be found on our readings page, at
+definitions, may be found on the GCC readings page, at
@w{@uref{http://gcc.gnu.org/readings.html}}.
@item -Wreturn-type
@item -Wswitch
@opindex Wswitch
-Warn whenever a @code{switch} statement has an index of enumeral type
+Warn whenever a @code{switch} statement has an index of enumerated type
and lacks a @code{case} for one or more of the named codes of that
enumeration. (The presence of a @code{default} label prevents this
warning.) @code{case} labels outside the enumeration range also
@item -Wswitch-enum
@opindex Wswitch-enum
-Warn whenever a @code{switch} statement has an index of enumeral type
+Warn whenever a @code{switch} statement has an index of enumerated type
and lacks a @code{case} for one or more of the named codes of that
enumeration. @code{case} labels outside the enumeration range also
provoke warnings when this option is used.
instrumentation code can be added to the block; otherwise, a new basic
block must be created to hold the instrumentation code.
+@item -ftree-based-profiling
+@opindex ftree-based-profiling
+This option is used in addition to @option{-fprofile-arcs} or
+@option{-fbranch-probabilities} to control whether those optimizations
+are performed on a tree-based or rtl-based internal representation.
+If you use this option when compiling with @option{-fprofile-arcs},
+you must also use it when compiling later with @option{-fbranch-probabilities}.
+Currently the tree-based optimization is in an early stage of
+development, and this option is recommended only for those people
+working on improving it.
+
@need 2000
@item -ftest-coverage
@opindex ftest-coverage
Dump after computing branch probabilities, to @file{@var{file}.12.bp}.
@item B
@opindex dB
-Dump after block reordering, to @file{@var{file}.31.bbro}.
+Dump after block reordering, to @file{@var{file}.32.bbro}.
@item c
@opindex dc
Dump after instruction combination, to the file @file{@var{file}.20.combine}.
Also dump after the second if conversion, to the file @file{@var{file}.21.ce2}.
@item d
@opindex dd
-Dump after branch target load optimization, to to @file{@var{file}.32.btl}.
-Also dump after delayed branch scheduling, to @file{@var{file}.36.dbr}.
+Dump after branch target load optimization, to to @file{@var{file}.33.btl}.
+Also dump after delayed branch scheduling, to @file{@var{file}.37.dbr}.
@item D
@opindex dD
Dump all macro definitions, at the end of preprocessing, in addition to
normal output.
@item E
@opindex dE
-Dump after the third if conversion, to @file{@var{file}.30.ce3}.
+Dump after the third if conversion, to @file{@var{file}.31.ce3}.
@item f
@opindex df
Dump after control and data flow analysis, to @file{@var{file}.11.cfg}.
Also dump after life analysis, to @file{@var{file}.19.life}.
-@item F
-@opindex dF
-Dump after purging @code{ADDRESSOF} codes, to @file{@var{file}.07.addressof}.
@item g
@opindex dg
-Dump after global register allocation, to @file{@var{file}.25.greg}.
+Dump after global register allocation, to @file{@var{file}.26.greg}.
@item G
@opindex dG
Dump after GCSE, to @file{@var{file}.08.gcse}.
Dump after the first jump optimization, to @file{@var{file}.04.jump}.
@item k
@opindex dk
-Dump after conversion from registers to stack, to @file{@var{file}.34.stack}.
+Dump after conversion from registers to stack, to @file{@var{file}.35.stack}.
@item l
@opindex dl
-Dump after local register allocation, to @file{@var{file}.24.lreg}.
+Dump after local register allocation, to @file{@var{file}.25.lreg}.
@item L
@opindex dL
Dump after loop optimization passes, to @file{@var{file}.09.loop} and
@file{@var{file}.16.loop2}.
+@item m
+@opindex dm
+Dump after modulo scheduling, to @file{@var{file}.23.sms}.
@item M
@opindex dM
Dump after performing the machine dependent reorganization pass, to
-@file{@var{file}.35.mach}.
+@file{@var{file}.36.mach}.
@item n
@opindex dn
-Dump after register renumbering, to @file{@var{file}.29.rnreg}.
+Dump after register renumbering, to @file{@var{file}.30.rnreg}.
@item N
@opindex dN
Dump after the register move pass, to @file{@var{file}.22.regmove}.
@item o
@opindex do
-Dump after post-reload optimizations, to @file{@var{file}.26.postreload}.
+Dump after post-reload optimizations, to @file{@var{file}.27.postreload}.
@item r
@opindex dr
Dump after RTL generation, to @file{@var{file}.01.rtl}.
@item R
@opindex dR
-Dump after the second scheduling pass, to @file{@var{file}.33.sched2}.
+Dump after the second scheduling pass, to @file{@var{file}.34.sched2}.
@item s
@opindex ds
Dump after CSE (including the jump optimization that sometimes follows
CSE), to @file{@var{file}.06.cse}.
@item S
@opindex dS
-Dump after the first scheduling pass, to @file{@var{file}.23.sched}.
+Dump after the first scheduling pass, to @file{@var{file}.24.sched}.
@item t
@opindex dt
Dump after the second CSE pass (including the jump optimization that
Also dump after variable tracking, to @file{@var{file}.35.vartrack}.
@item w
@opindex dw
-Dump after the second flow pass, to @file{@var{file}.27.flow2}.
+Dump after the second flow pass, to @file{@var{file}.28.flow2}.
@item z
@opindex dz
-Dump after the peephole pass, to @file{@var{file}.28.peephole2}.
+Dump after the peephole pass, to @file{@var{file}.29.peephole2}.
@item Z
@opindex dZ
Dump after constructing the web, to @file{@var{file}.17.web}.
@var{options} controls the details of the dump as described for the
@option{-fdump-tree} options.
-@item -fdump-tree-@var{switch} @r{(C++ only)}
-@itemx -fdump-tree-@var{switch}-@var{options} @r{(C++ only)}
+@item -fdump-tree-@var{switch} @r{(C and C++ only)}
+@itemx -fdump-tree-@var{switch}-@var{options} @r{(C and C++ only)}
@opindex fdump-tree
Control the dumping at various stages of processing the intermediate
language tree to a file. The file name is generated by appending a switch
is for tying up a dump file with a debug environment.
@item slim
Inhibit dumping of members of a scope or body of a function merely
-because that scope has been reached. Only dump such items when they
-are directly reachable by some other path.
+because that scope has been reached. Only dump such items when they
+are directly reachable by some other path. When dumping pretty-printed
+trees, this option inhibits dumping the bodies of control structures.
+@item raw
+Print a raw representation of the tree. By default, trees are
+pretty-printed into a C-like representation.
+@item details
+Enable more detailed dumps (not honored by every dump option).
+@item stats
+Enable dumping various statistics about the pass (not honored by every dump
+option).
+@item blocks
+Enable showing basic block boundaries (disabled in raw dumps).
+@item vops
+Enable showing virtual operands for every statement.
+@item lineno
+Enable showing line numbers for statements.
+@item uid
+Enable showing the unique ID (@code{DECL_UID}) for each variable.
@item all
-Turn on all options.
+Turn on all options, except @option{raw}, @option{slim} and @option{lineno}.
@end table
The following tree dumps are possible:
@table @samp
+
@item original
Dump before any tree based optimization, to @file{@var{file}.original}.
+
@item optimized
Dump after all tree based optimization, to @file{@var{file}.optimized}.
+
@item inlined
Dump after function inlining, to @file{@var{file}.inlined}.
+
+@item gimple
+@opindex fdump-tree-gimple
+Dump each function before and after the gimplification pass to a file. The
+file name is made by appending @file{.gimple} to the source file name.
+
+@item cfg
+@opindex fdump-tree-cfg
+Dump the control flow graph of each function to a file. The file name is
+made by appending @file{.cfg} to the source file name.
+
+@item vcg
+@opindex fdump-tree-vcg
+Dump the control flow graph of each function to a file in VCG format. The
+file name is made by appending @file{.vcg} to the source file name. Note
+that if the file contains more than one function, the generated file cannot
+be used directly by VCG. You will need to cut and paste each function's
+graph into its own separate file first.
+
+@item ch
+@opindex fdump-tree-ch
+Dump each function after copying loop headers. The file name is made by
+appending @file{.ch} to the source file name.
+
+@item ssa
+@opindex fdump-tree-ssa
+Dump SSA related information to a file. The file name is made by appending
+@file{.ssa} to the source file name.
+
+@item alias
+@opindex fdump-tree-alias
+Dump aliasing information for each function. The file name is made by
+appending @file{.alias} to the source file name.
+
+@item ccp
+@opindex fdump-tree-ccp
+Dump each function after CCP. The file name is made by appending
+@file{.ccp} to the source file name.
+
+@item pre
+@opindex fdump-tree-pre
+Dump trees after partial redundancy elimination. The file name is made
+by appending @file{.pre} to the source file name.
+
+@item fre
+@opindex fdump-tree-fre
+Dump trees after full redundancy elimination. The file name is made
+by appending @file{.fre} to the source file name.
+
+@item dce
+@opindex fdump-tree-dce
+Dump each function after dead code elimination. The file name is made by
+appending @file{.dce} to the source file name.
+
+@item mudflap
+@opindex fdump-tree-mudflap
+Dump each function after adding mudflap instrumentation. The file name is
+made by appending @file{.mudflap} to the source file name.
+
+@item sra
+@opindex fdump-tree-sra
+Dump each function after performing scalar replacement of aggregates. The
+file name is made by appending @file{.sra} to the source file name.
+
+@item dom
+@opindex fdump-tree-dom
+Dump each function after applying dominator tree optimizations. The file
+name is made by appending @file{.dom} to the source file name.
+
+@item dse
+@opindex fdump-tree-dse
+Dump each function after applying dead store elimination. The file
+name is made by appending @file{.dse} to the source file name.
+
+@item phiopt
+@opindex fdump-tree-phiopt
+Dump each function after optimizing PHI nodes into straightline code. The file
+name is made by appending @file{.phiopt} to the source file name.
+
+@item forwprop
+@opindex fdump-tree-forwprop
+Dump each function after forward propagating single use variables. The file
+name is made by appending @file{.forwprop} to the source file name.
+
+@item copyrename
+@opindex fdump-tree-copyrename
+Dump each function after applying the copy rename optimization. The file
+name is made by appending @file{.copyrename} to the source file name.
+
+@item nrv
+@opindex fdump-tree-nrv
+Dump each function after applying the named return value optimization on
+generic trees. The file name is made by appending @file{.nrv} to the source
+file name.
+
+@item all
+@opindex fdump-tree-all
+Enable all the available tree dumps with the flags provided in this option.
@end table
@item -frandom-seed=@var{string}
and possibly the ability to debug the program.
The compiler performs optimization based on the knowledge it has of
-the program. Using the @option{-funit-at-a-time} flag will allow the
-compiler to consider information gained from later functions in the
-file when compiling a function. Compiling multiple files at once to a
-single output file (and using @option{-funit-at-a-time}) will allow
+the program. Optimization levels @option{-O2} and above, in
+particular, enable @emph{unit-at-a-time} mode, which allows the
+compiler to consider information gained from later functions in
+the file when compiling a function. Compiling multiple files at
+once to a single output file in @emph{unit-at-a-time} mode allows
the compiler to use information gained from all of the files when
compiling each of them.
@opindex O3
Optimize yet more. @option{-O3} turns on all optimizations specified by
@option{-O2} and also turns on the @option{-finline-functions},
-@option{-fweb} and @option{-frename-registers} options.
+@option{-fweb}, @option{-frename-registers}
+and @option{-fgcse-after-reload} options.
@item -O0
@opindex O0
@option{-Os} disables the following optimization flags:
@gccoptlist{-falign-functions -falign-jumps -falign-loops @gol
--falign-labels -freorder-blocks -fprefetch-loop-arrays}
+-falign-labels -freorder-blocks -freorder-blocks-and-partition -fprefetch-loop-arrays}
If you use multiple @option{-O} options, with or without level numbers,
the last such option is the one that is effective.
have distinct location, so using this option will result in non-conforming
behavior.
+@item -fmodulo-sched
+@opindex fmodulo-sched
+Perform swing modulo scheduling immediately before the first scheduling
+pass. This pass looks at innermost loops and reorders their
+instructions by overlapping different iterations.
+
@item -fnew-ra
@opindex fnew-ra
Use a graph coloring register allocator. Currently this option is meant
The default is @option{-fzero-initialized-in-bss}.
+@item -fbounds-check
+@opindex fbounds-check
+For front-ends that support it, generate additional code to check that
+indices used to access arrays are within the declared range. This is
+currently only supported by the Java and Fortran front-ends, where
+this option defaults to true and false respectively.
+
+@item -fmudflap -fmudflapth -fmudflapir
+@opindex fmudflap
+@opindex fmudflapth
+@opindex fmudflapir
+@cindex bounds checking
+@cindex mudflap
+For front-ends that support it (C and C++), instrument all risky
+pointer/array dereferencing operations, some standard library
+string/heap functions, and some other associated constructs with
+range/validity tests. Modules so instrumented should be immune to
+buffer overflows, invalid heap use, and some other classes of C/C++
+programming errors. The instrumentation relies on a separate runtime
+library (@file{libmudflap}), which will be linked into a program if
+@option{-fmudflap} is given at link time. Run-time behavior of the
+instrumented program is controlled by the @env{MUDFLAP_OPTIONS}
+environment variable. See @code{env MUDFLAP_OPTIONS=-help a.out}
+for its options.
+
+Use @option{-fmudflapth} instead of @option{-fmudflap} to compile and to
+link if your program is multi-threaded. Use @option{-fmudflapir}, in
+addition to @option{-fmudflap} or @option{-fmudflapth}, if
+instrumentation should ignore pointer reads. This produces less
+instrumentation (and therefore faster execution) and still provides
+some protection against outright memory corrupting writes, but allows
+erroneously read data to propagate within a program.
+
@item -fstrength-reduce
@opindex fstrength-reduce
Perform the optimizations of loop strength reduction and
Enabled by default when gcse is enabled.
+@item -fgcse-after-reload
+@opindex fgcse-after-reload
+When @option{-fgcse-after-reload} is enabled, a redundant load elimination
+pass is performed after reload. The purpose of this pass is to cleanup
+redundant spilling.
+
@item -floop-optimize
@opindex floop-optimize
Perform loop optimizations: move constant expressions out of loops, simplify
Enabled at levels @option{-O}, @option{-O2}, @option{-O3}, @option{-Os}.
+@item -floop-optimize2
+@opindex floop-optimize2
+Perform loop optimizations using the new loop optimizer. The optimizations
+(loop unrolling, peeling and unswitching, loop invariant motion) are enabled
+by separate flags.
+
@item -fcrossjumping
@opindex crossjumping
Perform cross-jumping transformation. This transformation unifies equivalent code and save code size. The
Enabled at levels @option{-O2}, @option{-O3}, @option{-Os}.
-@item -fmove-all-movables
-@opindex fmove-all-movables
-Forces all invariant computations in loops to be moved
-outside the loop.
+@item -ftree-pre
+Perform Partial Redundancy Elimination (PRE) on trees. This flag is
+enabled by default at -O and higher.
+
+@item -ftree-fre
+Perform Full Redundancy Elimination (FRE) on trees. The difference
+between FRE and PRE is that FRE only considers expressions
+that are computed on all paths leading to the redundant computation.
+This analysis faster than PRE, though it exposes fewer redundancies.
+This flag is enabled by default at -O and higher.
+
+@item -ftree-ccp
+Perform sparse conditional constant propagation (CCP) on trees. This flag
+is enabled by default at -O and higher.
+
+@item -ftree-dce
+Perform dead code elimination (DCE) on trees. This flag is enabled by
+default at -O and higher.
+
+@item -ftree-dominator-opts
+Perform dead code elimination (DCE) on trees. This flag is enabled by
+default at -O and higher.
+
+@item -ftree-ch
+Perform loop header copying on trees. This is beneficial since it increases
+effectivity of code motion optimizations. It also saves one jump. This flag
+is enabled by default at -O and higher. It is not enabled for -Os, since it
+usually increases code size.
+
+@item -ftree-loop-optimize
+Perform loop optimizations on trees. This flag is enabled by default at -O
+and higher.
+
+@item -ftree-sra
+Perform scalar replacement of aggregates. This pass replaces structure
+references with scalars to prevent committing structures to memory too
+early. This flag is enabled by default at -O and higher.
+
+@item -ftree-copyrename
+Perform copy renaming on trees. This pass attempts to rename compiler
+temporaries to other variables at copy locations, usually resulting in
+variable names which more closely resemble the original variables. This flag
+is enabled by default at -O and higher.
+
+@item -ftree-ter
+Perform temporary expression replacement during the SSA->normal phase. Single
+use/single def temporaries are replaced at their use location with their
+defining expression. This results in non-GIMPLE code, but gives the expanders
+much more complex trees to work on resulting in better RTL generation. This is
+enabled by default at -O and higher.
+
+@item -ftree-lrs
+Perform live range splitting during the SSA->normal phase. Distinct live
+ranges of a variable are split into unique variables, allowing for better
+optimization later. This is enabled by default at -O and higher.
-@item -freduce-all-givs
+@item -ftracer
+@opindex ftracer
+Perform tail duplication to enlarge superblock size. This transformation
+simplifies the control flow of the function allowing other optimizations to do
+better job.
+
+@item -funroll-loops
+@opindex funroll-loops
+Unroll loops whose number of iterations can be determined at compile
+time or upon entry to the loop. @option{-funroll-loops} implies both
+@option{-fstrength-reduce} and @option{-frerun-cse-after-loop}. This
+option makes code larger, and may or may not make it run faster.
+
+@item -funroll-all-loops
+@opindex funroll-all-loops
+Unroll all loops, even if their number of iterations is uncertain when
+the loop is entered. This usually makes programs run more slowly.
+@option{-funroll-all-loops} implies the same options as
+@option{-funroll-loops},
+
+@item -fprefetch-loop-arrays
+@opindex fprefetch-loop-arrays
+If supported by the target machine, generate instructions to prefetch
+memory to improve the performance of loops that access large arrays.
+
+@item -fmove-all-movables
+@opindex fmove-all-movables
+Forces all invariant computations in loops to be moved
+outside the loop.
+
+@item -freduce-all-givs
@opindex freduce-all-givs
Forces all general-induction variables in loops to be
strength-reduced.
they have helped determine the efficacy of various
approaches to improving loop optimizations.
-Please let us (@w{@email{gcc@@gcc.gnu.org}} and @w{@email{fortran@@gnu.org}})
-know how use of these options affects
-the performance of your production code.
-We're very interested in code that runs @emph{slower}
-when these options are @emph{enabled}.
+Please contact @w{@email{gcc@@gcc.gnu.org}}, and describe how use of
+these options affects the performance of your production code.
+Examples of code that runs @emph{slower} when these options are
+@emph{enabled} are very valuable.
@item -fno-peephole
@itemx -fno-peephole2
Enabled at levels @option{-O2}, @option{-O3}.
+@item -freorder-blocks-and-partition
+@opindex freorder-blocks-and-partition
+In addition to reordering basic blocks in the compiled function, in order
+to reduce number of taken branches, partitions hot and cold basic blocks
+into separate sections of the assembly and .o files, to improve
+paging and cache locality performance.
+
@item -freorder-functions
@opindex freorder-functions
Reorder basic blocks in the compiled function in order to reduce number of
taken branches and improve code locality. This is implemented by using special
-subsections @code{text.hot} for most frequently executed functions and
-@code{text.unlikely} for unlikely executed functions. Reordering is done by
+subsections @code{.text.hot} for most frequently executed functions and
+@code{.text.unlikely} for unlikely executed functions. Reordering is done by
the linker so object file format must support named sections and linker must
place them in a reasonable way.
Enabled at levels @option{-O2}, @option{-O3}.
-@item -frename-registers
-@opindex frename-registers
-Attempt to avoid false dependencies in scheduled code by making use
-of registers left over after register allocation. This optimization
-will most benefit processors with lots of registers. It can, however,
-make debugging impossible, since variables will no longer stay in
-a ``home register''.
+@item -funit-at-a-time
+@opindex funit-at-a-time
+Parse the whole compilation unit before starting to produce code.
+This allows some extra optimizations to take place but consumes
+more memory (in general). There are some compatibility issues
+with @emph{unit-at-at-time} mode:
+@itemize @bullet
+@item
+enabling @emph{unit-at-a-time} mode may change the order
+in which functions, variables, and top-level @code{asm} statements
+are emitted, and will likely break code relying on some particular
+ordering. The majority of such top-level @code{asm} statements,
+though, can be replaced by @code{section} attributes.
+
+@item
+@emph{unit-at-a-time} mode removes unreferenced static variables
+and functions are removed. This may result in undefined references
+when an @code{asm} statement refers directly to variables or functions
+that are otherwise unused. In that case either the variable/function
+shall be listed as an operand of the @code{asm} statement operand or,
+in the case of top-level @code{asm} statements the attribute @code{used}
+shall be used on the declaration.
+
+@item
+Static functions now can use non-standard passing conventions that
+may break @code{asm} statements calling functions directly. Again,
+attribute @code{used} will prevent this behavior.
+@end itemize
+
+As a temporary workaround, @option{-fno-unit-at-a-time} can be used,
+but this scheme may not be supported by future releases of GCC.
+
+Enabled at levels @option{-O2}, @option{-O3}.
@item -fweb
@opindex fweb
Constructs webs as commonly used for register allocation purposes and assign
-each web individual pseudo register. This allows our register allocation pass
+each web individual pseudo register. This allows the register allocation pass
to operate on pseudos directly, but also strengthens several other optimization
passes, such as CSE, loop optimizer and trivial dead code remover. It can,
however, make debugging impossible, since variables will no longer stay in a
``home register''.
-Enabled at levels @option{-O3}.
+Enabled at levels @option{-O2}, @option{-O3}, @option{-Os},
+on targets where the default format for debugging information supports
+variable tracking.
@item -fno-cprop-registers
@opindex fno-cprop-registers
@item -fprofile-generate
@opindex fprofile-generate
-Enable options usually used for instrumenting application to produce profile usefull
-for later recompilation profile feedback based optimization.
-The following options are enabled: @code{-fprofile-arcs}, @code{-fprofile-values}, @code{-fvpt}
+Enable options usually used for instrumenting application to produce
+profile useful for later recompilation with profile feedback based
+optimization. You must use @code{-fprofile-generate} both when
+compiling and when linking your program.
+
+The following options are enabled: @code{-fprofile-arcs}, @code{-fprofile-values}, @code{-fvpt}.
@item -fprofile-use
@opindex fprofile-use
from profiling values of expressions and adds @samp{REG_VALUE_PROFILE}
notes to instructions for their later usage in optimizations.
+Enabled with @option{-fprofile-generate} and @option{-fprofile-use}.
+
@item -fvpt
@opindex fvpt
If combined with @option{-fprofile-arcs}, it instructs the compiler to add
Currently the optimizations include specialization of division operation
using the knowledge about the value of the denominator.
+Enabled with @option{-fprofile-generate} and @option{-fprofile-use}.
+
+@item -frename-registers
+@opindex frename-registers
+Attempt to avoid false dependencies in scheduled code by making use
+of registers left over after register allocation. This optimization
+will most benefit processors with lots of registers. Depending on the
+debug information format adopted by the target, however, it can
+make debugging impossible, since variables will no longer stay in
+a ``home register''.
+
+Not enabled by default at any level because it has known bugs.
+
@item -fnew-ra
@opindex fnew-ra
Use a graph coloring register allocator. Currently this option is meant
simplifies the control flow of the function allowing other optimizations to do
better job.
-@item -funit-at-a-time
-@opindex funit-at-a-time
-Parse the whole compilation unit before starting to produce code.
-This allows some extra optimizations to take place but consumes more
-memory.
+Enabled with @option{-fprofile-use}.
@item -funroll-loops
@opindex funroll-loops
(i.e. complete removal of loops with small constant number of iterations).
This option makes code larger, and may or may not make it run faster.
+Enabled with @option{-fprofile-use}.
+
@item -funroll-all-loops
@opindex funroll-all-loops
Unroll all loops, even if their number of iterations is uncertain when
roll much (from profile feedback). It also turns on complete loop peeling
(i.e. complete removal of loops with small constant number of iterations).
+Enabled with @option{-fprofile-use}.
+
+@item -fmove-loop-invariants
+@opindex fmove-loop-invariants
+Enables the loop invariant motion pass in the new loop optimizer. Enabled
+at level @option{-O1}
+
@item -funswitch-loops
@opindex funswitch-loops
Move branches with loop invariant conditions out of the loop, with duplicates
@option{-fold-unroll-all-loops} implies the same options as
@option{-fold-unroll-loops}.
-@item -funswitch-loops
-@opindex funswitch-loops
-Move branches with loop invariant conditions out of the loop, with duplicates
-of the loop on both branches (modified according to result of the condition).
-
-@item -funswitch-loops
-@opindex funswitch-loops
-Move branches with loop invariant conditions out of the loop, with duplicates
-of the loop on both branches (modified according to result of the condition).
-
@item -fprefetch-loop-arrays
@opindex fprefetch-loop-arrays
If supported by the target machine, generate instructions to prefetch
@item -fbtr-bb-exclusive
@opindex fbtr-bb-exclusive
-WHen performing branch target register load optimization, don't reuse
+When performing branch target register load optimization, don't reuse
branch target registers in within any basic block.
@item --param @var{name}=@var{value}
optimization will not be done.
@item max-gcse-passes
-The maximum number of passes of GCSE to run.
+The maximum number of passes of GCSE to run. The default is 1.
@item max-pending-list-length
The maximum number of pending dependencies scheduling will allow
This parameter is ignored when @option{-funit-at-a-time} is not used.
The default value is 150.
+@item max-inline-insns-recursive
+@itemx max-inline-insns-recursive-auto
+Specifies maximum number of instructions out-of-line copy of self recursive inline
+function can grow into by performing recursive inlining.
+
+For functions declared inline @option{--param max-inline-insns-recursive} is
+taken into acount. For function not declared inline, recursive inlining
+happens only when @option{-finline-functions} (included in @option{-O3}) is
+enabled and @option{--param max-inline-insns-recursive-auto} is used. The
+default value is 500.
+
+@item max-inline-recursive-depth
+@itemx max-inline-recursive-depth-auto
+Specifies maximum recursion depth used by the recursive inlining.
+
+For functions declared inline @option{--param max-inline-recursive-depth} is
+taken into acount. For function not declared inline, recursive inlining
+happens only when @option{-finline-functions} (included in @option{-O3}) is
+enabled and @option{--param max-inline-recursive-depth-auto} is used. The
+default value is 500.
+
@item max-inline-insns-rtl
For languages that use the RTL inliner (this happens at a later stage
than tree inlining), you can set the maximum allowable size (counted
@item max-cse-path-length
-Maximum number of basic blocks on path that cse considers.
+Maximum number of basic blocks on path that cse considers. The default is 10.
+
+@item global-var-threshold
+
+Counts the number of function calls (N) and the number of
+call-clobbered variables (V). If NxV is larger than this limit, a
+single artificial variable will be created to represent all the
+call-clobbered variables at function call sites. This artificial
+variable will then be made to alias every call-clobbered variable.
+(done as int * size_t on the host machine; beware overflow).
+
+@item max-aliased-vops
+
+Maxiumum number of virtual operands allowed to represent aliases
+before triggering the alias grouping heuristic. Alias grouping
+reduces compile times and memory consumption needed for aliasing at
+the expense of precision loss in alias information.
@item ggc-min-expand
Do not use the standard system libraries when linking.
Only the libraries you specify will be passed to the linker.
The standard startup files are used normally, unless @option{-nostartfiles}
-is used. The compiler may generate calls to memcmp, memset, and memcpy
-for System V (and ISO C) environments or to bcopy and bzero for
-BSD environments. These entries are usually resolved by entries in
+is used. The compiler may generate calls to @code{memcmp},
+@code{memset}, @code{memcpy} and @code{memmove}.
+These entries are usually resolved by entries in
libc. These entry points should be supplied through some other
mechanism when this option is specified.
@opindex nostdlib
Do not use the standard system startup files or libraries when linking.
No startup files and only the libraries you specify will be passed to
-the linker. The compiler may generate calls to memcmp, memset, and memcpy
-for System V (and ISO C) environments or to bcopy and bzero for
-BSD environments. These entries are usually resolved by entries in
+the linker. The compiler may generate calls to @code{memcmp}, @code{memset},
+@code{memcpy} and @code{memmove}.
+These entries are usually resolved by entries in
libc. These entry points should be supplied through some other
mechanism when this option is specified.
If, instead, you use the GCC driver to create shared libraries, you may
find that they will not always be linked with the shared @file{libgcc}.
-If GCC finds, at its configuration time, that you have a GNU linker that
-does not support option @option{--eh-frame-hdr}, it will link the shared
-version of @file{libgcc} into shared libraries by default. Otherwise,
-it will take advantage of the linker and optimize away the linking with
-the shared version of @file{libgcc}, linking with the static version of
-libgcc by default. This allows exceptions to propagate through such
-shared libraries, without incurring relocation costs at library load
-time.
+If GCC finds, at its configuration time, that you have a non-GNU linker
+or a GNU linker that does not support option @option{--eh-frame-hdr},
+it will link the shared version of @file{libgcc} into shared libraries
+by default. Otherwise, it will take advantage of the linker and optimize
+away the linking with the shared version of @file{libgcc}, linking with
+the static version of libgcc by default. This allows exceptions to
+propagate through such shared libraries, without incurring relocation
+costs at library load time.
However, if a library or main executable is supposed to throw or catch
exceptions, you must link it using the G++ or GCJ driver, as appropriate
If you really need to change the search order for system directories,
use the @option{-nostdinc} and/or @option{-isystem} options.
-@item -I-
-@opindex I-
-Any directories you specify with @option{-I} options before the @option{-I-}
-option are searched only for the case of @samp{#include "@var{file}"};
-they are not searched for @samp{#include <@var{file}>}.
-
-If additional directories are specified with @option{-I} options after
-the @option{-I-}, these directories are searched for all @samp{#include}
-directives. (Ordinarily @emph{all} @option{-I} directories are used
-this way.)
-
-In addition, the @option{-I-} option inhibits the use of the current
-directory (where the current input file came from) as the first search
-directory for @samp{#include "@var{file}"}. There is no way to
-override this effect of @option{-I-}. With @option{-I.} you can specify
-searching the directory which was current when the compiler was
-invoked. That is not exactly the same as what the preprocessor does
-by default, but it is often satisfactory.
-
-@option{-I-} does not inhibit the use of the standard system directories
-for header files. Thus, @option{-I-} and @option{-nostdinc} are
-independent.
+@item -iquote@var{dir}
+@opindex iquote
+Add the directory @var{dir} to the head of the list of directories to
+be searched for header files only for the case of @samp{#include
+"@var{file}"}; they are not searched for @samp{#include <@var{file}>},
+otherwise just like @option{-I}.
@item -L@var{dir}
@opindex L
@file{cc1plus}, @file{as}, @file{ld}, etc. More than one
@option{-specs=@var{file}} can be specified on the command line, and they
are processed in order, from left to right.
+
+@item -I-
+@opindex I-
+This option has been deprecated. Please use @option{-iquote} instead for
+@option{-I} directories before the @option{-I-} and remove the @option{-I-}.
+Any directories you specify with @option{-I} options before the @option{-I-}
+option are searched only for the case of @samp{#include "@var{file}"};
+they are not searched for @samp{#include <@var{file}>}.
+
+If additional directories are specified with @option{-I} options after
+the @option{-I-}, these directories are searched for all @samp{#include}
+directives. (Ordinarily @emph{all} @option{-I} directories are used
+this way.)
+
+In addition, the @option{-I-} option inhibits the use of the current
+directory (where the current input file came from) as the first search
+directory for @samp{#include "@var{file}"}. There is no way to
+override this effect of @option{-I-}. With @option{-I.} you can specify
+searching the directory which was current when the compiler was
+invoked. That is not exactly the same as what the preprocessor does
+by default, but it is often satisfactory.
+
+@option{-I-} does not inhibit the use of the standard system directories
+for header files. Thus, @option{-I-} and @option{-nostdinc} are
+independent.
@end table
@c man end
Process the @code{cpp} spec. This is used to construct the arguments
to be passed to the C preprocessor.
-@item %c
-Process the @code{signed_char} spec. This is intended to be used
-to tell cpp whether a char is signed. It typically has the definition:
-@smallexample
-%@{funsigned-char:-D__CHAR_UNSIGNED__@}
-@end smallexample
-
@item %1
Process the @code{cc1} spec. This is used to construct the options to be
passed to the actual C compiler (@samp{cc1}).
machine description. The default for the options is also defined by
that macro, which enables you to change the defaults.
+@c This list is ordered alphanumerically by subsection name.
+@c It should be the same order and spelling as these options are listed
+@c in Machine Dependent Options
+
@menu
-* M680x0 Options::
-* M68hc1x Options::
-* VAX Options::
-* SPARC Options::
+* ARC Options::
* ARM Options::
-* MN10300 Options::
-* M32R/D Options::
-* RS/6000 and PowerPC Options::
+* AVR Options::
+* CRIS Options::
* Darwin Options::
-* MIPS Options::
-* i386 and x86-64 Options::
-* HPPA Options::
* DEC Alpha Options::
* DEC Alpha/VMS Options::
+* FRV Options::
* H8/300 Options::
+* HPPA Options::
+* i386 and x86-64 Options::
+* IA-64 Options::
+* M32R/D Options::
+* M680x0 Options::
+* M68hc1x Options::
+* MCore Options::
+* MIPS Options::
+* MMIX Options::
+* MN10300 Options::
+* NS32K Options::
+* PDP-11 Options::
+* PowerPC Options::
+* RS/6000 and PowerPC Options::
+* S/390 and zSeries Options::
* SH Options::
+* SPARC Options::
* System V Options::
* TMS320C3x/C4x Options::
* V850 Options::
-* ARC Options::
-* NS32K Options::
-* AVR Options::
-* MCore Options::
-* IA-64 Options::
-* S/390 and zSeries Options::
-* CRIS Options::
-* MMIX Options::
-* PDP-11 Options::
+* VAX Options::
+* x86-64 Options::
* Xstormy16 Options::
* Xtensa Options::
-* FRV Options::
+* zSeries Options::
@end menu
-@node M680x0 Options
-@subsection M680x0 Options
-@cindex M680x0 options
+@node ARC Options
+@subsection ARC Options
+@cindex ARC Options
-These are the @samp{-m} options defined for the 68000 series. The default
-values for these options depends on which style of 68000 was selected when
-the compiler was configured; the defaults for the most common choices are
-given below.
+These options are defined for ARC implementations:
@table @gcctabopt
-@item -m68000
-@itemx -mc68000
-@opindex m68000
-@opindex mc68000
-Generate output for a 68000. This is the default
-when the compiler is configured for 68000-based systems.
-
-Use this option for microcontrollers with a 68000 or EC000 core,
-including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
+@item -EL
+@opindex EL
+Compile code for little endian mode. This is the default.
-@item -m68020
-@itemx -mc68020
-@opindex m68020
-@opindex mc68020
-Generate output for a 68020. This is the default
-when the compiler is configured for 68020-based systems.
+@item -EB
+@opindex EB
+Compile code for big endian mode.
-@item -m68881
-@opindex m68881
-Generate output containing 68881 instructions for floating point.
-This is the default for most 68020 systems unless @option{--nfp} was
-specified when the compiler was configured.
+@item -mmangle-cpu
+@opindex mmangle-cpu
+Prepend the name of the cpu to all public symbol names.
+In multiple-processor systems, there are many ARC variants with different
+instruction and register set characteristics. This flag prevents code
+compiled for one cpu to be linked with code compiled for another.
+No facility exists for handling variants that are ``almost identical''.
+This is an all or nothing option.
-@item -m68030
-@opindex m68030
-Generate output for a 68030. This is the default when the compiler is
-configured for 68030-based systems.
+@item -mcpu=@var{cpu}
+@opindex mcpu
+Compile code for ARC variant @var{cpu}.
+Which variants are supported depend on the configuration.
+All variants support @option{-mcpu=base}, this is the default.
-@item -m68040
-@opindex m68040
-Generate output for a 68040. This is the default when the compiler is
-configured for 68040-based systems.
+@item -mtext=@var{text-section}
+@itemx -mdata=@var{data-section}
+@itemx -mrodata=@var{readonly-data-section}
+@opindex mtext
+@opindex mdata
+@opindex mrodata
+Put functions, data, and readonly data in @var{text-section},
+@var{data-section}, and @var{readonly-data-section} respectively
+by default. This can be overridden with the @code{section} attribute.
+@xref{Variable Attributes}.
-This option inhibits the use of 68881/68882 instructions that have to be
-emulated by software on the 68040. Use this option if your 68040 does not
-have code to emulate those instructions.
+@end table
-@item -m68060
-@opindex m68060
-Generate output for a 68060. This is the default when the compiler is
-configured for 68060-based systems.
+@node ARM Options
+@subsection ARM Options
+@cindex ARM options
-This option inhibits the use of 68020 and 68881/68882 instructions that
-have to be emulated by software on the 68060. Use this option if your 68060
-does not have code to emulate those instructions.
+These @samp{-m} options are defined for Advanced RISC Machines (ARM)
+architectures:
-@item -mcpu32
-@opindex mcpu32
-Generate output for a CPU32. This is the default
-when the compiler is configured for CPU32-based systems.
+@table @gcctabopt
+@item -mabi=@var{name}
+@opindex mabi
+Generate code for the specified ABI. Permissible values are: @samp{apcs-gnu},
+@samp{atpcs}, @samp{aapcs} and @samp{iwmmxt}.
-Use this option for microcontrollers with a
-CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334,
-68336, 68340, 68341, 68349 and 68360.
+@item -mapcs-frame
+@opindex mapcs-frame
+Generate a stack frame that is compliant with the ARM Procedure Call
+Standard for all functions, even if this is not strictly necessary for
+correct execution of the code. Specifying @option{-fomit-frame-pointer}
+with this option will cause the stack frames not to be generated for
+leaf functions. The default is @option{-mno-apcs-frame}.
-@item -m5200
-@opindex m5200
-Generate output for a 520X ``coldfire'' family cpu. This is the default
-when the compiler is configured for 520X-based systems.
+@item -mapcs
+@opindex mapcs
+This is a synonym for @option{-mapcs-frame}.
-Use this option for microcontroller with a 5200 core, including
-the MCF5202, MCF5203, MCF5204 and MCF5202.
+@ignore
+@c not currently implemented
+@item -mapcs-stack-check
+@opindex mapcs-stack-check
+Generate code to check the amount of stack space available upon entry to
+every function (that actually uses some stack space). If there is
+insufficient space available then either the function
+@samp{__rt_stkovf_split_small} or @samp{__rt_stkovf_split_big} will be
+called, depending upon the amount of stack space required. The run time
+system is required to provide these functions. The default is
+@option{-mno-apcs-stack-check}, since this produces smaller code.
+@c not currently implemented
+@item -mapcs-float
+@opindex mapcs-float
+Pass floating point arguments using the float point registers. This is
+one of the variants of the APCS@. This option is recommended if the
+target hardware has a floating point unit or if a lot of floating point
+arithmetic is going to be performed by the code. The default is
+@option{-mno-apcs-float}, since integer only code is slightly increased in
+size if @option{-mapcs-float} is used.
-@item -m68020-40
-@opindex m68020-40
-Generate output for a 68040, without using any of the new instructions.
-This results in code which can run relatively efficiently on either a
-68020/68881 or a 68030 or a 68040. The generated code does use the
-68881 instructions that are emulated on the 68040.
+@c not currently implemented
+@item -mapcs-reentrant
+@opindex mapcs-reentrant
+Generate reentrant, position independent code. The default is
+@option{-mno-apcs-reentrant}.
+@end ignore
-@item -m68020-60
-@opindex m68020-60
-Generate output for a 68060, without using any of the new instructions.
-This results in code which can run relatively efficiently on either a
-68020/68881 or a 68030 or a 68040. The generated code does use the
-68881 instructions that are emulated on the 68060.
+@item -mthumb-interwork
+@opindex mthumb-interwork
+Generate code which supports calling between the ARM and Thumb
+instruction sets. Without this option the two instruction sets cannot
+be reliably used inside one program. The default is
+@option{-mno-thumb-interwork}, since slightly larger code is generated
+when @option{-mthumb-interwork} is specified.
+
+@item -mno-sched-prolog
+@opindex mno-sched-prolog
+Prevent the reordering of instructions in the function prolog, or the
+merging of those instruction with the instructions in the function's
+body. This means that all functions will start with a recognizable set
+of instructions (or in fact one of a choice from a small set of
+different function prologues), and this information can be used to
+locate the start if functions inside an executable piece of code. The
+default is @option{-msched-prolog}.
+
+@item -mhard-float
+@opindex mhard-float
+Generate output containing floating point instructions. This is the
+default.
@item -msoft-float
@opindex msoft-float
Generate output containing library calls for floating point.
-@strong{Warning:} the requisite libraries are not available for all m68k
+@strong{Warning:} the requisite libraries are not available for all ARM
targets. Normally the facilities of the machine's usual C compiler are
-used, but this can't be done directly in cross-compilation. You must
-make your own arrangements to provide suitable library functions for
-cross-compilation. The embedded targets @samp{m68k-*-aout} and
-@samp{m68k-*-coff} do provide software floating point support.
+used, but this cannot be done directly in cross-compilation. You must make
+your own arrangements to provide suitable library functions for
+cross-compilation.
-@item -mshort
-@opindex mshort
-Consider type @code{int} to be 16 bits wide, like @code{short int}.
+@option{-msoft-float} changes the calling convention in the output file;
+therefore, it is only useful if you compile @emph{all} of a program with
+this option. In particular, you need to compile @file{libgcc.a}, the
+library that comes with GCC, with @option{-msoft-float} in order for
+this to work.
-@item -mnobitfield
-@opindex mnobitfield
-Do not use the bit-field instructions. The @option{-m68000}, @option{-mcpu32}
-and @option{-m5200} options imply @w{@option{-mnobitfield}}.
+@item -mfloat-abi=@var{name}
+@opindex mfloat-abi
+Specifies which ABI to use for floating point values. Permissible values
+are: @samp{soft}, @samp{softfp} and @samp{hard}.
-@item -mbitfield
-@opindex mbitfield
-Do use the bit-field instructions. The @option{-m68020} option implies
-@option{-mbitfield}. This is the default if you use a configuration
-designed for a 68020.
+@samp{soft} and @samp{hard} are equivalent to @option{-msoft-float}
+and @option{-mhard-float} respectively. @samp{softfp} allows the generation
+of floating point instructions, but still uses the soft-float calling
+conventions.
-@item -mrtd
-@opindex mrtd
-Use a different function-calling convention, in which functions
-that take a fixed number of arguments return with the @code{rtd}
-instruction, which pops their arguments while returning. This
-saves one instruction in the caller since there is no need to pop
-the arguments there.
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code for a processor running in little-endian mode. This is
+the default for all standard configurations.
-This calling convention is incompatible with the one normally
-used on Unix, so you cannot use it if you need to call libraries
-compiled with the Unix compiler.
+@item -mbig-endian
+@opindex mbig-endian
+Generate code for a processor running in big-endian mode; the default is
+to compile code for a little-endian processor.
-Also, you must provide function prototypes for all functions that
-take variable numbers of arguments (including @code{printf});
-otherwise incorrect code will be generated for calls to those
-functions.
+@item -mwords-little-endian
+@opindex mwords-little-endian
+This option only applies when generating code for big-endian processors.
+Generate code for a little-endian word order but a big-endian byte
+order. That is, a byte order of the form @samp{32107654}. Note: this
+option should only be used if you require compatibility with code for
+big-endian ARM processors generated by versions of the compiler prior to
+2.8.
-In addition, seriously incorrect code will result if you call a
-function with too many arguments. (Normally, extra arguments are
-harmlessly ignored.)
+@item -mcpu=@var{name}
+@opindex mcpu
+This specifies the name of the target ARM processor. GCC uses this name
+to determine what kind of instructions it can emit when generating
+assembly code. Permissible names are: @samp{arm2}, @samp{arm250},
+@samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610},
+@samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
+@samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
+@samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
+@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm8},
+@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
+@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
+@samp{arm920t}, @samp{arm926ejs}, @samp{arm940t}, @samp{arm9tdmi},
+@samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ejs},
+@samp{arm1136js}, @samp{arm1136jfs} ,@samp{xscale}, @samp{iwmmxt},
+@samp{ep9312}.
-The @code{rtd} instruction is supported by the 68010, 68020, 68030,
-68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
+@itemx -mtune=@var{name}
+@opindex mtune
+This option is very similar to the @option{-mcpu=} option, except that
+instead of specifying the actual target processor type, and hence
+restricting which instructions can be used, it specifies that GCC should
+tune the performance of the code as if the target were of the type
+specified in this option, but still choosing the instructions that it
+will generate based on the cpu specified by a @option{-mcpu=} option.
+For some ARM implementations better performance can be obtained by using
+this option.
-@item -malign-int
-@itemx -mno-align-int
-@opindex malign-int
-@opindex mno-align-int
-Control whether GCC aligns @code{int}, @code{long}, @code{long long},
-@code{float}, @code{double}, and @code{long double} variables on a 32-bit
-boundary (@option{-malign-int}) or a 16-bit boundary (@option{-mno-align-int}).
-Aligning variables on 32-bit boundaries produces code that runs somewhat
-faster on processors with 32-bit busses at the expense of more memory.
+@item -march=@var{name}
+@opindex march
+This specifies the name of the target ARM architecture. GCC uses this
+name to determine what kind of instructions it can emit when generating
+assembly code. This option can be used in conjunction with or instead
+of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
+@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
+@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{armv6}, @samp{armv6j},
+@samp{iwmmxt}, @samp{ep9312}.
-@strong{Warning:} if you use the @option{-malign-int} switch, GCC will
-align structures containing the above types differently than
-most published application binary interface specifications for the m68k.
+@item -mfpu=@var{name}
+@itemx -mfpe=@var{number}
+@itemx -mfp=@var{number}
+@opindex mfpu
+@opindex mfpe
+@opindex mfp
+This specifies what floating point hardware (or hardware emulation) is
+available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
+@samp{fpe3}, @samp{maverick}, @samp{vfp}. @option{-mfp} and @option{-mfpe}
+are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility
+with older versions of GCC@.
-@item -mpcrel
-@opindex mpcrel
-Use the pc-relative addressing mode of the 68000 directly, instead of
-using a global offset table. At present, this option implies @option{-fpic},
-allowing at most a 16-bit offset for pc-relative addressing. @option{-fPIC} is
-not presently supported with @option{-mpcrel}, though this could be supported for
-68020 and higher processors.
+If @option{-msoft-float} is specified this specifies the format of
+floating point values.
-@item -mno-strict-align
-@itemx -mstrict-align
-@opindex mno-strict-align
-@opindex mstrict-align
-Do not (do) assume that unaligned memory references will be handled by
-the system.
+@item -mstructure-size-boundary=@var{n}
+@opindex mstructure-size-boundary
+The size of all structures and unions will be rounded up to a multiple
+of the number of bits set by this option. Permissible values are 8, 32
+and 64. The default value varies for different toolchains. For the COFF
+targeted toolchain the default value is 8. A value of 64 is only allowed
+if the underlying ABI supports it.
-@item -msep-data
-Generate code that allows the data segment to be located in a different
-area of memory from the text segment. This allows for execute in place in
-an environment without virtual memory management. This option implies -fPIC.
+Specifying the larger number can produce faster, more efficient code, but
+can also increase the size of the program. Different values are potentially
+incompatible. Code compiled with one value cannot necessarily expect to
+work with code or libraries compiled with another value, if they exchange
+information using structures or unions.
-@item -mno-sep-data
-Generate code that assumes that the data segment follows the text segment.
-This is the default.
+@item -mabort-on-noreturn
+@opindex mabort-on-noreturn
+Generate a call to the function @code{abort} at the end of a
+@code{noreturn} function. It will be executed if the function tries to
+return.
-@item -mid-shared-library
-Generate code that supports shared libraries via the library ID method.
-This allows for execute in place and shared libraries in an environment
-without virtual memory management. This option implies -fPIC.
+@item -mlong-calls
+@itemx -mno-long-calls
+@opindex mlong-calls
+@opindex mno-long-calls
+Tells the compiler to perform function calls by first loading the
+address of the function into a register and then performing a subroutine
+call on this register. This switch is needed if the target function
+will lie outside of the 64 megabyte addressing range of the offset based
+version of subroutine call instruction.
-@item -mno-id-shared-library
-Generate code that doesn't assume ID based shared libraries are being used.
-This is the default.
+Even if this switch is enabled, not all function calls will be turned
+into long calls. The heuristic is that static functions, functions
+which have the @samp{short-call} attribute, functions that are inside
+the scope of a @samp{#pragma no_long_calls} directive and functions whose
+definitions have already been compiled within the current compilation
+unit, will not be turned into long calls. The exception to this rule is
+that weak function definitions, functions with the @samp{long-call}
+attribute or the @samp{section} attribute, and functions that are within
+the scope of a @samp{#pragma long_calls} directive, will always be
+turned into long calls.
-@item -mshared-library-id=n
-Specified the identification number of the ID based shared library being
-compiled. Specifying a value of 0 will generate more compact code, specifying
-other values will force the allocation of that number to the current
-library but is no more space or time efficient than omitting this option.
+This feature is not enabled by default. Specifying
+@option{-mno-long-calls} will restore the default behavior, as will
+placing the function calls within the scope of a @samp{#pragma
+long_calls_off} directive. Note these switches have no effect on how
+the compiler generates code to handle function calls via function
+pointers.
-@end table
+@item -mnop-fun-dllimport
+@opindex mnop-fun-dllimport
+Disable support for the @code{dllimport} attribute.
-@node M68hc1x Options
-@subsection M68hc1x Options
-@cindex M68hc1x options
+@item -msingle-pic-base
+@opindex msingle-pic-base
+Treat the register used for PIC addressing as read-only, rather than
+loading it in the prologue for each function. The run-time system is
+responsible for initializing this register with an appropriate value
+before execution begins.
-These are the @samp{-m} options defined for the 68hc11 and 68hc12
-microcontrollers. The default values for these options depends on
-which style of microcontroller was selected when the compiler was configured;
-the defaults for the most common choices are given below.
+@item -mpic-register=@var{reg}
+@opindex mpic-register
+Specify the register to be used for PIC addressing. The default is R10
+unless stack-checking is enabled, when R9 is used.
-@table @gcctabopt
-@item -m6811
-@itemx -m68hc11
-@opindex m6811
-@opindex m68hc11
-Generate output for a 68HC11. This is the default
-when the compiler is configured for 68HC11-based systems.
+@item -mcirrus-fix-invalid-insns
+@opindex mcirrus-fix-invalid-insns
+@opindex mno-cirrus-fix-invalid-insns
+Insert NOPs into the instruction stream to in order to work around
+problems with invalid Maverick instruction combinations. This option
+is only valid if the @option{-mcpu=ep9312} option has been used to
+enable generation of instructions for the Cirrus Maverick floating
+point co-processor. This option is not enabled by default, since the
+problem is only present in older Maverick implementations. The default
+can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
+switch.
-@item -m6812
-@itemx -m68hc12
-@opindex m6812
-@opindex m68hc12
-Generate output for a 68HC12. This is the default
-when the compiler is configured for 68HC12-based systems.
+@item -mpoke-function-name
+@opindex mpoke-function-name
+Write the name of each function into the text section, directly
+preceding the function prologue. The generated code is similar to this:
-@item -m68S12
-@itemx -m68hcs12
-@opindex m68S12
-@opindex m68hcs12
-Generate output for a 68HCS12.
+@smallexample
+ t0
+ .ascii "arm_poke_function_name", 0
+ .align
+ t1
+ .word 0xff000000 + (t1 - t0)
+ arm_poke_function_name
+ mov ip, sp
+ stmfd sp!, @{fp, ip, lr, pc@}
+ sub fp, ip, #4
+@end smallexample
-@item -mauto-incdec
-@opindex mauto-incdec
-Enable the use of 68HC12 pre and post auto-increment and auto-decrement
-addressing modes.
+When performing a stack backtrace, code can inspect the value of
+@code{pc} stored at @code{fp + 0}. If the trace function then looks at
+location @code{pc - 12} and the top 8 bits are set, then we know that
+there is a function name embedded immediately preceding this location
+and has length @code{((pc[-3]) & 0xff000000)}.
-@item -minmax
-@itemx -nominmax
-@opindex minmax
-@opindex mnominmax
-Enable the use of 68HC12 min and max instructions.
+@item -mthumb
+@opindex mthumb
+Generate code for the 16-bit Thumb instruction set. The default is to
+use the 32-bit ARM instruction set.
-@item -mlong-calls
-@itemx -mno-long-calls
-@opindex mlong-calls
-@opindex mno-long-calls
-Treat all calls as being far away (near). If calls are assumed to be
-far away, the compiler will use the @code{call} instruction to
-call a function and the @code{rtc} instruction for returning.
+@item -mtpcs-frame
+@opindex mtpcs-frame
+Generate a stack frame that is compliant with the Thumb Procedure Call
+Standard for all non-leaf functions. (A leaf function is one that does
+not call any other functions.) The default is @option{-mno-tpcs-frame}.
-@item -mshort
-@opindex mshort
-Consider type @code{int} to be 16 bits wide, like @code{short int}.
+@item -mtpcs-leaf-frame
+@opindex mtpcs-leaf-frame
+Generate a stack frame that is compliant with the Thumb Procedure Call
+Standard for all leaf functions. (A leaf function is one that does
+not call any other functions.) The default is @option{-mno-apcs-leaf-frame}.
-@item -msoft-reg-count=@var{count}
-@opindex msoft-reg-count
-Specify the number of pseudo-soft registers which are used for the
-code generation. The maximum number is 32. Using more pseudo-soft
-register may or may not result in better code depending on the program.
-The default is 4 for 68HC11 and 2 for 68HC12.
+@item -mcallee-super-interworking
+@opindex mcallee-super-interworking
+Gives all externally visible functions in the file being compiled an ARM
+instruction set header which switches to Thumb mode before executing the
+rest of the function. This allows these functions to be called from
+non-interworking code.
+
+@item -mcaller-super-interworking
+@opindex mcaller-super-interworking
+Allows calls via function pointers (including virtual functions) to
+execute correctly regardless of whether the target code has been
+compiled for interworking or not. There is a small overhead in the cost
+of executing a function pointer if this option is enabled.
@end table
-@node VAX Options
-@subsection VAX Options
-@cindex VAX options
+@node AVR Options
+@subsection AVR Options
+@cindex AVR Options
-These @samp{-m} options are defined for the VAX:
+These options are defined for AVR implementations:
@table @gcctabopt
-@item -munix
-@opindex munix
-Do not output certain jump instructions (@code{aobleq} and so on)
-that the Unix assembler for the VAX cannot handle across long
-ranges.
+@item -mmcu=@var{mcu}
+@opindex mmcu
+Specify ATMEL AVR instruction set or MCU type.
-@item -mgnu
-@opindex mgnu
-Do output those jump instructions, on the assumption that you
-will assemble with the GNU assembler.
+Instruction set avr1 is for the minimal AVR core, not supported by the C
+compiler, only for assembler programs (MCU types: at90s1200, attiny10,
+attiny11, attiny12, attiny15, attiny28).
-@item -mg
-@opindex mg
-Output code for g-format floating point numbers instead of d-format.
-@end table
+Instruction set avr2 (default) is for the classic AVR core with up to
+8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
+at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
+at90c8534, at90s8535).
-@node SPARC Options
-@subsection SPARC Options
-@cindex SPARC options
+Instruction set avr3 is for the classic AVR core with up to 128K program
+memory space (MCU types: atmega103, atmega603, at43usb320, at76c711).
-These @samp{-m} options are supported on the SPARC:
+Instruction set avr4 is for the enhanced AVR core with up to 8K program
+memory space (MCU types: atmega8, atmega83, atmega85).
-@table @gcctabopt
-@item -mno-app-regs
-@itemx -mapp-regs
-@opindex mno-app-regs
-@opindex mapp-regs
-Specify @option{-mapp-regs} to generate output using the global registers
-2 through 4, which the SPARC SVR4 ABI reserves for applications. This
-is the default.
+Instruction set avr5 is for the enhanced AVR core with up to 128K program
+memory space (MCU types: atmega16, atmega161, atmega163, atmega32, atmega323,
+atmega64, atmega128, at43usb355, at94k).
-To be fully SVR4 ABI compliant at the cost of some performance loss,
-specify @option{-mno-app-regs}. You should compile libraries and system
-software with this option.
+@item -msize
+@opindex msize
+Output instruction sizes to the asm file.
-@item -mfpu
-@itemx -mhard-float
-@opindex mfpu
-@opindex mhard-float
-Generate output containing floating point instructions. This is the
-default.
+@item -minit-stack=@var{N}
+@opindex minit-stack
+Specify the initial stack address, which may be a symbol or numeric value,
+@samp{__stack} is the default.
-@item -mno-fpu
-@itemx -msoft-float
-@opindex mno-fpu
-@opindex msoft-float
-Generate output containing library calls for floating point.
-@strong{Warning:} the requisite libraries are not available for all SPARC
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross-compilation. The embedded targets @samp{sparc-*-aout} and
-@samp{sparclite-*-*} do provide software floating point support.
+@item -mno-interrupts
+@opindex mno-interrupts
+Generated code is not compatible with hardware interrupts.
+Code size will be smaller.
-@option{-msoft-float} changes the calling convention in the output file;
-therefore, it is only useful if you compile @emph{all} of a program with
-this option. In particular, you need to compile @file{libgcc.a}, the
-library that comes with GCC, with @option{-msoft-float} in order for
-this to work.
+@item -mcall-prologues
+@opindex mcall-prologues
+Functions prologues/epilogues expanded as call to appropriate
+subroutines. Code size will be smaller.
-@item -mhard-quad-float
-@opindex mhard-quad-float
-Generate output containing quad-word (long double) floating point
-instructions.
+@item -mno-tablejump
+@opindex mno-tablejump
+Do not generate tablejump insns which sometimes increase code size.
-@item -msoft-quad-float
-@opindex msoft-quad-float
-Generate output containing library calls for quad-word (long double)
-floating point instructions. The functions called are those specified
-in the SPARC ABI@. This is the default.
+@item -mtiny-stack
+@opindex mtiny-stack
+Change only the low 8 bits of the stack pointer.
-As of this writing, there are no SPARC implementations that have hardware
-support for the quad-word floating point instructions. They all invoke
-a trap handler for one of these instructions, and then the trap handler
-emulates the effect of the instruction. Because of the trap handler overhead,
-this is much slower than calling the ABI library routines. Thus the
-@option{-msoft-quad-float} option is the default.
+@item -mint8
+@opindex mint8
+Assume int to be 8 bit integer. This affects the sizes of all types: A
+char will be 1 byte, an int will be 1 byte, an long will be 2 bytes
+and long long will be 4 bytes. Please note that this option does not
+comply to the C standards, but it will provide you with smaller code
+size.
+@end table
-@item -mno-unaligned-doubles
-@itemx -munaligned-doubles
-@opindex mno-unaligned-doubles
-@opindex munaligned-doubles
-Assume that doubles have 8 byte alignment. This is the default.
+@node CRIS Options
+@subsection CRIS Options
+@cindex CRIS Options
-With @option{-munaligned-doubles}, GCC assumes that doubles have 8 byte
-alignment only if they are contained in another type, or if they have an
-absolute address. Otherwise, it assumes they have 4 byte alignment.
-Specifying this option avoids some rare compatibility problems with code
-generated by other compilers. It is not the default because it results
-in a performance loss, especially for floating point code.
+These options are defined specifically for the CRIS ports.
-@item -mno-faster-structs
-@itemx -mfaster-structs
-@opindex mno-faster-structs
-@opindex mfaster-structs
-With @option{-mfaster-structs}, the compiler assumes that structures
-should have 8 byte alignment. This enables the use of pairs of
-@code{ldd} and @code{std} instructions for copies in structure
-assignment, in place of twice as many @code{ld} and @code{st} pairs.
-However, the use of this changed alignment directly violates the SPARC
-ABI@. Thus, it's intended only for use on targets where the developer
-acknowledges that their resulting code will not be directly in line with
-the rules of the ABI@.
+@table @gcctabopt
+@item -march=@var{architecture-type}
+@itemx -mcpu=@var{architecture-type}
+@opindex march
+@opindex mcpu
+Generate code for the specified architecture. The choices for
+@var{architecture-type} are @samp{v3}, @samp{v8} and @samp{v10} for
+respectively ETRAX@w{ }4, ETRAX@w{ }100, and ETRAX@w{ }100@w{ }LX.
+Default is @samp{v0} except for cris-axis-linux-gnu, where the default is
+@samp{v10}.
-@item -mimpure-text
-@opindex mimpure-text
-@option{-mimpure-text}, used in addition to @option{-shared}, tells
-the compiler to not pass @option{-z text} to the linker when linking a
-shared object. Using this option, you can link position-dependent
-code into a shared object.
+@item -mtune=@var{architecture-type}
+@opindex mtune
+Tune to @var{architecture-type} everything applicable about the generated
+code, except for the ABI and the set of available instructions. The
+choices for @var{architecture-type} are the same as for
+@option{-march=@var{architecture-type}}.
-@option{-mimpure-text} suppresses the ``relocations remain against
-allocatable but non-writable sections'' linker error message.
-However, the necessary relocations will trigger copy-on-write, and the
-shared object is not actually shared across processes. Instead of
-using @option{-mimpure-text}, you should compile all source code with
-@option{-fpic} or @option{-fPIC}.
+@item -mmax-stack-frame=@var{n}
+@opindex mmax-stack-frame
+Warn when the stack frame of a function exceeds @var{n} bytes.
-This option is only available on SunOS and Solaris.
+@item -melinux-stacksize=@var{n}
+@opindex melinux-stacksize
+Only available with the @samp{cris-axis-aout} target. Arranges for
+indications in the program to the kernel loader that the stack of the
+program should be set to @var{n} bytes.
-@item -mcpu=@var{cpu_type}
-@opindex mcpu
-Set the instruction set, register set, and instruction scheduling parameters
-for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
-@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite},
-@samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x},
-@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, and
-@samp{ultrasparc3}.
+@item -metrax4
+@itemx -metrax100
+@opindex metrax4
+@opindex metrax100
+The options @option{-metrax4} and @option{-metrax100} are synonyms for
+@option{-march=v3} and @option{-march=v8} respectively.
-Default instruction scheduling parameters are used for values that select
-an architecture and not an implementation. These are @samp{v7}, @samp{v8},
-@samp{sparclite}, @samp{sparclet}, @samp{v9}.
+@item -mmul-bug-workaround
+@itemx -mno-mul-bug-workaround
+@opindex mmul-bug-workaround
+@opindex mno-mul-bug-workaround
+Work around a bug in the @code{muls} and @code{mulu} instructions for CPU
+models where it applies. This option is active by default.
-Here is a list of each supported architecture and their supported
-implementations.
+@item -mpdebug
+@opindex mpdebug
+Enable CRIS-specific verbose debug-related information in the assembly
+code. This option also has the effect to turn off the @samp{#NO_APP}
+formatted-code indicator to the assembler at the beginning of the
+assembly file.
-@smallexample
- v7: cypress
- v8: supersparc, hypersparc
- sparclite: f930, f934, sparclite86x
- sparclet: tsc701
- v9: ultrasparc, ultrasparc3
-@end smallexample
+@item -mcc-init
+@opindex mcc-init
+Do not use condition-code results from previous instruction; always emit
+compare and test instructions before use of condition codes.
-By default (unless configured otherwise), GCC generates code for the V7
-variant of the SPARC architecture. With @option{-mcpu=cypress}, the compiler
-additionally optimizes it for the Cypress CY7C602 chip, as used in the
-SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
-SPARCStation 1, 2, IPX etc.
+@item -mno-side-effects
+@opindex mno-side-effects
+Do not emit instructions with side-effects in addressing modes other than
+post-increment.
-With @option{-mcpu=v8}, GCC generates code for the V8 variant of the SPARC
-architecture. The only difference from V7 code is that the compiler emits
-the integer multiply and integer divide instructions which exist in SPARC-V8
-but not in SPARC-V7. With @option{-mcpu=supersparc}, the compiler additionally
-optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
-2000 series.
+@item -mstack-align
+@itemx -mno-stack-align
+@itemx -mdata-align
+@itemx -mno-data-align
+@itemx -mconst-align
+@itemx -mno-const-align
+@opindex mstack-align
+@opindex mno-stack-align
+@opindex mdata-align
+@opindex mno-data-align
+@opindex mconst-align
+@opindex mno-const-align
+These options (no-options) arranges (eliminate arrangements) for the
+stack-frame, individual data and constants to be aligned for the maximum
+single data access size for the chosen CPU model. The default is to
+arrange for 32-bit alignment. ABI details such as structure layout are
+not affected by these options.
-With @option{-mcpu=sparclite}, GCC generates code for the SPARClite variant of
-the SPARC architecture. This adds the integer multiply, integer divide step
-and scan (@code{ffs}) instructions which exist in SPARClite but not in SPARC-V7.
-With @option{-mcpu=f930}, the compiler additionally optimizes it for the
-Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With
-@option{-mcpu=f934}, the compiler additionally optimizes it for the Fujitsu
-MB86934 chip, which is the more recent SPARClite with FPU.
+@item -m32-bit
+@itemx -m16-bit
+@itemx -m8-bit
+@opindex m32-bit
+@opindex m16-bit
+@opindex m8-bit
+Similar to the stack- data- and const-align options above, these options
+arrange for stack-frame, writable data and constants to all be 32-bit,
+16-bit or 8-bit aligned. The default is 32-bit alignment.
-With @option{-mcpu=sparclet}, GCC generates code for the SPARClet variant of
-the SPARC architecture. This adds the integer multiply, multiply/accumulate,
-integer divide step and scan (@code{ffs}) instructions which exist in SPARClet
-but not in SPARC-V7. With @option{-mcpu=tsc701}, the compiler additionally
-optimizes it for the TEMIC SPARClet chip.
+@item -mno-prologue-epilogue
+@itemx -mprologue-epilogue
+@opindex mno-prologue-epilogue
+@opindex mprologue-epilogue
+With @option{-mno-prologue-epilogue}, the normal function prologue and
+epilogue that sets up the stack-frame are omitted and no return
+instructions or return sequences are generated in the code. Use this
+option only together with visual inspection of the compiled code: no
+warnings or errors are generated when call-saved registers must be saved,
+or storage for local variable needs to be allocated.
-With @option{-mcpu=v9}, GCC generates code for the V9 variant of the SPARC
-architecture. This adds 64-bit integer and floating-point move instructions,
-3 additional floating-point condition code registers and conditional move
-instructions. With @option{-mcpu=ultrasparc}, the compiler additionally
-optimizes it for the Sun UltraSPARC I/II chips. With
-@option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
-Sun UltraSPARC III chip.
+@item -mno-gotplt
+@itemx -mgotplt
+@opindex mno-gotplt
+@opindex mgotplt
+With @option{-fpic} and @option{-fPIC}, don't generate (do generate)
+instruction sequences that load addresses for functions from the PLT part
+of the GOT rather than (traditional on other architectures) calls to the
+PLT. The default is @option{-mgotplt}.
-@item -mtune=@var{cpu_type}
-@opindex mtune
-Set the instruction scheduling parameters for machine type
-@var{cpu_type}, but do not set the instruction set or register set that the
-option @option{-mcpu=@var{cpu_type}} would.
+@item -maout
+@opindex maout
+Legacy no-op option only recognized with the cris-axis-aout target.
-The same values for @option{-mcpu=@var{cpu_type}} can be used for
-@option{-mtune=@var{cpu_type}}, but the only useful values are those
-that select a particular cpu implementation. Those are @samp{cypress},
-@samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934},
-@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, and
-@samp{ultrasparc3}.
+@item -melf
+@opindex melf
+Legacy no-op option only recognized with the cris-axis-elf and
+cris-axis-linux-gnu targets.
-@item -mv8plus
-@itemx -mno-v8plus
-@opindex -mv8plus
-@opindex -mno-v8plus
-With @option{-mv8plus}, GCC generates code for the SPARC-V8+ ABI. The
-difference from the V8 ABI is that the global and out registers are
-considered 64-bit wide. This is enabled by default on Solaris in 32-bit
-mode for all SPARC-V9 processors.
+@item -melinux
+@opindex melinux
+Only recognized with the cris-axis-aout target, where it selects a
+GNU/linux-like multilib, include files and instruction set for
+@option{-march=v8}.
-@item -mvis
-@itemx -mno-vis
-@opindex -mvis
-@opindex -mno-vis
-With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC
-Visual Instruction Set extensions. The default is @option{-mno-vis}.
+@item -mlinux
+@opindex mlinux
+Legacy no-op option only recognized with the cris-axis-linux-gnu target.
+
+@item -sim
+@opindex sim
+This option, recognized for the cris-axis-aout and cris-axis-elf arranges
+to link with input-output functions from a simulator library. Code,
+initialized data and zero-initialized data are allocated consecutively.
+
+@item -sim2
+@opindex sim2
+Like @option{-sim}, but pass linker options to locate initialized data at
+0x40000000 and zero-initialized data at 0x80000000.
@end table
-These @samp{-m} options are supported in addition to the above
-on SPARC-V9 processors in 64-bit environments:
+@node Darwin Options
+@subsection Darwin Options
+@cindex Darwin options
+
+These options are defined for all architectures running the Darwin operating
+system. They are useful for compatibility with other Mac OS compilers.
@table @gcctabopt
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a processor running in little-endian mode. It is only
-available for a few configurations and most notably not on Solaris.
+@item -F@var{dir}
+@opindex F
+Add the framework directory @var{dir} to the head of the list of
+directories to be searched for header files. These directories are
+interleaved with those specified by @option{-I} options and are
+scanned in a left-to-right order.
+
+A framework directory is a directory with frameworks in it. A
+framework is a directory with a @samp{"Headers"} and/or
+@samp{"PrivateHeaders"} directory contained directly in it that ends
+in @samp{".framework"}. The name of a framework is the name of this
+directory excluding the @samp{".framework"}. Headers associated with
+the framework are found in one of those two directories, with
+@samp{"Headers"} being searched first. A subframework is a framework
+directory that is in a framework's @samp{"Frameworks"} directory.
+Includes of subframework headers can only appear in a header of a
+framework that contains the subframework, or in a sibling subframework
+header. Two subframeworks are siblings if they occur in the same
+framework. A subframework should not have the same name as a
+framework, a warning will be issued if this is violated. Currently a
+subframework cannot have subframeworks, in the future, the mechanism
+may be extended to support this. The standard frameworks can be found
+in @samp{"/System/Library/Frameworks"}, @samp{"/Library/Frameworks"}
+and @samp{"/Local/Library/Frameworks"}. An example include looks like
+@code{#include <Framework/header.h>}, where @samp{Framework} denotes
+the name of the framework and header.h is found in the
+@samp{"PrivateHeaders"} or @samp{"Headers"} directory.
-@item -m32
-@itemx -m64
-@opindex m32
-@opindex m64
-Generate code for a 32-bit or 64-bit environment.
-The 32-bit environment sets int, long and pointer to 32 bits.
-The 64-bit environment sets int to 32 bits and long and pointer
-to 64 bits.
-
-@item -mcmodel=medlow
-@opindex mcmodel=medlow
-Generate code for the Medium/Low code model: 64-bit addresses, programs
-must be linked in the low 32 bits of memory. Programs can be statically
-or dynamically linked.
-
-@item -mcmodel=medmid
-@opindex mcmodel=medmid
-Generate code for the Medium/Middle code model: 64-bit addresses, programs
-must be linked in the low 44 bits of memory, the text and data segments must
-be less than 2GB in size and the data segment must be located within 2GB of
-the text segment.
-
-@item -mcmodel=medany
-@opindex mcmodel=medany
-Generate code for the Medium/Anywhere code model: 64-bit addresses, programs
-may be linked anywhere in memory, the text and data segments must be less
-than 2GB in size and the data segment must be located within 2GB of the
-text segment.
-
-@item -mcmodel=embmedany
-@opindex mcmodel=embmedany
-Generate code for the Medium/Anywhere code model for embedded systems:
-64-bit addresses, the text and data segments must be less than 2GB in
-size, both starting anywhere in memory (determined at link time). The
-global register %g4 points to the base of the data segment. Programs
-are statically linked and PIC is not supported.
-
-@item -mstack-bias
-@itemx -mno-stack-bias
-@opindex mstack-bias
-@opindex mno-stack-bias
-With @option{-mstack-bias}, GCC assumes that the stack pointer, and
-frame pointer if present, are offset by @minus{}2047 which must be added back
-when making stack frame references. This is the default in 64-bit mode.
-Otherwise, assume no such offset is present.
-@end table
-
-@node ARM Options
-@subsection ARM Options
-@cindex ARM options
-
-These @samp{-m} options are defined for Advanced RISC Machines (ARM)
-architectures:
-
-@table @gcctabopt
-@item -mabi=@var{name}
-@opindex mabi
-Generate code for the specified ABI. Permissible values are: @samp{apcs-gnu},
-@samp{atpcs}, @samp{aapcs} and @samp{iwmmxt}.
-
-@item -mapcs-frame
-@opindex mapcs-frame
-Generate a stack frame that is compliant with the ARM Procedure Call
-Standard for all functions, even if this is not strictly necessary for
-correct execution of the code. Specifying @option{-fomit-frame-pointer}
-with this option will cause the stack frames not to be generated for
-leaf functions. The default is @option{-mno-apcs-frame}.
-
-@item -mapcs
-@opindex mapcs
-This is a synonym for @option{-mapcs-frame}.
-
-@item -mapcs-26
-@opindex mapcs-26
-Generate code for a processor running with a 26-bit program counter,
-and conforming to the function calling standards for the APCS 26-bit
-option. This option replaces the @option{-m2} and @option{-m3} options
-of previous releases of the compiler.
-
-@item -mapcs-32
-@opindex mapcs-32
-Generate code for a processor running with a 32-bit program counter,
-and conforming to the function calling standards for the APCS 32-bit
-option. This option replaces the @option{-m6} option of previous releases
-of the compiler.
-
-@ignore
-@c not currently implemented
-@item -mapcs-stack-check
-@opindex mapcs-stack-check
-Generate code to check the amount of stack space available upon entry to
-every function (that actually uses some stack space). If there is
-insufficient space available then either the function
-@samp{__rt_stkovf_split_small} or @samp{__rt_stkovf_split_big} will be
-called, depending upon the amount of stack space required. The run time
-system is required to provide these functions. The default is
-@option{-mno-apcs-stack-check}, since this produces smaller code.
-
-@c not currently implemented
-@item -mapcs-float
-@opindex mapcs-float
-Pass floating point arguments using the float point registers. This is
-one of the variants of the APCS@. This option is recommended if the
-target hardware has a floating point unit or if a lot of floating point
-arithmetic is going to be performed by the code. The default is
-@option{-mno-apcs-float}, since integer only code is slightly increased in
-size if @option{-mapcs-float} is used.
-
-@c not currently implemented
-@item -mapcs-reentrant
-@opindex mapcs-reentrant
-Generate reentrant, position independent code. The default is
-@option{-mno-apcs-reentrant}.
-@end ignore
-
-@item -mthumb-interwork
-@opindex mthumb-interwork
-Generate code which supports calling between the ARM and Thumb
-instruction sets. Without this option the two instruction sets cannot
-be reliably used inside one program. The default is
-@option{-mno-thumb-interwork}, since slightly larger code is generated
-when @option{-mthumb-interwork} is specified.
-
-@item -mno-sched-prolog
-@opindex mno-sched-prolog
-Prevent the reordering of instructions in the function prolog, or the
-merging of those instruction with the instructions in the function's
-body. This means that all functions will start with a recognizable set
-of instructions (or in fact one of a choice from a small set of
-different function prologues), and this information can be used to
-locate the start if functions inside an executable piece of code. The
-default is @option{-msched-prolog}.
-
-@item -mhard-float
-@opindex mhard-float
-Generate output containing floating point instructions. This is the
-default.
-
-@item -msoft-float
-@opindex msoft-float
-Generate output containing library calls for floating point.
-@strong{Warning:} the requisite libraries are not available for all ARM
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross-compilation.
-
-@option{-msoft-float} changes the calling convention in the output file;
-therefore, it is only useful if you compile @emph{all} of a program with
-this option. In particular, you need to compile @file{libgcc.a}, the
-library that comes with GCC, with @option{-msoft-float} in order for
-this to work.
-
-@item -mfloat-abi=@var{name}
-@opindex mfloat-abi
-Specifies which ABI to use for floating point values. Permissible values
-are: @samp{soft}, @samp{softfp} and @samp{hard}.
-
-@samp{soft} and @samp{hard} are equivalent to @option{-msoft-float}
-and @option{-mhard-float} respectively. @samp{softfp} allows the generation
-of floating point instructions, but still uses the soft-float calling
-conventions.
-
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a processor running in little-endian mode. This is
-the default for all standard configurations.
-
-@item -mbig-endian
-@opindex mbig-endian
-Generate code for a processor running in big-endian mode; the default is
-to compile code for a little-endian processor.
-
-@item -mwords-little-endian
-@opindex mwords-little-endian
-This option only applies when generating code for big-endian processors.
-Generate code for a little-endian word order but a big-endian byte
-order. That is, a byte order of the form @samp{32107654}. Note: this
-option should only be used if you require compatibility with code for
-big-endian ARM processors generated by versions of the compiler prior to
-2.8.
-
-@item -malignment-traps
-@opindex malignment-traps
-Generate code that will not trap if the MMU has alignment traps enabled.
-On ARM architectures prior to ARMv4, there were no instructions to
-access half-word objects stored in memory. However, when reading from
-memory a feature of the ARM architecture allows a word load to be used,
-even if the address is unaligned, and the processor core will rotate the
-data as it is being loaded. This option tells the compiler that such
-misaligned accesses will cause a MMU trap and that it should instead
-synthesize the access as a series of byte accesses. The compiler can
-still use word accesses to load half-word data if it knows that the
-address is aligned to a word boundary.
-
-This option is ignored when compiling for ARM architecture 4 or later,
-since these processors have instructions to directly access half-word
-objects in memory.
-
-@item -mno-alignment-traps
-@opindex mno-alignment-traps
-Generate code that assumes that the MMU will not trap unaligned
-accesses. This produces better code when the target instruction set
-does not have half-word memory operations (i.e.@: implementations prior to
-ARMv4).
-
-Note that you cannot use this option to access unaligned word objects,
-since the processor will only fetch one 32-bit aligned object from
-memory.
-
-The default setting for most targets is @option{-mno-alignment-traps}, since
-this produces better code when there are no half-word memory
-instructions available.
-
-@item -mshort-load-bytes
-@itemx -mno-short-load-words
-@opindex mshort-load-bytes
-@opindex mno-short-load-words
-These are deprecated aliases for @option{-malignment-traps}.
-
-@item -mno-short-load-bytes
-@itemx -mshort-load-words
-@opindex mno-short-load-bytes
-@opindex mshort-load-words
-This are deprecated aliases for @option{-mno-alignment-traps}.
-
-@item -mcpu=@var{name}
-@opindex mcpu
-This specifies the name of the target ARM processor. GCC uses this name
-to determine what kind of instructions it can emit when generating
-assembly code. Permissible names are: @samp{arm2}, @samp{arm250},
-@samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610},
-@samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
-@samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
-@samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
-@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm8},
-@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
-@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
-@samp{arm920t}, @samp{arm926ejs}, @samp{arm940t}, @samp{arm9tdmi},
-@samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ejs},
-@samp{arm1136js}, @samp{arm1136jfs} ,@samp{xscale}, @samp{iwmmxt},
-@samp{ep9312}.
-
-@itemx -mtune=@var{name}
-@opindex mtune
-This option is very similar to the @option{-mcpu=} option, except that
-instead of specifying the actual target processor type, and hence
-restricting which instructions can be used, it specifies that GCC should
-tune the performance of the code as if the target were of the type
-specified in this option, but still choosing the instructions that it
-will generate based on the cpu specified by a @option{-mcpu=} option.
-For some ARM implementations better performance can be obtained by using
-this option.
-
-@item -march=@var{name}
-@opindex march
-This specifies the name of the target ARM architecture. GCC uses this
-name to determine what kind of instructions it can emit when generating
-assembly code. This option can be used in conjunction with or instead
-of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
-@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
-@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{armv6}, @samp{armv6j},
-@samp{iwmmxt}, @samp{ep9312}.
-
-@item -mfpu=@var{name}
-@itemx -mfpe=@var{number}
-@itemx -mfp=@var{number}
-@opindex mfpu
-@opindex mfpe
-@opindex mfp
-This specifies what floating point hardware (or hardware emulation) is
-available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
-@samp{fpe3}, @samp{maverick}, @samp{vfp}. @option{-mfp} and @option{-mfpe}
-are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility
-with older versions of GCC@.
-
-If @option{-msoft-float} is specified this specifies the format of
-floating point values.
-
-@item -mstructure-size-boundary=@var{n}
-@opindex mstructure-size-boundary
-The size of all structures and unions will be rounded up to a multiple
-of the number of bits set by this option. Permissible values are 8, 32
-and 64. The default value varies for different toolchains. For the COFF
-targeted toolchain the default value is 8. A value of 64 is only allowed
-if the underlying ABI supports it.
-
-Specifying the larger number can produce faster, more efficient code, but
-can also increase the size of the program. Different values are potentially
-incompatible. Code compiled with one value cannot necessarily expect to
-work with code or libraries compiled with annother value, if they exchange
-information using structures or unions.
-
-@item -mabort-on-noreturn
-@opindex mabort-on-noreturn
-Generate a call to the function @code{abort} at the end of a
-@code{noreturn} function. It will be executed if the function tries to
-return.
-
-@item -mlong-calls
-@itemx -mno-long-calls
-@opindex mlong-calls
-@opindex mno-long-calls
-Tells the compiler to perform function calls by first loading the
-address of the function into a register and then performing a subroutine
-call on this register. This switch is needed if the target function
-will lie outside of the 64 megabyte addressing range of the offset based
-version of subroutine call instruction.
-
-Even if this switch is enabled, not all function calls will be turned
-into long calls. The heuristic is that static functions, functions
-which have the @samp{short-call} attribute, functions that are inside
-the scope of a @samp{#pragma no_long_calls} directive and functions whose
-definitions have already been compiled within the current compilation
-unit, will not be turned into long calls. The exception to this rule is
-that weak function definitions, functions with the @samp{long-call}
-attribute or the @samp{section} attribute, and functions that are within
-the scope of a @samp{#pragma long_calls} directive, will always be
-turned into long calls.
-
-This feature is not enabled by default. Specifying
-@option{-mno-long-calls} will restore the default behavior, as will
-placing the function calls within the scope of a @samp{#pragma
-long_calls_off} directive. Note these switches have no effect on how
-the compiler generates code to handle function calls via function
-pointers.
-
-@item -mnop-fun-dllimport
-@opindex mnop-fun-dllimport
-Disable support for the @code{dllimport} attribute.
-
-@item -msingle-pic-base
-@opindex msingle-pic-base
-Treat the register used for PIC addressing as read-only, rather than
-loading it in the prologue for each function. The run-time system is
-responsible for initializing this register with an appropriate value
-before execution begins.
-
-@item -mpic-register=@var{reg}
-@opindex mpic-register
-Specify the register to be used for PIC addressing. The default is R10
-unless stack-checking is enabled, when R9 is used.
-
-@item -mcirrus-fix-invalid-insns
-@opindex mcirrus-fix-invalid-insns
-@opindex mno-cirrus-fix-invalid-insns
-Insert NOPs into the instruction stream to in order to work around
-problems with invalid Maverick instruction combinations. This option
-is only valid if the @option{-mcpu=ep9312} option has been used to
-enable generation of instructions for the Cirrus Maverick floating
-point co-processor. This option is not enabled by default, since the
-problem is only present in older Maverick implementations. The default
-can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
-switch.
-
-@item -mpoke-function-name
-@opindex mpoke-function-name
-Write the name of each function into the text section, directly
-preceding the function prologue. The generated code is similar to this:
-
-@smallexample
- t0
- .ascii "arm_poke_function_name", 0
- .align
- t1
- .word 0xff000000 + (t1 - t0)
- arm_poke_function_name
- mov ip, sp
- stmfd sp!, @{fp, ip, lr, pc@}
- sub fp, ip, #4
-@end smallexample
-
-When performing a stack backtrace, code can inspect the value of
-@code{pc} stored at @code{fp + 0}. If the trace function then looks at
-location @code{pc - 12} and the top 8 bits are set, then we know that
-there is a function name embedded immediately preceding this location
-and has length @code{((pc[-3]) & 0xff000000)}.
-
-@item -mthumb
-@opindex mthumb
-Generate code for the 16-bit Thumb instruction set. The default is to
-use the 32-bit ARM instruction set.
-
-@item -mtpcs-frame
-@opindex mtpcs-frame
-Generate a stack frame that is compliant with the Thumb Procedure Call
-Standard for all non-leaf functions. (A leaf function is one that does
-not call any other functions.) The default is @option{-mno-tpcs-frame}.
-
-@item -mtpcs-leaf-frame
-@opindex mtpcs-leaf-frame
-Generate a stack frame that is compliant with the Thumb Procedure Call
-Standard for all leaf functions. (A leaf function is one that does
-not call any other functions.) The default is @option{-mno-apcs-leaf-frame}.
-
-@item -mcallee-super-interworking
-@opindex mcallee-super-interworking
-Gives all externally visible functions in the file being compiled an ARM
-instruction set header which switches to Thumb mode before executing the
-rest of the function. This allows these functions to be called from
-non-interworking code.
-
-@item -mcaller-super-interworking
-@opindex mcaller-super-interworking
-Allows calls via function pointers (including virtual functions) to
-execute correctly regardless of whether the target code has been
-compiled for interworking or not. There is a small overhead in the cost
-of executing a function pointer if this option is enabled.
-
-@end table
-
-@node MN10300 Options
-@subsection MN10300 Options
-@cindex MN10300 options
+@item -all_load
+@opindex all_load
+Loads all members of static archive libraries.
+See man ld(1) for more information.
-These @option{-m} options are defined for Matsushita MN10300 architectures:
+@item -arch_errors_fatal
+@opindex arch_errors_fatal
+Cause the errors having to do with files that have the wrong architecture
+to be fatal.
-@table @gcctabopt
-@item -mmult-bug
-@opindex mmult-bug
-Generate code to avoid bugs in the multiply instructions for the MN10300
-processors. This is the default.
+@item -bind_at_load
+@opindex bind_at_load
+Causes the output file to be marked such that the dynamic linker will
+bind all undefined references when the file is loaded or launched.
-@item -mno-mult-bug
-@opindex mno-mult-bug
-Do not generate code to avoid bugs in the multiply instructions for the
-MN10300 processors.
+@item -bundle
+@opindex bundle
+Produce a Mach-o bundle format file.
+See man ld(1) for more information.
-@item -mam33
-@opindex mam33
-Generate code which uses features specific to the AM33 processor.
+@item -bundle_loader @var{executable}
+@opindex bundle_loader
+This specifies the @var{executable} that will be loading the build
+output file being linked. See man ld(1) for more information.
-@item -mno-am33
-@opindex mno-am33
-Do not generate code which uses features specific to the AM33 processor. This
-is the default.
+@item -allowable_client @var{client_name}
+@itemx -arch_only
-@item -mno-crt0
-@opindex mno-crt0
-Do not link in the C run-time initialization object file.
+@itemx -client_name
+@itemx -compatibility_version
+@itemx -current_version
+@itemx -dependency-file
+@itemx -dylib_file
+@itemx -dylinker_install_name
+@itemx -dynamic
+@itemx -dynamiclib
+@itemx -exported_symbols_list
+@itemx -filelist
+@itemx -flat_namespace
+@itemx -force_cpusubtype_ALL
+@itemx -force_flat_namespace
+@itemx -headerpad_max_install_names
+@itemx -image_base
+@itemx -init
+@itemx -install_name
+@itemx -keep_private_externs
+@itemx -multi_module
+@itemx -multiply_defined
+@itemx -multiply_defined_unused
+@itemx -noall_load
+@itemx -nofixprebinding
+@itemx -nomultidefs
+@itemx -noprebind
+@itemx -noseglinkedit
+@itemx -pagezero_size
+@itemx -prebind
+@itemx -prebind_all_twolevel_modules
+@itemx -private_bundle
+@itemx -read_only_relocs
+@itemx -sectalign
+@itemx -sectobjectsymbols
+@itemx -whyload
+@itemx -seg1addr
+@itemx -sectcreate
+@itemx -sectobjectsymbols
+@itemx -sectorder
+@itemx -seg_addr_table
+@itemx -seg_addr_table_filename
+@itemx -seglinkedit
+@itemx -segprot
+@itemx -segs_read_only_addr
+@itemx -segs_read_write_addr
+@itemx -single_module
+@itemx -static
+@itemx -sub_library
+@itemx -sub_umbrella
+@itemx -twolevel_namespace
+@itemx -umbrella
+@itemx -undefined
+@itemx -unexported_symbols_list
+@itemx -weak_reference_mismatches
+@itemx -whatsloaded
-@item -mrelax
-@opindex mrelax
-Indicate to the linker that it should perform a relaxation optimization pass
-to shorten branches, calls and absolute memory addresses. This option only
-has an effect when used on the command line for the final link step.
+@opindex allowable_client
+@opindex arch_only
+@opindex client_name
+@opindex compatibility_version
+@opindex current_version
+@opindex dependency-file
+@opindex dylib_file
+@opindex dylinker_install_name
+@opindex dynamic
+@opindex dynamiclib
+@opindex exported_symbols_list
+@opindex filelist
+@opindex flat_namespace
+@opindex force_cpusubtype_ALL
+@opindex force_flat_namespace
+@opindex headerpad_max_install_names
+@opindex image_base
+@opindex init
+@opindex install_name
+@opindex keep_private_externs
+@opindex multi_module
+@opindex multiply_defined
+@opindex multiply_defined_unused
+@opindex noall_load
+@opindex nofixprebinding
+@opindex nomultidefs
+@opindex noprebind
+@opindex noseglinkedit
+@opindex pagezero_size
+@opindex prebind
+@opindex prebind_all_twolevel_modules
+@opindex private_bundle
+@opindex read_only_relocs
+@opindex sectalign
+@opindex sectobjectsymbols
+@opindex whyload
+@opindex seg1addr
+@opindex sectcreate
+@opindex sectobjectsymbols
+@opindex sectorder
+@opindex seg_addr_table
+@opindex seg_addr_table_filename
+@opindex seglinkedit
+@opindex segprot
+@opindex segs_read_only_addr
+@opindex segs_read_write_addr
+@opindex single_module
+@opindex static
+@opindex sub_library
+@opindex sub_umbrella
+@opindex twolevel_namespace
+@opindex umbrella
+@opindex undefined
+@opindex unexported_symbols_list
+@opindex weak_reference_mismatches
+@opindex whatsloaded
-This option makes symbolic debugging impossible.
+These options are available for Darwin linker. Darwin linker man page
+describes them in detail.
@end table
+@node DEC Alpha Options
+@subsection DEC Alpha Options
-@node M32R/D Options
-@subsection M32R/D Options
-@cindex M32R/D options
-
-These @option{-m} options are defined for Renesas M32R/D architectures:
+These @samp{-m} options are defined for the DEC Alpha implementations:
@table @gcctabopt
-@item -m32r2
-@opindex m32r2
-Generate code for the M32R/2@.
+@item -mno-soft-float
+@itemx -msoft-float
+@opindex mno-soft-float
+@opindex msoft-float
+Use (do not use) the hardware floating-point instructions for
+floating-point operations. When @option{-msoft-float} is specified,
+functions in @file{libgcc.a} will be used to perform floating-point
+operations. Unless they are replaced by routines that emulate the
+floating-point operations, or compiled in such a way as to call such
+emulations routines, these routines will issue floating-point
+operations. If you are compiling for an Alpha without floating-point
+operations, you must ensure that the library is built so as not to call
+them.
-@item -m32rx
-@opindex m32rx
-Generate code for the M32R/X@.
+Note that Alpha implementations without floating-point operations are
+required to have floating-point registers.
-@item -m32r
-@opindex m32r
-Generate code for the M32R@. This is the default.
+@item -mfp-reg
+@itemx -mno-fp-regs
+@opindex mfp-reg
+@opindex mno-fp-regs
+Generate code that uses (does not use) the floating-point register set.
+@option{-mno-fp-regs} implies @option{-msoft-float}. If the floating-point
+register set is not used, floating point operands are passed in integer
+registers as if they were integers and floating-point results are passed
+in @code{$0} instead of @code{$f0}. This is a non-standard calling sequence,
+so any function with a floating-point argument or return value called by code
+compiled with @option{-mno-fp-regs} must also be compiled with that
+option.
-@item -mmodel=small
-@opindex mmodel=small
-Assume all objects live in the lower 16MB of memory (so that their addresses
-can be loaded with the @code{ld24} instruction), and assume all subroutines
-are reachable with the @code{bl} instruction.
-This is the default.
+A typical use of this option is building a kernel that does not use,
+and hence need not save and restore, any floating-point registers.
-The addressability of a particular object can be set with the
-@code{model} attribute.
+@item -mieee
+@opindex mieee
+The Alpha architecture implements floating-point hardware optimized for
+maximum performance. It is mostly compliant with the IEEE floating
+point standard. However, for full compliance, software assistance is
+required. This option generates code fully IEEE compliant code
+@emph{except} that the @var{inexact-flag} is not maintained (see below).
+If this option is turned on, the preprocessor macro @code{_IEEE_FP} is
+defined during compilation. The resulting code is less efficient but is
+able to correctly support denormalized numbers and exceptional IEEE
+values such as not-a-number and plus/minus infinity. Other Alpha
+compilers call this option @option{-ieee_with_no_inexact}.
-@item -mmodel=medium
-@opindex mmodel=medium
-Assume objects may be anywhere in the 32-bit address space (the compiler
-will generate @code{seth/add3} instructions to load their addresses), and
-assume all subroutines are reachable with the @code{bl} instruction.
+@item -mieee-with-inexact
+@opindex mieee-with-inexact
+This is like @option{-mieee} except the generated code also maintains
+the IEEE @var{inexact-flag}. Turning on this option causes the
+generated code to implement fully-compliant IEEE math. In addition to
+@code{_IEEE_FP}, @code{_IEEE_FP_EXACT} is defined as a preprocessor
+macro. On some Alpha implementations the resulting code may execute
+significantly slower than the code generated by default. Since there is
+very little code that depends on the @var{inexact-flag}, you should
+normally not specify this option. Other Alpha compilers call this
+option @option{-ieee_with_inexact}.
-@item -mmodel=large
-@opindex mmodel=large
-Assume objects may be anywhere in the 32-bit address space (the compiler
-will generate @code{seth/add3} instructions to load their addresses), and
-assume subroutines may not be reachable with the @code{bl} instruction
-(the compiler will generate the much slower @code{seth/add3/jl}
-instruction sequence).
+@item -mfp-trap-mode=@var{trap-mode}
+@opindex mfp-trap-mode
+This option controls what floating-point related traps are enabled.
+Other Alpha compilers call this option @option{-fptm @var{trap-mode}}.
+The trap mode can be set to one of four values:
-@item -msdata=none
-@opindex msdata=none
-Disable use of the small data area. Variables will be put into
-one of @samp{.data}, @samp{bss}, or @samp{.rodata} (unless the
-@code{section} attribute has been specified).
-This is the default.
+@table @samp
+@item n
+This is the default (normal) setting. The only traps that are enabled
+are the ones that cannot be disabled in software (e.g., division by zero
+trap).
-The small data area consists of sections @samp{.sdata} and @samp{.sbss}.
-Objects may be explicitly put in the small data area with the
-@code{section} attribute using one of these sections.
+@item u
+In addition to the traps enabled by @samp{n}, underflow traps are enabled
+as well.
-@item -msdata=sdata
-@opindex msdata=sdata
-Put small global and static data in the small data area, but do not
-generate special code to reference them.
+@item su
+Like @samp{su}, but the instructions are marked to be safe for software
+completion (see Alpha architecture manual for details).
-@item -msdata=use
-@opindex msdata=use
-Put small global and static data in the small data area, and generate
-special instructions to reference them.
+@item sui
+Like @samp{su}, but inexact traps are enabled as well.
+@end table
-@item -G @var{num}
-@opindex G
-@cindex smaller data references
-Put global and static objects less than or equal to @var{num} bytes
-into the small data or bss sections instead of the normal data or bss
-sections. The default value of @var{num} is 8.
-The @option{-msdata} option must be set to one of @samp{sdata} or @samp{use}
-for this option to have any effect.
+@item -mfp-rounding-mode=@var{rounding-mode}
+@opindex mfp-rounding-mode
+Selects the IEEE rounding mode. Other Alpha compilers call this option
+@option{-fprm @var{rounding-mode}}. The @var{rounding-mode} can be one
+of:
-All modules should be compiled with the same @option{-G @var{num}} value.
-Compiling with different values of @var{num} may or may not work; if it
-doesn't the linker will give an error message---incorrect code will not be
-generated.
+@table @samp
+@item n
+Normal IEEE rounding mode. Floating point numbers are rounded towards
+the nearest machine number or towards the even machine number in case
+of a tie.
-@item -mdebug
-@opindex -mdebug
-Makes the M32R specific code in the compiler display some statistics
-that might help in debugging programs.
+@item m
+Round towards minus infinity.
-@item -malign-loops
-@opindex malign-loops
-Align all loops to a 32-byte boundary.
+@item c
+Chopped rounding mode. Floating point numbers are rounded towards zero.
-@item -mno-align-loops
-@opindex mno-align-loops
-Do not enforce a 32-byte alignment for loops. This is the default.
+@item d
+Dynamic rounding mode. A field in the floating point control register
+(@var{fpcr}, see Alpha architecture reference manual) controls the
+rounding mode in effect. The C library initializes this register for
+rounding towards plus infinity. Thus, unless your program modifies the
+@var{fpcr}, @samp{d} corresponds to round towards plus infinity.
+@end table
-@item -missue-rate=@var{number}
-@opindex missue-rate=@var{number}
-Issue @var{number} instructions per cycle. @var{number} can only be 1
-or 2.
+@item -mtrap-precision=@var{trap-precision}
+@opindex mtrap-precision
+In the Alpha architecture, floating point traps are imprecise. This
+means without software assistance it is impossible to recover from a
+floating trap and program execution normally needs to be terminated.
+GCC can generate code that can assist operating system trap handlers
+in determining the exact location that caused a floating point trap.
+Depending on the requirements of an application, different levels of
+precisions can be selected:
-@item -mbranch-cost=@var{number}
-@opindex mbranch-cost=@var{number}
-@var{number} can only be 1 or 2. If it is 1 then branches will be
-preferred over conditional code, if it is 2, then the opposite will
-apply.
+@table @samp
+@item p
+Program precision. This option is the default and means a trap handler
+can only identify which program caused a floating point exception.
-@item -mflush-trap=@var{number}
-@opindex mflush-trap=@var{number}
-Specifies the trap number to use to flush the cache. The default is
-12. Valid numbers are between 0 and 15 inclusive.
+@item f
+Function precision. The trap handler can determine the function that
+caused a floating point exception.
-@item -mno-flush-trap
-@opindex mno-flush-trap
-Specifies that the cache cannot be flushed by using a trap.
+@item i
+Instruction precision. The trap handler can determine the exact
+instruction that caused a floating point exception.
+@end table
-@item -mflush-func=@var{name}
-@opindex mflush-func=@var{name}
-Specifies the name of the operating system function to call to flush
-the cache. The default is @emph{_flush_cache}, but a function call
-will only be used if a trap is not available.
+Other Alpha compilers provide the equivalent options called
+@option{-scope_safe} and @option{-resumption_safe}.
+
+@item -mieee-conformant
+@opindex mieee-conformant
+This option marks the generated code as IEEE conformant. You must not
+use this option unless you also specify @option{-mtrap-precision=i} and either
+@option{-mfp-trap-mode=su} or @option{-mfp-trap-mode=sui}. Its only effect
+is to emit the line @samp{.eflag 48} in the function prologue of the
+generated assembly file. Under DEC Unix, this has the effect that
+IEEE-conformant math library routines will be linked in.
-@item -mno-flush-func
-@opindex mno-flush-func
-Indicates that there is no OS function for flushing the cache.
+@item -mbuild-constants
+@opindex mbuild-constants
+Normally GCC examines a 32- or 64-bit integer constant to
+see if it can construct it from smaller constants in two or three
+instructions. If it cannot, it will output the constant as a literal and
+generate code to load it from the data segment at runtime.
-@end table
+Use this option to require GCC to construct @emph{all} integer constants
+using code, even if it takes more instructions (the maximum is six).
-@node RS/6000 and PowerPC Options
-@subsection IBM RS/6000 and PowerPC Options
-@cindex RS/6000 and PowerPC Options
-@cindex IBM RS/6000 and PowerPC Options
+You would typically use this option to build a shared library dynamic
+loader. Itself a shared library, it must relocate itself in memory
+before it can find the variables and constants in its own data segment.
-These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
-@table @gcctabopt
-@item -mpower
-@itemx -mno-power
-@itemx -mpower2
-@itemx -mno-power2
-@itemx -mpowerpc
-@itemx -mno-powerpc
-@itemx -mpowerpc-gpopt
-@itemx -mno-powerpc-gpopt
-@itemx -mpowerpc-gfxopt
-@itemx -mno-powerpc-gfxopt
-@itemx -mpowerpc64
-@itemx -mno-powerpc64
-@opindex mpower
-@opindex mno-power
-@opindex mpower2
-@opindex mno-power2
-@opindex mpowerpc
-@opindex mno-powerpc
-@opindex mpowerpc-gpopt
-@opindex mno-powerpc-gpopt
-@opindex mpowerpc-gfxopt
-@opindex mno-powerpc-gfxopt
-@opindex mpowerpc64
-@opindex mno-powerpc64
-GCC supports two related instruction set architectures for the
-RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
-instructions supported by the @samp{rios} chip set used in the original
-RS/6000 systems and the @dfn{PowerPC} instruction set is the
-architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
-the IBM 4xx microprocessors.
+@item -malpha-as
+@itemx -mgas
+@opindex malpha-as
+@opindex mgas
+Select whether to generate code to be assembled by the vendor-supplied
+assembler (@option{-malpha-as}) or by the GNU assembler @option{-mgas}.
-Neither architecture is a subset of the other. However there is a
-large common subset of instructions supported by both. An MQ
-register is included in processors supporting the POWER architecture.
+@item -mbwx
+@itemx -mno-bwx
+@itemx -mcix
+@itemx -mno-cix
+@itemx -mfix
+@itemx -mno-fix
+@itemx -mmax
+@itemx -mno-max
+@opindex mbwx
+@opindex mno-bwx
+@opindex mcix
+@opindex mno-cix
+@opindex mfix
+@opindex mno-fix
+@opindex mmax
+@opindex mno-max
+Indicate whether GCC should generate code to use the optional BWX,
+CIX, FIX and MAX instruction sets. The default is to use the instruction
+sets supported by the CPU type specified via @option{-mcpu=} option or that
+of the CPU on which GCC was built if none was specified.
-You use these options to specify which instructions are available on the
-processor you are using. The default value of these options is
-determined when configuring GCC@. Specifying the
-@option{-mcpu=@var{cpu_type}} overrides the specification of these
-options. We recommend you use the @option{-mcpu=@var{cpu_type}} option
-rather than the options listed above.
+@item -mfloat-vax
+@itemx -mfloat-ieee
+@opindex mfloat-vax
+@opindex mfloat-ieee
+Generate code that uses (does not use) VAX F and G floating point
+arithmetic instead of IEEE single and double precision.
-The @option{-mpower} option allows GCC to generate instructions that
-are found only in the POWER architecture and to use the MQ register.
-Specifying @option{-mpower2} implies @option{-power} and also allows GCC
-to generate instructions that are present in the POWER2 architecture but
-not the original POWER architecture.
+@item -mexplicit-relocs
+@itemx -mno-explicit-relocs
+@opindex mexplicit-relocs
+@opindex mno-explicit-relocs
+Older Alpha assemblers provided no way to generate symbol relocations
+except via assembler macros. Use of these macros does not allow
+optimal instruction scheduling. GNU binutils as of version 2.12
+supports a new syntax that allows the compiler to explicitly mark
+which relocations should apply to which instructions. This option
+is mostly useful for debugging, as GCC detects the capabilities of
+the assembler when it is built and sets the default accordingly.
-The @option{-mpowerpc} option allows GCC to generate instructions that
-are found only in the 32-bit subset of the PowerPC architecture.
-Specifying @option{-mpowerpc-gpopt} implies @option{-mpowerpc} and also allows
-GCC to use the optional PowerPC architecture instructions in the
-General Purpose group, including floating-point square root. Specifying
-@option{-mpowerpc-gfxopt} implies @option{-mpowerpc} and also allows GCC to
-use the optional PowerPC architecture instructions in the Graphics
-group, including floating-point select.
+@item -msmall-data
+@itemx -mlarge-data
+@opindex msmall-data
+@opindex mlarge-data
+When @option{-mexplicit-relocs} is in effect, static data is
+accessed via @dfn{gp-relative} relocations. When @option{-msmall-data}
+is used, objects 8 bytes long or smaller are placed in a @dfn{small data area}
+(the @code{.sdata} and @code{.sbss} sections) and are accessed via
+16-bit relocations off of the @code{$gp} register. This limits the
+size of the small data area to 64KB, but allows the variables to be
+directly accessed via a single instruction.
-The @option{-mpowerpc64} option allows GCC to generate the additional
-64-bit instructions that are found in the full PowerPC64 architecture
-and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
-@option{-mno-powerpc64}.
+The default is @option{-mlarge-data}. With this option the data area
+is limited to just below 2GB. Programs that require more than 2GB of
+data must use @code{malloc} or @code{mmap} to allocate the data in the
+heap instead of in the program's data segment.
-If you specify both @option{-mno-power} and @option{-mno-powerpc}, GCC
-will use only the instructions in the common subset of both
-architectures plus some special AIX common-mode calls, and will not use
-the MQ register. Specifying both @option{-mpower} and @option{-mpowerpc}
-permits GCC to use any instruction from either architecture and to
-allow use of the MQ register; specify this for the Motorola MPC601.
+When generating code for shared libraries, @option{-fpic} implies
+@option{-msmall-data} and @option{-fPIC} implies @option{-mlarge-data}.
-@item -mnew-mnemonics
-@itemx -mold-mnemonics
-@opindex mnew-mnemonics
-@opindex mold-mnemonics
-Select which mnemonics to use in the generated assembler code. With
-@option{-mnew-mnemonics}, GCC uses the assembler mnemonics defined for
-the PowerPC architecture. With @option{-mold-mnemonics} it uses the
-assembler mnemonics defined for the POWER architecture. Instructions
-defined in only one architecture have only one mnemonic; GCC uses that
-mnemonic irrespective of which of these options is specified.
+@item -msmall-text
+@itemx -mlarge-text
+@opindex msmall-text
+@opindex mlarge-text
+When @option{-msmall-text} is used, the compiler assumes that the
+code of the entire program (or shared library) fits in 4MB, and is
+thus reachable with a branch instruction. When @option{-msmall-data}
+is used, the compiler can assume that all local symbols share the
+same @code{$gp} value, and thus reduce the number of instructions
+required for a function call from 4 to 1.
-GCC defaults to the mnemonics appropriate for the architecture in
-use. Specifying @option{-mcpu=@var{cpu_type}} sometimes overrides the
-value of these option. Unless you are building a cross-compiler, you
-should normally not specify either @option{-mnew-mnemonics} or
-@option{-mold-mnemonics}, but should instead accept the default.
+The default is @option{-mlarge-text}.
@item -mcpu=@var{cpu_type}
@opindex mcpu
-Set architecture type, register usage, choice of mnemonics, and
-instruction scheduling parameters for machine type @var{cpu_type}.
-Supported values for @var{cpu_type} are @samp{401}, @samp{403},
-@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{505},
-@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
-@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
-@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
-@samp{860}, @samp{970}, @samp{common}, @samp{ec603e}, @samp{G3},
-@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
-@samp{power4}, @samp{powerpc}, @samp{powerpc64}, @samp{rios},
-@samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}.
-
-@option{-mcpu=common} selects a completely generic processor. Code
-generated under this option will run on any POWER or PowerPC processor.
-GCC will use only the instructions in the common subset of both
-architectures, and will not use the MQ register. GCC assumes a generic
-processor model for scheduling purposes.
+Set the instruction set and instruction scheduling parameters for
+machine type @var{cpu_type}. You can specify either the @samp{EV}
+style name or the corresponding chip number. GCC supports scheduling
+parameters for the EV4, EV5 and EV6 family of processors and will
+choose the default values for the instruction set from the processor
+you specify. If you do not specify a processor type, GCC will default
+to the processor on which the compiler was built.
-@option{-mcpu=power}, @option{-mcpu=power2}, @option{-mcpu=powerpc}, and
-@option{-mcpu=powerpc64} specify generic POWER, POWER2, pure 32-bit
-PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine
-types, with an appropriate, generic processor model assumed for
-scheduling purposes.
+Supported values for @var{cpu_type} are
-The other options specify a specific processor. Code generated under
-those options will run best on that processor, and may not run at all on
-others.
+@table @samp
+@item ev4
+@itemx ev45
+@itemx 21064
+Schedules as an EV4 and has no instruction set extensions.
-The @option{-mcpu} options automatically enable or disable the
-following options: @option{-maltivec}, @option{-mhard-float},
-@option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
-@option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
-@option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
-@option{-mstring}. The particular options set for any particular CPU
-will vary between compiler versions, depending on what setting seems
-to produce optimal code for that CPU; it doesn't necessarily reflect
-the actual hardware's capabilities. If you wish to set an individual
-option to a particular value, you may specify it after the
-@option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
+@item ev5
+@itemx 21164
+Schedules as an EV5 and has no instruction set extensions.
-On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
-not enabled or disabled by the @option{-mcpu} option at present, since
-AIX does not have full support for these options. You may still
-enable or disable them individually if you're sure it'll work in your
-environment.
+@item ev56
+@itemx 21164a
+Schedules as an EV5 and supports the BWX extension.
-@item -mtune=@var{cpu_type}
-@opindex mtune
-Set the instruction scheduling parameters for machine type
-@var{cpu_type}, but do not set the architecture type, register usage, or
-choice of mnemonics, as @option{-mcpu=@var{cpu_type}} would. The same
-values for @var{cpu_type} are used for @option{-mtune} as for
-@option{-mcpu}. If both are specified, the code generated will use the
-architecture, registers, and mnemonics set by @option{-mcpu}, but the
-scheduling parameters set by @option{-mtune}.
+@item pca56
+@itemx 21164pc
+@itemx 21164PC
+Schedules as an EV5 and supports the BWX and MAX extensions.
-@item -maltivec
-@itemx -mno-altivec
-@opindex maltivec
-@opindex mno-altivec
-These switches enable or disable the use of built-in functions that
-allow access to the AltiVec instruction set. You may also need to set
-@option{-mabi=altivec} to adjust the current ABI with AltiVec ABI
-enhancements.
+@item ev6
+@itemx 21264
+Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
-@item -mabi=spe
-@opindex mabi=spe
-Extend the current ABI with SPE ABI extensions. This does not change
-the default ABI, instead it adds the SPE ABI extensions to the current
-ABI@.
+@item ev67
+@itemx 21264a
+Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
+@end table
-@item -mabi=no-spe
-@opindex mabi=no-spe
-Disable Booke SPE ABI extensions for the current ABI.
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set only the instruction scheduling parameters for machine type
+@var{cpu_type}. The instruction set is not changed.
-@item -misel=@var{yes/no}
-@itemx -misel
-@opindex misel
-This switch enables or disables the generation of ISEL instructions.
+@item -mmemory-latency=@var{time}
+@opindex mmemory-latency
+Sets the latency the scheduler should assume for typical memory
+references as seen by the application. This number is highly
+dependent on the memory access patterns used by the application
+and the size of the external cache on the machine.
-@item -mspe=@var{yes/no}
-@itemx -mspe
-@opindex mspe
-This switch enables or disables the generation of SPE simd
-instructions.
+Valid options for @var{time} are
-@item -mfloat-gprs=@var{yes/no}
-@itemx -mfloat-gprs
-@opindex mfloat-gprs
-This switch enables or disables the generation of floating point
-operations on the general purpose registers for architectures that
-support it. This option is currently only available on the MPC8540.
+@table @samp
+@item @var{number}
+A decimal number representing clock cycles.
-@item -mfull-toc
-@itemx -mno-fp-in-toc
-@itemx -mno-sum-in-toc
-@itemx -mminimal-toc
-@opindex mfull-toc
-@opindex mno-fp-in-toc
-@opindex mno-sum-in-toc
-@opindex mminimal-toc
-Modify generation of the TOC (Table Of Contents), which is created for
-every executable file. The @option{-mfull-toc} option is selected by
-default. In that case, GCC will allocate at least one TOC entry for
-each unique non-automatic variable reference in your program. GCC
-will also place floating-point constants in the TOC@. However, only
-16,384 entries are available in the TOC@.
+@item L1
+@itemx L2
+@itemx L3
+@itemx main
+The compiler contains estimates of the number of clock cycles for
+``typical'' EV4 & EV5 hardware for the Level 1, 2 & 3 caches
+(also called Dcache, Scache, and Bcache), as well as to main memory.
+Note that L3 is only valid for EV5.
-If you receive a linker error message that saying you have overflowed
-the available TOC space, you can reduce the amount of TOC space used
-with the @option{-mno-fp-in-toc} and @option{-mno-sum-in-toc} options.
-@option{-mno-fp-in-toc} prevents GCC from putting floating-point
-constants in the TOC and @option{-mno-sum-in-toc} forces GCC to
-generate code to calculate the sum of an address and a constant at
-run-time instead of putting that sum into the TOC@. You may specify one
-or both of these options. Each causes GCC to produce very slightly
-slower and larger code at the expense of conserving TOC space.
+@end table
+@end table
-If you still run out of space in the TOC even when you specify both of
-these options, specify @option{-mminimal-toc} instead. This option causes
-GCC to make only one TOC entry for every file. When you specify this
-option, GCC will produce code that is slower and larger but which
-uses extremely little TOC space. You may wish to use this option
-only on files that contain less frequently executed code.
+@node DEC Alpha/VMS Options
+@subsection DEC Alpha/VMS Options
-@item -maix64
-@itemx -maix32
-@opindex maix64
-@opindex maix32
-Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit
-@code{long} type, and the infrastructure needed to support them.
-Specifying @option{-maix64} implies @option{-mpowerpc64} and
-@option{-mpowerpc}, while @option{-maix32} disables the 64-bit ABI and
-implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}.
+These @samp{-m} options are defined for the DEC Alpha/VMS implementations:
-@item -mxl-call
-@itemx -mno-xl-call
-@opindex mxl-call
-@opindex mno-xl-call
-On AIX, pass floating-point arguments to prototyped functions beyond the
-register save area (RSA) on the stack in addition to argument FPRs. The
-AIX calling convention was extended but not initially documented to
-handle an obscure K&R C case of calling a function that takes the
-address of its arguments with fewer arguments than declared. AIX XL
-compilers access floating point arguments which do not fit in the
-RSA from the stack when a subroutine is compiled without
-optimization. Because always storing floating-point arguments on the
-stack is inefficient and rarely needed, this option is not enabled by
-default and only is necessary when calling subroutines compiled by AIX
-XL compilers without optimization.
+@table @gcctabopt
+@item -mvms-return-codes
+@opindex mvms-return-codes
+Return VMS condition codes from main. The default is to return POSIX
+style condition (e.g.@ error) codes.
+@end table
-@item -mpe
-@opindex mpe
-Support @dfn{IBM RS/6000 SP} @dfn{Parallel Environment} (PE)@. Link an
-application written to use message passing with special startup code to
-enable the application to run. The system must have PE installed in the
-standard location (@file{/usr/lpp/ppe.poe/}), or the @file{specs} file
-must be overridden with the @option{-specs=} option to specify the
-appropriate directory location. The Parallel Environment does not
-support threads, so the @option{-mpe} option and the @option{-pthread}
-option are incompatible.
+@node FRV Options
+@subsection FRV Options
+@cindex FRV Options
-@item -malign-natural
-@itemx -malign-power
-@opindex malign-natural
-@opindex malign-power
-On AIX, Darwin, and 64-bit PowerPC GNU/Linux, the option
-@option{-malign-natural} overrides the ABI-defined alignment of larger
-types, such as floating-point doubles, on their natural size-based boundary.
-The option @option{-malign-power} instructs GCC to follow the ABI-specified
-alignment rules. GCC defaults to the standard alignment defined in the ABI.
+@table @gcctabopt
+@item -mgpr-32
+@opindex mgpr-32
-@item -msoft-float
-@itemx -mhard-float
-@opindex msoft-float
-@opindex mhard-float
-Generate code that does not use (uses) the floating-point register set.
-Software floating point emulation is provided if you use the
-@option{-msoft-float} option, and pass the option to GCC when linking.
+Only use the first 32 general purpose registers.
-@item -mmultiple
-@itemx -mno-multiple
-@opindex mmultiple
-@opindex mno-multiple
-Generate code that uses (does not use) the load multiple word
-instructions and the store multiple word instructions. These
-instructions are generated by default on POWER systems, and not
-generated on PowerPC systems. Do not use @option{-mmultiple} on little
-endian PowerPC systems, since those instructions do not work when the
-processor is in little endian mode. The exceptions are PPC740 and
-PPC750 which permit the instructions usage in little endian mode.
+@item -mgpr-64
+@opindex mgpr-64
-@item -mstring
-@itemx -mno-string
-@opindex mstring
-@opindex mno-string
-Generate code that uses (does not use) the load string instructions
-and the store string word instructions to save multiple registers and
-do small block moves. These instructions are generated by default on
-POWER systems, and not generated on PowerPC systems. Do not use
-@option{-mstring} on little endian PowerPC systems, since those
-instructions do not work when the processor is in little endian mode.
-The exceptions are PPC740 and PPC750 which permit the instructions
-usage in little endian mode.
+Use all 64 general purpose registers.
-@item -mupdate
-@itemx -mno-update
-@opindex mupdate
-@opindex mno-update
-Generate code that uses (does not use) the load or store instructions
-that update the base register to the address of the calculated memory
-location. These instructions are generated by default. If you use
-@option{-mno-update}, there is a small window between the time that the
-stack pointer is updated and the address of the previous frame is
-stored, which means code that walks the stack frame across interrupts or
-signals may get corrupted data.
+@item -mfpr-32
+@opindex mfpr-32
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Generate code that uses (does not use) the floating point multiply and
-accumulate instructions. These instructions are generated by default if
-hardware floating is used.
+Use only the first 32 floating point registers.
-@item -mno-bit-align
-@itemx -mbit-align
-@opindex mno-bit-align
-@opindex mbit-align
-On System V.4 and embedded PowerPC systems do not (do) force structures
-and unions that contain bit-fields to be aligned to the base type of the
-bit-field.
+@item -mfpr-64
+@opindex mfpr-64
-For example, by default a structure containing nothing but 8
-@code{unsigned} bit-fields of length 1 would be aligned to a 4 byte
-boundary and have a size of 4 bytes. By using @option{-mno-bit-align},
-the structure would be aligned to a 1 byte boundary and be one byte in
-size.
+Use all 64 floating point registers
-@item -mno-strict-align
-@itemx -mstrict-align
-@opindex mno-strict-align
-@opindex mstrict-align
-On System V.4 and embedded PowerPC systems do not (do) assume that
-unaligned memory references will be handled by the system.
+@item -mhard-float
+@opindex mhard-float
-@item -mrelocatable
-@itemx -mno-relocatable
-@opindex mrelocatable
-@opindex mno-relocatable
-On embedded PowerPC systems generate code that allows (does not allow)
-the program to be relocated to a different address at runtime. If you
-use @option{-mrelocatable} on any module, all objects linked together must
-be compiled with @option{-mrelocatable} or @option{-mrelocatable-lib}.
+Use hardware instructions for floating point operations.
-@item -mrelocatable-lib
-@itemx -mno-relocatable-lib
-@opindex mrelocatable-lib
-@opindex mno-relocatable-lib
-On embedded PowerPC systems generate code that allows (does not allow)
-the program to be relocated to a different address at runtime. Modules
-compiled with @option{-mrelocatable-lib} can be linked with either modules
-compiled without @option{-mrelocatable} and @option{-mrelocatable-lib} or
-with modules compiled with the @option{-mrelocatable} options.
+@item -msoft-float
+@opindex msoft-float
-@item -mno-toc
-@itemx -mtoc
-@opindex mno-toc
-@opindex mtoc
-On System V.4 and embedded PowerPC systems do not (do) assume that
-register 2 contains a pointer to a global area pointing to the addresses
-used in the program.
+Use library routines for floating point operations.
-@item -mlittle
-@itemx -mlittle-endian
-@opindex mlittle
-@opindex mlittle-endian
-On System V.4 and embedded PowerPC systems compile code for the
-processor in little endian mode. The @option{-mlittle-endian} option is
-the same as @option{-mlittle}.
+@item -malloc-cc
+@opindex malloc-cc
-@item -mbig
-@itemx -mbig-endian
-@opindex mbig
-@opindex mbig-endian
-On System V.4 and embedded PowerPC systems compile code for the
-processor in big endian mode. The @option{-mbig-endian} option is
-the same as @option{-mbig}.
+Dynamically allocate condition code registers.
-@item -mdynamic-no-pic
-@opindex mdynamic-no-pic
-On Darwin and Mac OS X systems, compile code so that it is not
-relocatable, but that its external references are relocatable. The
-resulting code is suitable for applications, but not shared
-libraries.
+@item -mfixed-cc
+@opindex mfixed-cc
-@item -mprioritize-restricted-insns=@var{priority}
-@opindex mprioritize-restricted-insns
-This option controls the priority that is assigned to
-dispatch-slot restricted instructions during the second scheduling
-pass. The argument @var{priority} takes the value @var{0/1/2} to assign
-@var{no/highest/second-highest} priority to dispatch slot restricted
-instructions.
+Do not try to dynamically allocate condition code registers, only
+use @code{icc0} and @code{fcc0}.
-@item -msched-costly-dep=@var{dependence_type}
-@opindex msched-costly-dep
-This option controls which dependences are considered costly
-by the target during instruction scheduling. The argument
-@var{dependence_type} takes one of the following values:
-@var{no}: no dependence is costly,
-@var{all}: all dependences are costly,
-@var{true_store_to_load}: a true dependence from store to load is costly,
-@var{store_to_load}: any dependence from store to load is costly,
-@var{number}: any dependence which latency >= @var{number} is costly.
+@item -mdword
+@opindex mdword
-@item -minsert-sched-nops=@var{scheme}
-@opindex minsert-sched-nops
-This option controls which nop insertion scheme will be used during
-the second scheduling pass. The argument @var{scheme} takes one of the
-following values:
-@var{no}: Don't insert nops.
-@var{pad}: Pad with nops any dispatch group which has vacant issue slots,
-according to the scheduler's grouping.
-@var{regroup_exact}: Insert nops to force costly dependent insns into
-separate groups. Insert exactly as many nops as needed to force an insn
-to a new group, according to the estimated processor grouping.
-@var{number}: Insert nops to force costly dependent insns into
-separate groups. Insert @var{number} nops to force an insn to a new group.
+Change ABI to use double word insns.
-@item -mcall-sysv
-@opindex mcall-sysv
-On System V.4 and embedded PowerPC systems compile code using calling
-conventions that adheres to the March 1995 draft of the System V
-Application Binary Interface, PowerPC processor supplement. This is the
-default unless you configured GCC using @samp{powerpc-*-eabiaix}.
+@item -mno-dword
+@opindex mno-dword
-@item -mcall-sysv-eabi
-@opindex mcall-sysv-eabi
-Specify both @option{-mcall-sysv} and @option{-meabi} options.
+Do not use double word instructions.
-@item -mcall-sysv-noeabi
-@opindex mcall-sysv-noeabi
-Specify both @option{-mcall-sysv} and @option{-mno-eabi} options.
+@item -mdouble
+@opindex mdouble
-@item -mcall-solaris
-@opindex mcall-solaris
-On System V.4 and embedded PowerPC systems compile code for the Solaris
-operating system.
+Use floating point double instructions.
-@item -mcall-linux
-@opindex mcall-linux
-On System V.4 and embedded PowerPC systems compile code for the
-Linux-based GNU system.
+@item -mno-double
+@opindex mno-double
-@item -mcall-gnu
-@opindex mcall-gnu
-On System V.4 and embedded PowerPC systems compile code for the
-Hurd-based GNU system.
+Do not use floating point double instructions.
-@item -mcall-netbsd
-@opindex mcall-netbsd
-On System V.4 and embedded PowerPC systems compile code for the
-NetBSD operating system.
+@item -mmedia
+@opindex mmedia
-@item -maix-struct-return
-@opindex maix-struct-return
-Return all structures in memory (as specified by the AIX ABI)@.
+Use media instructions.
-@item -msvr4-struct-return
-@opindex msvr4-struct-return
-Return structures smaller than 8 bytes in registers (as specified by the
-SVR4 ABI)@.
+@item -mno-media
+@opindex mno-media
-@item -mabi=altivec
-@opindex mabi=altivec
-Extend the current ABI with AltiVec ABI extensions. This does not
-change the default ABI, instead it adds the AltiVec ABI extensions to
-the current ABI@.
+Do not use media instructions.
-@item -mabi=no-altivec
-@opindex mabi=no-altivec
-Disable AltiVec ABI extensions for the current ABI.
+@item -mmuladd
+@opindex mmuladd
-@item -mprototype
-@itemx -mno-prototype
-@opindex mprototype
-@opindex mno-prototype
-On System V.4 and embedded PowerPC systems assume that all calls to
-variable argument functions are properly prototyped. Otherwise, the
-compiler must insert an instruction before every non prototyped call to
-set or clear bit 6 of the condition code register (@var{CR}) to
-indicate whether floating point values were passed in the floating point
-registers in case the function takes a variable arguments. With
-@option{-mprototype}, only calls to prototyped variable argument functions
-will set or clear the bit.
+Use multiply and add/subtract instructions.
-@item -msim
-@opindex msim
-On embedded PowerPC systems, assume that the startup module is called
-@file{sim-crt0.o} and that the standard C libraries are @file{libsim.a} and
-@file{libc.a}. This is the default for @samp{powerpc-*-eabisim}.
-configurations.
+@item -mno-muladd
+@opindex mno-muladd
-@item -mmvme
-@opindex mmvme
-On embedded PowerPC systems, assume that the startup module is called
-@file{crt0.o} and the standard C libraries are @file{libmvme.a} and
-@file{libc.a}.
+Do not use multiply and add/subtract instructions.
-@item -mads
-@opindex mads
-On embedded PowerPC systems, assume that the startup module is called
-@file{crt0.o} and the standard C libraries are @file{libads.a} and
-@file{libc.a}.
+@item -mlibrary-pic
+@opindex mlibrary-pic
-@item -myellowknife
-@opindex myellowknife
-On embedded PowerPC systems, assume that the startup module is called
-@file{crt0.o} and the standard C libraries are @file{libyk.a} and
-@file{libc.a}.
+Generate position-independent EABI code.
-@item -mvxworks
-@opindex mvxworks
-On System V.4 and embedded PowerPC systems, specify that you are
-compiling for a VxWorks system.
+@item -macc-4
+@opindex macc-4
-@item -mwindiss
-@opindex mwindiss
-Specify that you are compiling for the WindISS simulation environment.
+Use only the first four media accumulator registers.
-@item -memb
-@opindex memb
-On embedded PowerPC systems, set the @var{PPC_EMB} bit in the ELF flags
-header to indicate that @samp{eabi} extended relocations are used.
+@item -macc-8
+@opindex macc-8
-@item -meabi
-@itemx -mno-eabi
-@opindex meabi
-@opindex mno-eabi
-On System V.4 and embedded PowerPC systems do (do not) adhere to the
-Embedded Applications Binary Interface (eabi) which is a set of
-modifications to the System V.4 specifications. Selecting @option{-meabi}
-means that the stack is aligned to an 8 byte boundary, a function
-@code{__eabi} is called to from @code{main} to set up the eabi
-environment, and the @option{-msdata} option can use both @code{r2} and
-@code{r13} to point to two separate small data areas. Selecting
-@option{-mno-eabi} means that the stack is aligned to a 16 byte boundary,
-do not call an initialization function from @code{main}, and the
-@option{-msdata} option will only use @code{r13} to point to a single
-small data area. The @option{-meabi} option is on by default if you
-configured GCC using one of the @samp{powerpc*-*-eabi*} options.
+Use all eight media accumulator registers.
-@item -msdata=eabi
-@opindex msdata=eabi
-On System V.4 and embedded PowerPC systems, put small initialized
-@code{const} global and static data in the @samp{.sdata2} section, which
-is pointed to by register @code{r2}. Put small initialized
-non-@code{const} global and static data in the @samp{.sdata} section,
-which is pointed to by register @code{r13}. Put small uninitialized
-global and static data in the @samp{.sbss} section, which is adjacent to
-the @samp{.sdata} section. The @option{-msdata=eabi} option is
-incompatible with the @option{-mrelocatable} option. The
-@option{-msdata=eabi} option also sets the @option{-memb} option.
+@item -mpack
+@opindex mpack
-@item -msdata=sysv
-@opindex msdata=sysv
-On System V.4 and embedded PowerPC systems, put small global and static
-data in the @samp{.sdata} section, which is pointed to by register
-@code{r13}. Put small uninitialized global and static data in the
-@samp{.sbss} section, which is adjacent to the @samp{.sdata} section.
-The @option{-msdata=sysv} option is incompatible with the
-@option{-mrelocatable} option.
+Pack VLIW instructions.
-@item -msdata=default
-@itemx -msdata
-@opindex msdata=default
-@opindex msdata
-On System V.4 and embedded PowerPC systems, if @option{-meabi} is used,
-compile code the same as @option{-msdata=eabi}, otherwise compile code the
-same as @option{-msdata=sysv}.
+@item -mno-pack
+@opindex mno-pack
-@item -msdata-data
-@opindex msdata-data
-On System V.4 and embedded PowerPC systems, put small global and static
-data in the @samp{.sdata} section. Put small uninitialized global and
-static data in the @samp{.sbss} section. Do not use register @code{r13}
-to address small data however. This is the default behavior unless
-other @option{-msdata} options are used.
+Do not pack VLIW instructions.
-@item -msdata=none
-@itemx -mno-sdata
-@opindex msdata=none
-@opindex mno-sdata
-On embedded PowerPC systems, put all initialized global and static data
-in the @samp{.data} section, and all uninitialized data in the
-@samp{.bss} section.
+@item -mno-eflags
+@opindex mno-eflags
-@item -G @var{num}
-@opindex G
-@cindex smaller data references (PowerPC)
-@cindex .sdata/.sdata2 references (PowerPC)
-On embedded PowerPC systems, put global and static items less than or
-equal to @var{num} bytes into the small data or bss sections instead of
-the normal data or bss section. By default, @var{num} is 8. The
-@option{-G @var{num}} switch is also passed to the linker.
-All modules should be compiled with the same @option{-G @var{num}} value.
+Do not mark ABI switches in e_flags.
-@item -mregnames
-@itemx -mno-regnames
-@opindex mregnames
-@opindex mno-regnames
-On System V.4 and embedded PowerPC systems do (do not) emit register
-names in the assembly language output using symbolic forms.
+@item -mcond-move
+@opindex mcond-move
-@item -mlongcall
-@itemx -mno-longcall
-@opindex mlongcall
-@opindex mno-longcall
-Default to making all function calls indirectly, using a register, so
-that functions which reside further than 32 megabytes (33,554,432
-bytes) from the current location can be called. This setting can be
-overridden by the @code{shortcall} function attribute, or by
-@code{#pragma longcall(0)}.
+Enable the use of conditional-move instructions (default).
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mno-cond-move
+@opindex mno-cond-move
-Some linkers are capable of detecting out-of-range calls and generating
-glue code on the fly. On these systems, long calls are unnecessary and
-generate slower code. As of this writing, the AIX linker can do this,
-as can the GNU linker for PowerPC/64. It is planned to add this feature
-to the GNU linker for 32-bit PowerPC systems as well.
+Disable the use of conditional-move instructions.
-On Darwin/PPC systems, @code{#pragma longcall} will generate ``jbsr
-callee, L42'', plus a ``branch island'' (glue code). The two target
-addresses represent the callee and the ``branch island.'' The
-Darwin/PPC linker will prefer the first address and generate a ``bl
-callee'' if the PPC ``bl'' instruction will reach the callee directly;
-otherwise, the linker will generate ``bl L42'' to call the ``branch
-island.'' The ``branch island'' is appended to the body of the
-calling function; it computes the full 32-bit address of the callee
-and jumps to it.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-On Mach-O (Darwin) systems, this option directs the compiler emit to
-the glue for every direct call, and the Darwin linker decides whether
-to use or discard it.
+@item -mscc
+@opindex mscc
-In the future, we may cause GCC to ignore all longcall specifications
-when the linker is known to generate glue.
+Enable the use of conditional set instructions (default).
-@item -pthread
-@opindex pthread
-Adds support for multithreading with the @dfn{pthreads} library.
-This option sets flags for both the preprocessor and linker.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@end table
+@item -mno-scc
+@opindex mno-scc
-@node Darwin Options
-@subsection Darwin Options
-@cindex Darwin options
+Disable the use of conditional set instructions.
-These options are defined for all architectures running the Darwin operating
-system. They are useful for compatibility with other Mac OS compilers.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@table @gcctabopt
-@item -all_load
-@opindex all_load
-Loads all members of static archive libraries.
-See man ld(1) for more information.
+@item -mcond-exec
+@opindex mcond-exec
-@item -arch_errors_fatal
-@opindex arch_errors_fatal
-Cause the errors having to do with files that have the wrong architecture
-to be fatal.
+Enable the use of conditional execution (default).
-@item -bind_at_load
-@opindex bind_at_load
-Causes the output file to be marked such that the dynamic linker will
-bind all undefined references when the file is loaded or launched.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -bundle
-@opindex bundle
-Produce a Mach-o bundle format file.
-See man ld(1) for more information.
+@item -mno-cond-exec
+@opindex mno-cond-exec
-@item -bundle_loader @var{executable}
-@opindex bundle_loader
-This specifies the @var{executable} that will be loading the build
-output file being linked. See man ld(1) for more information.
+Disable the use of conditional execution.
-@item -allowable_client @var{client_name}
-@itemx -arch_only
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@itemx -client_name
-@itemx -compatibility_version
-@itemx -current_version
-@itemx -dependency-file
-@itemx -dylib_file
-@itemx -dylinker_install_name
-@itemx -dynamic
-@itemx -dynamiclib
-@itemx -exported_symbols_list
-@itemx -filelist
-@itemx -flat_namespace
-@itemx -force_cpusubtype_ALL
-@itemx -force_flat_namespace
-@itemx -headerpad_max_install_names
-@itemx -image_base
-@itemx -init
-@itemx -install_name
-@itemx -keep_private_externs
-@itemx -multi_module
-@itemx -multiply_defined
-@itemx -multiply_defined_unused
-@itemx -noall_load
-@itemx -nofixprebinding
-@itemx -nomultidefs
-@itemx -noprebind
-@itemx -noseglinkedit
-@itemx -pagezero_size
-@itemx -prebind
-@itemx -prebind_all_twolevel_modules
-@itemx -private_bundle
-@itemx -read_only_relocs
-@itemx -sectalign
-@itemx -sectobjectsymbols
-@itemx -whyload
-@itemx -seg1addr
-@itemx -sectcreate
-@itemx -sectobjectsymbols
-@itemx -sectorder
-@itemx -seg_addr_table
-@itemx -seg_addr_table_filename
-@itemx -seglinkedit
-@itemx -segprot
-@itemx -segs_read_only_addr
-@itemx -segs_read_write_addr
-@itemx -single_module
-@itemx -static
-@itemx -sub_library
-@itemx -sub_umbrella
-@itemx -twolevel_namespace
-@itemx -umbrella
-@itemx -undefined
-@itemx -unexported_symbols_list
-@itemx -weak_reference_mismatches
-@itemx -whatsloaded
+@item -mvliw-branch
+@opindex mvliw-branch
-@opindex allowable_client
-@opindex arch_only
-@opindex client_name
-@opindex compatibility_version
-@opindex current_version
-@opindex dependency-file
-@opindex dylib_file
-@opindex dylinker_install_name
-@opindex dynamic
-@opindex dynamiclib
-@opindex exported_symbols_list
-@opindex filelist
-@opindex flat_namespace
-@opindex force_cpusubtype_ALL
-@opindex force_flat_namespace
-@opindex headerpad_max_install_names
-@opindex image_base
-@opindex init
-@opindex install_name
-@opindex keep_private_externs
-@opindex multi_module
-@opindex multiply_defined
-@opindex multiply_defined_unused
-@opindex noall_load
-@opindex nofixprebinding
-@opindex nomultidefs
-@opindex noprebind
-@opindex noseglinkedit
-@opindex pagezero_size
-@opindex prebind
-@opindex prebind_all_twolevel_modules
-@opindex private_bundle
-@opindex read_only_relocs
-@opindex sectalign
-@opindex sectobjectsymbols
-@opindex whyload
-@opindex seg1addr
-@opindex sectcreate
-@opindex sectobjectsymbols
-@opindex sectorder
-@opindex seg_addr_table
-@opindex seg_addr_table_filename
-@opindex seglinkedit
-@opindex segprot
-@opindex segs_read_only_addr
-@opindex segs_read_write_addr
-@opindex single_module
-@opindex static
-@opindex sub_library
-@opindex sub_umbrella
-@opindex twolevel_namespace
-@opindex umbrella
-@opindex undefined
-@opindex unexported_symbols_list
-@opindex weak_reference_mismatches
-@opindex whatsloaded
+Run a pass to pack branches into VLIW instructions (default).
-These options are available for Darwin linker. Darwin linker man page
-describes them in detail.
-@end table
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+@item -mno-vliw-branch
+@opindex mno-vliw-branch
-@node MIPS Options
-@subsection MIPS Options
-@cindex MIPS options
+Do not run a pass to pack branches into VLIW instructions.
-@table @gcctabopt
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -EB
-@opindex EB
-Generate big-endian code.
+@item -mmulti-cond-exec
+@opindex mmulti-cond-exec
-@item -EL
-@opindex EL
-Generate little-endian code. This is the default for @samp{mips*el-*-*}
-configurations.
+Enable optimization of @code{&&} and @code{||} in conditional execution
+(default).
-@item -march=@var{arch}
-@opindex march
-Generate code that will run on @var{arch}, which can be the name of a
-generic MIPS ISA, or the name of a particular processor.
-The ISA names are:
-@samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
-@samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
-The processor names are:
-@samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc},
-@samp{m4k},
-@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
-@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000}, @samp{rm7000},
-@samp{rm9000},
-@samp{orion},
-@samp{sb1},
-@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
-@samp{vr5000}, @samp{vr5400} and @samp{vr5500}.
-The special value @samp{from-abi} selects the
-most compatible architecture for the selected ABI (that is,
-@samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-In processor names, a final @samp{000} can be abbreviated as @samp{k}
-(for example, @samp{-march=r2k}). Prefixes are optional, and
-@samp{vr} may be written @samp{r}.
+@item -mno-multi-cond-exec
+@opindex mno-multi-cond-exec
-GCC defines two macros based on the value of this option. The first
-is @samp{_MIPS_ARCH}, which gives the name of target architecture, as
-a string. The second has the form @samp{_MIPS_ARCH_@var{foo}},
-where @var{foo} is the capitalized value of @samp{_MIPS_ARCH}@.
-For example, @samp{-march=r2000} will set @samp{_MIPS_ARCH}
-to @samp{"r2000"} and define the macro @samp{_MIPS_ARCH_R2000}.
+Disable optimization of @code{&&} and @code{||} in conditional execution.
+
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
+
+@item -mnested-cond-exec
+@opindex mnested-cond-exec
+
+Enable nested conditional execution optimizations (default).
-Note that the @samp{_MIPS_ARCH} macro uses the processor names given
-above. In other words, it will have the full prefix and will not
-abbreviate @samp{000} as @samp{k}. In the case of @samp{from-abi},
-the macro names the resolved architecture (either @samp{"mips1"} or
-@samp{"mips3"}). It names the default architecture when no
-@option{-march} option is given.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -mtune=@var{arch}
-@opindex mtune
-Optimize for @var{arch}. Among other things, this option controls
-the way instructions are scheduled, and the perceived cost of arithmetic
-operations. The list of @var{arch} values is the same as for
-@option{-march}.
+@item -mno-nested-cond-exec
+@opindex mno-nested-cond-exec
-When this option is not used, GCC will optimize for the processor
-specified by @option{-march}. By using @option{-march} and
-@option{-mtune} together, it is possible to generate code that will
-run on a family of processors, but optimize the code for one
-particular member of that family.
+Disable nested conditional execution optimizations.
-@samp{-mtune} defines the macros @samp{_MIPS_TUNE} and
-@samp{_MIPS_TUNE_@var{foo}}, which work in the same way as the
-@samp{-march} ones described above.
+This switch is mainly for debugging the compiler and will likely be removed
+in a future version.
-@item -mips1
-@opindex mips1
-Equivalent to @samp{-march=mips1}.
+@item -mtomcat-stats
+@opindex mtomcat-stats
-@item -mips2
-@opindex mips2
-Equivalent to @samp{-march=mips2}.
+Cause gas to print out tomcat statistics.
-@item -mips3
-@opindex mips3
-Equivalent to @samp{-march=mips3}.
+@item -mcpu=@var{cpu}
+@opindex mcpu
-@item -mips4
-@opindex mips4
-Equivalent to @samp{-march=mips4}.
+Select the processor type for which to generate code. Possible values are
+@samp{simple}, @samp{tomcat}, @samp{fr500}, @samp{fr400}, @samp{fr300},
+@samp{frv}.
-@item -mips32
-@opindex mips32
-Equivalent to @samp{-march=mips32}.
+@end table
-@item -mips32r2
-@opindex mips32r2
-Equivalent to @samp{-march=mips32r2}.
+@node H8/300 Options
+@subsection H8/300 Options
-@item -mips64
-@opindex mips64
-Equivalent to @samp{-march=mips64}.
+These @samp{-m} options are defined for the H8/300 implementations:
-@item -mips16
-@itemx -mno-mips16
-@opindex mips16
-@opindex mno-mips16
-Use (do not use) the MIPS16 ISA.
+@table @gcctabopt
+@item -mrelax
+@opindex mrelax
+Shorten some address references at link time, when possible; uses the
+linker option @option{-relax}. @xref{H8/300,, @code{ld} and the H8/300,
+ld, Using ld}, for a fuller description.
-@item -mabi=32
-@itemx -mabi=o64
-@itemx -mabi=n32
-@itemx -mabi=64
-@itemx -mabi=eabi
-@opindex mabi=32
-@opindex mabi=o64
-@opindex mabi=n32
-@opindex mabi=64
-@opindex mabi=eabi
-Generate code for the given ABI@.
+@item -mh
+@opindex mh
+Generate code for the H8/300H@.
-Note that the EABI has a 32-bit and a 64-bit variant. GCC normally
-generates 64-bit code when you select a 64-bit architecture, but you
-can use @option{-mgp32} to get 32-bit code instead.
+@item -ms
+@opindex ms
+Generate code for the H8S@.
-@item -mabicalls
-@itemx -mno-abicalls
-@opindex mabicalls
-@opindex mno-abicalls
-Generate (do not generate) SVR4-style position-independent code.
-@option{-mabicalls} is the default for SVR4-based systems.
+@item -mn
+@opindex mn
+Generate code for the H8S and H8/300H in the normal mode. This switch
+must be used either with -mh or -ms.
-@item -mxgot
-@itemx -mno-xgot
-@opindex mxgot
-@opindex mno-xgot
-Lift (do not lift) the usual restrictions on the size of the global
-offset table.
+@item -ms2600
+@opindex ms2600
+Generate code for the H8S/2600. This switch must be used with @option{-ms}.
-GCC normally uses a single instruction to load values from the GOT.
-While this is relatively efficient, it will only work if the GOT
-is smaller than about 64k. Anything larger will cause the linker
-to report an error such as:
+@item -mint32
+@opindex mint32
+Make @code{int} data 32 bits by default.
-@cindex relocation truncated to fit (MIPS)
-@smallexample
-relocation truncated to fit: R_MIPS_GOT16 foobar
-@end smallexample
+@item -malign-300
+@opindex malign-300
+On the H8/300H and H8S, use the same alignment rules as for the H8/300.
+The default for the H8/300H and H8S is to align longs and floats on 4
+byte boundaries.
+@option{-malign-300} causes them to be aligned on 2 byte boundaries.
+This option has no effect on the H8/300.
+@end table
-If this happens, you should recompile your code with @option{-mxgot}.
-It should then work with very large GOTs, although it will also be
-less efficient, since it will take three instructions to fetch the
-value of a global symbol.
+@node HPPA Options
+@subsection HPPA Options
+@cindex HPPA Options
-Note that some linkers can create multiple GOTs. If you have such a
-linker, you should only need to use @option{-mxgot} when a single object
-file accesses more than 64k's worth of GOT entries. Very few do.
+These @samp{-m} options are defined for the HPPA family of computers:
-These options have no effect unless GCC is generating position
-independent code.
+@table @gcctabopt
+@item -march=@var{architecture-type}
+@opindex march
+Generate code for the specified architecture. The choices for
+@var{architecture-type} are @samp{1.0} for PA 1.0, @samp{1.1} for PA
+1.1, and @samp{2.0} for PA 2.0 processors. Refer to
+@file{/usr/lib/sched.models} on an HP-UX system to determine the proper
+architecture option for your machine. Code compiled for lower numbered
+architectures will run on higher numbered architectures, but not the
+other way around.
-@item -membedded-pic
-@itemx -mno-embedded-pic
-@opindex membedded-pic
-@opindex mno-embedded-pic
-Generate (do not generate) position-independent code suitable for some
-embedded systems. All calls are made using PC relative addresses, and
-all data is addressed using the $gp register. No more than 65536
-bytes of global data may be used. This requires GNU as and GNU ld,
-which do most of the work.
+PA 2.0 support currently requires gas snapshot 19990413 or later. The
+next release of binutils (current is 2.9.1) will probably contain PA 2.0
+support.
-@item -mgp32
-@opindex mgp32
-Assume that general-purpose registers are 32 bits wide.
+@item -mpa-risc-1-0
+@itemx -mpa-risc-1-1
+@itemx -mpa-risc-2-0
+@opindex mpa-risc-1-0
+@opindex mpa-risc-1-1
+@opindex mpa-risc-2-0
+Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
-@item -mgp64
-@opindex mgp64
-Assume that general-purpose registers are 64 bits wide.
+@item -mbig-switch
+@opindex mbig-switch
+Generate code suitable for big switch tables. Use this option only if
+the assembler/linker complain about out of range branches within a switch
+table.
-@item -mfp32
-@opindex mfp32
-Assume that floating-point registers are 32 bits wide.
+@item -mjump-in-delay
+@opindex mjump-in-delay
+Fill delay slots of function calls with unconditional jump instructions
+by modifying the return pointer for the function call to be the target
+of the conditional jump.
-@item -mfp64
-@opindex mfp64
-Assume that floating-point registers are 64 bits wide.
+@item -mdisable-fpregs
+@opindex mdisable-fpregs
+Prevent floating point registers from being used in any manner. This is
+necessary for compiling kernels which perform lazy context switching of
+floating point registers. If you use this option and attempt to perform
+floating point operations, the compiler will abort.
-@item -mhard-float
-@opindex mhard-float
-Use floating-point coprocessor instructions.
+@item -mdisable-indexing
+@opindex mdisable-indexing
+Prevent the compiler from using indexing address modes. This avoids some
+rather obscure problems when compiling MIG generated code under MACH@.
-@item -msoft-float
-@opindex msoft-float
-Do not use floating-point coprocessor instructions. Implement
-floating-point calculations using library calls instead.
+@item -mno-space-regs
+@opindex mno-space-regs
+Generate code that assumes the target has no space registers. This allows
+GCC to generate faster indirect calls and use unscaled index address modes.
-@item -msingle-float
-@opindex msingle-float
-Assume that the floating-point coprocessor only supports single-precision
-operations.
+Such code is suitable for level 0 PA systems and kernels.
-@itemx -mdouble-float
-@opindex mdouble-float
-Assume that the floating-point coprocessor supports double-precision
-operations. This is the default.
+@item -mfast-indirect-calls
+@opindex mfast-indirect-calls
+Generate code that assumes calls never cross space boundaries. This
+allows GCC to emit code which performs faster indirect calls.
-@item -mint64
-@opindex mint64
-Force @code{int} and @code{long} types to be 64 bits wide. See
-@option{-mlong32} for an explanation of the default and the way
-that the pointer size is determined.
+This option will not work in the presence of shared libraries or nested
+functions.
-@item -mlong64
-@opindex mlong64
-Force @code{long} types to be 64 bits wide. See @option{-mlong32} for
-an explanation of the default and the way that the pointer size is
-determined.
+@item -mlong-load-store
+@opindex mlong-load-store
+Generate 3-instruction load and store sequences as sometimes required by
+the HP-UX 10 linker. This is equivalent to the @samp{+k} option to
+the HP compilers.
-@item -mlong32
-@opindex mlong32
-Force @code{long}, @code{int}, and pointer types to be 32 bits wide.
+@item -mportable-runtime
+@opindex mportable-runtime
+Use the portable calling conventions proposed by HP for ELF systems.
-The default size of @code{int}s, @code{long}s and pointers depends on
-the ABI@. All the supported ABIs use 32-bit @code{int}s. The n64 ABI
-uses 64-bit @code{long}s, as does the 64-bit EABI; the others use
-32-bit @code{long}s. Pointers are the same size as @code{long}s,
-or the same size as integer registers, whichever is smaller.
+@item -mgas
+@opindex mgas
+Enable the use of assembler directives only GAS understands.
+
+@item -mschedule=@var{cpu-type}
+@opindex mschedule
+Schedule code according to the constraints for the machine type
+@var{cpu-type}. The choices for @var{cpu-type} are @samp{700}
+@samp{7100}, @samp{7100LC}, @samp{7200}, @samp{7300} and @samp{8000}. Refer
+to @file{/usr/lib/sched.models} on an HP-UX system to determine the
+proper scheduling option for your machine. The default scheduling is
+@samp{8000}.
-@item -G @var{num}
-@opindex G
-@cindex smaller data references (MIPS)
-@cindex gp-relative references (MIPS)
-Put global and static items less than or equal to @var{num} bytes into
-the small data or bss section instead of the normal data or bss section.
-This allows the data to be accessed using a single instruction.
+@item -mlinker-opt
+@opindex mlinker-opt
+Enable the optimization pass in the HP-UX linker. Note this makes symbolic
+debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
+linkers in which they give bogus error messages when linking some programs.
-All modules should be compiled with the same @option{-G @var{num}}
-value.
+@item -msoft-float
+@opindex msoft-float
+Generate output containing library calls for floating point.
+@strong{Warning:} the requisite libraries are not available for all HPPA
+targets. Normally the facilities of the machine's usual C compiler are
+used, but this cannot be done directly in cross-compilation. You must make
+your own arrangements to provide suitable library functions for
+cross-compilation. The embedded target @samp{hppa1.1-*-pro}
+does provide software floating point support.
-@item -membedded-data
-@itemx -mno-embedded-data
-@opindex membedded-data
-@opindex mno-embedded-data
-Allocate variables to the read-only data section first if possible, then
-next in the small data section if possible, otherwise in data. This gives
-slightly slower code than the default, but reduces the amount of RAM required
-when executing, and thus may be preferred for some embedded systems.
+@option{-msoft-float} changes the calling convention in the output file;
+therefore, it is only useful if you compile @emph{all} of a program with
+this option. In particular, you need to compile @file{libgcc.a}, the
+library that comes with GCC, with @option{-msoft-float} in order for
+this to work.
-@item -muninit-const-in-rodata
-@itemx -mno-uninit-const-in-rodata
-@opindex muninit-const-in-rodata
-@opindex mno-uninit-const-in-rodata
-Put uninitialized @code{const} variables in the read-only data section.
-This option is only meaningful in conjunction with @option{-membedded-data}.
+@item -msio
+@opindex msio
+Generate the predefine, @code{_SIO}, for server IO. The default is
+@option{-mwsio}. This generates the predefines, @code{__hp9000s700},
+@code{__hp9000s700__} and @code{_WSIO}, for workstation IO. These
+options are available under HP-UX and HI-UX.
-@item -msplit-addresses
-@itemx -mno-split-addresses
-@opindex msplit-addresses
-@opindex mno-split-addresses
-Enable (disable) use of the @code{%hi()} and @code{%lo()} assembler
-relocation operators. This option has been superceded by
-@option{-mexplicit-relocs} but is retained for backwards compatibility.
+@item -mgnu-ld
+@opindex gnu-ld
+Use GNU ld specific options. This passes @option{-shared} to ld when
+building a shared library. It is the default when GCC is configured,
+explicitly or implicitly, with the GNU linker. This option does not
+have any affect on which ld is called, it only changes what parameters
+are passed to that ld. The ld that is called is determined by the
+@option{--with-ld} configure option, GCC's program search path, and
+finally by the user's @env{PATH}. The linker used by GCC can be printed
+using @samp{which `gcc -print-prog-name=ld`}.
-@item -mexplicit-relocs
-@itemx -mno-explicit-relocs
-@opindex mexplicit-relocs
-@opindex mno-explicit-relocs
-Use (do not use) assembler relocation operators when dealing with symbolic
-addresses. The alternative, selected by @option{-mno-explicit-relocs},
-is to use assembler macros instead.
+@item -mhp-ld
+@opindex hp-ld
+Use HP ld specific options. This passes @option{-b} to ld when building
+a shared library and passes @option{+Accept TypeMismatch} to ld on all
+links. It is the default when GCC is configured, explicitly or
+implicitly, with the HP linker. This option does not have any affect on
+which ld is called, it only changes what parameters are passed to that
+ld. The ld that is called is determined by the @option{--with-ld}
+configure option, GCC's program search path, and finally by the user's
+@env{PATH}. The linker used by GCC can be printed using @samp{which
+`gcc -print-prog-name=ld`}.
-@option{-mexplicit-relocs} is usually the default if GCC was configured
-to use an assembler that supports relocation operators. However, the
-combination of @option{-mabicalls} and @option{-fno-unit-at-a-time}
-implies @option{-mno-explicit-relocs} unless explicitly overridden.
-This is because, when generating abicalls, the choice of relocation
-depends on whether a symbol is local or global. In some rare cases,
-GCC will not be able to decide this until the whole compilation unit
-has been read.
+@item -mfdpic
+@opindex mfdpic
-@item -mrnames
-@itemx -mno-rnames
-@opindex mrnames
-@opindex mno-rnames
-Generate (do not generate) code that refers to registers using their
-software names. The default is @option{-mno-rnames}, which tells GCC
-to use hardware names like @samp{$4} instead of software names like
-@samp{a0}. The only assembler known to support @option{-rnames} is
-the Algorithmics assembler.
+Select the FDPIC ABI, that uses function descriptors to represent
+pointers to functions. Without any PIC/PIE-related options, it
+implies @option{-fPIE}. With @option{-fpic} or @option{-fpie}, it
+assumes GOT entries and small data are within a 12-bit range from the
+GOT base address; with @option{-fPIC} or @option{-fPIE}, GOT offsets
+are computed with 32 bits.
-@item -mcheck-zero-division
-@itemx -mno-check-zero-division
-@opindex mcheck-zero-division
-@opindex mno-check-zero-division
-Trap (do not trap) on integer division by zero. The default is
-@option{-mcheck-zero-division}.
+@item -minline-plt
+@opindex minline-plt
-@item -mmemcpy
-@itemx -mno-memcpy
-@opindex mmemcpy
-@opindex mno-memcpy
-Force (do not force) the use of @code{memcpy()} for non-trivial block
-moves. The default is @option{-mno-memcpy}, which allows GCC to inline
-most constant-sized copies.
+Enable inlining of PLT entries in function calls to functions that are
+not known to bind locally. It has no effect without @option{-mfdpic}.
+It's enabled by default if optimizing for speed and compiling for
+shared libraries (i.e., @option{-fPIC} or @option{-fpic}), or when an
+optimization option such as @option{-O3} or above is present in the
+command line.
-@item -mlong-calls
-@itemx -mno-long-calls
-@opindex mlong-calls
-@opindex mno-long-calls
-Disable (do not disable) use of the @code{jal} instruction. Calling
-functions using @code{jal} is more efficient but requires the caller
-and callee to be in the same 256 megabyte segment.
+@item -mgprel-ro
+@opindex mgprel-ro
-This option has no effect on abicalls code. The default is
-@option{-mno-long-calls}.
+Enable the use of @code{GPREL} relocations in the FDPIC ABI for data
+that is known to be in read-only sections. It's enabled by default,
+except for @option{-fpic} or @option{-fpie}: even though it may help
+make the global offset table smaller, it trades 1 instruction for 4.
+With @option{-fPIC} or @option{-fPIE}, it trades 3 instructions for 4,
+one of which may be shared by multiple symbols, and it avoids the need
+for a GOT entry for the referenced symbol, so it's more likely to be a
+win. If it is not, @option{-mno-gprel-ro} can be used to disable it.
-@item -mmad
-@itemx -mno-mad
-@opindex mmad
-@opindex mno-mad
-Enable (disable) use of the @code{mad}, @code{madu} and @code{mul}
-instructions, as provided by the R4650 ISA.
+@item -multilib-library-pic
+@opindex multilib-library-pic
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Enable (disable) use of the floating point multiply-accumulate
-instructions, when they are available. The default is
-@option{-mfused-madd}.
+Link with the (library, not FD) pic libraries. It's implied by
+@option{-mlibrary-pic}, as well as by @option{-fPIC} and
+@option{-fpic} without @option{-mfdpic}. You should never have to use
+it explicitly.
-When multiply-accumulate instructions are used, the intermediate
-product is calculated to infinite precision and is not subject to
-the FCSR Flush to Zero bit. This may be undesirable in some
-circumstances.
+@item -mlinked-fp
+@opindex mlinked-fp
-@item -nocpp
-@opindex nocpp
-Tell the MIPS assembler to not run its preprocessor over user
-assembler files (with a @samp{.s} suffix) when assembling them.
+Follow the EABI requirement of always creating a frame pointer whenever
+a stack frame is allocated. This option is enabled by default and can
+be disabled with @option{-mno-linked-fp}.
-@item -mfix-r4000
-@itemx -mno-fix-r4000
-@opindex mfix-r4000
-@opindex mno-fix-r4000
-Work around certain R4000 CPU errata:
-@itemize @minus
-@item
-A double-word or a variable shift may give an incorrect result if executed
-immediately after starting an integer division.
-@item
-A double-word or a variable shift may give an incorrect result if executed
-while an integer multiplication is in progress.
-@item
-An integer division may give an incorrect result if started in a delay slot
-of a taken branch or a jump.
-@end itemize
+@item -mlong-calls
+@opindex mno-long-calls
+Generate code that uses long call sequences. This ensures that a call
+is always able to reach linker generated stubs. The default is to generate
+long calls only when the distance from the call site to the beginning
+of the function or translation unit, as the case may be, exceeds a
+predefined limit set by the branch type being used. The limits for
+normal calls are 7,600,000 and 240,000 bytes, respectively for the
+PA 2.0 and PA 1.X architectures. Sibcalls are always limited at
+240,000 bytes.
-@item -mfix-r4400
-@itemx -mno-fix-r4400
-@opindex mfix-r4400
-@opindex mno-fix-r4400
-Work around certain R4400 CPU errata:
-@itemize @minus
-@item
-A double-word or a variable shift may give an incorrect result if executed
-immediately after starting an integer division.
-@end itemize
+Distances are measured from the beginning of functions when using the
+@option{-ffunction-sections} option, or when using the @option{-mgas}
+and @option{-mno-portable-runtime} options together under HP-UX with
+the SOM linker.
-@item -mfix-vr4122-bugs
-@itemx -mno-fix-vr4122-bugs
-@opindex mfix-vr4122-bugs
-Work around certain VR4122 errata:
-@itemize @minus
-@item
-@code{dmultu} does not always produce the correct result.
-@item
-@code{div} and @code{ddiv} do not always produce the correct result if one
-of the operands is negative.
-@end itemize
-The workarounds for the division errata rely on special functions in
-@file{libgcc.a}. At present, these functions are only provided by
-the @code{mips64vr*-elf} configurations.
+It is normally not desirable to use this option as it will degrade
+performance. However, it may be useful in large applications,
+particularly when partial linking is used to build the application.
-Other VR4122 errata require a nop to be inserted between certain pairs of
-instructions. These errata are handled by the assembler, not by GCC itself.
+The types of long calls used depends on the capabilities of the
+assembler and linker, and the type of code being generated. The
+impact on systems that support long absolute calls, and long pic
+symbol-difference or pc-relative calls should be relatively small.
+However, an indirect call is used on 32-bit ELF systems in pic code
+and it is quite long.
-@item -mfix-sb1
-@itemx -mno-fix-sb1
-@opindex mfix-sb1
-Work around certain SB-1 CPU core errata.
-(This flag currently works around the SB-1 revision 2
-``F1'' and ``F2'' floating point errata.)
+@item -nolibdld
+@opindex nolibdld
+Suppress the generation of link options to search libdld.sl when the
+@option{-static} option is specified on HP-UX 10 and later.
+
+@item -static
+@opindex static
+The HP-UX implementation of setlocale in libc has a dependency on
+libdld.sl. There isn't an archive version of libdld.sl. Thus,
+when the @option{-static} option is specified, special link options
+are needed to resolve this dependency.
-@item -mflush-func=@var{func}
-@itemx -mno-flush-func
-@opindex mflush-func
-Specifies the function to call to flush the I and D caches, or to not
-call any such function. If called, the function must take the same
-arguments as the common @code{_flush_func()}, that is, the address of the
-memory range for which the cache is being flushed, the size of the
-memory range, and the number 3 (to flush both caches). The default
-depends on the target GCC was configured for, but commonly is either
-@samp{_flush_func} or @samp{__cpu_flush}.
+On HP-UX 10 and later, the GCC driver adds the necessary options to
+link with libdld.sl when the @option{-static} option is specified.
+This causes the resulting binary to be dynamic. On the 64-bit port,
+the linkers generate dynamic binaries by default in any case. The
+@option{-nolibdld} option can be used to prevent the GCC driver from
+adding these link options.
-@item -mbranch-likely
-@itemx -mno-branch-likely
-@opindex mbranch-likely
-@opindex mno-branch-likely
-Enable or disable use of Branch Likely instructions, regardless of the
-default for the selected architecture. By default, Branch Likely
-instructions may be generated if they are supported by the selected
-architecture. An exception is for the MIPS32 and MIPS64 architectures
-and processors which implement those architectures; for those, Branch
-Likely instructions will not be generated by default because the MIPS32
-and MIPS64 architectures specifically deprecate their use.
+@item -threads
+@opindex threads
+Add support for multithreading with the @dfn{dce thread} library
+under HP-UX. This option sets flags for both the preprocessor and
+linker.
@end table
@node i386 and x86-64 Options
this model.
@end table
-@node HPPA Options
-@subsection HPPA Options
-@cindex HPPA Options
+@node IA-64 Options
+@subsection IA-64 Options
+@cindex IA-64 Options
-These @samp{-m} options are defined for the HPPA family of computers:
+These are the @samp{-m} options defined for the Intel IA-64 architecture.
@table @gcctabopt
-@item -march=@var{architecture-type}
-@opindex march
-Generate code for the specified architecture. The choices for
-@var{architecture-type} are @samp{1.0} for PA 1.0, @samp{1.1} for PA
-1.1, and @samp{2.0} for PA 2.0 processors. Refer to
-@file{/usr/lib/sched.models} on an HP-UX system to determine the proper
-architecture option for your machine. Code compiled for lower numbered
-architectures will run on higher numbered architectures, but not the
-other way around.
+@item -mbig-endian
+@opindex mbig-endian
+Generate code for a big endian target. This is the default for HP-UX@.
-PA 2.0 support currently requires gas snapshot 19990413 or later. The
-next release of binutils (current is 2.9.1) will probably contain PA 2.0
-support.
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code for a little endian target. This is the default for AIX5
+and GNU/Linux.
-@item -mpa-risc-1-0
-@itemx -mpa-risc-1-1
-@itemx -mpa-risc-2-0
-@opindex mpa-risc-1-0
-@opindex mpa-risc-1-1
-@opindex mpa-risc-2-0
-Synonyms for @option{-march=1.0}, @option{-march=1.1}, and @option{-march=2.0} respectively.
+@item -mgnu-as
+@itemx -mno-gnu-as
+@opindex mgnu-as
+@opindex mno-gnu-as
+Generate (or don't) code for the GNU assembler. This is the default.
+@c Also, this is the default if the configure option @option{--with-gnu-as}
+@c is used.
-@item -mbig-switch
-@opindex mbig-switch
-Generate code suitable for big switch tables. Use this option only if
-the assembler/linker complain about out of range branches within a switch
-table.
+@item -mgnu-ld
+@itemx -mno-gnu-ld
+@opindex mgnu-ld
+@opindex mno-gnu-ld
+Generate (or don't) code for the GNU linker. This is the default.
+@c Also, this is the default if the configure option @option{--with-gnu-ld}
+@c is used.
-@item -mjump-in-delay
-@opindex mjump-in-delay
-Fill delay slots of function calls with unconditional jump instructions
-by modifying the return pointer for the function call to be the target
-of the conditional jump.
+@item -mno-pic
+@opindex mno-pic
+Generate code that does not use a global pointer register. The result
+is not position independent code, and violates the IA-64 ABI@.
-@item -mdisable-fpregs
-@opindex mdisable-fpregs
-Prevent floating point registers from being used in any manner. This is
-necessary for compiling kernels which perform lazy context switching of
-floating point registers. If you use this option and attempt to perform
-floating point operations, the compiler will abort.
+@item -mvolatile-asm-stop
+@itemx -mno-volatile-asm-stop
+@opindex mvolatile-asm-stop
+@opindex mno-volatile-asm-stop
+Generate (or don't) a stop bit immediately before and after volatile asm
+statements.
-@item -mdisable-indexing
-@opindex mdisable-indexing
-Prevent the compiler from using indexing address modes. This avoids some
-rather obscure problems when compiling MIG generated code under MACH@.
+@item -mb-step
+@opindex mb-step
+Generate code that works around Itanium B step errata.
-@item -mno-space-regs
-@opindex mno-space-regs
-Generate code that assumes the target has no space registers. This allows
-GCC to generate faster indirect calls and use unscaled index address modes.
+@item -mregister-names
+@itemx -mno-register-names
+@opindex mregister-names
+@opindex mno-register-names
+Generate (or don't) @samp{in}, @samp{loc}, and @samp{out} register names for
+the stacked registers. This may make assembler output more readable.
-Such code is suitable for level 0 PA systems and kernels.
+@item -mno-sdata
+@itemx -msdata
+@opindex mno-sdata
+@opindex msdata
+Disable (or enable) optimizations that use the small data section. This may
+be useful for working around optimizer bugs.
-@item -mfast-indirect-calls
-@opindex mfast-indirect-calls
-Generate code that assumes calls never cross space boundaries. This
-allows GCC to emit code which performs faster indirect calls.
+@item -mconstant-gp
+@opindex mconstant-gp
+Generate code that uses a single constant global pointer value. This is
+useful when compiling kernel code.
-This option will not work in the presence of shared libraries or nested
-functions.
+@item -mauto-pic
+@opindex mauto-pic
+Generate code that is self-relocatable. This implies @option{-mconstant-gp}.
+This is useful when compiling firmware code.
-@item -mlong-load-store
-@opindex mlong-load-store
-Generate 3-instruction load and store sequences as sometimes required by
-the HP-UX 10 linker. This is equivalent to the @samp{+k} option to
-the HP compilers.
+@item -minline-float-divide-min-latency
+@opindex minline-float-divide-min-latency
+Generate code for inline divides of floating point values
+using the minimum latency algorithm.
-@item -mportable-runtime
-@opindex mportable-runtime
-Use the portable calling conventions proposed by HP for ELF systems.
+@item -minline-float-divide-max-throughput
+@opindex minline-float-divide-max-throughput
+Generate code for inline divides of floating point values
+using the maximum throughput algorithm.
-@item -mgas
-@opindex mgas
-Enable the use of assembler directives only GAS understands.
+@item -minline-int-divide-min-latency
+@opindex minline-int-divide-min-latency
+Generate code for inline divides of integer values
+using the minimum latency algorithm.
-@item -mschedule=@var{cpu-type}
-@opindex mschedule
-Schedule code according to the constraints for the machine type
-@var{cpu-type}. The choices for @var{cpu-type} are @samp{700}
-@samp{7100}, @samp{7100LC}, @samp{7200}, @samp{7300} and @samp{8000}. Refer
-to @file{/usr/lib/sched.models} on an HP-UX system to determine the
-proper scheduling option for your machine. The default scheduling is
-@samp{8000}.
+@item -minline-int-divide-max-throughput
+@opindex minline-int-divide-max-throughput
+Generate code for inline divides of integer values
+using the maximum throughput algorithm.
-@item -mlinker-opt
-@opindex mlinker-opt
-Enable the optimization pass in the HP-UX linker. Note this makes symbolic
-debugging impossible. It also triggers a bug in the HP-UX 8 and HP-UX 9
-linkers in which they give bogus error messages when linking some programs.
+@item -mno-dwarf2-asm
+@itemx -mdwarf2-asm
+@opindex mno-dwarf2-asm
+@opindex mdwarf2-asm
+Don't (or do) generate assembler code for the DWARF2 line number debugging
+info. This may be useful when not using the GNU assembler.
-@item -msoft-float
-@opindex msoft-float
-Generate output containing library calls for floating point.
-@strong{Warning:} the requisite libraries are not available for all HPPA
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross-compilation. The embedded target @samp{hppa1.1-*-pro}
-does provide software floating point support.
+@item -mfixed-range=@var{register-range}
+@opindex mfixed-range
+Generate code treating the given register range as fixed registers.
+A fixed register is one that the register allocator can not use. This is
+useful when compiling kernel code. A register range is specified as
+two registers separated by a dash. Multiple register ranges can be
+specified separated by a comma.
-@option{-msoft-float} changes the calling convention in the output file;
-therefore, it is only useful if you compile @emph{all} of a program with
-this option. In particular, you need to compile @file{libgcc.a}, the
-library that comes with GCC, with @option{-msoft-float} in order for
-this to work.
+@item -mearly-stop-bits
+@itemx -mno-early-stop-bits
+@opindex mearly-stop-bits
+@opindex mno-early-stop-bits
+Allow stop bits to be placed earlier than immediately preceding the
+instruction that triggered the stop bit. This can improve instruction
+scheduling, but does not always do so.
+@end table
-@item -msio
-@opindex msio
-Generate the predefine, @code{_SIO}, for server IO. The default is
-@option{-mwsio}. This generates the predefines, @code{__hp9000s700},
-@code{__hp9000s700__} and @code{_WSIO}, for workstation IO. These
-options are available under HP-UX and HI-UX.
+@node M32R/D Options
+@subsection M32R/D Options
+@cindex M32R/D options
-@item -mgnu-ld
-@opindex gnu-ld
-Use GNU ld specific options. This passes @option{-shared} to ld when
-building a shared library. It is the default when GCC is configured,
-explicitly or implicitly, with the GNU linker. This option does not
-have any affect on which ld is called, it only changes what parameters
-are passed to that ld. The ld that is called is determined by the
-@option{--with-ld} configure option, GCC's program search path, and
-finally by the user's @env{PATH}. The linker used by GCC can be printed
-using @samp{which `gcc -print-prog-name=ld`}.
+These @option{-m} options are defined for Renesas M32R/D architectures:
+
+@table @gcctabopt
+@item -m32r2
+@opindex m32r2
+Generate code for the M32R/2@.
+
+@item -m32rx
+@opindex m32rx
+Generate code for the M32R/X@.
+
+@item -m32r
+@opindex m32r
+Generate code for the M32R@. This is the default.
-@item -mhp-ld
-@opindex hp-ld
-Use HP ld specific options. This passes @option{-b} to ld when building
-a shared library and passes @option{+Accept TypeMismatch} to ld on all
-links. It is the default when GCC is configured, explicitly or
-implicitly, with the HP linker. This option does not have any affect on
-which ld is called, it only changes what parameters are passed to that
-ld. The ld that is called is determined by the @option{--with-ld}
-configure option, GCC's program search path, and finally by the user's
-@env{PATH}. The linker used by GCC can be printed using @samp{which
-`gcc -print-prog-name=ld`}.
+@item -mmodel=small
+@opindex mmodel=small
+Assume all objects live in the lower 16MB of memory (so that their addresses
+can be loaded with the @code{ld24} instruction), and assume all subroutines
+are reachable with the @code{bl} instruction.
+This is the default.
-@item -mfdpic
-@opindex mfdpic
+The addressability of a particular object can be set with the
+@code{model} attribute.
-Select the FDPIC ABI, that uses function descriptors to represent
-pointers to functions. Without any PIC/PIE-related options, it
-implies @option{-fPIE}. With @option{-fpic} or @option{-fpie}, it
-assumes GOT entries and small data are within a 12-bit range from the
-GOT base address; with @option{-fPIC} or @option{-fPIE}, GOT offsets
-are computed with 32 bits.
+@item -mmodel=medium
+@opindex mmodel=medium
+Assume objects may be anywhere in the 32-bit address space (the compiler
+will generate @code{seth/add3} instructions to load their addresses), and
+assume all subroutines are reachable with the @code{bl} instruction.
-@item -minline-plt
-@opindex minline-plt
+@item -mmodel=large
+@opindex mmodel=large
+Assume objects may be anywhere in the 32-bit address space (the compiler
+will generate @code{seth/add3} instructions to load their addresses), and
+assume subroutines may not be reachable with the @code{bl} instruction
+(the compiler will generate the much slower @code{seth/add3/jl}
+instruction sequence).
-Enable inlining of PLT entries in function calls to functions that are
-not known to bind locally. It has no effect without @option{-mfdpic}.
-It's enabled by default if optimizing for speed and compiling for
-shared libraries (i.e., @option{-fPIC} or @option{-fpic}), or when an
-optimization option such as @option{-O3} or above is present in the
-command line.
+@item -msdata=none
+@opindex msdata=none
+Disable use of the small data area. Variables will be put into
+one of @samp{.data}, @samp{bss}, or @samp{.rodata} (unless the
+@code{section} attribute has been specified).
+This is the default.
-@item -mgprel-ro
-@opindex mgprel-ro
+The small data area consists of sections @samp{.sdata} and @samp{.sbss}.
+Objects may be explicitly put in the small data area with the
+@code{section} attribute using one of these sections.
-Enable the use of @code{GPREL} relocations in the FDPIC ABI for data
-that is known to be in read-only sections. It's enabled by default,
-except for @option{-fpic} or @option{-fpie}: even though it may help
-make the global offset table smaller, it trades 1 instruction for 4.
-With @option{-fPIC} or @option{-fPIE}, it trades 3 instructions for 4,
-one of which may be shared by multiple symbols, and it avoids the need
-for a GOT entry for the referenced symbol, so it's more likely to be a
-win. If it is not, @option{-mno-gprel-ro} can be used to disable it.
+@item -msdata=sdata
+@opindex msdata=sdata
+Put small global and static data in the small data area, but do not
+generate special code to reference them.
-@item -multilib-library-pic
-@opindex multilib-library-pic
+@item -msdata=use
+@opindex msdata=use
+Put small global and static data in the small data area, and generate
+special instructions to reference them.
-Link with the (library, not FD) pic libraries. It's implied by
-@option{-mlibrary-pic}, as well as by @option{-fPIC} and
-@option{-fpic} without @option{-mfdpic}. You should never have to use
-it explicitly.
+@item -G @var{num}
+@opindex G
+@cindex smaller data references
+Put global and static objects less than or equal to @var{num} bytes
+into the small data or bss sections instead of the normal data or bss
+sections. The default value of @var{num} is 8.
+The @option{-msdata} option must be set to one of @samp{sdata} or @samp{use}
+for this option to have any effect.
-@item -mlinked-fp
-@opindex mlinked-fp
+All modules should be compiled with the same @option{-G @var{num}} value.
+Compiling with different values of @var{num} may or may not work; if it
+doesn't the linker will give an error message---incorrect code will not be
+generated.
-Follow the EABI requirement of always creating a frame pointer whenever
-a stack frame is allocated. This option is enabled by default and can
-be disabled with @option{-mno-linked-fp}.
+@item -mdebug
+@opindex mdebug
+Makes the M32R specific code in the compiler display some statistics
+that might help in debugging programs.
-@item -mlong-calls
-@opindex mno-long-calls
-Generate code that uses long call sequences. This ensures that a call
-is always able to reach linker generated stubs. The default is to generate
-long calls only when the distance from the call site to the beginning
-of the function or translation unit, as the case may be, exceeds a
-predefined limit set by the branch type being used. The limits for
-normal calls are 7,600,000 and 240,000 bytes, respectively for the
-PA 2.0 and PA 1.X architectures. Sibcalls are always limited at
-240,000 bytes.
+@item -malign-loops
+@opindex malign-loops
+Align all loops to a 32-byte boundary.
-Distances are measured from the beginning of functions when using the
-@option{-ffunction-sections} option, or when using the @option{-mgas}
-and @option{-mno-portable-runtime} options together under HP-UX with
-the SOM linker.
+@item -mno-align-loops
+@opindex mno-align-loops
+Do not enforce a 32-byte alignment for loops. This is the default.
-It is normally not desirable to use this option as it will degrade
-performance. However, it may be useful in large applications,
-particularly when partial linking is used to build the application.
+@item -missue-rate=@var{number}
+@opindex missue-rate=@var{number}
+Issue @var{number} instructions per cycle. @var{number} can only be 1
+or 2.
-The types of long calls used depends on the capabilities of the
-assembler and linker, and the type of code being generated. The
-impact on systems that support long absolute calls, and long pic
-symbol-difference or pc-relative calls should be relatively small.
-However, an indirect call is used on 32-bit ELF systems in pic code
-and it is quite long.
+@item -mbranch-cost=@var{number}
+@opindex mbranch-cost=@var{number}
+@var{number} can only be 1 or 2. If it is 1 then branches will be
+preferred over conditional code, if it is 2, then the opposite will
+apply.
-@item -nolibdld
-@opindex nolibdld
-Suppress the generation of link options to search libdld.sl when the
-@option{-static} option is specified on HP-UX 10 and later.
+@item -mflush-trap=@var{number}
+@opindex mflush-trap=@var{number}
+Specifies the trap number to use to flush the cache. The default is
+12. Valid numbers are between 0 and 15 inclusive.
-@item -static
-@opindex static
-The HP-UX implementation of setlocale in libc has a dependency on
-libdld.sl. There isn't an archive version of libdld.sl. Thus,
-when the @option{-static} option is specified, special link options
-are needed to resolve this dependency.
+@item -mno-flush-trap
+@opindex mno-flush-trap
+Specifies that the cache cannot be flushed by using a trap.
-On HP-UX 10 and later, the GCC driver adds the necessary options to
-link with libdld.sl when the @option{-static} option is specified.
-This causes the resulting binary to be dynamic. On the 64-bit port,
-the linkers generate dynamic binaries by default in any case. The
-@option{-nolibdld} option can be used to prevent the GCC driver from
-adding these link options.
+@item -mflush-func=@var{name}
+@opindex mflush-func=@var{name}
+Specifies the name of the operating system function to call to flush
+the cache. The default is @emph{_flush_cache}, but a function call
+will only be used if a trap is not available.
+
+@item -mno-flush-func
+@opindex mno-flush-func
+Indicates that there is no OS function for flushing the cache.
-@item -threads
-@opindex threads
-Add support for multithreading with the @dfn{dce thread} library
-under HP-UX. This option sets flags for both the preprocessor and
-linker.
@end table
-@node DEC Alpha Options
-@subsection DEC Alpha Options
+@node M680x0 Options
+@subsection M680x0 Options
+@cindex M680x0 options
-These @samp{-m} options are defined for the DEC Alpha implementations:
+These are the @samp{-m} options defined for the 68000 series. The default
+values for these options depends on which style of 68000 was selected when
+the compiler was configured; the defaults for the most common choices are
+given below.
@table @gcctabopt
-@item -mno-soft-float
-@itemx -msoft-float
-@opindex mno-soft-float
-@opindex msoft-float
-Use (do not use) the hardware floating-point instructions for
-floating-point operations. When @option{-msoft-float} is specified,
-functions in @file{libgcc.a} will be used to perform floating-point
-operations. Unless they are replaced by routines that emulate the
-floating-point operations, or compiled in such a way as to call such
-emulations routines, these routines will issue floating-point
-operations. If you are compiling for an Alpha without floating-point
-operations, you must ensure that the library is built so as not to call
-them.
+@item -m68000
+@itemx -mc68000
+@opindex m68000
+@opindex mc68000
+Generate output for a 68000. This is the default
+when the compiler is configured for 68000-based systems.
-Note that Alpha implementations without floating-point operations are
-required to have floating-point registers.
+Use this option for microcontrollers with a 68000 or EC000 core,
+including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356.
-@item -mfp-reg
-@itemx -mno-fp-regs
-@opindex mfp-reg
-@opindex mno-fp-regs
-Generate code that uses (does not use) the floating-point register set.
-@option{-mno-fp-regs} implies @option{-msoft-float}. If the floating-point
-register set is not used, floating point operands are passed in integer
-registers as if they were integers and floating-point results are passed
-in @code{$0} instead of @code{$f0}. This is a non-standard calling sequence,
-so any function with a floating-point argument or return value called by code
-compiled with @option{-mno-fp-regs} must also be compiled with that
-option.
+@item -m68020
+@itemx -mc68020
+@opindex m68020
+@opindex mc68020
+Generate output for a 68020. This is the default
+when the compiler is configured for 68020-based systems.
-A typical use of this option is building a kernel that does not use,
-and hence need not save and restore, any floating-point registers.
+@item -m68881
+@opindex m68881
+Generate output containing 68881 instructions for floating point.
+This is the default for most 68020 systems unless @option{--nfp} was
+specified when the compiler was configured.
-@item -mieee
-@opindex mieee
-The Alpha architecture implements floating-point hardware optimized for
-maximum performance. It is mostly compliant with the IEEE floating
-point standard. However, for full compliance, software assistance is
-required. This option generates code fully IEEE compliant code
-@emph{except} that the @var{inexact-flag} is not maintained (see below).
-If this option is turned on, the preprocessor macro @code{_IEEE_FP} is
-defined during compilation. The resulting code is less efficient but is
-able to correctly support denormalized numbers and exceptional IEEE
-values such as not-a-number and plus/minus infinity. Other Alpha
-compilers call this option @option{-ieee_with_no_inexact}.
+@item -m68030
+@opindex m68030
+Generate output for a 68030. This is the default when the compiler is
+configured for 68030-based systems.
+
+@item -m68040
+@opindex m68040
+Generate output for a 68040. This is the default when the compiler is
+configured for 68040-based systems.
+
+This option inhibits the use of 68881/68882 instructions that have to be
+emulated by software on the 68040. Use this option if your 68040 does not
+have code to emulate those instructions.
-@item -mieee-with-inexact
-@opindex mieee-with-inexact
-This is like @option{-mieee} except the generated code also maintains
-the IEEE @var{inexact-flag}. Turning on this option causes the
-generated code to implement fully-compliant IEEE math. In addition to
-@code{_IEEE_FP}, @code{_IEEE_FP_EXACT} is defined as a preprocessor
-macro. On some Alpha implementations the resulting code may execute
-significantly slower than the code generated by default. Since there is
-very little code that depends on the @var{inexact-flag}, you should
-normally not specify this option. Other Alpha compilers call this
-option @option{-ieee_with_inexact}.
+@item -m68060
+@opindex m68060
+Generate output for a 68060. This is the default when the compiler is
+configured for 68060-based systems.
-@item -mfp-trap-mode=@var{trap-mode}
-@opindex mfp-trap-mode
-This option controls what floating-point related traps are enabled.
-Other Alpha compilers call this option @option{-fptm @var{trap-mode}}.
-The trap mode can be set to one of four values:
+This option inhibits the use of 68020 and 68881/68882 instructions that
+have to be emulated by software on the 68060. Use this option if your 68060
+does not have code to emulate those instructions.
-@table @samp
-@item n
-This is the default (normal) setting. The only traps that are enabled
-are the ones that cannot be disabled in software (e.g., division by zero
-trap).
+@item -mcpu32
+@opindex mcpu32
+Generate output for a CPU32. This is the default
+when the compiler is configured for CPU32-based systems.
-@item u
-In addition to the traps enabled by @samp{n}, underflow traps are enabled
-as well.
+Use this option for microcontrollers with a
+CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334,
+68336, 68340, 68341, 68349 and 68360.
-@item su
-Like @samp{su}, but the instructions are marked to be safe for software
-completion (see Alpha architecture manual for details).
+@item -m5200
+@opindex m5200
+Generate output for a 520X ``coldfire'' family cpu. This is the default
+when the compiler is configured for 520X-based systems.
-@item sui
-Like @samp{su}, but inexact traps are enabled as well.
-@end table
+Use this option for microcontroller with a 5200 core, including
+the MCF5202, MCF5203, MCF5204 and MCF5202.
-@item -mfp-rounding-mode=@var{rounding-mode}
-@opindex mfp-rounding-mode
-Selects the IEEE rounding mode. Other Alpha compilers call this option
-@option{-fprm @var{rounding-mode}}. The @var{rounding-mode} can be one
-of:
-@table @samp
-@item n
-Normal IEEE rounding mode. Floating point numbers are rounded towards
-the nearest machine number or towards the even machine number in case
-of a tie.
+@item -m68020-40
+@opindex m68020-40
+Generate output for a 68040, without using any of the new instructions.
+This results in code which can run relatively efficiently on either a
+68020/68881 or a 68030 or a 68040. The generated code does use the
+68881 instructions that are emulated on the 68040.
-@item m
-Round towards minus infinity.
+@item -m68020-60
+@opindex m68020-60
+Generate output for a 68060, without using any of the new instructions.
+This results in code which can run relatively efficiently on either a
+68020/68881 or a 68030 or a 68040. The generated code does use the
+68881 instructions that are emulated on the 68060.
-@item c
-Chopped rounding mode. Floating point numbers are rounded towards zero.
+@item -msoft-float
+@opindex msoft-float
+Generate output containing library calls for floating point.
+@strong{Warning:} the requisite libraries are not available for all m68k
+targets. Normally the facilities of the machine's usual C compiler are
+used, but this can't be done directly in cross-compilation. You must
+make your own arrangements to provide suitable library functions for
+cross-compilation. The embedded targets @samp{m68k-*-aout} and
+@samp{m68k-*-coff} do provide software floating point support.
-@item d
-Dynamic rounding mode. A field in the floating point control register
-(@var{fpcr}, see Alpha architecture reference manual) controls the
-rounding mode in effect. The C library initializes this register for
-rounding towards plus infinity. Thus, unless your program modifies the
-@var{fpcr}, @samp{d} corresponds to round towards plus infinity.
-@end table
+@item -mshort
+@opindex mshort
+Consider type @code{int} to be 16 bits wide, like @code{short int}.
+Additionally, parameters passed on the stack are also aligned to a
+16-bit boundary even on targets whose API mandates promotion to 32-bit.
-@item -mtrap-precision=@var{trap-precision}
-@opindex mtrap-precision
-In the Alpha architecture, floating point traps are imprecise. This
-means without software assistance it is impossible to recover from a
-floating trap and program execution normally needs to be terminated.
-GCC can generate code that can assist operating system trap handlers
-in determining the exact location that caused a floating point trap.
-Depending on the requirements of an application, different levels of
-precisions can be selected:
+@item -mnobitfield
+@opindex mnobitfield
+Do not use the bit-field instructions. The @option{-m68000}, @option{-mcpu32}
+and @option{-m5200} options imply @w{@option{-mnobitfield}}.
-@table @samp
-@item p
-Program precision. This option is the default and means a trap handler
-can only identify which program caused a floating point exception.
+@item -mbitfield
+@opindex mbitfield
+Do use the bit-field instructions. The @option{-m68020} option implies
+@option{-mbitfield}. This is the default if you use a configuration
+designed for a 68020.
-@item f
-Function precision. The trap handler can determine the function that
-caused a floating point exception.
+@item -mrtd
+@opindex mrtd
+Use a different function-calling convention, in which functions
+that take a fixed number of arguments return with the @code{rtd}
+instruction, which pops their arguments while returning. This
+saves one instruction in the caller since there is no need to pop
+the arguments there.
-@item i
-Instruction precision. The trap handler can determine the exact
-instruction that caused a floating point exception.
-@end table
+This calling convention is incompatible with the one normally
+used on Unix, so you cannot use it if you need to call libraries
+compiled with the Unix compiler.
-Other Alpha compilers provide the equivalent options called
-@option{-scope_safe} and @option{-resumption_safe}.
+Also, you must provide function prototypes for all functions that
+take variable numbers of arguments (including @code{printf});
+otherwise incorrect code will be generated for calls to those
+functions.
-@item -mieee-conformant
-@opindex mieee-conformant
-This option marks the generated code as IEEE conformant. You must not
-use this option unless you also specify @option{-mtrap-precision=i} and either
-@option{-mfp-trap-mode=su} or @option{-mfp-trap-mode=sui}. Its only effect
-is to emit the line @samp{.eflag 48} in the function prologue of the
-generated assembly file. Under DEC Unix, this has the effect that
-IEEE-conformant math library routines will be linked in.
+In addition, seriously incorrect code will result if you call a
+function with too many arguments. (Normally, extra arguments are
+harmlessly ignored.)
-@item -mbuild-constants
-@opindex mbuild-constants
-Normally GCC examines a 32- or 64-bit integer constant to
-see if it can construct it from smaller constants in two or three
-instructions. If it cannot, it will output the constant as a literal and
-generate code to load it from the data segment at runtime.
+The @code{rtd} instruction is supported by the 68010, 68020, 68030,
+68040, 68060 and CPU32 processors, but not by the 68000 or 5200.
-Use this option to require GCC to construct @emph{all} integer constants
-using code, even if it takes more instructions (the maximum is six).
+@item -malign-int
+@itemx -mno-align-int
+@opindex malign-int
+@opindex mno-align-int
+Control whether GCC aligns @code{int}, @code{long}, @code{long long},
+@code{float}, @code{double}, and @code{long double} variables on a 32-bit
+boundary (@option{-malign-int}) or a 16-bit boundary (@option{-mno-align-int}).
+Aligning variables on 32-bit boundaries produces code that runs somewhat
+faster on processors with 32-bit busses at the expense of more memory.
-You would typically use this option to build a shared library dynamic
-loader. Itself a shared library, it must relocate itself in memory
-before it can find the variables and constants in its own data segment.
+@strong{Warning:} if you use the @option{-malign-int} switch, GCC will
+align structures containing the above types differently than
+most published application binary interface specifications for the m68k.
-@item -malpha-as
-@itemx -mgas
-@opindex malpha-as
-@opindex mgas
-Select whether to generate code to be assembled by the vendor-supplied
-assembler (@option{-malpha-as}) or by the GNU assembler @option{-mgas}.
+@item -mpcrel
+@opindex mpcrel
+Use the pc-relative addressing mode of the 68000 directly, instead of
+using a global offset table. At present, this option implies @option{-fpic},
+allowing at most a 16-bit offset for pc-relative addressing. @option{-fPIC} is
+not presently supported with @option{-mpcrel}, though this could be supported for
+68020 and higher processors.
-@item -mbwx
-@itemx -mno-bwx
-@itemx -mcix
-@itemx -mno-cix
-@itemx -mfix
-@itemx -mno-fix
-@itemx -mmax
-@itemx -mno-max
-@opindex mbwx
-@opindex mno-bwx
-@opindex mcix
-@opindex mno-cix
-@opindex mfix
-@opindex mno-fix
-@opindex mmax
-@opindex mno-max
-Indicate whether GCC should generate code to use the optional BWX,
-CIX, FIX and MAX instruction sets. The default is to use the instruction
-sets supported by the CPU type specified via @option{-mcpu=} option or that
-of the CPU on which GCC was built if none was specified.
+@item -mno-strict-align
+@itemx -mstrict-align
+@opindex mno-strict-align
+@opindex mstrict-align
+Do not (do) assume that unaligned memory references will be handled by
+the system.
-@item -mfloat-vax
-@itemx -mfloat-ieee
-@opindex mfloat-vax
-@opindex mfloat-ieee
-Generate code that uses (does not use) VAX F and G floating point
-arithmetic instead of IEEE single and double precision.
+@item -msep-data
+Generate code that allows the data segment to be located in a different
+area of memory from the text segment. This allows for execute in place in
+an environment without virtual memory management. This option implies -fPIC.
-@item -mexplicit-relocs
-@itemx -mno-explicit-relocs
-@opindex mexplicit-relocs
-@opindex mno-explicit-relocs
-Older Alpha assemblers provided no way to generate symbol relocations
-except via assembler macros. Use of these macros does not allow
-optimal instruction scheduling. GNU binutils as of version 2.12
-supports a new syntax that allows the compiler to explicitly mark
-which relocations should apply to which instructions. This option
-is mostly useful for debugging, as GCC detects the capabilities of
-the assembler when it is built and sets the default accordingly.
+@item -mno-sep-data
+Generate code that assumes that the data segment follows the text segment.
+This is the default.
-@item -msmall-data
-@itemx -mlarge-data
-@opindex msmall-data
-@opindex mlarge-data
-When @option{-mexplicit-relocs} is in effect, static data is
-accessed via @dfn{gp-relative} relocations. When @option{-msmall-data}
-is used, objects 8 bytes long or smaller are placed in a @dfn{small data area}
-(the @code{.sdata} and @code{.sbss} sections) and are accessed via
-16-bit relocations off of the @code{$gp} register. This limits the
-size of the small data area to 64KB, but allows the variables to be
-directly accessed via a single instruction.
+@item -mid-shared-library
+Generate code that supports shared libraries via the library ID method.
+This allows for execute in place and shared libraries in an environment
+without virtual memory management. This option implies -fPIC.
-The default is @option{-mlarge-data}. With this option the data area
-is limited to just below 2GB. Programs that require more than 2GB of
-data must use @code{malloc} or @code{mmap} to allocate the data in the
-heap instead of in the program's data segment.
+@item -mno-id-shared-library
+Generate code that doesn't assume ID based shared libraries are being used.
+This is the default.
-When generating code for shared libraries, @option{-fpic} implies
-@option{-msmall-data} and @option{-fPIC} implies @option{-mlarge-data}.
+@item -mshared-library-id=n
+Specified the identification number of the ID based shared library being
+compiled. Specifying a value of 0 will generate more compact code, specifying
+other values will force the allocation of that number to the current
+library but is no more space or time efficient than omitting this option.
-@item -msmall-text
-@itemx -mlarge-text
-@opindex msmall-text
-@opindex mlarge-text
-When @option{-msmall-text} is used, the compiler assumes that the
-code of the entire program (or shared library) fits in 4MB, and is
-thus reachable with a branch instruction. When @option{-msmall-data}
-is used, the compiler can assume that all local symbols share the
-same @code{$gp} value, and thus reduce the number of instructions
-required for a function call from 4 to 1.
+@end table
-The default is @option{-mlarge-text}.
+@node M68hc1x Options
+@subsection M68hc1x Options
+@cindex M68hc1x options
-@item -mcpu=@var{cpu_type}
-@opindex mcpu
-Set the instruction set and instruction scheduling parameters for
-machine type @var{cpu_type}. You can specify either the @samp{EV}
-style name or the corresponding chip number. GCC supports scheduling
-parameters for the EV4, EV5 and EV6 family of processors and will
-choose the default values for the instruction set from the processor
-you specify. If you do not specify a processor type, GCC will default
-to the processor on which the compiler was built.
+These are the @samp{-m} options defined for the 68hc11 and 68hc12
+microcontrollers. The default values for these options depends on
+which style of microcontroller was selected when the compiler was configured;
+the defaults for the most common choices are given below.
-Supported values for @var{cpu_type} are
+@table @gcctabopt
+@item -m6811
+@itemx -m68hc11
+@opindex m6811
+@opindex m68hc11
+Generate output for a 68HC11. This is the default
+when the compiler is configured for 68HC11-based systems.
-@table @samp
-@item ev4
-@itemx ev45
-@itemx 21064
-Schedules as an EV4 and has no instruction set extensions.
+@item -m6812
+@itemx -m68hc12
+@opindex m6812
+@opindex m68hc12
+Generate output for a 68HC12. This is the default
+when the compiler is configured for 68HC12-based systems.
-@item ev5
-@itemx 21164
-Schedules as an EV5 and has no instruction set extensions.
+@item -m68S12
+@itemx -m68hcs12
+@opindex m68S12
+@opindex m68hcs12
+Generate output for a 68HCS12.
-@item ev56
-@itemx 21164a
-Schedules as an EV5 and supports the BWX extension.
+@item -mauto-incdec
+@opindex mauto-incdec
+Enable the use of 68HC12 pre and post auto-increment and auto-decrement
+addressing modes.
-@item pca56
-@itemx 21164pc
-@itemx 21164PC
-Schedules as an EV5 and supports the BWX and MAX extensions.
+@item -minmax
+@itemx -nominmax
+@opindex minmax
+@opindex mnominmax
+Enable the use of 68HC12 min and max instructions.
-@item ev6
-@itemx 21264
-Schedules as an EV6 and supports the BWX, FIX, and MAX extensions.
+@item -mlong-calls
+@itemx -mno-long-calls
+@opindex mlong-calls
+@opindex mno-long-calls
+Treat all calls as being far away (near). If calls are assumed to be
+far away, the compiler will use the @code{call} instruction to
+call a function and the @code{rtc} instruction for returning.
+
+@item -mshort
+@opindex mshort
+Consider type @code{int} to be 16 bits wide, like @code{short int}.
+
+@item -msoft-reg-count=@var{count}
+@opindex msoft-reg-count
+Specify the number of pseudo-soft registers which are used for the
+code generation. The maximum number is 32. Using more pseudo-soft
+register may or may not result in better code depending on the program.
+The default is 4 for 68HC11 and 2 for 68HC12.
-@item ev67
-@itemx 21264a
-Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions.
@end table
-@item -mtune=@var{cpu_type}
-@opindex mtune
-Set only the instruction scheduling parameters for machine type
-@var{cpu_type}. The instruction set is not changed.
+@node MCore Options
+@subsection MCore Options
+@cindex MCore options
-@item -mmemory-latency=@var{time}
-@opindex mmemory-latency
-Sets the latency the scheduler should assume for typical memory
-references as seen by the application. This number is highly
-dependent on the memory access patterns used by the application
-and the size of the external cache on the machine.
+These are the @samp{-m} options defined for the Motorola M*Core
+processors.
-Valid options for @var{time} are
+@table @gcctabopt
-@table @samp
-@item @var{number}
-A decimal number representing clock cycles.
+@item -mhardlit
+@itemx -mno-hardlit
+@opindex mhardlit
+@opindex mno-hardlit
+Inline constants into the code stream if it can be done in two
+instructions or less.
-@item L1
-@itemx L2
-@itemx L3
-@itemx main
-The compiler contains estimates of the number of clock cycles for
-``typical'' EV4 & EV5 hardware for the Level 1, 2 & 3 caches
-(also called Dcache, Scache, and Bcache), as well as to main memory.
-Note that L3 is only valid for EV5.
+@item -mdiv
+@itemx -mno-div
+@opindex mdiv
+@opindex mno-div
+Use the divide instruction. (Enabled by default).
-@end table
-@end table
+@item -mrelax-immediate
+@itemx -mno-relax-immediate
+@opindex mrelax-immediate
+@opindex mno-relax-immediate
+Allow arbitrary sized immediates in bit operations.
-@node DEC Alpha/VMS Options
-@subsection DEC Alpha/VMS Options
+@item -mwide-bitfields
+@itemx -mno-wide-bitfields
+@opindex mwide-bitfields
+@opindex mno-wide-bitfields
+Always treat bit-fields as int-sized.
-These @samp{-m} options are defined for the DEC Alpha/VMS implementations:
+@item -m4byte-functions
+@itemx -mno-4byte-functions
+@opindex m4byte-functions
+@opindex mno-4byte-functions
+Force all functions to be aligned to a four byte boundary.
-@table @gcctabopt
-@item -mvms-return-codes
-@opindex mvms-return-codes
-Return VMS condition codes from main. The default is to return POSIX
-style condition (e.g.@ error) codes.
-@end table
+@item -mcallgraph-data
+@itemx -mno-callgraph-data
+@opindex mcallgraph-data
+@opindex mno-callgraph-data
+Emit callgraph information.
-@node H8/300 Options
-@subsection H8/300 Options
+@item -mslow-bytes
+@itemx -mno-slow-bytes
+@opindex mslow-bytes
+@opindex mno-slow-bytes
+Prefer word access when reading byte quantities.
-These @samp{-m} options are defined for the H8/300 implementations:
+@item -mlittle-endian
+@itemx -mbig-endian
+@opindex mlittle-endian
+@opindex mbig-endian
+Generate code for a little endian target.
-@table @gcctabopt
-@item -mrelax
-@opindex mrelax
-Shorten some address references at link time, when possible; uses the
-linker option @option{-relax}. @xref{H8/300,, @code{ld} and the H8/300,
-ld, Using ld}, for a fuller description.
+@item -m210
+@itemx -m340
+@opindex m210
+@opindex m340
+Generate code for the 210 processor.
+@end table
-@item -mh
-@opindex mh
-Generate code for the H8/300H@.
+@node MIPS Options
+@subsection MIPS Options
+@cindex MIPS options
-@item -ms
-@opindex ms
-Generate code for the H8S@.
+@table @gcctabopt
-@item -mn
-@opindex mn
-Generate code for the H8S and H8/300H in the normal mode. This switch
-must be used either with -mh or -ms.
+@item -EB
+@opindex EB
+Generate big-endian code.
-@item -ms2600
-@opindex ms2600
-Generate code for the H8S/2600. This switch must be used with @option{-ms}.
+@item -EL
+@opindex EL
+Generate little-endian code. This is the default for @samp{mips*el-*-*}
+configurations.
-@item -mint32
-@opindex mint32
-Make @code{int} data 32 bits by default.
+@item -march=@var{arch}
+@opindex march
+Generate code that will run on @var{arch}, which can be the name of a
+generic MIPS ISA, or the name of a particular processor.
+The ISA names are:
+@samp{mips1}, @samp{mips2}, @samp{mips3}, @samp{mips4},
+@samp{mips32}, @samp{mips32r2}, and @samp{mips64}.
+The processor names are:
+@samp{4kc}, @samp{4kp}, @samp{5kc}, @samp{20kc},
+@samp{m4k},
+@samp{r2000}, @samp{r3000}, @samp{r3900}, @samp{r4000}, @samp{r4400},
+@samp{r4600}, @samp{r4650}, @samp{r6000}, @samp{r8000}, @samp{rm7000},
+@samp{rm9000},
+@samp{orion},
+@samp{sb1},
+@samp{vr4100}, @samp{vr4111}, @samp{vr4120}, @samp{vr4130}, @samp{vr4300},
+@samp{vr5000}, @samp{vr5400} and @samp{vr5500}.
+The special value @samp{from-abi} selects the
+most compatible architecture for the selected ABI (that is,
+@samp{mips1} for 32-bit ABIs and @samp{mips3} for 64-bit ABIs)@.
+
+In processor names, a final @samp{000} can be abbreviated as @samp{k}
+(for example, @samp{-march=r2k}). Prefixes are optional, and
+@samp{vr} may be written @samp{r}.
-@item -malign-300
-@opindex malign-300
-On the H8/300H and H8S, use the same alignment rules as for the H8/300.
-The default for the H8/300H and H8S is to align longs and floats on 4
-byte boundaries.
-@option{-malign-300} causes them to be aligned on 2 byte boundaries.
-This option has no effect on the H8/300.
-@end table
+GCC defines two macros based on the value of this option. The first
+is @samp{_MIPS_ARCH}, which gives the name of target architecture, as
+a string. The second has the form @samp{_MIPS_ARCH_@var{foo}},
+where @var{foo} is the capitalized value of @samp{_MIPS_ARCH}@.
+For example, @samp{-march=r2000} will set @samp{_MIPS_ARCH}
+to @samp{"r2000"} and define the macro @samp{_MIPS_ARCH_R2000}.
-@node SH Options
-@subsection SH Options
+Note that the @samp{_MIPS_ARCH} macro uses the processor names given
+above. In other words, it will have the full prefix and will not
+abbreviate @samp{000} as @samp{k}. In the case of @samp{from-abi},
+the macro names the resolved architecture (either @samp{"mips1"} or
+@samp{"mips3"}). It names the default architecture when no
+@option{-march} option is given.
-These @samp{-m} options are defined for the SH implementations:
+@item -mtune=@var{arch}
+@opindex mtune
+Optimize for @var{arch}. Among other things, this option controls
+the way instructions are scheduled, and the perceived cost of arithmetic
+operations. The list of @var{arch} values is the same as for
+@option{-march}.
-@table @gcctabopt
-@item -m1
-@opindex m1
-Generate code for the SH1.
+When this option is not used, GCC will optimize for the processor
+specified by @option{-march}. By using @option{-march} and
+@option{-mtune} together, it is possible to generate code that will
+run on a family of processors, but optimize the code for one
+particular member of that family.
-@item -m2
-@opindex m2
-Generate code for the SH2.
+@samp{-mtune} defines the macros @samp{_MIPS_TUNE} and
+@samp{_MIPS_TUNE_@var{foo}}, which work in the same way as the
+@samp{-march} ones described above.
-@item -m2e
-Generate code for the SH2e.
+@item -mips1
+@opindex mips1
+Equivalent to @samp{-march=mips1}.
-@item -m3
-@opindex m3
-Generate code for the SH3.
+@item -mips2
+@opindex mips2
+Equivalent to @samp{-march=mips2}.
-@item -m3e
-@opindex m3e
-Generate code for the SH3e.
+@item -mips3
+@opindex mips3
+Equivalent to @samp{-march=mips3}.
-@item -m4-nofpu
-@opindex m4-nofpu
-Generate code for the SH4 without a floating-point unit.
+@item -mips4
+@opindex mips4
+Equivalent to @samp{-march=mips4}.
-@item -m4-single-only
-@opindex m4-single-only
-Generate code for the SH4 with a floating-point unit that only
-supports single-precision arithmetic.
+@item -mips32
+@opindex mips32
+Equivalent to @samp{-march=mips32}.
-@item -m4-single
-@opindex m4-single
-Generate code for the SH4 assuming the floating-point unit is in
-single-precision mode by default.
+@item -mips32r2
+@opindex mips32r2
+Equivalent to @samp{-march=mips32r2}.
-@item -m4
-@opindex m4
-Generate code for the SH4.
+@item -mips64
+@opindex mips64
+Equivalent to @samp{-march=mips64}.
-@item -mb
-@opindex mb
-Compile code for the processor in big endian mode.
+@item -mips16
+@itemx -mno-mips16
+@opindex mips16
+@opindex mno-mips16
+Use (do not use) the MIPS16 ISA.
-@item -ml
-@opindex ml
-Compile code for the processor in little endian mode.
+@item -mabi=32
+@itemx -mabi=o64
+@itemx -mabi=n32
+@itemx -mabi=64
+@itemx -mabi=eabi
+@opindex mabi=32
+@opindex mabi=o64
+@opindex mabi=n32
+@opindex mabi=64
+@opindex mabi=eabi
+Generate code for the given ABI@.
-@item -mdalign
-@opindex mdalign
-Align doubles at 64-bit boundaries. Note that this changes the calling
-conventions, and thus some functions from the standard C library will
-not work unless you recompile it first with @option{-mdalign}.
+Note that the EABI has a 32-bit and a 64-bit variant. GCC normally
+generates 64-bit code when you select a 64-bit architecture, but you
+can use @option{-mgp32} to get 32-bit code instead.
-@item -mrelax
-@opindex mrelax
-Shorten some address references at link time, when possible; uses the
-linker option @option{-relax}.
+For information about the O64 ABI, see
+@w{@uref{http://gcc.gnu.org/projects/mipso64-abi.html}}.
-@item -mbigtable
-@opindex mbigtable
-Use 32-bit offsets in @code{switch} tables. The default is to use
-16-bit offsets.
+@item -mabicalls
+@itemx -mno-abicalls
+@opindex mabicalls
+@opindex mno-abicalls
+Generate (do not generate) SVR4-style position-independent code.
+@option{-mabicalls} is the default for SVR4-based systems.
-@item -mfmovd
-@opindex mfmovd
-Enable the use of the instruction @code{fmovd}.
+@item -mxgot
+@itemx -mno-xgot
+@opindex mxgot
+@opindex mno-xgot
+Lift (do not lift) the usual restrictions on the size of the global
+offset table.
-@item -mhitachi
-@opindex mhitachi
-Comply with the calling conventions defined by Renesas.
+GCC normally uses a single instruction to load values from the GOT.
+While this is relatively efficient, it will only work if the GOT
+is smaller than about 64k. Anything larger will cause the linker
+to report an error such as:
-@item -mnomacsave
-@opindex mnomacsave
-Mark the @code{MAC} register as call-clobbered, even if
-@option{-mhitachi} is given.
+@cindex relocation truncated to fit (MIPS)
+@smallexample
+relocation truncated to fit: R_MIPS_GOT16 foobar
+@end smallexample
-@item -mieee
-@opindex mieee
-Increase IEEE-compliance of floating-point code.
+If this happens, you should recompile your code with @option{-mxgot}.
+It should then work with very large GOTs, although it will also be
+less efficient, since it will take three instructions to fetch the
+value of a global symbol.
-@item -misize
-@opindex misize
-Dump instruction size and location in the assembly code.
+Note that some linkers can create multiple GOTs. If you have such a
+linker, you should only need to use @option{-mxgot} when a single object
+file accesses more than 64k's worth of GOT entries. Very few do.
-@item -mpadstruct
-@opindex mpadstruct
-This option is deprecated. It pads structures to multiple of 4 bytes,
-which is incompatible with the SH ABI@.
+These options have no effect unless GCC is generating position
+independent code.
-@item -mspace
-@opindex mspace
-Optimize for space instead of speed. Implied by @option{-Os}.
+@item -mgp32
+@opindex mgp32
+Assume that general-purpose registers are 32 bits wide.
-@item -mprefergot
-@opindex mprefergot
-When generating position-independent code, emit function calls using
-the Global Offset Table instead of the Procedure Linkage Table.
+@item -mgp64
+@opindex mgp64
+Assume that general-purpose registers are 64 bits wide.
-@item -musermode
-@opindex musermode
-Generate a library function call to invalidate instruction cache
-entries, after fixing up a trampoline. This library function call
-doesn't assume it can write to the whole memory address space. This
-is the default when the target is @code{sh-*-linux*}.
-@end table
+@item -mfp32
+@opindex mfp32
+Assume that floating-point registers are 32 bits wide.
-@node System V Options
-@subsection Options for System V
+@item -mfp64
+@opindex mfp64
+Assume that floating-point registers are 64 bits wide.
-These additional options are available on System V Release 4 for
-compatibility with other compilers on those systems:
+@item -mhard-float
+@opindex mhard-float
+Use floating-point coprocessor instructions.
-@table @gcctabopt
-@item -G
-@opindex G
-Create a shared object.
-It is recommended that @option{-symbolic} or @option{-shared} be used instead.
+@item -msoft-float
+@opindex msoft-float
+Do not use floating-point coprocessor instructions. Implement
+floating-point calculations using library calls instead.
-@item -Qy
-@opindex Qy
-Identify the versions of each tool used by the compiler, in a
-@code{.ident} assembler directive in the output.
+@item -msingle-float
+@opindex msingle-float
+Assume that the floating-point coprocessor only supports single-precision
+operations.
-@item -Qn
-@opindex Qn
-Refrain from adding @code{.ident} directives to the output file (this is
-the default).
+@itemx -mdouble-float
+@opindex mdouble-float
+Assume that the floating-point coprocessor supports double-precision
+operations. This is the default.
-@item -YP,@var{dirs}
-@opindex YP
-Search the directories @var{dirs}, and no others, for libraries
-specified with @option{-l}.
+@item -mint64
+@opindex mint64
+Force @code{int} and @code{long} types to be 64 bits wide. See
+@option{-mlong32} for an explanation of the default and the way
+that the pointer size is determined.
-@item -Ym,@var{dir}
-@opindex Ym
-Look in the directory @var{dir} to find the M4 preprocessor.
-The assembler uses this option.
-@c This is supposed to go with a -Yd for predefined M4 macro files, but
-@c the generic assembler that comes with Solaris takes just -Ym.
-@end table
+@item -mlong64
+@opindex mlong64
+Force @code{long} types to be 64 bits wide. See @option{-mlong32} for
+an explanation of the default and the way that the pointer size is
+determined.
+
+@item -mlong32
+@opindex mlong32
+Force @code{long}, @code{int}, and pointer types to be 32 bits wide.
-@node TMS320C3x/C4x Options
-@subsection TMS320C3x/C4x Options
-@cindex TMS320C3x/C4x Options
+The default size of @code{int}s, @code{long}s and pointers depends on
+the ABI@. All the supported ABIs use 32-bit @code{int}s. The n64 ABI
+uses 64-bit @code{long}s, as does the 64-bit EABI; the others use
+32-bit @code{long}s. Pointers are the same size as @code{long}s,
+or the same size as integer registers, whichever is smaller.
-These @samp{-m} options are defined for TMS320C3x/C4x implementations:
+@item -G @var{num}
+@opindex G
+@cindex smaller data references (MIPS)
+@cindex gp-relative references (MIPS)
+Put global and static items less than or equal to @var{num} bytes into
+the small data or bss section instead of the normal data or bss section.
+This allows the data to be accessed using a single instruction.
-@table @gcctabopt
+All modules should be compiled with the same @option{-G @var{num}}
+value.
-@item -mcpu=@var{cpu_type}
-@opindex mcpu
-Set the instruction set, register set, and instruction scheduling
-parameters for machine type @var{cpu_type}. Supported values for
-@var{cpu_type} are @samp{c30}, @samp{c31}, @samp{c32}, @samp{c40}, and
-@samp{c44}. The default is @samp{c40} to generate code for the
-TMS320C40.
+@item -membedded-data
+@itemx -mno-embedded-data
+@opindex membedded-data
+@opindex mno-embedded-data
+Allocate variables to the read-only data section first if possible, then
+next in the small data section if possible, otherwise in data. This gives
+slightly slower code than the default, but reduces the amount of RAM required
+when executing, and thus may be preferred for some embedded systems.
-@item -mbig-memory
-@itemx -mbig
-@itemx -msmall-memory
-@itemx -msmall
-@opindex mbig-memory
-@opindex mbig
-@opindex msmall-memory
-@opindex msmall
-Generates code for the big or small memory model. The small memory
-model assumed that all data fits into one 64K word page. At run-time
-the data page (DP) register must be set to point to the 64K page
-containing the .bss and .data program sections. The big memory model is
-the default and requires reloading of the DP register for every direct
-memory access.
+@item -muninit-const-in-rodata
+@itemx -mno-uninit-const-in-rodata
+@opindex muninit-const-in-rodata
+@opindex mno-uninit-const-in-rodata
+Put uninitialized @code{const} variables in the read-only data section.
+This option is only meaningful in conjunction with @option{-membedded-data}.
-@item -mbk
-@itemx -mno-bk
-@opindex mbk
-@opindex mno-bk
-Allow (disallow) allocation of general integer operands into the block
-count register BK@.
+@item -msplit-addresses
+@itemx -mno-split-addresses
+@opindex msplit-addresses
+@opindex mno-split-addresses
+Enable (disable) use of the @code{%hi()} and @code{%lo()} assembler
+relocation operators. This option has been superceded by
+@option{-mexplicit-relocs} but is retained for backwards compatibility.
-@item -mdb
-@itemx -mno-db
-@opindex mdb
-@opindex mno-db
-Enable (disable) generation of code using decrement and branch,
-DBcond(D), instructions. This is enabled by default for the C4x. To be
-on the safe side, this is disabled for the C3x, since the maximum
-iteration count on the C3x is @math{2^{23} + 1} (but who iterates loops more than
-@math{2^{23}} times on the C3x?). Note that GCC will try to reverse a loop so
-that it can utilize the decrement and branch instruction, but will give
-up if there is more than one memory reference in the loop. Thus a loop
-where the loop counter is decremented can generate slightly more
-efficient code, in cases where the RPTB instruction cannot be utilized.
+@item -mexplicit-relocs
+@itemx -mno-explicit-relocs
+@opindex mexplicit-relocs
+@opindex mno-explicit-relocs
+Use (do not use) assembler relocation operators when dealing with symbolic
+addresses. The alternative, selected by @option{-mno-explicit-relocs},
+is to use assembler macros instead.
-@item -mdp-isr-reload
-@itemx -mparanoid
-@opindex mdp-isr-reload
-@opindex mparanoid
-Force the DP register to be saved on entry to an interrupt service
-routine (ISR), reloaded to point to the data section, and restored on
-exit from the ISR@. This should not be required unless someone has
-violated the small memory model by modifying the DP register, say within
-an object library.
+@option{-mexplicit-relocs} is usually the default if GCC was configured
+to use an assembler that supports relocation operators. However, the
+combination of @option{-mabicalls} and @option{-fno-unit-at-a-time}
+implies @option{-mno-explicit-relocs} unless explicitly overridden.
+This is because, when generating abicalls, the choice of relocation
+depends on whether a symbol is local or global. In some rare cases,
+GCC will not be able to decide this until the whole compilation unit
+has been read.
-@item -mmpyi
-@itemx -mno-mpyi
-@opindex mmpyi
-@opindex mno-mpyi
-For the C3x use the 24-bit MPYI instruction for integer multiplies
-instead of a library call to guarantee 32-bit results. Note that if one
-of the operands is a constant, then the multiplication will be performed
-using shifts and adds. If the @option{-mmpyi} option is not specified for the C3x,
-then squaring operations are performed inline instead of a library call.
+@item -mrnames
+@itemx -mno-rnames
+@opindex mrnames
+@opindex mno-rnames
+Generate (do not generate) code that refers to registers using their
+software names. The default is @option{-mno-rnames}, which tells GCC
+to use hardware names like @samp{$4} instead of software names like
+@samp{a0}. The only assembler known to support @option{-rnames} is
+the Algorithmics assembler.
-@item -mfast-fix
-@itemx -mno-fast-fix
-@opindex mfast-fix
-@opindex mno-fast-fix
-The C3x/C4x FIX instruction to convert a floating point value to an
-integer value chooses the nearest integer less than or equal to the
-floating point value rather than to the nearest integer. Thus if the
-floating point number is negative, the result will be incorrectly
-truncated an additional code is necessary to detect and correct this
-case. This option can be used to disable generation of the additional
-code required to correct the result.
+@item -mcheck-zero-division
+@itemx -mno-check-zero-division
+@opindex mcheck-zero-division
+@opindex mno-check-zero-division
+Trap (do not trap) on integer division by zero. The default is
+@option{-mcheck-zero-division}.
-@item -mrptb
-@itemx -mno-rptb
-@opindex mrptb
-@opindex mno-rptb
-Enable (disable) generation of repeat block sequences using the RPTB
-instruction for zero overhead looping. The RPTB construct is only used
-for innermost loops that do not call functions or jump across the loop
-boundaries. There is no advantage having nested RPTB loops due to the
-overhead required to save and restore the RC, RS, and RE registers.
-This is enabled by default with @option{-O2}.
+@item -mmemcpy
+@itemx -mno-memcpy
+@opindex mmemcpy
+@opindex mno-memcpy
+Force (do not force) the use of @code{memcpy()} for non-trivial block
+moves. The default is @option{-mno-memcpy}, which allows GCC to inline
+most constant-sized copies.
-@item -mrpts=@var{count}
-@itemx -mno-rpts
-@opindex mrpts
-@opindex mno-rpts
-Enable (disable) the use of the single instruction repeat instruction
-RPTS@. If a repeat block contains a single instruction, and the loop
-count can be guaranteed to be less than the value @var{count}, GCC will
-emit a RPTS instruction instead of a RPTB@. If no value is specified,
-then a RPTS will be emitted even if the loop count cannot be determined
-at compile time. Note that the repeated instruction following RPTS does
-not have to be reloaded from memory each iteration, thus freeing up the
-CPU buses for operands. However, since interrupts are blocked by this
-instruction, it is disabled by default.
+@item -mlong-calls
+@itemx -mno-long-calls
+@opindex mlong-calls
+@opindex mno-long-calls
+Disable (do not disable) use of the @code{jal} instruction. Calling
+functions using @code{jal} is more efficient but requires the caller
+and callee to be in the same 256 megabyte segment.
-@item -mloop-unsigned
-@itemx -mno-loop-unsigned
-@opindex mloop-unsigned
-@opindex mno-loop-unsigned
-The maximum iteration count when using RPTS and RPTB (and DB on the C40)
-is @math{2^{31} + 1} since these instructions test if the iteration count is
-negative to terminate the loop. If the iteration count is unsigned
-there is a possibility than the @math{2^{31} + 1} maximum iteration count may be
-exceeded. This switch allows an unsigned iteration count.
+This option has no effect on abicalls code. The default is
+@option{-mno-long-calls}.
-@item -mti
-@opindex mti
-Try to emit an assembler syntax that the TI assembler (asm30) is happy
-with. This also enforces compatibility with the API employed by the TI
-C3x C compiler. For example, long doubles are passed as structures
-rather than in floating point registers.
+@item -mmad
+@itemx -mno-mad
+@opindex mmad
+@opindex mno-mad
+Enable (disable) use of the @code{mad}, @code{madu} and @code{mul}
+instructions, as provided by the R4650 ISA.
-@item -mregparm
-@itemx -mmemparm
-@opindex mregparm
-@opindex mmemparm
-Generate code that uses registers (stack) for passing arguments to functions.
-By default, arguments are passed in registers where possible rather
-than by pushing arguments on to the stack.
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Enable (disable) use of the floating point multiply-accumulate
+instructions, when they are available. The default is
+@option{-mfused-madd}.
-@item -mparallel-insns
-@itemx -mno-parallel-insns
-@opindex mparallel-insns
-@opindex mno-parallel-insns
-Allow the generation of parallel instructions. This is enabled by
-default with @option{-O2}.
+When multiply-accumulate instructions are used, the intermediate
+product is calculated to infinite precision and is not subject to
+the FCSR Flush to Zero bit. This may be undesirable in some
+circumstances.
-@item -mparallel-mpy
-@itemx -mno-parallel-mpy
-@opindex mparallel-mpy
-@opindex mno-parallel-mpy
-Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
-provided @option{-mparallel-insns} is also specified. These instructions have
-tight register constraints which can pessimize the code generation
-of large functions.
+@item -nocpp
+@opindex nocpp
+Tell the MIPS assembler to not run its preprocessor over user
+assembler files (with a @samp{.s} suffix) when assembling them.
-@end table
+@item -mfix-r4000
+@itemx -mno-fix-r4000
+@opindex mfix-r4000
+@opindex mno-fix-r4000
+Work around certain R4000 CPU errata:
+@itemize @minus
+@item
+A double-word or a variable shift may give an incorrect result if executed
+immediately after starting an integer division.
+@item
+A double-word or a variable shift may give an incorrect result if executed
+while an integer multiplication is in progress.
+@item
+An integer division may give an incorrect result if started in a delay slot
+of a taken branch or a jump.
+@end itemize
-@node V850 Options
-@subsection V850 Options
-@cindex V850 Options
+@item -mfix-r4400
+@itemx -mno-fix-r4400
+@opindex mfix-r4400
+@opindex mno-fix-r4400
+Work around certain R4400 CPU errata:
+@itemize @minus
+@item
+A double-word or a variable shift may give an incorrect result if executed
+immediately after starting an integer division.
+@end itemize
-These @samp{-m} options are defined for V850 implementations:
+@item -mfix-vr4120
+@itemx -mno-fix-vr4120
+@opindex mfix-vr4120
+Work around certain VR4120 errata:
+@itemize @minus
+@item
+@code{dmultu} does not always produce the correct result.
+@item
+@code{div} and @code{ddiv} do not always produce the correct result if one
+of the operands is negative.
+@end itemize
+The workarounds for the division errata rely on special functions in
+@file{libgcc.a}. At present, these functions are only provided by
+the @code{mips64vr*-elf} configurations.
-@table @gcctabopt
-@item -mlong-calls
-@itemx -mno-long-calls
-@opindex mlong-calls
-@opindex mno-long-calls
-Treat all calls as being far away (near). If calls are assumed to be
-far away, the compiler will always load the functions address up into a
-register, and call indirect through the pointer.
+Other VR4120 errata require a nop to be inserted between certain pairs of
+instructions. These errata are handled by the assembler, not by GCC itself.
-@item -mno-ep
-@itemx -mep
-@opindex mno-ep
-@opindex mep
-Do not optimize (do optimize) basic blocks that use the same index
-pointer 4 or more times to copy pointer into the @code{ep} register, and
-use the shorter @code{sld} and @code{sst} instructions. The @option{-mep}
-option is on by default if you optimize.
+@item -mfix-sb1
+@itemx -mno-fix-sb1
+@opindex mfix-sb1
+Work around certain SB-1 CPU core errata.
+(This flag currently works around the SB-1 revision 2
+``F1'' and ``F2'' floating point errata.)
-@item -mno-prolog-function
-@itemx -mprolog-function
-@opindex mno-prolog-function
-@opindex mprolog-function
-Do not use (do use) external functions to save and restore registers
-at the prologue and epilogue of a function. The external functions
-are slower, but use less code space if more than one function saves
-the same number of registers. The @option{-mprolog-function} option
-is on by default if you optimize.
+@item -mflush-func=@var{func}
+@itemx -mno-flush-func
+@opindex mflush-func
+Specifies the function to call to flush the I and D caches, or to not
+call any such function. If called, the function must take the same
+arguments as the common @code{_flush_func()}, that is, the address of the
+memory range for which the cache is being flushed, the size of the
+memory range, and the number 3 (to flush both caches). The default
+depends on the target GCC was configured for, but commonly is either
+@samp{_flush_func} or @samp{__cpu_flush}.
-@item -mspace
-@opindex mspace
-Try to make the code as small as possible. At present, this just turns
-on the @option{-mep} and @option{-mprolog-function} options.
+@item -mbranch-likely
+@itemx -mno-branch-likely
+@opindex mbranch-likely
+@opindex mno-branch-likely
+Enable or disable use of Branch Likely instructions, regardless of the
+default for the selected architecture. By default, Branch Likely
+instructions may be generated if they are supported by the selected
+architecture. An exception is for the MIPS32 and MIPS64 architectures
+and processors which implement those architectures; for those, Branch
+Likely instructions will not be generated by default because the MIPS32
+and MIPS64 architectures specifically deprecate their use.
-@item -mtda=@var{n}
-@opindex mtda
-Put static or global variables whose size is @var{n} bytes or less into
-the tiny data area that register @code{ep} points to. The tiny data
-area can hold up to 256 bytes in total (128 bytes for byte references).
+@item -mfp-exceptions
+@itemx -mno-fp-exceptions
+@opindex mfp-exceptions
+Specifies whether FP exceptions are enabled. This affects how we schedule
+FP instructions for some processors. The default is that FP exceptions are
+enabled.
+
+For instance, on the SB-1, if FP exceptions are disabled, and we are emitting
+64-bit code, then we can use both FP pipes. Otherwise, we can only use one
+FP pipe.
+
+@item -mvr4130-align
+@itemx -mno-vr4130-align
+@opindex mvr4130-align
+The VR4130 pipeline is two-way superscalar, but can only issue two
+instructions together if the first one is 8-byte aligned. When this
+option is enabled, GCC will align pairs of instructions that it
+thinks should execute in parallel.
+
+This option only has an effect when optimizing for the VR4130.
+It normally makes code faster, but at the expense of making it bigger.
+It is enabled by default at optimization level @option{-O3}.
+@end table
-@item -msda=@var{n}
-@opindex msda
-Put static or global variables whose size is @var{n} bytes or less into
-the small data area that register @code{gp} points to. The small data
-area can hold up to 64 kilobytes.
+@node MMIX Options
+@subsection MMIX Options
+@cindex MMIX Options
-@item -mzda=@var{n}
-@opindex mzda
-Put static or global variables whose size is @var{n} bytes or less into
-the first 32 kilobytes of memory.
+These options are defined for the MMIX:
-@item -mv850
-@opindex mv850
-Specify that the target processor is the V850.
+@table @gcctabopt
+@item -mlibfuncs
+@itemx -mno-libfuncs
+@opindex mlibfuncs
+@opindex mno-libfuncs
+Specify that intrinsic library functions are being compiled, passing all
+values in registers, no matter the size.
-@item -mbig-switch
-@opindex mbig-switch
-Generate code suitable for big switch tables. Use this option only if
-the assembler/linker complain about out of range branches within a switch
-table.
+@item -mepsilon
+@itemx -mno-epsilon
+@opindex mepsilon
+@opindex mno-epsilon
+Generate floating-point comparison instructions that compare with respect
+to the @code{rE} epsilon register.
-@item -mapp-regs
-@opindex mapp-regs
-This option will cause r2 and r5 to be used in the code generated by
-the compiler. This setting is the default.
+@item -mabi=mmixware
+@itemx -mabi=gnu
+@opindex mabi-mmixware
+@opindex mabi=gnu
+Generate code that passes function parameters and return values that (in
+the called function) are seen as registers @code{$0} and up, as opposed to
+the GNU ABI which uses global registers @code{$231} and up.
-@item -mno-app-regs
-@opindex mno-app-regs
-This option will cause r2 and r5 to be treated as fixed registers.
+@item -mzero-extend
+@itemx -mno-zero-extend
+@opindex mzero-extend
+@opindex mno-zero-extend
+When reading data from memory in sizes shorter than 64 bits, use (do not
+use) zero-extending load instructions by default, rather than
+sign-extending ones.
-@item -mv850e1
-@opindex mv850e1
-Specify that the target processor is the V850E1. The preprocessor
-constants @samp{__v850e1__} and @samp{__v850e__} will be defined if
-this option is used.
+@item -mknuthdiv
+@itemx -mno-knuthdiv
+@opindex mknuthdiv
+@opindex mno-knuthdiv
+Make the result of a division yielding a remainder have the same sign as
+the divisor. With the default, @option{-mno-knuthdiv}, the sign of the
+remainder follows the sign of the dividend. Both methods are
+arithmetically valid, the latter being almost exclusively used.
-@item -mv850e
-@opindex mv850e
-Specify that the target processor is the V850E. The preprocessor
-constant @samp{__v850e__} will be defined if this option is used.
+@item -mtoplevel-symbols
+@itemx -mno-toplevel-symbols
+@opindex mtoplevel-symbols
+@opindex mno-toplevel-symbols
+Prepend (do not prepend) a @samp{:} to all global symbols, so the assembly
+code can be used with the @code{PREFIX} assembly directive.
-If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1}
-are defined then a default target processor will be chosen and the
-relevant @samp{__v850*__} preprocessor constant will be defined.
+@item -melf
+@opindex melf
+Generate an executable in the ELF format, rather than the default
+@samp{mmo} format used by the @command{mmix} simulator.
-The preprocessor constants @samp{__v850} and @samp{__v851__} are always
-defined, regardless of which processor variant is the target.
+@item -mbranch-predict
+@itemx -mno-branch-predict
+@opindex mbranch-predict
+@opindex mno-branch-predict
+Use (do not use) the probable-branch instructions, when static branch
+prediction indicates a probable branch.
-@item -mdisable-callt
-@opindex mdisable-callt
-This option will suppress generation of the CALLT instruction for the
-v850e and v850e1 flavors of the v850 architecture. The default is
-@option{-mno-disable-callt} which allows the CALLT instruction to be used.
+@item -mbase-addresses
+@itemx -mno-base-addresses
+@opindex mbase-addresses
+@opindex mno-base-addresses
+Generate (do not generate) code that uses @emph{base addresses}. Using a
+base address automatically generates a request (handled by the assembler
+and the linker) for a constant to be set up in a global register. The
+register is used for one or more base address requests within the range 0
+to 255 from the value held in the register. The generally leads to short
+and fast code, but the number of different data items that can be
+addressed is limited. This means that a program that uses lots of static
+data may require @option{-mno-base-addresses}.
+@item -msingle-exit
+@itemx -mno-single-exit
+@opindex msingle-exit
+@opindex mno-single-exit
+Force (do not force) generated code to have a single exit point in each
+function.
@end table
-@node ARC Options
-@subsection ARC Options
-@cindex ARC Options
+@node MN10300 Options
+@subsection MN10300 Options
+@cindex MN10300 options
-These options are defined for ARC implementations:
+These @option{-m} options are defined for Matsushita MN10300 architectures:
@table @gcctabopt
-@item -EL
-@opindex EL
-Compile code for little endian mode. This is the default.
+@item -mmult-bug
+@opindex mmult-bug
+Generate code to avoid bugs in the multiply instructions for the MN10300
+processors. This is the default.
-@item -EB
-@opindex EB
-Compile code for big endian mode.
+@item -mno-mult-bug
+@opindex mno-mult-bug
+Do not generate code to avoid bugs in the multiply instructions for the
+MN10300 processors.
-@item -mmangle-cpu
-@opindex mmangle-cpu
-Prepend the name of the cpu to all public symbol names.
-In multiple-processor systems, there are many ARC variants with different
-instruction and register set characteristics. This flag prevents code
-compiled for one cpu to be linked with code compiled for another.
-No facility exists for handling variants that are ``almost identical''.
-This is an all or nothing option.
+@item -mam33
+@opindex mam33
+Generate code which uses features specific to the AM33 processor.
-@item -mcpu=@var{cpu}
-@opindex mcpu
-Compile code for ARC variant @var{cpu}.
-Which variants are supported depend on the configuration.
-All variants support @option{-mcpu=base}, this is the default.
+@item -mno-am33
+@opindex mno-am33
+Do not generate code which uses features specific to the AM33 processor. This
+is the default.
-@item -mtext=@var{text-section}
-@itemx -mdata=@var{data-section}
-@itemx -mrodata=@var{readonly-data-section}
-@opindex mtext
-@opindex mdata
-@opindex mrodata
-Put functions, data, and readonly data in @var{text-section},
-@var{data-section}, and @var{readonly-data-section} respectively
-by default. This can be overridden with the @code{section} attribute.
-@xref{Variable Attributes}.
+@item -mno-crt0
+@opindex mno-crt0
+Do not link in the C run-time initialization object file.
+
+@item -mrelax
+@opindex mrelax
+Indicate to the linker that it should perform a relaxation optimization pass
+to shorten branches, calls and absolute memory addresses. This option only
+has an effect when used on the command line for the final link step.
+This option makes symbolic debugging impossible.
@end table
@node NS32K Options
Assume code will be loaded in the first 512MB of virtual address space.
This is the default for all platforms.
+@end table
+
+@node PDP-11 Options
+@subsection PDP-11 Options
+@cindex PDP-11 Options
+
+These options are defined for the PDP-11:
+
+@table @gcctabopt
+@item -mfpu
+@opindex mfpu
+Use hardware FPP floating point. This is the default. (FIS floating
+point on the PDP-11/40 is not supported.)
+
+@item -msoft-float
+@opindex msoft-float
+Do not use hardware floating point.
+
+@item -mac0
+@opindex mac0
+Return floating-point results in ac0 (fr0 in Unix assembler syntax).
+
+@item -mno-ac0
+@opindex mno-ac0
+Return floating-point results in memory. This is the default.
+
+@item -m40
+@opindex m40
+Generate code for a PDP-11/40.
+
+@item -m45
+@opindex m45
+Generate code for a PDP-11/45. This is the default.
+
+@item -m10
+@opindex m10
+Generate code for a PDP-11/10.
+
+@item -mbcopy-builtin
+@opindex bcopy-builtin
+Use inline @code{movstrhi} patterns for copying memory. This is the
+default.
+
+@item -mbcopy
+@opindex mbcopy
+Do not use inline @code{movstrhi} patterns for copying memory.
+
+@item -mint16
+@itemx -mno-int32
+@opindex mint16
+@opindex mno-int32
+Use 16-bit @code{int}. This is the default.
+
+@item -mint32
+@itemx -mno-int16
+@opindex mint32
+@opindex mno-int16
+Use 32-bit @code{int}.
+
+@item -mfloat64
+@itemx -mno-float32
+@opindex mfloat64
+@opindex mno-float32
+Use 64-bit @code{float}. This is the default.
+
+@item -mfloat32
+@itemx -mno-float64
+@opindex mfloat32
+@opindex mno-float64
+Use 32-bit @code{float}.
+
+@item -mabshi
+@opindex mabshi
+Use @code{abshi2} pattern. This is the default.
+
+@item -mno-abshi
+@opindex mno-abshi
+Do not use @code{abshi2} pattern.
+
+@item -mbranch-expensive
+@opindex mbranch-expensive
+Pretend that branches are expensive. This is for experimenting with
+code generation only.
+
+@item -mbranch-cheap
+@opindex mbranch-cheap
+Do not pretend that branches are expensive. This is the default.
+
+@item -msplit
+@opindex msplit
+Generate code for a system with split I&D.
+
+@item -mno-split
+@opindex mno-split
+Generate code for a system without split I&D. This is the default.
+
+@item -munix-asm
+@opindex munix-asm
+Use Unix assembler syntax. This is the default when configured for
+@samp{pdp11-*-bsd}.
+@item -mdec-asm
+@opindex mdec-asm
+Use DEC assembler syntax. This is the default when configured for any
+PDP-11 target other than @samp{pdp11-*-bsd}.
@end table
-@node AVR Options
-@subsection AVR Options
-@cindex AVR Options
+@node PowerPC Options
+@subsection PowerPC Options
+@cindex PowerPC options
-These options are defined for AVR implementations:
+These are listed under @xref{RS/6000 and PowerPC Options}.
+
+@node RS/6000 and PowerPC Options
+@subsection IBM RS/6000 and PowerPC Options
+@cindex RS/6000 and PowerPC Options
+@cindex IBM RS/6000 and PowerPC Options
+These @samp{-m} options are defined for the IBM RS/6000 and PowerPC:
@table @gcctabopt
-@item -mmcu=@var{mcu}
-@opindex mmcu
-Specify ATMEL AVR instruction set or MCU type.
+@item -mpower
+@itemx -mno-power
+@itemx -mpower2
+@itemx -mno-power2
+@itemx -mpowerpc
+@itemx -mno-powerpc
+@itemx -mpowerpc-gpopt
+@itemx -mno-powerpc-gpopt
+@itemx -mpowerpc-gfxopt
+@itemx -mno-powerpc-gfxopt
+@itemx -mpowerpc64
+@itemx -mno-powerpc64
+@opindex mpower
+@opindex mno-power
+@opindex mpower2
+@opindex mno-power2
+@opindex mpowerpc
+@opindex mno-powerpc
+@opindex mpowerpc-gpopt
+@opindex mno-powerpc-gpopt
+@opindex mpowerpc-gfxopt
+@opindex mno-powerpc-gfxopt
+@opindex mpowerpc64
+@opindex mno-powerpc64
+GCC supports two related instruction set architectures for the
+RS/6000 and PowerPC@. The @dfn{POWER} instruction set are those
+instructions supported by the @samp{rios} chip set used in the original
+RS/6000 systems and the @dfn{PowerPC} instruction set is the
+architecture of the Motorola MPC5xx, MPC6xx, MPC8xx microprocessors, and
+the IBM 4xx microprocessors.
-Instruction set avr1 is for the minimal AVR core, not supported by the C
-compiler, only for assembler programs (MCU types: at90s1200, attiny10,
-attiny11, attiny12, attiny15, attiny28).
+Neither architecture is a subset of the other. However there is a
+large common subset of instructions supported by both. An MQ
+register is included in processors supporting the POWER architecture.
-Instruction set avr2 (default) is for the classic AVR core with up to
-8K program memory space (MCU types: at90s2313, at90s2323, attiny22,
-at90s2333, at90s2343, at90s4414, at90s4433, at90s4434, at90s8515,
-at90c8534, at90s8535).
+You use these options to specify which instructions are available on the
+processor you are using. The default value of these options is
+determined when configuring GCC@. Specifying the
+@option{-mcpu=@var{cpu_type}} overrides the specification of these
+options. We recommend you use the @option{-mcpu=@var{cpu_type}} option
+rather than the options listed above.
-Instruction set avr3 is for the classic AVR core with up to 128K program
-memory space (MCU types: atmega103, atmega603, at43usb320, at76c711).
+The @option{-mpower} option allows GCC to generate instructions that
+are found only in the POWER architecture and to use the MQ register.
+Specifying @option{-mpower2} implies @option{-power} and also allows GCC
+to generate instructions that are present in the POWER2 architecture but
+not the original POWER architecture.
-Instruction set avr4 is for the enhanced AVR core with up to 8K program
-memory space (MCU types: atmega8, atmega83, atmega85).
+The @option{-mpowerpc} option allows GCC to generate instructions that
+are found only in the 32-bit subset of the PowerPC architecture.
+Specifying @option{-mpowerpc-gpopt} implies @option{-mpowerpc} and also allows
+GCC to use the optional PowerPC architecture instructions in the
+General Purpose group, including floating-point square root. Specifying
+@option{-mpowerpc-gfxopt} implies @option{-mpowerpc} and also allows GCC to
+use the optional PowerPC architecture instructions in the Graphics
+group, including floating-point select.
-Instruction set avr5 is for the enhanced AVR core with up to 128K program
-memory space (MCU types: atmega16, atmega161, atmega163, atmega32, atmega323,
-atmega64, atmega128, at43usb355, at94k).
+The @option{-mpowerpc64} option allows GCC to generate the additional
+64-bit instructions that are found in the full PowerPC64 architecture
+and to treat GPRs as 64-bit, doubleword quantities. GCC defaults to
+@option{-mno-powerpc64}.
-@item -msize
-@opindex msize
-Output instruction sizes to the asm file.
+If you specify both @option{-mno-power} and @option{-mno-powerpc}, GCC
+will use only the instructions in the common subset of both
+architectures plus some special AIX common-mode calls, and will not use
+the MQ register. Specifying both @option{-mpower} and @option{-mpowerpc}
+permits GCC to use any instruction from either architecture and to
+allow use of the MQ register; specify this for the Motorola MPC601.
-@item -minit-stack=@var{N}
-@opindex minit-stack
-Specify the initial stack address, which may be a symbol or numeric value,
-@samp{__stack} is the default.
+@item -mnew-mnemonics
+@itemx -mold-mnemonics
+@opindex mnew-mnemonics
+@opindex mold-mnemonics
+Select which mnemonics to use in the generated assembler code. With
+@option{-mnew-mnemonics}, GCC uses the assembler mnemonics defined for
+the PowerPC architecture. With @option{-mold-mnemonics} it uses the
+assembler mnemonics defined for the POWER architecture. Instructions
+defined in only one architecture have only one mnemonic; GCC uses that
+mnemonic irrespective of which of these options is specified.
-@item -mno-interrupts
-@opindex mno-interrupts
-Generated code is not compatible with hardware interrupts.
-Code size will be smaller.
+GCC defaults to the mnemonics appropriate for the architecture in
+use. Specifying @option{-mcpu=@var{cpu_type}} sometimes overrides the
+value of these option. Unless you are building a cross-compiler, you
+should normally not specify either @option{-mnew-mnemonics} or
+@option{-mold-mnemonics}, but should instead accept the default.
-@item -mcall-prologues
-@opindex mcall-prologues
-Functions prologues/epilogues expanded as call to appropriate
-subroutines. Code size will be smaller.
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set architecture type, register usage, choice of mnemonics, and
+instruction scheduling parameters for machine type @var{cpu_type}.
+Supported values for @var{cpu_type} are @samp{401}, @samp{403},
+@samp{405}, @samp{405fp}, @samp{440}, @samp{440fp}, @samp{505},
+@samp{601}, @samp{602}, @samp{603}, @samp{603e}, @samp{604},
+@samp{604e}, @samp{620}, @samp{630}, @samp{740}, @samp{7400},
+@samp{7450}, @samp{750}, @samp{801}, @samp{821}, @samp{823},
+@samp{860}, @samp{970}, @samp{common}, @samp{ec603e}, @samp{G3},
+@samp{G4}, @samp{G5}, @samp{power}, @samp{power2}, @samp{power3},
+@samp{power4}, @samp{power5}, @samp{powerpc}, @samp{powerpc64},
+@samp{rios}, @samp{rios1}, @samp{rios2}, @samp{rsc}, and @samp{rs64a}.
-@item -mno-tablejump
-@opindex mno-tablejump
-Do not generate tablejump insns which sometimes increase code size.
+@option{-mcpu=common} selects a completely generic processor. Code
+generated under this option will run on any POWER or PowerPC processor.
+GCC will use only the instructions in the common subset of both
+architectures, and will not use the MQ register. GCC assumes a generic
+processor model for scheduling purposes.
+
+@option{-mcpu=power}, @option{-mcpu=power2}, @option{-mcpu=powerpc}, and
+@option{-mcpu=powerpc64} specify generic POWER, POWER2, pure 32-bit
+PowerPC (i.e., not MPC601), and 64-bit PowerPC architecture machine
+types, with an appropriate, generic processor model assumed for
+scheduling purposes.
+
+The other options specify a specific processor. Code generated under
+those options will run best on that processor, and may not run at all on
+others.
-@item -mtiny-stack
-@opindex mtiny-stack
-Change only the low 8 bits of the stack pointer.
-@end table
+The @option{-mcpu} options automatically enable or disable the
+following options: @option{-maltivec}, @option{-mhard-float},
+@option{-mmfcrf}, @option{-mmultiple}, @option{-mnew-mnemonics},
+@option{-mpower}, @option{-mpower2}, @option{-mpowerpc64},
+@option{-mpowerpc-gpopt}, @option{-mpowerpc-gfxopt},
+@option{-mstring}. The particular options set for any particular CPU
+will vary between compiler versions, depending on what setting seems
+to produce optimal code for that CPU; it doesn't necessarily reflect
+the actual hardware's capabilities. If you wish to set an individual
+option to a particular value, you may specify it after the
+@option{-mcpu} option, like @samp{-mcpu=970 -mno-altivec}.
-@node MCore Options
-@subsection MCore Options
-@cindex MCore options
+On AIX, the @option{-maltivec} and @option{-mpowerpc64} options are
+not enabled or disabled by the @option{-mcpu} option at present, since
+AIX does not have full support for these options. You may still
+enable or disable them individually if you're sure it'll work in your
+environment.
-These are the @samp{-m} options defined for the Motorola M*Core
-processors.
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set the instruction scheduling parameters for machine type
+@var{cpu_type}, but do not set the architecture type, register usage, or
+choice of mnemonics, as @option{-mcpu=@var{cpu_type}} would. The same
+values for @var{cpu_type} are used for @option{-mtune} as for
+@option{-mcpu}. If both are specified, the code generated will use the
+architecture, registers, and mnemonics set by @option{-mcpu}, but the
+scheduling parameters set by @option{-mtune}.
-@table @gcctabopt
+@item -maltivec
+@itemx -mno-altivec
+@opindex maltivec
+@opindex mno-altivec
+These switches enable or disable the use of built-in functions that
+allow access to the AltiVec instruction set. You may also need to set
+@option{-mabi=altivec} to adjust the current ABI with AltiVec ABI
+enhancements.
-@item -mhardlit
-@itemx -mno-hardlit
-@opindex mhardlit
-@opindex mno-hardlit
-Inline constants into the code stream if it can be done in two
-instructions or less.
+@item -mabi=spe
+@opindex mabi=spe
+Extend the current ABI with SPE ABI extensions. This does not change
+the default ABI, instead it adds the SPE ABI extensions to the current
+ABI@.
-@item -mdiv
-@itemx -mno-div
-@opindex mdiv
-@opindex mno-div
-Use the divide instruction. (Enabled by default).
+@item -mabi=no-spe
+@opindex mabi=no-spe
+Disable Booke SPE ABI extensions for the current ABI.
-@item -mrelax-immediate
-@itemx -mno-relax-immediate
-@opindex mrelax-immediate
-@opindex mno-relax-immediate
-Allow arbitrary sized immediates in bit operations.
+@item -misel=@var{yes/no}
+@itemx -misel
+@opindex misel
+This switch enables or disables the generation of ISEL instructions.
-@item -mwide-bitfields
-@itemx -mno-wide-bitfields
-@opindex mwide-bitfields
-@opindex mno-wide-bitfields
-Always treat bit-fields as int-sized.
+@item -mspe=@var{yes/no}
+@itemx -mspe
+@opindex mspe
+This switch enables or disables the generation of SPE simd
+instructions.
-@item -m4byte-functions
-@itemx -mno-4byte-functions
-@opindex m4byte-functions
-@opindex mno-4byte-functions
-Force all functions to be aligned to a four byte boundary.
+@item -mfloat-gprs=@var{yes/no}
+@itemx -mfloat-gprs
+@opindex mfloat-gprs
+This switch enables or disables the generation of floating point
+operations on the general purpose registers for architectures that
+support it. This option is currently only available on the MPC8540.
-@item -mcallgraph-data
-@itemx -mno-callgraph-data
-@opindex mcallgraph-data
-@opindex mno-callgraph-data
-Emit callgraph information.
+@item -mfull-toc
+@itemx -mno-fp-in-toc
+@itemx -mno-sum-in-toc
+@itemx -mminimal-toc
+@opindex mfull-toc
+@opindex mno-fp-in-toc
+@opindex mno-sum-in-toc
+@opindex mminimal-toc
+Modify generation of the TOC (Table Of Contents), which is created for
+every executable file. The @option{-mfull-toc} option is selected by
+default. In that case, GCC will allocate at least one TOC entry for
+each unique non-automatic variable reference in your program. GCC
+will also place floating-point constants in the TOC@. However, only
+16,384 entries are available in the TOC@.
-@item -mslow-bytes
-@itemx -mno-slow-bytes
-@opindex mslow-bytes
-@opindex mno-slow-bytes
-Prefer word access when reading byte quantities.
+If you receive a linker error message that saying you have overflowed
+the available TOC space, you can reduce the amount of TOC space used
+with the @option{-mno-fp-in-toc} and @option{-mno-sum-in-toc} options.
+@option{-mno-fp-in-toc} prevents GCC from putting floating-point
+constants in the TOC and @option{-mno-sum-in-toc} forces GCC to
+generate code to calculate the sum of an address and a constant at
+run-time instead of putting that sum into the TOC@. You may specify one
+or both of these options. Each causes GCC to produce very slightly
+slower and larger code at the expense of conserving TOC space.
-@item -mlittle-endian
-@itemx -mbig-endian
-@opindex mlittle-endian
-@opindex mbig-endian
-Generate code for a little endian target.
+If you still run out of space in the TOC even when you specify both of
+these options, specify @option{-mminimal-toc} instead. This option causes
+GCC to make only one TOC entry for every file. When you specify this
+option, GCC will produce code that is slower and larger but which
+uses extremely little TOC space. You may wish to use this option
+only on files that contain less frequently executed code.
-@item -m210
-@itemx -m340
-@opindex m210
-@opindex m340
-Generate code for the 210 processor.
-@end table
+@item -maix64
+@itemx -maix32
+@opindex maix64
+@opindex maix32
+Enable 64-bit AIX ABI and calling convention: 64-bit pointers, 64-bit
+@code{long} type, and the infrastructure needed to support them.
+Specifying @option{-maix64} implies @option{-mpowerpc64} and
+@option{-mpowerpc}, while @option{-maix32} disables the 64-bit ABI and
+implies @option{-mno-powerpc64}. GCC defaults to @option{-maix32}.
-@node IA-64 Options
-@subsection IA-64 Options
-@cindex IA-64 Options
+@item -mxl-call
+@itemx -mno-xl-call
+@opindex mxl-call
+@opindex mno-xl-call
+On AIX, pass floating-point arguments to prototyped functions beyond the
+register save area (RSA) on the stack in addition to argument FPRs. The
+AIX calling convention was extended but not initially documented to
+handle an obscure K&R C case of calling a function that takes the
+address of its arguments with fewer arguments than declared. AIX XL
+compilers access floating point arguments which do not fit in the
+RSA from the stack when a subroutine is compiled without
+optimization. Because always storing floating-point arguments on the
+stack is inefficient and rarely needed, this option is not enabled by
+default and only is necessary when calling subroutines compiled by AIX
+XL compilers without optimization.
-These are the @samp{-m} options defined for the Intel IA-64 architecture.
+@item -mpe
+@opindex mpe
+Support @dfn{IBM RS/6000 SP} @dfn{Parallel Environment} (PE)@. Link an
+application written to use message passing with special startup code to
+enable the application to run. The system must have PE installed in the
+standard location (@file{/usr/lpp/ppe.poe/}), or the @file{specs} file
+must be overridden with the @option{-specs=} option to specify the
+appropriate directory location. The Parallel Environment does not
+support threads, so the @option{-mpe} option and the @option{-pthread}
+option are incompatible.
-@table @gcctabopt
-@item -mbig-endian
-@opindex mbig-endian
-Generate code for a big endian target. This is the default for HP-UX@.
+@item -malign-natural
+@itemx -malign-power
+@opindex malign-natural
+@opindex malign-power
+On AIX, Darwin, and 64-bit PowerPC GNU/Linux, the option
+@option{-malign-natural} overrides the ABI-defined alignment of larger
+types, such as floating-point doubles, on their natural size-based boundary.
+The option @option{-malign-power} instructs GCC to follow the ABI-specified
+alignment rules. GCC defaults to the standard alignment defined in the ABI.
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a little endian target. This is the default for AIX5
-and GNU/Linux.
+@item -msoft-float
+@itemx -mhard-float
+@opindex msoft-float
+@opindex mhard-float
+Generate code that does not use (uses) the floating-point register set.
+Software floating point emulation is provided if you use the
+@option{-msoft-float} option, and pass the option to GCC when linking.
-@item -mgnu-as
-@itemx -mno-gnu-as
-@opindex mgnu-as
-@opindex mno-gnu-as
-Generate (or don't) code for the GNU assembler. This is the default.
-@c Also, this is the default if the configure option @option{--with-gnu-as}
-@c is used.
+@item -mmultiple
+@itemx -mno-multiple
+@opindex mmultiple
+@opindex mno-multiple
+Generate code that uses (does not use) the load multiple word
+instructions and the store multiple word instructions. These
+instructions are generated by default on POWER systems, and not
+generated on PowerPC systems. Do not use @option{-mmultiple} on little
+endian PowerPC systems, since those instructions do not work when the
+processor is in little endian mode. The exceptions are PPC740 and
+PPC750 which permit the instructions usage in little endian mode.
-@item -mgnu-ld
-@itemx -mno-gnu-ld
-@opindex mgnu-ld
-@opindex mno-gnu-ld
-Generate (or don't) code for the GNU linker. This is the default.
-@c Also, this is the default if the configure option @option{--with-gnu-ld}
-@c is used.
+@item -mstring
+@itemx -mno-string
+@opindex mstring
+@opindex mno-string
+Generate code that uses (does not use) the load string instructions
+and the store string word instructions to save multiple registers and
+do small block moves. These instructions are generated by default on
+POWER systems, and not generated on PowerPC systems. Do not use
+@option{-mstring} on little endian PowerPC systems, since those
+instructions do not work when the processor is in little endian mode.
+The exceptions are PPC740 and PPC750 which permit the instructions
+usage in little endian mode.
-@item -mno-pic
-@opindex mno-pic
-Generate code that does not use a global pointer register. The result
-is not position independent code, and violates the IA-64 ABI@.
+@item -mupdate
+@itemx -mno-update
+@opindex mupdate
+@opindex mno-update
+Generate code that uses (does not use) the load or store instructions
+that update the base register to the address of the calculated memory
+location. These instructions are generated by default. If you use
+@option{-mno-update}, there is a small window between the time that the
+stack pointer is updated and the address of the previous frame is
+stored, which means code that walks the stack frame across interrupts or
+signals may get corrupted data.
-@item -mvolatile-asm-stop
-@itemx -mno-volatile-asm-stop
-@opindex mvolatile-asm-stop
-@opindex mno-volatile-asm-stop
-Generate (or don't) a stop bit immediately before and after volatile asm
-statements.
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Generate code that uses (does not use) the floating point multiply and
+accumulate instructions. These instructions are generated by default if
+hardware floating is used.
-@item -mb-step
-@opindex mb-step
-Generate code that works around Itanium B step errata.
+@item -mno-bit-align
+@itemx -mbit-align
+@opindex mno-bit-align
+@opindex mbit-align
+On System V.4 and embedded PowerPC systems do not (do) force structures
+and unions that contain bit-fields to be aligned to the base type of the
+bit-field.
-@item -mregister-names
-@itemx -mno-register-names
-@opindex mregister-names
-@opindex mno-register-names
-Generate (or don't) @samp{in}, @samp{loc}, and @samp{out} register names for
-the stacked registers. This may make assembler output more readable.
+For example, by default a structure containing nothing but 8
+@code{unsigned} bit-fields of length 1 would be aligned to a 4 byte
+boundary and have a size of 4 bytes. By using @option{-mno-bit-align},
+the structure would be aligned to a 1 byte boundary and be one byte in
+size.
-@item -mno-sdata
-@itemx -msdata
-@opindex mno-sdata
-@opindex msdata
-Disable (or enable) optimizations that use the small data section. This may
-be useful for working around optimizer bugs.
+@item -mno-strict-align
+@itemx -mstrict-align
+@opindex mno-strict-align
+@opindex mstrict-align
+On System V.4 and embedded PowerPC systems do not (do) assume that
+unaligned memory references will be handled by the system.
-@item -mconstant-gp
-@opindex mconstant-gp
-Generate code that uses a single constant global pointer value. This is
-useful when compiling kernel code.
+@item -mrelocatable
+@itemx -mno-relocatable
+@opindex mrelocatable
+@opindex mno-relocatable
+On embedded PowerPC systems generate code that allows (does not allow)
+the program to be relocated to a different address at runtime. If you
+use @option{-mrelocatable} on any module, all objects linked together must
+be compiled with @option{-mrelocatable} or @option{-mrelocatable-lib}.
-@item -mauto-pic
-@opindex mauto-pic
-Generate code that is self-relocatable. This implies @option{-mconstant-gp}.
-This is useful when compiling firmware code.
+@item -mrelocatable-lib
+@itemx -mno-relocatable-lib
+@opindex mrelocatable-lib
+@opindex mno-relocatable-lib
+On embedded PowerPC systems generate code that allows (does not allow)
+the program to be relocated to a different address at runtime. Modules
+compiled with @option{-mrelocatable-lib} can be linked with either modules
+compiled without @option{-mrelocatable} and @option{-mrelocatable-lib} or
+with modules compiled with the @option{-mrelocatable} options.
-@item -minline-float-divide-min-latency
-@opindex minline-float-divide-min-latency
-Generate code for inline divides of floating point values
-using the minimum latency algorithm.
+@item -mno-toc
+@itemx -mtoc
+@opindex mno-toc
+@opindex mtoc
+On System V.4 and embedded PowerPC systems do not (do) assume that
+register 2 contains a pointer to a global area pointing to the addresses
+used in the program.
-@item -minline-float-divide-max-throughput
-@opindex minline-float-divide-max-throughput
-Generate code for inline divides of floating point values
-using the maximum throughput algorithm.
+@item -mlittle
+@itemx -mlittle-endian
+@opindex mlittle
+@opindex mlittle-endian
+On System V.4 and embedded PowerPC systems compile code for the
+processor in little endian mode. The @option{-mlittle-endian} option is
+the same as @option{-mlittle}.
-@item -minline-int-divide-min-latency
-@opindex minline-int-divide-min-latency
-Generate code for inline divides of integer values
-using the minimum latency algorithm.
+@item -mbig
+@itemx -mbig-endian
+@opindex mbig
+@opindex mbig-endian
+On System V.4 and embedded PowerPC systems compile code for the
+processor in big endian mode. The @option{-mbig-endian} option is
+the same as @option{-mbig}.
-@item -minline-int-divide-max-throughput
-@opindex minline-int-divide-max-throughput
-Generate code for inline divides of integer values
-using the maximum throughput algorithm.
+@item -mdynamic-no-pic
+@opindex mdynamic-no-pic
+On Darwin and Mac OS X systems, compile code so that it is not
+relocatable, but that its external references are relocatable. The
+resulting code is suitable for applications, but not shared
+libraries.
-@item -mno-dwarf2-asm
-@itemx -mdwarf2-asm
-@opindex mno-dwarf2-asm
-@opindex mdwarf2-asm
-Don't (or do) generate assembler code for the DWARF2 line number debugging
-info. This may be useful when not using the GNU assembler.
+@item -mprioritize-restricted-insns=@var{priority}
+@opindex mprioritize-restricted-insns
+This option controls the priority that is assigned to
+dispatch-slot restricted instructions during the second scheduling
+pass. The argument @var{priority} takes the value @var{0/1/2} to assign
+@var{no/highest/second-highest} priority to dispatch slot restricted
+instructions.
-@item -mfixed-range=@var{register-range}
-@opindex mfixed-range
-Generate code treating the given register range as fixed registers.
-A fixed register is one that the register allocator can not use. This is
-useful when compiling kernel code. A register range is specified as
-two registers separated by a dash. Multiple register ranges can be
-specified separated by a comma.
+@item -msched-costly-dep=@var{dependence_type}
+@opindex msched-costly-dep
+This option controls which dependences are considered costly
+by the target during instruction scheduling. The argument
+@var{dependence_type} takes one of the following values:
+@var{no}: no dependence is costly,
+@var{all}: all dependences are costly,
+@var{true_store_to_load}: a true dependence from store to load is costly,
+@var{store_to_load}: any dependence from store to load is costly,
+@var{number}: any dependence which latency >= @var{number} is costly.
-@item -mearly-stop-bits
-@itemx -mno-early-stop-bits
-@opindex mearly-stop-bits
-@opindex mno-early-stop-bits
-Allow stop bits to be placed earlier than immediately preceding the
-instruction that triggered the stop bit. This can improve instruction
-scheduling, but does not always do so.
-@end table
+@item -minsert-sched-nops=@var{scheme}
+@opindex minsert-sched-nops
+This option controls which nop insertion scheme will be used during
+the second scheduling pass. The argument @var{scheme} takes one of the
+following values:
+@var{no}: Don't insert nops.
+@var{pad}: Pad with nops any dispatch group which has vacant issue slots,
+according to the scheduler's grouping.
+@var{regroup_exact}: Insert nops to force costly dependent insns into
+separate groups. Insert exactly as many nops as needed to force an insn
+to a new group, according to the estimated processor grouping.
+@var{number}: Insert nops to force costly dependent insns into
+separate groups. Insert @var{number} nops to force an insn to a new group.
-@node S/390 and zSeries Options
-@subsection S/390 and zSeries Options
-@cindex S/390 and zSeries Options
+@item -mcall-sysv
+@opindex mcall-sysv
+On System V.4 and embedded PowerPC systems compile code using calling
+conventions that adheres to the March 1995 draft of the System V
+Application Binary Interface, PowerPC processor supplement. This is the
+default unless you configured GCC using @samp{powerpc-*-eabiaix}.
-These are the @samp{-m} options defined for the S/390 and zSeries architecture.
+@item -mcall-sysv-eabi
+@opindex mcall-sysv-eabi
+Specify both @option{-mcall-sysv} and @option{-meabi} options.
-@table @gcctabopt
-@item -mhard-float
-@itemx -msoft-float
-@opindex mhard-float
-@opindex msoft-float
-Use (do not use) the hardware floating-point instructions and registers
-for floating-point operations. When @option{-msoft-float} is specified,
-functions in @file{libgcc.a} will be used to perform floating-point
-operations. When @option{-mhard-float} is specified, the compiler
-generates IEEE floating-point instructions. This is the default.
+@item -mcall-sysv-noeabi
+@opindex mcall-sysv-noeabi
+Specify both @option{-mcall-sysv} and @option{-mno-eabi} options.
-@item -mbackchain
-@itemx -mno-backchain
-@opindex mbackchain
-@opindex mno-backchain
-Generate (or do not generate) code which maintains an explicit
-backchain within the stack frame that points to the caller's frame.
-This may be needed to allow debugging using tools that do not understand
-DWARF-2 call frame information. The default is not to generate the
-backchain.
+@item -mcall-solaris
+@opindex mcall-solaris
+On System V.4 and embedded PowerPC systems compile code for the Solaris
+operating system.
-@item -msmall-exec
-@itemx -mno-small-exec
-@opindex msmall-exec
-@opindex mno-small-exec
-Generate (or do not generate) code using the @code{bras} instruction
-to do subroutine calls.
-This only works reliably if the total executable size does not
-exceed 64k. The default is to use the @code{basr} instruction instead,
-which does not have this limitation.
+@item -mcall-linux
+@opindex mcall-linux
+On System V.4 and embedded PowerPC systems compile code for the
+Linux-based GNU system.
-@item -m64
-@itemx -m31
-@opindex m64
-@opindex m31
-When @option{-m31} is specified, generate code compliant to the
-GNU/Linux for S/390 ABI@. When @option{-m64} is specified, generate
-code compliant to the GNU/Linux for zSeries ABI@. This allows GCC in
-particular to generate 64-bit instructions. For the @samp{s390}
-targets, the default is @option{-m31}, while the @samp{s390x}
-targets default to @option{-m64}.
+@item -mcall-gnu
+@opindex mcall-gnu
+On System V.4 and embedded PowerPC systems compile code for the
+Hurd-based GNU system.
-@item -mzarch
-@itemx -mesa
-@opindex mzarch
-@opindex mesa
-When @option{-mzarch} is specified, generate code using the
-instructions available on z/Architecture.
-When @option{-mesa} is specified, generate code using the
-instructions available on ESA/390. Note that @option{-mesa} is
-not possible with @option{-m64}.
-When generating code compliant to the GNU/Linux for S/390 ABI,
-the default is @option{-mesa}. When generating code compliant
-to the GNU/Linux for zSeries ABI, the default is @option{-mzarch}.
+@item -mcall-netbsd
+@opindex mcall-netbsd
+On System V.4 and embedded PowerPC systems compile code for the
+NetBSD operating system.
-@item -mmvcle
-@itemx -mno-mvcle
-@opindex mmvcle
-@opindex mno-mvcle
-Generate (or do not generate) code using the @code{mvcle} instruction
-to perform block moves. When @option{-mno-mvcle} is specified,
-use a @code{mvc} loop instead. This is the default.
+@item -maix-struct-return
+@opindex maix-struct-return
+Return all structures in memory (as specified by the AIX ABI)@.
-@item -mdebug
-@itemx -mno-debug
-@opindex mdebug
-@opindex mno-debug
-Print (or do not print) additional debug information when compiling.
-The default is to not print debug information.
+@item -msvr4-struct-return
+@opindex msvr4-struct-return
+Return structures smaller than 8 bytes in registers (as specified by the
+SVR4 ABI)@.
-@item -march=@var{cpu-type}
-@opindex march
-Generate code that will run on @var{cpu-type}, which is the name of a system
-representing a certain processor type. Possible values for
-@var{cpu-type} are @samp{g5}, @samp{g6}, @samp{z900}, and @samp{z990}.
-When generating code using the instructions available on z/Architecture,
-the default is @option{-march=z900}. Otherwise, the default is
-@option{-march=g5}.
+@item -mabi=altivec
+@opindex mabi=altivec
+Extend the current ABI with AltiVec ABI extensions. This does not
+change the default ABI, instead it adds the AltiVec ABI extensions to
+the current ABI@.
-@item -mtune=@var{cpu-type}
-@opindex mtune
-Tune to @var{cpu-type} everything applicable about the generated code,
-except for the ABI and the set of available instructions.
-The list of @var{cpu-type} values is the same as for @option{-march}.
-The default is the value used for @option{-march}.
+@item -mabi=no-altivec
+@opindex mabi=no-altivec
+Disable AltiVec ABI extensions for the current ABI.
-@item -mfused-madd
-@itemx -mno-fused-madd
-@opindex mfused-madd
-@opindex mno-fused-madd
-Generate code that uses (does not use) the floating point multiply and
-accumulate instructions. These instructions are generated by default if
-hardware floating point is used.
-@end table
+@item -mprototype
+@itemx -mno-prototype
+@opindex mprototype
+@opindex mno-prototype
+On System V.4 and embedded PowerPC systems assume that all calls to
+variable argument functions are properly prototyped. Otherwise, the
+compiler must insert an instruction before every non prototyped call to
+set or clear bit 6 of the condition code register (@var{CR}) to
+indicate whether floating point values were passed in the floating point
+registers in case the function takes a variable arguments. With
+@option{-mprototype}, only calls to prototyped variable argument functions
+will set or clear the bit.
-@node CRIS Options
-@subsection CRIS Options
-@cindex CRIS Options
+@item -msim
+@opindex msim
+On embedded PowerPC systems, assume that the startup module is called
+@file{sim-crt0.o} and that the standard C libraries are @file{libsim.a} and
+@file{libc.a}. This is the default for @samp{powerpc-*-eabisim}.
+configurations.
-These options are defined specifically for the CRIS ports.
+@item -mmvme
+@opindex mmvme
+On embedded PowerPC systems, assume that the startup module is called
+@file{crt0.o} and the standard C libraries are @file{libmvme.a} and
+@file{libc.a}.
-@table @gcctabopt
-@item -march=@var{architecture-type}
-@itemx -mcpu=@var{architecture-type}
-@opindex march
-@opindex mcpu
-Generate code for the specified architecture. The choices for
-@var{architecture-type} are @samp{v3}, @samp{v8} and @samp{v10} for
-respectively ETRAX@w{ }4, ETRAX@w{ }100, and ETRAX@w{ }100@w{ }LX.
-Default is @samp{v0} except for cris-axis-linux-gnu, where the default is
-@samp{v10}.
+@item -mads
+@opindex mads
+On embedded PowerPC systems, assume that the startup module is called
+@file{crt0.o} and the standard C libraries are @file{libads.a} and
+@file{libc.a}.
-@item -mtune=@var{architecture-type}
-@opindex mtune
-Tune to @var{architecture-type} everything applicable about the generated
-code, except for the ABI and the set of available instructions. The
-choices for @var{architecture-type} are the same as for
-@option{-march=@var{architecture-type}}.
+@item -myellowknife
+@opindex myellowknife
+On embedded PowerPC systems, assume that the startup module is called
+@file{crt0.o} and the standard C libraries are @file{libyk.a} and
+@file{libc.a}.
-@item -mmax-stack-frame=@var{n}
-@opindex mmax-stack-frame
-Warn when the stack frame of a function exceeds @var{n} bytes.
+@item -mvxworks
+@opindex mvxworks
+On System V.4 and embedded PowerPC systems, specify that you are
+compiling for a VxWorks system.
-@item -melinux-stacksize=@var{n}
-@opindex melinux-stacksize
-Only available with the @samp{cris-axis-aout} target. Arranges for
-indications in the program to the kernel loader that the stack of the
-program should be set to @var{n} bytes.
+@item -mwindiss
+@opindex mwindiss
+Specify that you are compiling for the WindISS simulation environment.
-@item -metrax4
-@itemx -metrax100
-@opindex metrax4
-@opindex metrax100
-The options @option{-metrax4} and @option{-metrax100} are synonyms for
-@option{-march=v3} and @option{-march=v8} respectively.
+@item -memb
+@opindex memb
+On embedded PowerPC systems, set the @var{PPC_EMB} bit in the ELF flags
+header to indicate that @samp{eabi} extended relocations are used.
-@item -mmul-bug-workaround
-@itemx -mno-mul-bug-workaround
-@opindex mmul-bug-workaround
-@opindex mno-mul-bug-workaround
-Work around a bug in the @code{muls} and @code{mulu} instructions for CPU
-models where it applies. This option is active by default.
+@item -meabi
+@itemx -mno-eabi
+@opindex meabi
+@opindex mno-eabi
+On System V.4 and embedded PowerPC systems do (do not) adhere to the
+Embedded Applications Binary Interface (eabi) which is a set of
+modifications to the System V.4 specifications. Selecting @option{-meabi}
+means that the stack is aligned to an 8 byte boundary, a function
+@code{__eabi} is called to from @code{main} to set up the eabi
+environment, and the @option{-msdata} option can use both @code{r2} and
+@code{r13} to point to two separate small data areas. Selecting
+@option{-mno-eabi} means that the stack is aligned to a 16 byte boundary,
+do not call an initialization function from @code{main}, and the
+@option{-msdata} option will only use @code{r13} to point to a single
+small data area. The @option{-meabi} option is on by default if you
+configured GCC using one of the @samp{powerpc*-*-eabi*} options.
-@item -mpdebug
-@opindex mpdebug
-Enable CRIS-specific verbose debug-related information in the assembly
-code. This option also has the effect to turn off the @samp{#NO_APP}
-formatted-code indicator to the assembler at the beginning of the
-assembly file.
+@item -msdata=eabi
+@opindex msdata=eabi
+On System V.4 and embedded PowerPC systems, put small initialized
+@code{const} global and static data in the @samp{.sdata2} section, which
+is pointed to by register @code{r2}. Put small initialized
+non-@code{const} global and static data in the @samp{.sdata} section,
+which is pointed to by register @code{r13}. Put small uninitialized
+global and static data in the @samp{.sbss} section, which is adjacent to
+the @samp{.sdata} section. The @option{-msdata=eabi} option is
+incompatible with the @option{-mrelocatable} option. The
+@option{-msdata=eabi} option also sets the @option{-memb} option.
-@item -mcc-init
-@opindex mcc-init
-Do not use condition-code results from previous instruction; always emit
-compare and test instructions before use of condition codes.
+@item -msdata=sysv
+@opindex msdata=sysv
+On System V.4 and embedded PowerPC systems, put small global and static
+data in the @samp{.sdata} section, which is pointed to by register
+@code{r13}. Put small uninitialized global and static data in the
+@samp{.sbss} section, which is adjacent to the @samp{.sdata} section.
+The @option{-msdata=sysv} option is incompatible with the
+@option{-mrelocatable} option.
-@item -mno-side-effects
-@opindex mno-side-effects
-Do not emit instructions with side-effects in addressing modes other than
-post-increment.
+@item -msdata=default
+@itemx -msdata
+@opindex msdata=default
+@opindex msdata
+On System V.4 and embedded PowerPC systems, if @option{-meabi} is used,
+compile code the same as @option{-msdata=eabi}, otherwise compile code the
+same as @option{-msdata=sysv}.
-@item -mstack-align
-@itemx -mno-stack-align
-@itemx -mdata-align
-@itemx -mno-data-align
-@itemx -mconst-align
-@itemx -mno-const-align
-@opindex mstack-align
-@opindex mno-stack-align
-@opindex mdata-align
-@opindex mno-data-align
-@opindex mconst-align
-@opindex mno-const-align
-These options (no-options) arranges (eliminate arrangements) for the
-stack-frame, individual data and constants to be aligned for the maximum
-single data access size for the chosen CPU model. The default is to
-arrange for 32-bit alignment. ABI details such as structure layout are
-not affected by these options.
+@item -msdata-data
+@opindex msdata-data
+On System V.4 and embedded PowerPC systems, put small global and static
+data in the @samp{.sdata} section. Put small uninitialized global and
+static data in the @samp{.sbss} section. Do not use register @code{r13}
+to address small data however. This is the default behavior unless
+other @option{-msdata} options are used.
-@item -m32-bit
-@itemx -m16-bit
-@itemx -m8-bit
-@opindex m32-bit
-@opindex m16-bit
-@opindex m8-bit
-Similar to the stack- data- and const-align options above, these options
-arrange for stack-frame, writable data and constants to all be 32-bit,
-16-bit or 8-bit aligned. The default is 32-bit alignment.
+@item -msdata=none
+@itemx -mno-sdata
+@opindex msdata=none
+@opindex mno-sdata
+On embedded PowerPC systems, put all initialized global and static data
+in the @samp{.data} section, and all uninitialized data in the
+@samp{.bss} section.
-@item -mno-prologue-epilogue
-@itemx -mprologue-epilogue
-@opindex mno-prologue-epilogue
-@opindex mprologue-epilogue
-With @option{-mno-prologue-epilogue}, the normal function prologue and
-epilogue that sets up the stack-frame are omitted and no return
-instructions or return sequences are generated in the code. Use this
-option only together with visual inspection of the compiled code: no
-warnings or errors are generated when call-saved registers must be saved,
-or storage for local variable needs to be allocated.
+@item -G @var{num}
+@opindex G
+@cindex smaller data references (PowerPC)
+@cindex .sdata/.sdata2 references (PowerPC)
+On embedded PowerPC systems, put global and static items less than or
+equal to @var{num} bytes into the small data or bss sections instead of
+the normal data or bss section. By default, @var{num} is 8. The
+@option{-G @var{num}} switch is also passed to the linker.
+All modules should be compiled with the same @option{-G @var{num}} value.
-@item -mno-gotplt
-@itemx -mgotplt
-@opindex mno-gotplt
-@opindex mgotplt
-With @option{-fpic} and @option{-fPIC}, don't generate (do generate)
-instruction sequences that load addresses for functions from the PLT part
-of the GOT rather than (traditional on other architectures) calls to the
-PLT. The default is @option{-mgotplt}.
+@item -mregnames
+@itemx -mno-regnames
+@opindex mregnames
+@opindex mno-regnames
+On System V.4 and embedded PowerPC systems do (do not) emit register
+names in the assembly language output using symbolic forms.
-@item -maout
-@opindex maout
-Legacy no-op option only recognized with the cris-axis-aout target.
+@item -mlongcall
+@itemx -mno-longcall
+@opindex mlongcall
+@opindex mno-longcall
+Default to making all function calls indirectly, using a register, so
+that functions which reside further than 32 megabytes (33,554,432
+bytes) from the current location can be called. This setting can be
+overridden by the @code{shortcall} function attribute, or by
+@code{#pragma longcall(0)}.
-@item -melf
-@opindex melf
-Legacy no-op option only recognized with the cris-axis-elf and
-cris-axis-linux-gnu targets.
+Some linkers are capable of detecting out-of-range calls and generating
+glue code on the fly. On these systems, long calls are unnecessary and
+generate slower code. As of this writing, the AIX linker can do this,
+as can the GNU linker for PowerPC/64. It is planned to add this feature
+to the GNU linker for 32-bit PowerPC systems as well.
-@item -melinux
-@opindex melinux
-Only recognized with the cris-axis-aout target, where it selects a
-GNU/linux-like multilib, include files and instruction set for
-@option{-march=v8}.
+On Darwin/PPC systems, @code{#pragma longcall} will generate ``jbsr
+callee, L42'', plus a ``branch island'' (glue code). The two target
+addresses represent the callee and the ``branch island.'' The
+Darwin/PPC linker will prefer the first address and generate a ``bl
+callee'' if the PPC ``bl'' instruction will reach the callee directly;
+otherwise, the linker will generate ``bl L42'' to call the ``branch
+island.'' The ``branch island'' is appended to the body of the
+calling function; it computes the full 32-bit address of the callee
+and jumps to it.
-@item -mlinux
-@opindex mlinux
-Legacy no-op option only recognized with the cris-axis-linux-gnu target.
+On Mach-O (Darwin) systems, this option directs the compiler emit to
+the glue for every direct call, and the Darwin linker decides whether
+to use or discard it.
-@item -sim
-@opindex sim
-This option, recognized for the cris-axis-aout and cris-axis-elf arranges
-to link with input-output functions from a simulator library. Code,
-initialized data and zero-initialized data are allocated consecutively.
+In the future, we may cause GCC to ignore all longcall specifications
+when the linker is known to generate glue.
+
+@item -pthread
+@opindex pthread
+Adds support for multithreading with the @dfn{pthreads} library.
+This option sets flags for both the preprocessor and linker.
-@item -sim2
-@opindex sim2
-Like @option{-sim}, but pass linker options to locate initialized data at
-0x40000000 and zero-initialized data at 0x80000000.
@end table
-@node MMIX Options
-@subsection MMIX Options
-@cindex MMIX Options
+@node S/390 and zSeries Options
+@subsection S/390 and zSeries Options
+@cindex S/390 and zSeries Options
-These options are defined for the MMIX:
+These are the @samp{-m} options defined for the S/390 and zSeries architecture.
@table @gcctabopt
-@item -mlibfuncs
-@itemx -mno-libfuncs
-@opindex mlibfuncs
-@opindex mno-libfuncs
-Specify that intrinsic library functions are being compiled, passing all
-values in registers, no matter the size.
+@item -mhard-float
+@itemx -msoft-float
+@opindex mhard-float
+@opindex msoft-float
+Use (do not use) the hardware floating-point instructions and registers
+for floating-point operations. When @option{-msoft-float} is specified,
+functions in @file{libgcc.a} will be used to perform floating-point
+operations. When @option{-mhard-float} is specified, the compiler
+generates IEEE floating-point instructions. This is the default.
-@item -mepsilon
-@itemx -mno-epsilon
-@opindex mepsilon
-@opindex mno-epsilon
-Generate floating-point comparison instructions that compare with respect
-to the @code{rE} epsilon register.
+@item -mbackchain
+@itemx -mno-backchain
+@opindex mbackchain
+@opindex mno-backchain
+Generate (or do not generate) code which maintains an explicit
+backchain within the stack frame that points to the caller's frame.
+This may be needed to allow debugging using tools that do not understand
+DWARF-2 call frame information. The default is not to generate the
+backchain.
-@item -mabi=mmixware
-@itemx -mabi=gnu
-@opindex mabi-mmixware
-@opindex mabi=gnu
-Generate code that passes function parameters and return values that (in
-the called function) are seen as registers @code{$0} and up, as opposed to
-the GNU ABI which uses global registers @code{$231} and up.
+@item -msmall-exec
+@itemx -mno-small-exec
+@opindex msmall-exec
+@opindex mno-small-exec
+Generate (or do not generate) code using the @code{bras} instruction
+to do subroutine calls.
+This only works reliably if the total executable size does not
+exceed 64k. The default is to use the @code{basr} instruction instead,
+which does not have this limitation.
-@item -mzero-extend
-@itemx -mno-zero-extend
-@opindex mzero-extend
-@opindex mno-zero-extend
-When reading data from memory in sizes shorter than 64 bits, use (do not
-use) zero-extending load instructions by default, rather than
-sign-extending ones.
+@item -m64
+@itemx -m31
+@opindex m64
+@opindex m31
+When @option{-m31} is specified, generate code compliant to the
+GNU/Linux for S/390 ABI@. When @option{-m64} is specified, generate
+code compliant to the GNU/Linux for zSeries ABI@. This allows GCC in
+particular to generate 64-bit instructions. For the @samp{s390}
+targets, the default is @option{-m31}, while the @samp{s390x}
+targets default to @option{-m64}.
-@item -mknuthdiv
-@itemx -mno-knuthdiv
-@opindex mknuthdiv
-@opindex mno-knuthdiv
-Make the result of a division yielding a remainder have the same sign as
-the divisor. With the default, @option{-mno-knuthdiv}, the sign of the
-remainder follows the sign of the dividend. Both methods are
-arithmetically valid, the latter being almost exclusively used.
+@item -mzarch
+@itemx -mesa
+@opindex mzarch
+@opindex mesa
+When @option{-mzarch} is specified, generate code using the
+instructions available on z/Architecture.
+When @option{-mesa} is specified, generate code using the
+instructions available on ESA/390. Note that @option{-mesa} is
+not possible with @option{-m64}.
+When generating code compliant to the GNU/Linux for S/390 ABI,
+the default is @option{-mesa}. When generating code compliant
+to the GNU/Linux for zSeries ABI, the default is @option{-mzarch}.
-@item -mtoplevel-symbols
-@itemx -mno-toplevel-symbols
-@opindex mtoplevel-symbols
-@opindex mno-toplevel-symbols
-Prepend (do not prepend) a @samp{:} to all global symbols, so the assembly
-code can be used with the @code{PREFIX} assembly directive.
+@item -mmvcle
+@itemx -mno-mvcle
+@opindex mmvcle
+@opindex mno-mvcle
+Generate (or do not generate) code using the @code{mvcle} instruction
+to perform block moves. When @option{-mno-mvcle} is specified,
+use a @code{mvc} loop instead. This is the default.
-@item -melf
-@opindex melf
-Generate an executable in the ELF format, rather than the default
-@samp{mmo} format used by the @command{mmix} simulator.
+@item -mdebug
+@itemx -mno-debug
+@opindex mdebug
+@opindex mno-debug
+Print (or do not print) additional debug information when compiling.
+The default is to not print debug information.
-@item -mbranch-predict
-@itemx -mno-branch-predict
-@opindex mbranch-predict
-@opindex mno-branch-predict
-Use (do not use) the probable-branch instructions, when static branch
-prediction indicates a probable branch.
+@item -march=@var{cpu-type}
+@opindex march
+Generate code that will run on @var{cpu-type}, which is the name of a system
+representing a certain processor type. Possible values for
+@var{cpu-type} are @samp{g5}, @samp{g6}, @samp{z900}, and @samp{z990}.
+When generating code using the instructions available on z/Architecture,
+the default is @option{-march=z900}. Otherwise, the default is
+@option{-march=g5}.
-@item -mbase-addresses
-@itemx -mno-base-addresses
-@opindex mbase-addresses
-@opindex mno-base-addresses
-Generate (do not generate) code that uses @emph{base addresses}. Using a
-base address automatically generates a request (handled by the assembler
-and the linker) for a constant to be set up in a global register. The
-register is used for one or more base address requests within the range 0
-to 255 from the value held in the register. The generally leads to short
-and fast code, but the number of different data items that can be
-addressed is limited. This means that a program that uses lots of static
-data may require @option{-mno-base-addresses}.
+@item -mtune=@var{cpu-type}
+@opindex mtune
+Tune to @var{cpu-type} everything applicable about the generated code,
+except for the ABI and the set of available instructions.
+The list of @var{cpu-type} values is the same as for @option{-march}.
+The default is the value used for @option{-march}.
-@item -msingle-exit
-@itemx -mno-single-exit
-@opindex msingle-exit
-@opindex mno-single-exit
-Force (do not force) generated code to have a single exit point in each
-function.
+@item -mtpf-trace
+@itemx -mno-tpf-trace
+@opindex mtpf-trace
+@opindex mno-tpf-trace
+Generate code that adds (does not add) in TPF OS specific branches to trace
+routines in the operating system. This option is off by default, even
+when compiling for the TPF OS.
+
+@item -mfused-madd
+@itemx -mno-fused-madd
+@opindex mfused-madd
+@opindex mno-fused-madd
+Generate code that uses (does not use) the floating point multiply and
+accumulate instructions. These instructions are generated by default if
+hardware floating point is used.
@end table
-@node PDP-11 Options
-@subsection PDP-11 Options
-@cindex PDP-11 Options
+@node SH Options
+@subsection SH Options
-These options are defined for the PDP-11:
+These @samp{-m} options are defined for the SH implementations:
@table @gcctabopt
-@item -mfpu
-@opindex mfpu
-Use hardware FPP floating point. This is the default. (FIS floating
-point on the PDP-11/40 is not supported.)
+@item -m1
+@opindex m1
+Generate code for the SH1.
-@item -msoft-float
-@opindex msoft-float
-Do not use hardware floating point.
+@item -m2
+@opindex m2
+Generate code for the SH2.
-@item -mac0
-@opindex mac0
-Return floating-point results in ac0 (fr0 in Unix assembler syntax).
+@item -m2e
+Generate code for the SH2e.
-@item -mno-ac0
-@opindex mno-ac0
-Return floating-point results in memory. This is the default.
+@item -m3
+@opindex m3
+Generate code for the SH3.
+
+@item -m3e
+@opindex m3e
+Generate code for the SH3e.
+
+@item -m4-nofpu
+@opindex m4-nofpu
+Generate code for the SH4 without a floating-point unit.
-@item -m40
-@opindex m40
-Generate code for a PDP-11/40.
+@item -m4-single-only
+@opindex m4-single-only
+Generate code for the SH4 with a floating-point unit that only
+supports single-precision arithmetic.
-@item -m45
-@opindex m45
-Generate code for a PDP-11/45. This is the default.
+@item -m4-single
+@opindex m4-single
+Generate code for the SH4 assuming the floating-point unit is in
+single-precision mode by default.
-@item -m10
-@opindex m10
-Generate code for a PDP-11/10.
+@item -m4
+@opindex m4
+Generate code for the SH4.
-@item -mbcopy-builtin
-@opindex bcopy-builtin
-Use inline @code{movstrhi} patterns for copying memory. This is the
-default.
+@item -mb
+@opindex mb
+Compile code for the processor in big endian mode.
-@item -mbcopy
-@opindex mbcopy
-Do not use inline @code{movstrhi} patterns for copying memory.
+@item -ml
+@opindex ml
+Compile code for the processor in little endian mode.
-@item -mint16
-@itemx -mno-int32
-@opindex mint16
-@opindex mno-int32
-Use 16-bit @code{int}. This is the default.
+@item -mdalign
+@opindex mdalign
+Align doubles at 64-bit boundaries. Note that this changes the calling
+conventions, and thus some functions from the standard C library will
+not work unless you recompile it first with @option{-mdalign}.
-@item -mint32
-@itemx -mno-int16
-@opindex mint32
-@opindex mno-int16
-Use 32-bit @code{int}.
+@item -mrelax
+@opindex mrelax
+Shorten some address references at link time, when possible; uses the
+linker option @option{-relax}.
-@item -mfloat64
-@itemx -mno-float32
-@opindex mfloat64
-@opindex mno-float32
-Use 64-bit @code{float}. This is the default.
+@item -mbigtable
+@opindex mbigtable
+Use 32-bit offsets in @code{switch} tables. The default is to use
+16-bit offsets.
-@item -mfloat32
-@itemx -mno-float64
-@opindex mfloat32
-@opindex mno-float64
-Use 32-bit @code{float}.
+@item -mfmovd
+@opindex mfmovd
+Enable the use of the instruction @code{fmovd}.
-@item -mabshi
-@opindex mabshi
-Use @code{abshi2} pattern. This is the default.
+@item -mhitachi
+@opindex mhitachi
+Comply with the calling conventions defined by Renesas.
-@item -mno-abshi
-@opindex mno-abshi
-Do not use @code{abshi2} pattern.
+@item -mnomacsave
+@opindex mnomacsave
+Mark the @code{MAC} register as call-clobbered, even if
+@option{-mhitachi} is given.
-@item -mbranch-expensive
-@opindex mbranch-expensive
-Pretend that branches are expensive. This is for experimenting with
-code generation only.
+@item -mieee
+@opindex mieee
+Increase IEEE-compliance of floating-point code.
-@item -mbranch-cheap
-@opindex mbranch-cheap
-Do not pretend that branches are expensive. This is the default.
+@item -misize
+@opindex misize
+Dump instruction size and location in the assembly code.
-@item -msplit
-@opindex msplit
-Generate code for a system with split I&D.
+@item -mpadstruct
+@opindex mpadstruct
+This option is deprecated. It pads structures to multiple of 4 bytes,
+which is incompatible with the SH ABI@.
-@item -mno-split
-@opindex mno-split
-Generate code for a system without split I&D. This is the default.
+@item -mspace
+@opindex mspace
+Optimize for space instead of speed. Implied by @option{-Os}.
-@item -munix-asm
-@opindex munix-asm
-Use Unix assembler syntax. This is the default when configured for
-@samp{pdp11-*-bsd}.
+@item -mprefergot
+@opindex mprefergot
+When generating position-independent code, emit function calls using
+the Global Offset Table instead of the Procedure Linkage Table.
-@item -mdec-asm
-@opindex mdec-asm
-Use DEC assembler syntax. This is the default when configured for any
-PDP-11 target other than @samp{pdp11-*-bsd}.
+@item -musermode
+@opindex musermode
+Generate a library function call to invalidate instruction cache
+entries, after fixing up a trampoline. This library function call
+doesn't assume it can write to the whole memory address space. This
+is the default when the target is @code{sh-*-linux*}.
@end table
-@node Xstormy16 Options
-@subsection Xstormy16 Options
-@cindex Xstormy16 Options
+@node SPARC Options
+@subsection SPARC Options
+@cindex SPARC options
-These options are defined for Xstormy16:
+These @samp{-m} options are supported on the SPARC:
@table @gcctabopt
-@item -msim
-@opindex msim
-Choose startup files and linker script suitable for the simulator.
-@end table
+@item -mno-app-regs
+@itemx -mapp-regs
+@opindex mno-app-regs
+@opindex mapp-regs
+Specify @option{-mapp-regs} to generate output using the global registers
+2 through 4, which the SPARC SVR4 ABI reserves for applications. This
+is the default.
-@node FRV Options
-@subsection FRV Options
-@cindex FRV Options
+To be fully SVR4 ABI compliant at the cost of some performance loss,
+specify @option{-mno-app-regs}. You should compile libraries and system
+software with this option.
-@table @gcctabopt
-@item -mgpr-32
-@opindex mgpr-32
+@item -mfpu
+@itemx -mhard-float
+@opindex mfpu
+@opindex mhard-float
+Generate output containing floating point instructions. This is the
+default.
-Only use the first 32 general purpose registers.
+@item -mno-fpu
+@itemx -msoft-float
+@opindex mno-fpu
+@opindex msoft-float
+Generate output containing library calls for floating point.
+@strong{Warning:} the requisite libraries are not available for all SPARC
+targets. Normally the facilities of the machine's usual C compiler are
+used, but this cannot be done directly in cross-compilation. You must make
+your own arrangements to provide suitable library functions for
+cross-compilation. The embedded targets @samp{sparc-*-aout} and
+@samp{sparclite-*-*} do provide software floating point support.
-@item -mgpr-64
-@opindex mgpr-64
+@option{-msoft-float} changes the calling convention in the output file;
+therefore, it is only useful if you compile @emph{all} of a program with
+this option. In particular, you need to compile @file{libgcc.a}, the
+library that comes with GCC, with @option{-msoft-float} in order for
+this to work.
-Use all 64 general purpose registers.
+@item -mhard-quad-float
+@opindex mhard-quad-float
+Generate output containing quad-word (long double) floating point
+instructions.
-@item -mfpr-32
-@opindex mfpr-32
+@item -msoft-quad-float
+@opindex msoft-quad-float
+Generate output containing library calls for quad-word (long double)
+floating point instructions. The functions called are those specified
+in the SPARC ABI@. This is the default.
-Use only the first 32 floating point registers.
+As of this writing, there are no SPARC implementations that have hardware
+support for the quad-word floating point instructions. They all invoke
+a trap handler for one of these instructions, and then the trap handler
+emulates the effect of the instruction. Because of the trap handler overhead,
+this is much slower than calling the ABI library routines. Thus the
+@option{-msoft-quad-float} option is the default.
-@item -mfpr-64
-@opindex mfpr-64
+@item -mno-unaligned-doubles
+@itemx -munaligned-doubles
+@opindex mno-unaligned-doubles
+@opindex munaligned-doubles
+Assume that doubles have 8 byte alignment. This is the default.
-Use all 64 floating point registers
+With @option{-munaligned-doubles}, GCC assumes that doubles have 8 byte
+alignment only if they are contained in another type, or if they have an
+absolute address. Otherwise, it assumes they have 4 byte alignment.
+Specifying this option avoids some rare compatibility problems with code
+generated by other compilers. It is not the default because it results
+in a performance loss, especially for floating point code.
-@item -mhard-float
-@opindex mhard-float
+@item -mno-faster-structs
+@itemx -mfaster-structs
+@opindex mno-faster-structs
+@opindex mfaster-structs
+With @option{-mfaster-structs}, the compiler assumes that structures
+should have 8 byte alignment. This enables the use of pairs of
+@code{ldd} and @code{std} instructions for copies in structure
+assignment, in place of twice as many @code{ld} and @code{st} pairs.
+However, the use of this changed alignment directly violates the SPARC
+ABI@. Thus, it's intended only for use on targets where the developer
+acknowledges that their resulting code will not be directly in line with
+the rules of the ABI@.
-Use hardware instructions for floating point operations.
+@item -mimpure-text
+@opindex mimpure-text
+@option{-mimpure-text}, used in addition to @option{-shared}, tells
+the compiler to not pass @option{-z text} to the linker when linking a
+shared object. Using this option, you can link position-dependent
+code into a shared object.
-@item -msoft-float
-@opindex msoft-float
+@option{-mimpure-text} suppresses the ``relocations remain against
+allocatable but non-writable sections'' linker error message.
+However, the necessary relocations will trigger copy-on-write, and the
+shared object is not actually shared across processes. Instead of
+using @option{-mimpure-text}, you should compile all source code with
+@option{-fpic} or @option{-fPIC}.
-Use library routines for floating point operations.
+This option is only available on SunOS and Solaris.
+
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set the instruction set, register set, and instruction scheduling parameters
+for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
+@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite},
+@samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x},
+@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, and
+@samp{ultrasparc3}.
+
+Default instruction scheduling parameters are used for values that select
+an architecture and not an implementation. These are @samp{v7}, @samp{v8},
+@samp{sparclite}, @samp{sparclet}, @samp{v9}.
-@item -malloc-cc
-@opindex malloc-cc
+Here is a list of each supported architecture and their supported
+implementations.
-Dynamically allocate condition code registers.
+@smallexample
+ v7: cypress
+ v8: supersparc, hypersparc
+ sparclite: f930, f934, sparclite86x
+ sparclet: tsc701
+ v9: ultrasparc, ultrasparc3
+@end smallexample
-@item -mfixed-cc
-@opindex mfixed-cc
+By default (unless configured otherwise), GCC generates code for the V7
+variant of the SPARC architecture. With @option{-mcpu=cypress}, the compiler
+additionally optimizes it for the Cypress CY7C602 chip, as used in the
+SPARCStation/SPARCServer 3xx series. This is also appropriate for the older
+SPARCStation 1, 2, IPX etc.
-Do not try to dynamically allocate condition code registers, only
-use @code{icc0} and @code{fcc0}.
+With @option{-mcpu=v8}, GCC generates code for the V8 variant of the SPARC
+architecture. The only difference from V7 code is that the compiler emits
+the integer multiply and integer divide instructions which exist in SPARC-V8
+but not in SPARC-V7. With @option{-mcpu=supersparc}, the compiler additionally
+optimizes it for the SuperSPARC chip, as used in the SPARCStation 10, 1000 and
+2000 series.
-@item -mdword
-@opindex mdword
+With @option{-mcpu=sparclite}, GCC generates code for the SPARClite variant of
+the SPARC architecture. This adds the integer multiply, integer divide step
+and scan (@code{ffs}) instructions which exist in SPARClite but not in SPARC-V7.
+With @option{-mcpu=f930}, the compiler additionally optimizes it for the
+Fujitsu MB86930 chip, which is the original SPARClite, with no FPU. With
+@option{-mcpu=f934}, the compiler additionally optimizes it for the Fujitsu
+MB86934 chip, which is the more recent SPARClite with FPU.
-Change ABI to use double word insns.
+With @option{-mcpu=sparclet}, GCC generates code for the SPARClet variant of
+the SPARC architecture. This adds the integer multiply, multiply/accumulate,
+integer divide step and scan (@code{ffs}) instructions which exist in SPARClet
+but not in SPARC-V7. With @option{-mcpu=tsc701}, the compiler additionally
+optimizes it for the TEMIC SPARClet chip.
-@item -mno-dword
-@opindex mno-dword
+With @option{-mcpu=v9}, GCC generates code for the V9 variant of the SPARC
+architecture. This adds 64-bit integer and floating-point move instructions,
+3 additional floating-point condition code registers and conditional move
+instructions. With @option{-mcpu=ultrasparc}, the compiler additionally
+optimizes it for the Sun UltraSPARC I/II chips. With
+@option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
+Sun UltraSPARC III chip.
-Do not use double word instructions.
+@item -mtune=@var{cpu_type}
+@opindex mtune
+Set the instruction scheduling parameters for machine type
+@var{cpu_type}, but do not set the instruction set or register set that the
+option @option{-mcpu=@var{cpu_type}} would.
-@item -mdouble
-@opindex mdouble
+The same values for @option{-mcpu=@var{cpu_type}} can be used for
+@option{-mtune=@var{cpu_type}}, but the only useful values are those
+that select a particular cpu implementation. Those are @samp{cypress},
+@samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934},
+@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, and
+@samp{ultrasparc3}.
-Use floating point double instructions.
+@item -mv8plus
+@itemx -mno-v8plus
+@opindex mv8plus
+@opindex mno-v8plus
+With @option{-mv8plus}, GCC generates code for the SPARC-V8+ ABI. The
+difference from the V8 ABI is that the global and out registers are
+considered 64-bit wide. This is enabled by default on Solaris in 32-bit
+mode for all SPARC-V9 processors.
-@item -mno-double
-@opindex mno-double
+@item -mvis
+@itemx -mno-vis
+@opindex mvis
+@opindex mno-vis
+With @option{-mvis}, GCC generates code that takes advantage of the UltraSPARC
+Visual Instruction Set extensions. The default is @option{-mno-vis}.
+@end table
-Do not use floating point double instructions.
+These @samp{-m} options are supported in addition to the above
+on SPARC-V9 processors in 64-bit environments:
-@item -mmedia
-@opindex mmedia
+@table @gcctabopt
+@item -mlittle-endian
+@opindex mlittle-endian
+Generate code for a processor running in little-endian mode. It is only
+available for a few configurations and most notably not on Solaris.
-Use media instructions.
+@item -m32
+@itemx -m64
+@opindex m32
+@opindex m64
+Generate code for a 32-bit or 64-bit environment.
+The 32-bit environment sets int, long and pointer to 32 bits.
+The 64-bit environment sets int to 32 bits and long and pointer
+to 64 bits.
-@item -mno-media
-@opindex mno-media
+@item -mcmodel=medlow
+@opindex mcmodel=medlow
+Generate code for the Medium/Low code model: 64-bit addresses, programs
+must be linked in the low 32 bits of memory. Programs can be statically
+or dynamically linked.
-Do not use media instructions.
+@item -mcmodel=medmid
+@opindex mcmodel=medmid
+Generate code for the Medium/Middle code model: 64-bit addresses, programs
+must be linked in the low 44 bits of memory, the text and data segments must
+be less than 2GB in size and the data segment must be located within 2GB of
+the text segment.
-@item -mmuladd
-@opindex mmuladd
+@item -mcmodel=medany
+@opindex mcmodel=medany
+Generate code for the Medium/Anywhere code model: 64-bit addresses, programs
+may be linked anywhere in memory, the text and data segments must be less
+than 2GB in size and the data segment must be located within 2GB of the
+text segment.
-Use multiply and add/subtract instructions.
+@item -mcmodel=embmedany
+@opindex mcmodel=embmedany
+Generate code for the Medium/Anywhere code model for embedded systems:
+64-bit addresses, the text and data segments must be less than 2GB in
+size, both starting anywhere in memory (determined at link time). The
+global register %g4 points to the base of the data segment. Programs
+are statically linked and PIC is not supported.
-@item -mno-muladd
-@opindex mno-muladd
+@item -mstack-bias
+@itemx -mno-stack-bias
+@opindex mstack-bias
+@opindex mno-stack-bias
+With @option{-mstack-bias}, GCC assumes that the stack pointer, and
+frame pointer if present, are offset by @minus{}2047 which must be added back
+when making stack frame references. This is the default in 64-bit mode.
+Otherwise, assume no such offset is present.
+@end table
-Do not use multiply and add/subtract instructions.
+@node System V Options
+@subsection Options for System V
-@item -mlibrary-pic
-@opindex mlibrary-pic
+These additional options are available on System V Release 4 for
+compatibility with other compilers on those systems:
-Generate position-independent EABI code.
+@table @gcctabopt
+@item -G
+@opindex G
+Create a shared object.
+It is recommended that @option{-symbolic} or @option{-shared} be used instead.
-@item -macc-4
-@opindex macc-4
+@item -Qy
+@opindex Qy
+Identify the versions of each tool used by the compiler, in a
+@code{.ident} assembler directive in the output.
-Use only the first four media accumulator registers.
+@item -Qn
+@opindex Qn
+Refrain from adding @code{.ident} directives to the output file (this is
+the default).
-@item -macc-8
-@opindex macc-8
+@item -YP,@var{dirs}
+@opindex YP
+Search the directories @var{dirs}, and no others, for libraries
+specified with @option{-l}.
-Use all eight media accumulator registers.
+@item -Ym,@var{dir}
+@opindex Ym
+Look in the directory @var{dir} to find the M4 preprocessor.
+The assembler uses this option.
+@c This is supposed to go with a -Yd for predefined M4 macro files, but
+@c the generic assembler that comes with Solaris takes just -Ym.
+@end table
-@item -mpack
-@opindex mpack
+@node TMS320C3x/C4x Options
+@subsection TMS320C3x/C4x Options
+@cindex TMS320C3x/C4x Options
-Pack VLIW instructions.
+These @samp{-m} options are defined for TMS320C3x/C4x implementations:
-@item -mno-pack
-@opindex mno-pack
+@table @gcctabopt
-Do not pack VLIW instructions.
+@item -mcpu=@var{cpu_type}
+@opindex mcpu
+Set the instruction set, register set, and instruction scheduling
+parameters for machine type @var{cpu_type}. Supported values for
+@var{cpu_type} are @samp{c30}, @samp{c31}, @samp{c32}, @samp{c40}, and
+@samp{c44}. The default is @samp{c40} to generate code for the
+TMS320C40.
-@item -mno-eflags
-@opindex mno-eflags
+@item -mbig-memory
+@itemx -mbig
+@itemx -msmall-memory
+@itemx -msmall
+@opindex mbig-memory
+@opindex mbig
+@opindex msmall-memory
+@opindex msmall
+Generates code for the big or small memory model. The small memory
+model assumed that all data fits into one 64K word page. At run-time
+the data page (DP) register must be set to point to the 64K page
+containing the .bss and .data program sections. The big memory model is
+the default and requires reloading of the DP register for every direct
+memory access.
-Do not mark ABI switches in e_flags.
+@item -mbk
+@itemx -mno-bk
+@opindex mbk
+@opindex mno-bk
+Allow (disallow) allocation of general integer operands into the block
+count register BK@.
-@item -mcond-move
-@opindex mcond-move
+@item -mdb
+@itemx -mno-db
+@opindex mdb
+@opindex mno-db
+Enable (disable) generation of code using decrement and branch,
+DBcond(D), instructions. This is enabled by default for the C4x. To be
+on the safe side, this is disabled for the C3x, since the maximum
+iteration count on the C3x is @math{2^{23} + 1} (but who iterates loops more than
+@math{2^{23}} times on the C3x?). Note that GCC will try to reverse a loop so
+that it can utilize the decrement and branch instruction, but will give
+up if there is more than one memory reference in the loop. Thus a loop
+where the loop counter is decremented can generate slightly more
+efficient code, in cases where the RPTB instruction cannot be utilized.
-Enable the use of conditional-move instructions (default).
+@item -mdp-isr-reload
+@itemx -mparanoid
+@opindex mdp-isr-reload
+@opindex mparanoid
+Force the DP register to be saved on entry to an interrupt service
+routine (ISR), reloaded to point to the data section, and restored on
+exit from the ISR@. This should not be required unless someone has
+violated the small memory model by modifying the DP register, say within
+an object library.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mmpyi
+@itemx -mno-mpyi
+@opindex mmpyi
+@opindex mno-mpyi
+For the C3x use the 24-bit MPYI instruction for integer multiplies
+instead of a library call to guarantee 32-bit results. Note that if one
+of the operands is a constant, then the multiplication will be performed
+using shifts and adds. If the @option{-mmpyi} option is not specified for the C3x,
+then squaring operations are performed inline instead of a library call.
-@item -mno-cond-move
-@opindex mno-cond-move
+@item -mfast-fix
+@itemx -mno-fast-fix
+@opindex mfast-fix
+@opindex mno-fast-fix
+The C3x/C4x FIX instruction to convert a floating point value to an
+integer value chooses the nearest integer less than or equal to the
+floating point value rather than to the nearest integer. Thus if the
+floating point number is negative, the result will be incorrectly
+truncated an additional code is necessary to detect and correct this
+case. This option can be used to disable generation of the additional
+code required to correct the result.
-Disable the use of conditional-move instructions.
+@item -mrptb
+@itemx -mno-rptb
+@opindex mrptb
+@opindex mno-rptb
+Enable (disable) generation of repeat block sequences using the RPTB
+instruction for zero overhead looping. The RPTB construct is only used
+for innermost loops that do not call functions or jump across the loop
+boundaries. There is no advantage having nested RPTB loops due to the
+overhead required to save and restore the RC, RS, and RE registers.
+This is enabled by default with @option{-O2}.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mrpts=@var{count}
+@itemx -mno-rpts
+@opindex mrpts
+@opindex mno-rpts
+Enable (disable) the use of the single instruction repeat instruction
+RPTS@. If a repeat block contains a single instruction, and the loop
+count can be guaranteed to be less than the value @var{count}, GCC will
+emit a RPTS instruction instead of a RPTB@. If no value is specified,
+then a RPTS will be emitted even if the loop count cannot be determined
+at compile time. Note that the repeated instruction following RPTS does
+not have to be reloaded from memory each iteration, thus freeing up the
+CPU buses for operands. However, since interrupts are blocked by this
+instruction, it is disabled by default.
-@item -mscc
-@opindex mscc
+@item -mloop-unsigned
+@itemx -mno-loop-unsigned
+@opindex mloop-unsigned
+@opindex mno-loop-unsigned
+The maximum iteration count when using RPTS and RPTB (and DB on the C40)
+is @math{2^{31} + 1} since these instructions test if the iteration count is
+negative to terminate the loop. If the iteration count is unsigned
+there is a possibility than the @math{2^{31} + 1} maximum iteration count may be
+exceeded. This switch allows an unsigned iteration count.
-Enable the use of conditional set instructions (default).
+@item -mti
+@opindex mti
+Try to emit an assembler syntax that the TI assembler (asm30) is happy
+with. This also enforces compatibility with the API employed by the TI
+C3x C compiler. For example, long doubles are passed as structures
+rather than in floating point registers.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mregparm
+@itemx -mmemparm
+@opindex mregparm
+@opindex mmemparm
+Generate code that uses registers (stack) for passing arguments to functions.
+By default, arguments are passed in registers where possible rather
+than by pushing arguments on to the stack.
-@item -mno-scc
-@opindex mno-scc
+@item -mparallel-insns
+@itemx -mno-parallel-insns
+@opindex mparallel-insns
+@opindex mno-parallel-insns
+Allow the generation of parallel instructions. This is enabled by
+default with @option{-O2}.
-Disable the use of conditional set instructions.
+@item -mparallel-mpy
+@itemx -mno-parallel-mpy
+@opindex mparallel-mpy
+@opindex mno-parallel-mpy
+Allow the generation of MPY||ADD and MPY||SUB parallel instructions,
+provided @option{-mparallel-insns} is also specified. These instructions have
+tight register constraints which can pessimize the code generation
+of large functions.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@end table
-@item -mcond-exec
-@opindex mcond-exec
+@node V850 Options
+@subsection V850 Options
+@cindex V850 Options
-Enable the use of conditional execution (default).
+These @samp{-m} options are defined for V850 implementations:
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@table @gcctabopt
+@item -mlong-calls
+@itemx -mno-long-calls
+@opindex mlong-calls
+@opindex mno-long-calls
+Treat all calls as being far away (near). If calls are assumed to be
+far away, the compiler will always load the functions address up into a
+register, and call indirect through the pointer.
-@item -mno-cond-exec
-@opindex mno-cond-exec
+@item -mno-ep
+@itemx -mep
+@opindex mno-ep
+@opindex mep
+Do not optimize (do optimize) basic blocks that use the same index
+pointer 4 or more times to copy pointer into the @code{ep} register, and
+use the shorter @code{sld} and @code{sst} instructions. The @option{-mep}
+option is on by default if you optimize.
-Disable the use of conditional execution.
+@item -mno-prolog-function
+@itemx -mprolog-function
+@opindex mno-prolog-function
+@opindex mprolog-function
+Do not use (do use) external functions to save and restore registers
+at the prologue and epilogue of a function. The external functions
+are slower, but use less code space if more than one function saves
+the same number of registers. The @option{-mprolog-function} option
+is on by default if you optimize.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mspace
+@opindex mspace
+Try to make the code as small as possible. At present, this just turns
+on the @option{-mep} and @option{-mprolog-function} options.
-@item -mvliw-branch
-@opindex mvliw-branch
+@item -mtda=@var{n}
+@opindex mtda
+Put static or global variables whose size is @var{n} bytes or less into
+the tiny data area that register @code{ep} points to. The tiny data
+area can hold up to 256 bytes in total (128 bytes for byte references).
-Run a pass to pack branches into VLIW instructions (default).
+@item -msda=@var{n}
+@opindex msda
+Put static or global variables whose size is @var{n} bytes or less into
+the small data area that register @code{gp} points to. The small data
+area can hold up to 64 kilobytes.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mzda=@var{n}
+@opindex mzda
+Put static or global variables whose size is @var{n} bytes or less into
+the first 32 kilobytes of memory.
-@item -mno-vliw-branch
-@opindex mno-vliw-branch
+@item -mv850
+@opindex mv850
+Specify that the target processor is the V850.
-Do not run a pass to pack branches into VLIW instructions.
+@item -mbig-switch
+@opindex mbig-switch
+Generate code suitable for big switch tables. Use this option only if
+the assembler/linker complain about out of range branches within a switch
+table.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mapp-regs
+@opindex mapp-regs
+This option will cause r2 and r5 to be used in the code generated by
+the compiler. This setting is the default.
-@item -mmulti-cond-exec
-@opindex mmulti-cond-exec
+@item -mno-app-regs
+@opindex mno-app-regs
+This option will cause r2 and r5 to be treated as fixed registers.
-Enable optimization of @code{&&} and @code{||} in conditional execution
-(default).
+@item -mv850e1
+@opindex mv850e1
+Specify that the target processor is the V850E1. The preprocessor
+constants @samp{__v850e1__} and @samp{__v850e__} will be defined if
+this option is used.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mv850e
+@opindex mv850e
+Specify that the target processor is the V850E. The preprocessor
+constant @samp{__v850e__} will be defined if this option is used.
-@item -mno-multi-cond-exec
-@opindex mno-multi-cond-exec
+If neither @option{-mv850} nor @option{-mv850e} nor @option{-mv850e1}
+are defined then a default target processor will be chosen and the
+relevant @samp{__v850*__} preprocessor constant will be defined.
-Disable optimization of @code{&&} and @code{||} in conditional execution.
+The preprocessor constants @samp{__v850} and @samp{__v851__} are always
+defined, regardless of which processor variant is the target.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mdisable-callt
+@opindex mdisable-callt
+This option will suppress generation of the CALLT instruction for the
+v850e and v850e1 flavors of the v850 architecture. The default is
+@option{-mno-disable-callt} which allows the CALLT instruction to be used.
-@item -mnested-cond-exec
-@opindex mnested-cond-exec
+@end table
-Enable nested conditional execution optimizations (default).
+@node VAX Options
+@subsection VAX Options
+@cindex VAX options
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+These @samp{-m} options are defined for the VAX:
-@item -mno-nested-cond-exec
-@opindex mno-nested-cond-exec
+@table @gcctabopt
+@item -munix
+@opindex munix
+Do not output certain jump instructions (@code{aobleq} and so on)
+that the Unix assembler for the VAX cannot handle across long
+ranges.
-Disable nested conditional execution optimizations.
+@item -mgnu
+@opindex mgnu
+Do output those jump instructions, on the assumption that you
+will assemble with the GNU assembler.
-This switch is mainly for debugging the compiler and will likely be removed
-in a future version.
+@item -mg
+@opindex mg
+Output code for g-format floating point numbers instead of d-format.
+@end table
-@item -mtomcat-stats
-@opindex mtomcat-stats
+@node x86-64 Options
+@subsection x86-64 Options
+@cindex x86-64 options
-Cause gas to print out tomcat statistics.
+These are listed under @xref{i386 and x86-64 Options}.
-@item -mcpu=@var{cpu}
-@opindex mcpu
+@node Xstormy16 Options
+@subsection Xstormy16 Options
+@cindex Xstormy16 Options
-Select the processor type for which to generate code. Possible values are
-@samp{simple}, @samp{tomcat}, @samp{fr500}, @samp{fr400}, @samp{fr300},
-@samp{frv}.
+These options are defined for Xstormy16:
+@table @gcctabopt
+@item -msim
+@opindex msim
+Choose startup files and linker script suitable for the simulator.
@end table
@node Xtensa Options
every cross-file call, not just those that really will be out of range.
@end table
+@node zSeries Options
+@subsection zSeries Options
+@cindex zSeries options
+
+These are listed under @xref{S/390 and zSeries Options}.
+
@node Code Gen Options
@section Options for Code Generation Conventions
@cindex code generation conventions
`precompile' a header file; then, if builds can use the precompiled
header file they will be much faster.
+@strong{Caution:} There are a few known situations where GCC will
+crash when trying to use a precompiled header. If you have trouble
+with a precompiled header, you should remove the precompiled header
+and compile without it. In addition, please use GCC's on-line
+defect-tracking system to report any problems you encounter with
+precompiled headers. @xref{Bugs}.
+
To create a precompiled header file, simply compile it as you would any
other file, if necessary using the @option{-x} option to make the driver
treat it as a C or C++ header file. You will probably want to use a
If you need to precompile the same header file for different
languages, targets, or compiler options, you can instead make a
@emph{directory} named like @file{all.h.gch}, and put each precompiled
-header in the directory. (It doesn't matter what you call the files
-in the directory, every precompiled header in the directory will be
-considered.) The first precompiled header encountered in the
-directory that is valid for this compilation will be used; they're
-searched in no particular order.
+header in the directory, perhaps using @option{-o}. It doesn't matter
+what you call the files in the directory, every precompiled header in
+the directory will be considered. The first precompiled header
+encountered in the directory that is valid for this compilation will
+be used; they're searched in no particular order.
There are many other possibilities, limited only by your imagination,
good sense, and the constraints of your build system.
@itemize
@item
Only one precompiled header can be used in a particular compilation.
+
@item
A precompiled header can't be used once the first C token is seen. You
can have preprocessor directives before a precompiled header; you can
even include a precompiled header from inside another header, so long as
there are no C tokens before the @code{#include}.
+
@item
The precompiled header file must be produced for the same language as
the current compilation. You can't use a C precompiled header for a C++
compilation.
+
@item
The precompiled header file must be produced by the same compiler
version and configuration as the current compilation is using.
The easiest way to guarantee this is to use the same compiler binary
for creating and using precompiled headers.
+
@item
-Any macros defined before the precompiled header (including with
-@option{-D}) must either be defined in the same way as when the
-precompiled header was generated, or must not affect the precompiled
-header, which usually means that the they don't appear in the
-precompiled header at all.
+Any macros defined before the precompiled header is included must
+either be defined in the same way as when the precompiled header was
+generated, or must not affect the precompiled header, which usually
+means that the they don't appear in the precompiled header at all.
+
+The @option{-D} option is one way to define a macro before a
+precompiled header is included; using a @code{#define} can also do it.
+There are also some options that define macros implicitly, like
+@option{-O} and @option{-Wdeprecated}; the same rule applies to macros
+defined this way.
+
+@item If debugging information is output when using the precompiled
+header, using @option{-g} or similar, the same kind of debugging information
+must have been output when building the precompiled header. However,
+a precompiled header built using @option{-g} can be used in a compilation
+when no debugging information is being output.
+
+@item The same @option{-m} options must generally be used when building
+and using the precompiled header. @xref{Submodel Options},
+for any cases where this rule is relaxed.
+
+@item Each of the following options must be the same when building and using
+the precompiled header:
+
+@gccoptlist{-fexceptions -funit-at-a-time}
+
@item
-Certain command-line options must be defined in the same way as when the
-precompiled header was generated. At present, it's not clear which
-options are safe to change and which are not; the safest choice is to
-use exactly the same options when generating and using the precompiled
-header.
+Some other command-line options starting with @option{-f},
+@option{-p}, or @option{-O} must be defined in the same way as when
+the precompiled header was generated. At present, it's not clear
+which options are safe to change and which are not; the safest choice
+is to use exactly the same options when generating and using the
+precompiled header. The following are known to be safe:
+
+@gccoptlist{-fpreprocessed -pedantic-errors}
+
@end itemize
-For all of these but the last, the compiler will automatically ignore
-the precompiled header if the conditions aren't met. For the last item,
-some option changes will cause the precompiled header to be rejected,
-but not all incompatible option combinations have yet been found. If
-you find a new incompatible combination, please consider filing a bug
-report, see @ref{Bugs}.
+For all of these except the last, the compiler will automatically
+ignore the precompiled header if the conditions aren't met. If you
+find an option combination that doesn't work and doesn't cause the
+precompiled header to be ignored, please consider filing a bug report,
+see @ref{Bugs}.
+
+If you do use differing options when generating and using the
+precompiled header, the actual behaviour will be a mixture of the
+behaviour for the options. For instance, if you use @option{-g} to
+generate the precompiled header but not when using it, you may or may
+not get debugging information for routines in the precompiled header.
@node Running Protoize
@section Running Protoize
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