-@item -m32
-@itemx -m64
-@opindex m32
-@opindex m64
-Generate code for a 32-bit or 64-bit environment.
-The 32-bit environment sets int, long and pointer to 32 bits.
-The 64-bit environment sets int to 32 bits and long and pointer
-to 64 bits.
-
-@item -mcmodel=medlow
-@opindex mcmodel=medlow
-Generate code for the Medium/Low code model: 64-bit addresses, programs
-must be linked in the low 32 bits of memory. Programs can be statically
-or dynamically linked.
-
-@item -mcmodel=medmid
-@opindex mcmodel=medmid
-Generate code for the Medium/Middle code model: 64-bit addresses, programs
-must be linked in the low 44 bits of memory, the text and data segments must
-be less than 2GB in size and the data segment must be located within 2GB of
-the text segment.
-
-@item -mcmodel=medany
-@opindex mcmodel=medany
-Generate code for the Medium/Anywhere code model: 64-bit addresses, programs
-may be linked anywhere in memory, the text and data segments must be less
-than 2GB in size and the data segment must be located within 2GB of the
-text segment.
-
-@item -mcmodel=embmedany
-@opindex mcmodel=embmedany
-Generate code for the Medium/Anywhere code model for embedded systems:
-64-bit addresses, the text and data segments must be less than 2GB in
-size, both starting anywhere in memory (determined at link time). The
-global register %g4 points to the base of the data segment. Programs
-are statically linked and PIC is not supported.
-
-@item -mstack-bias
-@itemx -mno-stack-bias
-@opindex mstack-bias
-@opindex mno-stack-bias
-With @option{-mstack-bias}, GCC assumes that the stack pointer, and
-frame pointer if present, are offset by @minus{}2047 which must be added back
-when making stack frame references. This is the default in 64-bit mode.
-Otherwise, assume no such offset is present.
-@end table
-
-@node ARM Options
-@subsection ARM Options
-@cindex ARM options
-
-These @samp{-m} options are defined for Advanced RISC Machines (ARM)
-architectures:
-
-@table @gcctabopt
-@item -mabi=@var{name}
-@opindex mabi
-Generate code for the specified ABI. Permissible values are: @samp{apcs-gnu},
-@samp{atpcs}, @samp{aapcs} and @samp{iwmmxt}.
-
-@item -mapcs-frame
-@opindex mapcs-frame
-Generate a stack frame that is compliant with the ARM Procedure Call
-Standard for all functions, even if this is not strictly necessary for
-correct execution of the code. Specifying @option{-fomit-frame-pointer}
-with this option will cause the stack frames not to be generated for
-leaf functions. The default is @option{-mno-apcs-frame}.
-
-@item -mapcs
-@opindex mapcs
-This is a synonym for @option{-mapcs-frame}.
-
-@item -mapcs-26
-@opindex mapcs-26
-Generate code for a processor running with a 26-bit program counter,
-and conforming to the function calling standards for the APCS 26-bit
-option. This option replaces the @option{-m2} and @option{-m3} options
-of previous releases of the compiler.
-
-@item -mapcs-32
-@opindex mapcs-32
-Generate code for a processor running with a 32-bit program counter,
-and conforming to the function calling standards for the APCS 32-bit
-option. This option replaces the @option{-m6} option of previous releases
-of the compiler.
-
-@ignore
-@c not currently implemented
-@item -mapcs-stack-check
-@opindex mapcs-stack-check
-Generate code to check the amount of stack space available upon entry to
-every function (that actually uses some stack space). If there is
-insufficient space available then either the function
-@samp{__rt_stkovf_split_small} or @samp{__rt_stkovf_split_big} will be
-called, depending upon the amount of stack space required. The run time
-system is required to provide these functions. The default is
-@option{-mno-apcs-stack-check}, since this produces smaller code.
-
-@c not currently implemented
-@item -mapcs-float
-@opindex mapcs-float
-Pass floating point arguments using the float point registers. This is
-one of the variants of the APCS@. This option is recommended if the
-target hardware has a floating point unit or if a lot of floating point
-arithmetic is going to be performed by the code. The default is
-@option{-mno-apcs-float}, since integer only code is slightly increased in
-size if @option{-mapcs-float} is used.
-
-@c not currently implemented
-@item -mapcs-reentrant
-@opindex mapcs-reentrant
-Generate reentrant, position independent code. The default is
-@option{-mno-apcs-reentrant}.
-@end ignore
-
-@item -mthumb-interwork
-@opindex mthumb-interwork
-Generate code which supports calling between the ARM and Thumb
-instruction sets. Without this option the two instruction sets cannot
-be reliably used inside one program. The default is
-@option{-mno-thumb-interwork}, since slightly larger code is generated
-when @option{-mthumb-interwork} is specified.
-
-@item -mno-sched-prolog
-@opindex mno-sched-prolog
-Prevent the reordering of instructions in the function prolog, or the
-merging of those instruction with the instructions in the function's
-body. This means that all functions will start with a recognizable set
-of instructions (or in fact one of a choice from a small set of
-different function prologues), and this information can be used to
-locate the start if functions inside an executable piece of code. The
-default is @option{-msched-prolog}.
-
-@item -mhard-float
-@opindex mhard-float
-Generate output containing floating point instructions. This is the
-default.
-
-@item -msoft-float
-@opindex msoft-float
-Generate output containing library calls for floating point.
-@strong{Warning:} the requisite libraries are not available for all ARM
-targets. Normally the facilities of the machine's usual C compiler are
-used, but this cannot be done directly in cross-compilation. You must make
-your own arrangements to provide suitable library functions for
-cross-compilation.
-
-@option{-msoft-float} changes the calling convention in the output file;
-therefore, it is only useful if you compile @emph{all} of a program with
-this option. In particular, you need to compile @file{libgcc.a}, the
-library that comes with GCC, with @option{-msoft-float} in order for
-this to work.
-
-@item -mfloat-abi=@var{name}
-@opindex mfloat-abi
-Specifies which ABI to use for floating point values. Permissible values
-are: @samp{soft}, @samp{softfp} and @samp{hard}.
-
-@samp{soft} and @samp{hard} are equivalent to @option{-msoft-float}
-and @option{-mhard-float} respectively. @samp{softfp} allows the generation
-of floating point instructions, but still uses the soft-float calling
-conventions.
-
-@item -mlittle-endian
-@opindex mlittle-endian
-Generate code for a processor running in little-endian mode. This is
-the default for all standard configurations.
-
-@item -mbig-endian
-@opindex mbig-endian
-Generate code for a processor running in big-endian mode; the default is
-to compile code for a little-endian processor.
-
-@item -mwords-little-endian
-@opindex mwords-little-endian
-This option only applies when generating code for big-endian processors.
-Generate code for a little-endian word order but a big-endian byte
-order. That is, a byte order of the form @samp{32107654}. Note: this
-option should only be used if you require compatibility with code for
-big-endian ARM processors generated by versions of the compiler prior to
-2.8.
-
-@item -malignment-traps
-@opindex malignment-traps
-Generate code that will not trap if the MMU has alignment traps enabled.
-On ARM architectures prior to ARMv4, there were no instructions to
-access half-word objects stored in memory. However, when reading from
-memory a feature of the ARM architecture allows a word load to be used,
-even if the address is unaligned, and the processor core will rotate the
-data as it is being loaded. This option tells the compiler that such
-misaligned accesses will cause a MMU trap and that it should instead
-synthesize the access as a series of byte accesses. The compiler can
-still use word accesses to load half-word data if it knows that the
-address is aligned to a word boundary.
-
-This option is ignored when compiling for ARM architecture 4 or later,
-since these processors have instructions to directly access half-word
-objects in memory.
-
-@item -mno-alignment-traps
-@opindex mno-alignment-traps
-Generate code that assumes that the MMU will not trap unaligned
-accesses. This produces better code when the target instruction set
-does not have half-word memory operations (i.e.@: implementations prior to
-ARMv4).
-
-Note that you cannot use this option to access unaligned word objects,
-since the processor will only fetch one 32-bit aligned object from
-memory.
-
-The default setting for most targets is @option{-mno-alignment-traps}, since
-this produces better code when there are no half-word memory
-instructions available.
-
-@item -mshort-load-bytes
-@itemx -mno-short-load-words
-@opindex mshort-load-bytes
-@opindex mno-short-load-words
-These are deprecated aliases for @option{-malignment-traps}.
-
-@item -mno-short-load-bytes
-@itemx -mshort-load-words
-@opindex mno-short-load-bytes
-@opindex mshort-load-words
-This are deprecated aliases for @option{-mno-alignment-traps}.
-
-@item -mcpu=@var{name}
-@opindex mcpu
-This specifies the name of the target ARM processor. GCC uses this name
-to determine what kind of instructions it can emit when generating
-assembly code. Permissible names are: @samp{arm2}, @samp{arm250},
-@samp{arm3}, @samp{arm6}, @samp{arm60}, @samp{arm600}, @samp{arm610},
-@samp{arm620}, @samp{arm7}, @samp{arm7m}, @samp{arm7d}, @samp{arm7dm},
-@samp{arm7di}, @samp{arm7dmi}, @samp{arm70}, @samp{arm700},
-@samp{arm700i}, @samp{arm710}, @samp{arm710c}, @samp{arm7100},
-@samp{arm7500}, @samp{arm7500fe}, @samp{arm7tdmi}, @samp{arm8},
-@samp{strongarm}, @samp{strongarm110}, @samp{strongarm1100},
-@samp{arm8}, @samp{arm810}, @samp{arm9}, @samp{arm9e}, @samp{arm920},
-@samp{arm920t}, @samp{arm926ejs}, @samp{arm940t}, @samp{arm9tdmi},
-@samp{arm10tdmi}, @samp{arm1020t}, @samp{arm1026ejs},
-@samp{arm1136js}, @samp{arm1136jfs} ,@samp{xscale}, @samp{iwmmxt},
-@samp{ep9312}.
-
-@itemx -mtune=@var{name}
-@opindex mtune
-This option is very similar to the @option{-mcpu=} option, except that
-instead of specifying the actual target processor type, and hence
-restricting which instructions can be used, it specifies that GCC should
-tune the performance of the code as if the target were of the type
-specified in this option, but still choosing the instructions that it
-will generate based on the cpu specified by a @option{-mcpu=} option.
-For some ARM implementations better performance can be obtained by using
-this option.
-
-@item -march=@var{name}
-@opindex march
-This specifies the name of the target ARM architecture. GCC uses this
-name to determine what kind of instructions it can emit when generating
-assembly code. This option can be used in conjunction with or instead
-of the @option{-mcpu=} option. Permissible names are: @samp{armv2},
-@samp{armv2a}, @samp{armv3}, @samp{armv3m}, @samp{armv4}, @samp{armv4t},
-@samp{armv5}, @samp{armv5t}, @samp{armv5te}, @samp{armv6}, @samp{armv6j},
-@samp{iwmmxt}, @samp{ep9312}.
-
-@item -mfpu=@var{name}
-@itemx -mfpe=@var{number}
-@itemx -mfp=@var{number}
-@opindex mfpu
-@opindex mfpe
-@opindex mfp
-This specifies what floating point hardware (or hardware emulation) is
-available on the target. Permissible names are: @samp{fpa}, @samp{fpe2},
-@samp{fpe3}, @samp{maverick}, @samp{vfp}. @option{-mfp} and @option{-mfpe}
-are synonyms for @option{-mfpu}=@samp{fpe}@var{number}, for compatibility
-with older versions of GCC@.
-
-If @option{-msoft-float} is specified this specifies the format of
-floating point values.
-
-@item -mstructure-size-boundary=@var{n}
-@opindex mstructure-size-boundary
-The size of all structures and unions will be rounded up to a multiple
-of the number of bits set by this option. Permissible values are 8, 32
-and 64. The default value varies for different toolchains. For the COFF
-targeted toolchain the default value is 8. A value of 64 is only allowed
-if the underlying ABI supports it.
-
-Specifying the larger number can produce faster, more efficient code, but
-can also increase the size of the program. Different values are potentially
-incompatible. Code compiled with one value cannot necessarily expect to
-work with code or libraries compiled with annother value, if they exchange
-information using structures or unions.
-
-@item -mabort-on-noreturn
-@opindex mabort-on-noreturn
-Generate a call to the function @code{abort} at the end of a
-@code{noreturn} function. It will be executed if the function tries to
-return.
-
-@item -mlong-calls
-@itemx -mno-long-calls
-@opindex mlong-calls
-@opindex mno-long-calls
-Tells the compiler to perform function calls by first loading the
-address of the function into a register and then performing a subroutine
-call on this register. This switch is needed if the target function
-will lie outside of the 64 megabyte addressing range of the offset based
-version of subroutine call instruction.
-
-Even if this switch is enabled, not all function calls will be turned
-into long calls. The heuristic is that static functions, functions
-which have the @samp{short-call} attribute, functions that are inside
-the scope of a @samp{#pragma no_long_calls} directive and functions whose
-definitions have already been compiled within the current compilation
-unit, will not be turned into long calls. The exception to this rule is
-that weak function definitions, functions with the @samp{long-call}
-attribute or the @samp{section} attribute, and functions that are within
-the scope of a @samp{#pragma long_calls} directive, will always be
-turned into long calls.
-
-This feature is not enabled by default. Specifying
-@option{-mno-long-calls} will restore the default behavior, as will
-placing the function calls within the scope of a @samp{#pragma
-long_calls_off} directive. Note these switches have no effect on how
-the compiler generates code to handle function calls via function
-pointers.
-
-@item -mnop-fun-dllimport
-@opindex mnop-fun-dllimport
-Disable support for the @code{dllimport} attribute.
-
-@item -msingle-pic-base
-@opindex msingle-pic-base
-Treat the register used for PIC addressing as read-only, rather than
-loading it in the prologue for each function. The run-time system is
-responsible for initializing this register with an appropriate value
-before execution begins.
-
-@item -mpic-register=@var{reg}
-@opindex mpic-register
-Specify the register to be used for PIC addressing. The default is R10
-unless stack-checking is enabled, when R9 is used.
-
-@item -mcirrus-fix-invalid-insns
-@opindex mcirrus-fix-invalid-insns
-@opindex mno-cirrus-fix-invalid-insns
-Insert NOPs into the instruction stream to in order to work around
-problems with invalid Maverick instruction combinations. This option
-is only valid if the @option{-mcpu=ep9312} option has been used to
-enable generation of instructions for the Cirrus Maverick floating
-point co-processor. This option is not enabled by default, since the
-problem is only present in older Maverick implementations. The default
-can be re-enabled by use of the @option{-mno-cirrus-fix-invalid-insns}
-switch.
-
-@item -mpoke-function-name
-@opindex mpoke-function-name
-Write the name of each function into the text section, directly
-preceding the function prologue. The generated code is similar to this:
-
-@smallexample
- t0
- .ascii "arm_poke_function_name", 0
- .align
- t1
- .word 0xff000000 + (t1 - t0)
- arm_poke_function_name
- mov ip, sp
- stmfd sp!, @{fp, ip, lr, pc@}
- sub fp, ip, #4
-@end smallexample
-
-When performing a stack backtrace, code can inspect the value of
-@code{pc} stored at @code{fp + 0}. If the trace function then looks at
-location @code{pc - 12} and the top 8 bits are set, then we know that
-there is a function name embedded immediately preceding this location
-and has length @code{((pc[-3]) & 0xff000000)}.
-
-@item -mthumb
-@opindex mthumb
-Generate code for the 16-bit Thumb instruction set. The default is to
-use the 32-bit ARM instruction set.
-
-@item -mtpcs-frame
-@opindex mtpcs-frame
-Generate a stack frame that is compliant with the Thumb Procedure Call
-Standard for all non-leaf functions. (A leaf function is one that does
-not call any other functions.) The default is @option{-mno-tpcs-frame}.
-
-@item -mtpcs-leaf-frame
-@opindex mtpcs-leaf-frame
-Generate a stack frame that is compliant with the Thumb Procedure Call
-Standard for all leaf functions. (A leaf function is one that does
-not call any other functions.) The default is @option{-mno-apcs-leaf-frame}.
-
-@item -mcallee-super-interworking
-@opindex mcallee-super-interworking
-Gives all externally visible functions in the file being compiled an ARM
-instruction set header which switches to Thumb mode before executing the
-rest of the function. This allows these functions to be called from
-non-interworking code.
-
-@item -mcaller-super-interworking
-@opindex mcaller-super-interworking
-Allows calls via function pointers (including virtual functions) to
-execute correctly regardless of whether the target code has been
-compiled for interworking or not. There is a small overhead in the cost
-of executing a function pointer if this option is enabled.
-
-@end table
-
-@node MN10300 Options
-@subsection MN10300 Options
-@cindex MN10300 options