(absence_set "pipe0" "pipe1")
\f
-(define_constants [
- (UNSPEC_BLOCKAGE 0)
- (UNSPEC_IPREFETCH 1)
- (UNSPEC_FREST 2)
- (UNSPEC_FRSQEST 3)
- (UNSPEC_FI 4)
- (UNSPEC_EXTEND_CMP 5)
- (UNSPEC_CG 6)
- (UNSPEC_CGX 7)
- (UNSPEC_ADDX 8)
- (UNSPEC_BG 9)
- (UNSPEC_BGX 10)
- (UNSPEC_SFX 11)
- (UNSPEC_FSM 12)
- (UNSPEC_HBR 13)
- (UNSPEC_LNOP 14)
- (UNSPEC_NOP 15)
- (UNSPEC_CONVERT 16)
- (UNSPEC_SELB 17)
- (UNSPEC_SHUFB 18)
- (UNSPEC_CPAT 19)
- (UNSPEC_SYNC 20)
- (UNSPEC_CNTB 21)
- (UNSPEC_SUMB 22)
- (UNSPEC_FSMB 23)
- (UNSPEC_FSMH 24)
- (UNSPEC_GBB 25)
- (UNSPEC_GBH 26)
- (UNSPEC_GB 27)
- (UNSPEC_AVGB 28)
- (UNSPEC_ABSDB 29)
- (UNSPEC_ORX 30)
- (UNSPEC_HEQ 31)
- (UNSPEC_HGT 32)
- (UNSPEC_HLGT 33)
- (UNSPEC_STOP 38)
- (UNSPEC_STOPD 39)
- (UNSPEC_SET_INTR 40)
- (UNSPEC_FSCRRD 42)
- (UNSPEC_FSCRWR 43)
- (UNSPEC_MFSPR 44)
- (UNSPEC_MTSPR 45)
- (UNSPEC_RDCH 46)
- (UNSPEC_RCHCNT 47)
- (UNSPEC_WRCH 48)
- (UNSPEC_SPU_REALIGN_LOAD 49)
- (UNSPEC_SPU_MASK_FOR_LOAD 50)
- (UNSPEC_DFTSV 51)
- (UNSPEC_FLOAT_EXTEND 52)
- (UNSPEC_FLOAT_TRUNCATE 53)
- (UNSPEC_SP_SET 54)
- (UNSPEC_SP_TEST 55)
+(define_c_enum "unspec" [
+ UNSPEC_IPREFETCH
+ UNSPEC_FREST
+ UNSPEC_FRSQEST
+ UNSPEC_FI
+ UNSPEC_EXTEND_CMP
+ UNSPEC_CG
+ UNSPEC_CGX
+ UNSPEC_ADDX
+ UNSPEC_BG
+ UNSPEC_BGX
+ UNSPEC_SFX
+ UNSPEC_FSM
+ UNSPEC_HBR
+ UNSPEC_NOP
+ UNSPEC_CONVERT
+ UNSPEC_SELB
+ UNSPEC_SHUFB
+ UNSPEC_CPAT
+ UNSPEC_CNTB
+ UNSPEC_SUMB
+ UNSPEC_FSMB
+ UNSPEC_FSMH
+ UNSPEC_GBB
+ UNSPEC_GBH
+ UNSPEC_GB
+ UNSPEC_AVGB
+ UNSPEC_ABSDB
+ UNSPEC_ORX
+ UNSPEC_HEQ
+ UNSPEC_HGT
+ UNSPEC_HLGT
+ UNSPEC_STOP
+ UNSPEC_STOPD
+ UNSPEC_SET_INTR
+ UNSPEC_FSCRRD
+ UNSPEC_FSCRWR
+ UNSPEC_MFSPR
+ UNSPEC_MTSPR
+ UNSPEC_RDCH
+ UNSPEC_RCHCNT
+ UNSPEC_WRCH
+ UNSPEC_SPU_REALIGN_LOAD
+ UNSPEC_SPU_MASK_FOR_LOAD
+ UNSPEC_DFTSV
+ UNSPEC_FLOAT_EXTEND
+ UNSPEC_FLOAT_TRUNCATE
+ UNSPEC_SP_SET
+ UNSPEC_SP_TEST
+])
+
+(define_c_enum "unspecv" [
+ UNSPECV_BLOCKAGE
+ UNSPECV_LNOP
+ UNSPECV_NOP
+ UNSPECV_SYNC
])
(include "predicates.md")
\f
;; vector conditional compare patterns
-(define_expand "vcond<mode>"
+(define_expand "vcond<mode><mode>"
[(set (match_operand:VCMP 0 "spu_reg_operand" "=r")
(if_then_else:VCMP
(match_operator 3 "comparison_operator"
FAIL;
})
-(define_expand "vcondu<mode>"
+(define_expand "vcondu<mode><mode>"
[(set (match_operand:VCMPU 0 "spu_reg_operand" "=r")
(if_then_else:VCMPU
(match_operator 3 "comparison_operator"
;; generated by the spu_expand_epilogue (taken from mips.md)
(define_insn "blockage"
- [(unspec_volatile [(const_int 0)] UNSPEC_BLOCKAGE)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)]
""
""
[(set_attr "type" "convert")
"shufb\t%0,%1,%2,%3"
[(set_attr "type" "shuf")])
+; The semantics of vec_permv16qi are nearly identical to those of the SPU
+; shufb instruction, except that we need to reduce the selector modulo 32.
+(define_expand "vec_permv16qi"
+ [(set (match_dup 4) (and:V16QI (match_operand:V16QI 3 "spu_reg_operand" "")
+ (match_dup 6)))
+ (set (match_operand:V16QI 0 "spu_reg_operand" "")
+ (unspec:V16QI
+ [(match_operand:V16QI 1 "spu_reg_operand" "")
+ (match_operand:V16QI 2 "spu_reg_operand" "")
+ (match_dup 5)]
+ UNSPEC_SHUFB))]
+ ""
+ {
+ operands[4] = gen_reg_rtx (V16QImode);
+ operands[5] = gen_lowpart (TImode, operands[4]);
+ operands[6] = spu_const (V16QImode, 31);
+ })
+
(define_insn "nop"
- [(unspec_volatile [(const_int 0)] UNSPEC_NOP)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_NOP)]
""
"nop"
[(set_attr "type" "nop")])
(define_insn "nopn"
- [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "K")] UNSPEC_NOP)]
+ [(unspec_volatile [(match_operand:SI 0 "immediate_operand" "K")] UNSPECV_NOP)]
""
"nop\t%0"
[(set_attr "type" "nop")])
(define_insn "lnop"
- [(unspec_volatile [(const_int 0)] UNSPEC_LNOP)]
+ [(unspec_volatile [(const_int 0)] UNSPECV_LNOP)]
""
"lnop"
[(set_attr "type" "lnop")])
[(set_attr "type" "hbr")])
(define_insn "sync"
- [(unspec_volatile [(const_int 0)] UNSPEC_SYNC)
+ [(unspec_volatile [(const_int 0)] UNSPECV_SYNC)
(clobber (mem:BLK (scratch)))]
""
"sync"
[(set_attr "type" "br")])
(define_insn "syncc"
- [(unspec_volatile [(const_int 1)] UNSPEC_SYNC)
+ [(unspec_volatile [(const_int 1)] UNSPECV_SYNC)
(clobber (mem:BLK (scratch)))]
""
"syncc"
[(set_attr "type" "br")])
(define_insn "dsync"
- [(unspec_volatile [(const_int 2)] UNSPEC_SYNC)
+ [(unspec_volatile [(const_int 2)] UNSPECV_SYNC)
(clobber (mem:BLK (scratch)))]
""
"dsync"
})
\f
-(define_expand "vec_extract_evenv4si"
- [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
- (vec_concat:V4SI
- (vec_select:V2SI
- (match_operand:V4SI 1 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 2)]))
- (vec_select:V2SI
- (match_operand:V4SI 2 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 2)]))))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x00, 0x01, 0x02, 0x03,
- 0x08, 0x09, 0x0A, 0x0B,
- 0x10, 0x11, 0x12, 0x13,
- 0x18, 0x19, 0x1A, 0x1B};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-
-(define_expand "vec_extract_evenv4sf"
- [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
- (vec_concat:V4SF
- (vec_select:V2SF
- (match_operand:V4SF 1 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 2)]))
- (vec_select:V2SF
- (match_operand:V4SF 2 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 2)]))))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x00, 0x01, 0x02, 0x03,
- 0x08, 0x09, 0x0A, 0x0B,
- 0x10, 0x11, 0x12, 0x13,
- 0x18, 0x19, 0x1A, 0x1B};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_extract_evenv8hi"
- [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
- (vec_concat:V8HI
- (vec_select:V4HI
- (match_operand:V8HI 1 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))
- (vec_select:V4HI
- (match_operand:V8HI 2 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)]))))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x00, 0x01, 0x04, 0x05,
- 0x08, 0x09, 0x0C, 0x0D,
- 0x10, 0x11, 0x14, 0x15,
- 0x18, 0x19, 0x1C, 0x1D};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_extract_evenv16qi"
- [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
- (vec_concat:V16QI
- (vec_select:V8QI
- (match_operand:V16QI 1 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)
- (const_int 8)(const_int 10)(const_int 12)(const_int 14)]))
- (vec_select:V8QI
- (match_operand:V16QI 2 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 2)(const_int 4)(const_int 6)
- (const_int 8)(const_int 10)(const_int 12)(const_int 14)]))))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x00, 0x02, 0x04, 0x06,
- 0x08, 0x0A, 0x0C, 0x0E,
- 0x10, 0x12, 0x14, 0x16,
- 0x18, 0x1A, 0x1C, 0x1E};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_extract_oddv4si"
- [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
- (vec_concat:V4SI
- (vec_select:V2SI
- (match_operand:V4SI 1 "spu_reg_operand" "r")
- (parallel [(const_int 1)(const_int 3)]))
- (vec_select:V2SI
- (match_operand:V4SI 2 "spu_reg_operand" "r")
- (parallel [(const_int 1)(const_int 3)]))))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x04, 0x05, 0x06, 0x07,
- 0x0C, 0x0D, 0x0E, 0x0F,
- 0x14, 0x15, 0x16, 0x17,
- 0x1C, 0x1D, 0x1E, 0x1F};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_extract_oddv4sf"
- [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
- (vec_concat:V4SF
- (vec_select:V2SF
- (match_operand:V4SF 1 "spu_reg_operand" "r")
- (parallel [(const_int 1)(const_int 3)]))
- (vec_select:V2SF
- (match_operand:V4SF 2 "spu_reg_operand" "r")
- (parallel [(const_int 1)(const_int 3)]))))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x04, 0x05, 0x06, 0x07,
- 0x0C, 0x0D, 0x0E, 0x0F,
- 0x14, 0x15, 0x16, 0x17,
- 0x1C, 0x1D, 0x1E, 0x1F};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_extract_oddv8hi"
- [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
- (vec_concat:V8HI
- (vec_select:V4HI
- (match_operand:V8HI 1 "spu_reg_operand" "r")
- (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))
- (vec_select:V4HI
- (match_operand:V8HI 2 "spu_reg_operand" "r")
- (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)]))))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x02, 0x03, 0x06, 0x07,
- 0x0A, 0x0B, 0x0E, 0x0F,
- 0x12, 0x13, 0x16, 0x17,
- 0x1A, 0x1B, 0x1E, 0x1F};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_extract_oddv16qi"
- [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
- (vec_concat:V16QI
- (vec_select:V8QI
- (match_operand:V16QI 1 "spu_reg_operand" "r")
- (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
- (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))
- (vec_select:V8QI
- (match_operand:V16QI 2 "spu_reg_operand" "r")
- (parallel [(const_int 1)(const_int 3)(const_int 5)(const_int 7)
- (const_int 9)(const_int 11)(const_int 13)(const_int 15)]))))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x01, 0x03, 0x05, 0x07,
- 0x09, 0x0B, 0x0D, 0x0F,
- 0x11, 0x13, 0x15, 0x17,
- 0x19, 0x1B, 0x1D, 0x1F};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_interleave_highv4sf"
- [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
- (vec_select:V4SF
- (vec_concat:V4SF
- (vec_select:V2SF
- (match_operand:V4SF 1 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 1)]))
- (vec_select:V2SF
- (match_operand:V4SF 2 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 1)])))
- (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x00, 0x01, 0x02, 0x03,
- 0x10, 0x11, 0x12, 0x13,
- 0x04, 0x05, 0x06, 0x07,
- 0x14, 0x15, 0x16, 0x17};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_interleave_lowv4sf"
- [(set (match_operand:V4SF 0 "spu_reg_operand" "=r")
- (vec_select:V4SF
- (vec_concat:V4SF
- (vec_select:V2SF
- (match_operand:V4SF 1 "spu_reg_operand" "r")
- (parallel [(const_int 2)(const_int 3)]))
- (vec_select:V2SF
- (match_operand:V4SF 2 "spu_reg_operand" "r")
- (parallel [(const_int 2)(const_int 3)])))
- (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x08, 0x09, 0x0A, 0x0B,
- 0x18, 0x19, 0x1A, 0x1B,
- 0x0C, 0x0D, 0x0E, 0x0F,
- 0x1C, 0x1D, 0x1E, 0x1F};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_interleave_highv4si"
- [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
- (vec_select:V4SI
- (vec_concat:V4SI
- (vec_select:V2SI
- (match_operand:V4SI 1 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 1)]))
- (vec_select:V2SI
- (match_operand:V4SI 2 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 1)])))
- (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x00, 0x01, 0x02, 0x03,
- 0x10, 0x11, 0x12, 0x13,
- 0x04, 0x05, 0x06, 0x07,
- 0x14, 0x15, 0x16, 0x17};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_interleave_lowv4si"
- [(set (match_operand:V4SI 0 "spu_reg_operand" "=r")
- (vec_select:V4SI
- (vec_concat:V4SI
- (vec_select:V2SI
- (match_operand:V4SI 1 "spu_reg_operand" "r")
- (parallel [(const_int 2)(const_int 3)]))
- (vec_select:V2SI
- (match_operand:V4SI 2 "spu_reg_operand" "r")
- (parallel [(const_int 2)(const_int 3)])))
- (parallel [(const_int 0)(const_int 2)(const_int 1)(const_int 3)])))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x08, 0x09, 0x0A, 0x0B,
- 0x18, 0x19, 0x1A, 0x1B,
- 0x0C, 0x0D, 0x0E, 0x0F,
- 0x1C, 0x1D, 0x1E, 0x1F};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_interleave_highv8hi"
- [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
- (vec_select:V8HI
- (vec_concat:V8HI
- (vec_select:V4HI
- (match_operand:V8HI 1 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)]))
- (vec_select:V4HI
- (match_operand:V8HI 2 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)])))
- (parallel [(const_int 0)(const_int 4)(const_int 1)(const_int 5)
- (const_int 2)(const_int 6)(const_int 3)(const_int 7)])))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x00, 0x01, 0x10, 0x11,
- 0x02, 0x03, 0x12, 0x13,
- 0x04, 0x05, 0x14, 0x15,
- 0x06, 0x07, 0x16, 0x17};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
- }")
-
-(define_expand "vec_interleave_lowv8hi"
- [(set (match_operand:V8HI 0 "spu_reg_operand" "=r")
- (vec_select:V8HI
- (vec_concat:V8HI
- (vec_select:V4HI
- (match_operand:V8HI 1 "spu_reg_operand" "r")
- (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)]))
- (vec_select:V4HI
- (match_operand:V8HI 2 "spu_reg_operand" "r")
- (parallel [(const_int 4)(const_int 5)(const_int 6)(const_int 7)])))
- (parallel [(const_int 0)(const_int 4)(const_int 1)(const_int 5)
- (const_int 2)(const_int 6)(const_int 3)(const_int 7)])))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x08, 0x09, 0x18, 0x19,
- 0x0A, 0x0B, 0x1A, 0x1B,
- 0x0C, 0x0D, 0x1C, 0x1D,
- 0x0E, 0x0F, 0x1E, 0x1F};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_interleave_highv16qi"
- [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
- (vec_select:V16QI
- (vec_concat:V16QI
- (vec_select:V8QI
- (match_operand:V16QI 1 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)
- (const_int 4)(const_int 5)(const_int 6)(const_int 7)]))
- (vec_select:V8QI
- (match_operand:V16QI 2 "spu_reg_operand" "r")
- (parallel [(const_int 0)(const_int 1)(const_int 2)(const_int 3)
- (const_int 4)(const_int 5)(const_int 6)(const_int 7)])))
- (parallel [(const_int 0)(const_int 8)(const_int 1)(const_int 9)
- (const_int 2)(const_int 10)(const_int 3)(const_int 11)
- (const_int 4)(const_int 12)(const_int 5)(const_int 13)
- (const_int 6)(const_int 14)(const_int 7)(const_int 15)])))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x00, 0x10, 0x01, 0x11,
- 0x02, 0x12, 0x03, 0x13,
- 0x04, 0x14, 0x05, 0x15,
- 0x06, 0x16, 0x07, 0x17};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
-(define_expand "vec_interleave_lowv16qi"
- [(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
- (vec_select:V16QI
- (vec_concat:V16QI
- (vec_select:V8QI
- (match_operand:V16QI 1 "spu_reg_operand" "r")
- (parallel [(const_int 8)(const_int 9)(const_int 10)(const_int 11)
- (const_int 12)(const_int 13)(const_int 14)(const_int 15)]))
- (vec_select:V8QI
- (match_operand:V16QI 2 "spu_reg_operand" "r")
- (parallel [(const_int 8)(const_int 9)(const_int 10)(const_int 11)
- (const_int 12)(const_int 13)(const_int 14)(const_int 15)])))
- (parallel [(const_int 0)(const_int 8)(const_int 1)(const_int 9)
- (const_int 2)(const_int 10)(const_int 3)(const_int 11)
- (const_int 4)(const_int 12)(const_int 5)(const_int 13)
- (const_int 6)(const_int 14)(const_int 7)(const_int 15)])))]
-
- ""
- "
-{
- rtx mask = gen_reg_rtx (TImode);
- unsigned char arr[16] = {
- 0x08, 0x18, 0x09, 0x19,
- 0x0A, 0x1A, 0x0B, 0x1B,
- 0x0C, 0x1C, 0x0D, 0x1D,
- 0x0E, 0x1E, 0x0F, 0x1F};
-
- emit_move_insn (mask, array_to_constant (TImode, arr));
- emit_insn (gen_shufb (operands[0], operands[1], operands[2], mask));
- DONE;
-}")
-
(define_expand "vec_pack_trunc_v8hi"
[(set (match_operand:V16QI 0 "spu_reg_operand" "=r")
(vec_concat:V16QI
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