1 #define _FP_W_TYPE_SIZE 32
2 #define _FP_W_TYPE unsigned int
3 #define _FP_WS_TYPE signed int
6 /* The type of the result of a floating point comparison. This must
7 match `__libgcc_cmp_return__' in GCC for the target. */
8 typedef int __gcc_CMPtype __attribute__ ((mode (__libgcc_cmp_return__)));
9 #define CMPtype __gcc_CMPtype
11 #define __FP_FRAC_ADD_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
12 __asm__ ("add{l} {%11,%3|%3,%11}\n\t" \
13 "adc{l} {%9,%2|%2,%9}\n\t" \
14 "adc{l} {%7,%1|%1,%7}\n\t" \
15 "adc{l} {%5,%0|%0,%5}" \
16 : "=r" ((USItype) (r3)), \
17 "=&r" ((USItype) (r2)), \
18 "=&r" ((USItype) (r1)), \
19 "=&r" ((USItype) (r0)) \
20 : "%0" ((USItype) (x3)), \
21 "g" ((USItype) (y3)), \
22 "%1" ((USItype) (x2)), \
23 "g" ((USItype) (y2)), \
24 "%2" ((USItype) (x1)), \
25 "g" ((USItype) (y1)), \
26 "%3" ((USItype) (x0)), \
28 #define __FP_FRAC_ADD_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
29 __asm__ ("add{l} {%8,%2|%2,%8}\n\t" \
30 "adc{l} {%6,%1|%1,%6}\n\t" \
31 "adc{l} {%4,%0|%0,%4}" \
32 : "=r" ((USItype) (r2)), \
33 "=&r" ((USItype) (r1)), \
34 "=&r" ((USItype) (r0)) \
35 : "%0" ((USItype) (x2)), \
36 "g" ((USItype) (y2)), \
37 "%1" ((USItype) (x1)), \
38 "g" ((USItype) (y1)), \
39 "%2" ((USItype) (x0)), \
42 /* FIXME: Change last operand constraint
43 from "im" to "g" when reload works properly. */
44 #define __FP_FRAC_SUB_4(r3,r2,r1,r0,x3,x2,x1,x0,y3,y2,y1,y0) \
45 __asm__ ("sub{l} {%11,%3|%3,%11}\n\t" \
46 "sbb{l} {%9,%2|%2,%9}\n\t" \
47 "sbb{l} {%7,%1|%1,%7}\n\t" \
48 "sbb{l} {%5,%0|%0,%5}" \
49 : "=r" ((USItype) (r3)), \
50 "=&r" ((USItype) (r2)), \
51 "=&r" ((USItype) (r1)), \
52 "=&r" ((USItype) (r0)) \
53 : "0" ((USItype) (x3)), \
54 "g" ((USItype) (y3)), \
55 "1" ((USItype) (x2)), \
56 "g" ((USItype) (y2)), \
57 "2" ((USItype) (x1)), \
58 "g" ((USItype) (y1)), \
59 "3" ((USItype) (x0)), \
60 "im" ((USItype) (y0)))
61 #define __FP_FRAC_SUB_3(r2,r1,r0,x2,x1,x0,y2,y1,y0) \
62 __asm__ ("sub{l} {%8,%2|%2,%8}\n\t" \
63 "sbb{l} {%6,%1|%1,%6}\n\t" \
64 "sbb{l} {%4,%0|%0,%4}" \
65 : "=r" ((USItype) (r2)), \
66 "=&r" ((USItype) (r1)), \
67 "=&r" ((USItype) (r0)) \
68 : "0" ((USItype) (x2)), \
69 "g" ((USItype) (y2)), \
70 "1" ((USItype) (x1)), \
71 "g" ((USItype) (y1)), \
72 "2" ((USItype) (x0)), \
76 #define _FP_MUL_MEAT_Q(R,X,Y) \
77 _FP_MUL_MEAT_4_wide(_FP_WFRACBITS_Q,R,X,Y,umul_ppmm)
79 #define _FP_DIV_MEAT_Q(R,X,Y) _FP_DIV_MEAT_4_udiv(Q,R,X,Y)
81 #define _FP_NANFRAC_S _FP_QNANBIT_S
82 #define _FP_NANFRAC_D _FP_QNANBIT_D, 0
83 /* Even if XFmode is 12byte, we have to pad it to
84 16byte since soft-fp emulation is done in 16byte. */
85 #define _FP_NANFRAC_E _FP_QNANBIT_E, 0, 0, 0
86 #define _FP_NANFRAC_Q _FP_QNANBIT_Q, 0, 0, 0
87 #define _FP_NANSIGN_S 1
88 #define _FP_NANSIGN_D 1
89 #define _FP_NANSIGN_E 1
90 #define _FP_NANSIGN_Q 1
92 #define _FP_KEEPNANFRACP 1
94 /* Here is something Intel misdesigned: the specs don't define
95 the case where we have two NaNs with same mantissas, but
96 different sign. Different operations pick up different NaNs. */
97 #define _FP_CHOOSENAN(fs, wc, R, X, Y, OP) \
99 if (_FP_FRAC_GT_##wc(X, Y) \
100 || (_FP_FRAC_EQ_##wc(X,Y) && (OP == '+' || OP == '*'))) \
103 _FP_FRAC_COPY_##wc(R,X); \
108 _FP_FRAC_COPY_##wc(R,Y); \
110 R##_c = FP_CLS_NAN; \
113 #define FP_EX_INVALID 0x01
114 #define FP_EX_DENORM 0x02
115 #define FP_EX_DIVZERO 0x04
116 #define FP_EX_OVERFLOW 0x08
117 #define FP_EX_UNDERFLOW 0x10
118 #define FP_EX_INEXACT 0x20
122 unsigned short int __control_word;
123 unsigned short int __unused1;
124 unsigned short int __status_word;
125 unsigned short int __unused2;
126 unsigned short int __tags;
127 unsigned short int __unused3;
129 unsigned short int __cs_selector;
130 unsigned int __opcode:11;
131 unsigned int __unused4:5;
132 unsigned int __data_offset;
133 unsigned short int __data_selector;
134 unsigned short int __unused5;
137 #define FP_HANDLE_EXCEPTIONS \
139 if (_fex & FP_EX_INVALID) \
142 __asm__ __volatile__ ("fdiv %0" : "+t" (f)); \
143 __asm__ __volatile__ ("fwait"); \
145 if (_fex & FP_EX_DIVZERO) \
147 float f = 1.0, g = 0.0; \
148 __asm__ __volatile__ ("fdivp" : "=t" (f) \
151 __asm__ __volatile__ ("fwait"); \
153 if (_fex & FP_EX_OVERFLOW) \
156 __asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
157 temp.__status_word |= FP_EX_OVERFLOW; \
158 __asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
159 __asm__ __volatile__ ("fwait"); \
161 if (_fex & FP_EX_UNDERFLOW) \
164 __asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
165 temp.__status_word |= FP_EX_UNDERFLOW; \
166 __asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
167 __asm__ __volatile__ ("fwait"); \
169 if (_fex & FP_EX_INEXACT) \
172 __asm__ __volatile__ ("fnstenv %0" : "=m" (temp)); \
173 temp.__status_word |= FP_EX_INEXACT; \
174 __asm__ __volatile__ ("fldenv %0" : : "m" (temp)); \
175 __asm__ __volatile__ ("fwait"); \
179 #define FP_RND_NEAREST 0
180 #define FP_RND_ZERO 0xc00
181 #define FP_RND_PINF 0x800
182 #define FP_RND_MINF 0x400
184 #define _FP_DECL_EX \
185 unsigned short _fcw __attribute__ ((unused)) = FP_RND_NEAREST
187 #define FP_INIT_ROUNDMODE \
189 __asm__ ("fnstcw %0" : "=m" (_fcw)); \
192 #define FP_ROUNDMODE (_fcw & 0xc00)
194 #define __LITTLE_ENDIAN 1234
195 #define __BIG_ENDIAN 4321
197 #define __BYTE_ORDER __LITTLE_ENDIAN
199 /* Define ALIASNAME as a strong alias for NAME. */
201 /* Mach-O doesn't support aliasing. If these functions ever return
202 anything but CMPtype we need to revisit this... */
203 #define strong_alias(name, aliasname) \
204 CMPtype aliasname (TFtype a, TFtype b) { return name(a, b); }
206 # define strong_alias(name, aliasname) _strong_alias(name, aliasname)
207 # define _strong_alias(name, aliasname) \
208 extern __typeof (name) aliasname __attribute__ ((alias (#name)));