1 /* Instruction scheduling pass. Selective scheduler and pipeliner.
2 Copyright (C) 2006, 2007, 2008, 2009, 2010, 2011
3 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 3, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING3. If not see
19 <http://www.gnu.org/licenses/>. */
23 #include "coretypes.h"
25 #include "rtl-error.h"
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-attr.h"
39 #include "tree-pass.h"
40 #include "sched-int.h"
44 #include "langhooks.h"
45 #include "rtlhooks-def.h"
49 #ifdef INSN_SCHEDULING
50 #include "sel-sched-ir.h"
51 #include "sel-sched-dump.h"
52 #include "sel-sched.h"
55 /* Implementation of selective scheduling approach.
56 The below implementation follows the original approach with the following
59 o the scheduler works after register allocation (but can be also tuned
61 o some instructions are not copied or register renamed;
62 o conditional jumps are not moved with code duplication;
63 o several jumps in one parallel group are not supported;
64 o when pipelining outer loops, code motion through inner loops
66 o control and data speculation are supported;
67 o some improvements for better compile time/performance were made.
72 A vinsn, or virtual insn, is an insn with additional data characterizing
73 insn pattern, such as LHS, RHS, register sets used/set/clobbered, etc.
74 Vinsns also act as smart pointers to save memory by reusing them in
75 different expressions. A vinsn is described by vinsn_t type.
77 An expression is a vinsn with additional data characterizing its properties
78 at some point in the control flow graph. The data may be its usefulness,
79 priority, speculative status, whether it was renamed/subsituted, etc.
80 An expression is described by expr_t type.
82 Availability set (av_set) is a set of expressions at a given control flow
83 point. It is represented as av_set_t. The expressions in av sets are kept
84 sorted in the terms of expr_greater_p function. It allows to truncate
85 the set while leaving the best expressions.
87 A fence is a point through which code motion is prohibited. On each step,
88 we gather a parallel group of insns at a fence. It is possible to have
89 multiple fences. A fence is represented via fence_t.
91 A boundary is the border between the fence group and the rest of the code.
92 Currently, we never have more than one boundary per fence, as we finalize
93 the fence group when a jump is scheduled. A boundary is represented
99 The scheduler finds regions to schedule, schedules each one, and finalizes.
100 The regions are formed starting from innermost loops, so that when the inner
101 loop is pipelined, its prologue can be scheduled together with yet unprocessed
102 outer loop. The rest of acyclic regions are found using extend_rgns:
103 the blocks that are not yet allocated to any regions are traversed in top-down
104 order, and a block is added to a region to which all its predecessors belong;
105 otherwise, the block starts its own region.
107 The main scheduling loop (sel_sched_region_2) consists of just
108 scheduling on each fence and updating fences. For each fence,
109 we fill a parallel group of insns (fill_insns) until some insns can be added.
110 First, we compute available exprs (av-set) at the boundary of the current
111 group. Second, we choose the best expression from it. If the stall is
112 required to schedule any of the expressions, we advance the current cycle
113 appropriately. So, the final group does not exactly correspond to a VLIW
114 word. Third, we move the chosen expression to the boundary (move_op)
115 and update the intermediate av sets and liveness sets. We quit fill_insns
116 when either no insns left for scheduling or we have scheduled enough insns
117 so we feel like advancing a scheduling point.
119 Computing available expressions
120 ===============================
122 The computation (compute_av_set) is a bottom-up traversal. At each insn,
123 we're moving the union of its successors' sets through it via
124 moveup_expr_set. The dependent expressions are removed. Local
125 transformations (substitution, speculation) are applied to move more
126 exprs. Then the expr corresponding to the current insn is added.
127 The result is saved on each basic block header.
129 When traversing the CFG, we're moving down for no more than max_ws insns.
130 Also, we do not move down to ineligible successors (is_ineligible_successor),
131 which include moving along a back-edge, moving to already scheduled code,
132 and moving to another fence. The first two restrictions are lifted during
133 pipelining, which allows us to move insns along a back-edge. We always have
134 an acyclic region for scheduling because we forbid motion through fences.
136 Choosing the best expression
137 ============================
139 We sort the final availability set via sel_rank_for_schedule, then we remove
140 expressions which are not yet ready (tick_check_p) or which dest registers
141 cannot be used. For some of them, we choose another register via
142 find_best_reg. To do this, we run find_used_regs to calculate the set of
143 registers which cannot be used. The find_used_regs function performs
144 a traversal of code motion paths for an expr. We consider for renaming
145 only registers which are from the same regclass as the original one and
146 using which does not interfere with any live ranges. Finally, we convert
147 the resulting set to the ready list format and use max_issue and reorder*
148 hooks similarly to the Haifa scheduler.
150 Scheduling the best expression
151 ==============================
153 We run the move_op routine to perform the same type of code motion paths
154 traversal as in find_used_regs. (These are working via the same driver,
155 code_motion_path_driver.) When moving down the CFG, we look for original
156 instruction that gave birth to a chosen expression. We undo
157 the transformations performed on an expression via the history saved in it.
158 When found, we remove the instruction or leave a reg-reg copy/speculation
159 check if needed. On a way up, we insert bookkeeping copies at each join
160 point. If a copy is not needed, it will be removed later during this
161 traversal. We update the saved av sets and liveness sets on the way up, too.
163 Finalizing the schedule
164 =======================
166 When pipelining, we reschedule the blocks from which insns were pipelined
167 to get a tighter schedule. On Itanium, we also perform bundling via
168 the same routine from ia64.c.
170 Dependence analysis changes
171 ===========================
173 We augmented the sched-deps.c with hooks that get called when a particular
174 dependence is found in a particular part of an insn. Using these hooks, we
175 can do several actions such as: determine whether an insn can be moved through
176 another (has_dependence_p, moveup_expr); find out whether an insn can be
177 scheduled on the current cycle (tick_check_p); find out registers that
178 are set/used/clobbered by an insn and find out all the strange stuff that
179 restrict its movement, like SCHED_GROUP_P or CANT_MOVE (done in
180 init_global_and_expr_for_insn).
182 Initialization changes
183 ======================
185 There are parts of haifa-sched.c, sched-deps.c, and sched-rgn.c that are
186 reused in all of the schedulers. We have split up the initialization of data
187 of such parts into different functions prefixed with scheduler type and
188 postfixed with the type of data initialized: {,sel_,haifa_}sched_{init,finish},
189 sched_rgn_init/finish, sched_deps_init/finish, sched_init_{luids/bbs}, etc.
190 The same splitting is done with current_sched_info structure:
191 dependence-related parts are in sched_deps_info, common part is in
192 common_sched_info, and haifa/sel/etc part is in current_sched_info.
197 As we now have multiple-point scheduling, this would not work with backends
198 which save some of the scheduler state to use it in the target hooks.
199 For this purpose, we introduce a concept of target contexts, which
200 encapsulate such information. The backend should implement simple routines
201 of allocating/freeing/setting such a context. The scheduler calls these
202 as target hooks and handles the target context as an opaque pointer (similar
203 to the DFA state type, state_t).
208 As the correct data dependence graph is not supported during scheduling (which
209 is to be changed in mid-term), we cache as much of the dependence analysis
210 results as possible to avoid reanalyzing. This includes: bitmap caches on
211 each insn in stream of the region saying yes/no for a query with a pair of
212 UIDs; hashtables with the previously done transformations on each insn in
213 stream; a vector keeping a history of transformations on each expr.
215 Also, we try to minimize the dependence context used on each fence to check
216 whether the given expression is ready for scheduling by removing from it
217 insns that are definitely completed the execution. The results of
218 tick_check_p checks are also cached in a vector on each fence.
220 We keep a valid liveness set on each insn in a region to avoid the high
221 cost of recomputation on large basic blocks.
223 Finally, we try to minimize the number of needed updates to the availability
224 sets. The updates happen in two cases: when fill_insns terminates,
225 we advance all fences and increase the stage number to show that the region
226 has changed and the sets are to be recomputed; and when the next iteration
227 of a loop in fill_insns happens (but this one reuses the saved av sets
228 on bb headers.) Thus, we try to break the fill_insns loop only when
229 "significant" number of insns from the current scheduling window was
230 scheduled. This should be made a target param.
233 TODO: correctly support the data dependence graph at all stages and get rid
234 of all caches. This should speed up the scheduler.
235 TODO: implement moving cond jumps with bookkeeping copies on both targets.
236 TODO: tune the scheduler before RA so it does not create too much pseudos.
240 S.-M. Moon and K. Ebcioglu. Parallelizing nonnumerical code with
241 selective scheduling and software pipelining.
242 ACM TOPLAS, Vol 19, No. 6, pages 853--898, Nov. 1997.
244 Andrey Belevantsev, Maxim Kuvyrkov, Vladimir Makarov, Dmitry Melnik,
245 and Dmitry Zhurikhin. An interblock VLIW-targeted instruction scheduler
246 for GCC. In Proceedings of GCC Developers' Summit 2006.
248 Arutyun Avetisyan, Andrey Belevantsev, and Dmitry Melnik. GCC Instruction
249 Scheduler and Software Pipeliner on the Itanium Platform. EPIC-7 Workshop.
250 http://rogue.colorado.edu/EPIC7/.
254 /* True when pipelining is enabled. */
257 /* True if bookkeeping is enabled. */
260 /* Maximum number of insns that are eligible for renaming. */
261 int max_insns_to_rename;
264 /* Definitions of local types and macros. */
266 /* Represents possible outcomes of moving an expression through an insn. */
267 enum MOVEUP_EXPR_CODE
269 /* The expression is not changed. */
272 /* Not changed, but requires a new destination register. */
275 /* Cannot be moved. */
278 /* Changed (substituted or speculated). */
282 /* The container to be passed into rtx search & replace functions. */
283 struct rtx_search_arg
285 /* What we are searching for. */
288 /* The occurence counter. */
292 typedef struct rtx_search_arg *rtx_search_arg_p;
294 /* This struct contains precomputed hard reg sets that are needed when
295 computing registers available for renaming. */
296 struct hard_regs_data
298 /* For every mode, this stores registers available for use with
300 HARD_REG_SET regs_for_mode[NUM_MACHINE_MODES];
302 /* True when regs_for_mode[mode] is initialized. */
303 bool regs_for_mode_ok[NUM_MACHINE_MODES];
305 /* For every register, it has regs that are ok to rename into it.
306 The register in question is always set. If not, this means
307 that the whole set is not computed yet. */
308 HARD_REG_SET regs_for_rename[FIRST_PSEUDO_REGISTER];
310 /* For every mode, this stores registers not available due to
312 HARD_REG_SET regs_for_call_clobbered[NUM_MACHINE_MODES];
314 /* All registers that are used or call used. */
315 HARD_REG_SET regs_ever_used;
318 /* Stack registers. */
319 HARD_REG_SET stack_regs;
323 /* Holds the results of computation of available for renaming and
324 unavailable hard registers. */
327 /* These are unavailable due to calls crossing, globalness, etc. */
328 HARD_REG_SET unavailable_hard_regs;
330 /* These are *available* for renaming. */
331 HARD_REG_SET available_for_renaming;
333 /* Whether this code motion path crosses a call. */
337 /* A global structure that contains the needed information about harg
339 static struct hard_regs_data sel_hrd;
342 /* This structure holds local data used in code_motion_path_driver hooks on
343 the same or adjacent levels of recursion. Here we keep those parameters
344 that are not used in code_motion_path_driver routine itself, but only in
345 its hooks. Moreover, all parameters that can be modified in hooks are
346 in this structure, so all other parameters passed explicitly to hooks are
348 struct cmpd_local_params
350 /* Local params used in move_op_* functions. */
352 /* Edges for bookkeeping generation. */
355 /* C_EXPR merged from all successors and locally allocated temporary C_EXPR. */
356 expr_t c_expr_merged, c_expr_local;
358 /* Local params used in fur_* functions. */
359 /* Copy of the ORIGINAL_INSN list, stores the original insns already
360 found before entering the current level of code_motion_path_driver. */
361 def_list_t old_original_insns;
363 /* Local params used in move_op_* functions. */
364 /* True when we have removed last insn in the block which was
365 also a boundary. Do not update anything or create bookkeeping copies. */
366 BOOL_BITFIELD removed_last_insn : 1;
369 /* Stores the static parameters for move_op_* calls. */
370 struct moveop_static_params
372 /* Destination register. */
375 /* Current C_EXPR. */
378 /* An UID of expr_vliw which is to be moved up. If we find other exprs,
379 they are to be removed. */
382 #ifdef ENABLE_CHECKING
383 /* This is initialized to the insn on which the driver stopped its traversal. */
387 /* True if we scheduled an insn with different register. */
391 /* Stores the static parameters for fur_* calls. */
392 struct fur_static_params
394 /* Set of registers unavailable on the code motion path. */
397 /* Pointer to the list of original insns definitions. */
398 def_list_t *original_insns;
400 /* True if a code motion path contains a CALL insn. */
404 typedef struct fur_static_params *fur_static_params_p;
405 typedef struct cmpd_local_params *cmpd_local_params_p;
406 typedef struct moveop_static_params *moveop_static_params_p;
408 /* Set of hooks and parameters that determine behaviour specific to
409 move_op or find_used_regs functions. */
410 struct code_motion_path_driver_info_def
412 /* Called on enter to the basic block. */
413 int (*on_enter) (insn_t, cmpd_local_params_p, void *, bool);
415 /* Called when original expr is found. */
416 void (*orig_expr_found) (insn_t, expr_t, cmpd_local_params_p, void *);
418 /* Called while descending current basic block if current insn is not
419 the original EXPR we're searching for. */
420 bool (*orig_expr_not_found) (insn_t, av_set_t, void *);
422 /* Function to merge C_EXPRes from different successors. */
423 void (*merge_succs) (insn_t, insn_t, int, cmpd_local_params_p, void *);
425 /* Function to finalize merge from different successors and possibly
426 deallocate temporary data structures used for merging. */
427 void (*after_merge_succs) (cmpd_local_params_p, void *);
429 /* Called on the backward stage of recursion to do moveup_expr.
430 Used only with move_op_*. */
431 void (*ascend) (insn_t, void *);
433 /* Called on the ascending pass, before returning from the current basic
434 block or from the whole traversal. */
435 void (*at_first_insn) (insn_t, cmpd_local_params_p, void *);
437 /* When processing successors in move_op we need only descend into
438 SUCCS_NORMAL successors, while in find_used_regs we need SUCCS_ALL. */
441 /* The routine name to print in dumps ("move_op" of "find_used_regs"). */
442 const char *routine_name;
445 /* Global pointer to current hooks, either points to MOVE_OP_HOOKS or
447 struct code_motion_path_driver_info_def *code_motion_path_driver_info;
449 /* Set of hooks for performing move_op and find_used_regs routines with
450 code_motion_path_driver. */
451 extern struct code_motion_path_driver_info_def move_op_hooks, fur_hooks;
453 /* True if/when we want to emulate Haifa scheduler in the common code.
454 This is used in sched_rgn_local_init and in various places in
456 int sched_emulate_haifa_p;
458 /* GLOBAL_LEVEL is used to discard information stored in basic block headers
459 av_sets. Av_set of bb header is valid if its (bb header's) level is equal
460 to GLOBAL_LEVEL. And invalid if lesser. This is primarily used to advance
461 scheduling window. */
464 /* Current fences. */
467 /* True when separable insns should be scheduled as RHSes. */
468 static bool enable_schedule_as_rhs_p;
470 /* Used in verify_target_availability to assert that target reg is reported
471 unavailabile by both TARGET_UNAVAILABLE and find_used_regs only if
472 we haven't scheduled anything on the previous fence.
473 if scheduled_something_on_previous_fence is true, TARGET_UNAVAILABLE can
474 have more conservative value than the one returned by the
475 find_used_regs, thus we shouldn't assert that these values are equal. */
476 static bool scheduled_something_on_previous_fence;
478 /* All newly emitted insns will have their uids greater than this value. */
479 static int first_emitted_uid;
481 /* Set of basic blocks that are forced to start new ebbs. This is a subset
482 of all the ebb heads. */
483 static bitmap_head _forced_ebb_heads;
484 bitmap_head *forced_ebb_heads = &_forced_ebb_heads;
486 /* Blocks that need to be rescheduled after pipelining. */
487 bitmap blocks_to_reschedule = NULL;
489 /* True when the first lv set should be ignored when updating liveness. */
490 static bool ignore_first = false;
492 /* Number of insns max_issue has initialized data structures for. */
493 static int max_issue_size = 0;
495 /* Whether we can issue more instructions. */
496 static int can_issue_more;
498 /* Maximum software lookahead window size, reduced when rescheduling after
502 /* Number of insns scheduled in current region. */
503 static int num_insns_scheduled;
505 /* A vector of expressions is used to be able to sort them. */
507 DEF_VEC_ALLOC_P(expr_t,heap);
508 static VEC(expr_t, heap) *vec_av_set = NULL;
510 /* A vector of vinsns is used to hold temporary lists of vinsns. */
512 DEF_VEC_ALLOC_P(vinsn_t,heap);
513 typedef VEC(vinsn_t, heap) *vinsn_vec_t;
515 /* This vector has the exprs which may still present in av_sets, but actually
516 can't be moved up due to bookkeeping created during code motion to another
517 fence. See comment near the call to update_and_record_unavailable_insns
518 for the detailed explanations. */
519 static vinsn_vec_t vec_bookkeeping_blocked_vinsns = NULL;
521 /* This vector has vinsns which are scheduled with renaming on the first fence
522 and then seen on the second. For expressions with such vinsns, target
523 availability information may be wrong. */
524 static vinsn_vec_t vec_target_unavailable_vinsns = NULL;
526 /* Vector to store temporary nops inserted in move_op to prevent removal
529 DEF_VEC_ALLOC_P(insn_t,heap);
530 static VEC(insn_t, heap) *vec_temp_moveop_nops = NULL;
532 /* These bitmaps record original instructions scheduled on the current
533 iteration and bookkeeping copies created by them. */
534 static bitmap current_originators = NULL;
535 static bitmap current_copies = NULL;
537 /* This bitmap marks the blocks visited by code_motion_path_driver so we don't
538 visit them afterwards. */
539 static bitmap code_motion_visited_blocks = NULL;
541 /* Variables to accumulate different statistics. */
543 /* The number of bookkeeping copies created. */
544 static int stat_bookkeeping_copies;
546 /* The number of insns that required bookkeeiping for their scheduling. */
547 static int stat_insns_needed_bookkeeping;
549 /* The number of insns that got renamed. */
550 static int stat_renamed_scheduled;
552 /* The number of substitutions made during scheduling. */
553 static int stat_substitutions_total;
556 /* Forward declarations of static functions. */
557 static bool rtx_ok_for_substitution_p (rtx, rtx);
558 static int sel_rank_for_schedule (const void *, const void *);
559 static av_set_t find_sequential_best_exprs (bnd_t, expr_t, bool);
560 static basic_block find_block_for_bookkeeping (edge e1, edge e2, bool lax);
562 static rtx get_dest_from_orig_ops (av_set_t);
563 static basic_block generate_bookkeeping_insn (expr_t, edge, edge);
564 static bool find_used_regs (insn_t, av_set_t, regset, struct reg_rename *,
566 static bool move_op (insn_t, av_set_t, expr_t, rtx, expr_t, bool*);
567 static int code_motion_path_driver (insn_t, av_set_t, ilist_t,
568 cmpd_local_params_p, void *);
569 static void sel_sched_region_1 (void);
570 static void sel_sched_region_2 (int);
571 static av_set_t compute_av_set_inside_bb (insn_t, ilist_t, int, bool);
573 static void debug_state (state_t);
576 /* Functions that work with fences. */
578 /* Advance one cycle on FENCE. */
580 advance_one_cycle (fence_t fence)
586 advance_state (FENCE_STATE (fence));
587 cycle = ++FENCE_CYCLE (fence);
588 FENCE_ISSUED_INSNS (fence) = 0;
589 FENCE_STARTS_CYCLE_P (fence) = 1;
590 can_issue_more = issue_rate;
591 FENCE_ISSUE_MORE (fence) = can_issue_more;
593 for (i = 0; VEC_iterate (rtx, FENCE_EXECUTING_INSNS (fence), i, insn); )
595 if (INSN_READY_CYCLE (insn) < cycle)
597 remove_from_deps (FENCE_DC (fence), insn);
598 VEC_unordered_remove (rtx, FENCE_EXECUTING_INSNS (fence), i);
603 if (sched_verbose >= 2)
605 sel_print ("Finished a cycle. Current cycle = %d\n", FENCE_CYCLE (fence));
606 debug_state (FENCE_STATE (fence));
610 /* Returns true when SUCC in a fallthru bb of INSN, possibly
611 skipping empty basic blocks. */
613 in_fallthru_bb_p (rtx insn, rtx succ)
615 basic_block bb = BLOCK_FOR_INSN (insn);
618 if (bb == BLOCK_FOR_INSN (succ))
621 e = find_fallthru_edge_from (bb);
627 while (sel_bb_empty_p (bb))
630 return bb == BLOCK_FOR_INSN (succ);
633 /* Construct successor fences from OLD_FENCEs and put them in NEW_FENCES.
634 When a successor will continue a ebb, transfer all parameters of a fence
635 to the new fence. ORIG_MAX_SEQNO is the maximal seqno before this round
636 of scheduling helping to distinguish between the old and the new code. */
638 extract_new_fences_from (flist_t old_fences, flist_tail_t new_fences,
641 bool was_here_p = false;
642 insn_t insn = NULL_RTX;
646 fence_t fence = FLIST_FENCE (old_fences);
649 /* Get the only element of FENCE_BNDS (fence). */
650 FOR_EACH_INSN (insn, ii, FENCE_BNDS (fence))
652 gcc_assert (!was_here_p);
655 gcc_assert (was_here_p && insn != NULL_RTX);
657 /* When in the "middle" of the block, just move this fence
659 bb = BLOCK_FOR_INSN (insn);
660 if (! sel_bb_end_p (insn)
661 || (single_succ_p (bb)
662 && single_pred_p (single_succ (bb))))
666 succ = (sel_bb_end_p (insn)
667 ? sel_bb_head (single_succ (bb))
670 if (INSN_SEQNO (succ) > 0
671 && INSN_SEQNO (succ) <= orig_max_seqno
672 && INSN_SCHED_TIMES (succ) <= 0)
674 FENCE_INSN (fence) = succ;
675 move_fence_to_fences (old_fences, new_fences);
677 if (sched_verbose >= 1)
678 sel_print ("Fence %d continues as %d[%d] (state continue)\n",
679 INSN_UID (insn), INSN_UID (succ), BLOCK_NUM (succ));
684 /* Otherwise copy fence's structures to (possibly) multiple successors. */
685 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
687 int seqno = INSN_SEQNO (succ);
689 if (0 < seqno && seqno <= orig_max_seqno
690 && (pipelining_p || INSN_SCHED_TIMES (succ) <= 0))
692 bool b = (in_same_ebb_p (insn, succ)
693 || in_fallthru_bb_p (insn, succ));
695 if (sched_verbose >= 1)
696 sel_print ("Fence %d continues as %d[%d] (state %s)\n",
697 INSN_UID (insn), INSN_UID (succ),
698 BLOCK_NUM (succ), b ? "continue" : "reset");
701 add_dirty_fence_to_fences (new_fences, succ, fence);
704 /* Mark block of the SUCC as head of the new ebb. */
705 bitmap_set_bit (forced_ebb_heads, BLOCK_NUM (succ));
706 add_clean_fence_to_fences (new_fences, succ, fence);
713 /* Functions to support substitution. */
715 /* Returns whether INSN with dependence status DS is eligible for
716 substitution, i.e. it's a copy operation x := y, and RHS that is
717 moved up through this insn should be substituted. */
719 can_substitute_through_p (insn_t insn, ds_t ds)
721 /* We can substitute only true dependencies. */
722 if ((ds & DEP_OUTPUT)
725 || ! INSN_LHS (insn))
728 /* Now we just need to make sure the INSN_RHS consists of only one
730 if (REG_P (INSN_LHS (insn))
731 && REG_P (INSN_RHS (insn)))
736 /* Substitute all occurences of INSN's destination in EXPR' vinsn with INSN's
737 source (if INSN is eligible for substitution). Returns TRUE if
738 substitution was actually performed, FALSE otherwise. Substitution might
739 be not performed because it's either EXPR' vinsn doesn't contain INSN's
740 destination or the resulting insn is invalid for the target machine.
741 When UNDO is true, perform unsubstitution instead (the difference is in
742 the part of rtx on which validate_replace_rtx is called). */
744 substitute_reg_in_expr (expr_t expr, insn_t insn, bool undo)
748 vinsn_t *vi = &EXPR_VINSN (expr);
749 bool has_rhs = VINSN_RHS (*vi) != NULL;
752 /* Do not try to replace in SET_DEST. Although we'll choose new
753 register for the RHS, we don't want to change RHS' original reg.
754 If the insn is not SET, we may still be able to substitute something
755 in it, and if we're here (don't have deps), it doesn't write INSN's
759 : &PATTERN (VINSN_INSN_RTX (*vi)));
760 old = undo ? INSN_RHS (insn) : INSN_LHS (insn);
762 /* Substitute if INSN has a form of x:=y and LHS(INSN) occurs in *VI. */
763 if (rtx_ok_for_substitution_p (old, *where))
768 /* We should copy these rtxes before substitution. */
769 new_rtx = copy_rtx (undo ? INSN_LHS (insn) : INSN_RHS (insn));
770 new_insn = create_copy_of_insn_rtx (VINSN_INSN_RTX (*vi));
772 /* Where we'll replace.
773 WHERE_REPLACE should point inside NEW_INSN, so INSN_RHS couldn't be
774 used instead of SET_SRC. */
775 where_replace = (has_rhs
776 ? &SET_SRC (PATTERN (new_insn))
777 : &PATTERN (new_insn));
780 = validate_replace_rtx_part_nosimplify (old, new_rtx, where_replace,
783 /* ??? Actually, constrain_operands result depends upon choice of
784 destination register. E.g. if we allow single register to be an rhs,
785 and if we try to move dx=ax(as rhs) through ax=dx, we'll result
786 in invalid insn dx=dx, so we'll loose this rhs here.
787 Just can't come up with significant testcase for this, so just
788 leaving it for now. */
791 change_vinsn_in_expr (expr,
792 create_vinsn_from_insn_rtx (new_insn, false));
794 /* Do not allow clobbering the address register of speculative
796 if ((EXPR_SPEC_DONE_DS (expr) & SPECULATIVE)
797 && bitmap_bit_p (VINSN_REG_USES (EXPR_VINSN (expr)),
798 expr_dest_regno (expr)))
799 EXPR_TARGET_AVAILABLE (expr) = false;
810 /* Helper function for count_occurences_equiv. */
812 count_occurrences_1 (rtx *cur_rtx, void *arg)
814 rtx_search_arg_p p = (rtx_search_arg_p) arg;
816 /* The last param FOR_GCSE is true, because otherwise it performs excessive
820 for the last insn it presumes r33 equivalent to r8, so it changes it to
821 r33. Actually, there's no change, but it spoils debugging. */
822 if (exp_equiv_p (*cur_rtx, p->x, 0, true))
824 /* Bail out if we occupy more than one register. */
826 && HARD_REGISTER_P (*cur_rtx)
827 && hard_regno_nregs[REGNO(*cur_rtx)][GET_MODE (*cur_rtx)] > 1)
835 /* Do not traverse subexprs. */
839 if (GET_CODE (*cur_rtx) == SUBREG
841 && (!REG_P (SUBREG_REG (*cur_rtx))
842 || REGNO (SUBREG_REG (*cur_rtx)) == REGNO (p->x)))
844 /* ??? Do not support substituting regs inside subregs. In that case,
845 simplify_subreg will be called by validate_replace_rtx, and
846 unsubstitution will fail later. */
851 /* Continue search. */
855 /* Return the number of places WHAT appears within WHERE.
856 Bail out when we found a reference occupying several hard registers. */
858 count_occurrences_equiv (rtx what, rtx where)
860 struct rtx_search_arg arg;
865 for_each_rtx (&where, &count_occurrences_1, (void *) &arg);
870 /* Returns TRUE if WHAT is found in WHERE rtx tree. */
872 rtx_ok_for_substitution_p (rtx what, rtx where)
874 return (count_occurrences_equiv (what, where) > 0);
878 /* Functions to support register renaming. */
880 /* Substitute VI's set source with REGNO. Returns newly created pattern
881 that has REGNO as its source. */
883 create_insn_rtx_with_rhs (vinsn_t vi, rtx rhs_rtx)
889 lhs_rtx = copy_rtx (VINSN_LHS (vi));
891 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
892 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
897 /* Returns whether INSN's src can be replaced with register number
898 NEW_SRC_REG. E.g. the following insn is valid for i386:
900 (insn:HI 2205 6585 2207 727 ../../gcc/libiberty/regex.c:3337
901 (set (mem/s:QI (plus:SI (plus:SI (reg/f:SI 7 sp)
902 (reg:SI 0 ax [orig:770 c1 ] [770]))
903 (const_int 288 [0x120])) [0 str S1 A8])
904 (const_int 0 [0x0])) 43 {*movqi_1} (nil)
907 But if we change (const_int 0 [0x0]) to (reg:QI 4 si), it will be invalid
908 because of operand constraints:
910 (define_insn "*movqi_1"
911 [(set (match_operand:QI 0 "nonimmediate_operand" "=q,q ,q ,r,r ,?r,m")
912 (match_operand:QI 1 "general_operand" " q,qn,qm,q,rn,qm,qn")
915 So do constrain_operands here, before choosing NEW_SRC_REG as best
919 replace_src_with_reg_ok_p (insn_t insn, rtx new_src_reg)
921 vinsn_t vi = INSN_VINSN (insn);
922 enum machine_mode mode;
926 gcc_assert (VINSN_SEPARABLE_P (vi));
928 get_dest_and_mode (insn, &dst_loc, &mode);
929 gcc_assert (mode == GET_MODE (new_src_reg));
931 if (REG_P (dst_loc) && REGNO (new_src_reg) == REGNO (dst_loc))
934 /* See whether SET_SRC can be replaced with this register. */
935 validate_change (insn, &SET_SRC (PATTERN (insn)), new_src_reg, 1);
936 res = verify_changes (0);
942 /* Returns whether INSN still be valid after replacing it's DEST with
945 replace_dest_with_reg_ok_p (insn_t insn, rtx new_reg)
947 vinsn_t vi = INSN_VINSN (insn);
950 /* We should deal here only with separable insns. */
951 gcc_assert (VINSN_SEPARABLE_P (vi));
952 gcc_assert (GET_MODE (VINSN_LHS (vi)) == GET_MODE (new_reg));
954 /* See whether SET_DEST can be replaced with this register. */
955 validate_change (insn, &SET_DEST (PATTERN (insn)), new_reg, 1);
956 res = verify_changes (0);
962 /* Create a pattern with rhs of VI and lhs of LHS_RTX. */
964 create_insn_rtx_with_lhs (vinsn_t vi, rtx lhs_rtx)
970 rhs_rtx = copy_rtx (VINSN_RHS (vi));
972 pattern = gen_rtx_SET (VOIDmode, lhs_rtx, rhs_rtx);
973 insn_rtx = create_insn_rtx_from_pattern (pattern, NULL_RTX);
978 /* Substitute lhs in the given expression EXPR for the register with number
979 NEW_REGNO. SET_DEST may be arbitrary rtx, not only register. */
981 replace_dest_with_reg_in_expr (expr_t expr, rtx new_reg)
986 insn_rtx = create_insn_rtx_with_lhs (EXPR_VINSN (expr), new_reg);
987 vinsn = create_vinsn_from_insn_rtx (insn_rtx, false);
989 change_vinsn_in_expr (expr, vinsn);
990 EXPR_WAS_RENAMED (expr) = 1;
991 EXPR_TARGET_AVAILABLE (expr) = 1;
994 /* Returns whether VI writes either one of the USED_REGS registers or,
995 if a register is a hard one, one of the UNAVAILABLE_HARD_REGS registers. */
997 vinsn_writes_one_of_regs_p (vinsn_t vi, regset used_regs,
998 HARD_REG_SET unavailable_hard_regs)
1001 reg_set_iterator rsi;
1003 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_SETS (vi), 0, regno, rsi)
1005 if (REGNO_REG_SET_P (used_regs, regno))
1007 if (HARD_REGISTER_NUM_P (regno)
1008 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1012 EXECUTE_IF_SET_IN_REG_SET (VINSN_REG_CLOBBERS (vi), 0, regno, rsi)
1014 if (REGNO_REG_SET_P (used_regs, regno))
1016 if (HARD_REGISTER_NUM_P (regno)
1017 && TEST_HARD_REG_BIT (unavailable_hard_regs, regno))
1024 /* Returns register class of the output register in INSN.
1025 Returns NO_REGS for call insns because some targets have constraints on
1026 destination register of a call insn.
1028 Code adopted from regrename.c::build_def_use. */
1029 static enum reg_class
1030 get_reg_class (rtx insn)
1034 extract_insn (insn);
1035 if (! constrain_operands (1))
1036 fatal_insn_not_found (insn);
1037 preprocess_constraints ();
1038 alt = which_alternative;
1039 n_ops = recog_data.n_operands;
1041 for (i = 0; i < n_ops; ++i)
1043 int matches = recog_op_alt[i][alt].matches;
1045 recog_op_alt[i][alt].cl = recog_op_alt[matches][alt].cl;
1048 if (asm_noperands (PATTERN (insn)) > 0)
1050 for (i = 0; i < n_ops; i++)
1051 if (recog_data.operand_type[i] == OP_OUT)
1053 rtx *loc = recog_data.operand_loc[i];
1055 enum reg_class cl = recog_op_alt[i][alt].cl;
1058 && REGNO (op) == ORIGINAL_REGNO (op))
1064 else if (!CALL_P (insn))
1066 for (i = 0; i < n_ops + recog_data.n_dups; i++)
1068 int opn = i < n_ops ? i : recog_data.dup_num[i - n_ops];
1069 enum reg_class cl = recog_op_alt[opn][alt].cl;
1071 if (recog_data.operand_type[opn] == OP_OUT ||
1072 recog_data.operand_type[opn] == OP_INOUT)
1078 (insn (set (reg:CCZ 17 flags) (compare:CCZ ...)))
1079 may result in returning NO_REGS, cause flags is written implicitly through
1080 CMP insn, which has no OP_OUT | OP_INOUT operands. */
1084 #ifdef HARD_REGNO_RENAME_OK
1085 /* Calculate HARD_REGNO_RENAME_OK data for REGNO. */
1087 init_hard_regno_rename (int regno)
1091 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], regno);
1093 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1095 /* We are not interested in renaming in other regs. */
1096 if (!TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg))
1099 if (HARD_REGNO_RENAME_OK (regno, cur_reg))
1100 SET_HARD_REG_BIT (sel_hrd.regs_for_rename[regno], cur_reg);
1105 /* A wrapper around HARD_REGNO_RENAME_OK that will look into the hard regs
1108 sel_hard_regno_rename_ok (int from ATTRIBUTE_UNUSED, int to ATTRIBUTE_UNUSED)
1110 #ifdef HARD_REGNO_RENAME_OK
1111 /* Check whether this is all calculated. */
1112 if (TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], from))
1113 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1115 init_hard_regno_rename (from);
1117 return TEST_HARD_REG_BIT (sel_hrd.regs_for_rename[from], to);
1123 /* Calculate set of registers that are capable of holding MODE. */
1125 init_regs_for_mode (enum machine_mode mode)
1129 CLEAR_HARD_REG_SET (sel_hrd.regs_for_mode[mode]);
1130 CLEAR_HARD_REG_SET (sel_hrd.regs_for_call_clobbered[mode]);
1132 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1134 int nregs = hard_regno_nregs[cur_reg][mode];
1137 for (i = nregs - 1; i >= 0; --i)
1138 if (fixed_regs[cur_reg + i]
1139 || global_regs[cur_reg + i]
1140 /* Can't use regs which aren't saved by
1142 || !TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg + i)
1143 /* Can't use regs with non-null REG_BASE_VALUE, because adjusting
1144 it affects aliasing globally and invalidates all AV sets. */
1145 || get_reg_base_value (cur_reg + i)
1146 #ifdef LEAF_REGISTERS
1147 /* We can't use a non-leaf register if we're in a
1149 || (current_function_is_leaf
1150 && !LEAF_REGISTERS[cur_reg + i])
1158 /* See whether it accepts all modes that occur in
1160 if (! HARD_REGNO_MODE_OK (cur_reg, mode))
1163 if (HARD_REGNO_CALL_PART_CLOBBERED (cur_reg, mode))
1164 SET_HARD_REG_BIT (sel_hrd.regs_for_call_clobbered[mode],
1167 /* If the CUR_REG passed all the checks above,
1169 SET_HARD_REG_BIT (sel_hrd.regs_for_mode[mode], cur_reg);
1172 sel_hrd.regs_for_mode_ok[mode] = true;
1175 /* Init all register sets gathered in HRD. */
1177 init_hard_regs_data (void)
1182 CLEAR_HARD_REG_SET (sel_hrd.regs_ever_used);
1183 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1184 if (df_regs_ever_live_p (cur_reg) || call_used_regs[cur_reg])
1185 SET_HARD_REG_BIT (sel_hrd.regs_ever_used, cur_reg);
1187 /* Initialize registers that are valid based on mode when this is
1189 for (cur_mode = 0; cur_mode < NUM_MACHINE_MODES; cur_mode++)
1190 sel_hrd.regs_for_mode_ok[cur_mode] = false;
1192 /* Mark that all HARD_REGNO_RENAME_OK is not calculated. */
1193 for (cur_reg = 0; cur_reg < FIRST_PSEUDO_REGISTER; cur_reg++)
1194 CLEAR_HARD_REG_SET (sel_hrd.regs_for_rename[cur_reg]);
1197 CLEAR_HARD_REG_SET (sel_hrd.stack_regs);
1199 for (cur_reg = FIRST_STACK_REG; cur_reg <= LAST_STACK_REG; cur_reg++)
1200 SET_HARD_REG_BIT (sel_hrd.stack_regs, cur_reg);
1204 /* Mark hardware regs in REG_RENAME_P that are not suitable
1205 for renaming rhs in INSN due to hardware restrictions (register class,
1206 modes compatibility etc). This doesn't affect original insn's dest reg,
1207 if it isn't in USED_REGS. DEF is a definition insn of rhs for which the
1208 destination register is sought. LHS (DEF->ORIG_INSN) may be REG or MEM.
1209 Registers that are in used_regs are always marked in
1210 unavailable_hard_regs as well. */
1213 mark_unavailable_hard_regs (def_t def, struct reg_rename *reg_rename_p,
1214 regset used_regs ATTRIBUTE_UNUSED)
1216 enum machine_mode mode;
1217 enum reg_class cl = NO_REGS;
1219 unsigned cur_reg, regno;
1220 hard_reg_set_iterator hrsi;
1222 gcc_assert (GET_CODE (PATTERN (def->orig_insn)) == SET);
1223 gcc_assert (reg_rename_p);
1225 orig_dest = SET_DEST (PATTERN (def->orig_insn));
1227 /* We have decided not to rename 'mem = something;' insns, as 'something'
1228 is usually a register. */
1229 if (!REG_P (orig_dest))
1232 regno = REGNO (orig_dest);
1234 /* If before reload, don't try to work with pseudos. */
1235 if (!reload_completed && !HARD_REGISTER_NUM_P (regno))
1238 if (reload_completed)
1239 cl = get_reg_class (def->orig_insn);
1241 /* Stop if the original register is one of the fixed_regs, global_regs or
1242 frame pointer, or we could not discover its class. */
1243 if (fixed_regs[regno]
1244 || global_regs[regno]
1245 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1246 || (frame_pointer_needed && regno == HARD_FRAME_POINTER_REGNUM)
1248 || (frame_pointer_needed && regno == FRAME_POINTER_REGNUM)
1250 || (reload_completed && cl == NO_REGS))
1252 SET_HARD_REG_SET (reg_rename_p->unavailable_hard_regs);
1254 /* Give a chance for original register, if it isn't in used_regs. */
1255 if (!def->crosses_call)
1256 CLEAR_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno);
1261 /* If something allocated on stack in this function, mark frame pointer
1262 register unavailable, considering also modes.
1263 FIXME: it is enough to do this once per all original defs. */
1264 if (frame_pointer_needed)
1268 for (i = hard_regno_nregs[FRAME_POINTER_REGNUM][Pmode]; i--;)
1269 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1270 FRAME_POINTER_REGNUM + i);
1272 #if !HARD_FRAME_POINTER_IS_FRAME_POINTER
1273 for (i = hard_regno_nregs[HARD_FRAME_POINTER_REGNUM][Pmode]; i--;)
1274 SET_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1275 HARD_FRAME_POINTER_REGNUM + i);
1280 /* For the stack registers the presence of FIRST_STACK_REG in USED_REGS
1281 is equivalent to as if all stack regs were in this set.
1282 I.e. no stack register can be renamed, and even if it's an original
1283 register here we make sure it won't be lifted over it's previous def
1284 (it's previous def will appear as if it's a FIRST_STACK_REG def.
1285 The HARD_REGNO_RENAME_OK covers other cases in condition below. */
1286 if (IN_RANGE (REGNO (orig_dest), FIRST_STACK_REG, LAST_STACK_REG)
1287 && REGNO_REG_SET_P (used_regs, FIRST_STACK_REG))
1288 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1289 sel_hrd.stack_regs);
1292 /* If there's a call on this path, make regs from call_used_reg_set
1294 if (def->crosses_call)
1295 IOR_HARD_REG_SET (reg_rename_p->unavailable_hard_regs,
1298 /* Stop here before reload: we need FRAME_REGS, STACK_REGS, and crosses_call,
1299 but not register classes. */
1300 if (!reload_completed)
1303 /* Leave regs as 'available' only from the current
1305 COPY_HARD_REG_SET (reg_rename_p->available_for_renaming,
1306 reg_class_contents[cl]);
1308 mode = GET_MODE (orig_dest);
1310 /* Leave only registers available for this mode. */
1311 if (!sel_hrd.regs_for_mode_ok[mode])
1312 init_regs_for_mode (mode);
1313 AND_HARD_REG_SET (reg_rename_p->available_for_renaming,
1314 sel_hrd.regs_for_mode[mode]);
1316 /* Exclude registers that are partially call clobbered. */
1317 if (def->crosses_call
1318 && ! HARD_REGNO_CALL_PART_CLOBBERED (regno, mode))
1319 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1320 sel_hrd.regs_for_call_clobbered[mode]);
1322 /* Leave only those that are ok to rename. */
1323 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1329 nregs = hard_regno_nregs[cur_reg][mode];
1330 gcc_assert (nregs > 0);
1332 for (i = nregs - 1; i >= 0; --i)
1333 if (! sel_hard_regno_rename_ok (regno + i, cur_reg + i))
1337 CLEAR_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1341 AND_COMPL_HARD_REG_SET (reg_rename_p->available_for_renaming,
1342 reg_rename_p->unavailable_hard_regs);
1344 /* Regno is always ok from the renaming part of view, but it really
1345 could be in *unavailable_hard_regs already, so set it here instead
1347 SET_HARD_REG_BIT (reg_rename_p->available_for_renaming, regno);
1350 /* reg_rename_tick[REG1] > reg_rename_tick[REG2] if REG1 was chosen as the
1351 best register more recently than REG2. */
1352 static int reg_rename_tick[FIRST_PSEUDO_REGISTER];
1354 /* Indicates the number of times renaming happened before the current one. */
1355 static int reg_rename_this_tick;
1357 /* Choose the register among free, that is suitable for storing
1360 ORIGINAL_INSNS is the list of insns where the operation (rhs)
1361 originally appears. There could be multiple original operations
1362 for single rhs since we moving it up and merging along different
1365 Some code is adapted from regrename.c (regrename_optimize).
1366 If original register is available, function returns it.
1367 Otherwise it performs the checks, so the new register should
1368 comply with the following:
1369 - it should not violate any live ranges (such registers are in
1370 REG_RENAME_P->available_for_renaming set);
1371 - it should not be in the HARD_REGS_USED regset;
1372 - it should be in the class compatible with original uses;
1373 - it should not be clobbered through reference with different mode;
1374 - if we're in the leaf function, then the new register should
1375 not be in the LEAF_REGISTERS;
1378 If several registers meet the conditions, the register with smallest
1379 tick is returned to achieve more even register allocation.
1381 If original register seems to be ok, we set *IS_ORIG_REG_P_PTR to true.
1383 If no register satisfies the above conditions, NULL_RTX is returned. */
1385 choose_best_reg_1 (HARD_REG_SET hard_regs_used,
1386 struct reg_rename *reg_rename_p,
1387 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1391 enum machine_mode mode = VOIDmode;
1392 unsigned regno, i, n;
1393 hard_reg_set_iterator hrsi;
1394 def_list_iterator di;
1397 /* If original register is available, return it. */
1398 *is_orig_reg_p_ptr = true;
1400 FOR_EACH_DEF (def, di, original_insns)
1402 rtx orig_dest = SET_DEST (PATTERN (def->orig_insn));
1404 gcc_assert (REG_P (orig_dest));
1406 /* Check that all original operations have the same mode.
1407 This is done for the next loop; if we'd return from this
1408 loop, we'd check only part of them, but in this case
1409 it doesn't matter. */
1410 if (mode == VOIDmode)
1411 mode = GET_MODE (orig_dest);
1412 gcc_assert (mode == GET_MODE (orig_dest));
1414 regno = REGNO (orig_dest);
1415 for (i = 0, n = hard_regno_nregs[regno][mode]; i < n; i++)
1416 if (TEST_HARD_REG_BIT (hard_regs_used, regno + i))
1419 /* All hard registers are available. */
1422 gcc_assert (mode != VOIDmode);
1424 /* Hard registers should not be shared. */
1425 return gen_rtx_REG (mode, regno);
1429 *is_orig_reg_p_ptr = false;
1432 /* Among all available regs choose the register that was
1433 allocated earliest. */
1434 EXECUTE_IF_SET_IN_HARD_REG_SET (reg_rename_p->available_for_renaming,
1436 if (! TEST_HARD_REG_BIT (hard_regs_used, cur_reg))
1438 /* Check that all hard regs for mode are available. */
1439 for (i = 1, n = hard_regno_nregs[cur_reg][mode]; i < n; i++)
1440 if (TEST_HARD_REG_BIT (hard_regs_used, cur_reg + i)
1441 || !TEST_HARD_REG_BIT (reg_rename_p->available_for_renaming,
1448 /* All hard registers are available. */
1449 if (best_new_reg < 0
1450 || reg_rename_tick[cur_reg] < reg_rename_tick[best_new_reg])
1452 best_new_reg = cur_reg;
1454 /* Return immediately when we know there's no better reg. */
1455 if (! reg_rename_tick[best_new_reg])
1460 if (best_new_reg >= 0)
1462 /* Use the check from the above loop. */
1463 gcc_assert (mode != VOIDmode);
1464 return gen_rtx_REG (mode, best_new_reg);
1470 /* A wrapper around choose_best_reg_1 () to verify that we make correct
1471 assumptions about available registers in the function. */
1473 choose_best_reg (HARD_REG_SET hard_regs_used, struct reg_rename *reg_rename_p,
1474 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1476 rtx best_reg = choose_best_reg_1 (hard_regs_used, reg_rename_p,
1477 original_insns, is_orig_reg_p_ptr);
1479 /* FIXME loop over hard_regno_nregs here. */
1480 gcc_assert (best_reg == NULL_RTX
1481 || TEST_HARD_REG_BIT (sel_hrd.regs_ever_used, REGNO (best_reg)));
1486 /* Choose the pseudo register for storing rhs value. As this is supposed
1487 to work before reload, we return either the original register or make
1488 the new one. The parameters are the same that in choose_nest_reg_1
1489 functions, except that USED_REGS may contain pseudos.
1490 If we work with hard regs, check also REG_RENAME_P->UNAVAILABLE_HARD_REGS.
1492 TODO: take into account register pressure while doing this. Up to this
1493 moment, this function would never return NULL for pseudos, but we should
1494 not rely on this. */
1496 choose_best_pseudo_reg (regset used_regs,
1497 struct reg_rename *reg_rename_p,
1498 def_list_t original_insns, bool *is_orig_reg_p_ptr)
1500 def_list_iterator i;
1502 enum machine_mode mode = VOIDmode;
1503 bool bad_hard_regs = false;
1505 /* We should not use this after reload. */
1506 gcc_assert (!reload_completed);
1508 /* If original register is available, return it. */
1509 *is_orig_reg_p_ptr = true;
1511 FOR_EACH_DEF (def, i, original_insns)
1513 rtx dest = SET_DEST (PATTERN (def->orig_insn));
1516 gcc_assert (REG_P (dest));
1518 /* Check that all original operations have the same mode. */
1519 if (mode == VOIDmode)
1520 mode = GET_MODE (dest);
1522 gcc_assert (mode == GET_MODE (dest));
1523 orig_regno = REGNO (dest);
1525 if (!REGNO_REG_SET_P (used_regs, orig_regno))
1527 if (orig_regno < FIRST_PSEUDO_REGISTER)
1529 gcc_assert (df_regs_ever_live_p (orig_regno));
1531 /* For hard registers, we have to check hardware imposed
1532 limitations (frame/stack registers, calls crossed). */
1533 if (!TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs,
1536 /* Don't let register cross a call if it doesn't already
1537 cross one. This condition is written in accordance with
1538 that in sched-deps.c sched_analyze_reg(). */
1539 if (!reg_rename_p->crosses_call
1540 || REG_N_CALLS_CROSSED (orig_regno) > 0)
1541 return gen_rtx_REG (mode, orig_regno);
1544 bad_hard_regs = true;
1551 *is_orig_reg_p_ptr = false;
1553 /* We had some original hard registers that couldn't be used.
1554 Those were likely special. Don't try to create a pseudo. */
1558 /* We haven't found a register from original operations. Get a new one.
1559 FIXME: control register pressure somehow. */
1561 rtx new_reg = gen_reg_rtx (mode);
1563 gcc_assert (mode != VOIDmode);
1565 max_regno = max_reg_num ();
1566 maybe_extend_reg_info_p ();
1567 REG_N_CALLS_CROSSED (REGNO (new_reg)) = reg_rename_p->crosses_call ? 1 : 0;
1573 /* True when target of EXPR is available due to EXPR_TARGET_AVAILABLE,
1574 USED_REGS and REG_RENAME_P->UNAVAILABLE_HARD_REGS. */
1576 verify_target_availability (expr_t expr, regset used_regs,
1577 struct reg_rename *reg_rename_p)
1579 unsigned n, i, regno;
1580 enum machine_mode mode;
1581 bool target_available, live_available, hard_available;
1583 if (!REG_P (EXPR_LHS (expr)) || EXPR_TARGET_AVAILABLE (expr) < 0)
1586 regno = expr_dest_regno (expr);
1587 mode = GET_MODE (EXPR_LHS (expr));
1588 target_available = EXPR_TARGET_AVAILABLE (expr) == 1;
1589 n = reload_completed ? hard_regno_nregs[regno][mode] : 1;
1591 live_available = hard_available = true;
1592 for (i = 0; i < n; i++)
1594 if (bitmap_bit_p (used_regs, regno + i))
1595 live_available = false;
1596 if (TEST_HARD_REG_BIT (reg_rename_p->unavailable_hard_regs, regno + i))
1597 hard_available = false;
1600 /* When target is not available, it may be due to hard register
1601 restrictions, e.g. crosses calls, so we check hard_available too. */
1602 if (target_available)
1603 gcc_assert (live_available);
1605 /* Check only if we haven't scheduled something on the previous fence,
1606 cause due to MAX_SOFTWARE_LOOKAHEAD_WINDOW_SIZE issues
1607 and having more than one fence, we may end having targ_un in a block
1608 in which successors target register is actually available.
1610 The last condition handles the case when a dependence from a call insn
1611 was created in sched-deps.c for insns with destination registers that
1612 never crossed a call before, but do cross one after our code motion.
1614 FIXME: in the latter case, we just uselessly called find_used_regs,
1615 because we can't move this expression with any other register
1617 gcc_assert (scheduled_something_on_previous_fence || !live_available
1619 || (!reload_completed && reg_rename_p->crosses_call
1620 && REG_N_CALLS_CROSSED (regno) == 0));
1623 /* Collect unavailable registers due to liveness for EXPR from BNDS
1624 into USED_REGS. Save additional information about available
1625 registers and unavailable due to hardware restriction registers
1626 into REG_RENAME_P structure. Save original insns into ORIGINAL_INSNS
1629 collect_unavailable_regs_from_bnds (expr_t expr, blist_t bnds, regset used_regs,
1630 struct reg_rename *reg_rename_p,
1631 def_list_t *original_insns)
1633 for (; bnds; bnds = BLIST_NEXT (bnds))
1636 av_set_t orig_ops = NULL;
1637 bnd_t bnd = BLIST_BND (bnds);
1639 /* If the chosen best expr doesn't belong to current boundary,
1641 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr)))
1644 /* Put in ORIG_OPS all exprs from this boundary that became
1646 orig_ops = find_sequential_best_exprs (bnd, expr, false);
1648 /* Compute used regs and OR it into the USED_REGS. */
1649 res = find_used_regs (BND_TO (bnd), orig_ops, used_regs,
1650 reg_rename_p, original_insns);
1652 /* FIXME: the assert is true until we'd have several boundaries. */
1654 av_set_clear (&orig_ops);
1658 /* Return TRUE if it is possible to replace LHSes of ORIG_INSNS with BEST_REG.
1659 If BEST_REG is valid, replace LHS of EXPR with it. */
1661 try_replace_dest_reg (ilist_t orig_insns, rtx best_reg, expr_t expr)
1663 /* Try whether we'll be able to generate the insn
1664 'dest := best_reg' at the place of the original operation. */
1665 for (; orig_insns; orig_insns = ILIST_NEXT (orig_insns))
1667 insn_t orig_insn = DEF_LIST_DEF (orig_insns)->orig_insn;
1669 gcc_assert (EXPR_SEPARABLE_P (INSN_EXPR (orig_insn)));
1671 if (REGNO (best_reg) != REGNO (INSN_LHS (orig_insn))
1672 && (! replace_src_with_reg_ok_p (orig_insn, best_reg)
1673 || ! replace_dest_with_reg_ok_p (orig_insn, best_reg)))
1677 /* Make sure that EXPR has the right destination
1679 if (expr_dest_regno (expr) != REGNO (best_reg))
1680 replace_dest_with_reg_in_expr (expr, best_reg);
1682 EXPR_TARGET_AVAILABLE (expr) = 1;
1687 /* Select and assign best register to EXPR searching from BNDS.
1688 Set *IS_ORIG_REG_P to TRUE if original register was selected.
1689 Return FALSE if no register can be chosen, which could happen when:
1690 * EXPR_SEPARABLE_P is true but we were unable to find suitable register;
1691 * EXPR_SEPARABLE_P is false but the insn sets/clobbers one of the registers
1692 that are used on the moving path. */
1694 find_best_reg_for_expr (expr_t expr, blist_t bnds, bool *is_orig_reg_p)
1696 static struct reg_rename reg_rename_data;
1699 def_list_t original_insns = NULL;
1702 *is_orig_reg_p = false;
1704 /* Don't bother to do anything if this insn doesn't set any registers. */
1705 if (bitmap_empty_p (VINSN_REG_SETS (EXPR_VINSN (expr)))
1706 && bitmap_empty_p (VINSN_REG_CLOBBERS (EXPR_VINSN (expr))))
1709 used_regs = get_clear_regset_from_pool ();
1710 CLEAR_HARD_REG_SET (reg_rename_data.unavailable_hard_regs);
1712 collect_unavailable_regs_from_bnds (expr, bnds, used_regs, ®_rename_data,
1715 #ifdef ENABLE_CHECKING
1716 /* If after reload, make sure we're working with hard regs here. */
1717 if (reload_completed)
1719 reg_set_iterator rsi;
1722 EXECUTE_IF_SET_IN_REG_SET (used_regs, FIRST_PSEUDO_REGISTER, i, rsi)
1727 if (EXPR_SEPARABLE_P (expr))
1729 rtx best_reg = NULL_RTX;
1730 /* Check that we have computed availability of a target register
1732 verify_target_availability (expr, used_regs, ®_rename_data);
1734 /* Turn everything in hard regs after reload. */
1735 if (reload_completed)
1737 HARD_REG_SET hard_regs_used;
1738 REG_SET_TO_HARD_REG_SET (hard_regs_used, used_regs);
1740 /* Join hard registers unavailable due to register class
1741 restrictions and live range intersection. */
1742 IOR_HARD_REG_SET (hard_regs_used,
1743 reg_rename_data.unavailable_hard_regs);
1745 best_reg = choose_best_reg (hard_regs_used, ®_rename_data,
1746 original_insns, is_orig_reg_p);
1749 best_reg = choose_best_pseudo_reg (used_regs, ®_rename_data,
1750 original_insns, is_orig_reg_p);
1754 else if (*is_orig_reg_p)
1756 /* In case of unification BEST_REG may be different from EXPR's LHS
1757 when EXPR's LHS is unavailable, and there is another LHS among
1759 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1763 /* Forbid renaming of low-cost insns. */
1764 if (sel_vinsn_cost (EXPR_VINSN (expr)) < 2)
1767 reg_ok = try_replace_dest_reg (original_insns, best_reg, expr);
1772 /* If !EXPR_SCHEDULE_AS_RHS (EXPR), just make sure INSN doesn't set
1773 any of the HARD_REGS_USED set. */
1774 if (vinsn_writes_one_of_regs_p (EXPR_VINSN (expr), used_regs,
1775 reg_rename_data.unavailable_hard_regs))
1778 gcc_assert (EXPR_TARGET_AVAILABLE (expr) <= 0);
1783 gcc_assert (EXPR_TARGET_AVAILABLE (expr) != 0);
1787 ilist_clear (&original_insns);
1788 return_regset_to_pool (used_regs);
1794 /* Return true if dependence described by DS can be overcomed. */
1796 can_speculate_dep_p (ds_t ds)
1798 if (spec_info == NULL)
1801 /* Leave only speculative data. */
1808 /* FIXME: make sched-deps.c produce only those non-hard dependencies,
1809 that we can overcome. */
1810 ds_t spec_mask = spec_info->mask;
1812 if ((ds & spec_mask) != ds)
1816 if (ds_weak (ds) < spec_info->data_weakness_cutoff)
1822 /* Get a speculation check instruction.
1823 C_EXPR is a speculative expression,
1824 CHECK_DS describes speculations that should be checked,
1825 ORIG_INSN is the original non-speculative insn in the stream. */
1827 create_speculation_check (expr_t c_expr, ds_t check_ds, insn_t orig_insn)
1832 basic_block recovery_block;
1835 /* Create a recovery block if target is going to emit branchy check, or if
1836 ORIG_INSN was speculative already. */
1837 if (targetm.sched.needs_block_p (check_ds)
1838 || EXPR_SPEC_DONE_DS (INSN_EXPR (orig_insn)) != 0)
1840 recovery_block = sel_create_recovery_block (orig_insn);
1841 label = BB_HEAD (recovery_block);
1845 recovery_block = NULL;
1849 /* Get pattern of the check. */
1850 check_pattern = targetm.sched.gen_spec_check (EXPR_INSN_RTX (c_expr), label,
1853 gcc_assert (check_pattern != NULL);
1856 insn_rtx = create_insn_rtx_from_pattern (check_pattern, label);
1858 insn = sel_gen_insn_from_rtx_after (insn_rtx, INSN_EXPR (orig_insn),
1859 INSN_SEQNO (orig_insn), orig_insn);
1861 /* Make check to be non-speculative. */
1862 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
1863 INSN_SPEC_CHECKED_DS (insn) = check_ds;
1865 /* Decrease priority of check by difference of load/check instruction
1867 EXPR_PRIORITY (INSN_EXPR (insn)) -= (sel_vinsn_cost (INSN_VINSN (orig_insn))
1868 - sel_vinsn_cost (INSN_VINSN (insn)));
1870 /* Emit copy of original insn (though with replaced target register,
1871 if needed) to the recovery block. */
1872 if (recovery_block != NULL)
1876 twin_rtx = copy_rtx (PATTERN (EXPR_INSN_RTX (c_expr)));
1877 twin_rtx = create_insn_rtx_from_pattern (twin_rtx, NULL_RTX);
1878 sel_gen_recovery_insn_from_rtx_after (twin_rtx,
1879 INSN_EXPR (orig_insn),
1881 bb_note (recovery_block));
1884 /* If we've generated a data speculation check, make sure
1885 that all the bookkeeping instruction we'll create during
1886 this move_op () will allocate an ALAT entry so that the
1888 In case of control speculation we must convert C_EXPR to control
1889 speculative mode, because failing to do so will bring us an exception
1890 thrown by the non-control-speculative load. */
1891 check_ds = ds_get_max_dep_weak (check_ds);
1892 speculate_expr (c_expr, check_ds);
1897 /* True when INSN is a "regN = regN" copy. */
1899 identical_copy_p (rtx insn)
1903 pat = PATTERN (insn);
1905 if (GET_CODE (pat) != SET)
1908 lhs = SET_DEST (pat);
1912 rhs = SET_SRC (pat);
1916 return REGNO (lhs) == REGNO (rhs);
1919 /* Undo all transformations on *AV_PTR that were done when
1920 moving through INSN. */
1922 undo_transformations (av_set_t *av_ptr, rtx insn)
1924 av_set_iterator av_iter;
1926 av_set_t new_set = NULL;
1928 /* First, kill any EXPR that uses registers set by an insn. This is
1929 required for correctness. */
1930 FOR_EACH_EXPR_1 (expr, av_iter, av_ptr)
1931 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (expr))
1932 && bitmap_intersect_p (INSN_REG_SETS (insn),
1933 VINSN_REG_USES (EXPR_VINSN (expr)))
1934 /* When an insn looks like 'r1 = r1', we could substitute through
1935 it, but the above condition will still hold. This happened with
1936 gcc.c-torture/execute/961125-1.c. */
1937 && !identical_copy_p (insn))
1939 if (sched_verbose >= 6)
1940 sel_print ("Expr %d removed due to use/set conflict\n",
1941 INSN_UID (EXPR_INSN_RTX (expr)));
1942 av_set_iter_remove (&av_iter);
1945 /* Undo transformations looking at the history vector. */
1946 FOR_EACH_EXPR (expr, av_iter, *av_ptr)
1948 int index = find_in_history_vect (EXPR_HISTORY_OF_CHANGES (expr),
1949 insn, EXPR_VINSN (expr), true);
1953 expr_history_def *phist;
1955 phist = VEC_index (expr_history_def,
1956 EXPR_HISTORY_OF_CHANGES (expr),
1959 switch (phist->type)
1961 case TRANS_SPECULATION:
1963 ds_t old_ds, new_ds;
1965 /* Compute the difference between old and new speculative
1966 statuses: that's what we need to check.
1967 Earlier we used to assert that the status will really
1968 change. This no longer works because only the probability
1969 bits in the status may have changed during compute_av_set,
1970 and in the case of merging different probabilities of the
1971 same speculative status along different paths we do not
1972 record this in the history vector. */
1973 old_ds = phist->spec_ds;
1974 new_ds = EXPR_SPEC_DONE_DS (expr);
1976 old_ds &= SPECULATIVE;
1977 new_ds &= SPECULATIVE;
1980 EXPR_SPEC_TO_CHECK_DS (expr) |= new_ds;
1983 case TRANS_SUBSTITUTION:
1985 expr_def _tmp_expr, *tmp_expr = &_tmp_expr;
1989 new_vi = phist->old_expr_vinsn;
1991 gcc_assert (VINSN_SEPARABLE_P (new_vi)
1992 == EXPR_SEPARABLE_P (expr));
1993 copy_expr (tmp_expr, expr);
1995 if (vinsn_equal_p (phist->new_expr_vinsn,
1996 EXPR_VINSN (tmp_expr)))
1997 change_vinsn_in_expr (tmp_expr, new_vi);
1999 /* This happens when we're unsubstituting on a bookkeeping
2000 copy, which was in turn substituted. The history is wrong
2001 in this case. Do it the hard way. */
2002 add = substitute_reg_in_expr (tmp_expr, insn, true);
2004 av_set_add (&new_set, tmp_expr);
2005 clear_expr (tmp_expr);
2015 av_set_union_and_clear (av_ptr, &new_set, NULL);
2019 /* Moveup_* helpers for code motion and computing av sets. */
2021 /* Propagates EXPR inside an insn group through THROUGH_INSN.
2022 The difference from the below function is that only substitution is
2024 static enum MOVEUP_EXPR_CODE
2025 moveup_expr_inside_insn_group (expr_t expr, insn_t through_insn)
2027 vinsn_t vi = EXPR_VINSN (expr);
2031 /* Do this only inside insn group. */
2032 gcc_assert (INSN_SCHED_CYCLE (through_insn) > 0);
2034 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2036 return MOVEUP_EXPR_SAME;
2038 /* Substitution is the possible choice in this case. */
2039 if (has_dep_p[DEPS_IN_RHS])
2041 /* Can't substitute UNIQUE VINSNs. */
2042 gcc_assert (!VINSN_UNIQUE_P (vi));
2044 if (can_substitute_through_p (through_insn,
2045 has_dep_p[DEPS_IN_RHS])
2046 && substitute_reg_in_expr (expr, through_insn, false))
2048 EXPR_WAS_SUBSTITUTED (expr) = true;
2049 return MOVEUP_EXPR_CHANGED;
2052 /* Don't care about this, as even true dependencies may be allowed
2053 in an insn group. */
2054 return MOVEUP_EXPR_SAME;
2057 /* This can catch output dependencies in COND_EXECs. */
2058 if (has_dep_p[DEPS_IN_INSN])
2059 return MOVEUP_EXPR_NULL;
2061 /* This is either an output or an anti dependence, which usually have
2062 a zero latency. Allow this here, if we'd be wrong, tick_check_p
2064 gcc_assert (has_dep_p[DEPS_IN_LHS]);
2065 return MOVEUP_EXPR_AS_RHS;
2068 /* True when a trapping EXPR cannot be moved through THROUGH_INSN. */
2069 #define CANT_MOVE_TRAPPING(expr, through_insn) \
2070 (VINSN_MAY_TRAP_P (EXPR_VINSN (expr)) \
2071 && !sel_insn_has_single_succ_p ((through_insn), SUCCS_ALL) \
2072 && !sel_insn_is_speculation_check (through_insn))
2074 /* True when a conflict on a target register was found during moveup_expr. */
2075 static bool was_target_conflict = false;
2077 /* Return true when moving a debug INSN across THROUGH_INSN will
2078 create a bookkeeping block. We don't want to create such blocks,
2079 for they would cause codegen differences between compilations with
2080 and without debug info. */
2083 moving_insn_creates_bookkeeping_block_p (insn_t insn,
2084 insn_t through_insn)
2086 basic_block bbi, bbt;
2088 edge_iterator ei1, ei2;
2090 if (!bookkeeping_can_be_created_if_moved_through_p (through_insn))
2092 if (sched_verbose >= 9)
2093 sel_print ("no bookkeeping required: ");
2097 bbi = BLOCK_FOR_INSN (insn);
2099 if (EDGE_COUNT (bbi->preds) == 1)
2101 if (sched_verbose >= 9)
2102 sel_print ("only one pred edge: ");
2106 bbt = BLOCK_FOR_INSN (through_insn);
2108 FOR_EACH_EDGE (e1, ei1, bbt->succs)
2110 FOR_EACH_EDGE (e2, ei2, bbi->preds)
2112 if (find_block_for_bookkeeping (e1, e2, TRUE))
2114 if (sched_verbose >= 9)
2115 sel_print ("found existing block: ");
2121 if (sched_verbose >= 9)
2122 sel_print ("would create bookkeeping block: ");
2127 /* Modifies EXPR so it can be moved through the THROUGH_INSN,
2128 performing necessary transformations. Record the type of transformation
2129 made in PTRANS_TYPE, when it is not NULL. When INSIDE_INSN_GROUP,
2130 permit all dependencies except true ones, and try to remove those
2131 too via forward substitution. All cases when a non-eliminable
2132 non-zero cost dependency exists inside an insn group will be fixed
2133 in tick_check_p instead. */
2134 static enum MOVEUP_EXPR_CODE
2135 moveup_expr (expr_t expr, insn_t through_insn, bool inside_insn_group,
2136 enum local_trans_type *ptrans_type)
2138 vinsn_t vi = EXPR_VINSN (expr);
2139 insn_t insn = VINSN_INSN_RTX (vi);
2140 bool was_changed = false;
2141 bool as_rhs = false;
2145 /* ??? We use dependencies of non-debug insns on debug insns to
2146 indicate that the debug insns need to be reset if the non-debug
2147 insn is pulled ahead of it. It's hard to figure out how to
2148 introduce such a notion in sel-sched, but it already fails to
2149 support debug insns in other ways, so we just go ahead and
2150 let the deug insns go corrupt for now. */
2151 if (DEBUG_INSN_P (through_insn) && !DEBUG_INSN_P (insn))
2152 return MOVEUP_EXPR_SAME;
2154 /* When inside_insn_group, delegate to the helper. */
2155 if (inside_insn_group)
2156 return moveup_expr_inside_insn_group (expr, through_insn);
2158 /* Deal with unique insns and control dependencies. */
2159 if (VINSN_UNIQUE_P (vi))
2161 /* We can move jumps without side-effects or jumps that are
2162 mutually exclusive with instruction THROUGH_INSN (all in cases
2163 dependencies allow to do so and jump is not speculative). */
2164 if (control_flow_insn_p (insn))
2166 basic_block fallthru_bb;
2168 /* Do not move checks and do not move jumps through other
2170 if (control_flow_insn_p (through_insn)
2171 || sel_insn_is_speculation_check (insn))
2172 return MOVEUP_EXPR_NULL;
2174 /* Don't move jumps through CFG joins. */
2175 if (bookkeeping_can_be_created_if_moved_through_p (through_insn))
2176 return MOVEUP_EXPR_NULL;
2178 /* The jump should have a clear fallthru block, and
2179 this block should be in the current region. */
2180 if ((fallthru_bb = fallthru_bb_of_jump (insn)) == NULL
2181 || ! in_current_region_p (fallthru_bb))
2182 return MOVEUP_EXPR_NULL;
2184 /* And it should be mutually exclusive with through_insn. */
2185 if (! sched_insns_conditions_mutex_p (insn, through_insn)
2186 && ! DEBUG_INSN_P (through_insn))
2187 return MOVEUP_EXPR_NULL;
2190 /* Don't move what we can't move. */
2191 if (EXPR_CANT_MOVE (expr)
2192 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn))
2193 return MOVEUP_EXPR_NULL;
2195 /* Don't move SCHED_GROUP instruction through anything.
2196 If we don't force this, then it will be possible to start
2197 scheduling a sched_group before all its dependencies are
2199 ??? Haifa deals with this issue by delaying the SCHED_GROUP
2200 as late as possible through rank_for_schedule. */
2201 if (SCHED_GROUP_P (insn))
2202 return MOVEUP_EXPR_NULL;
2205 gcc_assert (!control_flow_insn_p (insn));
2207 /* Don't move debug insns if this would require bookkeeping. */
2208 if (DEBUG_INSN_P (insn)
2209 && BLOCK_FOR_INSN (through_insn) != BLOCK_FOR_INSN (insn)
2210 && moving_insn_creates_bookkeeping_block_p (insn, through_insn))
2211 return MOVEUP_EXPR_NULL;
2213 /* Deal with data dependencies. */
2214 was_target_conflict = false;
2215 full_ds = has_dependence_p (expr, through_insn, &has_dep_p);
2218 if (!CANT_MOVE_TRAPPING (expr, through_insn))
2219 return MOVEUP_EXPR_SAME;
2223 /* We can move UNIQUE insn up only as a whole and unchanged,
2224 so it shouldn't have any dependencies. */
2225 if (VINSN_UNIQUE_P (vi))
2226 return MOVEUP_EXPR_NULL;
2229 if (full_ds != 0 && can_speculate_dep_p (full_ds))
2233 res = speculate_expr (expr, full_ds);
2236 /* Speculation was successful. */
2238 was_changed = (res > 0);
2240 was_target_conflict = true;
2242 *ptrans_type = TRANS_SPECULATION;
2243 sel_clear_has_dependence ();
2247 if (has_dep_p[DEPS_IN_INSN])
2248 /* We have some dependency that cannot be discarded. */
2249 return MOVEUP_EXPR_NULL;
2251 if (has_dep_p[DEPS_IN_LHS])
2253 /* Only separable insns can be moved up with the new register.
2254 Anyways, we should mark that the original register is
2256 if (!enable_schedule_as_rhs_p || !EXPR_SEPARABLE_P (expr))
2257 return MOVEUP_EXPR_NULL;
2259 EXPR_TARGET_AVAILABLE (expr) = false;
2260 was_target_conflict = true;
2264 /* At this point we have either separable insns, that will be lifted
2265 up only as RHSes, or non-separable insns with no dependency in lhs.
2266 If dependency is in RHS, then try to perform substitution and move up
2273 In Ex.1 y*2 can be substituted for x*2 and the whole operation can be
2274 moved above y=x assignment as z=x*2.
2276 In Ex.2 y*2 also can be substituted for x*2, but only the right hand
2277 side can be moved because of the output dependency. The operation was
2278 cropped to its rhs above. */
2279 if (has_dep_p[DEPS_IN_RHS])
2281 ds_t *rhs_dsp = &has_dep_p[DEPS_IN_RHS];
2283 /* Can't substitute UNIQUE VINSNs. */
2284 gcc_assert (!VINSN_UNIQUE_P (vi));
2286 if (can_speculate_dep_p (*rhs_dsp))
2290 res = speculate_expr (expr, *rhs_dsp);
2293 /* Speculation was successful. */
2295 was_changed = (res > 0);
2297 was_target_conflict = true;
2299 *ptrans_type = TRANS_SPECULATION;
2302 return MOVEUP_EXPR_NULL;
2304 else if (can_substitute_through_p (through_insn,
2306 && substitute_reg_in_expr (expr, through_insn, false))
2308 /* ??? We cannot perform substitution AND speculation on the same
2310 gcc_assert (!was_changed);
2313 *ptrans_type = TRANS_SUBSTITUTION;
2314 EXPR_WAS_SUBSTITUTED (expr) = true;
2317 return MOVEUP_EXPR_NULL;
2320 /* Don't move trapping insns through jumps.
2321 This check should be at the end to give a chance to control speculation
2322 to perform its duties. */
2323 if (CANT_MOVE_TRAPPING (expr, through_insn))
2324 return MOVEUP_EXPR_NULL;
2327 ? MOVEUP_EXPR_CHANGED
2329 ? MOVEUP_EXPR_AS_RHS
2330 : MOVEUP_EXPR_SAME));
2333 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2334 if successful. When INSIDE_INSN_GROUP, also try ignore dependencies
2335 that can exist within a parallel group. Write to RES the resulting
2336 code for moveup_expr. */
2338 try_bitmap_cache (expr_t expr, insn_t insn,
2339 bool inside_insn_group,
2340 enum MOVEUP_EXPR_CODE *res)
2342 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2344 /* First check whether we've analyzed this situation already. */
2345 if (bitmap_bit_p (INSN_ANALYZED_DEPS (insn), expr_uid))
2347 if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2349 if (sched_verbose >= 6)
2350 sel_print ("removed (cached)\n");
2351 *res = MOVEUP_EXPR_NULL;
2356 if (sched_verbose >= 6)
2357 sel_print ("unchanged (cached)\n");
2358 *res = MOVEUP_EXPR_SAME;
2362 else if (bitmap_bit_p (INSN_FOUND_DEPS (insn), expr_uid))
2364 if (inside_insn_group)
2366 if (sched_verbose >= 6)
2367 sel_print ("unchanged (as RHS, cached, inside insn group)\n");
2368 *res = MOVEUP_EXPR_SAME;
2373 EXPR_TARGET_AVAILABLE (expr) = false;
2375 /* This is the only case when propagation result can change over time,
2376 as we can dynamically switch off scheduling as RHS. In this case,
2377 just check the flag to reach the correct decision. */
2378 if (enable_schedule_as_rhs_p)
2380 if (sched_verbose >= 6)
2381 sel_print ("unchanged (as RHS, cached)\n");
2382 *res = MOVEUP_EXPR_AS_RHS;
2387 if (sched_verbose >= 6)
2388 sel_print ("removed (cached as RHS, but renaming"
2389 " is now disabled)\n");
2390 *res = MOVEUP_EXPR_NULL;
2398 /* Try to look at bitmap caches for EXPR and INSN pair, return true
2399 if successful. Write to RES the resulting code for moveup_expr. */
2401 try_transformation_cache (expr_t expr, insn_t insn,
2402 enum MOVEUP_EXPR_CODE *res)
2404 struct transformed_insns *pti
2405 = (struct transformed_insns *)
2406 htab_find_with_hash (INSN_TRANSFORMED_INSNS (insn),
2408 VINSN_HASH_RTX (EXPR_VINSN (expr)));
2411 /* This EXPR was already moved through this insn and was
2412 changed as a result. Fetch the proper data from
2414 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2415 INSN_UID (insn), pti->type,
2416 pti->vinsn_old, pti->vinsn_new,
2417 EXPR_SPEC_DONE_DS (expr));
2419 if (INSN_IN_STREAM_P (VINSN_INSN_RTX (pti->vinsn_new)))
2420 pti->vinsn_new = vinsn_copy (pti->vinsn_new, true);
2421 change_vinsn_in_expr (expr, pti->vinsn_new);
2422 if (pti->was_target_conflict)
2423 EXPR_TARGET_AVAILABLE (expr) = false;
2424 if (pti->type == TRANS_SPECULATION)
2426 EXPR_SPEC_DONE_DS (expr) = pti->ds;
2427 EXPR_NEEDS_SPEC_CHECK_P (expr) |= pti->needs_check;
2430 if (sched_verbose >= 6)
2432 sel_print ("changed (cached): ");
2437 *res = MOVEUP_EXPR_CHANGED;
2444 /* Update bitmap caches on INSN with result RES of propagating EXPR. */
2446 update_bitmap_cache (expr_t expr, insn_t insn, bool inside_insn_group,
2447 enum MOVEUP_EXPR_CODE res)
2449 int expr_uid = INSN_UID (EXPR_INSN_RTX (expr));
2451 /* Do not cache result of propagating jumps through an insn group,
2452 as it is always true, which is not useful outside the group. */
2453 if (inside_insn_group)
2456 if (res == MOVEUP_EXPR_NULL)
2458 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2459 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2461 else if (res == MOVEUP_EXPR_SAME)
2463 bitmap_set_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2464 bitmap_clear_bit (INSN_FOUND_DEPS (insn), expr_uid);
2466 else if (res == MOVEUP_EXPR_AS_RHS)
2468 bitmap_clear_bit (INSN_ANALYZED_DEPS (insn), expr_uid);
2469 bitmap_set_bit (INSN_FOUND_DEPS (insn), expr_uid);
2475 /* Update hashtable on INSN with changed EXPR, old EXPR_OLD_VINSN
2476 and transformation type TRANS_TYPE. */
2478 update_transformation_cache (expr_t expr, insn_t insn,
2479 bool inside_insn_group,
2480 enum local_trans_type trans_type,
2481 vinsn_t expr_old_vinsn)
2483 struct transformed_insns *pti;
2485 if (inside_insn_group)
2488 pti = XNEW (struct transformed_insns);
2489 pti->vinsn_old = expr_old_vinsn;
2490 pti->vinsn_new = EXPR_VINSN (expr);
2491 pti->type = trans_type;
2492 pti->was_target_conflict = was_target_conflict;
2493 pti->ds = EXPR_SPEC_DONE_DS (expr);
2494 pti->needs_check = EXPR_NEEDS_SPEC_CHECK_P (expr);
2495 vinsn_attach (pti->vinsn_old);
2496 vinsn_attach (pti->vinsn_new);
2497 *((struct transformed_insns **)
2498 htab_find_slot_with_hash (INSN_TRANSFORMED_INSNS (insn),
2499 pti, VINSN_HASH_RTX (expr_old_vinsn),
2503 /* Same as moveup_expr, but first looks up the result of
2504 transformation in caches. */
2505 static enum MOVEUP_EXPR_CODE
2506 moveup_expr_cached (expr_t expr, insn_t insn, bool inside_insn_group)
2508 enum MOVEUP_EXPR_CODE res;
2509 bool got_answer = false;
2511 if (sched_verbose >= 6)
2513 sel_print ("Moving ");
2515 sel_print (" through %d: ", INSN_UID (insn));
2518 if (DEBUG_INSN_P (EXPR_INSN_RTX (expr))
2519 && (sel_bb_head (BLOCK_FOR_INSN (EXPR_INSN_RTX (expr)))
2520 == EXPR_INSN_RTX (expr)))
2521 /* Don't use cached information for debug insns that are heads of
2523 else if (try_bitmap_cache (expr, insn, inside_insn_group, &res))
2524 /* When inside insn group, we do not want remove stores conflicting
2525 with previosly issued loads. */
2526 got_answer = ! inside_insn_group || res != MOVEUP_EXPR_NULL;
2527 else if (try_transformation_cache (expr, insn, &res))
2532 /* Invoke moveup_expr and record the results. */
2533 vinsn_t expr_old_vinsn = EXPR_VINSN (expr);
2534 ds_t expr_old_spec_ds = EXPR_SPEC_DONE_DS (expr);
2535 int expr_uid = INSN_UID (VINSN_INSN_RTX (expr_old_vinsn));
2536 bool unique_p = VINSN_UNIQUE_P (expr_old_vinsn);
2537 enum local_trans_type trans_type = TRANS_SUBSTITUTION;
2539 /* ??? Invent something better than this. We can't allow old_vinsn
2540 to go, we need it for the history vector. */
2541 vinsn_attach (expr_old_vinsn);
2543 res = moveup_expr (expr, insn, inside_insn_group,
2547 case MOVEUP_EXPR_NULL:
2548 update_bitmap_cache (expr, insn, inside_insn_group, res);
2549 if (sched_verbose >= 6)
2550 sel_print ("removed\n");
2553 case MOVEUP_EXPR_SAME:
2554 update_bitmap_cache (expr, insn, inside_insn_group, res);
2555 if (sched_verbose >= 6)
2556 sel_print ("unchanged\n");
2559 case MOVEUP_EXPR_AS_RHS:
2560 gcc_assert (!unique_p || inside_insn_group);
2561 update_bitmap_cache (expr, insn, inside_insn_group, res);
2562 if (sched_verbose >= 6)
2563 sel_print ("unchanged (as RHS)\n");
2566 case MOVEUP_EXPR_CHANGED:
2567 gcc_assert (INSN_UID (EXPR_INSN_RTX (expr)) != expr_uid
2568 || EXPR_SPEC_DONE_DS (expr) != expr_old_spec_ds);
2569 insert_in_history_vect (&EXPR_HISTORY_OF_CHANGES (expr),
2570 INSN_UID (insn), trans_type,
2571 expr_old_vinsn, EXPR_VINSN (expr),
2573 update_transformation_cache (expr, insn, inside_insn_group,
2574 trans_type, expr_old_vinsn);
2575 if (sched_verbose >= 6)
2577 sel_print ("changed: ");
2586 vinsn_detach (expr_old_vinsn);
2592 /* Moves an av set AVP up through INSN, performing necessary
2595 moveup_set_expr (av_set_t *avp, insn_t insn, bool inside_insn_group)
2600 FOR_EACH_EXPR_1 (expr, i, avp)
2603 switch (moveup_expr_cached (expr, insn, inside_insn_group))
2605 case MOVEUP_EXPR_SAME:
2606 case MOVEUP_EXPR_AS_RHS:
2609 case MOVEUP_EXPR_NULL:
2610 av_set_iter_remove (&i);
2613 case MOVEUP_EXPR_CHANGED:
2614 expr = merge_with_other_exprs (avp, &i, expr);
2623 /* Moves AVP set along PATH. */
2625 moveup_set_inside_insn_group (av_set_t *avp, ilist_t path)
2629 if (sched_verbose >= 6)
2630 sel_print ("Moving expressions up in the insn group...\n");
2633 last_cycle = INSN_SCHED_CYCLE (ILIST_INSN (path));
2635 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2637 moveup_set_expr (avp, ILIST_INSN (path), true);
2638 path = ILIST_NEXT (path);
2642 /* Returns true if after moving EXPR along PATH it equals to EXPR_VLIW. */
2644 equal_after_moveup_path_p (expr_t expr, ilist_t path, expr_t expr_vliw)
2646 expr_def _tmp, *tmp = &_tmp;
2650 copy_expr_onside (tmp, expr);
2651 last_cycle = path ? INSN_SCHED_CYCLE (ILIST_INSN (path)) : 0;
2654 && INSN_SCHED_CYCLE (ILIST_INSN (path)) == last_cycle)
2656 res = (moveup_expr_cached (tmp, ILIST_INSN (path), true)
2657 != MOVEUP_EXPR_NULL);
2658 path = ILIST_NEXT (path);
2663 vinsn_t tmp_vinsn = EXPR_VINSN (tmp);
2664 vinsn_t expr_vliw_vinsn = EXPR_VINSN (expr_vliw);
2666 if (tmp_vinsn != expr_vliw_vinsn)
2667 res = vinsn_equal_p (tmp_vinsn, expr_vliw_vinsn);
2675 /* Functions that compute av and lv sets. */
2677 /* Returns true if INSN is not a downward continuation of the given path P in
2678 the current stage. */
2680 is_ineligible_successor (insn_t insn, ilist_t p)
2684 /* Check if insn is not deleted. */
2685 if (PREV_INSN (insn) && NEXT_INSN (PREV_INSN (insn)) != insn)
2687 else if (NEXT_INSN (insn) && PREV_INSN (NEXT_INSN (insn)) != insn)
2690 /* If it's the first insn visited, then the successor is ok. */
2694 prev_insn = ILIST_INSN (p);
2696 if (/* a backward edge. */
2697 INSN_SEQNO (insn) < INSN_SEQNO (prev_insn)
2698 /* is already visited. */
2699 || (INSN_SEQNO (insn) == INSN_SEQNO (prev_insn)
2700 && (ilist_is_in_p (p, insn)
2701 /* We can reach another fence here and still seqno of insn
2702 would be equal to seqno of prev_insn. This is possible
2703 when prev_insn is a previously created bookkeeping copy.
2704 In that case it'd get a seqno of insn. Thus, check here
2705 whether insn is in current fence too. */
2706 || IN_CURRENT_FENCE_P (insn)))
2707 /* Was already scheduled on this round. */
2708 || (INSN_SEQNO (insn) > INSN_SEQNO (prev_insn)
2709 && IN_CURRENT_FENCE_P (insn))
2710 /* An insn from another fence could also be
2711 scheduled earlier even if this insn is not in
2712 a fence list right now. Check INSN_SCHED_CYCLE instead. */
2714 && INSN_SCHED_TIMES (insn) > 0))
2720 /* Computes the av_set below the last bb insn INSN, doing all the 'dirty work'
2721 of handling multiple successors and properly merging its av_sets. P is
2722 the current path traversed. WS is the size of lookahead window.
2723 Return the av set computed. */
2725 compute_av_set_at_bb_end (insn_t insn, ilist_t p, int ws)
2727 struct succs_info *sinfo;
2728 av_set_t expr_in_all_succ_branches = NULL;
2730 insn_t succ, zero_succ = NULL;
2731 av_set_t av1 = NULL;
2733 gcc_assert (sel_bb_end_p (insn));
2735 /* Find different kind of successors needed for correct computing of
2736 SPEC and TARGET_AVAILABLE attributes. */
2737 sinfo = compute_succs_info (insn, SUCCS_NORMAL);
2740 if (sched_verbose >= 6)
2742 sel_print ("successors of bb end (%d): ", INSN_UID (insn));
2743 dump_insn_vector (sinfo->succs_ok);
2745 if (sinfo->succs_ok_n != sinfo->all_succs_n)
2746 sel_print ("real successors num: %d\n", sinfo->all_succs_n);
2749 /* Add insn to to the tail of current path. */
2750 ilist_add (&p, insn);
2752 FOR_EACH_VEC_ELT (rtx, sinfo->succs_ok, is, succ)
2756 /* We will edit SUCC_SET and EXPR_SPEC field of its elements. */
2757 succ_set = compute_av_set_inside_bb (succ, p, ws, true);
2759 av_set_split_usefulness (succ_set,
2760 VEC_index (int, sinfo->probs_ok, is),
2763 if (sinfo->all_succs_n > 1)
2765 /* Find EXPR'es that came from *all* successors and save them
2766 into expr_in_all_succ_branches. This set will be used later
2767 for calculating speculation attributes of EXPR'es. */
2770 expr_in_all_succ_branches = av_set_copy (succ_set);
2772 /* Remember the first successor for later. */
2780 FOR_EACH_EXPR_1 (expr, i, &expr_in_all_succ_branches)
2781 if (!av_set_is_in_p (succ_set, EXPR_VINSN (expr)))
2782 av_set_iter_remove (&i);
2786 /* Union the av_sets. Check liveness restrictions on target registers
2787 in special case of two successors. */
2788 if (sinfo->succs_ok_n == 2 && is == 1)
2790 basic_block bb0 = BLOCK_FOR_INSN (zero_succ);
2791 basic_block bb1 = BLOCK_FOR_INSN (succ);
2793 gcc_assert (BB_LV_SET_VALID_P (bb0) && BB_LV_SET_VALID_P (bb1));
2794 av_set_union_and_live (&av1, &succ_set,
2800 av_set_union_and_clear (&av1, &succ_set, insn);
2803 /* Check liveness restrictions via hard way when there are more than
2805 if (sinfo->succs_ok_n > 2)
2806 FOR_EACH_VEC_ELT (rtx, sinfo->succs_ok, is, succ)
2808 basic_block succ_bb = BLOCK_FOR_INSN (succ);
2810 gcc_assert (BB_LV_SET_VALID_P (succ_bb));
2811 mark_unavailable_targets (av1, BB_AV_SET (succ_bb),
2812 BB_LV_SET (succ_bb));
2815 /* Finally, check liveness restrictions on paths leaving the region. */
2816 if (sinfo->all_succs_n > sinfo->succs_ok_n)
2817 FOR_EACH_VEC_ELT (rtx, sinfo->succs_other, is, succ)
2818 mark_unavailable_targets
2819 (av1, NULL, BB_LV_SET (BLOCK_FOR_INSN (succ)));
2821 if (sinfo->all_succs_n > 1)
2826 /* Increase the spec attribute of all EXPR'es that didn't come
2827 from all successors. */
2828 FOR_EACH_EXPR (expr, i, av1)
2829 if (!av_set_is_in_p (expr_in_all_succ_branches, EXPR_VINSN (expr)))
2832 av_set_clear (&expr_in_all_succ_branches);
2834 /* Do not move conditional branches through other
2835 conditional branches. So, remove all conditional
2836 branches from av_set if current operator is a conditional
2838 av_set_substract_cond_branches (&av1);
2842 free_succs_info (sinfo);
2844 if (sched_verbose >= 6)
2846 sel_print ("av_succs (%d): ", INSN_UID (insn));
2854 /* This function computes av_set for the FIRST_INSN by dragging valid
2855 av_set through all basic block insns either from the end of basic block
2856 (computed using compute_av_set_at_bb_end) or from the insn on which
2857 MAX_WS was exceeded. It uses compute_av_set_at_bb_end to compute av_set
2858 below the basic block and handling conditional branches.
2859 FIRST_INSN - the basic block head, P - path consisting of the insns
2860 traversed on the way to the FIRST_INSN (the path is sparse, only bb heads
2861 and bb ends are added to the path), WS - current window size,
2862 NEED_COPY_P - true if we'll make a copy of av_set before returning it. */
2864 compute_av_set_inside_bb (insn_t first_insn, ilist_t p, int ws,
2869 insn_t bb_end = sel_bb_end (BLOCK_FOR_INSN (first_insn));
2870 insn_t after_bb_end = NEXT_INSN (bb_end);
2873 basic_block cur_bb = BLOCK_FOR_INSN (first_insn);
2875 /* Return NULL if insn is not on the legitimate downward path. */
2876 if (is_ineligible_successor (first_insn, p))
2878 if (sched_verbose >= 6)
2879 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (first_insn));
2884 /* If insn already has valid av(insn) computed, just return it. */
2885 if (AV_SET_VALID_P (first_insn))
2889 if (sel_bb_head_p (first_insn))
2890 av_set = BB_AV_SET (BLOCK_FOR_INSN (first_insn));
2894 if (sched_verbose >= 6)
2896 sel_print ("Insn %d has a valid av set: ", INSN_UID (first_insn));
2897 dump_av_set (av_set);
2901 return need_copy_p ? av_set_copy (av_set) : av_set;
2904 ilist_add (&p, first_insn);
2906 /* As the result after this loop have completed, in LAST_INSN we'll
2907 have the insn which has valid av_set to start backward computation
2908 from: it either will be NULL because on it the window size was exceeded
2909 or other valid av_set as returned by compute_av_set for the last insn
2910 of the basic block. */
2911 for (last_insn = first_insn; last_insn != after_bb_end;
2912 last_insn = NEXT_INSN (last_insn))
2914 /* We may encounter valid av_set not only on bb_head, but also on
2915 those insns on which previously MAX_WS was exceeded. */
2916 if (AV_SET_VALID_P (last_insn))
2918 if (sched_verbose >= 6)
2919 sel_print ("Insn %d has a valid empty av set\n", INSN_UID (last_insn));
2923 /* The special case: the last insn of the BB may be an
2924 ineligible_successor due to its SEQ_NO that was set on
2925 it as a bookkeeping. */
2926 if (last_insn != first_insn
2927 && is_ineligible_successor (last_insn, p))
2929 if (sched_verbose >= 6)
2930 sel_print ("Insn %d is ineligible_successor\n", INSN_UID (last_insn));
2934 if (DEBUG_INSN_P (last_insn))
2937 if (end_ws > max_ws)
2939 /* We can reach max lookahead size at bb_header, so clean av_set
2941 INSN_WS_LEVEL (last_insn) = global_level;
2943 if (sched_verbose >= 6)
2944 sel_print ("Insn %d is beyond the software lookahead window size\n",
2945 INSN_UID (last_insn));
2952 /* Get the valid av_set into AV above the LAST_INSN to start backward
2953 computation from. It either will be empty av_set or av_set computed from
2954 the successors on the last insn of the current bb. */
2955 if (last_insn != after_bb_end)
2959 /* This is needed only to obtain av_sets that are identical to
2960 those computed by the old compute_av_set version. */
2961 if (last_insn == first_insn && !INSN_NOP_P (last_insn))
2962 av_set_add (&av, INSN_EXPR (last_insn));
2965 /* END_WS is always already increased by 1 if LAST_INSN == AFTER_BB_END. */
2966 av = compute_av_set_at_bb_end (bb_end, p, end_ws);
2968 /* Compute av_set in AV starting from below the LAST_INSN up to
2969 location above the FIRST_INSN. */
2970 for (cur_insn = PREV_INSN (last_insn); cur_insn != PREV_INSN (first_insn);
2971 cur_insn = PREV_INSN (cur_insn))
2972 if (!INSN_NOP_P (cur_insn))
2976 moveup_set_expr (&av, cur_insn, false);
2978 /* If the expression for CUR_INSN is already in the set,
2979 replace it by the new one. */
2980 expr = av_set_lookup (av, INSN_VINSN (cur_insn));
2984 copy_expr (expr, INSN_EXPR (cur_insn));
2987 av_set_add (&av, INSN_EXPR (cur_insn));
2990 /* Clear stale bb_av_set. */
2991 if (sel_bb_head_p (first_insn))
2993 av_set_clear (&BB_AV_SET (cur_bb));
2994 BB_AV_SET (cur_bb) = need_copy_p ? av_set_copy (av) : av;
2995 BB_AV_LEVEL (cur_bb) = global_level;
2998 if (sched_verbose >= 6)
3000 sel_print ("Computed av set for insn %d: ", INSN_UID (first_insn));
3009 /* Compute av set before INSN.
3010 INSN - the current operation (actual rtx INSN)
3011 P - the current path, which is list of insns visited so far
3012 WS - software lookahead window size.
3013 UNIQUE_P - TRUE, if returned av_set will be changed, hence
3014 if we want to save computed av_set in s_i_d, we should make a copy of it.
3016 In the resulting set we will have only expressions that don't have delay
3017 stalls and nonsubstitutable dependences. */
3019 compute_av_set (insn_t insn, ilist_t p, int ws, bool unique_p)
3021 return compute_av_set_inside_bb (insn, p, ws, unique_p);
3024 /* Propagate a liveness set LV through INSN. */
3026 propagate_lv_set (regset lv, insn_t insn)
3028 gcc_assert (INSN_P (insn));
3030 if (INSN_NOP_P (insn))
3033 df_simulate_one_insn_backwards (BLOCK_FOR_INSN (insn), insn, lv);
3036 /* Return livness set at the end of BB. */
3038 compute_live_after_bb (basic_block bb)
3042 regset lv = get_clear_regset_from_pool ();
3044 gcc_assert (!ignore_first);
3046 FOR_EACH_EDGE (e, ei, bb->succs)
3047 if (sel_bb_empty_p (e->dest))
3049 if (! BB_LV_SET_VALID_P (e->dest))
3052 gcc_assert (BB_LV_SET (e->dest) == NULL);
3053 BB_LV_SET (e->dest) = compute_live_after_bb (e->dest);
3054 BB_LV_SET_VALID_P (e->dest) = true;
3056 IOR_REG_SET (lv, BB_LV_SET (e->dest));
3059 IOR_REG_SET (lv, compute_live (sel_bb_head (e->dest)));
3064 /* Compute the set of all live registers at the point before INSN and save
3065 it at INSN if INSN is bb header. */
3067 compute_live (insn_t insn)
3069 basic_block bb = BLOCK_FOR_INSN (insn);
3073 /* Return the valid set if we're already on it. */
3078 if (sel_bb_head_p (insn) && BB_LV_SET_VALID_P (bb))
3079 src = BB_LV_SET (bb);
3082 gcc_assert (in_current_region_p (bb));
3083 if (INSN_LIVE_VALID_P (insn))
3084 src = INSN_LIVE (insn);
3089 lv = get_regset_from_pool ();
3090 COPY_REG_SET (lv, src);
3092 if (sel_bb_head_p (insn) && ! BB_LV_SET_VALID_P (bb))
3094 COPY_REG_SET (BB_LV_SET (bb), lv);
3095 BB_LV_SET_VALID_P (bb) = true;
3098 return_regset_to_pool (lv);
3103 /* We've skipped the wrong lv_set. Don't skip the right one. */
3104 ignore_first = false;
3105 gcc_assert (in_current_region_p (bb));
3107 /* Find a valid LV set in this block or below, if needed.
3108 Start searching from the next insn: either ignore_first is true, or
3109 INSN doesn't have a correct live set. */
3110 temp = NEXT_INSN (insn);
3111 final = NEXT_INSN (BB_END (bb));
3112 while (temp != final && ! INSN_LIVE_VALID_P (temp))
3113 temp = NEXT_INSN (temp);
3116 lv = compute_live_after_bb (bb);
3117 temp = PREV_INSN (temp);
3121 lv = get_regset_from_pool ();
3122 COPY_REG_SET (lv, INSN_LIVE (temp));
3125 /* Put correct lv sets on the insns which have bad sets. */
3126 final = PREV_INSN (insn);
3127 while (temp != final)
3129 propagate_lv_set (lv, temp);
3130 COPY_REG_SET (INSN_LIVE (temp), lv);
3131 INSN_LIVE_VALID_P (temp) = true;
3132 temp = PREV_INSN (temp);
3135 /* Also put it in a BB. */
3136 if (sel_bb_head_p (insn))
3138 basic_block bb = BLOCK_FOR_INSN (insn);
3140 COPY_REG_SET (BB_LV_SET (bb), lv);
3141 BB_LV_SET_VALID_P (bb) = true;
3144 /* We return LV to the pool, but will not clear it there. Thus we can
3145 legimatelly use LV till the next use of regset_pool_get (). */
3146 return_regset_to_pool (lv);
3150 /* Update liveness sets for INSN. */
3152 update_liveness_on_insn (rtx insn)
3154 ignore_first = true;
3155 compute_live (insn);
3158 /* Compute liveness below INSN and write it into REGS. */
3160 compute_live_below_insn (rtx insn, regset regs)
3165 FOR_EACH_SUCC_1 (succ, si, insn, SUCCS_ALL)
3166 IOR_REG_SET (regs, compute_live (succ));
3169 /* Update the data gathered in av and lv sets starting from INSN. */
3171 update_data_sets (rtx insn)
3173 update_liveness_on_insn (insn);
3174 if (sel_bb_head_p (insn))
3176 gcc_assert (AV_LEVEL (insn) != 0);
3177 BB_AV_LEVEL (BLOCK_FOR_INSN (insn)) = -1;
3178 compute_av_set (insn, NULL, 0, 0);
3183 /* Helper for move_op () and find_used_regs ().
3184 Return speculation type for which a check should be created on the place
3185 of INSN. EXPR is one of the original ops we are searching for. */
3187 get_spec_check_type_for_insn (insn_t insn, expr_t expr)
3190 ds_t already_checked_ds = EXPR_SPEC_DONE_DS (INSN_EXPR (insn));
3192 to_check_ds = EXPR_SPEC_TO_CHECK_DS (expr);
3194 if (targetm.sched.get_insn_checked_ds)
3195 already_checked_ds |= targetm.sched.get_insn_checked_ds (insn);
3197 if (spec_info != NULL
3198 && (spec_info->flags & SEL_SCHED_SPEC_DONT_CHECK_CONTROL))
3199 already_checked_ds |= BEGIN_CONTROL;
3201 already_checked_ds = ds_get_speculation_types (already_checked_ds);
3203 to_check_ds &= ~already_checked_ds;
3208 /* Find the set of registers that are unavailable for storing expres
3209 while moving ORIG_OPS up on the path starting from INSN due to
3210 liveness (USED_REGS) or hardware restrictions (REG_RENAME_P).
3212 All the original operations found during the traversal are saved in the
3213 ORIGINAL_INSNS list.
3215 REG_RENAME_P denotes the set of hardware registers that
3216 can not be used with renaming due to the register class restrictions,
3217 mode restrictions and other (the register we'll choose should be
3218 compatible class with the original uses, shouldn't be in call_used_regs,
3219 should be HARD_REGNO_RENAME_OK etc).
3221 Returns TRUE if we've found all original insns, FALSE otherwise.
3223 This function utilizes code_motion_path_driver (formerly find_used_regs_1)
3224 to traverse the code motion paths. This helper function finds registers
3225 that are not available for storing expres while moving ORIG_OPS up on the
3226 path starting from INSN. A register considered as used on the moving path,
3227 if one of the following conditions is not satisfied:
3229 (1) a register not set or read on any path from xi to an instance of
3230 the original operation,
3231 (2) not among the live registers of the point immediately following the
3232 first original operation on a given downward path, except for the
3233 original target register of the operation,
3234 (3) not live on the other path of any conditional branch that is passed
3235 by the operation, in case original operations are not present on
3236 both paths of the conditional branch.
3238 All the original operations found during the traversal are saved in the
3239 ORIGINAL_INSNS list.
3241 REG_RENAME_P->CROSSES_CALL is true, if there is a call insn on the path
3242 from INSN to original insn. In this case CALL_USED_REG_SET will be added
3243 to unavailable hard regs at the point original operation is found. */
3246 find_used_regs (insn_t insn, av_set_t orig_ops, regset used_regs,
3247 struct reg_rename *reg_rename_p, def_list_t *original_insns)
3249 def_list_iterator i;
3252 bool needs_spec_check_p = false;
3254 av_set_iterator expr_iter;
3255 struct fur_static_params sparams;
3256 struct cmpd_local_params lparams;
3258 /* We haven't visited any blocks yet. */
3259 bitmap_clear (code_motion_visited_blocks);
3261 /* Init parameters for code_motion_path_driver. */
3262 sparams.crosses_call = false;
3263 sparams.original_insns = original_insns;
3264 sparams.used_regs = used_regs;
3266 /* Set the appropriate hooks and data. */
3267 code_motion_path_driver_info = &fur_hooks;
3269 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
3271 reg_rename_p->crosses_call |= sparams.crosses_call;
3273 gcc_assert (res == 1);
3274 gcc_assert (original_insns && *original_insns);
3276 /* ??? We calculate whether an expression needs a check when computing
3277 av sets. This information is not as precise as it could be due to
3278 merging this bit in merge_expr. We can do better in find_used_regs,
3279 but we want to avoid multiple traversals of the same code motion
3281 FOR_EACH_EXPR (expr, expr_iter, orig_ops)
3282 needs_spec_check_p |= EXPR_NEEDS_SPEC_CHECK_P (expr);
3284 /* Mark hardware regs in REG_RENAME_P that are not suitable
3285 for renaming expr in INSN due to hardware restrictions (register class,
3286 modes compatibility etc). */
3287 FOR_EACH_DEF (def, i, *original_insns)
3289 vinsn_t vinsn = INSN_VINSN (def->orig_insn);
3291 if (VINSN_SEPARABLE_P (vinsn))
3292 mark_unavailable_hard_regs (def, reg_rename_p, used_regs);
3294 /* Do not allow clobbering of ld.[sa] address in case some of the
3295 original operations need a check. */
3296 if (needs_spec_check_p)
3297 IOR_REG_SET (used_regs, VINSN_REG_USES (vinsn));
3304 /* Functions to choose the best insn from available ones. */
3306 /* Adjusts the priority for EXPR using the backend *_adjust_priority hook. */
3308 sel_target_adjust_priority (expr_t expr)
3310 int priority = EXPR_PRIORITY (expr);
3313 if (targetm.sched.adjust_priority)
3314 new_priority = targetm.sched.adjust_priority (EXPR_INSN_RTX (expr), priority);
3316 new_priority = priority;
3318 /* If the priority has changed, adjust EXPR_PRIORITY_ADJ accordingly. */
3319 EXPR_PRIORITY_ADJ (expr) = new_priority - EXPR_PRIORITY (expr);
3321 gcc_assert (EXPR_PRIORITY_ADJ (expr) >= 0);
3323 if (sched_verbose >= 4)
3324 sel_print ("sel_target_adjust_priority: insn %d, %d+%d = %d.\n",
3325 INSN_UID (EXPR_INSN_RTX (expr)), EXPR_PRIORITY (expr),
3326 EXPR_PRIORITY_ADJ (expr), new_priority);
3328 return new_priority;
3331 /* Rank two available exprs for schedule. Never return 0 here. */
3333 sel_rank_for_schedule (const void *x, const void *y)
3335 expr_t tmp = *(const expr_t *) y;
3336 expr_t tmp2 = *(const expr_t *) x;
3337 insn_t tmp_insn, tmp2_insn;
3338 vinsn_t tmp_vinsn, tmp2_vinsn;
3341 tmp_vinsn = EXPR_VINSN (tmp);
3342 tmp2_vinsn = EXPR_VINSN (tmp2);
3343 tmp_insn = EXPR_INSN_RTX (tmp);
3344 tmp2_insn = EXPR_INSN_RTX (tmp2);
3346 /* Schedule debug insns as early as possible. */
3347 if (DEBUG_INSN_P (tmp_insn) && !DEBUG_INSN_P (tmp2_insn))
3349 else if (DEBUG_INSN_P (tmp2_insn))
3352 /* Prefer SCHED_GROUP_P insns to any others. */
3353 if (SCHED_GROUP_P (tmp_insn) != SCHED_GROUP_P (tmp2_insn))
3355 if (VINSN_UNIQUE_P (tmp_vinsn) && VINSN_UNIQUE_P (tmp2_vinsn))
3356 return SCHED_GROUP_P (tmp2_insn) ? 1 : -1;
3358 /* Now uniqueness means SCHED_GROUP_P is set, because schedule groups
3359 cannot be cloned. */
3360 if (VINSN_UNIQUE_P (tmp2_vinsn))
3365 /* Discourage scheduling of speculative checks. */
3366 val = (sel_insn_is_speculation_check (tmp_insn)
3367 - sel_insn_is_speculation_check (tmp2_insn));
3371 /* Prefer not scheduled insn over scheduled one. */
3372 if (EXPR_SCHED_TIMES (tmp) > 0 || EXPR_SCHED_TIMES (tmp2) > 0)
3374 val = EXPR_SCHED_TIMES (tmp) - EXPR_SCHED_TIMES (tmp2);
3379 /* Prefer jump over non-jump instruction. */
3380 if (control_flow_insn_p (tmp_insn) && !control_flow_insn_p (tmp2_insn))
3382 else if (control_flow_insn_p (tmp2_insn) && !control_flow_insn_p (tmp_insn))
3385 /* Prefer an expr with greater priority. */
3386 if (EXPR_USEFULNESS (tmp) != 0 && EXPR_USEFULNESS (tmp2) != 0)
3388 int p2 = EXPR_PRIORITY (tmp2) + EXPR_PRIORITY_ADJ (tmp2),
3389 p1 = EXPR_PRIORITY (tmp) + EXPR_PRIORITY_ADJ (tmp);
3391 val = p2 * EXPR_USEFULNESS (tmp2) - p1 * EXPR_USEFULNESS (tmp);
3394 val = EXPR_PRIORITY (tmp2) - EXPR_PRIORITY (tmp)
3395 + EXPR_PRIORITY_ADJ (tmp2) - EXPR_PRIORITY_ADJ (tmp);
3399 if (spec_info != NULL && spec_info->mask != 0)
3400 /* This code was taken from haifa-sched.c: rank_for_schedule (). */
3406 ds1 = EXPR_SPEC_DONE_DS (tmp);
3408 dw1 = ds_weak (ds1);
3412 ds2 = EXPR_SPEC_DONE_DS (tmp2);
3414 dw2 = ds_weak (ds2);
3419 if (dw > (NO_DEP_WEAK / 8) || dw < -(NO_DEP_WEAK / 8))
3423 /* Prefer an old insn to a bookkeeping insn. */
3424 if (INSN_UID (tmp_insn) < first_emitted_uid
3425 && INSN_UID (tmp2_insn) >= first_emitted_uid)
3427 if (INSN_UID (tmp_insn) >= first_emitted_uid
3428 && INSN_UID (tmp2_insn) < first_emitted_uid)
3431 /* Prefer an insn with smaller UID, as a last resort.
3432 We can't safely use INSN_LUID as it is defined only for those insns
3433 that are in the stream. */
3434 return INSN_UID (tmp_insn) - INSN_UID (tmp2_insn);
3437 /* Filter out expressions from av set pointed to by AV_PTR
3438 that are pipelined too many times. */
3440 process_pipelined_exprs (av_set_t *av_ptr)
3445 /* Don't pipeline already pipelined code as that would increase
3446 number of unnecessary register moves. */
3447 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3449 if (EXPR_SCHED_TIMES (expr)
3450 >= PARAM_VALUE (PARAM_SELSCHED_MAX_SCHED_TIMES))
3451 av_set_iter_remove (&si);
3455 /* Filter speculative insns from AV_PTR if we don't want them. */
3457 process_spec_exprs (av_set_t *av_ptr)
3459 bool try_data_p = true;
3460 bool try_control_p = true;
3464 if (spec_info == NULL)
3467 /* Scan *AV_PTR to find out if we want to consider speculative
3468 instructions for scheduling. */
3469 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3473 ds = EXPR_SPEC_DONE_DS (expr);
3475 /* The probability of a success is too low - don't speculate. */
3476 if ((ds & SPECULATIVE)
3477 && (ds_weak (ds) < spec_info->data_weakness_cutoff
3478 || EXPR_USEFULNESS (expr) < spec_info->control_weakness_cutoff
3479 || (pipelining_p && false
3481 && (ds & CONTROL_SPEC))))
3483 av_set_iter_remove (&si);
3487 if ((spec_info->flags & PREFER_NON_DATA_SPEC)
3488 && !(ds & BEGIN_DATA))
3491 if ((spec_info->flags & PREFER_NON_CONTROL_SPEC)
3492 && !(ds & BEGIN_CONTROL))
3493 try_control_p = false;
3496 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3500 ds = EXPR_SPEC_DONE_DS (expr);
3502 if (ds & SPECULATIVE)
3504 if ((ds & BEGIN_DATA) && !try_data_p)
3505 /* We don't want any data speculative instructions right
3507 av_set_iter_remove (&si);
3509 if ((ds & BEGIN_CONTROL) && !try_control_p)
3510 /* We don't want any control speculative instructions right
3512 av_set_iter_remove (&si);
3517 /* Search for any use-like insns in AV_PTR and decide on scheduling
3518 them. Return one when found, and NULL otherwise.
3519 Note that we check here whether a USE could be scheduled to avoid
3520 an infinite loop later. */
3522 process_use_exprs (av_set_t *av_ptr)
3526 bool uses_present_p = false;
3527 bool try_uses_p = true;
3529 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3531 /* This will also initialize INSN_CODE for later use. */
3532 if (recog_memoized (EXPR_INSN_RTX (expr)) < 0)
3534 /* If we have a USE in *AV_PTR that was not scheduled yet,
3535 do so because it will do good only. */
3536 if (EXPR_SCHED_TIMES (expr) <= 0)
3538 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3541 av_set_iter_remove (&si);
3545 gcc_assert (pipelining_p);
3547 uses_present_p = true;
3556 /* If we don't want to schedule any USEs right now and we have some
3557 in *AV_PTR, remove them, else just return the first one found. */
3560 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3561 if (INSN_CODE (EXPR_INSN_RTX (expr)) < 0)
3562 av_set_iter_remove (&si);
3566 FOR_EACH_EXPR_1 (expr, si, av_ptr)
3568 gcc_assert (INSN_CODE (EXPR_INSN_RTX (expr)) < 0);
3570 if (EXPR_TARGET_AVAILABLE (expr) == 1)
3573 av_set_iter_remove (&si);
3581 /* Lookup EXPR in VINSN_VEC and return TRUE if found. Also check patterns from
3582 EXPR's history of changes. */
3584 vinsn_vec_has_expr_p (vinsn_vec_t vinsn_vec, expr_t expr)
3586 vinsn_t vinsn, expr_vinsn;
3590 /* Start with checking expr itself and then proceed with all the old forms
3591 of expr taken from its history vector. */
3592 for (i = 0, expr_vinsn = EXPR_VINSN (expr);
3594 expr_vinsn = (i < VEC_length (expr_history_def,
3595 EXPR_HISTORY_OF_CHANGES (expr))
3596 ? VEC_index (expr_history_def,
3597 EXPR_HISTORY_OF_CHANGES (expr),
3598 i++)->old_expr_vinsn
3600 FOR_EACH_VEC_ELT (vinsn_t, vinsn_vec, n, vinsn)
3601 if (VINSN_SEPARABLE_P (vinsn))
3603 if (vinsn_equal_p (vinsn, expr_vinsn))
3608 /* For non-separable instructions, the blocking insn can have
3609 another pattern due to substitution, and we can't choose
3610 different register as in the above case. Check all registers
3611 being written instead. */
3612 if (bitmap_intersect_p (VINSN_REG_SETS (vinsn),
3613 VINSN_REG_SETS (expr_vinsn)))
3620 #ifdef ENABLE_CHECKING
3621 /* Return true if either of expressions from ORIG_OPS can be blocked
3622 by previously created bookkeeping code. STATIC_PARAMS points to static
3623 parameters of move_op. */
3625 av_set_could_be_blocked_by_bookkeeping_p (av_set_t orig_ops, void *static_params)
3628 av_set_iterator iter;
3629 moveop_static_params_p sparams;
3631 /* This checks that expressions in ORIG_OPS are not blocked by bookkeeping
3632 created while scheduling on another fence. */
3633 FOR_EACH_EXPR (expr, iter, orig_ops)
3634 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3637 gcc_assert (code_motion_path_driver_info == &move_op_hooks);
3638 sparams = (moveop_static_params_p) static_params;
3640 /* Expressions can be also blocked by bookkeeping created during current
3642 if (bitmap_bit_p (current_copies, INSN_UID (sparams->failed_insn)))
3643 FOR_EACH_EXPR (expr, iter, orig_ops)
3644 if (moveup_expr_cached (expr, sparams->failed_insn, false) != MOVEUP_EXPR_NULL)
3647 /* Expressions in ORIG_OPS may have wrong destination register due to
3648 renaming. Check with the right register instead. */
3649 if (sparams->dest && REG_P (sparams->dest))
3651 unsigned regno = REGNO (sparams->dest);
3652 vinsn_t failed_vinsn = INSN_VINSN (sparams->failed_insn);
3654 if (bitmap_bit_p (VINSN_REG_SETS (failed_vinsn), regno)
3655 || bitmap_bit_p (VINSN_REG_USES (failed_vinsn), regno)
3656 || bitmap_bit_p (VINSN_REG_CLOBBERS (failed_vinsn), regno))
3664 /* Clear VINSN_VEC and detach vinsns. */
3666 vinsn_vec_clear (vinsn_vec_t *vinsn_vec)
3668 unsigned len = VEC_length (vinsn_t, *vinsn_vec);
3674 FOR_EACH_VEC_ELT (vinsn_t, *vinsn_vec, n, vinsn)
3675 vinsn_detach (vinsn);
3676 VEC_block_remove (vinsn_t, *vinsn_vec, 0, len);
3680 /* Add the vinsn of EXPR to the VINSN_VEC. */
3682 vinsn_vec_add (vinsn_vec_t *vinsn_vec, expr_t expr)
3684 vinsn_attach (EXPR_VINSN (expr));
3685 VEC_safe_push (vinsn_t, heap, *vinsn_vec, EXPR_VINSN (expr));
3688 /* Free the vector representing blocked expressions. */
3690 vinsn_vec_free (vinsn_vec_t *vinsn_vec)
3693 VEC_free (vinsn_t, heap, *vinsn_vec);
3696 /* Increase EXPR_PRIORITY_ADJ for INSN by AMOUNT. */
3698 void sel_add_to_insn_priority (rtx insn, int amount)
3700 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)) += amount;
3702 if (sched_verbose >= 2)
3703 sel_print ("sel_add_to_insn_priority: insn %d, by %d (now %d+%d).\n",
3704 INSN_UID (insn), amount, EXPR_PRIORITY (INSN_EXPR (insn)),
3705 EXPR_PRIORITY_ADJ (INSN_EXPR (insn)));
3708 /* Turn AV into a vector, filter inappropriate insns and sort it. Return
3709 true if there is something to schedule. BNDS and FENCE are current
3710 boundaries and fence, respectively. If we need to stall for some cycles
3711 before an expr from AV would become available, write this number to
3714 fill_vec_av_set (av_set_t av, blist_t bnds, fence_t fence,
3719 int sched_next_worked = 0, stalled, n;
3720 static int av_max_prio, est_ticks_till_branch;
3721 int min_need_stall = -1;
3722 deps_t dc = BND_DC (BLIST_BND (bnds));
3724 /* Bail out early when the ready list contained only USEs/CLOBBERs that are
3725 already scheduled. */
3729 /* Empty vector from the previous stuff. */
3730 if (VEC_length (expr_t, vec_av_set) > 0)
3731 VEC_block_remove (expr_t, vec_av_set, 0, VEC_length (expr_t, vec_av_set));
3733 /* Turn the set into a vector for sorting and call sel_target_adjust_priority
3735 gcc_assert (VEC_empty (expr_t, vec_av_set));
3736 FOR_EACH_EXPR (expr, si, av)
3738 VEC_safe_push (expr_t, heap, vec_av_set, expr);
3740 gcc_assert (EXPR_PRIORITY_ADJ (expr) == 0 || *pneed_stall);
3742 /* Adjust priority using target backend hook. */
3743 sel_target_adjust_priority (expr);
3746 /* Sort the vector. */
3747 VEC_qsort (expr_t, vec_av_set, sel_rank_for_schedule);
3749 /* We record maximal priority of insns in av set for current instruction
3751 if (FENCE_STARTS_CYCLE_P (fence))
3752 av_max_prio = est_ticks_till_branch = INT_MIN;
3754 /* Filter out inappropriate expressions. Loop's direction is reversed to
3755 visit "best" instructions first. We assume that VEC_unordered_remove
3756 moves last element in place of one being deleted. */
3757 for (n = VEC_length (expr_t, vec_av_set) - 1, stalled = 0; n >= 0; n--)
3759 expr_t expr = VEC_index (expr_t, vec_av_set, n);
3760 insn_t insn = EXPR_INSN_RTX (expr);
3761 signed char target_available;
3762 bool is_orig_reg_p = true;
3763 int need_cycles, new_prio;
3765 /* Don't allow any insns other than from SCHED_GROUP if we have one. */
3766 if (FENCE_SCHED_NEXT (fence) && insn != FENCE_SCHED_NEXT (fence))
3768 VEC_unordered_remove (expr_t, vec_av_set, n);
3772 /* Set number of sched_next insns (just in case there
3773 could be several). */
3774 if (FENCE_SCHED_NEXT (fence))
3775 sched_next_worked++;
3777 /* Check all liveness requirements and try renaming.
3778 FIXME: try to minimize calls to this. */
3779 target_available = EXPR_TARGET_AVAILABLE (expr);
3781 /* If insn was already scheduled on the current fence,
3782 set TARGET_AVAILABLE to -1 no matter what expr's attribute says. */
3783 if (vinsn_vec_has_expr_p (vec_target_unavailable_vinsns, expr))
3784 target_available = -1;
3786 /* If the availability of the EXPR is invalidated by the insertion of
3787 bookkeeping earlier, make sure that we won't choose this expr for
3788 scheduling if it's not separable, and if it is separable, then
3789 we have to recompute the set of available registers for it. */
3790 if (vinsn_vec_has_expr_p (vec_bookkeeping_blocked_vinsns, expr))
3792 VEC_unordered_remove (expr_t, vec_av_set, n);
3793 if (sched_verbose >= 4)
3794 sel_print ("Expr %d is blocked by bookkeeping inserted earlier\n",
3799 if (target_available == true)
3801 /* Do nothing -- we can use an existing register. */
3802 is_orig_reg_p = EXPR_SEPARABLE_P (expr);
3804 else if (/* Non-separable instruction will never
3805 get another register. */
3806 (target_available == false
3807 && !EXPR_SEPARABLE_P (expr))
3808 /* Don't try to find a register for low-priority expression. */
3809 || (int) VEC_length (expr_t, vec_av_set) - 1 - n >= max_insns_to_rename
3810 /* ??? FIXME: Don't try to rename data speculation. */
3811 || (EXPR_SPEC_DONE_DS (expr) & BEGIN_DATA)
3812 || ! find_best_reg_for_expr (expr, bnds, &is_orig_reg_p))
3814 VEC_unordered_remove (expr_t, vec_av_set, n);
3815 if (sched_verbose >= 4)
3816 sel_print ("Expr %d has no suitable target register\n",
3821 /* Filter expressions that need to be renamed or speculated when
3822 pipelining, because compensating register copies or speculation
3823 checks are likely to be placed near the beginning of the loop,
3825 if (pipelining_p && EXPR_ORIG_SCHED_CYCLE (expr) > 0
3826 && (!is_orig_reg_p || EXPR_SPEC_DONE_DS (expr) != 0))
3828 /* Estimation of number of cycles until loop branch for
3829 renaming/speculation to be successful. */
3830 int need_n_ticks_till_branch = sel_vinsn_cost (EXPR_VINSN (expr));
3832 if ((int) current_loop_nest->ninsns < 9)
3834 VEC_unordered_remove (expr_t, vec_av_set, n);
3835 if (sched_verbose >= 4)
3836 sel_print ("Pipelining expr %d will likely cause stall\n",
3841 if ((int) current_loop_nest->ninsns - num_insns_scheduled
3842 < need_n_ticks_till_branch * issue_rate / 2
3843 && est_ticks_till_branch < need_n_ticks_till_branch)
3845 VEC_unordered_remove (expr_t, vec_av_set, n);
3846 if (sched_verbose >= 4)
3847 sel_print ("Pipelining expr %d will likely cause stall\n",
3853 /* We want to schedule speculation checks as late as possible. Discard
3854 them from av set if there are instructions with higher priority. */
3855 if (sel_insn_is_speculation_check (insn)
3856 && EXPR_PRIORITY (expr) < av_max_prio)
3859 min_need_stall = min_need_stall < 0 ? 1 : MIN (min_need_stall, 1);
3860 VEC_unordered_remove (expr_t, vec_av_set, n);
3861 if (sched_verbose >= 4)
3862 sel_print ("Delaying speculation check %d until its first use\n",
3867 /* Ignore EXPRs available from pipelining to update AV_MAX_PRIO. */
3868 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3869 av_max_prio = MAX (av_max_prio, EXPR_PRIORITY (expr));
3871 /* Don't allow any insns whose data is not yet ready.
3872 Check first whether we've already tried them and failed. */
3873 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
3875 need_cycles = (FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3876 - FENCE_CYCLE (fence));
3877 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3878 est_ticks_till_branch = MAX (est_ticks_till_branch,
3879 EXPR_PRIORITY (expr) + need_cycles);
3881 if (need_cycles > 0)
3884 min_need_stall = (min_need_stall < 0
3886 : MIN (min_need_stall, need_cycles));
3887 VEC_unordered_remove (expr_t, vec_av_set, n);
3889 if (sched_verbose >= 4)
3890 sel_print ("Expr %d is not ready until cycle %d (cached)\n",
3892 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3897 /* Now resort to dependence analysis to find whether EXPR might be
3898 stalled due to dependencies from FENCE's context. */
3899 need_cycles = tick_check_p (expr, dc, fence);
3900 new_prio = EXPR_PRIORITY (expr) + EXPR_PRIORITY_ADJ (expr) + need_cycles;
3902 if (EXPR_ORIG_SCHED_CYCLE (expr) <= 0)
3903 est_ticks_till_branch = MAX (est_ticks_till_branch,
3906 if (need_cycles > 0)
3908 if (INSN_UID (insn) >= FENCE_READY_TICKS_SIZE (fence))
3910 int new_size = INSN_UID (insn) * 3 / 2;
3912 FENCE_READY_TICKS (fence)
3913 = (int *) xrecalloc (FENCE_READY_TICKS (fence),
3914 new_size, FENCE_READY_TICKS_SIZE (fence),
3917 FENCE_READY_TICKS (fence)[INSN_UID (insn)]
3918 = FENCE_CYCLE (fence) + need_cycles;
3921 min_need_stall = (min_need_stall < 0
3923 : MIN (min_need_stall, need_cycles));
3925 VEC_unordered_remove (expr_t, vec_av_set, n);
3927 if (sched_verbose >= 4)
3928 sel_print ("Expr %d is not ready yet until cycle %d\n",
3930 FENCE_READY_TICKS (fence)[INSN_UID (insn)]);
3934 if (sched_verbose >= 4)
3935 sel_print ("Expr %d is ok\n", INSN_UID (insn));
3939 /* Clear SCHED_NEXT. */
3940 if (FENCE_SCHED_NEXT (fence))
3942 gcc_assert (sched_next_worked == 1);
3943 FENCE_SCHED_NEXT (fence) = NULL_RTX;
3946 /* No need to stall if this variable was not initialized. */
3947 if (min_need_stall < 0)
3950 if (VEC_empty (expr_t, vec_av_set))
3952 /* We need to set *pneed_stall here, because later we skip this code
3953 when ready list is empty. */
3954 *pneed_stall = min_need_stall;
3958 gcc_assert (min_need_stall == 0);
3960 /* Sort the vector. */
3961 VEC_qsort (expr_t, vec_av_set, sel_rank_for_schedule);
3963 if (sched_verbose >= 4)
3965 sel_print ("Total ready exprs: %d, stalled: %d\n",
3966 VEC_length (expr_t, vec_av_set), stalled);
3967 sel_print ("Sorted av set (%d): ", VEC_length (expr_t, vec_av_set));
3968 FOR_EACH_VEC_ELT (expr_t, vec_av_set, n, expr)
3977 /* Convert a vectored and sorted av set to the ready list that
3978 the rest of the backend wants to see. */
3980 convert_vec_av_set_to_ready (void)
3985 /* Allocate and fill the ready list from the sorted vector. */
3986 ready.n_ready = VEC_length (expr_t, vec_av_set);
3987 ready.first = ready.n_ready - 1;
3989 gcc_assert (ready.n_ready > 0);
3991 if (ready.n_ready > max_issue_size)
3993 max_issue_size = ready.n_ready;
3994 sched_extend_ready_list (ready.n_ready);
3997 FOR_EACH_VEC_ELT (expr_t, vec_av_set, n, expr)
3999 vinsn_t vi = EXPR_VINSN (expr);
4000 insn_t insn = VINSN_INSN_RTX (vi);
4003 ready.vec[n] = insn;
4007 /* Initialize ready list from *AV_PTR for the max_issue () call.
4008 If any unrecognizable insn found in *AV_PTR, return it (and skip
4009 max_issue). BND and FENCE are current boundary and fence,
4010 respectively. If we need to stall for some cycles before an expr
4011 from *AV_PTR would become available, write this number to *PNEED_STALL. */
4013 fill_ready_list (av_set_t *av_ptr, blist_t bnds, fence_t fence,
4018 /* We do not support multiple boundaries per fence. */
4019 gcc_assert (BLIST_NEXT (bnds) == NULL);
4021 /* Process expressions required special handling, i.e. pipelined,
4022 speculative and recog() < 0 expressions first. */
4023 process_pipelined_exprs (av_ptr);
4024 process_spec_exprs (av_ptr);
4026 /* A USE could be scheduled immediately. */
4027 expr = process_use_exprs (av_ptr);
4034 /* Turn the av set to a vector for sorting. */
4035 if (! fill_vec_av_set (*av_ptr, bnds, fence, pneed_stall))
4041 /* Build the final ready list. */
4042 convert_vec_av_set_to_ready ();
4046 /* Wrapper for dfa_new_cycle (). Returns TRUE if cycle was advanced. */
4048 sel_dfa_new_cycle (insn_t insn, fence_t fence)
4050 int last_scheduled_cycle = FENCE_LAST_SCHEDULED_INSN (fence)
4051 ? INSN_SCHED_CYCLE (FENCE_LAST_SCHEDULED_INSN (fence))
4052 : FENCE_CYCLE (fence) - 1;
4056 if (!targetm.sched.dfa_new_cycle)
4059 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4061 while (!sort_p && targetm.sched.dfa_new_cycle (sched_dump, sched_verbose,
4062 insn, last_scheduled_cycle,
4063 FENCE_CYCLE (fence), &sort_p))
4065 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4066 advance_one_cycle (fence);
4067 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4074 /* Invoke reorder* target hooks on the ready list. Return the number of insns
4075 we can issue. FENCE is the current fence. */
4077 invoke_reorder_hooks (fence_t fence)
4080 bool ran_hook = false;
4082 /* Call the reorder hook at the beginning of the cycle, and call
4083 the reorder2 hook in the middle of the cycle. */
4084 if (FENCE_ISSUED_INSNS (fence) == 0)
4086 if (targetm.sched.reorder
4087 && !SCHED_GROUP_P (ready_element (&ready, 0))
4088 && ready.n_ready > 1)
4090 /* Don't give reorder the most prioritized insn as it can break
4096 = targetm.sched.reorder (sched_dump, sched_verbose,
4097 ready_lastpos (&ready),
4098 &ready.n_ready, FENCE_CYCLE (fence));
4106 /* Initialize can_issue_more for variable_issue. */
4107 issue_more = issue_rate;
4109 else if (targetm.sched.reorder2
4110 && !SCHED_GROUP_P (ready_element (&ready, 0)))
4112 if (ready.n_ready == 1)
4114 targetm.sched.reorder2 (sched_dump, sched_verbose,
4115 ready_lastpos (&ready),
4116 &ready.n_ready, FENCE_CYCLE (fence));
4123 targetm.sched.reorder2 (sched_dump, sched_verbose,
4125 ? ready_lastpos (&ready) : NULL,
4126 &ready.n_ready, FENCE_CYCLE (fence));
4135 issue_more = FENCE_ISSUE_MORE (fence);
4137 /* Ensure that ready list and vec_av_set are in line with each other,
4138 i.e. vec_av_set[i] == ready_element (&ready, i). */
4139 if (issue_more && ran_hook)
4142 rtx *arr = ready.vec;
4143 expr_t *vec = VEC_address (expr_t, vec_av_set);
4145 for (i = 0, n = ready.n_ready; i < n; i++)
4146 if (EXPR_INSN_RTX (vec[i]) != arr[i])
4150 for (j = i; j < n; j++)
4151 if (EXPR_INSN_RTX (vec[j]) == arr[i])
4164 /* Return an EXPR correponding to INDEX element of ready list, if
4165 FOLLOW_READY_ELEMENT is true (i.e., an expr of
4166 ready_element (&ready, INDEX) will be returned), and to INDEX element of
4167 ready.vec otherwise. */
4168 static inline expr_t
4169 find_expr_for_ready (int index, bool follow_ready_element)
4174 real_index = follow_ready_element ? ready.first - index : index;
4176 expr = VEC_index (expr_t, vec_av_set, real_index);
4177 gcc_assert (ready.vec[real_index] == EXPR_INSN_RTX (expr));
4182 /* Calculate insns worth trying via lookahead_guard hook. Return a number
4183 of such insns found. */
4185 invoke_dfa_lookahead_guard (void)
4189 = targetm.sched.first_cycle_multipass_dfa_lookahead_guard != NULL;
4191 if (sched_verbose >= 2)
4192 sel_print ("ready after reorder: ");
4194 for (i = 0, n = 0; i < ready.n_ready; i++)
4200 /* In this loop insn is Ith element of the ready list given by
4201 ready_element, not Ith element of ready.vec. */
4202 insn = ready_element (&ready, i);
4204 if (! have_hook || i == 0)
4207 r = !targetm.sched.first_cycle_multipass_dfa_lookahead_guard (insn);
4209 gcc_assert (INSN_CODE (insn) >= 0);
4211 /* Only insns with ready_try = 0 can get here
4212 from fill_ready_list. */
4213 gcc_assert (ready_try [i] == 0);
4218 expr = find_expr_for_ready (i, true);
4220 if (sched_verbose >= 2)
4222 dump_vinsn (EXPR_VINSN (expr));
4223 sel_print (":%d; ", ready_try[i]);
4227 if (sched_verbose >= 2)
4232 /* Calculate the number of privileged insns and return it. */
4234 calculate_privileged_insns (void)
4236 expr_t cur_expr, min_spec_expr = NULL;
4237 int privileged_n = 0, i;
4239 for (i = 0; i < ready.n_ready; i++)
4244 if (! min_spec_expr)
4245 min_spec_expr = find_expr_for_ready (i, true);
4247 cur_expr = find_expr_for_ready (i, true);
4249 if (EXPR_SPEC (cur_expr) > EXPR_SPEC (min_spec_expr))
4255 if (i == ready.n_ready)
4258 if (sched_verbose >= 2)
4259 sel_print ("privileged_n: %d insns with SPEC %d\n",
4260 privileged_n, privileged_n ? EXPR_SPEC (min_spec_expr) : -1);
4261 return privileged_n;
4264 /* Call the rest of the hooks after the choice was made. Return
4265 the number of insns that still can be issued given that the current
4266 number is ISSUE_MORE. FENCE and BEST_INSN are the current fence
4267 and the insn chosen for scheduling, respectively. */
4269 invoke_aftermath_hooks (fence_t fence, rtx best_insn, int issue_more)
4271 gcc_assert (INSN_P (best_insn));
4273 /* First, call dfa_new_cycle, and then variable_issue, if available. */
4274 sel_dfa_new_cycle (best_insn, fence);
4276 if (targetm.sched.variable_issue)
4278 memcpy (curr_state, FENCE_STATE (fence), dfa_state_size);
4280 targetm.sched.variable_issue (sched_dump, sched_verbose, best_insn,
4282 memcpy (FENCE_STATE (fence), curr_state, dfa_state_size);
4284 else if (GET_CODE (PATTERN (best_insn)) != USE
4285 && GET_CODE (PATTERN (best_insn)) != CLOBBER)
4291 /* Estimate the cost of issuing INSN on DFA state STATE. */
4293 estimate_insn_cost (rtx insn, state_t state)
4295 static state_t temp = NULL;
4299 temp = xmalloc (dfa_state_size);
4301 memcpy (temp, state, dfa_state_size);
4302 cost = state_transition (temp, insn);
4311 /* Return the cost of issuing EXPR on the FENCE as estimated by DFA.
4312 This function properly handles ASMs, USEs etc. */
4314 get_expr_cost (expr_t expr, fence_t fence)
4316 rtx insn = EXPR_INSN_RTX (expr);
4318 if (recog_memoized (insn) < 0)
4320 if (!FENCE_STARTS_CYCLE_P (fence)
4321 && INSN_ASM_P (insn))
4322 /* This is asm insn which is tryed to be issued on the
4323 cycle not first. Issue it on the next cycle. */
4326 /* A USE insn, or something else we don't need to
4327 understand. We can't pass these directly to
4328 state_transition because it will trigger a
4329 fatal error for unrecognizable insns. */
4333 return estimate_insn_cost (insn, FENCE_STATE (fence));
4336 /* Find the best insn for scheduling, either via max_issue or just take
4337 the most prioritized available. */
4339 choose_best_insn (fence_t fence, int privileged_n, int *index)
4343 if (dfa_lookahead > 0)
4345 cycle_issued_insns = FENCE_ISSUED_INSNS (fence);
4346 /* TODO: pass equivalent of first_cycle_insn_p to max_issue (). */
4347 can_issue = max_issue (&ready, privileged_n,
4348 FENCE_STATE (fence), true, index);
4349 if (sched_verbose >= 2)
4350 sel_print ("max_issue: we can issue %d insns, already did %d insns\n",
4351 can_issue, FENCE_ISSUED_INSNS (fence));
4355 /* We can't use max_issue; just return the first available element. */
4358 for (i = 0; i < ready.n_ready; i++)
4360 expr_t expr = find_expr_for_ready (i, true);
4362 if (get_expr_cost (expr, fence) < 1)
4364 can_issue = can_issue_more;
4367 if (sched_verbose >= 2)
4368 sel_print ("using %dth insn from the ready list\n", i + 1);
4374 if (i == ready.n_ready)
4384 /* Choose the best expr from *AV_VLIW_PTR and a suitable register for it.
4385 BNDS and FENCE are current boundaries and scheduling fence respectively.
4386 Return the expr found and NULL if nothing can be issued atm.
4387 Write to PNEED_STALL the number of cycles to stall if no expr was found. */
4389 find_best_expr (av_set_t *av_vliw_ptr, blist_t bnds, fence_t fence,
4394 /* Choose the best insn for scheduling via:
4395 1) sorting the ready list based on priority;
4396 2) calling the reorder hook;
4397 3) calling max_issue. */
4398 best = fill_ready_list (av_vliw_ptr, bnds, fence, pneed_stall);
4399 if (best == NULL && ready.n_ready > 0)
4401 int privileged_n, index;
4403 can_issue_more = invoke_reorder_hooks (fence);
4404 if (can_issue_more > 0)
4406 /* Try choosing the best insn until we find one that is could be
4407 scheduled due to liveness restrictions on its destination register.
4408 In the future, we'd like to choose once and then just probe insns
4409 in the order of their priority. */
4410 invoke_dfa_lookahead_guard ();
4411 privileged_n = calculate_privileged_insns ();
4412 can_issue_more = choose_best_insn (fence, privileged_n, &index);
4414 best = find_expr_for_ready (index, true);
4416 /* We had some available insns, so if we can't issue them,
4418 if (can_issue_more == 0)
4427 can_issue_more = invoke_aftermath_hooks (fence, EXPR_INSN_RTX (best),
4429 if (targetm.sched.variable_issue
4430 && can_issue_more == 0)
4434 if (sched_verbose >= 2)
4438 sel_print ("Best expression (vliw form): ");
4440 sel_print ("; cycle %d\n", FENCE_CYCLE (fence));
4443 sel_print ("No best expr found!\n");
4450 /* Functions that implement the core of the scheduler. */
4453 /* Emit an instruction from EXPR with SEQNO and VINSN after
4456 emit_insn_from_expr_after (expr_t expr, vinsn_t vinsn, int seqno,
4457 insn_t place_to_insert)
4459 /* This assert fails when we have identical instructions
4460 one of which dominates the other. In this case move_op ()
4461 finds the first instruction and doesn't search for second one.
4462 The solution would be to compute av_set after the first found
4463 insn and, if insn present in that set, continue searching.
4464 For now we workaround this issue in move_op. */
4465 gcc_assert (!INSN_IN_STREAM_P (EXPR_INSN_RTX (expr)));
4467 if (EXPR_WAS_RENAMED (expr))
4469 unsigned regno = expr_dest_regno (expr);
4471 if (HARD_REGISTER_NUM_P (regno))
4473 df_set_regs_ever_live (regno, true);
4474 reg_rename_tick[regno] = ++reg_rename_this_tick;
4478 return sel_gen_insn_from_expr_after (expr, vinsn, seqno,
4482 /* Return TRUE if BB can hold bookkeeping code. */
4484 block_valid_for_bookkeeping_p (basic_block bb)
4486 insn_t bb_end = BB_END (bb);
4488 if (!in_current_region_p (bb) || EDGE_COUNT (bb->succs) > 1)
4491 if (INSN_P (bb_end))
4493 if (INSN_SCHED_TIMES (bb_end) > 0)
4497 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (bb_end));
4502 /* Attempt to find a block that can hold bookkeeping code for path(s) incoming
4503 into E2->dest, except from E1->src (there may be a sequence of empty basic
4504 blocks between E1->src and E2->dest). Return found block, or NULL if new
4505 one must be created. If LAX holds, don't assume there is a simple path
4506 from E1->src to E2->dest. */
4508 find_block_for_bookkeeping (edge e1, edge e2, bool lax)
4510 basic_block candidate_block = NULL;
4513 /* Loop over edges from E1 to E2, inclusive. */
4514 for (e = e1; !lax || e->dest != EXIT_BLOCK_PTR; e = EDGE_SUCC (e->dest, 0))
4516 if (EDGE_COUNT (e->dest->preds) == 2)
4518 if (candidate_block == NULL)
4519 candidate_block = (EDGE_PRED (e->dest, 0) == e
4520 ? EDGE_PRED (e->dest, 1)->src
4521 : EDGE_PRED (e->dest, 0)->src);
4523 /* Found additional edge leading to path from e1 to e2
4527 else if (EDGE_COUNT (e->dest->preds) > 2)
4528 /* Several edges leading to path from e1 to e2 from aside. */
4532 return ((!lax || candidate_block)
4533 && block_valid_for_bookkeeping_p (candidate_block)
4537 if (lax && EDGE_COUNT (e->dest->succs) != 1)
4547 /* Create new basic block for bookkeeping code for path(s) incoming into
4548 E2->dest, except from E1->src. Return created block. */
4550 create_block_for_bookkeeping (edge e1, edge e2)
4552 basic_block new_bb, bb = e2->dest;
4554 /* Check that we don't spoil the loop structure. */
4555 if (current_loop_nest)
4557 basic_block latch = current_loop_nest->latch;
4559 /* We do not split header. */
4560 gcc_assert (e2->dest != current_loop_nest->header);
4562 /* We do not redirect the only edge to the latch block. */
4563 gcc_assert (e1->dest != latch
4564 || !single_pred_p (latch)
4565 || e1 != single_pred_edge (latch));
4568 /* Split BB to insert BOOK_INSN there. */
4569 new_bb = sched_split_block (bb, NULL);
4571 /* Move note_list from the upper bb. */
4572 gcc_assert (BB_NOTE_LIST (new_bb) == NULL_RTX);
4573 BB_NOTE_LIST (new_bb) = BB_NOTE_LIST (bb);
4574 BB_NOTE_LIST (bb) = NULL_RTX;
4576 gcc_assert (e2->dest == bb);
4578 /* Skip block for bookkeeping copy when leaving E1->src. */
4579 if (e1->flags & EDGE_FALLTHRU)
4580 sel_redirect_edge_and_branch_force (e1, new_bb);
4582 sel_redirect_edge_and_branch (e1, new_bb);
4584 gcc_assert (e1->dest == new_bb);
4585 gcc_assert (sel_bb_empty_p (bb));
4587 /* To keep basic block numbers in sync between debug and non-debug
4588 compilations, we have to rotate blocks here. Consider that we
4589 started from (a,b)->d, (c,d)->e, and d contained only debug
4590 insns. It would have been removed before if the debug insns
4591 weren't there, so we'd have split e rather than d. So what we do
4592 now is to swap the block numbers of new_bb and
4593 single_succ(new_bb) == e, so that the insns that were in e before
4594 get the new block number. */
4596 if (MAY_HAVE_DEBUG_INSNS)
4599 insn_t insn = sel_bb_head (new_bb);
4602 if (DEBUG_INSN_P (insn)
4603 && single_succ_p (new_bb)
4604 && (succ = single_succ (new_bb))
4605 && succ != EXIT_BLOCK_PTR
4606 && DEBUG_INSN_P ((last = sel_bb_end (new_bb))))
4608 while (insn != last && (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4609 insn = NEXT_INSN (insn);
4613 sel_global_bb_info_def gbi;
4614 sel_region_bb_info_def rbi;
4617 if (sched_verbose >= 2)
4618 sel_print ("Swapping block ids %i and %i\n",
4619 new_bb->index, succ->index);
4622 new_bb->index = succ->index;
4625 SET_BASIC_BLOCK (new_bb->index, new_bb);
4626 SET_BASIC_BLOCK (succ->index, succ);
4628 memcpy (&gbi, SEL_GLOBAL_BB_INFO (new_bb), sizeof (gbi));
4629 memcpy (SEL_GLOBAL_BB_INFO (new_bb), SEL_GLOBAL_BB_INFO (succ),
4631 memcpy (SEL_GLOBAL_BB_INFO (succ), &gbi, sizeof (gbi));
4633 memcpy (&rbi, SEL_REGION_BB_INFO (new_bb), sizeof (rbi));
4634 memcpy (SEL_REGION_BB_INFO (new_bb), SEL_REGION_BB_INFO (succ),
4636 memcpy (SEL_REGION_BB_INFO (succ), &rbi, sizeof (rbi));
4638 i = BLOCK_TO_BB (new_bb->index);
4639 BLOCK_TO_BB (new_bb->index) = BLOCK_TO_BB (succ->index);
4640 BLOCK_TO_BB (succ->index) = i;
4642 i = CONTAINING_RGN (new_bb->index);
4643 CONTAINING_RGN (new_bb->index) = CONTAINING_RGN (succ->index);
4644 CONTAINING_RGN (succ->index) = i;
4646 for (i = 0; i < current_nr_blocks; i++)
4647 if (BB_TO_BLOCK (i) == succ->index)
4648 BB_TO_BLOCK (i) = new_bb->index;
4649 else if (BB_TO_BLOCK (i) == new_bb->index)
4650 BB_TO_BLOCK (i) = succ->index;
4652 FOR_BB_INSNS (new_bb, insn)
4654 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = new_bb->index;
4656 FOR_BB_INSNS (succ, insn)
4658 EXPR_ORIG_BB_INDEX (INSN_EXPR (insn)) = succ->index;
4660 if (bitmap_clear_bit (code_motion_visited_blocks, new_bb->index))
4661 bitmap_set_bit (code_motion_visited_blocks, succ->index);
4663 gcc_assert (LABEL_P (BB_HEAD (new_bb))
4664 && LABEL_P (BB_HEAD (succ)));
4666 if (sched_verbose >= 4)
4667 sel_print ("Swapping code labels %i and %i\n",
4668 CODE_LABEL_NUMBER (BB_HEAD (new_bb)),
4669 CODE_LABEL_NUMBER (BB_HEAD (succ)));
4671 i = CODE_LABEL_NUMBER (BB_HEAD (new_bb));
4672 CODE_LABEL_NUMBER (BB_HEAD (new_bb))
4673 = CODE_LABEL_NUMBER (BB_HEAD (succ));
4674 CODE_LABEL_NUMBER (BB_HEAD (succ)) = i;
4682 /* Return insn after which we must insert bookkeeping code for path(s) incoming
4683 into E2->dest, except from E1->src. */
4685 find_place_for_bookkeeping (edge e1, edge e2)
4687 insn_t place_to_insert;
4688 /* Find a basic block that can hold bookkeeping. If it can be found, do not
4689 create new basic block, but insert bookkeeping there. */
4690 basic_block book_block = find_block_for_bookkeeping (e1, e2, FALSE);
4694 place_to_insert = BB_END (book_block);
4696 /* Don't use a block containing only debug insns for
4697 bookkeeping, this causes scheduling differences between debug
4698 and non-debug compilations, for the block would have been
4700 if (DEBUG_INSN_P (place_to_insert))
4702 rtx insn = sel_bb_head (book_block);
4704 while (insn != place_to_insert &&
4705 (DEBUG_INSN_P (insn) || NOTE_P (insn)))
4706 insn = NEXT_INSN (insn);
4708 if (insn == place_to_insert)
4715 book_block = create_block_for_bookkeeping (e1, e2);
4716 place_to_insert = BB_END (book_block);
4717 if (sched_verbose >= 9)
4718 sel_print ("New block is %i, split from bookkeeping block %i\n",
4719 EDGE_SUCC (book_block, 0)->dest->index, book_block->index);
4723 if (sched_verbose >= 9)
4724 sel_print ("Pre-existing bookkeeping block is %i\n", book_block->index);
4727 /* If basic block ends with a jump, insert bookkeeping code right before it. */
4728 if (INSN_P (place_to_insert) && control_flow_insn_p (place_to_insert))
4729 place_to_insert = PREV_INSN (place_to_insert);
4731 return place_to_insert;
4734 /* Find a proper seqno for bookkeeing insn inserted at PLACE_TO_INSERT
4737 find_seqno_for_bookkeeping (insn_t place_to_insert, insn_t join_point)
4742 /* Check if we are about to insert bookkeeping copy before a jump, and use
4743 jump's seqno for the copy; otherwise, use JOIN_POINT's seqno. */
4744 next = NEXT_INSN (place_to_insert);
4747 && BLOCK_FOR_INSN (next) == BLOCK_FOR_INSN (place_to_insert))
4749 gcc_assert (INSN_SCHED_TIMES (next) == 0);
4750 seqno = INSN_SEQNO (next);
4752 else if (INSN_SEQNO (join_point) > 0)
4753 seqno = INSN_SEQNO (join_point);
4756 seqno = get_seqno_by_preds (place_to_insert);
4758 /* Sometimes the fences can move in such a way that there will be
4759 no instructions with positive seqno around this bookkeeping.
4760 This means that there will be no way to get to it by a regular
4761 fence movement. Never mind because we pick up such pieces for
4762 rescheduling anyways, so any positive value will do for now. */
4765 gcc_assert (pipelining_p);
4770 gcc_assert (seqno > 0);
4774 /* Insert bookkeeping copy of C_EXPS's insn after PLACE_TO_INSERT, assigning
4775 NEW_SEQNO to it. Return created insn. */
4777 emit_bookkeeping_insn (insn_t place_to_insert, expr_t c_expr, int new_seqno)
4779 rtx new_insn_rtx = create_copy_of_insn_rtx (EXPR_INSN_RTX (c_expr));
4782 = create_vinsn_from_insn_rtx (new_insn_rtx,
4783 VINSN_UNIQUE_P (EXPR_VINSN (c_expr)));
4785 insn_t new_insn = emit_insn_from_expr_after (c_expr, new_vinsn, new_seqno,
4788 INSN_SCHED_TIMES (new_insn) = 0;
4789 bitmap_set_bit (current_copies, INSN_UID (new_insn));
4794 /* Generate a bookkeeping copy of C_EXPR's insn for path(s) incoming into to
4795 E2->dest, except from E1->src (there may be a sequence of empty blocks
4796 between E1->src and E2->dest). Return block containing the copy.
4797 All scheduler data is initialized for the newly created insn. */
4799 generate_bookkeeping_insn (expr_t c_expr, edge e1, edge e2)
4801 insn_t join_point, place_to_insert, new_insn;
4803 bool need_to_exchange_data_sets;
4805 if (sched_verbose >= 4)
4806 sel_print ("Generating bookkeeping insn (%d->%d)\n", e1->src->index,
4809 join_point = sel_bb_head (e2->dest);
4810 place_to_insert = find_place_for_bookkeeping (e1, e2);
4811 if (!place_to_insert)
4813 new_seqno = find_seqno_for_bookkeeping (place_to_insert, join_point);
4814 need_to_exchange_data_sets
4815 = sel_bb_empty_p (BLOCK_FOR_INSN (place_to_insert));
4817 new_insn = emit_bookkeeping_insn (place_to_insert, c_expr, new_seqno);
4819 /* When inserting bookkeeping insn in new block, av sets should be
4820 following: old basic block (that now holds bookkeeping) data sets are
4821 the same as was before generation of bookkeeping, and new basic block
4822 (that now hold all other insns of old basic block) data sets are
4823 invalid. So exchange data sets for these basic blocks as sel_split_block
4824 mistakenly exchanges them in this case. Cannot do it earlier because
4825 when single instruction is added to new basic block it should hold NULL
4827 if (need_to_exchange_data_sets)
4828 exchange_data_sets (BLOCK_FOR_INSN (new_insn),
4829 BLOCK_FOR_INSN (join_point));
4831 stat_bookkeeping_copies++;
4832 return BLOCK_FOR_INSN (new_insn);
4835 /* Remove from AV_PTR all insns that may need bookkeeping when scheduling
4836 on FENCE, but we are unable to copy them. */
4838 remove_insns_that_need_bookkeeping (fence_t fence, av_set_t *av_ptr)
4843 /* An expression does not need bookkeeping if it is available on all paths
4844 from current block to original block and current block dominates
4845 original block. We check availability on all paths by examining
4846 EXPR_SPEC; this is not equivalent, because it may be positive even
4847 if expr is available on all paths (but if expr is not available on
4848 any path, EXPR_SPEC will be positive). */
4850 FOR_EACH_EXPR_1 (expr, i, av_ptr)
4852 if (!control_flow_insn_p (EXPR_INSN_RTX (expr))
4853 && (!bookkeeping_p || VINSN_UNIQUE_P (EXPR_VINSN (expr)))
4854 && (EXPR_SPEC (expr)
4855 || !EXPR_ORIG_BB_INDEX (expr)
4856 || !dominated_by_p (CDI_DOMINATORS,
4857 BASIC_BLOCK (EXPR_ORIG_BB_INDEX (expr)),
4858 BLOCK_FOR_INSN (FENCE_INSN (fence)))))
4860 if (sched_verbose >= 4)
4861 sel_print ("Expr %d removed because it would need bookkeeping, which "
4862 "cannot be created\n", INSN_UID (EXPR_INSN_RTX (expr)));
4863 av_set_iter_remove (&i);
4868 /* Moving conditional jump through some instructions.
4872 ... <- current scheduling point
4873 NOTE BASIC BLOCK: <- bb header
4874 (p8) add r14=r14+0x9;;
4880 We can schedule jump one cycle earlier, than mov, because they cannot be
4881 executed together as their predicates are mutually exclusive.
4883 This is done in this way: first, new fallthrough basic block is created
4884 after jump (it is always can be done, because there already should be a
4885 fallthrough block, where control flow goes in case of predicate being true -
4886 in our example; otherwise there should be a dependence between those
4887 instructions and jump and we cannot schedule jump right now);
4888 next, all instructions between jump and current scheduling point are moved
4889 to this new block. And the result is this:
4892 (!p8) jump L1 <- current scheduling point
4893 NOTE BASIC BLOCK: <- bb header
4894 (p8) add r14=r14+0x9;;
4900 move_cond_jump (rtx insn, bnd_t bnd)
4903 basic_block block_from, block_next, block_new, block_bnd, bb;
4904 rtx next, prev, link, head;
4906 block_from = BLOCK_FOR_INSN (insn);
4907 block_bnd = BLOCK_FOR_INSN (BND_TO (bnd));
4908 prev = BND_TO (bnd);
4910 #ifdef ENABLE_CHECKING
4911 /* Moving of jump should not cross any other jumps or beginnings of new
4912 basic blocks. The only exception is when we move a jump through
4913 mutually exclusive insns along fallthru edges. */
4914 if (block_from != block_bnd)
4917 for (link = PREV_INSN (insn); link != PREV_INSN (prev);
4918 link = PREV_INSN (link))
4921 gcc_assert (sched_insns_conditions_mutex_p (insn, link));
4922 if (BLOCK_FOR_INSN (link) && BLOCK_FOR_INSN (link) != bb)
4924 gcc_assert (single_pred (bb) == BLOCK_FOR_INSN (link));
4925 bb = BLOCK_FOR_INSN (link);
4931 /* Jump is moved to the boundary. */
4932 next = PREV_INSN (insn);
4933 BND_TO (bnd) = insn;
4935 ft_edge = find_fallthru_edge_from (block_from);
4936 block_next = ft_edge->dest;
4937 /* There must be a fallthrough block (or where should go
4938 control flow in case of false jump predicate otherwise?). */
4939 gcc_assert (block_next);
4941 /* Create new empty basic block after source block. */
4942 block_new = sel_split_edge (ft_edge);
4943 gcc_assert (block_new->next_bb == block_next
4944 && block_from->next_bb == block_new);
4946 /* Move all instructions except INSN to BLOCK_NEW. */
4948 head = BB_HEAD (block_new);
4949 while (bb != block_from->next_bb)
4952 from = bb == block_bnd ? prev : sel_bb_head (bb);
4953 to = bb == block_from ? next : sel_bb_end (bb);
4955 /* The jump being moved can be the first insn in the block.
4956 In this case we don't have to move anything in this block. */
4957 if (NEXT_INSN (to) != from)
4959 reorder_insns (from, to, head);
4961 for (link = to; link != head; link = PREV_INSN (link))
4962 EXPR_ORIG_BB_INDEX (INSN_EXPR (link)) = block_new->index;
4966 /* Cleanup possibly empty blocks left. */
4967 block_next = bb->next_bb;
4968 if (bb != block_from)
4969 tidy_control_flow (bb, false);
4973 /* Assert there is no jump to BLOCK_NEW, only fallthrough edge. */
4974 gcc_assert (NOTE_INSN_BASIC_BLOCK_P (BB_HEAD (block_new)));
4976 gcc_assert (!sel_bb_empty_p (block_from)
4977 && !sel_bb_empty_p (block_new));
4979 /* Update data sets for BLOCK_NEW to represent that INSN and
4980 instructions from the other branch of INSN is no longer
4981 available at BLOCK_NEW. */
4982 BB_AV_LEVEL (block_new) = global_level;
4983 gcc_assert (BB_LV_SET (block_new) == NULL);
4984 BB_LV_SET (block_new) = get_clear_regset_from_pool ();
4985 update_data_sets (sel_bb_head (block_new));
4987 /* INSN is a new basic block header - so prepare its data
4988 structures and update availability and liveness sets. */
4989 update_data_sets (insn);
4991 if (sched_verbose >= 4)
4992 sel_print ("Moving jump %d\n", INSN_UID (insn));
4995 /* Remove nops generated during move_op for preventing removal of empty
4998 remove_temp_moveop_nops (bool full_tidying)
5003 FOR_EACH_VEC_ELT (insn_t, vec_temp_moveop_nops, i, insn)
5005 gcc_assert (INSN_NOP_P (insn));
5006 return_nop_to_pool (insn, full_tidying);
5009 /* Empty the vector. */
5010 if (VEC_length (insn_t, vec_temp_moveop_nops) > 0)
5011 VEC_block_remove (insn_t, vec_temp_moveop_nops, 0,
5012 VEC_length (insn_t, vec_temp_moveop_nops));
5015 /* Records the maximal UID before moving up an instruction. Used for
5016 distinguishing between bookkeeping copies and original insns. */
5017 static int max_uid_before_move_op = 0;
5019 /* Remove from AV_VLIW_P all instructions but next when debug counter
5020 tells us so. Next instruction is fetched from BNDS. */
5022 remove_insns_for_debug (blist_t bnds, av_set_t *av_vliw_p)
5024 if (! dbg_cnt (sel_sched_insn_cnt))
5025 /* Leave only the next insn in av_vliw. */
5027 av_set_iterator av_it;
5029 bnd_t bnd = BLIST_BND (bnds);
5030 insn_t next = BND_TO (bnd);
5032 gcc_assert (BLIST_NEXT (bnds) == NULL);
5034 FOR_EACH_EXPR_1 (expr, av_it, av_vliw_p)
5035 if (EXPR_INSN_RTX (expr) != next)
5036 av_set_iter_remove (&av_it);
5040 /* Compute available instructions on BNDS. FENCE is the current fence. Write
5041 the computed set to *AV_VLIW_P. */
5043 compute_av_set_on_boundaries (fence_t fence, blist_t bnds, av_set_t *av_vliw_p)
5045 if (sched_verbose >= 2)
5047 sel_print ("Boundaries: ");
5052 for (; bnds; bnds = BLIST_NEXT (bnds))
5054 bnd_t bnd = BLIST_BND (bnds);
5056 insn_t bnd_to = BND_TO (bnd);
5058 /* Rewind BND->TO to the basic block header in case some bookkeeping
5059 instructions were inserted before BND->TO and it needs to be
5061 if (sel_bb_head_p (bnd_to))
5062 gcc_assert (INSN_SCHED_TIMES (bnd_to) == 0);
5064 while (INSN_SCHED_TIMES (PREV_INSN (bnd_to)) == 0)
5066 bnd_to = PREV_INSN (bnd_to);
5067 if (sel_bb_head_p (bnd_to))
5071 if (BND_TO (bnd) != bnd_to)
5073 gcc_assert (FENCE_INSN (fence) == BND_TO (bnd));
5074 FENCE_INSN (fence) = bnd_to;
5075 BND_TO (bnd) = bnd_to;
5078 av_set_clear (&BND_AV (bnd));
5079 BND_AV (bnd) = compute_av_set (BND_TO (bnd), NULL, 0, true);
5081 av_set_clear (&BND_AV1 (bnd));
5082 BND_AV1 (bnd) = av_set_copy (BND_AV (bnd));
5084 moveup_set_inside_insn_group (&BND_AV1 (bnd), NULL);
5086 av1_copy = av_set_copy (BND_AV1 (bnd));
5087 av_set_union_and_clear (av_vliw_p, &av1_copy, NULL);
5090 if (sched_verbose >= 2)
5092 sel_print ("Available exprs (vliw form): ");
5093 dump_av_set (*av_vliw_p);
5098 /* Calculate the sequential av set on BND corresponding to the EXPR_VLIW
5099 expression. When FOR_MOVEOP is true, also replace the register of
5100 expressions found with the register from EXPR_VLIW. */
5102 find_sequential_best_exprs (bnd_t bnd, expr_t expr_vliw, bool for_moveop)
5104 av_set_t expr_seq = NULL;
5108 FOR_EACH_EXPR (expr, i, BND_AV (bnd))
5110 if (equal_after_moveup_path_p (expr, NULL, expr_vliw))
5114 /* The sequential expression has the right form to pass
5115 to move_op except when renaming happened. Put the
5116 correct register in EXPR then. */
5117 if (EXPR_SEPARABLE_P (expr) && REG_P (EXPR_LHS (expr)))
5119 if (expr_dest_regno (expr) != expr_dest_regno (expr_vliw))
5121 replace_dest_with_reg_in_expr (expr, EXPR_LHS (expr_vliw));
5122 stat_renamed_scheduled++;
5124 /* Also put the correct TARGET_AVAILABLE bit on the expr.
5125 This is needed when renaming came up with original
5127 else if (EXPR_TARGET_AVAILABLE (expr)
5128 != EXPR_TARGET_AVAILABLE (expr_vliw))
5130 gcc_assert (EXPR_TARGET_AVAILABLE (expr_vliw) == 1);
5131 EXPR_TARGET_AVAILABLE (expr) = 1;
5134 if (EXPR_WAS_SUBSTITUTED (expr))
5135 stat_substitutions_total++;
5138 av_set_add (&expr_seq, expr);
5140 /* With substitution inside insn group, it is possible
5141 that more than one expression in expr_seq will correspond
5142 to expr_vliw. In this case, choose one as the attempt to
5143 move both leads to miscompiles. */
5148 if (for_moveop && sched_verbose >= 2)
5150 sel_print ("Best expression(s) (sequential form): ");
5151 dump_av_set (expr_seq);
5159 /* Move nop to previous block. */
5160 static void ATTRIBUTE_UNUSED
5161 move_nop_to_previous_block (insn_t nop, basic_block prev_bb)
5163 insn_t prev_insn, next_insn, note;
5165 gcc_assert (sel_bb_head_p (nop)
5166 && prev_bb == BLOCK_FOR_INSN (nop)->prev_bb);
5167 note = bb_note (BLOCK_FOR_INSN (nop));
5168 prev_insn = sel_bb_end (prev_bb);
5169 next_insn = NEXT_INSN (nop);
5170 gcc_assert (prev_insn != NULL_RTX
5171 && PREV_INSN (note) == prev_insn);
5173 NEXT_INSN (prev_insn) = nop;
5174 PREV_INSN (nop) = prev_insn;
5176 PREV_INSN (note) = nop;
5177 NEXT_INSN (note) = next_insn;
5179 NEXT_INSN (nop) = note;
5180 PREV_INSN (next_insn) = note;
5182 BB_END (prev_bb) = nop;
5183 BLOCK_FOR_INSN (nop) = prev_bb;
5186 /* Prepare a place to insert the chosen expression on BND. */
5188 prepare_place_to_insert (bnd_t bnd)
5190 insn_t place_to_insert;
5192 /* Init place_to_insert before calling move_op, as the later
5193 can possibly remove BND_TO (bnd). */
5194 if (/* If this is not the first insn scheduled. */
5197 /* Add it after last scheduled. */
5198 place_to_insert = ILIST_INSN (BND_PTR (bnd));
5199 if (DEBUG_INSN_P (place_to_insert))
5201 ilist_t l = BND_PTR (bnd);
5202 while ((l = ILIST_NEXT (l)) &&
5203 DEBUG_INSN_P (ILIST_INSN (l)))
5206 place_to_insert = NULL;
5210 place_to_insert = NULL;
5212 if (!place_to_insert)
5214 /* Add it before BND_TO. The difference is in the
5215 basic block, where INSN will be added. */
5216 place_to_insert = get_nop_from_pool (BND_TO (bnd));
5217 gcc_assert (BLOCK_FOR_INSN (place_to_insert)
5218 == BLOCK_FOR_INSN (BND_TO (bnd)));
5221 return place_to_insert;
5224 /* Find original instructions for EXPR_SEQ and move it to BND boundary.
5225 Return the expression to emit in C_EXPR. */
5227 move_exprs_to_boundary (bnd_t bnd, expr_t expr_vliw,
5228 av_set_t expr_seq, expr_t c_expr)
5230 bool b, should_move;
5233 int n_bookkeeping_copies_before_moveop;
5235 /* Make a move. This call will remove the original operation,
5236 insert all necessary bookkeeping instructions and update the
5237 data sets. After that all we have to do is add the operation
5238 at before BND_TO (BND). */
5239 n_bookkeeping_copies_before_moveop = stat_bookkeeping_copies;
5240 max_uid_before_move_op = get_max_uid ();
5241 bitmap_clear (current_copies);
5242 bitmap_clear (current_originators);
5244 b = move_op (BND_TO (bnd), expr_seq, expr_vliw,
5245 get_dest_from_orig_ops (expr_seq), c_expr, &should_move);
5247 /* We should be able to find the expression we've chosen for
5251 if (stat_bookkeeping_copies > n_bookkeeping_copies_before_moveop)
5252 stat_insns_needed_bookkeeping++;
5254 EXECUTE_IF_SET_IN_BITMAP (current_copies, 0, book_uid, bi)
5259 /* We allocate these bitmaps lazily. */
5260 if (! INSN_ORIGINATORS_BY_UID (book_uid))
5261 INSN_ORIGINATORS_BY_UID (book_uid) = BITMAP_ALLOC (NULL);
5263 bitmap_copy (INSN_ORIGINATORS_BY_UID (book_uid),
5264 current_originators);
5266 /* Transitively add all originators' originators. */
5267 EXECUTE_IF_SET_IN_BITMAP (current_originators, 0, uid, bi)
5268 if (INSN_ORIGINATORS_BY_UID (uid))
5269 bitmap_ior_into (INSN_ORIGINATORS_BY_UID (book_uid),
5270 INSN_ORIGINATORS_BY_UID (uid));
5277 /* Debug a DFA state as an array of bytes. */
5279 debug_state (state_t state)
5282 unsigned int i, size = dfa_state_size;
5284 sel_print ("state (%u):", size);
5285 for (i = 0, p = (unsigned char *) state; i < size; i++)
5286 sel_print (" %d", p[i]);
5290 /* Advance state on FENCE with INSN. Return true if INSN is
5291 an ASM, and we should advance state once more. */
5293 advance_state_on_fence (fence_t fence, insn_t insn)
5297 if (recog_memoized (insn) >= 0)
5300 state_t temp_state = alloca (dfa_state_size);
5302 gcc_assert (!INSN_ASM_P (insn));
5305 memcpy (temp_state, FENCE_STATE (fence), dfa_state_size);
5306 res = state_transition (FENCE_STATE (fence), insn);
5307 gcc_assert (res < 0);
5309 if (memcmp (temp_state, FENCE_STATE (fence), dfa_state_size))
5311 FENCE_ISSUED_INSNS (fence)++;
5313 /* We should never issue more than issue_rate insns. */
5314 if (FENCE_ISSUED_INSNS (fence) > issue_rate)
5320 /* This could be an ASM insn which we'd like to schedule
5321 on the next cycle. */
5322 asm_p = INSN_ASM_P (insn);
5323 if (!FENCE_STARTS_CYCLE_P (fence) && asm_p)
5324 advance_one_cycle (fence);
5327 if (sched_verbose >= 2)
5328 debug_state (FENCE_STATE (fence));
5329 if (!DEBUG_INSN_P (insn))
5330 FENCE_STARTS_CYCLE_P (fence) = 0;
5331 FENCE_ISSUE_MORE (fence) = can_issue_more;
5335 /* Update FENCE on which INSN was scheduled and this INSN, too. NEED_STALL
5336 is nonzero if we need to stall after issuing INSN. */
5338 update_fence_and_insn (fence_t fence, insn_t insn, int need_stall)
5342 /* First, reflect that something is scheduled on this fence. */
5343 asm_p = advance_state_on_fence (fence, insn);
5344 FENCE_LAST_SCHEDULED_INSN (fence) = insn;
5345 VEC_safe_push (rtx, gc, FENCE_EXECUTING_INSNS (fence), insn);
5346 if (SCHED_GROUP_P (insn))
5348 FENCE_SCHED_NEXT (fence) = INSN_SCHED_NEXT (insn);
5349 SCHED_GROUP_P (insn) = 0;
5352 FENCE_SCHED_NEXT (fence) = NULL_RTX;
5353 if (INSN_UID (insn) < FENCE_READY_TICKS_SIZE (fence))
5354 FENCE_READY_TICKS (fence) [INSN_UID (insn)] = 0;
5356 /* Set instruction scheduling info. This will be used in bundling,
5357 pipelining, tick computations etc. */
5358 ++INSN_SCHED_TIMES (insn);
5359 EXPR_TARGET_AVAILABLE (INSN_EXPR (insn)) = true;
5360 EXPR_ORIG_SCHED_CYCLE (INSN_EXPR (insn)) = FENCE_CYCLE (fence);
5361 INSN_AFTER_STALL_P (insn) = FENCE_AFTER_STALL_P (fence);
5362 INSN_SCHED_CYCLE (insn) = FENCE_CYCLE (fence);
5364 /* This does not account for adjust_cost hooks, just add the biggest
5365 constant the hook may add to the latency. TODO: make this
5366 a target dependent constant. */
5367 INSN_READY_CYCLE (insn)
5368 = INSN_SCHED_CYCLE (insn) + (INSN_CODE (insn) < 0
5370 : maximal_insn_latency (insn) + 1);
5372 /* Change these fields last, as they're used above. */
5373 FENCE_AFTER_STALL_P (fence) = 0;
5374 if (asm_p || need_stall)
5375 advance_one_cycle (fence);
5377 /* Indicate that we've scheduled something on this fence. */
5378 FENCE_SCHEDULED_P (fence) = true;
5379 scheduled_something_on_previous_fence = true;
5381 /* Print debug information when insn's fields are updated. */
5382 if (sched_verbose >= 2)
5384 sel_print ("Scheduling insn: ");
5385 dump_insn_1 (insn, 1);
5390 /* Update boundary BND (and, if needed, FENCE) with INSN, remove the
5391 old boundary from BNDSP, add new boundaries to BNDS_TAIL_P and
5394 update_boundaries (fence_t fence, bnd_t bnd, insn_t insn, blist_t *bndsp,
5395 blist_t *bnds_tailp)
5400 advance_deps_context (BND_DC (bnd), insn);
5401 FOR_EACH_SUCC_1 (succ, si, insn,
5402 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
5404 ilist_t ptr = ilist_copy (BND_PTR (bnd));
5406 ilist_add (&ptr, insn);
5408 if (DEBUG_INSN_P (insn) && sel_bb_end_p (insn)
5409 && is_ineligible_successor (succ, ptr))
5415 if (FENCE_INSN (fence) == insn && !sel_bb_end_p (insn))
5417 if (sched_verbose >= 9)
5418 sel_print ("Updating fence insn from %i to %i\n",
5419 INSN_UID (insn), INSN_UID (succ));
5420 FENCE_INSN (fence) = succ;
5422 blist_add (bnds_tailp, succ, ptr, BND_DC (bnd));
5423 bnds_tailp = &BLIST_NEXT (*bnds_tailp);
5426 blist_remove (bndsp);
5430 /* Schedule EXPR_VLIW on BND. Return the insn emitted. */
5432 schedule_expr_on_boundary (bnd_t bnd, expr_t expr_vliw, int seqno)
5435 expr_t c_expr = XALLOCA (expr_def);
5436 insn_t place_to_insert;
5440 expr_seq = find_sequential_best_exprs (bnd, expr_vliw, true);
5442 /* In case of scheduling a jump skipping some other instructions,
5443 prepare CFG. After this, jump is at the boundary and can be
5444 scheduled as usual insn by MOVE_OP. */
5445 if (vinsn_cond_branch_p (EXPR_VINSN (expr_vliw)))
5447 insn = EXPR_INSN_RTX (expr_vliw);
5449 /* Speculative jumps are not handled. */
5450 if (insn != BND_TO (bnd)
5451 && !sel_insn_is_speculation_check (insn))
5452 move_cond_jump (insn, bnd);
5455 /* Find a place for C_EXPR to schedule. */
5456 place_to_insert = prepare_place_to_insert (bnd);
5457 should_move = move_exprs_to_boundary (bnd, expr_vliw, expr_seq, c_expr);
5458 clear_expr (c_expr);
5460 /* Add the instruction. The corner case to care about is when
5461 the expr_seq set has more than one expr, and we chose the one that
5462 is not equal to expr_vliw. Then expr_vliw may be insn in stream, and
5463 we can't use it. Generate the new vinsn. */
5464 if (INSN_IN_STREAM_P (EXPR_INSN_RTX (expr_vliw)))
5468 vinsn_new = vinsn_copy (EXPR_VINSN (expr_vliw), false);
5469 change_vinsn_in_expr (expr_vliw, vinsn_new);
5470 should_move = false;
5473 insn = sel_move_insn (expr_vliw, seqno, place_to_insert);
5475 insn = emit_insn_from_expr_after (expr_vliw, NULL, seqno,
5478 /* Return the nops generated for preserving of data sets back
5480 if (INSN_NOP_P (place_to_insert))
5481 return_nop_to_pool (place_to_insert, !DEBUG_INSN_P (insn));
5482 remove_temp_moveop_nops (!DEBUG_INSN_P (insn));
5484 av_set_clear (&expr_seq);
5486 /* Save the expression scheduled so to reset target availability if we'll
5487 meet it later on the same fence. */
5488 if (EXPR_WAS_RENAMED (expr_vliw))
5489 vinsn_vec_add (&vec_target_unavailable_vinsns, INSN_EXPR (insn));
5491 /* Check that the recent movement didn't destroyed loop
5493 gcc_assert (!pipelining_p
5494 || current_loop_nest == NULL
5495 || loop_latch_edge (current_loop_nest));
5499 /* Stall for N cycles on FENCE. */
5501 stall_for_cycles (fence_t fence, int n)
5505 could_more = n > 1 || FENCE_ISSUED_INSNS (fence) < issue_rate;
5507 advance_one_cycle (fence);
5509 FENCE_AFTER_STALL_P (fence) = 1;
5512 /* Gather a parallel group of insns at FENCE and assign their seqno
5513 to SEQNO. All scheduled insns are gathered in SCHEDULED_INSNS_TAILPP
5514 list for later recalculation of seqnos. */
5516 fill_insns (fence_t fence, int seqno, ilist_t **scheduled_insns_tailpp)
5518 blist_t bnds = NULL, *bnds_tailp;
5519 av_set_t av_vliw = NULL;
5520 insn_t insn = FENCE_INSN (fence);
5522 if (sched_verbose >= 2)
5523 sel_print ("Starting fill_insns for insn %d, cycle %d\n",
5524 INSN_UID (insn), FENCE_CYCLE (fence));
5526 blist_add (&bnds, insn, NULL, FENCE_DC (fence));
5527 bnds_tailp = &BLIST_NEXT (bnds);
5528 set_target_context (FENCE_TC (fence));
5529 can_issue_more = FENCE_ISSUE_MORE (fence);
5530 target_bb = INSN_BB (insn);
5532 /* Do while we can add any operation to the current group. */
5535 blist_t *bnds_tailp1, *bndsp;
5538 int was_stall = 0, scheduled_insns = 0;
5539 int max_insns = pipelining_p ? issue_rate : 2 * issue_rate;
5540 int max_stall = pipelining_p ? 1 : 3;
5541 bool last_insn_was_debug = false;
5542 bool was_debug_bb_end_p = false;
5544 compute_av_set_on_boundaries (fence, bnds, &av_vliw);
5545 remove_insns_that_need_bookkeeping (fence, &av_vliw);
5546 remove_insns_for_debug (bnds, &av_vliw);
5548 /* Return early if we have nothing to schedule. */
5549 if (av_vliw == NULL)
5552 /* Choose the best expression and, if needed, destination register
5556 expr_vliw = find_best_expr (&av_vliw, bnds, fence, &need_stall);
5557 if (! expr_vliw && need_stall)
5559 /* All expressions required a stall. Do not recompute av sets
5560 as we'll get the same answer (modulo the insns between
5561 the fence and its boundary, which will not be available for
5563 If we are going to stall for too long, break to recompute av
5564 sets and bring more insns for pipelining. */
5566 if (need_stall <= 3)
5567 stall_for_cycles (fence, need_stall);
5570 stall_for_cycles (fence, 1);
5575 while (! expr_vliw && need_stall);
5577 /* Now either we've selected expr_vliw or we have nothing to schedule. */
5580 av_set_clear (&av_vliw);
5585 bnds_tailp1 = bnds_tailp;
5588 /* This code will be executed only once until we'd have several
5589 boundaries per fence. */
5591 bnd_t bnd = BLIST_BND (*bndsp);
5593 if (!av_set_is_in_p (BND_AV1 (bnd), EXPR_VINSN (expr_vliw)))
5595 bndsp = &BLIST_NEXT (*bndsp);
5599 insn = schedule_expr_on_boundary (bnd, expr_vliw, seqno);
5600 last_insn_was_debug = DEBUG_INSN_P (insn);
5601 if (last_insn_was_debug)
5602 was_debug_bb_end_p = (insn == BND_TO (bnd) && sel_bb_end_p (insn));
5603 update_fence_and_insn (fence, insn, need_stall);
5604 bnds_tailp = update_boundaries (fence, bnd, insn, bndsp, bnds_tailp);
5606 /* Add insn to the list of scheduled on this cycle instructions. */
5607 ilist_add (*scheduled_insns_tailpp, insn);
5608 *scheduled_insns_tailpp = &ILIST_NEXT (**scheduled_insns_tailpp);
5610 while (*bndsp != *bnds_tailp1);
5612 av_set_clear (&av_vliw);
5613 if (!last_insn_was_debug)
5616 /* We currently support information about candidate blocks only for
5617 one 'target_bb' block. Hence we can't schedule after jump insn,
5618 as this will bring two boundaries and, hence, necessity to handle
5619 information for two or more blocks concurrently. */
5620 if ((last_insn_was_debug ? was_debug_bb_end_p : sel_bb_end_p (insn))
5622 && (was_stall >= max_stall
5623 || scheduled_insns >= max_insns)))
5628 gcc_assert (!FENCE_BNDS (fence));
5630 /* Update boundaries of the FENCE. */
5633 ilist_t ptr = BND_PTR (BLIST_BND (bnds));
5637 insn = ILIST_INSN (ptr);
5639 if (!ilist_is_in_p (FENCE_BNDS (fence), insn))
5640 ilist_add (&FENCE_BNDS (fence), insn);
5643 blist_remove (&bnds);
5646 /* Update target context on the fence. */
5647 reset_target_context (FENCE_TC (fence), false);
5650 /* All exprs in ORIG_OPS must have the same destination register or memory.
5651 Return that destination. */
5653 get_dest_from_orig_ops (av_set_t orig_ops)
5655 rtx dest = NULL_RTX;
5656 av_set_iterator av_it;
5658 bool first_p = true;
5660 FOR_EACH_EXPR (expr, av_it, orig_ops)
5662 rtx x = EXPR_LHS (expr);
5670 gcc_assert (dest == x
5671 || (dest != NULL_RTX && x != NULL_RTX
5672 && rtx_equal_p (dest, x)));
5678 /* Update data sets for the bookkeeping block and record those expressions
5679 which become no longer available after inserting this bookkeeping. */
5681 update_and_record_unavailable_insns (basic_block book_block)
5684 av_set_t old_av_set = NULL;
5686 rtx bb_end = sel_bb_end (book_block);
5688 /* First, get correct liveness in the bookkeeping block. The problem is
5689 the range between the bookeeping insn and the end of block. */
5690 update_liveness_on_insn (bb_end);
5691 if (control_flow_insn_p (bb_end))
5692 update_liveness_on_insn (PREV_INSN (bb_end));
5694 /* If there's valid av_set on BOOK_BLOCK, then there might exist another
5695 fence above, where we may choose to schedule an insn which is
5696 actually blocked from moving up with the bookkeeping we create here. */
5697 if (AV_SET_VALID_P (sel_bb_head (book_block)))
5699 old_av_set = av_set_copy (BB_AV_SET (book_block));
5700 update_data_sets (sel_bb_head (book_block));
5702 /* Traverse all the expressions in the old av_set and check whether
5703 CUR_EXPR is in new AV_SET. */
5704 FOR_EACH_EXPR (cur_expr, i, old_av_set)
5706 expr_t new_expr = av_set_lookup (BB_AV_SET (book_block),
5707 EXPR_VINSN (cur_expr));
5710 /* In this case, we can just turn off the E_T_A bit, but we can't
5711 represent this information with the current vector. */
5712 || EXPR_TARGET_AVAILABLE (new_expr)
5713 != EXPR_TARGET_AVAILABLE (cur_expr))
5714 /* Unfortunately, the below code could be also fired up on
5715 separable insns, e.g. when moving insns through the new
5716 speculation check as in PR 53701. */
5717 vinsn_vec_add (&vec_bookkeeping_blocked_vinsns, cur_expr);
5720 av_set_clear (&old_av_set);
5724 /* The main effect of this function is that sparams->c_expr is merged
5725 with (or copied to) lparams->c_expr_merged. If there's only one successor,
5726 we avoid merging anything by copying sparams->c_expr to lparams->c_expr_merged.
5727 lparams->c_expr_merged is copied back to sparams->c_expr after all
5728 successors has been traversed. lparams->c_expr_local is an expr allocated
5729 on stack in the caller function, and is used if there is more than one
5732 SUCC is one of the SUCCS_NORMAL successors of INSN,
5733 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ,
5734 LPARAMS and STATIC_PARAMS contain the parameters described above. */
5736 move_op_merge_succs (insn_t insn ATTRIBUTE_UNUSED,
5737 insn_t succ ATTRIBUTE_UNUSED,
5738 int moveop_drv_call_res,
5739 cmpd_local_params_p lparams, void *static_params)
5741 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
5743 /* Nothing to do, if original expr wasn't found below. */
5744 if (moveop_drv_call_res != 1)
5747 /* If this is a first successor. */
5748 if (!lparams->c_expr_merged)
5750 lparams->c_expr_merged = sparams->c_expr;
5751 sparams->c_expr = lparams->c_expr_local;
5755 /* We must merge all found expressions to get reasonable
5756 EXPR_SPEC_DONE_DS for the resulting insn. If we don't
5757 do so then we can first find the expr with epsilon
5758 speculation success probability and only then with the
5759 good probability. As a result the insn will get epsilon
5760 probability and will never be scheduled because of
5761 weakness_cutoff in find_best_expr.
5763 We call merge_expr_data here instead of merge_expr
5764 because due to speculation C_EXPR and X may have the
5765 same insns with different speculation types. And as of
5766 now such insns are considered non-equal.
5768 However, EXPR_SCHED_TIMES is different -- we must get
5769 SCHED_TIMES from a real insn, not a bookkeeping copy.
5770 We force this here. Instead, we may consider merging
5771 SCHED_TIMES to the maximum instead of minimum in the
5773 int old_times = EXPR_SCHED_TIMES (lparams->c_expr_merged);
5775 merge_expr_data (lparams->c_expr_merged, sparams->c_expr, NULL);
5776 if (EXPR_SCHED_TIMES (sparams->c_expr) == 0)
5777 EXPR_SCHED_TIMES (lparams->c_expr_merged) = old_times;
5779 clear_expr (sparams->c_expr);
5783 /* Add used regs for the successor SUCC into SPARAMS->USED_REGS.
5785 SUCC is one of the SUCCS_NORMAL successors of INSN,
5786 MOVEOP_DRV_CALL_RES is the result of call code_motion_path_driver on succ or 0,
5787 if SUCC is one of SUCCS_BACK or SUCCS_OUT.
5788 STATIC_PARAMS contain USED_REGS set. */
5790 fur_merge_succs (insn_t insn ATTRIBUTE_UNUSED, insn_t succ,
5791 int moveop_drv_call_res,
5792 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
5793 void *static_params)
5796 fur_static_params_p sparams = (fur_static_params_p) static_params;
5798 /* Here we compute live regsets only for branches that do not lie
5799 on the code motion paths. These branches correspond to value
5800 MOVEOP_DRV_CALL_RES==0 and include SUCCS_BACK and SUCCS_OUT, though
5801 for such branches code_motion_path_driver is not called. */
5802 if (moveop_drv_call_res != 0)
5805 /* Mark all registers that do not meet the following condition:
5806 (3) not live on the other path of any conditional branch
5807 that is passed by the operation, in case original
5808 operations are not present on both paths of the
5809 conditional branch. */
5810 succ_live = compute_live (succ);
5811 IOR_REG_SET (sparams->used_regs, succ_live);
5814 /* This function is called after the last successor. Copies LP->C_EXPR_MERGED
5817 move_op_after_merge_succs (cmpd_local_params_p lp, void *sparams)
5819 moveop_static_params_p sp = (moveop_static_params_p) sparams;
5821 sp->c_expr = lp->c_expr_merged;
5824 /* Track bookkeeping copies created, insns scheduled, and blocks for
5825 rescheduling when INSN is found by move_op. */
5827 track_scheduled_insns_and_blocks (rtx insn)
5829 /* Even if this insn can be a copy that will be removed during current move_op,
5830 we still need to count it as an originator. */
5831 bitmap_set_bit (current_originators, INSN_UID (insn));
5833 if (!bitmap_clear_bit (current_copies, INSN_UID (insn)))
5835 /* Note that original block needs to be rescheduled, as we pulled an
5836 instruction out of it. */
5837 if (INSN_SCHED_TIMES (insn) > 0)
5838 bitmap_set_bit (blocks_to_reschedule, BLOCK_FOR_INSN (insn)->index);
5839 else if (INSN_UID (insn) < first_emitted_uid && !DEBUG_INSN_P (insn))
5840 num_insns_scheduled++;
5843 /* For instructions we must immediately remove insn from the
5844 stream, so subsequent update_data_sets () won't include this
5846 For expr we must make insn look like "INSN_REG (insn) := c_expr". */
5847 if (INSN_UID (insn) > max_uid_before_move_op)
5848 stat_bookkeeping_copies--;
5851 /* Emit a register-register copy for INSN if needed. Return true if
5852 emitted one. PARAMS is the move_op static parameters. */
5854 maybe_emit_renaming_copy (rtx insn,
5855 moveop_static_params_p params)
5857 bool insn_emitted = false;
5860 /* Bail out early when expression can not be renamed at all. */
5861 if (!EXPR_SEPARABLE_P (params->c_expr))
5864 cur_reg = expr_dest_reg (params->c_expr);
5865 gcc_assert (cur_reg && params->dest && REG_P (params->dest));
5867 /* If original operation has expr and the register chosen for
5868 that expr is not original operation's dest reg, substitute
5869 operation's right hand side with the register chosen. */
5870 if (REGNO (params->dest) != REGNO (cur_reg))
5872 insn_t reg_move_insn, reg_move_insn_rtx;
5874 reg_move_insn_rtx = create_insn_rtx_with_rhs (INSN_VINSN (insn),
5876 reg_move_insn = sel_gen_insn_from_rtx_after (reg_move_insn_rtx,
5880 EXPR_SPEC_DONE_DS (INSN_EXPR (reg_move_insn)) = 0;
5881 replace_dest_with_reg_in_expr (params->c_expr, params->dest);
5883 insn_emitted = true;
5884 params->was_renamed = true;
5887 return insn_emitted;
5890 /* Emit a speculative check for INSN speculated as EXPR if needed.
5891 Return true if we've emitted one. PARAMS is the move_op static
5894 maybe_emit_speculative_check (rtx insn, expr_t expr,
5895 moveop_static_params_p params)
5897 bool insn_emitted = false;
5901 check_ds = get_spec_check_type_for_insn (insn, expr);
5904 /* A speculation check should be inserted. */
5905 x = create_speculation_check (params->c_expr, check_ds, insn);
5906 insn_emitted = true;
5910 EXPR_SPEC_DONE_DS (INSN_EXPR (insn)) = 0;
5914 gcc_assert (EXPR_SPEC_DONE_DS (INSN_EXPR (x)) == 0
5915 && EXPR_SPEC_TO_CHECK_DS (INSN_EXPR (x)) == 0);
5916 return insn_emitted;
5919 /* Handle transformations that leave an insn in place of original
5920 insn such as renaming/speculation. Return true if one of such
5921 transformations actually happened, and we have emitted this insn. */
5923 handle_emitting_transformations (rtx insn, expr_t expr,
5924 moveop_static_params_p params)
5926 bool insn_emitted = false;
5928 insn_emitted = maybe_emit_renaming_copy (insn, params);
5929 insn_emitted |= maybe_emit_speculative_check (insn, expr, params);
5931 return insn_emitted;
5934 /* If INSN is the only insn in the basic block (not counting JUMP,
5935 which may be a jump to next insn, and DEBUG_INSNs), we want to
5936 leave a NOP there till the return to fill_insns. */
5939 need_nop_to_preserve_insn_bb (rtx insn)
5941 insn_t bb_head, bb_end, bb_next, in_next;
5942 basic_block bb = BLOCK_FOR_INSN (insn);
5944 bb_head = sel_bb_head (bb);
5945 bb_end = sel_bb_end (bb);
5947 if (bb_head == bb_end)
5950 while (bb_head != bb_end && DEBUG_INSN_P (bb_head))
5951 bb_head = NEXT_INSN (bb_head);
5953 if (bb_head == bb_end)
5956 while (bb_head != bb_end && DEBUG_INSN_P (bb_end))
5957 bb_end = PREV_INSN (bb_end);
5959 if (bb_head == bb_end)
5962 bb_next = NEXT_INSN (bb_head);
5963 while (bb_next != bb_end && DEBUG_INSN_P (bb_next))
5964 bb_next = NEXT_INSN (bb_next);
5966 if (bb_next == bb_end && JUMP_P (bb_end))
5969 in_next = NEXT_INSN (insn);
5970 while (DEBUG_INSN_P (in_next))
5971 in_next = NEXT_INSN (in_next);
5973 if (IN_CURRENT_FENCE_P (in_next))
5979 /* Remove INSN from stream. When ONLY_DISCONNECT is true, its data
5980 is not removed but reused when INSN is re-emitted. */
5982 remove_insn_from_stream (rtx insn, bool only_disconnect)
5984 /* If there's only one insn in the BB, make sure that a nop is
5985 inserted into it, so the basic block won't disappear when we'll
5986 delete INSN below with sel_remove_insn. It should also survive
5987 till the return to fill_insns. */
5988 if (need_nop_to_preserve_insn_bb (insn))
5990 insn_t nop = get_nop_from_pool (insn);
5991 gcc_assert (INSN_NOP_P (nop));
5992 VEC_safe_push (insn_t, heap, vec_temp_moveop_nops, nop);
5995 sel_remove_insn (insn, only_disconnect, false);
5998 /* This function is called when original expr is found.
5999 INSN - current insn traversed, EXPR - the corresponding expr found.
6000 LPARAMS is the local parameters of code modion driver, STATIC_PARAMS
6001 is static parameters of move_op. */
6003 move_op_orig_expr_found (insn_t insn, expr_t expr,
6004 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6005 void *static_params)
6007 bool only_disconnect, insn_emitted;
6008 moveop_static_params_p params = (moveop_static_params_p) static_params;
6010 copy_expr_onside (params->c_expr, INSN_EXPR (insn));
6011 track_scheduled_insns_and_blocks (insn);
6012 insn_emitted = handle_emitting_transformations (insn, expr, params);
6013 only_disconnect = (params->uid == INSN_UID (insn)
6014 && ! insn_emitted && ! EXPR_WAS_CHANGED (expr));
6016 /* Mark that we've disconnected an insn. */
6017 if (only_disconnect)
6019 remove_insn_from_stream (insn, only_disconnect);
6022 /* The function is called when original expr is found.
6023 INSN - current insn traversed, EXPR - the corresponding expr found,
6024 crosses_call and original_insns in STATIC_PARAMS are updated. */
6026 fur_orig_expr_found (insn_t insn, expr_t expr ATTRIBUTE_UNUSED,
6027 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6028 void *static_params)
6030 fur_static_params_p params = (fur_static_params_p) static_params;
6034 params->crosses_call = true;
6036 def_list_add (params->original_insns, insn, params->crosses_call);
6038 /* Mark the registers that do not meet the following condition:
6039 (2) not among the live registers of the point
6040 immediately following the first original operation on
6041 a given downward path, except for the original target
6042 register of the operation. */
6043 tmp = get_clear_regset_from_pool ();
6044 compute_live_below_insn (insn, tmp);
6045 AND_COMPL_REG_SET (tmp, INSN_REG_SETS (insn));
6046 AND_COMPL_REG_SET (tmp, INSN_REG_CLOBBERS (insn));
6047 IOR_REG_SET (params->used_regs, tmp);
6048 return_regset_to_pool (tmp);
6050 /* (*1) We need to add to USED_REGS registers that are read by
6051 INSN's lhs. This may lead to choosing wrong src register.
6052 E.g. (scheduling const expr enabled):
6054 429: ax=0x0 <- Can't use AX for this expr (0x0)
6061 /* FIXME: see comment above and enable MEM_P
6062 in vinsn_separable_p. */
6063 gcc_assert (!VINSN_SEPARABLE_P (INSN_VINSN (insn))
6064 || !MEM_P (INSN_LHS (insn)));
6067 /* This function is called on the ascending pass, before returning from
6068 current basic block. */
6070 move_op_at_first_insn (insn_t insn, cmpd_local_params_p lparams,
6071 void *static_params)
6073 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6074 basic_block book_block = NULL;
6076 /* When we have removed the boundary insn for scheduling, which also
6077 happened to be the end insn in its bb, we don't need to update sets. */
6078 if (!lparams->removed_last_insn
6080 && sel_bb_head_p (insn))
6082 /* We should generate bookkeeping code only if we are not at the
6083 top level of the move_op. */
6084 if (sel_num_cfg_preds_gt_1 (insn))
6085 book_block = generate_bookkeeping_insn (sparams->c_expr,
6086 lparams->e1, lparams->e2);
6087 /* Update data sets for the current insn. */
6088 update_data_sets (insn);
6091 /* If bookkeeping code was inserted, we need to update av sets of basic
6092 block that received bookkeeping. After generation of bookkeeping insn,
6093 bookkeeping block does not contain valid av set because we are not following
6094 the original algorithm in every detail with regards to e.g. renaming
6095 simple reg-reg copies. Consider example:
6097 bookkeeping block scheduling fence
6107 We try to schedule insn "r1 := r3" on the current
6108 scheduling fence. Also, note that av set of bookkeeping block
6109 contain both insns "r1 := r2" and "r1 := r3". When the insn has
6110 been scheduled, the CFG is as follows:
6113 bookkeeping block scheduling fence
6123 Here, insn "r1 := r3" was scheduled at the current scheduling point
6124 and bookkeeping code was generated at the bookeeping block. This
6125 way insn "r1 := r2" is no longer available as a whole instruction
6126 (but only as expr) ahead of insn "r1 := r3" in bookkeeping block.
6127 This situation is handled by calling update_data_sets.
6129 Since update_data_sets is called only on the bookkeeping block, and
6130 it also may have predecessors with av_sets, containing instructions that
6131 are no longer available, we save all such expressions that become
6132 unavailable during data sets update on the bookkeeping block in
6133 VEC_BOOKKEEPING_BLOCKED_VINSNS. Later we avoid selecting such
6134 expressions for scheduling. This allows us to avoid recomputation of
6135 av_sets outside the code motion path. */
6138 update_and_record_unavailable_insns (book_block);
6140 /* If INSN was previously marked for deletion, it's time to do it. */
6141 if (lparams->removed_last_insn)
6142 insn = PREV_INSN (insn);
6144 /* Do not tidy control flow at the topmost moveop, as we can erroneously
6145 kill a block with a single nop in which the insn should be emitted. */
6147 tidy_control_flow (BLOCK_FOR_INSN (insn), true);
6150 /* This function is called on the ascending pass, before returning from the
6151 current basic block. */
6153 fur_at_first_insn (insn_t insn,
6154 cmpd_local_params_p lparams ATTRIBUTE_UNUSED,
6155 void *static_params ATTRIBUTE_UNUSED)
6157 gcc_assert (!sel_bb_head_p (insn) || AV_SET_VALID_P (insn)
6158 || AV_LEVEL (insn) == -1);
6161 /* Called on the backward stage of recursion to call moveup_expr for insn
6162 and sparams->c_expr. */
6164 move_op_ascend (insn_t insn, void *static_params)
6166 enum MOVEUP_EXPR_CODE res;
6167 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6169 if (! INSN_NOP_P (insn))
6171 res = moveup_expr_cached (sparams->c_expr, insn, false);
6172 gcc_assert (res != MOVEUP_EXPR_NULL);
6175 /* Update liveness for this insn as it was invalidated. */
6176 update_liveness_on_insn (insn);
6179 /* This function is called on enter to the basic block.
6180 Returns TRUE if this block already have been visited and
6181 code_motion_path_driver should return 1, FALSE otherwise. */
6183 fur_on_enter (insn_t insn ATTRIBUTE_UNUSED, cmpd_local_params_p local_params,
6184 void *static_params, bool visited_p)
6186 fur_static_params_p sparams = (fur_static_params_p) static_params;
6190 /* If we have found something below this block, there should be at
6191 least one insn in ORIGINAL_INSNS. */
6192 gcc_assert (*sparams->original_insns);
6194 /* Adjust CROSSES_CALL, since we may have come to this block along
6196 DEF_LIST_DEF (*sparams->original_insns)->crosses_call
6197 |= sparams->crosses_call;
6200 local_params->old_original_insns = *sparams->original_insns;
6205 /* Same as above but for move_op. */
6207 move_op_on_enter (insn_t insn ATTRIBUTE_UNUSED,
6208 cmpd_local_params_p local_params ATTRIBUTE_UNUSED,
6209 void *static_params ATTRIBUTE_UNUSED, bool visited_p)
6216 /* This function is called while descending current basic block if current
6217 insn is not the original EXPR we're searching for.
6219 Return value: FALSE, if code_motion_path_driver should perform a local
6220 cleanup and return 0 itself;
6221 TRUE, if code_motion_path_driver should continue. */
6223 move_op_orig_expr_not_found (insn_t insn, av_set_t orig_ops ATTRIBUTE_UNUSED,
6224 void *static_params)
6226 moveop_static_params_p sparams = (moveop_static_params_p) static_params;
6228 #ifdef ENABLE_CHECKING
6229 sparams->failed_insn = insn;
6232 /* If we're scheduling separate expr, in order to generate correct code
6233 we need to stop the search at bookkeeping code generated with the
6234 same destination register or memory. */
6235 if (lhs_of_insn_equals_to_dest_p (insn, sparams->dest))
6240 /* This function is called while descending current basic block if current
6241 insn is not the original EXPR we're searching for.
6243 Return value: TRUE (code_motion_path_driver should continue). */
6245 fur_orig_expr_not_found (insn_t insn, av_set_t orig_ops, void *static_params)
6249 av_set_iterator avi;
6250 fur_static_params_p sparams = (fur_static_params_p) static_params;
6253 sparams->crosses_call = true;
6254 else if (DEBUG_INSN_P (insn))
6257 /* If current insn we are looking at cannot be executed together
6258 with original insn, then we can skip it safely.
6260 Example: ORIG_OPS = { (p6) r14 = sign_extend (r15); }
6261 INSN = (!p6) r14 = r14 + 1;
6263 Here we can schedule ORIG_OP with lhs = r14, though only
6264 looking at the set of used and set registers of INSN we must
6265 forbid it. So, add set/used in INSN registers to the
6266 untouchable set only if there is an insn in ORIG_OPS that can
6269 FOR_EACH_EXPR (r, avi, orig_ops)
6270 if (!sched_insns_conditions_mutex_p (insn, EXPR_INSN_RTX (r)))
6276 /* Mark all registers that do not meet the following condition:
6277 (1) Not set or read on any path from xi to an instance of the
6278 original operation. */
6281 IOR_REG_SET (sparams->used_regs, INSN_REG_SETS (insn));
6282 IOR_REG_SET (sparams->used_regs, INSN_REG_USES (insn));
6283 IOR_REG_SET (sparams->used_regs, INSN_REG_CLOBBERS (insn));
6289 /* Hooks and data to perform move_op operations with code_motion_path_driver. */
6290 struct code_motion_path_driver_info_def move_op_hooks = {
6292 move_op_orig_expr_found,
6293 move_op_orig_expr_not_found,
6294 move_op_merge_succs,
6295 move_op_after_merge_succs,
6297 move_op_at_first_insn,
6302 /* Hooks and data to perform find_used_regs operations
6303 with code_motion_path_driver. */
6304 struct code_motion_path_driver_info_def fur_hooks = {
6306 fur_orig_expr_found,
6307 fur_orig_expr_not_found,
6309 NULL, /* fur_after_merge_succs */
6310 NULL, /* fur_ascend */
6316 /* Traverse all successors of INSN. For each successor that is SUCCS_NORMAL
6317 code_motion_path_driver is called recursively. Original operation
6318 was found at least on one path that is starting with one of INSN's
6319 successors (this fact is asserted). ORIG_OPS is expressions we're looking
6320 for, PATH is the path we've traversed, STATIC_PARAMS is the parameters
6321 of either move_op or find_used_regs depending on the caller.
6323 Return 0 if we haven't found expression, 1 if we found it, -1 if we don't
6324 know for sure at this point. */
6326 code_motion_process_successors (insn_t insn, av_set_t orig_ops,
6327 ilist_t path, void *static_params)
6330 succ_iterator succ_i;
6336 struct cmpd_local_params lparams;
6339 lparams.c_expr_local = &_x;
6340 lparams.c_expr_merged = NULL;
6342 /* We need to process only NORMAL succs for move_op, and collect live
6343 registers from ALL branches (including those leading out of the
6344 region) for find_used_regs.
6346 In move_op, there can be a case when insn's bb number has changed
6347 due to created bookkeeping. This happens very rare, as we need to
6348 move expression from the beginning to the end of the same block.
6349 Rescan successors in this case. */
6352 bb = BLOCK_FOR_INSN (insn);
6353 old_index = bb->index;
6354 old_succs = EDGE_COUNT (bb->succs);
6356 FOR_EACH_SUCC_1 (succ, succ_i, insn, code_motion_path_driver_info->succ_flags)
6360 lparams.e1 = succ_i.e1;
6361 lparams.e2 = succ_i.e2;
6363 /* Go deep into recursion only for NORMAL edges (non-backedges within the
6365 if (succ_i.current_flags == SUCCS_NORMAL)
6366 b = code_motion_path_driver (succ, orig_ops, path, &lparams,
6371 /* Merge c_expres found or unify live register sets from different
6373 code_motion_path_driver_info->merge_succs (insn, succ, b, &lparams,
6377 else if (b == -1 && res != 1)
6380 /* We have simplified the control flow below this point. In this case,
6381 the iterator becomes invalid. We need to try again. */
6382 if (BLOCK_FOR_INSN (insn)->index != old_index
6383 || EDGE_COUNT (bb->succs) != old_succs)
6387 #ifdef ENABLE_CHECKING
6388 /* Here, RES==1 if original expr was found at least for one of the
6389 successors. After the loop, RES may happen to have zero value
6390 only if at some point the expr searched is present in av_set, but is
6391 not found below. In most cases, this situation is an error.
6392 The exception is when the original operation is blocked by
6393 bookkeeping generated for another fence or for another path in current
6395 gcc_assert (res == 1
6397 && av_set_could_be_blocked_by_bookkeeping_p (orig_ops,
6402 /* Merge data, clean up, etc. */
6403 if (res != -1 && code_motion_path_driver_info->after_merge_succs)
6404 code_motion_path_driver_info->after_merge_succs (&lparams, static_params);
6410 /* Perform a cleanup when the driver is about to terminate. ORIG_OPS_P
6411 is the pointer to the av set with expressions we were looking for,
6412 PATH_P is the pointer to the traversed path. */
6414 code_motion_path_driver_cleanup (av_set_t *orig_ops_p, ilist_t *path_p)
6416 ilist_remove (path_p);
6417 av_set_clear (orig_ops_p);
6420 /* The driver function that implements move_op or find_used_regs
6421 functionality dependent whether code_motion_path_driver_INFO is set to
6422 &MOVE_OP_HOOKS or &FUR_HOOKS. This function implements the common parts
6423 of code (CFG traversal etc) that are shared among both functions. INSN
6424 is the insn we're starting the search from, ORIG_OPS are the expressions
6425 we're searching for, PATH is traversed path, LOCAL_PARAMS_IN are local
6426 parameters of the driver, and STATIC_PARAMS are static parameters of
6429 Returns whether original instructions were found. Note that top-level
6430 code_motion_path_driver always returns true. */
6432 code_motion_path_driver (insn_t insn, av_set_t orig_ops, ilist_t path,
6433 cmpd_local_params_p local_params_in,
6434 void *static_params)
6437 basic_block bb = BLOCK_FOR_INSN (insn);
6438 insn_t first_insn, bb_tail, before_first;
6439 bool removed_last_insn = false;
6441 if (sched_verbose >= 6)
6443 sel_print ("%s (", code_motion_path_driver_info->routine_name);
6446 dump_av_set (orig_ops);
6450 gcc_assert (orig_ops);
6452 /* If no original operations exist below this insn, return immediately. */
6453 if (is_ineligible_successor (insn, path))
6455 if (sched_verbose >= 6)
6456 sel_print ("Insn %d is ineligible successor\n", INSN_UID (insn));
6460 /* The block can have invalid av set, in which case it was created earlier
6461 during move_op. Return immediately. */
6462 if (sel_bb_head_p (insn))
6464 if (! AV_SET_VALID_P (insn))
6466 if (sched_verbose >= 6)
6467 sel_print ("Returned from block %d as it had invalid av set\n",
6472 if (bitmap_bit_p (code_motion_visited_blocks, bb->index))
6474 /* We have already found an original operation on this branch, do not
6475 go any further and just return TRUE here. If we don't stop here,
6476 function can have exponential behaviour even on the small code
6477 with many different paths (e.g. with data speculation and
6478 recovery blocks). */
6479 if (sched_verbose >= 6)
6480 sel_print ("Block %d already visited in this traversal\n", bb->index);
6481 if (code_motion_path_driver_info->on_enter)
6482 return code_motion_path_driver_info->on_enter (insn,
6489 if (code_motion_path_driver_info->on_enter)
6490 code_motion_path_driver_info->on_enter (insn, local_params_in,
6491 static_params, false);
6492 orig_ops = av_set_copy (orig_ops);
6494 /* Filter the orig_ops set. */
6495 if (AV_SET_VALID_P (insn))
6496 av_set_code_motion_filter (&orig_ops, AV_SET (insn));
6498 /* If no more original ops, return immediately. */
6501 if (sched_verbose >= 6)
6502 sel_print ("No intersection with av set of block %d\n", bb->index);
6506 /* For non-speculative insns we have to leave only one form of the
6507 original operation, because if we don't, we may end up with
6508 different C_EXPRes and, consequently, with bookkeepings for different
6509 expression forms along the same code motion path. That may lead to
6510 generation of incorrect code. So for each code motion we stick to
6511 the single form of the instruction, except for speculative insns
6512 which we need to keep in different forms with all speculation
6514 av_set_leave_one_nonspec (&orig_ops);
6516 /* It is not possible that all ORIG_OPS are filtered out. */
6517 gcc_assert (orig_ops);
6519 /* It is enough to place only heads and tails of visited basic blocks into
6521 ilist_add (&path, insn);
6523 bb_tail = sel_bb_end (bb);
6525 /* Descend the basic block in search of the original expr; this part
6526 corresponds to the part of the original move_op procedure executed
6527 before the recursive call. */
6530 /* Look at the insn and decide if it could be an ancestor of currently
6531 scheduling operation. If it is so, then the insn "dest = op" could
6532 either be replaced with "dest = reg", because REG now holds the result
6533 of OP, or just removed, if we've scheduled the insn as a whole.
6535 If this insn doesn't contain currently scheduling OP, then proceed
6536 with searching and look at its successors. Operations we're searching
6537 for could have changed when moving up through this insn via
6538 substituting. In this case, perform unsubstitution on them first.
6540 When traversing the DAG below this insn is finished, insert
6541 bookkeeping code, if the insn is a joint point, and remove
6544 expr = av_set_lookup (orig_ops, INSN_VINSN (insn));
6547 insn_t last_insn = PREV_INSN (insn);
6549 /* We have found the original operation. */
6550 if (sched_verbose >= 6)
6551 sel_print ("Found original operation at insn %d\n", INSN_UID (insn));
6553 code_motion_path_driver_info->orig_expr_found
6554 (insn, expr, local_params_in, static_params);
6556 /* Step back, so on the way back we'll start traversing from the
6557 previous insn (or we'll see that it's bb_note and skip that
6559 if (insn == first_insn)
6561 first_insn = NEXT_INSN (last_insn);
6562 removed_last_insn = sel_bb_end_p (last_insn);
6569 /* We haven't found the original expr, continue descending the basic
6571 if (code_motion_path_driver_info->orig_expr_not_found
6572 (insn, orig_ops, static_params))
6574 /* Av set ops could have been changed when moving through this
6575 insn. To find them below it, we have to un-substitute them. */
6576 undo_transformations (&orig_ops, insn);
6580 /* Clean up and return, if the hook tells us to do so. It may
6581 happen if we've encountered the previously created
6583 code_motion_path_driver_cleanup (&orig_ops, &path);
6587 gcc_assert (orig_ops);
6590 /* Stop at insn if we got to the end of BB. */
6591 if (insn == bb_tail)
6594 insn = NEXT_INSN (insn);
6597 /* Here INSN either points to the insn before the original insn (may be
6598 bb_note, if original insn was a bb_head) or to the bb_end. */
6603 gcc_assert (insn == sel_bb_end (bb));
6605 /* Add bb tail to PATH (but it doesn't make any sense if it's a bb_head -
6606 it's already in PATH then). */
6607 if (insn != first_insn)
6608 ilist_add (&path, insn);
6610 /* Process_successors should be able to find at least one
6611 successor for which code_motion_path_driver returns TRUE. */
6612 res = code_motion_process_successors (insn, orig_ops,
6613 path, static_params);
6615 /* Remove bb tail from path. */
6616 if (insn != first_insn)
6617 ilist_remove (&path);
6621 /* This is the case when one of the original expr is no longer available
6622 due to bookkeeping created on this branch with the same register.
6623 In the original algorithm, which doesn't have update_data_sets call
6624 on a bookkeeping block, it would simply result in returning
6625 FALSE when we've encountered a previously generated bookkeeping
6626 insn in moveop_orig_expr_not_found. */
6627 code_motion_path_driver_cleanup (&orig_ops, &path);
6632 /* Don't need it any more. */
6633 av_set_clear (&orig_ops);
6635 /* Backward pass: now, when we have C_EXPR computed, we'll drag it to
6636 the beginning of the basic block. */
6637 before_first = PREV_INSN (first_insn);
6638 while (insn != before_first)
6640 if (code_motion_path_driver_info->ascend)
6641 code_motion_path_driver_info->ascend (insn, static_params);
6643 insn = PREV_INSN (insn);
6646 /* Now we're at the bb head. */
6648 ilist_remove (&path);
6649 local_params_in->removed_last_insn = removed_last_insn;
6650 code_motion_path_driver_info->at_first_insn (insn, local_params_in, static_params);
6652 /* This should be the very last operation as at bb head we could change
6653 the numbering by creating bookkeeping blocks. */
6654 if (removed_last_insn)
6655 insn = PREV_INSN (insn);
6656 bitmap_set_bit (code_motion_visited_blocks, BLOCK_FOR_INSN (insn)->index);
6660 /* Move up the operations from ORIG_OPS set traversing the dag starting
6661 from INSN. PATH represents the edges traversed so far.
6662 DEST is the register chosen for scheduling the current expr. Insert
6663 bookkeeping code in the join points. EXPR_VLIW is the chosen expression,
6664 C_EXPR is how it looks like at the given cfg point.
6665 Set *SHOULD_MOVE to indicate whether we have only disconnected
6666 one of the insns found.
6668 Returns whether original instructions were found, which is asserted
6669 to be true in the caller. */
6671 move_op (insn_t insn, av_set_t orig_ops, expr_t expr_vliw,
6672 rtx dest, expr_t c_expr, bool *should_move)
6674 struct moveop_static_params sparams;
6675 struct cmpd_local_params lparams;
6678 /* Init params for code_motion_path_driver. */
6679 sparams.dest = dest;
6680 sparams.c_expr = c_expr;
6681 sparams.uid = INSN_UID (EXPR_INSN_RTX (expr_vliw));
6682 #ifdef ENABLE_CHECKING
6683 sparams.failed_insn = NULL;
6685 sparams.was_renamed = false;
6688 /* We haven't visited any blocks yet. */
6689 bitmap_clear (code_motion_visited_blocks);
6691 /* Set appropriate hooks and data. */
6692 code_motion_path_driver_info = &move_op_hooks;
6693 res = code_motion_path_driver (insn, orig_ops, NULL, &lparams, &sparams);
6695 if (sparams.was_renamed)
6696 EXPR_WAS_RENAMED (expr_vliw) = true;
6698 *should_move = (sparams.uid == -1);
6704 /* Functions that work with regions. */
6706 /* Current number of seqno used in init_seqno and init_seqno_1. */
6707 static int cur_seqno;
6709 /* A helper for init_seqno. Traverse the region starting from BB and
6710 compute seqnos for visited insns, marking visited bbs in VISITED_BBS.
6711 Clear visited blocks from BLOCKS_TO_RESCHEDULE. */
6713 init_seqno_1 (basic_block bb, sbitmap visited_bbs, bitmap blocks_to_reschedule)
6715 int bbi = BLOCK_TO_BB (bb->index);
6716 insn_t insn, note = bb_note (bb);
6720 SET_BIT (visited_bbs, bbi);
6721 if (blocks_to_reschedule)
6722 bitmap_clear_bit (blocks_to_reschedule, bb->index);
6724 FOR_EACH_SUCC_1 (succ_insn, si, BB_END (bb),
6725 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
6727 basic_block succ = BLOCK_FOR_INSN (succ_insn);
6728 int succ_bbi = BLOCK_TO_BB (succ->index);
6730 gcc_assert (in_current_region_p (succ));
6732 if (!TEST_BIT (visited_bbs, succ_bbi))
6734 gcc_assert (succ_bbi > bbi);
6736 init_seqno_1 (succ, visited_bbs, blocks_to_reschedule);
6738 else if (blocks_to_reschedule)
6739 bitmap_set_bit (forced_ebb_heads, succ->index);
6742 for (insn = BB_END (bb); insn != note; insn = PREV_INSN (insn))
6743 INSN_SEQNO (insn) = cur_seqno--;
6746 /* Initialize seqnos for the current region. NUMBER_OF_INSNS is the number
6747 of instructions in the region, BLOCKS_TO_RESCHEDULE contains blocks on
6748 which we're rescheduling when pipelining, FROM is the block where
6749 traversing region begins (it may not be the head of the region when
6750 pipelining, but the head of the loop instead).
6752 Returns the maximal seqno found. */
6754 init_seqno (int number_of_insns, bitmap blocks_to_reschedule, basic_block from)
6756 sbitmap visited_bbs;
6760 visited_bbs = sbitmap_alloc (current_nr_blocks);
6762 if (blocks_to_reschedule)
6764 sbitmap_ones (visited_bbs);
6765 EXECUTE_IF_SET_IN_BITMAP (blocks_to_reschedule, 0, bbi, bi)
6767 gcc_assert (BLOCK_TO_BB (bbi) < current_nr_blocks);
6768 RESET_BIT (visited_bbs, BLOCK_TO_BB (bbi));
6773 sbitmap_zero (visited_bbs);
6774 from = EBB_FIRST_BB (0);
6777 cur_seqno = number_of_insns > 0 ? number_of_insns : sched_max_luid - 1;
6778 init_seqno_1 (from, visited_bbs, blocks_to_reschedule);
6779 gcc_assert (cur_seqno == 0 || number_of_insns == 0);
6781 sbitmap_free (visited_bbs);
6782 return sched_max_luid - 1;
6785 /* Initialize scheduling parameters for current region. */
6787 sel_setup_region_sched_flags (void)
6789 enable_schedule_as_rhs_p = 1;
6791 pipelining_p = (bookkeeping_p
6792 && (flag_sel_sched_pipelining != 0)
6793 && current_loop_nest != NULL
6794 && loop_has_exit_edges (current_loop_nest));
6795 max_insns_to_rename = PARAM_VALUE (PARAM_SELSCHED_INSNS_TO_RENAME);
6799 /* Return true if all basic blocks of current region are empty. */
6801 current_region_empty_p (void)
6804 for (i = 0; i < current_nr_blocks; i++)
6805 if (! sel_bb_empty_p (BASIC_BLOCK (BB_TO_BLOCK (i))))
6811 /* Prepare and verify loop nest for pipelining. */
6813 setup_current_loop_nest (int rgn)
6815 current_loop_nest = get_loop_nest_for_rgn (rgn);
6817 if (!current_loop_nest)
6820 /* If this loop has any saved loop preheaders from nested loops,
6821 add these basic blocks to the current region. */
6822 sel_add_loop_preheaders ();
6824 /* Check that we're starting with a valid information. */
6825 gcc_assert (loop_latch_edge (current_loop_nest));
6826 gcc_assert (LOOP_MARKED_FOR_PIPELINING_P (current_loop_nest));
6829 /* Compute instruction priorities for current region. */
6831 sel_compute_priorities (int rgn)
6833 sched_rgn_compute_dependencies (rgn);
6835 /* Compute insn priorities in haifa style. Then free haifa style
6836 dependencies that we've calculated for this. */
6837 compute_priorities ();
6839 if (sched_verbose >= 5)
6840 debug_rgn_dependencies (0);
6845 /* Init scheduling data for RGN. Returns true when this region should not
6848 sel_region_init (int rgn)
6853 rgn_setup_region (rgn);
6855 /* Even if sched_is_disabled_for_current_region_p() is true, we still
6856 do region initialization here so the region can be bundled correctly,
6857 but we'll skip the scheduling in sel_sched_region (). */
6858 if (current_region_empty_p ())
6861 if (flag_sel_sched_pipelining)
6862 setup_current_loop_nest (rgn);
6864 sel_setup_region_sched_flags ();
6866 bbs = VEC_alloc (basic_block, heap, current_nr_blocks);
6868 for (i = 0; i < current_nr_blocks; i++)
6869 VEC_quick_push (basic_block, bbs, BASIC_BLOCK (BB_TO_BLOCK (i)));
6871 sel_init_bbs (bbs, NULL);
6873 /* Initialize luids and dependence analysis which both sel-sched and haifa
6875 sched_init_luids (bbs, NULL, NULL, NULL);
6876 sched_deps_init (false);
6878 /* Initialize haifa data. */
6879 rgn_setup_sched_infos ();
6880 sel_set_sched_flags ();
6881 haifa_init_h_i_d (bbs, NULL, NULL, NULL);
6883 sel_compute_priorities (rgn);
6884 init_deps_global ();
6886 /* Main initialization. */
6887 sel_setup_sched_infos ();
6888 sel_init_global_and_expr (bbs);
6890 VEC_free (basic_block, heap, bbs);
6892 blocks_to_reschedule = BITMAP_ALLOC (NULL);
6894 /* Init correct liveness sets on each instruction of a single-block loop.
6895 This is the only situation when we can't update liveness when calling
6896 compute_live for the first insn of the loop. */
6897 if (current_loop_nest)
6899 int header = (sel_is_loop_preheader_p (BASIC_BLOCK (BB_TO_BLOCK (0)))
6903 if (current_nr_blocks == header + 1)
6904 update_liveness_on_insn
6905 (sel_bb_head (BASIC_BLOCK (BB_TO_BLOCK (header))));
6908 /* Set hooks so that no newly generated insn will go out unnoticed. */
6909 sel_register_cfg_hooks ();
6911 /* !!! We call target.sched.init () for the whole region, but we invoke
6912 targetm.sched.finish () for every ebb. */
6913 if (targetm.sched.init)
6914 /* None of the arguments are actually used in any target. */
6915 targetm.sched.init (sched_dump, sched_verbose, -1);
6917 first_emitted_uid = get_max_uid () + 1;
6918 preheader_removed = false;
6920 /* Reset register allocation ticks array. */
6921 memset (reg_rename_tick, 0, sizeof reg_rename_tick);
6922 reg_rename_this_tick = 0;
6924 bitmap_initialize (forced_ebb_heads, 0);
6925 bitmap_clear (forced_ebb_heads);
6928 current_copies = BITMAP_ALLOC (NULL);
6929 current_originators = BITMAP_ALLOC (NULL);
6930 code_motion_visited_blocks = BITMAP_ALLOC (NULL);
6935 /* Simplify insns after the scheduling. */
6937 simplify_changed_insns (void)
6941 for (i = 0; i < current_nr_blocks; i++)
6943 basic_block bb = BASIC_BLOCK (BB_TO_BLOCK (i));
6946 FOR_BB_INSNS (bb, insn)
6949 expr_t expr = INSN_EXPR (insn);
6951 if (EXPR_WAS_SUBSTITUTED (expr))
6952 validate_simplify_insn (insn);
6957 /* Find boundaries of the EBB starting from basic block BB, marking blocks of
6958 this EBB in SCHEDULED_BLOCKS and appropriately filling in HEAD, TAIL,
6959 PREV_HEAD, and NEXT_TAIL fields of CURRENT_SCHED_INFO structure. */
6961 find_ebb_boundaries (basic_block bb, bitmap scheduled_blocks)
6964 basic_block bb1 = bb;
6965 if (sched_verbose >= 2)
6966 sel_print ("Finishing schedule in bbs: ");
6970 bitmap_set_bit (scheduled_blocks, BLOCK_TO_BB (bb1->index));
6972 if (sched_verbose >= 2)
6973 sel_print ("%d; ", bb1->index);
6975 while (!bb_ends_ebb_p (bb1) && (bb1 = bb_next_bb (bb1)));
6977 if (sched_verbose >= 2)
6980 get_ebb_head_tail (bb, bb1, &head, &tail);
6982 current_sched_info->head = head;
6983 current_sched_info->tail = tail;
6984 current_sched_info->prev_head = PREV_INSN (head);
6985 current_sched_info->next_tail = NEXT_INSN (tail);
6988 /* Regenerate INSN_SCHED_CYCLEs for insns of current EBB. */
6990 reset_sched_cycles_in_current_ebb (void)
6993 int haifa_last_clock = -1;
6994 int haifa_clock = 0;
6995 int issued_insns = 0;
6998 if (targetm.sched.init)
7000 /* None of the arguments are actually used in any target.
7001 NB: We should have md_reset () hook for cases like this. */
7002 targetm.sched.init (sched_dump, sched_verbose, -1);
7005 state_reset (curr_state);
7006 advance_state (curr_state);
7008 for (insn = current_sched_info->head;
7009 insn != current_sched_info->next_tail;
7010 insn = NEXT_INSN (insn))
7012 int cost, haifa_cost;
7014 bool asm_p, real_insn, after_stall, all_issued;
7021 real_insn = recog_memoized (insn) >= 0;
7022 clock = INSN_SCHED_CYCLE (insn);
7024 cost = clock - last_clock;
7026 /* Initialize HAIFA_COST. */
7029 asm_p = INSN_ASM_P (insn);
7032 /* This is asm insn which *had* to be scheduled first
7036 /* This is a use/clobber insn. It should not change
7041 haifa_cost = estimate_insn_cost (insn, curr_state);
7043 /* Stall for whatever cycles we've stalled before. */
7045 if (INSN_AFTER_STALL_P (insn) && cost > haifa_cost)
7050 all_issued = issued_insns == issue_rate;
7051 if (haifa_cost == 0 && all_issued)
7057 while (haifa_cost--)
7059 advance_state (curr_state);
7063 if (sched_verbose >= 2)
7065 sel_print ("advance_state (state_transition)\n");
7066 debug_state (curr_state);
7069 /* The DFA may report that e.g. insn requires 2 cycles to be
7070 issued, but on the next cycle it says that insn is ready
7071 to go. Check this here. */
7075 && estimate_insn_cost (insn, curr_state) == 0)
7078 /* When the data dependency stall is longer than the DFA stall,
7079 and when we have issued exactly issue_rate insns and stalled,
7080 it could be that after this longer stall the insn will again
7081 become unavailable to the DFA restrictions. Looks strange
7082 but happens e.g. on x86-64. So recheck DFA on the last
7084 if ((after_stall || all_issued)
7087 haifa_cost = estimate_insn_cost (insn, curr_state);
7091 if (sched_verbose >= 2)
7092 sel_print ("haifa clock: %d\n", haifa_clock);
7095 gcc_assert (haifa_cost == 0);
7097 if (sched_verbose >= 2)
7098 sel_print ("Haifa cost for insn %d: %d\n", INSN_UID (insn), haifa_cost);
7100 if (targetm.sched.dfa_new_cycle)
7101 while (targetm.sched.dfa_new_cycle (sched_dump, sched_verbose, insn,
7102 haifa_last_clock, haifa_clock,
7105 advance_state (curr_state);
7108 if (sched_verbose >= 2)
7110 sel_print ("advance_state (dfa_new_cycle)\n");
7111 debug_state (curr_state);
7112 sel_print ("haifa clock: %d\n", haifa_clock + 1);
7118 cost = state_transition (curr_state, insn);
7121 if (sched_verbose >= 2)
7123 sel_print ("scheduled insn %d, clock %d\n", INSN_UID (insn),
7125 debug_state (curr_state);
7127 gcc_assert (cost < 0);
7130 if (targetm.sched.variable_issue)
7131 targetm.sched.variable_issue (sched_dump, sched_verbose, insn, 0);
7133 INSN_SCHED_CYCLE (insn) = haifa_clock;
7136 haifa_last_clock = haifa_clock;
7140 /* Put TImode markers on insns starting a new issue group. */
7144 int last_clock = -1;
7147 for (insn = current_sched_info->head; insn != current_sched_info->next_tail;
7148 insn = NEXT_INSN (insn))
7155 clock = INSN_SCHED_CYCLE (insn);
7156 cost = (last_clock == -1) ? 1 : clock - last_clock;
7158 gcc_assert (cost >= 0);
7161 && GET_CODE (PATTERN (insn)) != USE
7162 && GET_CODE (PATTERN (insn)) != CLOBBER)
7164 if (reload_completed && cost > 0)
7165 PUT_MODE (insn, TImode);
7170 if (sched_verbose >= 2)
7171 sel_print ("Cost for insn %d is %d\n", INSN_UID (insn), cost);
7175 /* Perform MD_FINISH on EBBs comprising current region. When
7176 RESET_SCHED_CYCLES_P is true, run a pass emulating the scheduler
7177 to produce correct sched cycles on insns. */
7179 sel_region_target_finish (bool reset_sched_cycles_p)
7182 bitmap scheduled_blocks = BITMAP_ALLOC (NULL);
7184 for (i = 0; i < current_nr_blocks; i++)
7186 if (bitmap_bit_p (scheduled_blocks, i))
7189 /* While pipelining outer loops, skip bundling for loop
7190 preheaders. Those will be rescheduled in the outer loop. */
7191 if (sel_is_loop_preheader_p (EBB_FIRST_BB (i)))
7194 find_ebb_boundaries (EBB_FIRST_BB (i), scheduled_blocks);
7196 if (no_real_insns_p (current_sched_info->head, current_sched_info->tail))
7199 if (reset_sched_cycles_p)
7200 reset_sched_cycles_in_current_ebb ();
7202 if (targetm.sched.init)
7203 targetm.sched.init (sched_dump, sched_verbose, -1);
7207 if (targetm.sched.finish)
7209 targetm.sched.finish (sched_dump, sched_verbose);
7211 /* Extend luids so that insns generated by the target will
7213 sched_init_luids (NULL, NULL, NULL, NULL);
7217 BITMAP_FREE (scheduled_blocks);
7220 /* Free the scheduling data for the current region. When RESET_SCHED_CYCLES_P
7221 is true, make an additional pass emulating scheduler to get correct insn
7222 cycles for md_finish calls. */
7224 sel_region_finish (bool reset_sched_cycles_p)
7226 simplify_changed_insns ();
7227 sched_finish_ready_list ();
7230 /* Free the vectors. */
7232 VEC_free (expr_t, heap, vec_av_set);
7233 BITMAP_FREE (current_copies);
7234 BITMAP_FREE (current_originators);
7235 BITMAP_FREE (code_motion_visited_blocks);
7236 vinsn_vec_free (&vec_bookkeeping_blocked_vinsns);
7237 vinsn_vec_free (&vec_target_unavailable_vinsns);
7239 /* If LV_SET of the region head should be updated, do it now because
7240 there will be no other chance. */
7245 FOR_EACH_SUCC_1 (insn, si, bb_note (EBB_FIRST_BB (0)),
7246 SUCCS_NORMAL | SUCCS_SKIP_TO_LOOP_EXITS)
7248 basic_block bb = BLOCK_FOR_INSN (insn);
7250 if (!BB_LV_SET_VALID_P (bb))
7251 compute_live (insn);
7255 /* Emulate the Haifa scheduler for bundling. */
7256 if (reload_completed)
7257 sel_region_target_finish (reset_sched_cycles_p);
7259 sel_finish_global_and_expr ();
7261 bitmap_clear (forced_ebb_heads);
7265 finish_deps_global ();
7266 sched_finish_luids ();
7269 BITMAP_FREE (blocks_to_reschedule);
7271 sel_unregister_cfg_hooks ();
7277 /* Functions that implement the scheduler driver. */
7279 /* Schedule a parallel instruction group on each of FENCES. MAX_SEQNO
7280 is the current maximum seqno. SCHEDULED_INSNS_TAILPP is the list
7281 of insns scheduled -- these would be postprocessed later. */
7283 schedule_on_fences (flist_t fences, int max_seqno,
7284 ilist_t **scheduled_insns_tailpp)
7286 flist_t old_fences = fences;
7288 if (sched_verbose >= 1)
7290 sel_print ("\nScheduling on fences: ");
7291 dump_flist (fences);
7295 scheduled_something_on_previous_fence = false;
7296 for (; fences; fences = FLIST_NEXT (fences))
7298 fence_t fence = NULL;
7301 bool first_p = true;
7303 /* Choose the next fence group to schedule.
7304 The fact that insn can be scheduled only once
7305 on the cycle is guaranteed by two properties:
7306 1. seqnos of parallel groups decrease with each iteration.
7307 2. If is_ineligible_successor () sees the larger seqno, it
7308 checks if candidate insn is_in_current_fence_p (). */
7309 for (fences2 = old_fences; fences2; fences2 = FLIST_NEXT (fences2))
7311 fence_t f = FLIST_FENCE (fences2);
7313 if (!FENCE_PROCESSED_P (f))
7315 int i = INSN_SEQNO (FENCE_INSN (f));
7317 if (first_p || i > seqno)
7324 /* ??? Seqnos of different groups should be different. */
7325 gcc_assert (1 || i != seqno);
7331 /* As FENCE is nonnull, SEQNO is initialized. */
7332 seqno -= max_seqno + 1;
7333 fill_insns (fence, seqno, scheduled_insns_tailpp);
7334 FENCE_PROCESSED_P (fence) = true;
7337 /* All av_sets are invalidated by GLOBAL_LEVEL increase, thus we
7338 don't need to keep bookkeeping-invalidated and target-unavailable
7340 vinsn_vec_clear (&vec_bookkeeping_blocked_vinsns);
7341 vinsn_vec_clear (&vec_target_unavailable_vinsns);
7344 /* Calculate MIN_SEQNO and MAX_SEQNO. */
7346 find_min_max_seqno (flist_t fences, int *min_seqno, int *max_seqno)
7348 *min_seqno = *max_seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7350 /* The first element is already processed. */
7351 while ((fences = FLIST_NEXT (fences)))
7353 int seqno = INSN_SEQNO (FENCE_INSN (FLIST_FENCE (fences)));
7355 if (*min_seqno > seqno)
7357 else if (*max_seqno < seqno)
7362 /* Calculate new fences from FENCES. */
7364 calculate_new_fences (flist_t fences, int orig_max_seqno)
7366 flist_t old_fences = fences;
7367 struct flist_tail_def _new_fences, *new_fences = &_new_fences;
7369 flist_tail_init (new_fences);
7370 for (; fences; fences = FLIST_NEXT (fences))
7372 fence_t fence = FLIST_FENCE (fences);
7375 if (!FENCE_BNDS (fence))
7377 /* This fence doesn't have any successors. */
7378 if (!FENCE_SCHEDULED_P (fence))
7380 /* Nothing was scheduled on this fence. */
7383 insn = FENCE_INSN (fence);
7384 seqno = INSN_SEQNO (insn);
7385 gcc_assert (seqno > 0 && seqno <= orig_max_seqno);
7387 if (sched_verbose >= 1)
7388 sel_print ("Fence %d[%d] has not changed\n",
7391 move_fence_to_fences (fences, new_fences);
7395 extract_new_fences_from (fences, new_fences, orig_max_seqno);
7398 flist_clear (&old_fences);
7399 return FLIST_TAIL_HEAD (new_fences);
7402 /* Update seqnos of insns given by PSCHEDULED_INSNS. MIN_SEQNO and MAX_SEQNO
7403 are the miminum and maximum seqnos of the group, HIGHEST_SEQNO_IN_USE is
7404 the highest seqno used in a region. Return the updated highest seqno. */
7406 update_seqnos_and_stage (int min_seqno, int max_seqno,
7407 int highest_seqno_in_use,
7408 ilist_t *pscheduled_insns)
7414 /* Actually, new_hs is the seqno of the instruction, that was
7415 scheduled first (i.e. it is the first one in SCHEDULED_INSNS). */
7416 if (*pscheduled_insns)
7418 new_hs = (INSN_SEQNO (ILIST_INSN (*pscheduled_insns))
7419 + highest_seqno_in_use + max_seqno - min_seqno + 2);
7420 gcc_assert (new_hs > highest_seqno_in_use);
7423 new_hs = highest_seqno_in_use;
7425 FOR_EACH_INSN (insn, ii, *pscheduled_insns)
7427 gcc_assert (INSN_SEQNO (insn) < 0);
7428 INSN_SEQNO (insn) += highest_seqno_in_use + max_seqno - min_seqno + 2;
7429 gcc_assert (INSN_SEQNO (insn) <= new_hs);
7431 /* When not pipelining, purge unneeded insn info on the scheduled insns.
7432 For example, having reg_last array of INSN_DEPS_CONTEXT in memory may
7433 require > 1GB of memory e.g. on limit-fnargs.c. */
7435 free_data_for_scheduled_insn (insn);
7438 ilist_clear (pscheduled_insns);
7444 /* The main driver for scheduling a region. This function is responsible
7445 for correct propagation of fences (i.e. scheduling points) and creating
7446 a group of parallel insns at each of them. It also supports
7447 pipelining. ORIG_MAX_SEQNO is the maximal seqno before this pass
7450 sel_sched_region_2 (int orig_max_seqno)
7452 int highest_seqno_in_use = orig_max_seqno;
7454 stat_bookkeeping_copies = 0;
7455 stat_insns_needed_bookkeeping = 0;
7456 stat_renamed_scheduled = 0;
7457 stat_substitutions_total = 0;
7458 num_insns_scheduled = 0;
7462 int min_seqno, max_seqno;
7463 ilist_t scheduled_insns = NULL;
7464 ilist_t *scheduled_insns_tailp = &scheduled_insns;
7466 find_min_max_seqno (fences, &min_seqno, &max_seqno);
7467 schedule_on_fences (fences, max_seqno, &scheduled_insns_tailp);
7468 fences = calculate_new_fences (fences, orig_max_seqno);
7469 highest_seqno_in_use = update_seqnos_and_stage (min_seqno, max_seqno,
7470 highest_seqno_in_use,
7474 if (sched_verbose >= 1)
7475 sel_print ("Scheduled %d bookkeeping copies, %d insns needed "
7476 "bookkeeping, %d insns renamed, %d insns substituted\n",
7477 stat_bookkeeping_copies,
7478 stat_insns_needed_bookkeeping,
7479 stat_renamed_scheduled,
7480 stat_substitutions_total);
7483 /* Schedule a region. When pipelining, search for possibly never scheduled
7484 bookkeeping code and schedule it. Reschedule pipelined code without
7485 pipelining after. */
7487 sel_sched_region_1 (void)
7489 int number_of_insns;
7492 /* Remove empty blocks that might be in the region from the beginning.
7493 We need to do save sched_max_luid before that, as it actually shows
7494 the number of insns in the region, and purge_empty_blocks can
7496 number_of_insns = sched_max_luid - 1;
7497 purge_empty_blocks ();
7499 orig_max_seqno = init_seqno (number_of_insns, NULL, NULL);
7500 gcc_assert (orig_max_seqno >= 1);
7502 /* When pipelining outer loops, create fences on the loop header,
7505 if (current_loop_nest)
7506 init_fences (BB_END (EBB_FIRST_BB (0)));
7508 init_fences (bb_note (EBB_FIRST_BB (0)));
7511 sel_sched_region_2 (orig_max_seqno);
7513 gcc_assert (fences == NULL);
7519 struct flist_tail_def _new_fences;
7520 flist_tail_t new_fences = &_new_fences;
7523 pipelining_p = false;
7524 max_ws = MIN (max_ws, issue_rate * 3 / 2);
7525 bookkeeping_p = false;
7526 enable_schedule_as_rhs_p = false;
7528 /* Schedule newly created code, that has not been scheduled yet. */
7535 for (i = 0; i < current_nr_blocks; i++)
7537 basic_block bb = EBB_FIRST_BB (i);
7539 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7541 if (! bb_ends_ebb_p (bb))
7542 bitmap_set_bit (blocks_to_reschedule, bb_next_bb (bb)->index);
7543 if (sel_bb_empty_p (bb))
7545 bitmap_clear_bit (blocks_to_reschedule, bb->index);
7548 clear_outdated_rtx_info (bb);
7549 if (sel_insn_is_speculation_check (BB_END (bb))
7550 && JUMP_P (BB_END (bb)))
7551 bitmap_set_bit (blocks_to_reschedule,
7552 BRANCH_EDGE (bb)->dest->index);
7554 else if (! sel_bb_empty_p (bb)
7555 && INSN_SCHED_TIMES (sel_bb_head (bb)) <= 0)
7556 bitmap_set_bit (blocks_to_reschedule, bb->index);
7559 for (i = 0; i < current_nr_blocks; i++)
7561 bb = EBB_FIRST_BB (i);
7563 /* While pipelining outer loops, skip bundling for loop
7564 preheaders. Those will be rescheduled in the outer
7566 if (sel_is_loop_preheader_p (bb))
7568 clear_outdated_rtx_info (bb);
7572 if (bitmap_bit_p (blocks_to_reschedule, bb->index))
7574 flist_tail_init (new_fences);
7576 orig_max_seqno = init_seqno (0, blocks_to_reschedule, bb);
7578 /* Mark BB as head of the new ebb. */
7579 bitmap_set_bit (forced_ebb_heads, bb->index);
7581 gcc_assert (fences == NULL);
7583 init_fences (bb_note (bb));
7585 sel_sched_region_2 (orig_max_seqno);
7595 /* Schedule the RGN region. */
7597 sel_sched_region (int rgn)
7600 bool reset_sched_cycles_p;
7602 if (sel_region_init (rgn))
7605 if (sched_verbose >= 1)
7606 sel_print ("Scheduling region %d\n", rgn);
7608 schedule_p = (!sched_is_disabled_for_current_region_p ()
7609 && dbg_cnt (sel_sched_region_cnt));
7610 reset_sched_cycles_p = pipelining_p;
7612 sel_sched_region_1 ();
7614 /* Force initialization of INSN_SCHED_CYCLEs for correct bundling. */
7615 reset_sched_cycles_p = true;
7617 sel_region_finish (reset_sched_cycles_p);
7620 /* Perform global init for the scheduler. */
7622 sel_global_init (void)
7624 calculate_dominance_info (CDI_DOMINATORS);
7625 alloc_sched_pools ();
7627 /* Setup the infos for sched_init. */
7628 sel_setup_sched_infos ();
7629 setup_sched_dump ();
7631 sched_rgn_init (false);
7635 /* Reset AFTER_RECOVERY if it has been set by the 1st scheduler pass. */
7637 can_issue_more = issue_rate;
7639 sched_extend_target ();
7640 sched_deps_init (true);
7641 setup_nop_and_exit_insns ();
7642 sel_extend_global_bb_info ();
7644 init_hard_regs_data ();
7647 /* Free the global data of the scheduler. */
7649 sel_global_finish (void)
7651 free_bb_note_pool ();
7653 sel_finish_global_bb_info ();
7655 free_regset_pool ();
7656 free_nop_and_exit_insns ();
7658 sched_rgn_finish ();
7659 sched_deps_finish ();
7663 sel_finish_pipelining ();
7665 free_sched_pools ();
7666 free_dominance_info (CDI_DOMINATORS);
7669 /* Return true when we need to skip selective scheduling. Used for debugging. */
7671 maybe_skip_selective_scheduling (void)
7673 return ! dbg_cnt (sel_sched_cnt);
7676 /* The entry point. */
7678 run_selective_scheduling (void)
7682 if (n_basic_blocks == NUM_FIXED_BLOCKS)
7687 for (rgn = 0; rgn < nr_regions; rgn++)
7688 sel_sched_region (rgn);
7690 sel_global_finish ();