1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
5 2005, 2006, 2007, 2008, 2009, 2010, 2011
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
77 All of the expressions that appear only in machine descriptions,
78 not in RTL used by the compiler itself, are at the end of the file. */
80 /* Unknown, or no such operation; the enumeration constant should have
82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
84 /* Used in the cselib routines to describe a value. Objects of this
85 kind are only allocated in cselib.c, in an alloc pool instead of in
86 GC memory. The only operand of a VALUE is a cselib_val_struct.
87 var-tracking requires this to have a distinct integral value from
88 DECL codes in trees. */
89 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
91 /* The RTL generated for a DEBUG_EXPR_DECL. It links back to the
92 DEBUG_EXPR_DECL in the first operand. */
93 DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ)
95 /* ---------------------------------------------------------------------
96 Expressions used in constructing lists.
97 --------------------------------------------------------------------- */
99 /* a linked list of expressions */
100 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
102 /* a linked list of instructions.
103 The insns are represented in print by their uids. */
104 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
106 /* SEQUENCE appears in the result of a `gen_...' function
107 for a DEFINE_EXPAND that wants to make several insns.
108 Its elements are the bodies of the insns that should be made.
109 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
110 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
112 /* Refers to the address of its argument. This is only used in alias.c. */
113 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
115 /* ----------------------------------------------------------------------
116 Expression types used for things in the instruction chain.
118 All formats must start with "iuu" to handle the chain.
119 Each insn expression holds an rtl instruction and its semantics
120 during back-end processing.
121 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
123 ---------------------------------------------------------------------- */
125 /* An annotation for variable assignment tracking. */
126 DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBeiie", RTX_INSN)
128 /* An instruction that cannot jump. */
129 DEF_RTL_EXPR(INSN, "insn", "iuuBeiie", RTX_INSN)
131 /* An instruction that can possibly jump.
132 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
133 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBeiie0", RTX_INSN)
135 /* An instruction that can possibly call a subroutine
136 but which will not change which instruction comes next
137 in the current function.
138 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
139 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
140 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBeiiee", RTX_INSN)
142 /* A marker that indicates that control will not flow through. */
143 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
145 /* Holds a label that is followed by instructions.
147 4: is used in jump.c for the use-count of the label.
148 5: is used in the sh backend.
149 6: is a number that is unique in the entire compilation.
150 7: is the user-given name of the label, if any. */
151 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
153 /* Say where in the code a source line starts, for symbol table's sake.
155 4: note-specific data
157 6: unique number if insn_note == note_insn_deleted_label. */
158 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
160 /* ----------------------------------------------------------------------
161 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
162 ---------------------------------------------------------------------- */
164 /* Conditionally execute code.
165 Operand 0 is the condition that if true, the code is executed.
166 Operand 1 is the code to be executed (typically a SET).
168 Semantics are that there are no side effects if the condition
169 is false. This pattern is created automatically by the if_convert
170 pass run after reload or by target-specific splitters. */
171 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
173 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
174 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
176 /* A string that is passed through to the assembler as input.
177 One can obviously pass comments through by using the
178 assembler comment syntax.
179 These occur in an insn all by themselves as the PATTERN.
180 They also appear inside an ASM_OPERANDS
181 as a convenient way to hold a string. */
182 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
184 /* An assembler instruction with operands.
185 1st operand is the instruction template.
186 2nd operand is the constraint for the output.
187 3rd operand is the number of the output this expression refers to.
188 When an insn stores more than one value, a separate ASM_OPERANDS
189 is made for each output; this integer distinguishes them.
190 4th is a vector of values of input operands.
191 5th is a vector of modes and constraints for the input operands.
192 Each element is an ASM_INPUT containing a constraint string
193 and whose mode indicates the mode of the input operand.
194 6th is a vector of labels that may be branched to by the asm.
195 7th is the source line number. */
196 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA)
198 /* A machine-specific operation.
199 1st operand is a vector of operands being used by the operation so that
200 any needed reloads can be done.
201 2nd operand is a unique value saying which of a number of machine-specific
202 operations is to be performed.
203 (Note that the vector must be the first operand because of the way that
204 genrecog.c record positions within an insn.)
206 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
207 or inside an expression.
208 UNSPEC by itself or as a component of a PARALLEL
209 is currently considered not deletable.
211 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
212 of a PARALLEL with USE.
214 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
216 /* Similar, but a volatile operation and one which may trap. */
217 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
219 /* Vector of addresses, stored as full words. */
220 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
221 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
223 /* Vector of address differences X0 - BASE, X1 - BASE, ...
224 First operand is BASE; the vector contains the X's.
225 The machine mode of this rtx says how much space to leave
226 for each difference and is adjusted by branch shortening if
227 CASE_VECTOR_SHORTEN_MODE is defined.
228 The third and fourth operands store the target labels with the
229 minimum and maximum addresses respectively.
230 The fifth operand stores flags for use by branch shortening.
231 Set at the start of shorten_branches:
232 min_align: the minimum alignment for any of the target labels.
233 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
234 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
235 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
236 min_after_base: true iff minimum address target label is after BASE.
237 max_after_base: true iff maximum address target label is after BASE.
238 Set by the actual branch shortening process:
239 offset_unsigned: true iff offsets have to be treated as unsigned.
240 scale: scaling that is necessary to make offsets fit into the mode.
242 The third, fourth and fifth operands are only valid when
243 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
246 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
248 /* Memory prefetch, with attributes supported on some targets.
249 Operand 1 is the address of the memory to fetch.
250 Operand 2 is 1 for a write access, 0 otherwise.
251 Operand 3 is the level of temporal locality; 0 means there is no
252 temporal locality and 1, 2, and 3 are for increasing levels of temporal
255 The attributes specified by operands 2 and 3 are ignored for targets
256 whose prefetch instructions do not support them. */
257 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
259 /* ----------------------------------------------------------------------
260 At the top level of an instruction (perhaps under PARALLEL).
261 ---------------------------------------------------------------------- */
264 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
265 Operand 2 is the value stored there.
266 ALL assignment must use SET.
267 Instructions that do multiple assignments must use multiple SET,
269 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
271 /* Indicate something is used in a way that we don't want to explain.
272 For example, subroutine calls will use the register
273 in which the static chain is passed.
275 USE can not appear as an operand of other rtx except for PARALLEL.
276 USE is not deletable, as it indicates that the operand
277 is used in some unknown way. */
278 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
280 /* Indicate something is clobbered in a way that we don't want to explain.
281 For example, subroutine calls will clobber some physical registers
282 (the ones that are by convention not saved).
284 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
285 CLOBBER of a hard register appearing by itself (not within PARALLEL)
286 is considered undeletable before reload. */
287 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
289 /* Call a subroutine.
290 Operand 1 is the address to call.
291 Operand 2 is the number of arguments. */
293 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
295 /* Return from a subroutine. */
297 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
299 /* Special for EH return from subroutine. */
301 DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA)
304 Operand 1 is the condition.
305 Operand 2 is the trap code.
306 For an unconditional trap, make the condition (const_int 1). */
307 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
309 /* ----------------------------------------------------------------------
310 Primitive values for use in expressions.
311 ---------------------------------------------------------------------- */
313 /* numeric integer constant */
314 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
316 /* fixed-point constant */
317 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
319 /* numeric floating point constant.
320 Operands hold the value. They are all 'w' and there may be from 2 to 6;
322 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
324 /* Describes a vector constant. */
325 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
327 /* String constant. Used for attributes in machine descriptions and
328 for special cases in DWARF2 debug output. NOT used for source-
329 language string constants. */
330 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
332 /* This is used to encapsulate an expression whose value is constant
333 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
334 recognized as a constant operand rather than by arithmetic instructions. */
336 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
338 /* program counter. Ordinary jumps are represented
339 by a SET whose first operand is (PC). */
340 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
342 /* A register. The "operand" is the register number, accessed with
343 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
344 than a hardware register is being referred to. The second operand
345 holds the original register number - this will be different for a
346 pseudo register that got turned into a hard register. The third
347 operand points to a reg_attrs structure.
348 This rtx needs to have as many (or more) fields as a MEM, since we
349 can change REG rtx's into MEMs during reload. */
350 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
352 /* A scratch register. This represents a register used only within a
353 single insn. It will be turned into a REG during register allocation
354 or reload unless the constraint indicates that the register won't be
355 needed, in which case it can remain a SCRATCH. This code is
356 marked as having one operand so it can be turned into a REG. */
357 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
359 /* A reference to a part of another value. The first operand is the
360 complete value and the second is the byte offset of the selected part. */
361 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
363 /* This one-argument rtx is used for move instructions
364 that are guaranteed to alter only the low part of a destination.
365 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
366 has an unspecified effect on the high part of REG,
367 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
368 is guaranteed to alter only the bits of REG that are in HImode.
370 The actual instruction used is probably the same in both cases,
371 but the register constraints may be tighter when STRICT_LOW_PART
374 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
376 /* (CONCAT a b) represents the virtual concatenation of a and b
377 to make a value that has as many bits as a and b put together.
378 This is used for complex values. Normally it appears only
379 in DECL_RTLs and during RTL generation, but not in the insn chain. */
380 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
382 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
383 all An to make a value. This is an extension of CONCAT to larger
384 number of components. Like CONCAT, it should not appear in the
385 insn chain. Every element of the CONCATN is the same size. */
386 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
388 /* A memory location; operand is the address. The second operand is the
389 alias set to which this MEM belongs. We use `0' instead of `w' for this
390 field so that the field need not be specified in machine descriptions. */
391 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
393 /* Reference to an assembler label in the code for this function.
394 The operand is a CODE_LABEL found in the insn chain. */
395 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
397 /* Reference to a named label:
398 Operand 0: label name
399 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
400 Operand 2: tree from which this symbol is derived, or null.
401 This is either a DECL node, or some kind of constant. */
402 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
404 /* The condition code register is represented, in our imagination,
405 as a register holding a value that can be compared to zero.
406 In fact, the machine has already compared them and recorded the
407 results; but instructions that look at the condition code
408 pretend to be looking at the entire value and comparing it. */
409 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
411 /* ----------------------------------------------------------------------
412 Expressions for operators in an rtl pattern
413 ---------------------------------------------------------------------- */
415 /* if_then_else. This is used in representing ordinary
416 conditional jump instructions.
421 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
423 /* Comparison, produces a condition code result. */
424 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
427 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
429 /* Operand 0 minus operand 1. */
430 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
432 /* Minus operand 0. */
433 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
435 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
437 /* Multiplication with signed saturation */
438 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
439 /* Multiplication with unsigned saturation */
440 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
442 /* Operand 0 divided by operand 1. */
443 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
444 /* Division with signed saturation */
445 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
446 /* Division with unsigned saturation */
447 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
449 /* Remainder of operand 0 divided by operand 1. */
450 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
452 /* Unsigned divide and remainder. */
453 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
454 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
456 /* Bitwise operations. */
457 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
458 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
459 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
460 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
463 0: value to be shifted.
464 1: number of bits. */
465 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
466 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
467 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
468 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
469 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
471 /* Minimum and maximum values of two operands. We need both signed and
472 unsigned forms. (We cannot use MIN for SMIN because it conflicts
473 with a macro of the same name.) The signed variants should be used
474 with floating point. Further, if both operands are zeros, or if either
475 operand is NaN, then it is unspecified which of the two operands is
476 returned as the result. */
478 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
479 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
480 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
481 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
483 /* These unary operations are used to represent incrementation
484 and decrementation as they occur in memory addresses.
485 The amount of increment or decrement are not represented
486 because they can be understood from the machine-mode of the
487 containing MEM. These operations exist in only two cases:
488 1. pushes onto the stack.
489 2. created automatically by the auto-inc-dec pass. */
490 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
491 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
492 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
493 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
495 /* These binary operations are used to represent generic address
496 side-effects in memory addresses, except for simple incrementation
497 or decrementation which use the above operations. They are
498 created automatically by the life_analysis pass in flow.c.
499 The first operand is a REG which is used as the address.
500 The second operand is an expression that is assigned to the
501 register, either before (PRE_MODIFY) or after (POST_MODIFY)
502 evaluating the address.
503 Currently, the compiler can only handle second operands of the
504 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
505 the first operand of the PLUS has to be the same register as
506 the first operand of the *_MODIFY. */
507 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
508 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
510 /* Comparison operations. The ordered comparisons exist in two
511 flavors, signed and unsigned. */
512 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
513 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
514 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
515 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
516 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
517 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
518 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
519 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
520 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
521 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
523 /* Additional floating point unordered comparison flavors. */
524 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
525 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
527 /* These are equivalent to unordered or ... */
528 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
529 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
530 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
531 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
532 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
534 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
535 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
537 /* Represents the result of sign-extending the sole operand.
538 The machine modes of the operand and of the SIGN_EXTEND expression
539 determine how much sign-extension is going on. */
540 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
542 /* Similar for zero-extension (such as unsigned short to int). */
543 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
545 /* Similar but here the operand has a wider mode. */
546 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
548 /* Similar for extending floating-point values (such as SFmode to DFmode). */
549 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
550 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
552 /* Conversion of fixed point operand to floating point value. */
553 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
555 /* With fixed-point machine mode:
556 Conversion of floating point operand to fixed point value.
557 Value is defined only when the operand's value is an integer.
558 With floating-point machine mode (and operand with same mode):
559 Operand is rounded toward zero to produce an integer value
560 represented in floating point. */
561 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
563 /* Conversion of unsigned fixed point operand to floating point value. */
564 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
566 /* With fixed-point machine mode:
567 Conversion of floating point operand to *unsigned* fixed point value.
568 Value is defined only when the operand's value is an integer. */
569 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
571 /* Conversions involving fractional fixed-point types without saturation,
573 fractional to fractional (of different precision),
574 signed integer to fractional,
575 fractional to signed integer,
576 floating point to fractional,
577 fractional to floating point.
578 NOTE: fractional can be either signed or unsigned for conversions. */
579 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
581 /* Conversions involving fractional fixed-point types and unsigned integer
582 without saturation, including:
583 unsigned integer to fractional,
584 fractional to unsigned integer.
585 NOTE: fractional can be either signed or unsigned for conversions. */
586 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
588 /* Conversions involving fractional fixed-point types with saturation,
590 fractional to fractional (of different precision),
591 signed integer to fractional,
592 floating point to fractional.
593 NOTE: fractional can be either signed or unsigned for conversions. */
594 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
596 /* Conversions involving fractional fixed-point types and unsigned integer
597 with saturation, including:
598 unsigned integer to fractional.
599 NOTE: fractional can be either signed or unsigned for conversions. */
600 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
603 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
606 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
609 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
611 /* Find first bit that is set.
612 Value is 1 + number of trailing zeros in the arg.,
614 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
616 /* Count number of leading redundant sign bits (number of leading
617 sign bits minus one). */
618 DEF_RTL_EXPR(CLRSB, "clrsb", "e", RTX_UNARY)
620 /* Count leading zeros. */
621 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
623 /* Count trailing zeros. */
624 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
626 /* Population count (number of 1 bits). */
627 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
629 /* Population parity (number of 1 bits modulo 2). */
630 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
632 /* Reference to a signed bit-field of specified size and position.
633 Operand 0 is the memory unit (usually SImode or QImode) which
634 contains the field's first bit. Operand 1 is the width, in bits.
635 Operand 2 is the number of bits in the memory unit before the
636 first bit of this field.
637 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
638 operand 2 counts from the msb of the memory unit.
639 Otherwise, the first bit is the lsb and operand 2 counts from
640 the lsb of the memory unit.
641 This kind of expression can not appear as an lvalue in RTL. */
642 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
644 /* Similar for unsigned bit-field.
645 But note! This kind of expression _can_ appear as an lvalue. */
646 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
648 /* For RISC machines. These save memory when splitting insns. */
650 /* HIGH are the high-order bits of a constant expression. */
651 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
653 /* LO_SUM is the sum of a register and the low-order bits
654 of a constant expression. */
655 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
657 /* Describes a merge operation between two vector values.
658 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
659 that specifies where the parts of the result are taken from. Set bits
660 indicate operand 0, clear bits indicate operand 1. The parts are defined
661 by the mode of the vectors. */
662 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
664 /* Describes an operation that selects parts of a vector.
665 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
666 a CONST_INT for each of the subparts of the result vector, giving the
667 number of the source subpart that should be stored into it. */
668 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
670 /* Describes a vector concat operation. Operands 0 and 1 are the source
671 vectors, the result is a vector that is as long as operands 0 and 1
672 combined and is the concatenation of the two source vectors. */
673 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
675 /* Describes an operation that converts a small vector into a larger one by
676 duplicating the input values. The output vector mode must have the same
677 submodes as the input vector mode, and the number of output parts must be
678 an integer multiple of the number of input parts. */
679 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
681 /* Addition with signed saturation */
682 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
684 /* Addition with unsigned saturation */
685 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
687 /* Operand 0 minus operand 1, with signed saturation. */
688 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
690 /* Negation with signed saturation. */
691 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
692 /* Negation with unsigned saturation. */
693 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
695 /* Absolute value with signed saturation. */
696 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
698 /* Shift left with signed saturation. */
699 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
701 /* Shift left with unsigned saturation. */
702 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
704 /* Operand 0 minus operand 1, with unsigned saturation. */
705 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
707 /* Signed saturating truncate. */
708 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
710 /* Unsigned saturating truncate. */
711 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
713 /* Floating point multiply/add combined instruction. */
714 DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY)
716 /* Information about the variable and its location. */
717 /* Changed 'te' to 'tei'; the 'i' field is for recording
718 initialization status of variables. */
719 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
721 /* Used in VAR_LOCATION for a pointer to a decl that is no longer
723 DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ)
725 /* Represents value that argument had on function entry. The
726 single argument is the DECL_INCOMING_RTL of the corresponding
728 DEF_RTL_EXPR(ENTRY_VALUE, "entry_value", "0", RTX_OBJ)
730 /* All expressions from this point forward appear only in machine
732 #ifdef GENERATOR_FILE
734 /* Pattern-matching operators: */
736 /* Use the function named by the second arg (the string)
737 as a predicate; if matched, store the structure that was matched
738 in the operand table at index specified by the first arg (the integer).
739 If the second arg is the null string, the structure is just stored.
741 A third string argument indicates to the register allocator restrictions
742 on where the operand can be allocated.
744 If the target needs no restriction on any instruction this field should
747 The string is prepended by:
748 '=' to indicate the operand is only written to.
749 '+' to indicate the operand is both read and written to.
751 Each character in the string represents an allocable class for an operand.
752 'g' indicates the operand can be any valid class.
753 'i' indicates the operand can be immediate (in the instruction) data.
754 'r' indicates the operand can be in a register.
755 'm' indicates the operand can be in memory.
756 'o' a subset of the 'm' class. Those memory addressing modes that
757 can be offset at compile time (have a constant added to them).
759 Other characters indicate target dependent operand classes and
760 are described in each target's machine description.
762 For instructions with more than one operand, sets of classes can be
763 separated by a comma to indicate the appropriate multi-operand constraints.
764 There must be a 1 to 1 correspondence between these sets of classes in
765 all operands for an instruction.
767 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
769 /* Match a SCRATCH or a register. When used to generate rtl, a
770 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
771 the desired mode and the first argument is the operand number.
772 The second argument is the constraint. */
773 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
775 /* Apply a predicate, AND match recursively the operands of the rtx.
776 Operand 0 is the operand-number, as in match_operand.
777 Operand 1 is a predicate to apply (as a string, a function name).
778 Operand 2 is a vector of expressions, each of which must match
779 one subexpression of the rtx this construct is matching. */
780 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
782 /* Match a PARALLEL of arbitrary length. The predicate is applied
783 to the PARALLEL and the initial expressions in the PARALLEL are matched.
784 Operand 0 is the operand-number, as in match_operand.
785 Operand 1 is a predicate to apply to the PARALLEL.
786 Operand 2 is a vector of expressions, each of which must match the
787 corresponding element in the PARALLEL. */
788 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
790 /* Match only something equal to what is stored in the operand table
791 at the index specified by the argument. Use with MATCH_OPERAND. */
792 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
794 /* Match only something equal to what is stored in the operand table
795 at the index specified by the argument. Use with MATCH_OPERATOR. */
796 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
798 /* Match only something equal to what is stored in the operand table
799 at the index specified by the argument. Use with MATCH_PARALLEL. */
800 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
802 /* Appears only in define_predicate/define_special_predicate
803 expressions. Evaluates true only if the operand has an RTX code
804 from the set given by the argument (a comma-separated list). If the
805 second argument is present and nonempty, it is a sequence of digits
806 and/or letters which indicates the subexpression to test, using the
807 same syntax as genextract/genrecog's location strings: 0-9 for
808 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
809 the result of the one before it. */
810 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
812 /* Appears only in define_predicate/define_special_predicate
813 expressions. The argument is a C expression to be injected at this
814 point in the predicate formula. */
815 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
817 /* Insn (and related) definitions. */
819 /* Definition of the pattern for one kind of instruction.
821 0: names this instruction.
822 If the name is the null string, the instruction is in the
823 machine description just to be recognized, and will never be emitted by
824 the tree to rtl expander.
826 2: is a string which is a C expression
827 giving an additional condition for recognizing this pattern.
828 A null string means no extra condition.
829 3: is the action to execute if this pattern is matched.
830 If this assembler code template starts with a * then it is a fragment of
831 C code to run to decide on a template to use. Otherwise, it is the
833 4: optionally, a vector of attributes for this insn.
835 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
837 /* Definition of a peephole optimization.
838 1st operand: vector of insn patterns to match
839 2nd operand: C expression that must be true
840 3rd operand: template or C code to produce assembler output.
841 4: optionally, a vector of attributes for this insn.
843 This form is deprecated; use define_peephole2 instead. */
844 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
846 /* Definition of a split operation.
847 1st operand: insn pattern to match
848 2nd operand: C expression that must be true
849 3rd operand: vector of insn patterns to place into a SEQUENCE
850 4th operand: optionally, some C code to execute before generating the
851 insns. This might, for example, create some RTX's and store them in
852 elements of `recog_data.operand' for use by the vector of
854 (`operands' is an alias here for `recog_data.operand'). */
855 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
857 /* Definition of an insn and associated split.
858 This is the concatenation, with a few modifications, of a define_insn
859 and a define_split which share the same pattern.
861 0: names this instruction.
862 If the name is the null string, the instruction is in the
863 machine description just to be recognized, and will never be emitted by
864 the tree to rtl expander.
866 2: is a string which is a C expression
867 giving an additional condition for recognizing this pattern.
868 A null string means no extra condition.
869 3: is the action to execute if this pattern is matched.
870 If this assembler code template starts with a * then it is a fragment of
871 C code to run to decide on a template to use. Otherwise, it is the
873 4: C expression that must be true for split. This may start with "&&"
874 in which case the split condition is the logical and of the insn
875 condition and what follows the "&&" of this operand.
876 5: vector of insn patterns to place into a SEQUENCE
877 6: optionally, some C code to execute before generating the
878 insns. This might, for example, create some RTX's and store them in
879 elements of `recog_data.operand' for use by the vector of
881 (`operands' is an alias here for `recog_data.operand').
882 7: optionally, a vector of attributes for this insn. */
883 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
885 /* Definition of an RTL peephole operation.
886 Follows the same arguments as define_split. */
887 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
889 /* Define how to generate multiple insns for a standard insn name.
890 1st operand: the insn name.
891 2nd operand: vector of insn-patterns.
892 Use match_operand to substitute an element of `recog_data.operand'.
893 3rd operand: C expression that must be true for this to be available.
894 This may not test any operands.
895 4th operand: Extra C code to execute before generating the insns.
896 This might, for example, create some RTX's and store them in
897 elements of `recog_data.operand' for use by the vector of
899 (`operands' is an alias here for `recog_data.operand'). */
900 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
902 /* Define a requirement for delay slots.
903 1st operand: Condition involving insn attributes that, if true,
904 indicates that the insn requires the number of delay slots
906 2nd operand: Vector whose length is the three times the number of delay
908 Each entry gives three conditions, each involving attributes.
909 The first must be true for an insn to occupy that delay slot
910 location. The second is true for all insns that can be
911 annulled if the branch is true and the third is true for all
912 insns that can be annulled if the branch is false.
914 Multiple DEFINE_DELAYs may be present. They indicate differing
915 requirements for delay slots. */
916 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
918 /* Define attribute computation for `asm' instructions. */
919 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
921 /* Definition of a conditional execution meta operation. Automatically
922 generates new instances of DEFINE_INSN, selected by having attribute
923 "predicable" true. The new pattern will contain a COND_EXEC and the
924 predicate at top-level.
927 0: The predicate pattern. The top-level form should match a
928 relational operator. Operands should have only one alternative.
929 1: A C expression giving an additional condition for recognizing
930 the generated pattern.
931 2: A template or C code to produce assembler output. */
932 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
934 /* Definition of an operand predicate. The difference between
935 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
936 not warn about a match_operand with no mode if it has a predicate
937 defined with DEFINE_SPECIAL_PREDICATE.
940 0: The name of the predicate.
941 1: A boolean expression which computes whether or not the predicate
942 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
943 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
944 can calculate the set of RTX codes that can possibly match.
945 2: A C function body which must return true for the predicate to match.
946 Optional. Use this when the test is too complicated to fit into a
947 match_test expression. */
948 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
949 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
951 /* Definition of a register operand constraint. This simply maps the
952 constraint string to a register class.
955 0: The name of the constraint (often, but not always, a single letter).
956 1: A C expression which evaluates to the appropriate register class for
957 this constraint. If this is not just a constant, it should look only
958 at -m switches and the like.
959 2: A docstring for this constraint, in Texinfo syntax; not currently
960 used, in future will be incorporated into the manual's list of
961 machine-specific operand constraints. */
962 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
964 /* Definition of a non-register operand constraint. These look at the
965 operand and decide whether it fits the constraint.
967 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
968 It is appropriate for constant-only constraints, and most others.
970 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
971 to match, if it doesn't already, by converting the operand to the form
972 (mem (reg X)) where X is a base register. It is suitable for constraints
973 that describe a subset of all memory references.
975 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
976 to match, if it doesn't already, by converting the operand to the form
977 (reg X) where X is a base register. It is suitable for constraints that
978 describe a subset of all address references.
980 When in doubt, use plain DEFINE_CONSTRAINT.
983 0: The name of the constraint (often, but not always, a single letter).
984 1: A docstring for this constraint, in Texinfo syntax; not currently
985 used, in future will be incorporated into the manual's list of
986 machine-specific operand constraints.
987 2: A boolean expression which computes whether or not the constraint
988 matches. It should follow the same rules as a define_predicate
989 expression, including the bit about specifying the set of RTX codes
990 that could possibly match. MATCH_TEST subexpressions may make use of
992 `op' - the RTL object defining the operand.
993 `mode' - the mode of `op'.
994 `ival' - INTVAL(op), if op is a CONST_INT.
995 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
996 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
997 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
999 Do not use ival/hval/lval/rval if op is not the appropriate kind of
1001 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1002 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1003 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1006 /* Constructions for CPU pipeline description described by NDFAs. */
1008 /* (define_cpu_unit string [string]) describes cpu functional
1009 units (separated by comma).
1011 1st operand: Names of cpu functional units.
1012 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1014 All define_reservations, define_cpu_units, and
1015 define_query_cpu_units should have unique names which may not be
1017 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1019 /* (define_query_cpu_unit string [string]) describes cpu functional
1020 units analogously to define_cpu_unit. The reservation of such
1021 units can be queried for automaton state. */
1022 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1024 /* (exclusion_set string string) means that each CPU functional unit
1025 in the first string can not be reserved simultaneously with any
1026 unit whose name is in the second string and vise versa. CPU units
1027 in the string are separated by commas. For example, it is useful
1028 for description CPU with fully pipelined floating point functional
1029 unit which can execute simultaneously only single floating point
1030 insns or only double floating point insns. All CPU functional
1031 units in a set should belong to the same automaton. */
1032 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1034 /* (presence_set string string) means that each CPU functional unit in
1035 the first string can not be reserved unless at least one of pattern
1036 of units whose names are in the second string is reserved. This is
1037 an asymmetric relation. CPU units or unit patterns in the strings
1038 are separated by commas. Pattern is one unit name or unit names
1039 separated by white-spaces.
1041 For example, it is useful for description that slot1 is reserved
1042 after slot0 reservation for a VLIW processor. We could describe it
1043 by the following construction
1045 (presence_set "slot1" "slot0")
1047 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1048 this case we could write
1050 (presence_set "slot1" "slot0 b0")
1052 All CPU functional units in a set should belong to the same
1054 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1056 /* (final_presence_set string string) is analogous to `presence_set'.
1057 The difference between them is when checking is done. When an
1058 instruction is issued in given automaton state reflecting all
1059 current and planned unit reservations, the automaton state is
1060 changed. The first state is a source state, the second one is a
1061 result state. Checking for `presence_set' is done on the source
1062 state reservation, checking for `final_presence_set' is done on the
1063 result reservation. This construction is useful to describe a
1064 reservation which is actually two subsequent reservations. For
1067 (presence_set "slot1" "slot0")
1069 the following insn will be never issued (because slot1 requires
1070 slot0 which is absent in the source state).
1072 (define_reservation "insn_and_nop" "slot0 + slot1")
1074 but it can be issued if we use analogous `final_presence_set'. */
1075 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1077 /* (absence_set string string) means that each CPU functional unit in
1078 the first string can be reserved only if each pattern of units
1079 whose names are in the second string is not reserved. This is an
1080 asymmetric relation (actually exclusion set is analogous to this
1081 one but it is symmetric). CPU units or unit patterns in the string
1082 are separated by commas. Pattern is one unit name or unit names
1083 separated by white-spaces.
1085 For example, it is useful for description that slot0 can not be
1086 reserved after slot1 or slot2 reservation for a VLIW processor. We
1087 could describe it by the following construction
1089 (absence_set "slot2" "slot0, slot1")
1091 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1092 slot1 and unit b1 are reserved . In this case we could write
1094 (absence_set "slot2" "slot0 b0, slot1 b1")
1096 All CPU functional units in a set should to belong the same
1098 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1100 /* (final_absence_set string string) is analogous to `absence_set' but
1101 checking is done on the result (state) reservation. See comments
1102 for `final_presence_set'. */
1103 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1105 /* (define_bypass number out_insn_names in_insn_names) names bypass
1106 with given latency (the first number) from insns given by the first
1107 string (see define_insn_reservation) into insns given by the second
1108 string. Insn names in the strings are separated by commas. The
1109 third operand is optional name of function which is additional
1110 guard for the bypass. The function will get the two insns as
1111 parameters. If the function returns zero the bypass will be
1112 ignored for this case. Additional guard is necessary to recognize
1113 complicated bypasses, e.g. when consumer is load address. If there
1114 are more one bypass with the same output and input insns, the
1115 chosen bypass is the first bypass with a guard in description whose
1116 guard function returns nonzero. If there is no such bypass, then
1117 bypass without the guard function is chosen. */
1118 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1120 /* (define_automaton string) describes names of automata generated and
1121 used for pipeline hazards recognition. The names are separated by
1122 comma. Actually it is possibly to generate the single automaton
1123 but unfortunately it can be very large. If we use more one
1124 automata, the summary size of the automata usually is less than the
1125 single one. The automaton name is used in define_cpu_unit and
1126 define_query_cpu_unit. All automata should have unique names. */
1127 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1129 /* (automata_option string) describes option for generation of
1130 automata. Currently there are the following options:
1132 o "no-minimization" which makes no minimization of automata. This
1133 is only worth to do when we are debugging the description and
1134 need to look more accurately at reservations of states.
1136 o "time" which means printing additional time statistics about
1137 generation of automata.
1139 o "v" which means generation of file describing the result
1140 automata. The file has suffix `.dfa' and can be used for the
1141 description verification and debugging.
1143 o "w" which means generation of warning instead of error for
1144 non-critical errors.
1146 o "ndfa" which makes nondeterministic finite state automata.
1148 o "progress" which means output of a progress bar showing how many
1149 states were generated so far for automaton being processed. */
1150 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1152 /* (define_reservation string string) names reservation (the first
1153 string) of cpu functional units (the 2nd string). Sometimes unit
1154 reservations for different insns contain common parts. In such
1155 case, you can describe common part and use its name (the 1st
1156 parameter) in regular expression in define_insn_reservation. All
1157 define_reservations, define_cpu_units, and define_query_cpu_units
1158 should have unique names which may not be "nothing". */
1159 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1161 /* (define_insn_reservation name default_latency condition regexpr)
1162 describes reservation of cpu functional units (the 3nd operand) for
1163 instruction which is selected by the condition (the 2nd parameter).
1164 The first parameter is used for output of debugging information.
1165 The reservations are described by a regular expression according
1166 the following syntax:
1168 regexp = regexp "," oneof
1171 oneof = oneof "|" allof
1174 allof = allof "+" repeat
1177 repeat = element "*" number
1180 element = cpu_function_unit_name
1186 1. "," is used for describing start of the next cycle in
1189 2. "|" is used for describing the reservation described by the
1190 first regular expression *or* the reservation described by the
1191 second regular expression *or* etc.
1193 3. "+" is used for describing the reservation described by the
1194 first regular expression *and* the reservation described by the
1195 second regular expression *and* etc.
1197 4. "*" is used for convenience and simply means sequence in
1198 which the regular expression are repeated NUMBER times with
1199 cycle advancing (see ",").
1201 5. cpu functional unit name which means its reservation.
1203 6. reservation name -- see define_reservation.
1205 7. string "nothing" means no units reservation. */
1207 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1209 /* Expressions used for insn attributes. */
1211 /* Definition of an insn attribute.
1212 1st operand: name of the attribute
1213 2nd operand: comma-separated list of possible attribute values
1214 3rd operand: expression for the default value of the attribute. */
1215 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1217 /* Definition of an insn attribute that uses an existing enumerated type.
1218 1st operand: name of the attribute
1219 2nd operand: the name of the enumerated type
1220 3rd operand: expression for the default value of the attribute. */
1221 DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA)
1223 /* Marker for the name of an attribute. */
1224 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1226 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1227 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1230 (set_attr "name" "value") is equivalent to
1231 (set (attr "name") (const_string "value")) */
1232 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1234 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1235 specify that attribute values are to be assigned according to the
1236 alternative matched.
1238 The following three expressions are equivalent:
1240 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1241 (eq_attrq "alternative" "2") (const_string "a2")]
1242 (const_string "a3")))
1243 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1244 (const_string "a3")])
1245 (set_attr "att" "a1,a2,a3")
1247 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1249 /* A conditional expression true if the value of the specified attribute of
1250 the current insn equals the specified value. The first operand is the
1251 attribute name and the second is the comparison value. */
1252 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1254 /* A special case of the above representing a set of alternatives. The first
1255 operand is bitmap of the set, the second one is the default value. */
1256 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1258 /* A conditional expression which is true if the specified flag is
1259 true for the insn being scheduled in reorg.
1261 genattr.c defines the following flags which can be tested by
1262 (attr_flag "foo") expressions in eligible_for_delay.
1264 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1266 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1268 /* General conditional. The first operand is a vector composed of pairs of
1269 expressions. The first element of each pair is evaluated, in turn.
1270 The value of the conditional is the second expression of the first pair
1271 whose first expression evaluates nonzero. If none of the expressions is
1272 true, the second operand will be used as the value of the conditional. */
1273 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1275 #endif /* GENERATOR_FILE */
OSDN Git Service
