1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 3, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING3. If not see
22 <http://www.gnu.org/licenses/>. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
77 All of the expressions that appear only in machine descriptions,
78 not in RTL used by the compiler itself, are at the end of the file. */
80 /* Unknown, or no such operation; the enumeration constant should have
82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
84 /* ---------------------------------------------------------------------
85 Expressions used in constructing lists.
86 --------------------------------------------------------------------- */
88 /* a linked list of expressions */
89 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
91 /* a linked list of instructions.
92 The insns are represented in print by their uids. */
93 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
95 /* SEQUENCE appears in the result of a `gen_...' function
96 for a DEFINE_EXPAND that wants to make several insns.
97 Its elements are the bodies of the insns that should be made.
98 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
99 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
101 /* Refers to the address of its argument. This is only used in alias.c. */
102 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
104 /* ----------------------------------------------------------------------
105 Expression types used for things in the instruction chain.
107 All formats must start with "iuu" to handle the chain.
108 Each insn expression holds an rtl instruction and its semantics
109 during back-end processing.
110 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
112 ---------------------------------------------------------------------- */
114 /* An instruction that cannot jump. */
115 DEF_RTL_EXPR(INSN, "insn", "iuuBieie", RTX_INSN)
117 /* An instruction that can possibly jump.
118 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
119 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieie0", RTX_INSN)
121 /* An instruction that can possibly call a subroutine
122 but which will not change which instruction comes next
123 in the current function.
124 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE.
125 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
126 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieiee", RTX_INSN)
128 /* A marker that indicates that control will not flow through. */
129 DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA)
131 /* Holds a label that is followed by instructions.
133 4: is used in jump.c for the use-count of the label.
134 5: is used in the sh backend.
135 6: is a number that is unique in the entire compilation.
136 7: is the user-given name of the label, if any. */
137 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
139 /* Say where in the code a source line starts, for symbol table's sake.
141 4: note-specific data
143 6: unique number if insn_note == note_insn_deleted_label. */
144 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
146 /* ----------------------------------------------------------------------
147 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
148 ---------------------------------------------------------------------- */
150 /* Conditionally execute code.
151 Operand 0 is the condition that if true, the code is executed.
152 Operand 1 is the code to be executed (typically a SET).
154 Semantics are that there are no side effects if the condition
155 is false. This pattern is created automatically by the if_convert
156 pass run after reload or by target-specific splitters. */
157 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
159 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
160 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
162 #ifdef USE_MAPPED_LOCATION
163 /* A string that is passed through to the assembler as input.
164 One can obviously pass comments through by using the
165 assembler comment syntax.
166 These occur in an insn all by themselves as the PATTERN.
167 They also appear inside an ASM_OPERANDS
168 as a convenient way to hold a string. */
169 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA)
171 /* An assembler instruction with operands.
172 1st operand is the instruction template.
173 2nd operand is the constraint for the output.
174 3rd operand is the number of the output this expression refers to.
175 When an insn stores more than one value, a separate ASM_OPERANDS
176 is made for each output; this integer distinguishes them.
177 4th is a vector of values of input operands.
178 5th is a vector of modes and constraints for the input operands.
179 Each element is an ASM_INPUT containing a constraint string
180 and whose mode indicates the mode of the input operand.
181 6th is the source line number. */
182 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
184 /* A string that is passed through to the assembler as input.
185 One can obviously pass comments through by using the
186 assembler comment syntax.
187 These occur in an insn all by themselves as the PATTERN.
188 They also appear inside an ASM_OPERANDS
189 as a convenient way to hold a string. */
190 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "ssi", RTX_EXTRA)
192 /* An assembler instruction with operands.
193 1st operand is the instruction template.
194 2nd operand is the constraint for the output.
195 3rd operand is the number of the output this expression refers to.
196 When an insn stores more than one value, a separate ASM_OPERANDS
197 is made for each output; this integer distinguishes them.
198 4th is a vector of values of input operands.
199 5th is a vector of modes and constraints for the input operands.
200 Each element is an ASM_INPUT containing a constraint string
201 and whose mode indicates the mode of the input operand.
202 6th is the name of the containing source file.
203 7th is the source line number. */
204 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
207 /* A machine-specific operation.
208 1st operand is a vector of operands being used by the operation so that
209 any needed reloads can be done.
210 2nd operand is a unique value saying which of a number of machine-specific
211 operations is to be performed.
212 (Note that the vector must be the first operand because of the way that
213 genrecog.c record positions within an insn.)
215 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL,
216 or inside an expression.
217 UNSPEC by itself or as a component of a PARALLEL
218 is currently considered not deletable.
220 FIXME: Replace all uses of UNSPEC that appears by itself or as a component
221 of a PARALLEL with USE.
223 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
225 /* Similar, but a volatile operation and one which may trap. */
226 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
228 /* Vector of addresses, stored as full words. */
229 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
230 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
232 /* Vector of address differences X0 - BASE, X1 - BASE, ...
233 First operand is BASE; the vector contains the X's.
234 The machine mode of this rtx says how much space to leave
235 for each difference and is adjusted by branch shortening if
236 CASE_VECTOR_SHORTEN_MODE is defined.
237 The third and fourth operands store the target labels with the
238 minimum and maximum addresses respectively.
239 The fifth operand stores flags for use by branch shortening.
240 Set at the start of shorten_branches:
241 min_align: the minimum alignment for any of the target labels.
242 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
243 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
244 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
245 min_after_base: true iff minimum address target label is after BASE.
246 max_after_base: true iff maximum address target label is after BASE.
247 Set by the actual branch shortening process:
248 offset_unsigned: true iff offsets have to be treated as unsigned.
249 scale: scaling that is necessary to make offsets fit into the mode.
251 The third, fourth and fifth operands are only valid when
252 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
255 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
257 /* Memory prefetch, with attributes supported on some targets.
258 Operand 1 is the address of the memory to fetch.
259 Operand 2 is 1 for a write access, 0 otherwise.
260 Operand 3 is the level of temporal locality; 0 means there is no
261 temporal locality and 1, 2, and 3 are for increasing levels of temporal
264 The attributes specified by operands 2 and 3 are ignored for targets
265 whose prefetch instructions do not support them. */
266 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
268 /* ----------------------------------------------------------------------
269 At the top level of an instruction (perhaps under PARALLEL).
270 ---------------------------------------------------------------------- */
273 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
274 Operand 2 is the value stored there.
275 ALL assignment must use SET.
276 Instructions that do multiple assignments must use multiple SET,
278 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
280 /* Indicate something is used in a way that we don't want to explain.
281 For example, subroutine calls will use the register
282 in which the static chain is passed.
284 USE can not appear as an operand of other rtx except for PARALLEL.
285 USE is not deletable, as it indicates that the operand
286 is used in some unknown way. */
287 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
289 /* Indicate something is clobbered in a way that we don't want to explain.
290 For example, subroutine calls will clobber some physical registers
291 (the ones that are by convention not saved).
293 CLOBBER can not appear as an operand of other rtx except for PARALLEL.
294 CLOBBER of a hard register appearing by itself (not within PARALLEL)
295 is considered undeletable before reload. */
296 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
298 /* Call a subroutine.
299 Operand 1 is the address to call.
300 Operand 2 is the number of arguments. */
302 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
304 /* Return from a subroutine. */
306 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
309 Operand 1 is the condition.
310 Operand 2 is the trap code.
311 For an unconditional trap, make the condition (const_int 1). */
312 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
314 /* Placeholder for _Unwind_Resume before we know if a function call
315 or a branch is needed. Operand 1 is the exception region from
316 which control is flowing. */
317 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
319 /* ----------------------------------------------------------------------
320 Primitive values for use in expressions.
321 ---------------------------------------------------------------------- */
323 /* numeric integer constant */
324 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
326 /* fixed-point constant */
327 DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ)
329 /* numeric floating point constant.
330 Operands hold the value. They are all 'w' and there may be from 2 to 6;
332 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
334 /* Describes a vector constant. */
335 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
337 /* String constant. Used for attributes in machine descriptions and
338 for special cases in DWARF2 debug output. NOT used for source-
339 language string constants. */
340 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
342 /* This is used to encapsulate an expression whose value is constant
343 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
344 recognized as a constant operand rather than by arithmetic instructions. */
346 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
348 /* program counter. Ordinary jumps are represented
349 by a SET whose first operand is (PC). */
350 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
352 /* Used in the cselib routines to describe a value. Objects of this
353 kind are only allocated in cselib.c, in an alloc pool instead of
354 in GC memory. The only operand of a VALUE is a cselib_val_struct. */
355 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
357 /* A register. The "operand" is the register number, accessed with
358 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
359 than a hardware register is being referred to. The second operand
360 holds the original register number - this will be different for a
361 pseudo register that got turned into a hard register. The third
362 operand points to a reg_attrs structure.
363 This rtx needs to have as many (or more) fields as a MEM, since we
364 can change REG rtx's into MEMs during reload. */
365 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
367 /* A scratch register. This represents a register used only within a
368 single insn. It will be turned into a REG during register allocation
369 or reload unless the constraint indicates that the register won't be
370 needed, in which case it can remain a SCRATCH. This code is
371 marked as having one operand so it can be turned into a REG. */
372 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
374 /* A reference to a part of another value. The first operand is the
375 complete value and the second is the byte offset of the selected part. */
376 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
378 /* This one-argument rtx is used for move instructions
379 that are guaranteed to alter only the low part of a destination.
380 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
381 has an unspecified effect on the high part of REG,
382 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
383 is guaranteed to alter only the bits of REG that are in HImode.
385 The actual instruction used is probably the same in both cases,
386 but the register constraints may be tighter when STRICT_LOW_PART
389 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
391 /* (CONCAT a b) represents the virtual concatenation of a and b
392 to make a value that has as many bits as a and b put together.
393 This is used for complex values. Normally it appears only
394 in DECL_RTLs and during RTL generation, but not in the insn chain. */
395 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
397 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
398 all An to make a value. This is an extension of CONCAT to larger
399 number of components. Like CONCAT, it should not appear in the
400 insn chain. Every element of the CONCATN is the same size. */
401 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
403 /* A memory location; operand is the address. The second operand is the
404 alias set to which this MEM belongs. We use `0' instead of `w' for this
405 field so that the field need not be specified in machine descriptions. */
406 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
408 /* Reference to an assembler label in the code for this function.
409 The operand is a CODE_LABEL found in the insn chain. */
410 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
412 /* Reference to a named label:
413 Operand 0: label name
414 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
415 Operand 2: tree from which this symbol is derived, or null.
416 This is either a DECL node, or some kind of constant. */
417 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
419 /* The condition code register is represented, in our imagination,
420 as a register holding a value that can be compared to zero.
421 In fact, the machine has already compared them and recorded the
422 results; but instructions that look at the condition code
423 pretend to be looking at the entire value and comparing it. */
424 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
426 /* ----------------------------------------------------------------------
427 Expressions for operators in an rtl pattern
428 ---------------------------------------------------------------------- */
430 /* if_then_else. This is used in representing ordinary
431 conditional jump instructions.
436 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
438 /* Comparison, produces a condition code result. */
439 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
442 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
444 /* Operand 0 minus operand 1. */
445 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
447 /* Minus operand 0. */
448 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
450 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
452 /* Multiplication with signed saturation */
453 DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH)
454 /* Multiplication with unsigned saturation */
455 DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH)
457 /* Operand 0 divided by operand 1. */
458 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
459 /* Division with signed saturation */
460 DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH)
461 /* Division with unsigned saturation */
462 DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH)
464 /* Remainder of operand 0 divided by operand 1. */
465 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
467 /* Unsigned divide and remainder. */
468 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
469 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
471 /* Bitwise operations. */
472 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
473 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
474 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
475 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
478 0: value to be shifted.
479 1: number of bits. */
480 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
481 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
482 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
483 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
484 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
486 /* Minimum and maximum values of two operands. We need both signed and
487 unsigned forms. (We cannot use MIN for SMIN because it conflicts
488 with a macro of the same name.) The signed variants should be used
489 with floating point. Further, if both operands are zeros, or if either
490 operand is NaN, then it is unspecified which of the two operands is
491 returned as the result. */
493 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
494 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
495 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
496 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
498 /* These unary operations are used to represent incrementation
499 and decrementation as they occur in memory addresses.
500 The amount of increment or decrement are not represented
501 because they can be understood from the machine-mode of the
502 containing MEM. These operations exist in only two cases:
503 1. pushes onto the stack.
504 2. created automatically by the life_analysis pass in flow.c. */
505 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
506 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
507 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
508 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
510 /* These binary operations are used to represent generic address
511 side-effects in memory addresses, except for simple incrementation
512 or decrementation which use the above operations. They are
513 created automatically by the life_analysis pass in flow.c.
514 The first operand is a REG which is used as the address.
515 The second operand is an expression that is assigned to the
516 register, either before (PRE_MODIFY) or after (POST_MODIFY)
517 evaluating the address.
518 Currently, the compiler can only handle second operands of the
519 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
520 the first operand of the PLUS has to be the same register as
521 the first operand of the *_MODIFY. */
522 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
523 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
525 /* Comparison operations. The ordered comparisons exist in two
526 flavors, signed and unsigned. */
527 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
528 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
529 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
530 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
531 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
532 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
533 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
534 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
535 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
536 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
538 /* Additional floating point unordered comparison flavors. */
539 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
540 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
542 /* These are equivalent to unordered or ... */
543 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
544 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
545 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
546 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
547 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
549 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
550 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
552 /* Represents the result of sign-extending the sole operand.
553 The machine modes of the operand and of the SIGN_EXTEND expression
554 determine how much sign-extension is going on. */
555 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
557 /* Similar for zero-extension (such as unsigned short to int). */
558 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
560 /* Similar but here the operand has a wider mode. */
561 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
563 /* Similar for extending floating-point values (such as SFmode to DFmode). */
564 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
565 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
567 /* Conversion of fixed point operand to floating point value. */
568 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
570 /* With fixed-point machine mode:
571 Conversion of floating point operand to fixed point value.
572 Value is defined only when the operand's value is an integer.
573 With floating-point machine mode (and operand with same mode):
574 Operand is rounded toward zero to produce an integer value
575 represented in floating point. */
576 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
578 /* Conversion of unsigned fixed point operand to floating point value. */
579 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
581 /* With fixed-point machine mode:
582 Conversion of floating point operand to *unsigned* fixed point value.
583 Value is defined only when the operand's value is an integer. */
584 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
586 /* Conversions involving fractional fixed-point types without saturation,
588 fractional to fractional (of different precision),
589 signed integer to fractional,
590 fractional to signed integer,
591 floating point to fractional,
592 fractional to floating point.
593 NOTE: fractional can be either signed or unsigned for conversions. */
594 DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY)
596 /* Conversions involving fractional fixed-point types and unsigned integer
597 without saturation, including:
598 unsigned integer to fractional,
599 fractional to unsigned integer.
600 NOTE: fractional can be either signed or unsigned for conversions. */
601 DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY)
603 /* Conversions involving fractional fixed-point types with saturation,
605 fractional to fractional (of different precision),
606 signed integer to fractional,
607 floating point to fractional.
608 NOTE: fractional can be either signed or unsigned for conversions. */
609 DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY)
611 /* Conversions involving fractional fixed-point types and unsigned integer
612 with saturation, including:
613 unsigned integer to fractional.
614 NOTE: fractional can be either signed or unsigned for conversions. */
615 DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY)
618 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
621 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
624 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
626 /* Find first bit that is set.
627 Value is 1 + number of trailing zeros in the arg.,
629 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
631 /* Count leading zeros. */
632 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
634 /* Count trailing zeros. */
635 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
637 /* Population count (number of 1 bits). */
638 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
640 /* Population parity (number of 1 bits modulo 2). */
641 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
643 /* Reference to a signed bit-field of specified size and position.
644 Operand 0 is the memory unit (usually SImode or QImode) which
645 contains the field's first bit. Operand 1 is the width, in bits.
646 Operand 2 is the number of bits in the memory unit before the
647 first bit of this field.
648 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
649 operand 2 counts from the msb of the memory unit.
650 Otherwise, the first bit is the lsb and operand 2 counts from
651 the lsb of the memory unit.
652 This kind of expression can not appear as an lvalue in RTL. */
653 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
655 /* Similar for unsigned bit-field.
656 But note! This kind of expression _can_ appear as an lvalue. */
657 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
659 /* For RISC machines. These save memory when splitting insns. */
661 /* HIGH are the high-order bits of a constant expression. */
662 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
664 /* LO_SUM is the sum of a register and the low-order bits
665 of a constant expression. */
666 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
668 /* Describes a merge operation between two vector values.
669 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
670 that specifies where the parts of the result are taken from. Set bits
671 indicate operand 0, clear bits indicate operand 1. The parts are defined
672 by the mode of the vectors. */
673 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
675 /* Describes an operation that selects parts of a vector.
676 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
677 a CONST_INT for each of the subparts of the result vector, giving the
678 number of the source subpart that should be stored into it. */
679 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
681 /* Describes a vector concat operation. Operands 0 and 1 are the source
682 vectors, the result is a vector that is as long as operands 0 and 1
683 combined and is the concatenation of the two source vectors. */
684 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
686 /* Describes an operation that converts a small vector into a larger one by
687 duplicating the input values. The output vector mode must have the same
688 submodes as the input vector mode, and the number of output parts must be
689 an integer multiple of the number of input parts. */
690 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
692 /* Addition with signed saturation */
693 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
695 /* Addition with unsigned saturation */
696 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
698 /* Operand 0 minus operand 1, with signed saturation. */
699 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
701 /* Negation with signed saturation. */
702 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
703 /* Negation with unsigned saturation. */
704 DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY)
706 /* Absolute value with signed saturation. */
707 DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY)
709 /* Shift left with signed saturation. */
710 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
712 /* Shift left with unsigned saturation. */
713 DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH)
715 /* Operand 0 minus operand 1, with unsigned saturation. */
716 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
718 /* Signed saturating truncate. */
719 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
721 /* Unsigned saturating truncate. */
722 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
724 /* Information about the variable and its location. */
725 /* Changed 'te' to 'tei'; the 'i' field is for recording
726 initialization status of variables. */
727 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA)
729 /* All expressions from this point forward appear only in machine
731 #ifdef GENERATOR_FILE
733 /* Include a secondary machine-description file at this point. */
734 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
736 /* Pattern-matching operators: */
738 /* Use the function named by the second arg (the string)
739 as a predicate; if matched, store the structure that was matched
740 in the operand table at index specified by the first arg (the integer).
741 If the second arg is the null string, the structure is just stored.
743 A third string argument indicates to the register allocator restrictions
744 on where the operand can be allocated.
746 If the target needs no restriction on any instruction this field should
749 The string is prepended by:
750 '=' to indicate the operand is only written to.
751 '+' to indicate the operand is both read and written to.
753 Each character in the string represents an allocable class for an operand.
754 'g' indicates the operand can be any valid class.
755 'i' indicates the operand can be immediate (in the instruction) data.
756 'r' indicates the operand can be in a register.
757 'm' indicates the operand can be in memory.
758 'o' a subset of the 'm' class. Those memory addressing modes that
759 can be offset at compile time (have a constant added to them).
761 Other characters indicate target dependent operand classes and
762 are described in each target's machine description.
764 For instructions with more than one operand, sets of classes can be
765 separated by a comma to indicate the appropriate multi-operand constraints.
766 There must be a 1 to 1 correspondence between these sets of classes in
767 all operands for an instruction.
769 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
771 /* Match a SCRATCH or a register. When used to generate rtl, a
772 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
773 the desired mode and the first argument is the operand number.
774 The second argument is the constraint. */
775 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
777 /* Apply a predicate, AND match recursively the operands of the rtx.
778 Operand 0 is the operand-number, as in match_operand.
779 Operand 1 is a predicate to apply (as a string, a function name).
780 Operand 2 is a vector of expressions, each of which must match
781 one subexpression of the rtx this construct is matching. */
782 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
784 /* Match a PARALLEL of arbitrary length. The predicate is applied
785 to the PARALLEL and the initial expressions in the PARALLEL are matched.
786 Operand 0 is the operand-number, as in match_operand.
787 Operand 1 is a predicate to apply to the PARALLEL.
788 Operand 2 is a vector of expressions, each of which must match the
789 corresponding element in the PARALLEL. */
790 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
792 /* Match only something equal to what is stored in the operand table
793 at the index specified by the argument. Use with MATCH_OPERAND. */
794 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
796 /* Match only something equal to what is stored in the operand table
797 at the index specified by the argument. Use with MATCH_OPERATOR. */
798 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
800 /* Match only something equal to what is stored in the operand table
801 at the index specified by the argument. Use with MATCH_PARALLEL. */
802 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
804 /* Appears only in define_predicate/define_special_predicate
805 expressions. Evaluates true only if the operand has an RTX code
806 from the set given by the argument (a comma-separated list). If the
807 second argument is present and nonempty, it is a sequence of digits
808 and/or letters which indicates the subexpression to test, using the
809 same syntax as genextract/genrecog's location strings: 0-9 for
810 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
811 the result of the one before it. */
812 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
814 /* Appears only in define_predicate/define_special_predicate
815 expressions. The argument is a C expression to be injected at this
816 point in the predicate formula. */
817 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
819 /* Insn (and related) definitions. */
821 /* Definition of the pattern for one kind of instruction.
823 0: names this instruction.
824 If the name is the null string, the instruction is in the
825 machine description just to be recognized, and will never be emitted by
826 the tree to rtl expander.
828 2: is a string which is a C expression
829 giving an additional condition for recognizing this pattern.
830 A null string means no extra condition.
831 3: is the action to execute if this pattern is matched.
832 If this assembler code template starts with a * then it is a fragment of
833 C code to run to decide on a template to use. Otherwise, it is the
835 4: optionally, a vector of attributes for this insn.
837 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
839 /* Definition of a peephole optimization.
840 1st operand: vector of insn patterns to match
841 2nd operand: C expression that must be true
842 3rd operand: template or C code to produce assembler output.
843 4: optionally, a vector of attributes for this insn.
845 This form is deprecated; use define_peephole2 instead. */
846 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
848 /* Definition of a split operation.
849 1st operand: insn pattern to match
850 2nd operand: C expression that must be true
851 3rd operand: vector of insn patterns to place into a SEQUENCE
852 4th operand: optionally, some C code to execute before generating the
853 insns. This might, for example, create some RTX's and store them in
854 elements of `recog_data.operand' for use by the vector of
856 (`operands' is an alias here for `recog_data.operand'). */
857 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
859 /* Definition of an insn and associated split.
860 This is the concatenation, with a few modifications, of a define_insn
861 and a define_split which share the same pattern.
863 0: names this instruction.
864 If the name is the null string, the instruction is in the
865 machine description just to be recognized, and will never be emitted by
866 the tree to rtl expander.
868 2: is a string which is a C expression
869 giving an additional condition for recognizing this pattern.
870 A null string means no extra condition.
871 3: is the action to execute if this pattern is matched.
872 If this assembler code template starts with a * then it is a fragment of
873 C code to run to decide on a template to use. Otherwise, it is the
875 4: C expression that must be true for split. This may start with "&&"
876 in which case the split condition is the logical and of the insn
877 condition and what follows the "&&" of this operand.
878 5: vector of insn patterns to place into a SEQUENCE
879 6: optionally, some C code to execute before generating the
880 insns. This might, for example, create some RTX's and store them in
881 elements of `recog_data.operand' for use by the vector of
883 (`operands' is an alias here for `recog_data.operand').
884 7: optionally, a vector of attributes for this insn. */
885 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
887 /* Definition of an RTL peephole operation.
888 Follows the same arguments as define_split. */
889 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
891 /* Define how to generate multiple insns for a standard insn name.
892 1st operand: the insn name.
893 2nd operand: vector of insn-patterns.
894 Use match_operand to substitute an element of `recog_data.operand'.
895 3rd operand: C expression that must be true for this to be available.
896 This may not test any operands.
897 4th operand: Extra C code to execute before generating the insns.
898 This might, for example, create some RTX's and store them in
899 elements of `recog_data.operand' for use by the vector of
901 (`operands' is an alias here for `recog_data.operand'). */
902 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
904 /* Define a requirement for delay slots.
905 1st operand: Condition involving insn attributes that, if true,
906 indicates that the insn requires the number of delay slots
908 2nd operand: Vector whose length is the three times the number of delay
910 Each entry gives three conditions, each involving attributes.
911 The first must be true for an insn to occupy that delay slot
912 location. The second is true for all insns that can be
913 annulled if the branch is true and the third is true for all
914 insns that can be annulled if the branch is false.
916 Multiple DEFINE_DELAYs may be present. They indicate differing
917 requirements for delay slots. */
918 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
920 /* Define attribute computation for `asm' instructions. */
921 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
923 /* Definition of a conditional execution meta operation. Automatically
924 generates new instances of DEFINE_INSN, selected by having attribute
925 "predicable" true. The new pattern will contain a COND_EXEC and the
926 predicate at top-level.
929 0: The predicate pattern. The top-level form should match a
930 relational operator. Operands should have only one alternative.
931 1: A C expression giving an additional condition for recognizing
932 the generated pattern.
933 2: A template or C code to produce assembler output. */
934 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
936 /* Definition of an operand predicate. The difference between
937 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
938 not warn about a match_operand with no mode if it has a predicate
939 defined with DEFINE_SPECIAL_PREDICATE.
942 0: The name of the predicate.
943 1: A boolean expression which computes whether or not the predicate
944 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
945 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
946 can calculate the set of RTX codes that can possibly match.
947 2: A C function body which must return true for the predicate to match.
948 Optional. Use this when the test is too complicated to fit into a
949 match_test expression. */
950 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
951 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
953 /* Definition of a register operand constraint. This simply maps the
954 constraint string to a register class.
957 0: The name of the constraint (often, but not always, a single letter).
958 1: A C expression which evaluates to the appropriate register class for
959 this constraint. If this is not just a constant, it should look only
960 at -m switches and the like.
961 2: A docstring for this constraint, in Texinfo syntax; not currently
962 used, in future will be incorporated into the manual's list of
963 machine-specific operand constraints. */
964 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
966 /* Definition of a non-register operand constraint. These look at the
967 operand and decide whether it fits the constraint.
969 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
970 It is appropriate for constant-only constraints, and most others.
972 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
973 to match, if it doesn't already, by converting the operand to the form
974 (mem (reg X)) where X is a base register. It is suitable for constraints
975 that describe a subset of all memory references.
977 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
978 to match, if it doesn't already, by converting the operand to the form
979 (reg X) where X is a base register. It is suitable for constraints that
980 describe a subset of all address references.
982 When in doubt, use plain DEFINE_CONSTRAINT.
985 0: The name of the constraint (often, but not always, a single letter).
986 1: A docstring for this constraint, in Texinfo syntax; not currently
987 used, in future will be incorporated into the manual's list of
988 machine-specific operand constraints.
989 2: A boolean expression which computes whether or not the constraint
990 matches. It should follow the same rules as a define_predicate
991 expression, including the bit about specifying the set of RTX codes
992 that could possibly match. MATCH_TEST subexpressions may make use of
994 `op' - the RTL object defining the operand.
995 `mode' - the mode of `op'.
996 `ival' - INTVAL(op), if op is a CONST_INT.
997 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
998 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
999 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
1001 Do not use ival/hval/lval/rval if op is not the appropriate kind of
1003 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
1004 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
1005 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
1008 /* Constructions for CPU pipeline description described by NDFAs. */
1010 /* (define_cpu_unit string [string]) describes cpu functional
1011 units (separated by comma).
1013 1st operand: Names of cpu functional units.
1014 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
1016 All define_reservations, define_cpu_units, and
1017 define_query_cpu_units should have unique names which may not be
1019 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
1021 /* (define_query_cpu_unit string [string]) describes cpu functional
1022 units analogously to define_cpu_unit. The reservation of such
1023 units can be queried for automaton state. */
1024 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
1026 /* (exclusion_set string string) means that each CPU functional unit
1027 in the first string can not be reserved simultaneously with any
1028 unit whose name is in the second string and vise versa. CPU units
1029 in the string are separated by commas. For example, it is useful
1030 for description CPU with fully pipelined floating point functional
1031 unit which can execute simultaneously only single floating point
1032 insns or only double floating point insns. All CPU functional
1033 units in a set should belong to the same automaton. */
1034 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
1036 /* (presence_set string string) means that each CPU functional unit in
1037 the first string can not be reserved unless at least one of pattern
1038 of units whose names are in the second string is reserved. This is
1039 an asymmetric relation. CPU units or unit patterns in the strings
1040 are separated by commas. Pattern is one unit name or unit names
1041 separated by white-spaces.
1043 For example, it is useful for description that slot1 is reserved
1044 after slot0 reservation for a VLIW processor. We could describe it
1045 by the following construction
1047 (presence_set "slot1" "slot0")
1049 Or slot1 is reserved only after slot0 and unit b0 reservation. In
1050 this case we could write
1052 (presence_set "slot1" "slot0 b0")
1054 All CPU functional units in a set should belong to the same
1056 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
1058 /* (final_presence_set string string) is analogous to `presence_set'.
1059 The difference between them is when checking is done. When an
1060 instruction is issued in given automaton state reflecting all
1061 current and planned unit reservations, the automaton state is
1062 changed. The first state is a source state, the second one is a
1063 result state. Checking for `presence_set' is done on the source
1064 state reservation, checking for `final_presence_set' is done on the
1065 result reservation. This construction is useful to describe a
1066 reservation which is actually two subsequent reservations. For
1069 (presence_set "slot1" "slot0")
1071 the following insn will be never issued (because slot1 requires
1072 slot0 which is absent in the source state).
1074 (define_reservation "insn_and_nop" "slot0 + slot1")
1076 but it can be issued if we use analogous `final_presence_set'. */
1077 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1079 /* (absence_set string string) means that each CPU functional unit in
1080 the first string can be reserved only if each pattern of units
1081 whose names are in the second string is not reserved. This is an
1082 asymmetric relation (actually exclusion set is analogous to this
1083 one but it is symmetric). CPU units or unit patterns in the string
1084 are separated by commas. Pattern is one unit name or unit names
1085 separated by white-spaces.
1087 For example, it is useful for description that slot0 can not be
1088 reserved after slot1 or slot2 reservation for a VLIW processor. We
1089 could describe it by the following construction
1091 (absence_set "slot2" "slot0, slot1")
1093 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1094 slot1 and unit b1 are reserved . In this case we could write
1096 (absence_set "slot2" "slot0 b0, slot1 b1")
1098 All CPU functional units in a set should to belong the same
1100 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1102 /* (final_absence_set string string) is analogous to `absence_set' but
1103 checking is done on the result (state) reservation. See comments
1104 for `final_presence_set'. */
1105 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1107 /* (define_bypass number out_insn_names in_insn_names) names bypass
1108 with given latency (the first number) from insns given by the first
1109 string (see define_insn_reservation) into insns given by the second
1110 string. Insn names in the strings are separated by commas. The
1111 third operand is optional name of function which is additional
1112 guard for the bypass. The function will get the two insns as
1113 parameters. If the function returns zero the bypass will be
1114 ignored for this case. Additional guard is necessary to recognize
1115 complicated bypasses, e.g. when consumer is load address. */
1116 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1118 /* (define_automaton string) describes names of automata generated and
1119 used for pipeline hazards recognition. The names are separated by
1120 comma. Actually it is possibly to generate the single automaton
1121 but unfortunately it can be very large. If we use more one
1122 automata, the summary size of the automata usually is less than the
1123 single one. The automaton name is used in define_cpu_unit and
1124 define_query_cpu_unit. All automata should have unique names. */
1125 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1127 /* (automata_option string) describes option for generation of
1128 automata. Currently there are the following options:
1130 o "no-minimization" which makes no minimization of automata. This
1131 is only worth to do when we are debugging the description and
1132 need to look more accurately at reservations of states.
1134 o "time" which means printing additional time statistics about
1135 generation of automata.
1137 o "v" which means generation of file describing the result
1138 automata. The file has suffix `.dfa' and can be used for the
1139 description verification and debugging.
1141 o "w" which means generation of warning instead of error for
1142 non-critical errors.
1144 o "ndfa" which makes nondeterministic finite state automata.
1146 o "progress" which means output of a progress bar showing how many
1147 states were generated so far for automaton being processed. */
1148 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1150 /* (define_reservation string string) names reservation (the first
1151 string) of cpu functional units (the 2nd string). Sometimes unit
1152 reservations for different insns contain common parts. In such
1153 case, you can describe common part and use its name (the 1st
1154 parameter) in regular expression in define_insn_reservation. All
1155 define_reservations, define_cpu_units, and define_query_cpu_units
1156 should have unique names which may not be "nothing". */
1157 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1159 /* (define_insn_reservation name default_latency condition regexpr)
1160 describes reservation of cpu functional units (the 3nd operand) for
1161 instruction which is selected by the condition (the 2nd parameter).
1162 The first parameter is used for output of debugging information.
1163 The reservations are described by a regular expression according
1164 the following syntax:
1166 regexp = regexp "," oneof
1169 oneof = oneof "|" allof
1172 allof = allof "+" repeat
1175 repeat = element "*" number
1178 element = cpu_function_unit_name
1184 1. "," is used for describing start of the next cycle in
1187 2. "|" is used for describing the reservation described by the
1188 first regular expression *or* the reservation described by the
1189 second regular expression *or* etc.
1191 3. "+" is used for describing the reservation described by the
1192 first regular expression *and* the reservation described by the
1193 second regular expression *and* etc.
1195 4. "*" is used for convenience and simply means sequence in
1196 which the regular expression are repeated NUMBER times with
1197 cycle advancing (see ",").
1199 5. cpu functional unit name which means its reservation.
1201 6. reservation name -- see define_reservation.
1203 7. string "nothing" means no units reservation. */
1205 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1207 /* Expressions used for insn attributes. */
1209 /* Definition of an insn attribute.
1210 1st operand: name of the attribute
1211 2nd operand: comma-separated list of possible attribute values
1212 3rd operand: expression for the default value of the attribute. */
1213 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1215 /* Marker for the name of an attribute. */
1216 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1218 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1219 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1222 (set_attr "name" "value") is equivalent to
1223 (set (attr "name") (const_string "value")) */
1224 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1226 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1227 specify that attribute values are to be assigned according to the
1228 alternative matched.
1230 The following three expressions are equivalent:
1232 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1233 (eq_attrq "alternative" "2") (const_string "a2")]
1234 (const_string "a3")))
1235 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1236 (const_string "a3")])
1237 (set_attr "att" "a1,a2,a3")
1239 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1241 /* A conditional expression true if the value of the specified attribute of
1242 the current insn equals the specified value. The first operand is the
1243 attribute name and the second is the comparison value. */
1244 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1246 /* A special case of the above representing a set of alternatives. The first
1247 operand is bitmap of the set, the second one is the default value. */
1248 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1250 /* A conditional expression which is true if the specified flag is
1251 true for the insn being scheduled in reorg.
1253 genattr.c defines the following flags which can be tested by
1254 (attr_flag "foo") expressions in eligible_for_delay.
1256 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1258 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1260 /* General conditional. The first operand is a vector composed of pairs of
1261 expressions. The first element of each pair is evaluated, in turn.
1262 The value of the conditional is the second expression of the first pair
1263 whose first expression evaluates nonzero. If none of the expressions is
1264 true, the second operand will be used as the value of the conditional. */
1265 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1267 #endif /* GENERATOR_FILE */
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