1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
50 an rtx code that can be used to represent a constant object
53 an rtx code that can be used to represent an object (e.g, REG, MEM)
55 an rtx code for a comparison (e.g, LT, GT)
57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
71 an rtx code for something that matches in insns (e.g, MATCH_DUP)
73 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
77 All of the expressions that appear only in machine descriptions,
78 not in RTL used by the compiler itself, are at the end of the file. */
80 /* Unknown, or no such operation; the enumeration constant should have
82 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
84 /* ---------------------------------------------------------------------
85 Expressions used in constructing lists.
86 --------------------------------------------------------------------- */
88 /* a linked list of expressions */
89 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
91 /* a linked list of instructions.
92 The insns are represented in print by their uids. */
93 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
95 /* SEQUENCE appears in the result of a `gen_...' function
96 for a DEFINE_EXPAND that wants to make several insns.
97 Its elements are the bodies of the insns that should be made.
98 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
99 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
101 /* Refers to the address of its argument. This is only used in alias.c. */
102 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
104 /* ----------------------------------------------------------------------
105 Expression types used for things in the instruction chain.
107 All formats must start with "iuu" to handle the chain.
108 Each insn expression holds an rtl instruction and its semantics
109 during back-end processing.
110 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
112 ---------------------------------------------------------------------- */
114 /* An instruction that cannot jump. */
115 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
117 /* An instruction that can possibly jump.
118 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
119 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
121 /* An instruction that can possibly call a subroutine
122 but which will not change which instruction comes next
123 in the current function.
124 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
125 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
126 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
128 /* A marker that indicates that control will not flow through. */
129 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
131 /* Holds a label that is followed by instructions.
133 4: is used in jump.c for the use-count of the label.
134 5: is used in flow.c to point to the chain of label_ref's to this label.
135 6: is a number that is unique in the entire compilation.
136 7: is the user-given name of the label, if any. */
137 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
139 #ifdef USE_MAPPED_LOCATION
140 /* Say where in the code a source line starts, for symbol table's sake.
142 4: unused if line number > 0, note-specific data otherwise.
143 5: line number if > 0, enum note_insn otherwise.
144 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
146 /* Say where in the code a source line starts, for symbol table's sake.
148 4: filename, if line number > 0, note-specific data otherwise.
149 5: line number if > 0, enum note_insn otherwise.
150 6: unique number if line number == note_insn_deleted_label. */
152 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
154 /* ----------------------------------------------------------------------
155 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
156 ---------------------------------------------------------------------- */
158 /* Conditionally execute code.
159 Operand 0 is the condition that if true, the code is executed.
160 Operand 1 is the code to be executed (typically a SET).
162 Semantics are that there are no side effects if the condition
163 is false. This pattern is created automatically by the if_convert
164 pass run after reload or by target-specific splitters. */
165 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
167 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
168 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
170 /* A string that is passed through to the assembler as input.
171 One can obviously pass comments through by using the
172 assembler comment syntax.
173 These occur in an insn all by themselves as the PATTERN.
174 They also appear inside an ASM_OPERANDS
175 as a convenient way to hold a string. */
176 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
178 #ifdef USE_MAPPED_LOCATION
179 /* An assembler instruction with operands.
180 1st operand is the instruction template.
181 2nd operand is the constraint for the output.
182 3rd operand is the number of the output this expression refers to.
183 When an insn stores more than one value, a separate ASM_OPERANDS
184 is made for each output; this integer distinguishes them.
185 4th is a vector of values of input operands.
186 5th is a vector of modes and constraints for the input operands.
187 Each element is an ASM_INPUT containing a constraint string
188 and whose mode indicates the mode of the input operand.
189 6th is the source line number. */
190 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
192 /* An assembler instruction with operands.
193 1st operand is the instruction template.
194 2nd operand is the constraint for the output.
195 3rd operand is the number of the output this expression refers to.
196 When an insn stores more than one value, a separate ASM_OPERANDS
197 is made for each output; this integer distinguishes them.
198 4th is a vector of values of input operands.
199 5th is a vector of modes and constraints for the input operands.
200 Each element is an ASM_INPUT containing a constraint string
201 and whose mode indicates the mode of the input operand.
202 6th is the name of the containing source file.
203 7th is the source line number. */
204 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
207 /* A machine-specific operation.
208 1st operand is a vector of operands being used by the operation so that
209 any needed reloads can be done.
210 2nd operand is a unique value saying which of a number of machine-specific
211 operations is to be performed.
212 (Note that the vector must be the first operand because of the way that
213 genrecog.c record positions within an insn.)
214 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
215 or inside an expression. */
216 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
218 /* Similar, but a volatile operation and one which may trap. */
219 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
221 /* Vector of addresses, stored as full words. */
222 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
223 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
225 /* Vector of address differences X0 - BASE, X1 - BASE, ...
226 First operand is BASE; the vector contains the X's.
227 The machine mode of this rtx says how much space to leave
228 for each difference and is adjusted by branch shortening if
229 CASE_VECTOR_SHORTEN_MODE is defined.
230 The third and fourth operands store the target labels with the
231 minimum and maximum addresses respectively.
232 The fifth operand stores flags for use by branch shortening.
233 Set at the start of shorten_branches:
234 min_align: the minimum alignment for any of the target labels.
235 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
236 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
237 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
238 min_after_base: true iff minimum address target label is after BASE.
239 max_after_base: true iff maximum address target label is after BASE.
240 Set by the actual branch shortening process:
241 offset_unsigned: true iff offsets have to be treated as unsigned.
242 scale: scaling that is necessary to make offsets fit into the mode.
244 The third, fourth and fifth operands are only valid when
245 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
248 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
250 /* Memory prefetch, with attributes supported on some targets.
251 Operand 1 is the address of the memory to fetch.
252 Operand 2 is 1 for a write access, 0 otherwise.
253 Operand 3 is the level of temporal locality; 0 means there is no
254 temporal locality and 1, 2, and 3 are for increasing levels of temporal
257 The attributes specified by operands 2 and 3 are ignored for targets
258 whose prefetch instructions do not support them. */
259 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
261 /* ----------------------------------------------------------------------
262 At the top level of an instruction (perhaps under PARALLEL).
263 ---------------------------------------------------------------------- */
266 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
267 Operand 2 is the value stored there.
268 ALL assignment must use SET.
269 Instructions that do multiple assignments must use multiple SET,
271 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
273 /* Indicate something is used in a way that we don't want to explain.
274 For example, subroutine calls will use the register
275 in which the static chain is passed. */
276 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
278 /* Indicate something is clobbered in a way that we don't want to explain.
279 For example, subroutine calls will clobber some physical registers
280 (the ones that are by convention not saved). */
281 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
283 /* Call a subroutine.
284 Operand 1 is the address to call.
285 Operand 2 is the number of arguments. */
287 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
289 /* Return from a subroutine. */
291 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
294 Operand 1 is the condition.
295 Operand 2 is the trap code.
296 For an unconditional trap, make the condition (const_int 1). */
297 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
299 /* Placeholder for _Unwind_Resume before we know if a function call
300 or a branch is needed. Operand 1 is the exception region from
301 which control is flowing. */
302 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
304 /* ----------------------------------------------------------------------
305 Primitive values for use in expressions.
306 ---------------------------------------------------------------------- */
308 /* numeric integer constant */
309 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
311 /* numeric floating point constant.
312 Operands hold the value. They are all 'w' and there may be from 2 to 6;
314 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
316 /* Describes a vector constant. */
317 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_EXTRA)
319 /* String constant. Used for attributes in machine descriptions and
320 for special cases in DWARF2 debug output. NOT used for source-
321 language string constants. */
322 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
324 /* This is used to encapsulate an expression whose value is constant
325 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
326 recognized as a constant operand rather than by arithmetic instructions. */
328 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
330 /* program counter. Ordinary jumps are represented
331 by a SET whose first operand is (PC). */
332 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
334 /* Used in the cselib routines to describe a value. Objects of this
335 kind are only allocated in cselib.c, in an alloc pool instead of
336 in GC memory. The only operand of a VALUE is a cselib_val_struct. */
337 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
339 /* A register. The "operand" is the register number, accessed with
340 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
341 than a hardware register is being referred to. The second operand
342 holds the original register number - this will be different for a
343 pseudo register that got turned into a hard register. The third
344 operand points to a reg_attrs structure.
345 This rtx needs to have as many (or more) fields as a MEM, since we
346 can change REG rtx's into MEMs during reload. */
347 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
349 /* A scratch register. This represents a register used only within a
350 single insn. It will be turned into a REG during register allocation
351 or reload unless the constraint indicates that the register won't be
352 needed, in which case it can remain a SCRATCH. This code is
353 marked as having one operand so it can be turned into a REG. */
354 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
356 /* One word of a multi-word value.
357 The first operand is the complete value; the second says which word.
358 The WORDS_BIG_ENDIAN flag controls whether word number 0
359 (as numbered in a SUBREG) is the most or least significant word.
361 This is also used to refer to a value in a different machine mode.
362 For example, it can be used to refer to a SImode value as if it were
363 Qimode, or vice versa. Then the word number is always 0. */
364 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
366 /* This one-argument rtx is used for move instructions
367 that are guaranteed to alter only the low part of a destination.
368 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
369 has an unspecified effect on the high part of REG,
370 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
371 is guaranteed to alter only the bits of REG that are in HImode.
373 The actual instruction used is probably the same in both cases,
374 but the register constraints may be tighter when STRICT_LOW_PART
377 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
379 /* (CONCAT a b) represents the virtual concatenation of a and b
380 to make a value that has as many bits as a and b put together.
381 This is used for complex values. Normally it appears only
382 in DECL_RTLs and during RTL generation, but not in the insn chain. */
383 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
385 /* A memory location; operand is the address. The second operand is the
386 alias set to which this MEM belongs. We use `0' instead of `w' for this
387 field so that the field need not be specified in machine descriptions. */
388 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
390 /* Reference to an assembler label in the code for this function.
391 The operand is a CODE_LABEL found in the insn chain.
392 The unprinted field 1 is used in flow.c for the LABEL_NEXTREF. */
393 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u0", RTX_CONST_OBJ)
395 /* Reference to a named label:
396 Operand 0: label name
397 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
398 Operand 2: tree from which this symbol is derived, or null.
399 This is either a DECL node, or some kind of constant. */
400 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
402 /* The condition code register is represented, in our imagination,
403 as a register holding a value that can be compared to zero.
404 In fact, the machine has already compared them and recorded the
405 results; but instructions that look at the condition code
406 pretend to be looking at the entire value and comparing it. */
407 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
409 /* ----------------------------------------------------------------------
410 Expressions for operators in an rtl pattern
411 ---------------------------------------------------------------------- */
413 /* if_then_else. This is used in representing ordinary
414 conditional jump instructions.
419 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
421 /* Comparison, produces a condition code result. */
422 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
425 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
427 /* Operand 0 minus operand 1. */
428 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
430 /* Minus operand 0. */
431 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
433 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
435 /* Operand 0 divided by operand 1. */
436 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
437 /* Remainder of operand 0 divided by operand 1. */
438 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
440 /* Unsigned divide and remainder. */
441 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
442 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
444 /* Bitwise operations. */
445 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
447 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
449 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
451 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
454 0: value to be shifted.
455 1: number of bits. */
456 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
457 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
458 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
459 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
460 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
462 /* Minimum and maximum values of two operands. We need both signed and
463 unsigned forms. (We cannot use MIN for SMIN because it conflicts
464 with a macro of the same name.) */
466 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
467 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
468 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
469 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
471 /* These unary operations are used to represent incrementation
472 and decrementation as they occur in memory addresses.
473 The amount of increment or decrement are not represented
474 because they can be understood from the machine-mode of the
475 containing MEM. These operations exist in only two cases:
476 1. pushes onto the stack.
477 2. created automatically by the life_analysis pass in flow.c. */
478 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
479 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
480 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
481 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
483 /* These binary operations are used to represent generic address
484 side-effects in memory addresses, except for simple incrementation
485 or decrementation which use the above operations. They are
486 created automatically by the life_analysis pass in flow.c.
487 The first operand is a REG which is used as the address.
488 The second operand is an expression that is assigned to the
489 register, either before (PRE_MODIFY) or after (POST_MODIFY)
490 evaluating the address.
491 Currently, the compiler can only handle second operands of the
492 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
493 the first operand of the PLUS has to be the same register as
494 the first operand of the *_MODIFY. */
495 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
496 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
498 /* Comparison operations. The ordered comparisons exist in two
499 flavors, signed and unsigned. */
500 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
501 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
502 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
503 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
504 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
505 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
506 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
507 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
508 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
509 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
511 /* Additional floating point unordered comparison flavors. */
512 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
513 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
515 /* These are equivalent to unordered or ... */
516 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
517 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
518 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
519 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
520 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
522 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
523 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
525 /* Represents the result of sign-extending the sole operand.
526 The machine modes of the operand and of the SIGN_EXTEND expression
527 determine how much sign-extension is going on. */
528 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
530 /* Similar for zero-extension (such as unsigned short to int). */
531 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
533 /* Similar but here the operand has a wider mode. */
534 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
536 /* Similar for extending floating-point values (such as SFmode to DFmode). */
537 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
538 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
540 /* Conversion of fixed point operand to floating point value. */
541 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
543 /* With fixed-point machine mode:
544 Conversion of floating point operand to fixed point value.
545 Value is defined only when the operand's value is an integer.
546 With floating-point machine mode (and operand with same mode):
547 Operand is rounded toward zero to produce an integer value
548 represented in floating point. */
549 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
551 /* Conversion of unsigned fixed point operand to floating point value. */
552 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
554 /* With fixed-point machine mode:
555 Conversion of floating point operand to *unsigned* fixed point value.
556 Value is defined only when the operand's value is an integer. */
557 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
560 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
563 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
565 /* Find first bit that is set.
566 Value is 1 + number of trailing zeros in the arg.,
568 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
570 /* Count leading zeros. */
571 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
573 /* Count trailing zeros. */
574 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
576 /* Population count (number of 1 bits). */
577 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
579 /* Population parity (number of 1 bits modulo 2). */
580 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
582 /* Reference to a signed bit-field of specified size and position.
583 Operand 0 is the memory unit (usually SImode or QImode) which
584 contains the field's first bit. Operand 1 is the width, in bits.
585 Operand 2 is the number of bits in the memory unit before the
586 first bit of this field.
587 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
588 operand 2 counts from the msb of the memory unit.
589 Otherwise, the first bit is the lsb and operand 2 counts from
590 the lsb of the memory unit. */
591 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
593 /* Similar for unsigned bit-field. */
594 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
596 /* For RISC machines. These save memory when splitting insns. */
598 /* HIGH are the high-order bits of a constant expression. */
599 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
601 /* LO_SUM is the sum of a register and the low-order bits
602 of a constant expression. */
603 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
605 /* Describes a merge operation between two vector values.
606 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
607 that specifies where the parts of the result are taken from. Set bits
608 indicate operand 0, clear bits indicate operand 1. The parts are defined
609 by the mode of the vectors. */
610 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
612 /* Describes an operation that selects parts of a vector.
613 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
614 a CONST_INT for each of the subparts of the result vector, giving the
615 number of the source subpart that should be stored into it. */
616 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
618 /* Describes a vector concat operation. Operands 0 and 1 are the source
619 vectors, the result is a vector that is as long as operands 0 and 1
620 combined and is the concatenation of the two source vectors. */
621 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
623 /* Describes an operation that converts a small vector into a larger one by
624 duplicating the input values. The output vector mode must have the same
625 submodes as the input vector mode, and the number of output parts must be
626 an integer multiple of the number of input parts. */
627 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
629 /* Addition with signed saturation */
630 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
632 /* Addition with unsigned saturation */
633 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
635 /* Operand 0 minus operand 1, with signed saturation. */
636 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
638 /* Operand 0 minus operand 1, with unsigned saturation. */
639 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
641 /* Signed saturating truncate. */
642 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
644 /* Unsigned saturating truncate. */
645 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
647 /* Information about the variable and its location. */
648 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
650 /* All expressions from this point forward appear only in machine
652 #ifdef GENERATOR_FILE
654 /* Include a secondary machine-description file at this point. */
655 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
657 /* Pattern-matching operators: */
659 /* Use the function named by the second arg (the string)
660 as a predicate; if matched, store the structure that was matched
661 in the operand table at index specified by the first arg (the integer).
662 If the second arg is the null string, the structure is just stored.
664 A third string argument indicates to the register allocator restrictions
665 on where the operand can be allocated.
667 If the target needs no restriction on any instruction this field should
670 The string is prepended by:
671 '=' to indicate the operand is only written to.
672 '+' to indicate the operand is both read and written to.
674 Each character in the string represents an allocable class for an operand.
675 'g' indicates the operand can be any valid class.
676 'i' indicates the operand can be immediate (in the instruction) data.
677 'r' indicates the operand can be in a register.
678 'm' indicates the operand can be in memory.
679 'o' a subset of the 'm' class. Those memory addressing modes that
680 can be offset at compile time (have a constant added to them).
682 Other characters indicate target dependent operand classes and
683 are described in each target's machine description.
685 For instructions with more than one operand, sets of classes can be
686 separated by a comma to indicate the appropriate multi-operand constraints.
687 There must be a 1 to 1 correspondence between these sets of classes in
688 all operands for an instruction.
690 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
692 /* Match a SCRATCH or a register. When used to generate rtl, a
693 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
694 the desired mode and the first argument is the operand number.
695 The second argument is the constraint. */
696 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
698 /* Apply a predicate, AND match recursively the operands of the rtx.
699 Operand 0 is the operand-number, as in match_operand.
700 Operand 1 is a predicate to apply (as a string, a function name).
701 Operand 2 is a vector of expressions, each of which must match
702 one subexpression of the rtx this construct is matching. */
703 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
705 /* Match a PARALLEL of arbitrary length. The predicate is applied
706 to the PARALLEL and the initial expressions in the PARALLEL are matched.
707 Operand 0 is the operand-number, as in match_operand.
708 Operand 1 is a predicate to apply to the PARALLEL.
709 Operand 2 is a vector of expressions, each of which must match the
710 corresponding element in the PARALLEL. */
711 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
713 /* Match only something equal to what is stored in the operand table
714 at the index specified by the argument. Use with MATCH_OPERAND. */
715 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
717 /* Match only something equal to what is stored in the operand table
718 at the index specified by the argument. Use with MATCH_OPERATOR. */
719 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
721 /* Match only something equal to what is stored in the operand table
722 at the index specified by the argument. Use with MATCH_PARALLEL. */
723 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
725 /* Appears only in define_predicate/define_special_predicate
726 expressions. Evaluates true only if the operand has an RTX code
727 from the set given by the argument (a comma-separated list). */
728 DEF_RTL_EXPR(MATCH_CODE, "match_code", "s", RTX_MATCH)
730 /* Appears only in define_predicate/define_special_predicate
731 expressions. The argument is a C expression to be injected at this
732 point in the predicate formula. */
733 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
735 /* Insn (and related) definitions. */
737 /* Definition of the pattern for one kind of instruction.
739 0: names this instruction.
740 If the name is the null string, the instruction is in the
741 machine description just to be recognized, and will never be emitted by
742 the tree to rtl expander.
744 2: is a string which is a C expression
745 giving an additional condition for recognizing this pattern.
746 A null string means no extra condition.
747 3: is the action to execute if this pattern is matched.
748 If this assembler code template starts with a * then it is a fragment of
749 C code to run to decide on a template to use. Otherwise, it is the
751 4: optionally, a vector of attributes for this insn.
753 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
755 /* Definition of a peephole optimization.
756 1st operand: vector of insn patterns to match
757 2nd operand: C expression that must be true
758 3rd operand: template or C code to produce assembler output.
759 4: optionally, a vector of attributes for this insn.
761 This form is deprecated; use define_peephole2 instead. */
762 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
764 /* Definition of a split operation.
765 1st operand: insn pattern to match
766 2nd operand: C expression that must be true
767 3rd operand: vector of insn patterns to place into a SEQUENCE
768 4th operand: optionally, some C code to execute before generating the
769 insns. This might, for example, create some RTX's and store them in
770 elements of `recog_data.operand' for use by the vector of
772 (`operands' is an alias here for `recog_data.operand'). */
773 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
775 /* Definition of an insn and associated split.
776 This is the concatenation, with a few modifications, of a define_insn
777 and a define_split which share the same pattern.
779 0: names this instruction.
780 If the name is the null string, the instruction is in the
781 machine description just to be recognized, and will never be emitted by
782 the tree to rtl expander.
784 2: is a string which is a C expression
785 giving an additional condition for recognizing this pattern.
786 A null string means no extra condition.
787 3: is the action to execute if this pattern is matched.
788 If this assembler code template starts with a * then it is a fragment of
789 C code to run to decide on a template to use. Otherwise, it is the
791 4: C expression that must be true for split. This may start with "&&"
792 in which case the split condition is the logical and of the insn
793 condition and what follows the "&&" of this operand.
794 5: vector of insn patterns to place into a SEQUENCE
795 6: optionally, some C code to execute before generating the
796 insns. This might, for example, create some RTX's and store them in
797 elements of `recog_data.operand' for use by the vector of
799 (`operands' is an alias here for `recog_data.operand').
800 7: optionally, a vector of attributes for this insn. */
801 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
803 /* Definition of an RTL peephole operation.
804 Follows the same arguments as define_split. */
805 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
807 /* Define how to generate multiple insns for a standard insn name.
808 1st operand: the insn name.
809 2nd operand: vector of insn-patterns.
810 Use match_operand to substitute an element of `recog_data.operand'.
811 3rd operand: C expression that must be true for this to be available.
812 This may not test any operands.
813 4th operand: Extra C code to execute before generating the insns.
814 This might, for example, create some RTX's and store them in
815 elements of `recog_data.operand' for use by the vector of
817 (`operands' is an alias here for `recog_data.operand'). */
818 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
820 /* Define a requirement for delay slots.
821 1st operand: Condition involving insn attributes that, if true,
822 indicates that the insn requires the number of delay slots
824 2nd operand: Vector whose length is the three times the number of delay
826 Each entry gives three conditions, each involving attributes.
827 The first must be true for an insn to occupy that delay slot
828 location. The second is true for all insns that can be
829 annulled if the branch is true and the third is true for all
830 insns that can be annulled if the branch is false.
832 Multiple DEFINE_DELAYs may be present. They indicate differing
833 requirements for delay slots. */
834 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
836 /* Define attribute computation for `asm' instructions. */
837 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
839 /* Definition of a conditional execution meta operation. Automatically
840 generates new instances of DEFINE_INSN, selected by having attribute
841 "predicable" true. The new pattern will contain a COND_EXEC and the
842 predicate at top-level.
845 0: The predicate pattern. The top-level form should match a
846 relational operator. Operands should have only one alternative.
847 1: A C expression giving an additional condition for recognizing
848 the generated pattern.
849 2: A template or C code to produce assembler output. */
850 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
852 /* Definition of an operand predicate. The difference between
853 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
854 not warn about a match_operand with no mode if it has a predicate
855 defined with DEFINE_SPECIAL_PREDICATE.
858 0: The name of the predicate.
859 1: A boolean expression which computes whether or not the predicate
860 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
861 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
862 can calculate the set of RTX codes that can possibly match.
863 2: A C function body which must return true for the predicate to match.
864 Optional. Use this when the test is too complicated to fit into a
865 match_test expression. */
866 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
867 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
869 /* Constructions for CPU pipeline description described by NDFAs. */
871 /* (define_cpu_unit string [string]) describes cpu functional
872 units (separated by comma).
874 1st operand: Names of cpu functional units.
875 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
877 All define_reservations, define_cpu_units, and
878 define_query_cpu_units should have unique names which may not be
880 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
882 /* (define_query_cpu_unit string [string]) describes cpu functional
883 units analogously to define_cpu_unit. The reservation of such
884 units can be queried for automaton state. */
885 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
887 /* (exclusion_set string string) means that each CPU functional unit
888 in the first string can not be reserved simultaneously with any
889 unit whose name is in the second string and vise versa. CPU units
890 in the string are separated by commas. For example, it is useful
891 for description CPU with fully pipelined floating point functional
892 unit which can execute simultaneously only single floating point
893 insns or only double floating point insns. All CPU functional
894 units in a set should belong to the same automaton. */
895 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
897 /* (presence_set string string) means that each CPU functional unit in
898 the first string can not be reserved unless at least one of pattern
899 of units whose names are in the second string is reserved. This is
900 an asymmetric relation. CPU units or unit patterns in the strings
901 are separated by commas. Pattern is one unit name or unit names
902 separated by white-spaces.
904 For example, it is useful for description that slot1 is reserved
905 after slot0 reservation for a VLIW processor. We could describe it
906 by the following construction
908 (presence_set "slot1" "slot0")
910 Or slot1 is reserved only after slot0 and unit b0 reservation. In
911 this case we could write
913 (presence_set "slot1" "slot0 b0")
915 All CPU functional units in a set should belong to the same
917 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
919 /* (final_presence_set string string) is analogous to `presence_set'.
920 The difference between them is when checking is done. When an
921 instruction is issued in given automaton state reflecting all
922 current and planned unit reservations, the automaton state is
923 changed. The first state is a source state, the second one is a
924 result state. Checking for `presence_set' is done on the source
925 state reservation, checking for `final_presence_set' is done on the
926 result reservation. This construction is useful to describe a
927 reservation which is actually two subsequent reservations. For
930 (presence_set "slot1" "slot0")
932 the following insn will be never issued (because slot1 requires
933 slot0 which is absent in the source state).
935 (define_reservation "insn_and_nop" "slot0 + slot1")
937 but it can be issued if we use analogous `final_presence_set'. */
938 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
940 /* (absence_set string string) means that each CPU functional unit in
941 the first string can be reserved only if each pattern of units
942 whose names are in the second string is not reserved. This is an
943 asymmetric relation (actually exclusion set is analogous to this
944 one but it is symmetric). CPU units or unit patterns in the string
945 are separated by commas. Pattern is one unit name or unit names
946 separated by white-spaces.
948 For example, it is useful for description that slot0 can not be
949 reserved after slot1 or slot2 reservation for a VLIW processor. We
950 could describe it by the following construction
952 (absence_set "slot2" "slot0, slot1")
954 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
955 slot1 and unit b1 are reserved . In this case we could write
957 (absence_set "slot2" "slot0 b0, slot1 b1")
959 All CPU functional units in a set should to belong the same
961 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
963 /* (final_absence_set string string) is analogous to `absence_set' but
964 checking is done on the result (state) reservation. See comments
965 for `final_presence_set'. */
966 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
968 /* (define_bypass number out_insn_names in_insn_names) names bypass
969 with given latency (the first number) from insns given by the first
970 string (see define_insn_reservation) into insns given by the second
971 string. Insn names in the strings are separated by commas. The
972 third operand is optional name of function which is additional
973 guard for the bypass. The function will get the two insns as
974 parameters. If the function returns zero the bypass will be
975 ignored for this case. Additional guard is necessary to recognize
976 complicated bypasses, e.g. when consumer is load address. */
977 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
979 /* (define_automaton string) describes names of automata generated and
980 used for pipeline hazards recognition. The names are separated by
981 comma. Actually it is possibly to generate the single automaton
982 but unfortunately it can be very large. If we use more one
983 automata, the summary size of the automata usually is less than the
984 single one. The automaton name is used in define_cpu_unit and
985 define_query_cpu_unit. All automata should have unique names. */
986 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
988 /* (automata_option string) describes option for generation of
989 automata. Currently there are the following options:
991 o "no-minimization" which makes no minimization of automata. This
992 is only worth to do when we are debugging the description and
993 need to look more accurately at reservations of states.
995 o "time" which means printing additional time statistics about
996 generation of automata.
998 o "v" which means generation of file describing the result
999 automata. The file has suffix `.dfa' and can be used for the
1000 description verification and debugging.
1002 o "w" which means generation of warning instead of error for
1003 non-critical errors.
1005 o "ndfa" which makes nondeterministic finite state automata.
1007 o "progress" which means output of a progress bar showing how many
1008 states were generated so far for automaton being processed. */
1009 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1011 /* (define_reservation string string) names reservation (the first
1012 string) of cpu functional units (the 2nd string). Sometimes unit
1013 reservations for different insns contain common parts. In such
1014 case, you can describe common part and use its name (the 1st
1015 parameter) in regular expression in define_insn_reservation. All
1016 define_reservations, define_cpu_units, and define_query_cpu_units
1017 should have unique names which may not be "nothing". */
1018 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1020 /* (define_insn_reservation name default_latency condition regexpr)
1021 describes reservation of cpu functional units (the 3nd operand) for
1022 instruction which is selected by the condition (the 2nd parameter).
1023 The first parameter is used for output of debugging information.
1024 The reservations are described by a regular expression according
1025 the following syntax:
1027 regexp = regexp "," oneof
1030 oneof = oneof "|" allof
1033 allof = allof "+" repeat
1036 repeat = element "*" number
1039 element = cpu_function_unit_name
1045 1. "," is used for describing start of the next cycle in
1048 2. "|" is used for describing the reservation described by the
1049 first regular expression *or* the reservation described by the
1050 second regular expression *or* etc.
1052 3. "+" is used for describing the reservation described by the
1053 first regular expression *and* the reservation described by the
1054 second regular expression *and* etc.
1056 4. "*" is used for convenience and simply means sequence in
1057 which the regular expression are repeated NUMBER times with
1058 cycle advancing (see ",").
1060 5. cpu functional unit name which means its reservation.
1062 6. reservation name -- see define_reservation.
1064 7. string "nothing" means no units reservation. */
1066 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1068 /* Expressions used for insn attributes. */
1070 /* Definition of an insn attribute.
1071 1st operand: name of the attribute
1072 2nd operand: comma-separated list of possible attribute values
1073 3rd operand: expression for the default value of the attribute. */
1074 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1076 /* Marker for the name of an attribute. */
1077 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1079 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1080 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1083 (set_attr "name" "value") is equivalent to
1084 (set (attr "name") (const_string "value")) */
1085 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1087 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1088 specify that attribute values are to be assigned according to the
1089 alternative matched.
1091 The following three expressions are equivalent:
1093 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1094 (eq_attrq "alternative" "2") (const_string "a2")]
1095 (const_string "a3")))
1096 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1097 (const_string "a3")])
1098 (set_attr "att" "a1,a2,a3")
1100 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1102 /* A conditional expression true if the value of the specified attribute of
1103 the current insn equals the specified value. The first operand is the
1104 attribute name and the second is the comparison value. */
1105 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1107 /* A special case of the above representing a set of alternatives. The first
1108 operand is bitmap of the set, the second one is the default value. */
1109 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1111 /* A conditional expression which is true if the specified flag is
1112 true for the insn being scheduled in reorg.
1114 genattr.c defines the following flags which can be tested by
1115 (attr_flag "foo") expressions in eligible_for_delay.
1117 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1119 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1121 /* General conditional. The first operand is a vector composed of pairs of
1122 expressions. The first element of each pair is evaluated, in turn.
1123 The value of the conditional is the second expression of the first pair
1124 whose first expression evaluates nonzero. If none of the expressions is
1125 true, the second operand will be used as the value of the conditional. */
1126 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1128 #endif /* GENERATOR_FILE */
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