1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004,
6 Free Software Foundation, Inc.
8 This file is part of GCC.
10 GCC is free software; you can redistribute it and/or modify it under
11 the terms of the GNU General Public License as published by the Free
12 Software Foundation; either version 2, or (at your option) any later
15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
16 WARRANTY; without even the implied warranty of MERCHANTABILITY or
17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
20 You should have received a copy of the GNU General Public License
21 along with GCC; see the file COPYING. If not, write to the Free
22 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
26 /* Expression definitions and descriptions for all targets are in this file.
27 Some will not be used for some targets.
29 The fields in the cpp macro call "DEF_RTL_EXPR()"
30 are used to create declarations in the C source of the compiler.
34 1. The internal name of the rtx used in the C source.
35 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
36 By convention these are in UPPER_CASE.
38 2. The name of the rtx in the external ASCII format read by
39 read_rtx(), and printed by print_rtx().
40 These names are stored in rtx_name[].
41 By convention these are the internal (field 1) names in lower_case.
43 3. The print format, and type of each rtx->u.fld[] (field) in this rtx.
44 These formats are stored in rtx_format[].
45 The meaning of the formats is documented in front of this array in rtl.c
47 4. The class of the rtx. These are stored in rtx_class and are accessed
48 via the GET_RTX_CLASS macro. They are defined as follows:
51 an rtx code that can be used to represent a constant object
54 an rtx code that can be used to represent an object (e.g, REG, MEM)
56 an rtx code for a comparison (e.g, LT, GT)
58 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED)
60 an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
62 an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
64 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
66 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
68 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
70 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
72 an rtx code for something that matches in insns (e.g, MATCH_DUP)
74 an rtx code for autoincrement addressing modes (e.g. POST_DEC)
78 All of the expressions that appear only in machine descriptions,
79 not in RTL used by the compiler itself, are at the end of the file. */
81 /* Unknown, or no such operation; the enumeration constant should have
83 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA)
85 /* ---------------------------------------------------------------------
86 Expressions used in constructing lists.
87 --------------------------------------------------------------------- */
89 /* a linked list of expressions */
90 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA)
92 /* a linked list of instructions.
93 The insns are represented in print by their uids. */
94 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA)
96 /* SEQUENCE appears in the result of a `gen_...' function
97 for a DEFINE_EXPAND that wants to make several insns.
98 Its elements are the bodies of the insns that should be made.
99 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
100 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA)
102 /* Refers to the address of its argument. This is only used in alias.c. */
103 DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH)
105 /* ----------------------------------------------------------------------
106 Expression types used for things in the instruction chain.
108 All formats must start with "iuu" to handle the chain.
109 Each insn expression holds an rtl instruction and its semantics
110 during back-end processing.
111 See macros's in "rtl.h" for the meaning of each rtx->u.fld[].
113 ---------------------------------------------------------------------- */
115 /* An instruction that cannot jump. */
116 DEF_RTL_EXPR(INSN, "insn", "iuuBieiee", RTX_INSN)
118 /* An instruction that can possibly jump.
119 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
120 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBieiee0", RTX_INSN)
122 /* An instruction that can possibly call a subroutine
123 but which will not change which instruction comes next
124 in the current function.
125 Field ( rtx->u.fld[9] ) is CALL_INSN_FUNCTION_USAGE.
126 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */
127 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBieieee", RTX_INSN)
129 /* A marker that indicates that control will not flow through. */
130 DEF_RTL_EXPR(BARRIER, "barrier", "iuu000000", RTX_EXTRA)
132 /* Holds a label that is followed by instructions.
134 4: is used in jump.c for the use-count of the label.
135 5: is used in flow.c to point to the chain of label_ref's to this label.
136 6: is a number that is unique in the entire compilation.
137 7: is the user-given name of the label, if any. */
138 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA)
140 #ifdef USE_MAPPED_LOCATION
141 /* Say where in the code a source line starts, for symbol table's sake.
143 4: unused if line number > 0, note-specific data otherwise.
144 5: line number if > 0, enum note_insn otherwise.
145 6: CODE_LABEL_NUMBER if line number == NOTE_INSN_DELETED_LABEL. */
147 /* Say where in the code a source line starts, for symbol table's sake.
149 4: filename, if line number > 0, note-specific data otherwise.
150 5: line number if > 0, enum note_insn otherwise.
151 6: unique number if line number == note_insn_deleted_label. */
153 DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA)
155 /* ----------------------------------------------------------------------
156 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
157 ---------------------------------------------------------------------- */
159 /* Conditionally execute code.
160 Operand 0 is the condition that if true, the code is executed.
161 Operand 1 is the code to be executed (typically a SET).
163 Semantics are that there are no side effects if the condition
164 is false. This pattern is created automatically by the if_convert
165 pass run after reload or by target-specific splitters. */
166 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA)
168 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
169 DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA)
171 /* A string that is passed through to the assembler as input.
172 One can obviously pass comments through by using the
173 assembler comment syntax.
174 These occur in an insn all by themselves as the PATTERN.
175 They also appear inside an ASM_OPERANDS
176 as a convenient way to hold a string. */
177 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", RTX_EXTRA)
179 #ifdef USE_MAPPED_LOCATION
180 /* An assembler instruction with operands.
181 1st operand is the instruction template.
182 2nd operand is the constraint for the output.
183 3rd operand is the number of the output this expression refers to.
184 When an insn stores more than one value, a separate ASM_OPERANDS
185 is made for each output; this integer distinguishes them.
186 4th is a vector of values of input operands.
187 5th is a vector of modes and constraints for the input operands.
188 Each element is an ASM_INPUT containing a constraint string
189 and whose mode indicates the mode of the input operand.
190 6th is the source line number. */
191 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEi", RTX_EXTRA)
193 /* An assembler instruction with operands.
194 1st operand is the instruction template.
195 2nd operand is the constraint for the output.
196 3rd operand is the number of the output this expression refers to.
197 When an insn stores more than one value, a separate ASM_OPERANDS
198 is made for each output; this integer distinguishes them.
199 4th is a vector of values of input operands.
200 5th is a vector of modes and constraints for the input operands.
201 Each element is an ASM_INPUT containing a constraint string
202 and whose mode indicates the mode of the input operand.
203 6th is the name of the containing source file.
204 7th is the source line number. */
205 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", RTX_EXTRA)
208 /* A machine-specific operation.
209 1st operand is a vector of operands being used by the operation so that
210 any needed reloads can be done.
211 2nd operand is a unique value saying which of a number of machine-specific
212 operations is to be performed.
213 (Note that the vector must be the first operand because of the way that
214 genrecog.c record positions within an insn.)
215 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
216 or inside an expression. */
217 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA)
219 /* Similar, but a volatile operation and one which may trap. */
220 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA)
222 /* Vector of addresses, stored as full words. */
223 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
224 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA)
226 /* Vector of address differences X0 - BASE, X1 - BASE, ...
227 First operand is BASE; the vector contains the X's.
228 The machine mode of this rtx says how much space to leave
229 for each difference and is adjusted by branch shortening if
230 CASE_VECTOR_SHORTEN_MODE is defined.
231 The third and fourth operands store the target labels with the
232 minimum and maximum addresses respectively.
233 The fifth operand stores flags for use by branch shortening.
234 Set at the start of shorten_branches:
235 min_align: the minimum alignment for any of the target labels.
236 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
237 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
238 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
239 min_after_base: true iff minimum address target label is after BASE.
240 max_after_base: true iff maximum address target label is after BASE.
241 Set by the actual branch shortening process:
242 offset_unsigned: true iff offsets have to be treated as unsigned.
243 scale: scaling that is necessary to make offsets fit into the mode.
245 The third, fourth and fifth operands are only valid when
246 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
249 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA)
251 /* Memory prefetch, with attributes supported on some targets.
252 Operand 1 is the address of the memory to fetch.
253 Operand 2 is 1 for a write access, 0 otherwise.
254 Operand 3 is the level of temporal locality; 0 means there is no
255 temporal locality and 1, 2, and 3 are for increasing levels of temporal
258 The attributes specified by operands 2 and 3 are ignored for targets
259 whose prefetch instructions do not support them. */
260 DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA)
262 /* ----------------------------------------------------------------------
263 At the top level of an instruction (perhaps under PARALLEL).
264 ---------------------------------------------------------------------- */
267 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
268 Operand 2 is the value stored there.
269 ALL assignment must use SET.
270 Instructions that do multiple assignments must use multiple SET,
272 DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA)
274 /* Indicate something is used in a way that we don't want to explain.
275 For example, subroutine calls will use the register
276 in which the static chain is passed. */
277 DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA)
279 /* Indicate something is clobbered in a way that we don't want to explain.
280 For example, subroutine calls will clobber some physical registers
281 (the ones that are by convention not saved). */
282 DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA)
284 /* Call a subroutine.
285 Operand 1 is the address to call.
286 Operand 2 is the number of arguments. */
288 DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA)
290 /* Return from a subroutine. */
292 DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA)
295 Operand 1 is the condition.
296 Operand 2 is the trap code.
297 For an unconditional trap, make the condition (const_int 1). */
298 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA)
300 /* Placeholder for _Unwind_Resume before we know if a function call
301 or a branch is needed. Operand 1 is the exception region from
302 which control is flowing. */
303 DEF_RTL_EXPR(RESX, "resx", "i", RTX_EXTRA)
305 /* ----------------------------------------------------------------------
306 Primitive values for use in expressions.
307 ---------------------------------------------------------------------- */
309 /* numeric integer constant */
310 DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ)
312 /* numeric floating point constant.
313 Operands hold the value. They are all 'w' and there may be from 2 to 6;
315 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ)
317 /* Describes a vector constant. */
318 DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ)
320 /* String constant. Used for attributes in machine descriptions and
321 for special cases in DWARF2 debug output. NOT used for source-
322 language string constants. */
323 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ)
325 /* This is used to encapsulate an expression whose value is constant
326 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
327 recognized as a constant operand rather than by arithmetic instructions. */
329 DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ)
331 /* program counter. Ordinary jumps are represented
332 by a SET whose first operand is (PC). */
333 DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ)
335 /* Used in the cselib routines to describe a value. Objects of this
336 kind are only allocated in cselib.c, in an alloc pool instead of
337 in GC memory. The only operand of a VALUE is a cselib_val_struct. */
338 DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ)
340 /* A register. The "operand" is the register number, accessed with
341 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
342 than a hardware register is being referred to. The second operand
343 holds the original register number - this will be different for a
344 pseudo register that got turned into a hard register. The third
345 operand points to a reg_attrs structure.
346 This rtx needs to have as many (or more) fields as a MEM, since we
347 can change REG rtx's into MEMs during reload. */
348 DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ)
350 /* A scratch register. This represents a register used only within a
351 single insn. It will be turned into a REG during register allocation
352 or reload unless the constraint indicates that the register won't be
353 needed, in which case it can remain a SCRATCH. This code is
354 marked as having one operand so it can be turned into a REG. */
355 DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ)
357 /* One word of a multi-word value.
358 The first operand is the complete value; the second says which word.
359 The WORDS_BIG_ENDIAN flag controls whether word number 0
360 (as numbered in a SUBREG) is the most or least significant word.
362 This is also used to refer to a value in a different machine mode.
363 For example, it can be used to refer to a SImode value as if it were
364 Qimode, or vice versa. Then the word number is always 0. */
365 DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA)
367 /* This one-argument rtx is used for move instructions
368 that are guaranteed to alter only the low part of a destination.
369 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
370 has an unspecified effect on the high part of REG,
371 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
372 is guaranteed to alter only the bits of REG that are in HImode.
374 The actual instruction used is probably the same in both cases,
375 but the register constraints may be tighter when STRICT_LOW_PART
378 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA)
380 /* (CONCAT a b) represents the virtual concatenation of a and b
381 to make a value that has as many bits as a and b put together.
382 This is used for complex values. Normally it appears only
383 in DECL_RTLs and during RTL generation, but not in the insn chain. */
384 DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ)
386 /* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of
387 all An to make a value. This is an extension of CONCAT to larger
388 number of components. Like CONCAT, it should not appear in the
389 insn chain. Every element of the CONCATN is the same size. */
390 DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ)
392 /* A memory location; operand is the address. The second operand is the
393 alias set to which this MEM belongs. We use `0' instead of `w' for this
394 field so that the field need not be specified in machine descriptions. */
395 DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ)
397 /* Reference to an assembler label in the code for this function.
398 The operand is a CODE_LABEL found in the insn chain. */
399 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ)
401 /* Reference to a named label:
402 Operand 0: label name
403 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h)
404 Operand 2: tree from which this symbol is derived, or null.
405 This is either a DECL node, or some kind of constant. */
406 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ)
408 /* The condition code register is represented, in our imagination,
409 as a register holding a value that can be compared to zero.
410 In fact, the machine has already compared them and recorded the
411 results; but instructions that look at the condition code
412 pretend to be looking at the entire value and comparing it. */
413 DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ)
415 /* ----------------------------------------------------------------------
416 Expressions for operators in an rtl pattern
417 ---------------------------------------------------------------------- */
419 /* if_then_else. This is used in representing ordinary
420 conditional jump instructions.
425 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY)
427 /* Comparison, produces a condition code result. */
428 DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH)
431 DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH)
433 /* Operand 0 minus operand 1. */
434 DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH)
436 /* Minus operand 0. */
437 DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY)
439 DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH)
441 /* Operand 0 divided by operand 1. */
442 DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH)
443 /* Remainder of operand 0 divided by operand 1. */
444 DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH)
446 /* Unsigned divide and remainder. */
447 DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH)
448 DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH)
450 /* Bitwise operations. */
451 DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH)
452 DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH)
453 DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH)
454 DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY)
457 0: value to be shifted.
458 1: number of bits. */
459 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */
460 DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */
461 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */
462 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */
463 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */
465 /* Minimum and maximum values of two operands. We need both signed and
466 unsigned forms. (We cannot use MIN for SMIN because it conflicts
467 with a macro of the same name.) The signed variants should be used
468 with floating point. Further, if both operands are zeros, or if either
469 operand is NaN, then it is unspecified which of the two operands is
470 returned as the result. */
472 DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH)
473 DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH)
474 DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH)
475 DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH)
477 /* These unary operations are used to represent incrementation
478 and decrementation as they occur in memory addresses.
479 The amount of increment or decrement are not represented
480 because they can be understood from the machine-mode of the
481 containing MEM. These operations exist in only two cases:
482 1. pushes onto the stack.
483 2. created automatically by the life_analysis pass in flow.c. */
484 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC)
485 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC)
486 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC)
487 DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC)
489 /* These binary operations are used to represent generic address
490 side-effects in memory addresses, except for simple incrementation
491 or decrementation which use the above operations. They are
492 created automatically by the life_analysis pass in flow.c.
493 The first operand is a REG which is used as the address.
494 The second operand is an expression that is assigned to the
495 register, either before (PRE_MODIFY) or after (POST_MODIFY)
496 evaluating the address.
497 Currently, the compiler can only handle second operands of the
498 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
499 the first operand of the PLUS has to be the same register as
500 the first operand of the *_MODIFY. */
501 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC)
502 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC)
504 /* Comparison operations. The ordered comparisons exist in two
505 flavors, signed and unsigned. */
506 DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE)
507 DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE)
508 DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE)
509 DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE)
510 DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE)
511 DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE)
512 DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE)
513 DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE)
514 DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE)
515 DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE)
517 /* Additional floating point unordered comparison flavors. */
518 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE)
519 DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE)
521 /* These are equivalent to unordered or ... */
522 DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE)
523 DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE)
524 DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE)
525 DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE)
526 DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE)
528 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
529 DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE)
531 /* Represents the result of sign-extending the sole operand.
532 The machine modes of the operand and of the SIGN_EXTEND expression
533 determine how much sign-extension is going on. */
534 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY)
536 /* Similar for zero-extension (such as unsigned short to int). */
537 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY)
539 /* Similar but here the operand has a wider mode. */
540 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY)
542 /* Similar for extending floating-point values (such as SFmode to DFmode). */
543 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY)
544 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY)
546 /* Conversion of fixed point operand to floating point value. */
547 DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY)
549 /* With fixed-point machine mode:
550 Conversion of floating point operand to fixed point value.
551 Value is defined only when the operand's value is an integer.
552 With floating-point machine mode (and operand with same mode):
553 Operand is rounded toward zero to produce an integer value
554 represented in floating point. */
555 DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY)
557 /* Conversion of unsigned fixed point operand to floating point value. */
558 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY)
560 /* With fixed-point machine mode:
561 Conversion of floating point operand to *unsigned* fixed point value.
562 Value is defined only when the operand's value is an integer. */
563 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY)
566 DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY)
569 DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY)
572 DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY)
574 /* Find first bit that is set.
575 Value is 1 + number of trailing zeros in the arg.,
577 DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY)
579 /* Count leading zeros. */
580 DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY)
582 /* Count trailing zeros. */
583 DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY)
585 /* Population count (number of 1 bits). */
586 DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY)
588 /* Population parity (number of 1 bits modulo 2). */
589 DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY)
591 /* Reference to a signed bit-field of specified size and position.
592 Operand 0 is the memory unit (usually SImode or QImode) which
593 contains the field's first bit. Operand 1 is the width, in bits.
594 Operand 2 is the number of bits in the memory unit before the
595 first bit of this field.
596 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
597 operand 2 counts from the msb of the memory unit.
598 Otherwise, the first bit is the lsb and operand 2 counts from
599 the lsb of the memory unit.
600 This kind of expression can not appear as an lvalue in RTL. */
601 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS)
603 /* Similar for unsigned bit-field.
604 But note! This kind of expression _can_ appear as an lvalue. */
605 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS)
607 /* For RISC machines. These save memory when splitting insns. */
609 /* HIGH are the high-order bits of a constant expression. */
610 DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ)
612 /* LO_SUM is the sum of a register and the low-order bits
613 of a constant expression. */
614 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ)
616 /* Describes a merge operation between two vector values.
617 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
618 that specifies where the parts of the result are taken from. Set bits
619 indicate operand 0, clear bits indicate operand 1. The parts are defined
620 by the mode of the vectors. */
621 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY)
623 /* Describes an operation that selects parts of a vector.
624 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
625 a CONST_INT for each of the subparts of the result vector, giving the
626 number of the source subpart that should be stored into it. */
627 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH)
629 /* Describes a vector concat operation. Operands 0 and 1 are the source
630 vectors, the result is a vector that is as long as operands 0 and 1
631 combined and is the concatenation of the two source vectors. */
632 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH)
634 /* Describes an operation that converts a small vector into a larger one by
635 duplicating the input values. The output vector mode must have the same
636 submodes as the input vector mode, and the number of output parts must be
637 an integer multiple of the number of input parts. */
638 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY)
640 /* Addition with signed saturation */
641 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH)
643 /* Addition with unsigned saturation */
644 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH)
646 /* Operand 0 minus operand 1, with signed saturation. */
647 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH)
649 /* Negation with signed saturation. */
650 DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY)
652 /* Shift left with signed saturation. */
653 DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH)
655 /* Operand 0 minus operand 1, with unsigned saturation. */
656 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH)
658 /* Signed saturating truncate. */
659 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY)
661 /* Unsigned saturating truncate. */
662 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY)
664 /* Information about the variable and its location. */
665 DEF_RTL_EXPR(VAR_LOCATION, "var_location", "te", RTX_EXTRA)
667 /* All expressions from this point forward appear only in machine
669 #ifdef GENERATOR_FILE
671 /* Include a secondary machine-description file at this point. */
672 DEF_RTL_EXPR(INCLUDE, "include", "s", RTX_EXTRA)
674 /* Pattern-matching operators: */
676 /* Use the function named by the second arg (the string)
677 as a predicate; if matched, store the structure that was matched
678 in the operand table at index specified by the first arg (the integer).
679 If the second arg is the null string, the structure is just stored.
681 A third string argument indicates to the register allocator restrictions
682 on where the operand can be allocated.
684 If the target needs no restriction on any instruction this field should
687 The string is prepended by:
688 '=' to indicate the operand is only written to.
689 '+' to indicate the operand is both read and written to.
691 Each character in the string represents an allocable class for an operand.
692 'g' indicates the operand can be any valid class.
693 'i' indicates the operand can be immediate (in the instruction) data.
694 'r' indicates the operand can be in a register.
695 'm' indicates the operand can be in memory.
696 'o' a subset of the 'm' class. Those memory addressing modes that
697 can be offset at compile time (have a constant added to them).
699 Other characters indicate target dependent operand classes and
700 are described in each target's machine description.
702 For instructions with more than one operand, sets of classes can be
703 separated by a comma to indicate the appropriate multi-operand constraints.
704 There must be a 1 to 1 correspondence between these sets of classes in
705 all operands for an instruction.
707 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH)
709 /* Match a SCRATCH or a register. When used to generate rtl, a
710 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
711 the desired mode and the first argument is the operand number.
712 The second argument is the constraint. */
713 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH)
715 /* Apply a predicate, AND match recursively the operands of the rtx.
716 Operand 0 is the operand-number, as in match_operand.
717 Operand 1 is a predicate to apply (as a string, a function name).
718 Operand 2 is a vector of expressions, each of which must match
719 one subexpression of the rtx this construct is matching. */
720 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH)
722 /* Match a PARALLEL of arbitrary length. The predicate is applied
723 to the PARALLEL and the initial expressions in the PARALLEL are matched.
724 Operand 0 is the operand-number, as in match_operand.
725 Operand 1 is a predicate to apply to the PARALLEL.
726 Operand 2 is a vector of expressions, each of which must match the
727 corresponding element in the PARALLEL. */
728 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH)
730 /* Match only something equal to what is stored in the operand table
731 at the index specified by the argument. Use with MATCH_OPERAND. */
732 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH)
734 /* Match only something equal to what is stored in the operand table
735 at the index specified by the argument. Use with MATCH_OPERATOR. */
736 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH)
738 /* Match only something equal to what is stored in the operand table
739 at the index specified by the argument. Use with MATCH_PARALLEL. */
740 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH)
742 /* Appears only in define_predicate/define_special_predicate
743 expressions. Evaluates true only if the operand has an RTX code
744 from the set given by the argument (a comma-separated list). If the
745 second argument is present and nonempty, it is a sequence of digits
746 and/or letters which indicates the subexpression to test, using the
747 same syntax as genextract/genrecog's location strings: 0-9 for
748 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to
749 the result of the one before it. */
750 DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH)
752 /* Appears only in define_predicate/define_special_predicate
753 expressions. The argument is a C expression to be injected at this
754 point in the predicate formula. */
755 DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH)
757 /* Insn (and related) definitions. */
759 /* Definition of the pattern for one kind of instruction.
761 0: names this instruction.
762 If the name is the null string, the instruction is in the
763 machine description just to be recognized, and will never be emitted by
764 the tree to rtl expander.
766 2: is a string which is a C expression
767 giving an additional condition for recognizing this pattern.
768 A null string means no extra condition.
769 3: is the action to execute if this pattern is matched.
770 If this assembler code template starts with a * then it is a fragment of
771 C code to run to decide on a template to use. Otherwise, it is the
773 4: optionally, a vector of attributes for this insn.
775 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA)
777 /* Definition of a peephole optimization.
778 1st operand: vector of insn patterns to match
779 2nd operand: C expression that must be true
780 3rd operand: template or C code to produce assembler output.
781 4: optionally, a vector of attributes for this insn.
783 This form is deprecated; use define_peephole2 instead. */
784 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA)
786 /* Definition of a split operation.
787 1st operand: insn pattern to match
788 2nd operand: C expression that must be true
789 3rd operand: vector of insn patterns to place into a SEQUENCE
790 4th operand: optionally, some C code to execute before generating the
791 insns. This might, for example, create some RTX's and store them in
792 elements of `recog_data.operand' for use by the vector of
794 (`operands' is an alias here for `recog_data.operand'). */
795 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA)
797 /* Definition of an insn and associated split.
798 This is the concatenation, with a few modifications, of a define_insn
799 and a define_split which share the same pattern.
801 0: names this instruction.
802 If the name is the null string, the instruction is in the
803 machine description just to be recognized, and will never be emitted by
804 the tree to rtl expander.
806 2: is a string which is a C expression
807 giving an additional condition for recognizing this pattern.
808 A null string means no extra condition.
809 3: is the action to execute if this pattern is matched.
810 If this assembler code template starts with a * then it is a fragment of
811 C code to run to decide on a template to use. Otherwise, it is the
813 4: C expression that must be true for split. This may start with "&&"
814 in which case the split condition is the logical and of the insn
815 condition and what follows the "&&" of this operand.
816 5: vector of insn patterns to place into a SEQUENCE
817 6: optionally, some C code to execute before generating the
818 insns. This might, for example, create some RTX's and store them in
819 elements of `recog_data.operand' for use by the vector of
821 (`operands' is an alias here for `recog_data.operand').
822 7: optionally, a vector of attributes for this insn. */
823 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA)
825 /* Definition of an RTL peephole operation.
826 Follows the same arguments as define_split. */
827 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA)
829 /* Define how to generate multiple insns for a standard insn name.
830 1st operand: the insn name.
831 2nd operand: vector of insn-patterns.
832 Use match_operand to substitute an element of `recog_data.operand'.
833 3rd operand: C expression that must be true for this to be available.
834 This may not test any operands.
835 4th operand: Extra C code to execute before generating the insns.
836 This might, for example, create some RTX's and store them in
837 elements of `recog_data.operand' for use by the vector of
839 (`operands' is an alias here for `recog_data.operand'). */
840 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA)
842 /* Define a requirement for delay slots.
843 1st operand: Condition involving insn attributes that, if true,
844 indicates that the insn requires the number of delay slots
846 2nd operand: Vector whose length is the three times the number of delay
848 Each entry gives three conditions, each involving attributes.
849 The first must be true for an insn to occupy that delay slot
850 location. The second is true for all insns that can be
851 annulled if the branch is true and the third is true for all
852 insns that can be annulled if the branch is false.
854 Multiple DEFINE_DELAYs may be present. They indicate differing
855 requirements for delay slots. */
856 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA)
858 /* Define attribute computation for `asm' instructions. */
859 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA)
861 /* Definition of a conditional execution meta operation. Automatically
862 generates new instances of DEFINE_INSN, selected by having attribute
863 "predicable" true. The new pattern will contain a COND_EXEC and the
864 predicate at top-level.
867 0: The predicate pattern. The top-level form should match a
868 relational operator. Operands should have only one alternative.
869 1: A C expression giving an additional condition for recognizing
870 the generated pattern.
871 2: A template or C code to produce assembler output. */
872 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA)
874 /* Definition of an operand predicate. The difference between
875 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will
876 not warn about a match_operand with no mode if it has a predicate
877 defined with DEFINE_SPECIAL_PREDICATE.
880 0: The name of the predicate.
881 1: A boolean expression which computes whether or not the predicate
882 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND,
883 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog
884 can calculate the set of RTX codes that can possibly match.
885 2: A C function body which must return true for the predicate to match.
886 Optional. Use this when the test is too complicated to fit into a
887 match_test expression. */
888 DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA)
889 DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA)
891 /* Definition of a register operand constraint. This simply maps the
892 constraint string to a register class.
895 0: The name of the constraint (often, but not always, a single letter).
896 1: A C expression which evaluates to the appropriate register class for
897 this constraint. If this is not just a constant, it should look only
898 at -m switches and the like.
899 2: A docstring for this constraint, in Texinfo syntax; not currently
900 used, in future will be incorporated into the manual's list of
901 machine-specific operand constraints. */
902 DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA)
904 /* Definition of a non-register operand constraint. These look at the
905 operand and decide whether it fits the constraint.
907 DEFINE_CONSTRAINT gets no special treatment if it fails to match.
908 It is appropriate for constant-only constraints, and most others.
910 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made
911 to match, if it doesn't already, by converting the operand to the form
912 (mem (reg X)) where X is a base register. It is suitable for constraints
913 that describe a subset of all memory references.
915 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made
916 to match, if it doesn't already, by converting the operand to the form
917 (reg X) where X is a base register. It is suitable for constraints that
918 describe a subset of all address references.
920 When in doubt, use plain DEFINE_CONSTRAINT.
923 0: The name of the constraint (often, but not always, a single letter).
924 1: A docstring for this constraint, in Texinfo syntax; not currently
925 used, in future will be incorporated into the manual's list of
926 machine-specific operand constraints.
927 2: A boolean expression which computes whether or not the constraint
928 matches. It should follow the same rules as a define_predicate
929 expression, including the bit about specifying the set of RTX codes
930 that could possibly match. MATCH_TEST subexpressions may make use of
932 `op' - the RTL object defining the operand.
933 `mode' - the mode of `op'.
934 `ival' - INTVAL(op), if op is a CONST_INT.
935 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE.
936 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE.
937 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point
939 Do not use ival/hval/lval/rval if op is not the appropriate kind of
941 DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA)
942 DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA)
943 DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA)
946 /* Constructions for CPU pipeline description described by NDFAs. */
948 /* (define_cpu_unit string [string]) describes cpu functional
949 units (separated by comma).
951 1st operand: Names of cpu functional units.
952 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON).
954 All define_reservations, define_cpu_units, and
955 define_query_cpu_units should have unique names which may not be
957 DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA)
959 /* (define_query_cpu_unit string [string]) describes cpu functional
960 units analogously to define_cpu_unit. The reservation of such
961 units can be queried for automaton state. */
962 DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA)
964 /* (exclusion_set string string) means that each CPU functional unit
965 in the first string can not be reserved simultaneously with any
966 unit whose name is in the second string and vise versa. CPU units
967 in the string are separated by commas. For example, it is useful
968 for description CPU with fully pipelined floating point functional
969 unit which can execute simultaneously only single floating point
970 insns or only double floating point insns. All CPU functional
971 units in a set should belong to the same automaton. */
972 DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA)
974 /* (presence_set string string) means that each CPU functional unit in
975 the first string can not be reserved unless at least one of pattern
976 of units whose names are in the second string is reserved. This is
977 an asymmetric relation. CPU units or unit patterns in the strings
978 are separated by commas. Pattern is one unit name or unit names
979 separated by white-spaces.
981 For example, it is useful for description that slot1 is reserved
982 after slot0 reservation for a VLIW processor. We could describe it
983 by the following construction
985 (presence_set "slot1" "slot0")
987 Or slot1 is reserved only after slot0 and unit b0 reservation. In
988 this case we could write
990 (presence_set "slot1" "slot0 b0")
992 All CPU functional units in a set should belong to the same
994 DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA)
996 /* (final_presence_set string string) is analogous to `presence_set'.
997 The difference between them is when checking is done. When an
998 instruction is issued in given automaton state reflecting all
999 current and planned unit reservations, the automaton state is
1000 changed. The first state is a source state, the second one is a
1001 result state. Checking for `presence_set' is done on the source
1002 state reservation, checking for `final_presence_set' is done on the
1003 result reservation. This construction is useful to describe a
1004 reservation which is actually two subsequent reservations. For
1007 (presence_set "slot1" "slot0")
1009 the following insn will be never issued (because slot1 requires
1010 slot0 which is absent in the source state).
1012 (define_reservation "insn_and_nop" "slot0 + slot1")
1014 but it can be issued if we use analogous `final_presence_set'. */
1015 DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA)
1017 /* (absence_set string string) means that each CPU functional unit in
1018 the first string can be reserved only if each pattern of units
1019 whose names are in the second string is not reserved. This is an
1020 asymmetric relation (actually exclusion set is analogous to this
1021 one but it is symmetric). CPU units or unit patterns in the string
1022 are separated by commas. Pattern is one unit name or unit names
1023 separated by white-spaces.
1025 For example, it is useful for description that slot0 can not be
1026 reserved after slot1 or slot2 reservation for a VLIW processor. We
1027 could describe it by the following construction
1029 (absence_set "slot2" "slot0, slot1")
1031 Or slot2 can not be reserved if slot0 and unit b0 are reserved or
1032 slot1 and unit b1 are reserved . In this case we could write
1034 (absence_set "slot2" "slot0 b0, slot1 b1")
1036 All CPU functional units in a set should to belong the same
1038 DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA)
1040 /* (final_absence_set string string) is analogous to `absence_set' but
1041 checking is done on the result (state) reservation. See comments
1042 for `final_presence_set'. */
1043 DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA)
1045 /* (define_bypass number out_insn_names in_insn_names) names bypass
1046 with given latency (the first number) from insns given by the first
1047 string (see define_insn_reservation) into insns given by the second
1048 string. Insn names in the strings are separated by commas. The
1049 third operand is optional name of function which is additional
1050 guard for the bypass. The function will get the two insns as
1051 parameters. If the function returns zero the bypass will be
1052 ignored for this case. Additional guard is necessary to recognize
1053 complicated bypasses, e.g. when consumer is load address. */
1054 DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA)
1056 /* (define_automaton string) describes names of automata generated and
1057 used for pipeline hazards recognition. The names are separated by
1058 comma. Actually it is possibly to generate the single automaton
1059 but unfortunately it can be very large. If we use more one
1060 automata, the summary size of the automata usually is less than the
1061 single one. The automaton name is used in define_cpu_unit and
1062 define_query_cpu_unit. All automata should have unique names. */
1063 DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA)
1065 /* (automata_option string) describes option for generation of
1066 automata. Currently there are the following options:
1068 o "no-minimization" which makes no minimization of automata. This
1069 is only worth to do when we are debugging the description and
1070 need to look more accurately at reservations of states.
1072 o "time" which means printing additional time statistics about
1073 generation of automata.
1075 o "v" which means generation of file describing the result
1076 automata. The file has suffix `.dfa' and can be used for the
1077 description verification and debugging.
1079 o "w" which means generation of warning instead of error for
1080 non-critical errors.
1082 o "ndfa" which makes nondeterministic finite state automata.
1084 o "progress" which means output of a progress bar showing how many
1085 states were generated so far for automaton being processed. */
1086 DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA)
1088 /* (define_reservation string string) names reservation (the first
1089 string) of cpu functional units (the 2nd string). Sometimes unit
1090 reservations for different insns contain common parts. In such
1091 case, you can describe common part and use its name (the 1st
1092 parameter) in regular expression in define_insn_reservation. All
1093 define_reservations, define_cpu_units, and define_query_cpu_units
1094 should have unique names which may not be "nothing". */
1095 DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA)
1097 /* (define_insn_reservation name default_latency condition regexpr)
1098 describes reservation of cpu functional units (the 3nd operand) for
1099 instruction which is selected by the condition (the 2nd parameter).
1100 The first parameter is used for output of debugging information.
1101 The reservations are described by a regular expression according
1102 the following syntax:
1104 regexp = regexp "," oneof
1107 oneof = oneof "|" allof
1110 allof = allof "+" repeat
1113 repeat = element "*" number
1116 element = cpu_function_unit_name
1122 1. "," is used for describing start of the next cycle in
1125 2. "|" is used for describing the reservation described by the
1126 first regular expression *or* the reservation described by the
1127 second regular expression *or* etc.
1129 3. "+" is used for describing the reservation described by the
1130 first regular expression *and* the reservation described by the
1131 second regular expression *and* etc.
1133 4. "*" is used for convenience and simply means sequence in
1134 which the regular expression are repeated NUMBER times with
1135 cycle advancing (see ",").
1137 5. cpu functional unit name which means its reservation.
1139 6. reservation name -- see define_reservation.
1141 7. string "nothing" means no units reservation. */
1143 DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA)
1145 /* Expressions used for insn attributes. */
1147 /* Definition of an insn attribute.
1148 1st operand: name of the attribute
1149 2nd operand: comma-separated list of possible attribute values
1150 3rd operand: expression for the default value of the attribute. */
1151 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA)
1153 /* Marker for the name of an attribute. */
1154 DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA)
1156 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
1157 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
1160 (set_attr "name" "value") is equivalent to
1161 (set (attr "name") (const_string "value")) */
1162 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA)
1164 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
1165 specify that attribute values are to be assigned according to the
1166 alternative matched.
1168 The following three expressions are equivalent:
1170 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
1171 (eq_attrq "alternative" "2") (const_string "a2")]
1172 (const_string "a3")))
1173 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
1174 (const_string "a3")])
1175 (set_attr "att" "a1,a2,a3")
1177 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA)
1179 /* A conditional expression true if the value of the specified attribute of
1180 the current insn equals the specified value. The first operand is the
1181 attribute name and the second is the comparison value. */
1182 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA)
1184 /* A special case of the above representing a set of alternatives. The first
1185 operand is bitmap of the set, the second one is the default value. */
1186 DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA)
1188 /* A conditional expression which is true if the specified flag is
1189 true for the insn being scheduled in reorg.
1191 genattr.c defines the following flags which can be tested by
1192 (attr_flag "foo") expressions in eligible_for_delay.
1194 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
1196 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA)
1198 /* General conditional. The first operand is a vector composed of pairs of
1199 expressions. The first element of each pair is evaluated, in turn.
1200 The value of the conditional is the second expression of the first pair
1201 whose first expression evaluates nonzero. If none of the expressions is
1202 true, the second operand will be used as the value of the conditional. */
1203 DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA)
1205 #endif /* GENERATOR_FILE */
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