1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
5 Free Software Foundation, Inc.
7 This file is part of GNU CC.
9 GNU CC is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2, or (at your option)
14 GNU CC is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with GNU CC; see the file COPYING. If not, write to
21 the Free Software Foundation, 59 Temple Place - Suite 330,
22 Boston, MA 02111-1307, USA. */
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
50 "<" an rtx code for a comparison (e.g, EQ, NE, LT)
51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
59 "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
64 /* ---------------------------------------------------------------------
65 Expressions (and "meta" expressions) used for structuring the
66 rtl representation of a program.
67 --------------------------------------------------------------------- */
69 /* an expression code name unknown to the reader */
70 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
72 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
74 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
76 /* ---------------------------------------------------------------------
77 Expressions used in constructing lists.
78 --------------------------------------------------------------------- */
80 /* a linked list of expressions */
81 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
83 /* a linked list of instructions.
84 The insns are represented in print by their uids. */
85 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
87 /* ----------------------------------------------------------------------
88 Expression types for machine descriptions.
89 These do not appear in actual rtl code in the compiler.
90 ---------------------------------------------------------------------- */
92 /* Appears only in machine descriptions.
93 Means use the function named by the second arg (the string)
94 as a predicate; if matched, store the structure that was matched
95 in the operand table at index specified by the first arg (the integer).
96 If the second arg is the null string, the structure is just stored.
98 A third string argument indicates to the register allocator restrictions
99 on where the operand can be allocated.
101 If the target needs no restriction on any instruction this field should
104 The string is prepended by:
105 '=' to indicate the operand is only written to.
106 '+' to indicate the operand is both read and written to.
108 Each character in the string represents an allocable class for an operand.
109 'g' indicates the operand can be any valid class.
110 'i' indicates the operand can be immediate (in the instruction) data.
111 'r' indicates the operand can be in a register.
112 'm' indicates the operand can be in memory.
113 'o' a subset of the 'm' class. Those memory addressing modes that
114 can be offset at compile time (have a constant added to them).
116 Other characters indicate target dependent operand classes and
117 are described in each target's machine description.
119 For instructions with more than one operand, sets of classes can be
120 separated by a comma to indicate the appropriate multi-operand constraints.
121 There must be a 1 to 1 correspondence between these sets of classes in
122 all operands for an instruction.
124 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
126 /* Appears only in machine descriptions.
127 Means match a SCRATCH or a register. When used to generate rtl, a
128 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
129 the desired mode and the first argument is the operand number.
130 The second argument is the constraint. */
131 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
133 /* Appears only in machine descriptions.
134 Means match only something equal to what is stored in the operand table
135 at the index specified by the argument. */
136 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
138 /* Appears only in machine descriptions.
139 Means apply a predicate, AND match recursively the operands of the rtx.
140 Operand 0 is the operand-number, as in match_operand.
141 Operand 1 is a predicate to apply (as a string, a function name).
142 Operand 2 is a vector of expressions, each of which must match
143 one subexpression of the rtx this construct is matching. */
144 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
146 /* Appears only in machine descriptions.
147 Means to match a PARALLEL of arbitrary length. The predicate is applied
148 to the PARALLEL and the initial expressions in the PARALLEL are matched.
149 Operand 0 is the operand-number, as in match_operand.
150 Operand 1 is a predicate to apply to the PARALLEL.
151 Operand 2 is a vector of expressions, each of which must match the
152 corresponding element in the PARALLEL. */
153 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
155 /* Appears only in machine descriptions.
156 Means match only something equal to what is stored in the operand table
157 at the index specified by the argument. For MATCH_OPERATOR. */
158 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
160 /* Appears only in machine descriptions.
161 Means match only something equal to what is stored in the operand table
162 at the index specified by the argument. For MATCH_PARALLEL. */
163 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
165 /* Appears only in machine descriptions.
166 Operand 0 is the operand number, as in match_operand.
167 Operand 1 is the predicate to apply to the insn. */
168 DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')
170 /* Appears only in machine descriptions.
171 Defines the pattern for one kind of instruction.
173 0: names this instruction.
174 If the name is the null string, the instruction is in the
175 machine description just to be recognized, and will never be emitted by
176 the tree to rtl expander.
178 2: is a string which is a C expression
179 giving an additional condition for recognizing this pattern.
180 A null string means no extra condition.
181 3: is the action to execute if this pattern is matched.
182 If this assembler code template starts with a * then it is a fragment of
183 C code to run to decide on a template to use. Otherwise, it is the
185 4: optionally, a vector of attributes for this insn.
187 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEssV", 'x')
189 /* Definition of a peephole optimization.
190 1st operand: vector of insn patterns to match
191 2nd operand: C expression that must be true
192 3rd operand: template or C code to produce assembler output.
193 4: optionally, a vector of attributes for this insn.
195 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EssV", 'x')
197 /* Definition of a split operation.
198 1st operand: insn pattern to match
199 2nd operand: C expression that must be true
200 3rd operand: vector of insn patterns to place into a SEQUENCE
201 4th operand: optionally, some C code to execute before generating the
202 insns. This might, for example, create some RTX's and store them in
203 elements of `recog_operand' for use by the vector of insn-patterns.
204 (`operands' is an alias here for `recog_operand'). */
205 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
207 /* Definition of an insn and associated split.
208 This is the concatenation, with a few modifications, of a define_insn
209 and a define_split which share the same pattern.
211 0: names this instruction.
212 If the name is the null string, the instruction is in the
213 machine description just to be recognized, and will never be emitted by
214 the tree to rtl expander.
216 2: is a string which is a C expression
217 giving an additional condition for recognizing this pattern.
218 A null string means no extra condition.
219 3: is the action to execute if this pattern is matched.
220 If this assembler code template starts with a * then it is a fragment of
221 C code to run to decide on a template to use. Otherwise, it is the
223 4: C expression that must be true for split. This may start with "&&"
224 in which case the split condition is the logical and of the insn
225 condition and what follows the "&&" of this operand.
226 5: vector of insn patterns to place into a SEQUENCE
227 6: optionally, some C code to execute before generating the
228 insns. This might, for example, create some RTX's and store them in
229 elements of `recog_operand' for use by the vector of insn-patterns.
230 (`operands' is an alias here for `recog_operand').
231 7: optionally, a vector of attributes for this insn. */
232 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsssESV", 'x')
234 /* Definition of an RTL peephole operation.
235 Follows the same arguments as define_split. */
236 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
238 /* Definition of a combiner pattern.
239 Operands not defined yet. */
240 DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
242 /* Define how to generate multiple insns for a standard insn name.
243 1st operand: the insn name.
244 2nd operand: vector of insn-patterns.
245 Use match_operand to substitute an element of `recog_operand'.
246 3rd operand: C expression that must be true for this to be available.
247 This may not test any operands.
248 4th operand: Extra C code to execute before generating the insns.
249 This might, for example, create some RTX's and store them in
250 elements of `recog_operand' for use by the vector of insn-patterns.
251 (`operands' is an alias here for `recog_operand'). */
252 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
254 /* Define a requirement for delay slots.
255 1st operand: Condition involving insn attributes that, if true,
256 indicates that the insn requires the number of delay slots
258 2nd operand: Vector whose length is the three times the number of delay
260 Each entry gives three conditions, each involving attributes.
261 The first must be true for an insn to occupy that delay slot
262 location. The second is true for all insns that can be
263 annulled if the branch is true and the third is true for all
264 insns that can be annulled if the branch is false.
266 Multiple DEFINE_DELAYs may be present. They indicate differing
267 requirements for delay slots. */
268 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
270 /* Define a set of insns that requires a function unit. This means that
271 these insns produce their result after a delay and that there may be
272 restrictions on the number of insns of this type that can be scheduled
275 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
276 Each gives a set of operations and associated delays. The first three
277 operands must be the same for each operation for the same function unit.
279 All delays are specified in cycles.
281 1st operand: Name of function unit (mostly for documentation)
282 2nd operand: Number of identical function units in CPU
283 3rd operand: Total number of simultaneous insns that can execute on this
284 function unit; 0 if unlimited.
285 4th operand: Condition involving insn attribute, that, if true, specifies
286 those insns that this expression applies to.
287 5th operand: Constant delay after which insn result will be
289 6th operand: Delay until next insn can be scheduled on the function unit
290 executing this operation. The meaning depends on whether or
291 not the next operand is supplied.
292 7th operand: If this operand is not specified, the 6th operand gives the
293 number of cycles after the instruction matching the 4th
294 operand begins using the function unit until a subsequent
295 insn can begin. A value of zero should be used for a
296 unit with no issue constraints. If only one operation can
297 be executed a time and the unit is busy for the entire time,
298 the 3rd operand should be specified as 1, the 6th operand
299 should be specified as 0, and the 7th operand should not
302 If this operand is specified, it is a list of attribute
303 expressions. If an insn for which any of these expressions
304 is true is currently executing on the function unit, the
305 issue delay will be given by the 6th operand. Otherwise,
306 the insn can be immediately scheduled (subject to the limit
307 on the number of simultaneous operations executing on the
309 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
311 /* Define attribute computation for `asm' instructions. */
312 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
314 /* Definition of a conditional execution meta operation. Automatically
315 generates new instances of DEFINE_INSN, selected by having attribute
316 "predicable" true. The new pattern will contain a COND_EXEC and the
317 predicate at top-level.
320 0: The predicate pattern. The top-level form should match a
321 relational operator. Operands should have only one alternative.
322 1: A C expression giving an additional condition for recognizing
323 the generated pattern.
324 2: A template or C code to produce assembler output. */
325 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
327 /* SEQUENCE appears in the result of a `gen_...' function
328 for a DEFINE_EXPAND that wants to make several insns.
329 Its elements are the bodies of the insns that should be made.
330 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
331 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
333 /* Refers to the address of its argument. This is only used in alias.c. */
334 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
336 /* ----------------------------------------------------------------------
337 Expressions used for insn attributes. These also do not appear in
338 actual rtl code in the compiler.
339 ---------------------------------------------------------------------- */
341 /* Definition of an insn attribute.
342 1st operand: name of the attribute
343 2nd operand: comma-separated list of possible attribute values
344 3rd operand: expression for the default value of the attribute. */
345 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
347 /* Marker for the name of an attribute. */
348 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
350 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
351 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
354 (set_attr "name" "value") is equivalent to
355 (set (attr "name") (const_string "value")) */
356 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
358 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
359 specify that attribute values are to be assigned according to the
362 The following three expressions are equivalent:
364 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
365 (eq_attrq "alternative" "2") (const_string "a2")]
366 (const_string "a3")))
367 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
368 (const_string "a3")])
369 (set_attr "att" "a1,a2,a3")
371 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
373 /* A conditional expression true if the value of the specified attribute of
374 the current insn equals the specified value. The first operand is the
375 attribute name and the second is the comparison value. */
376 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
378 /* A conditional expression which is true if the specified flag is
379 true for the insn being scheduled in reorg.
381 genattr.c defines the following flags which can be tested by
382 (attr_flag "foo") expressions in eligible_for_delay.
384 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
386 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
388 /* ----------------------------------------------------------------------
389 Expression types used for things in the instruction chain.
391 All formats must start with "iuu" to handle the chain.
392 Each insn expression holds an rtl instruction and its semantics
393 during back-end processing.
394 See macros's in "rtl.h" for the meaning of each rtx->fld[].
396 ---------------------------------------------------------------------- */
398 /* An instruction that cannot jump. */
399 DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
401 /* An instruction that can possibly jump.
402 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
403 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
405 /* An instruction that can possibly call a subroutine
406 but which will not change which instruction comes next
407 in the current function.
408 Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
409 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
410 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')
412 /* A marker that indicates that control will not flow through. */
413 DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
415 /* Holds a label that is followed by instructions.
417 3: is used in jump.c for the use-count of the label.
418 4: is used in flow.c to point to the chain of label_ref's to this label.
419 5: is a number that is unique in the entire compilation.
420 6: is the user-given name of the label, if any.
421 7: is the alternate label name. */
422 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuu00iss", 'x')
424 /* Say where in the code a source line starts, for symbol table's sake.
426 3: filename, if line number > 0, note-specific data otherwise.
427 4: line number if > 0, enum note_insn otherwise.
428 5: unique number if line number == note_insn_deleted_label. */
429 DEF_RTL_EXPR(NOTE, "note", "iuu0ni", 'x')
431 /* ----------------------------------------------------------------------
432 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
433 ---------------------------------------------------------------------- */
435 /* Conditionally execute code.
436 Operand 0 is the condition that if true, the code is executed.
437 Operand 1 is the code to be executed (typically a SET).
439 Semantics are that there are no side effects if the condition
440 is false. This pattern is created automatically by the if_convert
441 pass run after reload or by target-specific splitters. */
442 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')
444 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
445 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
447 /* A string that is passed through to the assembler as input.
448 One can obviously pass comments through by using the
449 assembler comment syntax.
450 These occur in an insn all by themselves as the PATTERN.
451 They also appear inside an ASM_OPERANDS
452 as a convenient way to hold a string. */
453 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
455 /* An assembler instruction with operands.
456 1st operand is the instruction template.
457 2nd operand is the constraint for the output.
458 3rd operand is the number of the output this expression refers to.
459 When an insn stores more than one value, a separate ASM_OPERANDS
460 is made for each output; this integer distinguishes them.
461 4th is a vector of values of input operands.
462 5th is a vector of modes and constraints for the input operands.
463 Each element is an ASM_INPUT containing a constraint string
464 and whose mode indicates the mode of the input operand.
465 6th is the name of the containing source file.
466 7th is the source line number. */
467 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
469 /* A machine-specific operation.
470 1st operand is a vector of operands being used by the operation so that
471 any needed reloads can be done.
472 2nd operand is a unique value saying which of a number of machine-specific
473 operations is to be performed.
474 (Note that the vector must be the first operand because of the way that
475 genrecog.c record positions within an insn.)
476 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
477 or inside an expression. */
478 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
480 /* Similar, but a volatile operation and one which may trap. */
481 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
483 /* Vector of addresses, stored as full words. */
484 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
485 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
487 /* Vector of address differences X0 - BASE, X1 - BASE, ...
488 First operand is BASE; the vector contains the X's.
489 The machine mode of this rtx says how much space to leave
490 for each difference and is adjusted by branch shortening if
491 CASE_VECTOR_SHORTEN_MODE is defined.
492 The third and fourth operands store the target labels with the
493 minimum and maximum addresses respectively.
494 The fifth operand stores flags for use by branch shortening.
495 Set at the start of shorten_branches:
496 min_align: the minimum alignment for any of the target labels.
497 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
498 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
499 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
500 min_after_base: true iff minimum address target label is after BASE.
501 max_after_base: true iff maximum address target label is after BASE.
502 Set by the actual branch shortening process:
503 offset_unsigned: true iff offsets have to be treated as unsigned.
504 scale: scaling that is necessary to make offsets fit into the mode.
506 The third, fourth and fifth operands are only valid when
507 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
510 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
512 /* ----------------------------------------------------------------------
513 At the top level of an instruction (perhaps under PARALLEL).
514 ---------------------------------------------------------------------- */
517 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
518 Operand 2 is the value stored there.
519 ALL assignment must use SET.
520 Instructions that do multiple assignments must use multiple SET,
522 DEF_RTL_EXPR(SET, "set", "ee", 'x')
524 /* Indicate something is used in a way that we don't want to explain.
525 For example, subroutine calls will use the register
526 in which the static chain is passed. */
527 DEF_RTL_EXPR(USE, "use", "e", 'x')
529 /* Indicate something is clobbered in a way that we don't want to explain.
530 For example, subroutine calls will clobber some physical registers
531 (the ones that are by convention not saved). */
532 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
534 /* Call a subroutine.
535 Operand 1 is the address to call.
536 Operand 2 is the number of arguments. */
538 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
540 /* Return from a subroutine. */
542 DEF_RTL_EXPR(RETURN, "return", "", 'x')
545 Operand 1 is the condition.
546 Operand 2 is the trap code.
547 For an unconditional trap, make the condition (const_int 1). */
548 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
550 /* ----------------------------------------------------------------------
551 Primitive values for use in expressions.
552 ---------------------------------------------------------------------- */
554 /* numeric integer constant */
555 DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
557 /* numeric floating point constant.
558 Operand 0 ('e') is the MEM that stores this constant in memory, or
559 various other things (see comments at immed_double_const in
561 Operand 1 ('0') is a chain of all CONST_DOUBLEs in use in the
563 Remaining operands hold the actual value. They are all 'w' and
564 there may be from 1 to 4; see rtl.c. */
565 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
567 /* String constant. Used only for attributes right now. */
568 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
570 /* This is used to encapsulate an expression whose value is constant
571 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
572 recognized as a constant operand rather than by arithmetic instructions. */
574 DEF_RTL_EXPR(CONST, "const", "e", 'o')
576 /* program counter. Ordinary jumps are represented
577 by a SET whose first operand is (PC). */
578 DEF_RTL_EXPR(PC, "pc", "", 'o')
580 /* Used in the cselib routines to describe a value. */
581 DEF_RTL_EXPR(VALUE, "value", "0", 'o')
583 /* A register. The "operand" is the register number, accessed with
584 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
585 than a hardware register is being referred to. The second operand
586 holds the original register number - this will be different for a
587 pseudo register that got turned into a hard register.
588 This rtx needs to have as many (or more) fields as a MEM, since we
589 can change REG rtx's into MEMs during reload. */
590 DEF_RTL_EXPR(REG, "reg", "i0", 'o')
592 /* A scratch register. This represents a register used only within a
593 single insn. It will be turned into a REG during register allocation
594 or reload unless the constraint indicates that the register won't be
595 needed, in which case it can remain a SCRATCH. This code is
596 marked as having one operand so it can be turned into a REG. */
597 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
599 /* One word of a multi-word value.
600 The first operand is the complete value; the second says which word.
601 The WORDS_BIG_ENDIAN flag controls whether word number 0
602 (as numbered in a SUBREG) is the most or least significant word.
604 This is also used to refer to a value in a different machine mode.
605 For example, it can be used to refer to a SImode value as if it were
606 Qimode, or vice versa. Then the word number is always 0. */
607 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
609 /* This one-argument rtx is used for move instructions
610 that are guaranteed to alter only the low part of a destination.
611 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
612 has an unspecified effect on the high part of REG,
613 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
614 is guaranteed to alter only the bits of REG that are in HImode.
616 The actual instruction used is probably the same in both cases,
617 but the register constraints may be tighter when STRICT_LOW_PART
620 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
622 /* (CONCAT a b) represents the virtual concatenation of a and b
623 to make a value that has as many bits as a and b put together.
624 This is used for complex values. Normally it appears only
625 in DECL_RTLs and during RTL generation, but not in the insn chain. */
626 DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
628 /* A memory location; operand is the address. Can be nested inside a
629 VOLATILE. The second operand is the alias set to which this MEM
630 belongs. We use `0' instead of `w' for this field so that the
631 field need not be specified in machine descriptions. */
632 DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
634 /* Reference to an assembler label in the code for this function.
635 The operand is a CODE_LABEL found in the insn chain.
636 The unprinted fields 1 and 2 are used in flow.c for the
637 LABEL_NEXTREF and CONTAINING_INSN. */
638 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
640 /* Reference to a named label: the string that is the first operand,
641 with `_' added implicitly in front.
642 Exception: if the first character explicitly given is `*',
643 to give it to the assembler, remove the `*' and do not add `_'. */
644 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
646 /* The condition code register is represented, in our imagination,
647 as a register holding a value that can be compared to zero.
648 In fact, the machine has already compared them and recorded the
649 results; but instructions that look at the condition code
650 pretend to be looking at the entire value and comparing it. */
651 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
653 /* Reference to the address of a register. Removed by purge_addressof after
654 CSE has elided as many as possible.
655 1st operand: the register we may need the address of.
656 2nd operand: the original pseudo regno we were generated for.
657 3rd operand: the decl for the object in the register, for
660 DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
662 /* =====================================================================
663 A QUEUED expression really points to a member of the queue of instructions
664 to be output later for postincrement/postdecrement.
665 QUEUED expressions never become part of instructions.
666 When a QUEUED expression would be put into an instruction,
667 instead either the incremented variable or a copy of its previous
671 0. the variable to be incremented (a REG rtx).
672 1. the incrementing instruction, or 0 if it hasn't been output yet.
673 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
674 3. the body to use for the incrementing instruction
675 4. the next QUEUED expression in the queue.
676 ====================================================================== */
678 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
680 /* ----------------------------------------------------------------------
681 Expressions for operators in an rtl pattern
682 ---------------------------------------------------------------------- */
684 /* if_then_else. This is used in representing ordinary
685 conditional jump instructions.
690 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
692 /* General conditional. The first operand is a vector composed of pairs of
693 expressions. The first element of each pair is evaluated, in turn.
694 The value of the conditional is the second expression of the first pair
695 whose first expression evaluates non-zero. If none of the expressions is
696 true, the second operand will be used as the value of the conditional.
698 This should be replaced with use of IF_THEN_ELSE. */
699 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
701 /* Comparison, produces a condition code result. */
702 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
705 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
707 /* Operand 0 minus operand 1. */
708 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
710 /* Minus operand 0. */
711 DEF_RTL_EXPR(NEG, "neg", "e", '1')
713 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
715 /* Operand 0 divided by operand 1. */
716 DEF_RTL_EXPR(DIV, "div", "ee", '2')
717 /* Remainder of operand 0 divided by operand 1. */
718 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
720 /* Unsigned divide and remainder. */
721 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
722 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
724 /* Bitwise operations. */
725 DEF_RTL_EXPR(AND, "and", "ee", 'c')
727 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
729 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
731 DEF_RTL_EXPR(NOT, "not", "e", '1')
734 0: value to be shifted.
735 1: number of bits. */
736 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
737 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
738 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
739 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
740 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */
742 /* Minimum and maximum values of two operands. We need both signed and
743 unsigned forms. (We cannot use MIN for SMIN because it conflicts
744 with a macro of the same name.) */
746 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
747 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
748 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
749 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
751 /* These unary operations are used to represent incrementation
752 and decrementation as they occur in memory addresses.
753 The amount of increment or decrement are not represented
754 because they can be understood from the machine-mode of the
755 containing MEM. These operations exist in only two cases:
756 1. pushes onto the stack.
757 2. created automatically by the life_analysis pass in flow.c. */
758 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
759 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
760 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
761 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')
763 /* These binary operations are used to represent generic address
764 side-effects in memory addresses, except for simple incrementation
765 or decrementation which use the above operations. They are
766 created automatically by the life_analysis pass in flow.c.
767 The first operand is a REG which is used as the address.
768 The second operand is an expression that is assigned to the
769 register, either before (PRE_MODIFY) or after (POST_MODIFY)
770 evaluating the address.
771 Currently, the compiler can only handle second operands of the
772 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
773 the first operand of the PLUS has to be the same register as
774 the first operand of the *_MODIFY. */
775 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
776 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')
778 /* Comparison operations. The ordered comparisons exist in two
779 flavors, signed and unsigned. */
780 DEF_RTL_EXPR(NE, "ne", "ee", '<')
781 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
782 DEF_RTL_EXPR(GE, "ge", "ee", '<')
783 DEF_RTL_EXPR(GT, "gt", "ee", '<')
784 DEF_RTL_EXPR(LE, "le", "ee", '<')
785 DEF_RTL_EXPR(LT, "lt", "ee", '<')
786 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
787 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
788 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
789 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
791 /* Additional floating point unordered comparision flavors. */
792 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
793 DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
795 /* These are equivalent to unordered or ... */
796 DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
797 DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
798 DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
799 DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
800 DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
802 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
803 DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
805 /* Represents the result of sign-extending the sole operand.
806 The machine modes of the operand and of the SIGN_EXTEND expression
807 determine how much sign-extension is going on. */
808 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
810 /* Similar for zero-extension (such as unsigned short to int). */
811 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
813 /* Similar but here the operand has a wider mode. */
814 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
816 /* Similar for extending floating-point values (such as SFmode to DFmode). */
817 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
818 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
820 /* Conversion of fixed point operand to floating point value. */
821 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
823 /* With fixed-point machine mode:
824 Conversion of floating point operand to fixed point value.
825 Value is defined only when the operand's value is an integer.
826 With floating-point machine mode (and operand with same mode):
827 Operand is rounded toward zero to produce an integer value
828 represented in floating point. */
829 DEF_RTL_EXPR(FIX, "fix", "e", '1')
831 /* Conversion of unsigned fixed point operand to floating point value. */
832 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
834 /* With fixed-point machine mode:
835 Conversion of floating point operand to *unsigned* fixed point value.
836 Value is defined only when the operand's value is an integer. */
837 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
840 DEF_RTL_EXPR(ABS, "abs", "e", '1')
843 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
845 /* Find first bit that is set.
846 Value is 1 + number of trailing zeros in the arg.,
848 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
850 /* Reference to a signed bit-field of specified size and position.
851 Operand 0 is the memory unit (usually SImode or QImode) which
852 contains the field's first bit. Operand 1 is the width, in bits.
853 Operand 2 is the number of bits in the memory unit before the
854 first bit of this field.
855 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
856 operand 2 counts from the msb of the memory unit.
857 Otherwise, the first bit is the lsb and operand 2 counts from
858 the lsb of the memory unit. */
859 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
861 /* Similar for unsigned bit-field. */
862 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
864 /* For RISC machines. These save memory when splitting insns. */
866 /* HIGH are the high-order bits of a constant expression. */
867 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
869 /* LO_SUM is the sum of a register and the low-order bits
870 of a constant expression. */
871 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
873 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
874 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
875 the registers that can be substituted within this range. Operand 3 is the
876 number of calls in the range. Operand 4 is the number of insns in the
877 range. Operand 5 is the unique range number for this range. Operand 6 is
878 the basic block # of the start of the live range. Operand 7 is the basic
879 block # of the end of the live range. Operand 8 is the loop depth. Operand
880 9 is a bitmap of the registers live at the start of the range. Operand 10
881 is a bitmap of the registers live at the end of the range. Operand 11 is
882 marker number for the start of the range. Operand 12 is the marker number
883 for the end of the range. */
884 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')
886 /* Registers that can be substituted within the range. Operand 0 is the
887 original pseudo register number. Operand 1 will be filled in with the
888 pseudo register the value is copied for the duration of the range. Operand
889 2 is the number of references within the range to the register. Operand 3
890 is the number of sets or clobbers of the register in the range. Operand 4
891 is the number of deaths the register has. Operand 5 is the copy flags that
892 give the status of whether a copy is needed from the original register to
893 the new register at the beginning of the range, or whether a copy from the
894 new register back to the original at the end of the range. Operand 6 is the
895 live length. Operand 7 is the number of calls that this register is live
896 across. Operand 8 is the symbol node of the variable if the register is a
897 user variable. Operand 9 is the block node that the variable is declared
898 in if the register is a user variable. */
899 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
901 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
902 the different ranges a variable is in where it is copied to a different
903 pseudo register. Operand 1 is the block that the variable is declared in.
904 Operand 2 is the number of distinct ranges. */
905 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')
907 /* Information about the registers that are live at the current point. Operand
908 0 is the live bitmap. Operand 1 is the original block number. */
909 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
911 /* A unary `__builtin_constant_p' expression. These are only emitted
912 during RTL generation, and then only if optimize > 0. They are
913 eliminated by the first CSE pass. */
914 DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
916 /* A placeholder for a CALL_INSN which may be turned into a normal call,
917 a sibling (tail) call or tail recursion.
919 Immediately after RTL generation, this placeholder will be replaced
920 by the insns to perform the call, sibcall or tail recursion.
922 This RTX has 4 operands. The first three are lists of instructions to
923 perform the call as a normal call, sibling call and tail recursion
924 respectively. The latter two lists may be NULL, the first may never
927 The last operand is the tail recursion CODE_LABEL, which may be NULL if no
928 potential tail recursive calls were found.
930 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
931 after we select a call method.
933 This method of tail-call elimination is intended to be replaced by
934 tree-based optimizations once front-end conversions are complete. */
935 DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
937 /* Describes a merge operation between two vector values.
938 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
939 that specifies where the parts of the result are taken from. Set bits
940 indicate operand 0, clear bits indicate operand 1. The parts are defined
941 by the mode of the vectors. */
942 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x')
944 /* Describes an operation that selects parts of a vector.
945 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
946 a CONST_INT for each of the subparts of the result vector, giving the
947 number of the source subpart that should be stored into it. */
948 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x')
950 /* Describes a vector concat operation. Operands 0 and 1 are the source
951 vectors, the result is a vector that is as long as operands 0 and 1
952 combined and is the concatenation of the two source vectors. */
953 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x')
955 /* Describes a vector constant. Each part of the PARALLEL that is operand 0
956 describes a constant for one of the subparts. */
957 DEF_RTL_EXPR(VEC_CONST, "vec_const", "e", 'x')
959 /* Describes an operation that converts a small vector into a larger one by
960 duplicating the input values. The output vector mode must have the same
961 submodes as the input vector mode, and the number of output parts must be
962 an integer multiple of the number of input parts. */
963 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x')
965 /* Addition with signed saturation */
966 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
968 /* Addition with unsigned saturation */
969 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
971 /* Operand 0 minus operand 1, with signed saturation. */
972 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
974 /* Operand 0 minus operand 1, with unsigned saturation. */
975 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
977 /* Signed saturating truncate. */
978 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
980 /* Unsigned saturating truncate. */
981 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
983 /* The SSA phi operator.
985 The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT
986 containing the block number of the predecessor through which control
987 has passed when the register at element 2N is used.
989 Note that PHI may only appear at the beginning of a basic block.
991 ??? There may be multiple PHI insns, but they are all evaluated
992 in parallel. This probably ought to be changed to use a real
993 PARALLEL, as that would be less confusing and more in the spirit
994 of canonical RTL. It is, however, easier to manipulate this way. */
995 DEF_RTL_EXPR(PHI, "phi", "E", 'x')
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