1 /* This file contains the definitions and documentation for the
2 Register Transfer Expressions (rtx's) that make up the
3 Register Transfer Language (rtl) used in the Back End of the GNU compiler.
4 Copyright (C) 1987, 88, 92, 94, 95, 97, 98, 1999, 2000
5 Free Software Foundation, Inc.
7 This file is part of GCC.
9 GCC is free software; you can redistribute it and/or modify it under
10 the terms of the GNU General Public License as published by the Free
11 Software Foundation; either version 2, or (at your option) any later
14 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
15 WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
19 You should have received a copy of the GNU General Public License
20 along with GCC; see the file COPYING. If not, write to the Free
21 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
25 /* Expression definitions and descriptions for all targets are in this file.
26 Some will not be used for some targets.
28 The fields in the cpp macro call "DEF_RTL_EXPR()"
29 are used to create declarations in the C source of the compiler.
33 1. The internal name of the rtx used in the C source.
34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h".
35 By convention these are in UPPER_CASE.
37 2. The name of the rtx in the external ASCII format read by
38 read_rtx(), and printed by print_rtx().
39 These names are stored in rtx_name[].
40 By convention these are the internal (field 1) names in lower_case.
42 3. The print format, and type of each rtx->fld[] (field) in this rtx.
43 These formats are stored in rtx_format[].
44 The meaning of the formats is documented in front of this array in rtl.c
46 4. The class of the rtx. These are stored in rtx_class and are accessed
47 via the GET_RTX_CLASS macro. They are defined as follows:
49 "o" an rtx code that can be used to represent an object (e.g, REG, MEM)
50 "<" an rtx code for a comparison (e.g, EQ, NE, LT)
51 "1" an rtx code for a unary arithmetic expression (e.g, NEG, NOT)
52 "c" an rtx code for a commutative binary operation (e.g,, PLUS, MULT)
53 "3" an rtx code for a non-bitfield three input operation (IF_THEN_ELSE)
54 "2" an rtx code for a non-commutative binary operation (e.g., MINUS, DIV)
55 "b" an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT)
56 "i" an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN)
57 "m" an rtx code for something that matches in insns (e.g, MATCH_DUP)
58 "g" an rtx code for grouping insns together (e.g, GROUP_PARALLEL)
59 "a" an rtx code for autoincrement addressing modes (e.g. POST_DEC)
64 /* ---------------------------------------------------------------------
65 Expressions (and "meta" expressions) used for structuring the
66 rtl representation of a program.
67 --------------------------------------------------------------------- */
69 /* an expression code name unknown to the reader */
70 DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", 'x')
72 /* (NIL) is used by rtl reader and printer to represent a null pointer. */
74 DEF_RTL_EXPR(NIL, "nil", "*", 'x')
79 DEF_RTL_EXPR(INCLUDE, "include", "s", 'x')
81 /* ---------------------------------------------------------------------
82 Expressions used in constructing lists.
83 --------------------------------------------------------------------- */
85 /* a linked list of expressions */
86 DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", 'x')
88 /* a linked list of instructions.
89 The insns are represented in print by their uids. */
90 DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", 'x')
92 /* ----------------------------------------------------------------------
93 Expression types for machine descriptions.
94 These do not appear in actual rtl code in the compiler.
95 ---------------------------------------------------------------------- */
97 /* Appears only in machine descriptions.
98 Means use the function named by the second arg (the string)
99 as a predicate; if matched, store the structure that was matched
100 in the operand table at index specified by the first arg (the integer).
101 If the second arg is the null string, the structure is just stored.
103 A third string argument indicates to the register allocator restrictions
104 on where the operand can be allocated.
106 If the target needs no restriction on any instruction this field should
109 The string is prepended by:
110 '=' to indicate the operand is only written to.
111 '+' to indicate the operand is both read and written to.
113 Each character in the string represents an allocable class for an operand.
114 'g' indicates the operand can be any valid class.
115 'i' indicates the operand can be immediate (in the instruction) data.
116 'r' indicates the operand can be in a register.
117 'm' indicates the operand can be in memory.
118 'o' a subset of the 'm' class. Those memory addressing modes that
119 can be offset at compile time (have a constant added to them).
121 Other characters indicate target dependent operand classes and
122 are described in each target's machine description.
124 For instructions with more than one operand, sets of classes can be
125 separated by a comma to indicate the appropriate multi-operand constraints.
126 There must be a 1 to 1 correspondence between these sets of classes in
127 all operands for an instruction.
129 DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", 'm')
131 /* Appears only in machine descriptions.
132 Means match a SCRATCH or a register. When used to generate rtl, a
133 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies
134 the desired mode and the first argument is the operand number.
135 The second argument is the constraint. */
136 DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", 'm')
138 /* Appears only in machine descriptions.
139 Means match only something equal to what is stored in the operand table
140 at the index specified by the argument. */
141 DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", 'm')
143 /* Appears only in machine descriptions.
144 Means apply a predicate, AND match recursively the operands of the rtx.
145 Operand 0 is the operand-number, as in match_operand.
146 Operand 1 is a predicate to apply (as a string, a function name).
147 Operand 2 is a vector of expressions, each of which must match
148 one subexpression of the rtx this construct is matching. */
149 DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", 'm')
151 /* Appears only in machine descriptions.
152 Means to match a PARALLEL of arbitrary length. The predicate is applied
153 to the PARALLEL and the initial expressions in the PARALLEL are matched.
154 Operand 0 is the operand-number, as in match_operand.
155 Operand 1 is a predicate to apply to the PARALLEL.
156 Operand 2 is a vector of expressions, each of which must match the
157 corresponding element in the PARALLEL. */
158 DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", 'm')
160 /* Appears only in machine descriptions.
161 Means match only something equal to what is stored in the operand table
162 at the index specified by the argument. For MATCH_OPERATOR. */
163 DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", 'm')
165 /* Appears only in machine descriptions.
166 Means match only something equal to what is stored in the operand table
167 at the index specified by the argument. For MATCH_PARALLEL. */
168 DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", 'm')
170 /* Appears only in machine descriptions.
171 Operand 0 is the operand number, as in match_operand.
172 Operand 1 is the predicate to apply to the insn. */
173 DEF_RTL_EXPR(MATCH_INSN, "match_insn", "is", 'm')
175 /* Appears only in machine descriptions.
176 Defines the pattern for one kind of instruction.
178 0: names this instruction.
179 If the name is the null string, the instruction is in the
180 machine description just to be recognized, and will never be emitted by
181 the tree to rtl expander.
183 2: is a string which is a C expression
184 giving an additional condition for recognizing this pattern.
185 A null string means no extra condition.
186 3: is the action to execute if this pattern is matched.
187 If this assembler code template starts with a * then it is a fragment of
188 C code to run to decide on a template to use. Otherwise, it is the
190 4: optionally, a vector of attributes for this insn.
192 DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", 'x')
194 /* Definition of a peephole optimization.
195 1st operand: vector of insn patterns to match
196 2nd operand: C expression that must be true
197 3rd operand: template or C code to produce assembler output.
198 4: optionally, a vector of attributes for this insn.
200 DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", 'x')
202 /* Definition of a split operation.
203 1st operand: insn pattern to match
204 2nd operand: C expression that must be true
205 3rd operand: vector of insn patterns to place into a SEQUENCE
206 4th operand: optionally, some C code to execute before generating the
207 insns. This might, for example, create some RTX's and store them in
208 elements of `recog_operand' for use by the vector of insn-patterns.
209 (`operands' is an alias here for `recog_operand'). */
210 DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", 'x')
212 /* Definition of an insn and associated split.
213 This is the concatenation, with a few modifications, of a define_insn
214 and a define_split which share the same pattern.
216 0: names this instruction.
217 If the name is the null string, the instruction is in the
218 machine description just to be recognized, and will never be emitted by
219 the tree to rtl expander.
221 2: is a string which is a C expression
222 giving an additional condition for recognizing this pattern.
223 A null string means no extra condition.
224 3: is the action to execute if this pattern is matched.
225 If this assembler code template starts with a * then it is a fragment of
226 C code to run to decide on a template to use. Otherwise, it is the
228 4: C expression that must be true for split. This may start with "&&"
229 in which case the split condition is the logical and of the insn
230 condition and what follows the "&&" of this operand.
231 5: vector of insn patterns to place into a SEQUENCE
232 6: optionally, some C code to execute before generating the
233 insns. This might, for example, create some RTX's and store them in
234 elements of `recog_operand' for use by the vector of insn-patterns.
235 (`operands' is an alias here for `recog_operand').
236 7: optionally, a vector of attributes for this insn. */
237 DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", 'x')
239 /* Definition of an RTL peephole operation.
240 Follows the same arguments as define_split. */
241 DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", 'x')
243 /* Definition of a combiner pattern.
244 Operands not defined yet. */
245 DEF_RTL_EXPR(DEFINE_COMBINE, "define_combine", "Ess", 'x')
247 /* Define how to generate multiple insns for a standard insn name.
248 1st operand: the insn name.
249 2nd operand: vector of insn-patterns.
250 Use match_operand to substitute an element of `recog_operand'.
251 3rd operand: C expression that must be true for this to be available.
252 This may not test any operands.
253 4th operand: Extra C code to execute before generating the insns.
254 This might, for example, create some RTX's and store them in
255 elements of `recog_operand' for use by the vector of insn-patterns.
256 (`operands' is an alias here for `recog_operand'). */
257 DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", 'x')
259 /* Define a requirement for delay slots.
260 1st operand: Condition involving insn attributes that, if true,
261 indicates that the insn requires the number of delay slots
263 2nd operand: Vector whose length is the three times the number of delay
265 Each entry gives three conditions, each involving attributes.
266 The first must be true for an insn to occupy that delay slot
267 location. The second is true for all insns that can be
268 annulled if the branch is true and the third is true for all
269 insns that can be annulled if the branch is false.
271 Multiple DEFINE_DELAYs may be present. They indicate differing
272 requirements for delay slots. */
273 DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", 'x')
275 /* Define a set of insns that requires a function unit. This means that
276 these insns produce their result after a delay and that there may be
277 restrictions on the number of insns of this type that can be scheduled
280 More than one DEFINE_FUNCTION_UNIT can be specified for a function unit.
281 Each gives a set of operations and associated delays. The first three
282 operands must be the same for each operation for the same function unit.
284 All delays are specified in cycles.
286 1st operand: Name of function unit (mostly for documentation)
287 2nd operand: Number of identical function units in CPU
288 3rd operand: Total number of simultaneous insns that can execute on this
289 function unit; 0 if unlimited.
290 4th operand: Condition involving insn attribute, that, if true, specifies
291 those insns that this expression applies to.
292 5th operand: Constant delay after which insn result will be
294 6th operand: Delay until next insn can be scheduled on the function unit
295 executing this operation. The meaning depends on whether or
296 not the next operand is supplied.
297 7th operand: If this operand is not specified, the 6th operand gives the
298 number of cycles after the instruction matching the 4th
299 operand begins using the function unit until a subsequent
300 insn can begin. A value of zero should be used for a
301 unit with no issue constraints. If only one operation can
302 be executed a time and the unit is busy for the entire time,
303 the 3rd operand should be specified as 1, the 6th operand
304 should be specified as 0, and the 7th operand should not
307 If this operand is specified, it is a list of attribute
308 expressions. If an insn for which any of these expressions
309 is true is currently executing on the function unit, the
310 issue delay will be given by the 6th operand. Otherwise,
311 the insn can be immediately scheduled (subject to the limit
312 on the number of simultaneous operations executing on the
314 DEF_RTL_EXPR(DEFINE_FUNCTION_UNIT, "define_function_unit", "siieiiV", 'x')
316 /* Define attribute computation for `asm' instructions. */
317 DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", 'x' )
319 /* Definition of a conditional execution meta operation. Automatically
320 generates new instances of DEFINE_INSN, selected by having attribute
321 "predicable" true. The new pattern will contain a COND_EXEC and the
322 predicate at top-level.
325 0: The predicate pattern. The top-level form should match a
326 relational operator. Operands should have only one alternative.
327 1: A C expression giving an additional condition for recognizing
328 the generated pattern.
329 2: A template or C code to produce assembler output. */
330 DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", 'x')
332 /* SEQUENCE appears in the result of a `gen_...' function
333 for a DEFINE_EXPAND that wants to make several insns.
334 Its elements are the bodies of the insns that should be made.
335 `emit_insn' takes the SEQUENCE apart and makes separate insns. */
336 DEF_RTL_EXPR(SEQUENCE, "sequence", "E", 'x')
338 /* Refers to the address of its argument. This is only used in alias.c. */
339 DEF_RTL_EXPR(ADDRESS, "address", "e", 'm')
341 /* ----------------------------------------------------------------------
342 Expressions used for insn attributes. These also do not appear in
343 actual rtl code in the compiler.
344 ---------------------------------------------------------------------- */
346 /* Definition of an insn attribute.
347 1st operand: name of the attribute
348 2nd operand: comma-separated list of possible attribute values
349 3rd operand: expression for the default value of the attribute. */
350 DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", 'x')
352 /* Marker for the name of an attribute. */
353 DEF_RTL_EXPR(ATTR, "attr", "s", 'x')
355 /* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and
356 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that
359 (set_attr "name" "value") is equivalent to
360 (set (attr "name") (const_string "value")) */
361 DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", 'x')
363 /* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to
364 specify that attribute values are to be assigned according to the
367 The following three expressions are equivalent:
369 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1")
370 (eq_attrq "alternative" "2") (const_string "a2")]
371 (const_string "a3")))
372 (set_attr_alternative "att" [(const_string "a1") (const_string "a2")
373 (const_string "a3")])
374 (set_attr "att" "a1,a2,a3")
376 DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", 'x')
378 /* A conditional expression true if the value of the specified attribute of
379 the current insn equals the specified value. The first operand is the
380 attribute name and the second is the comparison value. */
381 DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", 'x')
383 /* A conditional expression which is true if the specified flag is
384 true for the insn being scheduled in reorg.
386 genattr.c defines the following flags which can be tested by
387 (attr_flag "foo") expressions in eligible_for_delay.
389 forward, backward, very_likely, likely, very_unlikely, and unlikely. */
391 DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", 'x')
393 /* ----------------------------------------------------------------------
394 Expression types used for things in the instruction chain.
396 All formats must start with "iuu" to handle the chain.
397 Each insn expression holds an rtl instruction and its semantics
398 during back-end processing.
399 See macros's in "rtl.h" for the meaning of each rtx->fld[].
401 ---------------------------------------------------------------------- */
403 /* An instruction that cannot jump. */
404 DEF_RTL_EXPR(INSN, "insn", "iuueiee", 'i')
406 /* An instruction that can possibly jump.
407 Fields ( rtx->fld[] ) have exact same meaning as INSN's. */
408 DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuueiee0", 'i')
410 /* An instruction that can possibly call a subroutine
411 but which will not change which instruction comes next
412 in the current function.
413 Field ( rtx->fld[7] ) is CALL_INSN_FUNCTION_USAGE.
414 All other fields ( rtx->fld[] ) have exact same meaning as INSN's. */
415 DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuueieee", 'i')
417 /* A marker that indicates that control will not flow through. */
418 DEF_RTL_EXPR(BARRIER, "barrier", "iuu", 'x')
420 /* Holds a label that is followed by instructions.
422 3: is used in jump.c for the use-count of the label.
423 4: is used in flow.c to point to the chain of label_ref's to this label.
424 5: is a number that is unique in the entire compilation.
425 6: is the user-given name of the label, if any.
426 7: is the alternate label name. */
427 DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuu00iss", 'x')
429 /* Say where in the code a source line starts, for symbol table's sake.
431 3: filename, if line number > 0, note-specific data otherwise.
432 4: line number if > 0, enum note_insn otherwise.
433 5: unique number if line number == note_insn_deleted_label. */
434 DEF_RTL_EXPR(NOTE, "note", "iuu0ni", 'x')
436 /* ----------------------------------------------------------------------
437 Top level constituents of INSN, JUMP_INSN and CALL_INSN.
438 ---------------------------------------------------------------------- */
440 /* Conditionally execute code.
441 Operand 0 is the condition that if true, the code is executed.
442 Operand 1 is the code to be executed (typically a SET).
444 Semantics are that there are no side effects if the condition
445 is false. This pattern is created automatically by the if_convert
446 pass run after reload or by target-specific splitters. */
447 DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", 'x')
449 /* Several operations to be done in parallel (perhaps under COND_EXEC). */
450 DEF_RTL_EXPR(PARALLEL, "parallel", "E", 'x')
452 /* A string that is passed through to the assembler as input.
453 One can obviously pass comments through by using the
454 assembler comment syntax.
455 These occur in an insn all by themselves as the PATTERN.
456 They also appear inside an ASM_OPERANDS
457 as a convenient way to hold a string. */
458 DEF_RTL_EXPR(ASM_INPUT, "asm_input", "s", 'x')
460 /* An assembler instruction with operands.
461 1st operand is the instruction template.
462 2nd operand is the constraint for the output.
463 3rd operand is the number of the output this expression refers to.
464 When an insn stores more than one value, a separate ASM_OPERANDS
465 is made for each output; this integer distinguishes them.
466 4th is a vector of values of input operands.
467 5th is a vector of modes and constraints for the input operands.
468 Each element is an ASM_INPUT containing a constraint string
469 and whose mode indicates the mode of the input operand.
470 6th is the name of the containing source file.
471 7th is the source line number. */
472 DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEsi", 'x')
474 /* A machine-specific operation.
475 1st operand is a vector of operands being used by the operation so that
476 any needed reloads can be done.
477 2nd operand is a unique value saying which of a number of machine-specific
478 operations is to be performed.
479 (Note that the vector must be the first operand because of the way that
480 genrecog.c record positions within an insn.)
481 This can occur all by itself in a PATTERN, as a component of a PARALLEL,
482 or inside an expression. */
483 DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", 'x')
485 /* Similar, but a volatile operation and one which may trap. */
486 DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", 'x')
488 /* Vector of addresses, stored as full words. */
489 /* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */
490 DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", 'x')
492 /* Vector of address differences X0 - BASE, X1 - BASE, ...
493 First operand is BASE; the vector contains the X's.
494 The machine mode of this rtx says how much space to leave
495 for each difference and is adjusted by branch shortening if
496 CASE_VECTOR_SHORTEN_MODE is defined.
497 The third and fourth operands store the target labels with the
498 minimum and maximum addresses respectively.
499 The fifth operand stores flags for use by branch shortening.
500 Set at the start of shorten_branches:
501 min_align: the minimum alignment for any of the target labels.
502 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC.
503 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC.
504 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC.
505 min_after_base: true iff minimum address target label is after BASE.
506 max_after_base: true iff maximum address target label is after BASE.
507 Set by the actual branch shortening process:
508 offset_unsigned: true iff offsets have to be treated as unsigned.
509 scale: scaling that is necessary to make offsets fit into the mode.
511 The third, fourth and fifth operands are only valid when
512 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing
515 DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", 'x')
517 /* ----------------------------------------------------------------------
518 At the top level of an instruction (perhaps under PARALLEL).
519 ---------------------------------------------------------------------- */
522 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to.
523 Operand 2 is the value stored there.
524 ALL assignment must use SET.
525 Instructions that do multiple assignments must use multiple SET,
527 DEF_RTL_EXPR(SET, "set", "ee", 'x')
529 /* Indicate something is used in a way that we don't want to explain.
530 For example, subroutine calls will use the register
531 in which the static chain is passed. */
532 DEF_RTL_EXPR(USE, "use", "e", 'x')
534 /* Indicate something is clobbered in a way that we don't want to explain.
535 For example, subroutine calls will clobber some physical registers
536 (the ones that are by convention not saved). */
537 DEF_RTL_EXPR(CLOBBER, "clobber", "e", 'x')
539 /* Call a subroutine.
540 Operand 1 is the address to call.
541 Operand 2 is the number of arguments. */
543 DEF_RTL_EXPR(CALL, "call", "ee", 'x')
545 /* Return from a subroutine. */
547 DEF_RTL_EXPR(RETURN, "return", "", 'x')
550 Operand 1 is the condition.
551 Operand 2 is the trap code.
552 For an unconditional trap, make the condition (const_int 1). */
553 DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", 'x')
555 /* Placeholder for _Unwind_Resume before we know if a function call
556 or a branch is needed. Operand 1 is the exception region from
557 which control is flowing. */
558 DEF_RTL_EXPR(RESX, "resx", "i", 'x')
560 /* ----------------------------------------------------------------------
561 Primitive values for use in expressions.
562 ---------------------------------------------------------------------- */
564 /* numeric integer constant */
565 DEF_RTL_EXPR(CONST_INT, "const_int", "w", 'o')
567 /* numeric floating point constant.
568 Operand 0 ('0') is a chain of all CONST_DOUBLEs in use in the
570 Remaining operands hold the actual value. They are all 'w' and
571 there may be from 1 to 4; see rtl.c. */
572 DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, 'o')
574 /* String constant. Used only for attributes right now. */
575 DEF_RTL_EXPR(CONST_STRING, "const_string", "s", 'o')
577 /* This is used to encapsulate an expression whose value is constant
578 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be
579 recognized as a constant operand rather than by arithmetic instructions. */
581 DEF_RTL_EXPR(CONST, "const", "e", 'o')
583 /* program counter. Ordinary jumps are represented
584 by a SET whose first operand is (PC). */
585 DEF_RTL_EXPR(PC, "pc", "", 'o')
587 /* Used in the cselib routines to describe a value. */
588 DEF_RTL_EXPR(VALUE, "value", "0", 'o')
590 /* A register. The "operand" is the register number, accessed with
591 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER
592 than a hardware register is being referred to. The second operand
593 holds the original register number - this will be different for a
594 pseudo register that got turned into a hard register.
595 This rtx needs to have as many (or more) fields as a MEM, since we
596 can change REG rtx's into MEMs during reload. */
597 DEF_RTL_EXPR(REG, "reg", "i0", 'o')
599 /* A scratch register. This represents a register used only within a
600 single insn. It will be turned into a REG during register allocation
601 or reload unless the constraint indicates that the register won't be
602 needed, in which case it can remain a SCRATCH. This code is
603 marked as having one operand so it can be turned into a REG. */
604 DEF_RTL_EXPR(SCRATCH, "scratch", "0", 'o')
606 /* One word of a multi-word value.
607 The first operand is the complete value; the second says which word.
608 The WORDS_BIG_ENDIAN flag controls whether word number 0
609 (as numbered in a SUBREG) is the most or least significant word.
611 This is also used to refer to a value in a different machine mode.
612 For example, it can be used to refer to a SImode value as if it were
613 Qimode, or vice versa. Then the word number is always 0. */
614 DEF_RTL_EXPR(SUBREG, "subreg", "ei", 'x')
616 /* This one-argument rtx is used for move instructions
617 that are guaranteed to alter only the low part of a destination.
618 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...))
619 has an unspecified effect on the high part of REG,
620 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...))
621 is guaranteed to alter only the bits of REG that are in HImode.
623 The actual instruction used is probably the same in both cases,
624 but the register constraints may be tighter when STRICT_LOW_PART
627 DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", 'x')
629 /* (CONCAT a b) represents the virtual concatenation of a and b
630 to make a value that has as many bits as a and b put together.
631 This is used for complex values. Normally it appears only
632 in DECL_RTLs and during RTL generation, but not in the insn chain. */
633 DEF_RTL_EXPR(CONCAT, "concat", "ee", 'o')
635 /* A memory location; operand is the address. The second operand is the
636 alias set to which this MEM belongs. We use `0' instead of `w' for this
637 field so that the field need not be specified in machine descriptions. */
638 DEF_RTL_EXPR(MEM, "mem", "e0", 'o')
640 /* Reference to an assembler label in the code for this function.
641 The operand is a CODE_LABEL found in the insn chain.
642 The unprinted fields 1 and 2 are used in flow.c for the
643 LABEL_NEXTREF and CONTAINING_INSN. */
644 DEF_RTL_EXPR(LABEL_REF, "label_ref", "u00", 'o')
646 /* Reference to a named label: the string that is the first operand,
647 with `_' added implicitly in front.
648 Exception: if the first character explicitly given is `*',
649 to give it to the assembler, remove the `*' and do not add `_'. */
650 DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s", 'o')
652 /* The condition code register is represented, in our imagination,
653 as a register holding a value that can be compared to zero.
654 In fact, the machine has already compared them and recorded the
655 results; but instructions that look at the condition code
656 pretend to be looking at the entire value and comparing it. */
657 DEF_RTL_EXPR(CC0, "cc0", "", 'o')
659 /* Reference to the address of a register. Removed by purge_addressof after
660 CSE has elided as many as possible.
661 1st operand: the register we may need the address of.
662 2nd operand: the original pseudo regno we were generated for.
663 3rd operand: the decl for the object in the register, for
666 DEF_RTL_EXPR(ADDRESSOF, "addressof", "eit", 'o')
668 /* =====================================================================
669 A QUEUED expression really points to a member of the queue of instructions
670 to be output later for postincrement/postdecrement.
671 QUEUED expressions never become part of instructions.
672 When a QUEUED expression would be put into an instruction,
673 instead either the incremented variable or a copy of its previous
677 0. the variable to be incremented (a REG rtx).
678 1. the incrementing instruction, or 0 if it hasn't been output yet.
679 2. A REG rtx for a copy of the old value of the variable, or 0 if none yet.
680 3. the body to use for the incrementing instruction
681 4. the next QUEUED expression in the queue.
682 ====================================================================== */
684 DEF_RTL_EXPR(QUEUED, "queued", "eeeee", 'x')
686 /* ----------------------------------------------------------------------
687 Expressions for operators in an rtl pattern
688 ---------------------------------------------------------------------- */
690 /* if_then_else. This is used in representing ordinary
691 conditional jump instructions.
696 DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", '3')
698 /* General conditional. The first operand is a vector composed of pairs of
699 expressions. The first element of each pair is evaluated, in turn.
700 The value of the conditional is the second expression of the first pair
701 whose first expression evaluates non-zero. If none of the expressions is
702 true, the second operand will be used as the value of the conditional.
704 This should be replaced with use of IF_THEN_ELSE. */
705 DEF_RTL_EXPR(COND, "cond", "Ee", 'x')
707 /* Comparison, produces a condition code result. */
708 DEF_RTL_EXPR(COMPARE, "compare", "ee", '2')
711 DEF_RTL_EXPR(PLUS, "plus", "ee", 'c')
713 /* Operand 0 minus operand 1. */
714 DEF_RTL_EXPR(MINUS, "minus", "ee", '2')
716 /* Minus operand 0. */
717 DEF_RTL_EXPR(NEG, "neg", "e", '1')
719 DEF_RTL_EXPR(MULT, "mult", "ee", 'c')
721 /* Operand 0 divided by operand 1. */
722 DEF_RTL_EXPR(DIV, "div", "ee", '2')
723 /* Remainder of operand 0 divided by operand 1. */
724 DEF_RTL_EXPR(MOD, "mod", "ee", '2')
726 /* Unsigned divide and remainder. */
727 DEF_RTL_EXPR(UDIV, "udiv", "ee", '2')
728 DEF_RTL_EXPR(UMOD, "umod", "ee", '2')
730 /* Bitwise operations. */
731 DEF_RTL_EXPR(AND, "and", "ee", 'c')
733 DEF_RTL_EXPR(IOR, "ior", "ee", 'c')
735 DEF_RTL_EXPR(XOR, "xor", "ee", 'c')
737 DEF_RTL_EXPR(NOT, "not", "e", '1')
740 0: value to be shifted.
741 1: number of bits. */
742 DEF_RTL_EXPR(ASHIFT, "ashift", "ee", '2') /* shift left */
743 DEF_RTL_EXPR(ROTATE, "rotate", "ee", '2') /* rotate left */
744 DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", '2') /* arithmetic shift right */
745 DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", '2') /* logical shift right */
746 DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", '2') /* rotate right */
748 /* Minimum and maximum values of two operands. We need both signed and
749 unsigned forms. (We cannot use MIN for SMIN because it conflicts
750 with a macro of the same name.) */
752 DEF_RTL_EXPR(SMIN, "smin", "ee", 'c')
753 DEF_RTL_EXPR(SMAX, "smax", "ee", 'c')
754 DEF_RTL_EXPR(UMIN, "umin", "ee", 'c')
755 DEF_RTL_EXPR(UMAX, "umax", "ee", 'c')
757 /* These unary operations are used to represent incrementation
758 and decrementation as they occur in memory addresses.
759 The amount of increment or decrement are not represented
760 because they can be understood from the machine-mode of the
761 containing MEM. These operations exist in only two cases:
762 1. pushes onto the stack.
763 2. created automatically by the life_analysis pass in flow.c. */
764 DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", 'a')
765 DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", 'a')
766 DEF_RTL_EXPR(POST_DEC, "post_dec", "e", 'a')
767 DEF_RTL_EXPR(POST_INC, "post_inc", "e", 'a')
769 /* These binary operations are used to represent generic address
770 side-effects in memory addresses, except for simple incrementation
771 or decrementation which use the above operations. They are
772 created automatically by the life_analysis pass in flow.c.
773 The first operand is a REG which is used as the address.
774 The second operand is an expression that is assigned to the
775 register, either before (PRE_MODIFY) or after (POST_MODIFY)
776 evaluating the address.
777 Currently, the compiler can only handle second operands of the
778 form (plus (reg) (reg)) and (plus (reg) (const_int)), where
779 the first operand of the PLUS has to be the same register as
780 the first operand of the *_MODIFY. */
781 DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", 'a')
782 DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", 'a')
784 /* Comparison operations. The ordered comparisons exist in two
785 flavors, signed and unsigned. */
786 DEF_RTL_EXPR(NE, "ne", "ee", '<')
787 DEF_RTL_EXPR(EQ, "eq", "ee", '<')
788 DEF_RTL_EXPR(GE, "ge", "ee", '<')
789 DEF_RTL_EXPR(GT, "gt", "ee", '<')
790 DEF_RTL_EXPR(LE, "le", "ee", '<')
791 DEF_RTL_EXPR(LT, "lt", "ee", '<')
792 DEF_RTL_EXPR(GEU, "geu", "ee", '<')
793 DEF_RTL_EXPR(GTU, "gtu", "ee", '<')
794 DEF_RTL_EXPR(LEU, "leu", "ee", '<')
795 DEF_RTL_EXPR(LTU, "ltu", "ee", '<')
797 /* Additional floating point unordered comparision flavors. */
798 DEF_RTL_EXPR(UNORDERED, "unordered", "ee", '<')
799 DEF_RTL_EXPR(ORDERED, "ordered", "ee", '<')
801 /* These are equivalent to unordered or ... */
802 DEF_RTL_EXPR(UNEQ, "uneq", "ee", '<')
803 DEF_RTL_EXPR(UNGE, "unge", "ee", '<')
804 DEF_RTL_EXPR(UNGT, "ungt", "ee", '<')
805 DEF_RTL_EXPR(UNLE, "unle", "ee", '<')
806 DEF_RTL_EXPR(UNLT, "unlt", "ee", '<')
808 /* This is an ordered NE, ie !UNEQ, ie false for NaN. */
809 DEF_RTL_EXPR(LTGT, "ltgt", "ee", '<')
811 /* Represents the result of sign-extending the sole operand.
812 The machine modes of the operand and of the SIGN_EXTEND expression
813 determine how much sign-extension is going on. */
814 DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", '1')
816 /* Similar for zero-extension (such as unsigned short to int). */
817 DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", '1')
819 /* Similar but here the operand has a wider mode. */
820 DEF_RTL_EXPR(TRUNCATE, "truncate", "e", '1')
822 /* Similar for extending floating-point values (such as SFmode to DFmode). */
823 DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", '1')
824 DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", '1')
826 /* Conversion of fixed point operand to floating point value. */
827 DEF_RTL_EXPR(FLOAT, "float", "e", '1')
829 /* With fixed-point machine mode:
830 Conversion of floating point operand to fixed point value.
831 Value is defined only when the operand's value is an integer.
832 With floating-point machine mode (and operand with same mode):
833 Operand is rounded toward zero to produce an integer value
834 represented in floating point. */
835 DEF_RTL_EXPR(FIX, "fix", "e", '1')
837 /* Conversion of unsigned fixed point operand to floating point value. */
838 DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", '1')
840 /* With fixed-point machine mode:
841 Conversion of floating point operand to *unsigned* fixed point value.
842 Value is defined only when the operand's value is an integer. */
843 DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", '1')
846 DEF_RTL_EXPR(ABS, "abs", "e", '1')
849 DEF_RTL_EXPR(SQRT, "sqrt", "e", '1')
851 /* Find first bit that is set.
852 Value is 1 + number of trailing zeros in the arg.,
854 DEF_RTL_EXPR(FFS, "ffs", "e", '1')
856 /* Reference to a signed bit-field of specified size and position.
857 Operand 0 is the memory unit (usually SImode or QImode) which
858 contains the field's first bit. Operand 1 is the width, in bits.
859 Operand 2 is the number of bits in the memory unit before the
860 first bit of this field.
861 If BITS_BIG_ENDIAN is defined, the first bit is the msb and
862 operand 2 counts from the msb of the memory unit.
863 Otherwise, the first bit is the lsb and operand 2 counts from
864 the lsb of the memory unit. */
865 DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", 'b')
867 /* Similar for unsigned bit-field. */
868 DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", 'b')
870 /* For RISC machines. These save memory when splitting insns. */
872 /* HIGH are the high-order bits of a constant expression. */
873 DEF_RTL_EXPR(HIGH, "high", "e", 'o')
875 /* LO_SUM is the sum of a register and the low-order bits
876 of a constant expression. */
877 DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", 'o')
879 /* Header for range information. Operand 0 is the NOTE_INSN_RANGE_BEG insn.
880 Operand 1 is the NOTE_INSN_RANGE_END insn. Operand 2 is a vector of all of
881 the registers that can be substituted within this range. Operand 3 is the
882 number of calls in the range. Operand 4 is the number of insns in the
883 range. Operand 5 is the unique range number for this range. Operand 6 is
884 the basic block # of the start of the live range. Operand 7 is the basic
885 block # of the end of the live range. Operand 8 is the loop depth. Operand
886 9 is a bitmap of the registers live at the start of the range. Operand 10
887 is a bitmap of the registers live at the end of the range. Operand 11 is
888 marker number for the start of the range. Operand 12 is the marker number
889 for the end of the range. */
890 DEF_RTL_EXPR(RANGE_INFO, "range_info", "uuEiiiiiibbii", 'x')
892 /* Registers that can be substituted within the range. Operand 0 is the
893 original pseudo register number. Operand 1 will be filled in with the
894 pseudo register the value is copied for the duration of the range. Operand
895 2 is the number of references within the range to the register. Operand 3
896 is the number of sets or clobbers of the register in the range. Operand 4
897 is the number of deaths the register has. Operand 5 is the copy flags that
898 give the status of whether a copy is needed from the original register to
899 the new register at the beginning of the range, or whether a copy from the
900 new register back to the original at the end of the range. Operand 6 is the
901 live length. Operand 7 is the number of calls that this register is live
902 across. Operand 8 is the symbol node of the variable if the register is a
903 user variable. Operand 9 is the block node that the variable is declared
904 in if the register is a user variable. */
905 DEF_RTL_EXPR(RANGE_REG, "range_reg", "iiiiiiiitt", 'x')
907 /* Information about a local variable's ranges. Operand 0 is an EXPR_LIST of
908 the different ranges a variable is in where it is copied to a different
909 pseudo register. Operand 1 is the block that the variable is declared in.
910 Operand 2 is the number of distinct ranges. */
911 DEF_RTL_EXPR(RANGE_VAR, "range_var", "eti", 'x')
913 /* Information about the registers that are live at the current point. Operand
914 0 is the live bitmap. Operand 1 is the original block number. */
915 DEF_RTL_EXPR(RANGE_LIVE, "range_live", "bi", 'x')
917 /* A unary `__builtin_constant_p' expression. These are only emitted
918 during RTL generation, and then only if optimize > 0. They are
919 eliminated by the first CSE pass. */
920 DEF_RTL_EXPR(CONSTANT_P_RTX, "constant_p_rtx", "e", 'x')
922 /* A placeholder for a CALL_INSN which may be turned into a normal call,
923 a sibling (tail) call or tail recursion.
925 Immediately after RTL generation, this placeholder will be replaced
926 by the insns to perform the call, sibcall or tail recursion.
928 This RTX has 4 operands. The first three are lists of instructions to
929 perform the call as a normal call, sibling call and tail recursion
930 respectively. The latter two lists may be NULL, the first may never
933 The last operand is the tail recursion CODE_LABEL, which may be NULL if no
934 potential tail recursive calls were found.
936 The tail recursion label is needed so that we can clear LABEL_PRESERVE_P
937 after we select a call method.
939 This method of tail-call elimination is intended to be replaced by
940 tree-based optimizations once front-end conversions are complete. */
941 DEF_RTL_EXPR(CALL_PLACEHOLDER, "call_placeholder", "uuuu", 'x')
943 /* Describes a merge operation between two vector values.
944 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask
945 that specifies where the parts of the result are taken from. Set bits
946 indicate operand 0, clear bits indicate operand 1. The parts are defined
947 by the mode of the vectors. */
948 DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", 'x')
950 /* Describes an operation that selects parts of a vector.
951 Operands 0 is the source vector, operand 1 is a PARALLEL that contains
952 a CONST_INT for each of the subparts of the result vector, giving the
953 number of the source subpart that should be stored into it. */
954 DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", 'x')
956 /* Describes a vector concat operation. Operands 0 and 1 are the source
957 vectors, the result is a vector that is as long as operands 0 and 1
958 combined and is the concatenation of the two source vectors. */
959 DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", 'x')
961 /* Describes a vector constant. Each part of the PARALLEL that is operand 0
962 describes a constant for one of the subparts. */
963 DEF_RTL_EXPR(VEC_CONST, "vec_const", "e", 'x')
965 /* Describes an operation that converts a small vector into a larger one by
966 duplicating the input values. The output vector mode must have the same
967 submodes as the input vector mode, and the number of output parts must be
968 an integer multiple of the number of input parts. */
969 DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", 'x')
971 /* Addition with signed saturation */
972 DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", 'c')
974 /* Addition with unsigned saturation */
975 DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", 'c')
977 /* Operand 0 minus operand 1, with signed saturation. */
978 DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", '2')
980 /* Operand 0 minus operand 1, with unsigned saturation. */
981 DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", '2')
983 /* Signed saturating truncate. */
984 DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", '1')
986 /* Unsigned saturating truncate. */
987 DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", '1')
989 /* The SSA phi operator.
991 The argument is a vector of 2N rtxes. Element 2N+1 is a CONST_INT
992 containing the block number of the predecessor through which control
993 has passed when the register at element 2N is used.
995 Note that PHI may only appear at the beginning of a basic block.
997 ??? There may be multiple PHI insns, but they are all evaluated
998 in parallel. This probably ought to be changed to use a real
999 PARALLEL, as that would be less confusing and more in the spirit
1000 of canonical RTL. It is, however, easier to manipulate this way. */
1001 DEF_RTL_EXPR(PHI, "phi", "E", 'x')
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