1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
36 #include "basic-block.h"
45 /* This file contains the reload pass of the compiler, which is
46 run after register allocation has been done. It checks that
47 each insn is valid (operands required to be in registers really
48 are in registers of the proper class) and fixes up invalid ones
49 by copying values temporarily into registers for the insns
52 The results of register allocation are described by the vector
53 reg_renumber; the insns still contain pseudo regs, but reg_renumber
54 can be used to find which hard reg, if any, a pseudo reg is in.
56 The technique we always use is to free up a few hard regs that are
57 called ``reload regs'', and for each place where a pseudo reg
58 must be in a hard reg, copy it temporarily into one of the reload regs.
60 Reload regs are allocated locally for every instruction that needs
61 reloads. When there are pseudos which are allocated to a register that
62 has been chosen as a reload reg, such pseudos must be ``spilled''.
63 This means that they go to other hard regs, or to stack slots if no other
64 available hard regs can be found. Spilling can invalidate more
65 insns, requiring additional need for reloads, so we must keep checking
66 until the process stabilizes.
68 For machines with different classes of registers, we must keep track
69 of the register class needed for each reload, and make sure that
70 we allocate enough reload registers of each class.
72 The file reload.c contains the code that checks one insn for
73 validity and reports the reloads that it needs. This file
74 is in charge of scanning the entire rtl code, accumulating the
75 reload needs, spilling, assigning reload registers to use for
76 fixing up each insn, and generating the new insns to copy values
77 into the reload registers. */
79 #ifndef REGISTER_MOVE_COST
80 #define REGISTER_MOVE_COST(m, x, y) 2
84 #define LOCAL_REGNO(REGNO) 0
87 /* During reload_as_needed, element N contains a REG rtx for the hard reg
88 into which reg N has been reloaded (perhaps for a previous insn). */
89 static rtx *reg_last_reload_reg;
91 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
92 for an output reload that stores into reg N. */
93 static char *reg_has_output_reload;
95 /* Indicates which hard regs are reload-registers for an output reload
96 in the current insn. */
97 static HARD_REG_SET reg_is_output_reload;
99 /* Element N is the constant value to which pseudo reg N is equivalent,
100 or zero if pseudo reg N is not equivalent to a constant.
101 find_reloads looks at this in order to replace pseudo reg N
102 with the constant it stands for. */
103 rtx *reg_equiv_constant;
105 /* Element N is a memory location to which pseudo reg N is equivalent,
106 prior to any register elimination (such as frame pointer to stack
107 pointer). Depending on whether or not it is a valid address, this value
108 is transferred to either reg_equiv_address or reg_equiv_mem. */
109 rtx *reg_equiv_memory_loc;
111 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
112 This is used when the address is not valid as a memory address
113 (because its displacement is too big for the machine.) */
114 rtx *reg_equiv_address;
116 /* Element N is the memory slot to which pseudo reg N is equivalent,
117 or zero if pseudo reg N is not equivalent to a memory slot. */
120 /* Widest width in which each pseudo reg is referred to (via subreg). */
121 static unsigned int *reg_max_ref_width;
123 /* Element N is the list of insns that initialized reg N from its equivalent
124 constant or memory slot. */
125 static rtx *reg_equiv_init;
127 /* Vector to remember old contents of reg_renumber before spilling. */
128 static short *reg_old_renumber;
130 /* During reload_as_needed, element N contains the last pseudo regno reloaded
131 into hard register N. If that pseudo reg occupied more than one register,
132 reg_reloaded_contents points to that pseudo for each spill register in
133 use; all of these must remain set for an inheritance to occur. */
134 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
136 /* During reload_as_needed, element N contains the insn for which
137 hard register N was last used. Its contents are significant only
138 when reg_reloaded_valid is set for this register. */
139 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
141 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
142 static HARD_REG_SET reg_reloaded_valid;
143 /* Indicate if the register was dead at the end of the reload.
144 This is only valid if reg_reloaded_contents is set and valid. */
145 static HARD_REG_SET reg_reloaded_dead;
147 /* Number of spill-regs so far; number of valid elements of spill_regs. */
150 /* In parallel with spill_regs, contains REG rtx's for those regs.
151 Holds the last rtx used for any given reg, or 0 if it has never
152 been used for spilling yet. This rtx is reused, provided it has
154 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
156 /* In parallel with spill_regs, contains nonzero for a spill reg
157 that was stored after the last time it was used.
158 The precise value is the insn generated to do the store. */
159 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
161 /* This is the register that was stored with spill_reg_store. This is a
162 copy of reload_out / reload_out_reg when the value was stored; if
163 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
164 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
166 /* This table is the inverse mapping of spill_regs:
167 indexed by hard reg number,
168 it contains the position of that reg in spill_regs,
169 or -1 for something that is not in spill_regs.
171 ?!? This is no longer accurate. */
172 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
174 /* This reg set indicates registers that can't be used as spill registers for
175 the currently processed insn. These are the hard registers which are live
176 during the insn, but not allocated to pseudos, as well as fixed
178 static HARD_REG_SET bad_spill_regs;
180 /* These are the hard registers that can't be used as spill register for any
181 insn. This includes registers used for user variables and registers that
182 we can't eliminate. A register that appears in this set also can't be used
183 to retry register allocation. */
184 static HARD_REG_SET bad_spill_regs_global;
186 /* Describes order of use of registers for reloading
187 of spilled pseudo-registers. `n_spills' is the number of
188 elements that are actually valid; new ones are added at the end.
190 Both spill_regs and spill_reg_order are used on two occasions:
191 once during find_reload_regs, where they keep track of the spill registers
192 for a single insn, but also during reload_as_needed where they show all
193 the registers ever used by reload. For the latter case, the information
194 is calculated during finish_spills. */
195 static short spill_regs[FIRST_PSEUDO_REGISTER];
197 /* This vector of reg sets indicates, for each pseudo, which hard registers
198 may not be used for retrying global allocation because the register was
199 formerly spilled from one of them. If we allowed reallocating a pseudo to
200 a register that it was already allocated to, reload might not
202 static HARD_REG_SET *pseudo_previous_regs;
204 /* This vector of reg sets indicates, for each pseudo, which hard
205 registers may not be used for retrying global allocation because they
206 are used as spill registers during one of the insns in which the
208 static HARD_REG_SET *pseudo_forbidden_regs;
210 /* All hard regs that have been used as spill registers for any insn are
211 marked in this set. */
212 static HARD_REG_SET used_spill_regs;
214 /* Index of last register assigned as a spill register. We allocate in
215 a round-robin fashion. */
216 static int last_spill_reg;
218 /* Nonzero if indirect addressing is supported on the machine; this means
219 that spilling (REG n) does not require reloading it into a register in
220 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
221 value indicates the level of indirect addressing supported, e.g., two
222 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
224 static char spill_indirect_levels;
226 /* Nonzero if indirect addressing is supported when the innermost MEM is
227 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
228 which these are valid is the same as spill_indirect_levels, above. */
229 char indirect_symref_ok;
231 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
232 char double_reg_address_ok;
234 /* Record the stack slot for each spilled hard register. */
235 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
237 /* Width allocated so far for that stack slot. */
238 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
240 /* Record which pseudos needed to be spilled. */
241 static regset_head spilled_pseudos;
243 /* Used for communication between order_regs_for_reload and count_pseudo.
244 Used to avoid counting one pseudo twice. */
245 static regset_head pseudos_counted;
247 /* First uid used by insns created by reload in this function.
248 Used in find_equiv_reg. */
249 int reload_first_uid;
251 /* Flag set by local-alloc or global-alloc if anything is live in
252 a call-clobbered reg across calls. */
253 int caller_save_needed;
255 /* Set to 1 while reload_as_needed is operating.
256 Required by some machines to handle any generated moves differently. */
257 int reload_in_progress = 0;
259 /* These arrays record the insn_code of insns that may be needed to
260 perform input and output reloads of special objects. They provide a
261 place to pass a scratch register. */
262 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
263 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
265 /* This obstack is used for allocation of rtl during register elimination.
266 The allocated storage can be freed once find_reloads has processed the
268 struct obstack reload_obstack;
270 /* Points to the beginning of the reload_obstack. All insn_chain structures
271 are allocated first. */
272 char *reload_startobj;
274 /* The point after all insn_chain structures. Used to quickly deallocate
275 memory allocated in copy_reloads during calculate_needs_all_insns. */
276 char *reload_firstobj;
278 /* This points before all local rtl generated by register elimination.
279 Used to quickly free all memory after processing one insn. */
280 static char *reload_insn_firstobj;
282 #define obstack_chunk_alloc xmalloc
283 #define obstack_chunk_free free
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
290 extern tree current_function_decl;
292 extern union tree_node *current_function_decl;
295 /* List of all insns needing reloads. */
296 static struct insn_chain *insns_need_reload;
298 /* This structure is used to record information about register eliminations.
299 Each array entry describes one possible way of eliminating a register
300 in favor of another. If there is more than one way of eliminating a
301 particular register, the most preferred should be specified first. */
305 int from; /* Register number to be eliminated. */
306 int to; /* Register number used as replacement. */
307 int initial_offset; /* Initial difference between values. */
308 int can_eliminate; /* Non-zero if this elimination can be done. */
309 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
310 insns made by reload. */
311 int offset; /* Current offset between the two regs. */
312 int previous_offset; /* Offset at end of previous insn. */
313 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
314 rtx from_rtx; /* REG rtx for the register to be eliminated.
315 We cannot simply compare the number since
316 we might then spuriously replace a hard
317 register corresponding to a pseudo
318 assigned to the reg to be eliminated. */
319 rtx to_rtx; /* REG rtx for the replacement. */
322 static struct elim_table *reg_eliminate = 0;
324 /* This is an intermediate structure to initialize the table. It has
325 exactly the members provided by ELIMINABLE_REGS. */
326 static struct elim_table_1
330 } reg_eliminate_1[] =
332 /* If a set of eliminable registers was specified, define the table from it.
333 Otherwise, default to the normal case of the frame pointer being
334 replaced by the stack pointer. */
336 #ifdef ELIMINABLE_REGS
339 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
342 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
344 /* Record the number of pending eliminations that have an offset not equal
345 to their initial offset. If non-zero, we use a new copy of each
346 replacement result in any insns encountered. */
347 int num_not_at_initial_offset;
349 /* Count the number of registers that we may be able to eliminate. */
350 static int num_eliminable;
351 /* And the number of registers that are equivalent to a constant that
352 can be eliminated to frame_pointer / arg_pointer + constant. */
353 static int num_eliminable_invariants;
355 /* For each label, we record the offset of each elimination. If we reach
356 a label by more than one path and an offset differs, we cannot do the
357 elimination. This information is indexed by the number of the label.
358 The first table is an array of flags that records whether we have yet
359 encountered a label and the second table is an array of arrays, one
360 entry in the latter array for each elimination. */
362 static char *offsets_known_at;
363 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
365 /* Number of labels in the current function. */
367 static int num_labels;
369 static void replace_pseudos_in_call_usage PARAMS((rtx *,
372 static void maybe_fix_stack_asms PARAMS ((void));
373 static void copy_reloads PARAMS ((struct insn_chain *));
374 static void calculate_needs_all_insns PARAMS ((int));
375 static int find_reg PARAMS ((struct insn_chain *, int));
376 static void find_reload_regs PARAMS ((struct insn_chain *));
377 static void select_reload_regs PARAMS ((void));
378 static void delete_caller_save_insns PARAMS ((void));
380 static void spill_failure PARAMS ((rtx, enum reg_class));
381 static void count_spilled_pseudo PARAMS ((int, int, int));
382 static void delete_dead_insn PARAMS ((rtx));
383 static void alter_reg PARAMS ((int, int));
384 static void set_label_offsets PARAMS ((rtx, rtx, int));
385 static void check_eliminable_occurrences PARAMS ((rtx));
386 static void elimination_effects PARAMS ((rtx, enum machine_mode));
387 static int eliminate_regs_in_insn PARAMS ((rtx, int));
388 static void update_eliminable_offsets PARAMS ((void));
389 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
390 static void set_initial_elim_offsets PARAMS ((void));
391 static void verify_initial_elim_offsets PARAMS ((void));
392 static void set_initial_label_offsets PARAMS ((void));
393 static void set_offsets_for_label PARAMS ((rtx));
394 static void init_elim_table PARAMS ((void));
395 static void update_eliminables PARAMS ((HARD_REG_SET *));
396 static void spill_hard_reg PARAMS ((unsigned int, int));
397 static int finish_spills PARAMS ((int));
398 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
399 static void scan_paradoxical_subregs PARAMS ((rtx));
400 static void count_pseudo PARAMS ((int));
401 static void order_regs_for_reload PARAMS ((struct insn_chain *));
402 static void reload_as_needed PARAMS ((int));
403 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
404 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
405 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
408 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
411 static int reload_reg_free_p PARAMS ((unsigned int, int,
413 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
415 rtx, rtx, int, int));
416 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
417 enum reload_type, rtx, rtx,
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static int conflicts_with_override PARAMS ((rtx));
424 static void failed_reload PARAMS ((rtx, int));
425 static int set_reload_reg PARAMS ((int, int));
426 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
427 static void choose_reload_regs PARAMS ((struct insn_chain *));
428 static void merge_assigned_reloads PARAMS ((rtx));
429 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
430 struct reload *, rtx, int));
431 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, int));
433 static void do_input_reload PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_output_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void emit_reload_insns PARAMS ((struct insn_chain *));
438 static void delete_output_reload PARAMS ((rtx, int, int));
439 static void delete_address_reloads PARAMS ((rtx, rtx));
440 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
441 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
442 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
443 static void reload_cse_regs_1 PARAMS ((rtx));
444 static int reload_cse_noop_set_p PARAMS ((rtx));
445 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
446 static int reload_cse_simplify_operands PARAMS ((rtx));
447 static void reload_combine PARAMS ((void));
448 static void reload_combine_note_use PARAMS ((rtx *, rtx));
449 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
450 static void reload_cse_move2add PARAMS ((rtx));
451 static void move2add_note_store PARAMS ((rtx, rtx, void *));
453 static void add_auto_inc_notes PARAMS ((rtx, rtx));
455 static void copy_eh_notes PARAMS ((rtx, rtx));
456 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
458 static void failed_reload PARAMS ((rtx, int));
459 static int set_reload_reg PARAMS ((int, int));
460 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
461 static void reload_cse_simplify PARAMS ((rtx));
462 static void fixup_abnormal_edges PARAMS ((void));
463 extern void dump_needs PARAMS ((struct insn_chain *));
465 /* Initialize the reload pass once per compilation. */
472 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
473 Set spill_indirect_levels to the number of levels such addressing is
474 permitted, zero if it is not permitted at all. */
477 = gen_rtx_MEM (Pmode,
480 LAST_VIRTUAL_REGISTER + 1),
482 spill_indirect_levels = 0;
484 while (memory_address_p (QImode, tem))
486 spill_indirect_levels++;
487 tem = gen_rtx_MEM (Pmode, tem);
490 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
492 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
493 indirect_symref_ok = memory_address_p (QImode, tem);
495 /* See if reg+reg is a valid (and offsettable) address. */
497 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
499 tem = gen_rtx_PLUS (Pmode,
500 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
501 gen_rtx_REG (Pmode, i));
503 /* This way, we make sure that reg+reg is an offsettable address. */
504 tem = plus_constant (tem, 4);
506 if (memory_address_p (QImode, tem))
508 double_reg_address_ok = 1;
513 /* Initialize obstack for our rtl allocation. */
514 gcc_obstack_init (&reload_obstack);
515 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
517 INIT_REG_SET (&spilled_pseudos);
518 INIT_REG_SET (&pseudos_counted);
521 /* List of insn chains that are currently unused. */
522 static struct insn_chain *unused_insn_chains = 0;
524 /* Allocate an empty insn_chain structure. */
528 struct insn_chain *c;
530 if (unused_insn_chains == 0)
532 c = (struct insn_chain *)
533 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
534 INIT_REG_SET (&c->live_throughout);
535 INIT_REG_SET (&c->dead_or_set);
539 c = unused_insn_chains;
540 unused_insn_chains = c->next;
542 c->is_caller_save_insn = 0;
543 c->need_operand_change = 0;
549 /* Small utility function to set all regs in hard reg set TO which are
550 allocated to pseudos in regset FROM. */
553 compute_use_by_pseudos (to, from)
559 EXECUTE_IF_SET_IN_REG_SET
560 (from, FIRST_PSEUDO_REGISTER, regno,
562 int r = reg_renumber[regno];
567 /* reload_combine uses the information from
568 BASIC_BLOCK->global_live_at_start, which might still
569 contain registers that have not actually been allocated
570 since they have an equivalence. */
571 if (! reload_completed)
576 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
578 SET_HARD_REG_BIT (*to, r + nregs);
583 /* Replace all pseudos found in LOC with their corresponding
587 replace_pseudos_in_call_usage (loc, mem_mode, usage)
589 enum machine_mode mem_mode;
603 unsigned int regno = REGNO (x);
605 if (regno < FIRST_PSEUDO_REGISTER)
608 x = eliminate_regs (x, mem_mode, usage);
612 replace_pseudos_in_call_usage (loc, mem_mode, usage);
616 if (reg_equiv_constant[regno])
617 *loc = reg_equiv_constant[regno];
618 else if (reg_equiv_mem[regno])
619 *loc = reg_equiv_mem[regno];
620 else if (reg_equiv_address[regno])
621 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
622 else if (GET_CODE (regno_reg_rtx[regno]) != REG
623 || REGNO (regno_reg_rtx[regno]) != regno)
624 *loc = regno_reg_rtx[regno];
630 else if (code == MEM)
632 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
636 /* Process each of our operands recursively. */
637 fmt = GET_RTX_FORMAT (code);
638 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
640 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
641 else if (*fmt == 'E')
642 for (j = 0; j < XVECLEN (x, i); j++)
643 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
647 /* Global variables used by reload and its subroutines. */
649 /* Set during calculate_needs if an insn needs register elimination. */
650 static int something_needs_elimination;
651 /* Set during calculate_needs if an insn needs an operand changed. */
652 int something_needs_operands_changed;
654 /* Nonzero means we couldn't get enough spill regs. */
657 /* Main entry point for the reload pass.
659 FIRST is the first insn of the function being compiled.
661 GLOBAL nonzero means we were called from global_alloc
662 and should attempt to reallocate any pseudoregs that we
663 displace from hard regs we will use for reloads.
664 If GLOBAL is zero, we do not have enough information to do that,
665 so any pseudo reg that is spilled must go to the stack.
667 Return value is nonzero if reload failed
668 and we must not do any more for this function. */
671 reload (first, global)
677 register struct elim_table *ep;
679 /* The two pointers used to track the true location of the memory used
680 for label offsets. */
681 char *real_known_ptr = NULL;
682 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
684 /* Make sure even insns with volatile mem refs are recognizable. */
689 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
691 /* Make sure that the last insn in the chain
692 is not something that needs reloading. */
693 emit_note (NULL, NOTE_INSN_DELETED);
695 /* Enable find_equiv_reg to distinguish insns made by reload. */
696 reload_first_uid = get_max_uid ();
698 #ifdef SECONDARY_MEMORY_NEEDED
699 /* Initialize the secondary memory table. */
700 clear_secondary_mem ();
703 /* We don't have a stack slot for any spill reg yet. */
704 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
705 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
707 /* Initialize the save area information for caller-save, in case some
711 /* Compute which hard registers are now in use
712 as homes for pseudo registers.
713 This is done here rather than (eg) in global_alloc
714 because this point is reached even if not optimizing. */
715 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
718 /* A function that receives a nonlocal goto must save all call-saved
720 if (current_function_has_nonlocal_label)
721 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
722 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
723 regs_ever_live[i] = 1;
725 /* Find all the pseudo registers that didn't get hard regs
726 but do have known equivalent constants or memory slots.
727 These include parameters (known equivalent to parameter slots)
728 and cse'd or loop-moved constant memory addresses.
730 Record constant equivalents in reg_equiv_constant
731 so they will be substituted by find_reloads.
732 Record memory equivalents in reg_mem_equiv so they can
733 be substituted eventually by altering the REG-rtx's. */
735 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
736 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
740 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
741 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
742 pseudo_forbidden_regs
743 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
745 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
747 CLEAR_HARD_REG_SET (bad_spill_regs_global);
749 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
750 Also find all paradoxical subregs and find largest such for each pseudo.
751 On machines with small register classes, record hard registers that
752 are used for user variables. These can never be used for spills.
753 Also look for a "constant" REG_SETJMP. This means that all
754 caller-saved registers must be marked live. */
756 num_eliminable_invariants = 0;
757 for (insn = first; insn; insn = NEXT_INSN (insn))
759 rtx set = single_set (insn);
761 if (GET_CODE (insn) == CALL_INSN
762 && find_reg_note (insn, REG_SETJMP, NULL))
763 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
764 if (! call_used_regs[i])
765 regs_ever_live[i] = 1;
767 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
769 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
771 #ifdef LEGITIMATE_PIC_OPERAND_P
772 && (! function_invariant_p (XEXP (note, 0))
774 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
778 rtx x = XEXP (note, 0);
779 i = REGNO (SET_DEST (set));
780 if (i > LAST_VIRTUAL_REGISTER)
782 if (GET_CODE (x) == MEM)
784 /* Always unshare the equivalence, so we can
785 substitute into this insn without touching the
787 reg_equiv_memory_loc[i] = copy_rtx (x);
789 else if (function_invariant_p (x))
791 if (GET_CODE (x) == PLUS)
793 /* This is PLUS of frame pointer and a constant,
794 and might be shared. Unshare it. */
795 reg_equiv_constant[i] = copy_rtx (x);
796 num_eliminable_invariants++;
798 else if (x == frame_pointer_rtx
799 || x == arg_pointer_rtx)
801 reg_equiv_constant[i] = x;
802 num_eliminable_invariants++;
804 else if (LEGITIMATE_CONSTANT_P (x))
805 reg_equiv_constant[i] = x;
807 reg_equiv_memory_loc[i]
808 = force_const_mem (GET_MODE (SET_DEST (set)), x);
813 /* If this register is being made equivalent to a MEM
814 and the MEM is not SET_SRC, the equivalencing insn
815 is one with the MEM as a SET_DEST and it occurs later.
816 So don't mark this insn now. */
817 if (GET_CODE (x) != MEM
818 || rtx_equal_p (SET_SRC (set), x))
820 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
825 /* If this insn is setting a MEM from a register equivalent to it,
826 this is the equivalencing insn. */
827 else if (set && GET_CODE (SET_DEST (set)) == MEM
828 && GET_CODE (SET_SRC (set)) == REG
829 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
830 && rtx_equal_p (SET_DEST (set),
831 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
832 reg_equiv_init[REGNO (SET_SRC (set))]
833 = gen_rtx_INSN_LIST (VOIDmode, insn,
834 reg_equiv_init[REGNO (SET_SRC (set))]);
837 scan_paradoxical_subregs (PATTERN (insn));
842 num_labels = max_label_num () - get_first_label_num ();
844 /* Allocate the tables used to store offset information at labels. */
845 /* We used to use alloca here, but the size of what it would try to
846 allocate would occasionally cause it to exceed the stack limit and
847 cause a core dump. */
848 real_known_ptr = xmalloc (num_labels);
850 = (int (*)[NUM_ELIMINABLE_REGS])
851 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
853 offsets_known_at = real_known_ptr - get_first_label_num ();
855 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
857 /* Alter each pseudo-reg rtx to contain its hard reg number.
858 Assign stack slots to the pseudos that lack hard regs or equivalents.
859 Do not touch virtual registers. */
861 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
864 /* If we have some registers we think can be eliminated, scan all insns to
865 see if there is an insn that sets one of these registers to something
866 other than itself plus a constant. If so, the register cannot be
867 eliminated. Doing this scan here eliminates an extra pass through the
868 main reload loop in the most common case where register elimination
870 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
871 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
872 || GET_CODE (insn) == CALL_INSN)
873 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
875 maybe_fix_stack_asms ();
877 insns_need_reload = 0;
878 something_needs_elimination = 0;
880 /* Initialize to -1, which means take the first spill register. */
883 /* Spill any hard regs that we know we can't eliminate. */
884 CLEAR_HARD_REG_SET (used_spill_regs);
885 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
886 if (! ep->can_eliminate)
887 spill_hard_reg (ep->from, 1);
889 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
890 if (frame_pointer_needed)
891 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
893 finish_spills (global);
895 /* From now on, we may need to generate moves differently. We may also
896 allow modifications of insns which cause them to not be recognized.
897 Any such modifications will be cleaned up during reload itself. */
898 reload_in_progress = 1;
900 /* This loop scans the entire function each go-round
901 and repeats until one repetition spills no additional hard regs. */
904 int something_changed;
907 HOST_WIDE_INT starting_frame_size;
909 /* Round size of stack frame to stack_alignment_needed. This must be done
910 here because the stack size may be a part of the offset computation
911 for register elimination, and there might have been new stack slots
912 created in the last iteration of this loop. */
913 if (cfun->stack_alignment_needed)
914 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
916 starting_frame_size = get_frame_size ();
918 set_initial_elim_offsets ();
919 set_initial_label_offsets ();
921 /* For each pseudo register that has an equivalent location defined,
922 try to eliminate any eliminable registers (such as the frame pointer)
923 assuming initial offsets for the replacement register, which
926 If the resulting location is directly addressable, substitute
927 the MEM we just got directly for the old REG.
929 If it is not addressable but is a constant or the sum of a hard reg
930 and constant, it is probably not addressable because the constant is
931 out of range, in that case record the address; we will generate
932 hairy code to compute the address in a register each time it is
933 needed. Similarly if it is a hard register, but one that is not
934 valid as an address register.
936 If the location is not addressable, but does not have one of the
937 above forms, assign a stack slot. We have to do this to avoid the
938 potential of producing lots of reloads if, e.g., a location involves
939 a pseudo that didn't get a hard register and has an equivalent memory
940 location that also involves a pseudo that didn't get a hard register.
942 Perhaps at some point we will improve reload_when_needed handling
943 so this problem goes away. But that's very hairy. */
945 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
946 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
948 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
950 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
952 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
953 else if (CONSTANT_P (XEXP (x, 0))
954 || (GET_CODE (XEXP (x, 0)) == REG
955 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
956 || (GET_CODE (XEXP (x, 0)) == PLUS
957 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
958 && (REGNO (XEXP (XEXP (x, 0), 0))
959 < FIRST_PSEUDO_REGISTER)
960 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
961 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
964 /* Make a new stack slot. Then indicate that something
965 changed so we go back and recompute offsets for
966 eliminable registers because the allocation of memory
967 below might change some offset. reg_equiv_{mem,address}
968 will be set up for this pseudo on the next pass around
970 reg_equiv_memory_loc[i] = 0;
971 reg_equiv_init[i] = 0;
976 if (caller_save_needed)
979 /* If we allocated another stack slot, redo elimination bookkeeping. */
980 if (starting_frame_size != get_frame_size ())
983 if (caller_save_needed)
985 save_call_clobbered_regs ();
986 /* That might have allocated new insn_chain structures. */
987 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
990 calculate_needs_all_insns (global);
992 CLEAR_REG_SET (&spilled_pseudos);
995 something_changed = 0;
997 /* If we allocated any new memory locations, make another pass
998 since it might have changed elimination offsets. */
999 if (starting_frame_size != get_frame_size ())
1000 something_changed = 1;
1003 HARD_REG_SET to_spill;
1004 CLEAR_HARD_REG_SET (to_spill);
1005 update_eliminables (&to_spill);
1006 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1007 if (TEST_HARD_REG_BIT (to_spill, i))
1009 spill_hard_reg (i, 1);
1012 /* Regardless of the state of spills, if we previously had
1013 a register that we thought we could eliminate, but no can
1014 not eliminate, we must run another pass.
1016 Consider pseudos which have an entry in reg_equiv_* which
1017 reference an eliminable register. We must make another pass
1018 to update reg_equiv_* so that we do not substitute in the
1019 old value from when we thought the elimination could be
1021 something_changed = 1;
1025 select_reload_regs ();
1029 if (insns_need_reload != 0 || did_spill)
1030 something_changed |= finish_spills (global);
1032 if (! something_changed)
1035 if (caller_save_needed)
1036 delete_caller_save_insns ();
1038 obstack_free (&reload_obstack, reload_firstobj);
1041 /* If global-alloc was run, notify it of any register eliminations we have
1044 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1045 if (ep->can_eliminate)
1046 mark_elimination (ep->from, ep->to);
1048 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1049 If that insn didn't set the register (i.e., it copied the register to
1050 memory), just delete that insn instead of the equivalencing insn plus
1051 anything now dead. If we call delete_dead_insn on that insn, we may
1052 delete the insn that actually sets the register if the register dies
1053 there and that is incorrect. */
1055 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1057 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1060 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1062 rtx equiv_insn = XEXP (list, 0);
1063 if (GET_CODE (equiv_insn) == NOTE)
1065 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1066 delete_dead_insn (equiv_insn);
1069 PUT_CODE (equiv_insn, NOTE);
1070 NOTE_SOURCE_FILE (equiv_insn) = 0;
1071 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1077 /* Use the reload registers where necessary
1078 by generating move instructions to move the must-be-register
1079 values into or out of the reload registers. */
1081 if (insns_need_reload != 0 || something_needs_elimination
1082 || something_needs_operands_changed)
1084 HOST_WIDE_INT old_frame_size = get_frame_size ();
1086 reload_as_needed (global);
1088 if (old_frame_size != get_frame_size ())
1092 verify_initial_elim_offsets ();
1095 /* If we were able to eliminate the frame pointer, show that it is no
1096 longer live at the start of any basic block. If it ls live by
1097 virtue of being in a pseudo, that pseudo will be marked live
1098 and hence the frame pointer will be known to be live via that
1101 if (! frame_pointer_needed)
1102 for (i = 0; i < n_basic_blocks; i++)
1103 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1104 HARD_FRAME_POINTER_REGNUM);
1106 /* Come here (with failure set nonzero) if we can't get enough spill regs
1107 and we decide not to abort about it. */
1110 CLEAR_REG_SET (&spilled_pseudos);
1111 reload_in_progress = 0;
1113 /* Now eliminate all pseudo regs by modifying them into
1114 their equivalent memory references.
1115 The REG-rtx's for the pseudos are modified in place,
1116 so all insns that used to refer to them now refer to memory.
1118 For a reg that has a reg_equiv_address, all those insns
1119 were changed by reloading so that no insns refer to it any longer;
1120 but the DECL_RTL of a variable decl may refer to it,
1121 and if so this causes the debugging info to mention the variable. */
1123 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1128 int is_readonly = 0;
1130 if (reg_equiv_memory_loc[i])
1132 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1133 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1134 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1137 if (reg_equiv_mem[i])
1138 addr = XEXP (reg_equiv_mem[i], 0);
1140 if (reg_equiv_address[i])
1141 addr = reg_equiv_address[i];
1145 if (reg_renumber[i] < 0)
1147 rtx reg = regno_reg_rtx[i];
1148 PUT_CODE (reg, MEM);
1149 XEXP (reg, 0) = addr;
1150 REG_USERVAR_P (reg) = 0;
1151 RTX_UNCHANGING_P (reg) = is_readonly;
1152 MEM_IN_STRUCT_P (reg) = in_struct;
1153 MEM_SCALAR_P (reg) = is_scalar;
1154 /* We have no alias information about this newly created
1156 set_mem_alias_set (reg, 0);
1158 else if (reg_equiv_mem[i])
1159 XEXP (reg_equiv_mem[i], 0) = addr;
1163 /* We must set reload_completed now since the cleanup_subreg_operands call
1164 below will re-recognize each insn and reload may have generated insns
1165 which are only valid during and after reload. */
1166 reload_completed = 1;
1168 /* Make a pass over all the insns and delete all USEs which we inserted
1169 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1170 notes. Delete all CLOBBER insns that don't refer to the return value
1171 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1172 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1173 and regenerate REG_INC notes that may have been moved around. */
1175 for (insn = first; insn; insn = NEXT_INSN (insn))
1180 if (GET_CODE (insn) == CALL_INSN)
1181 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1183 CALL_INSN_FUNCTION_USAGE (insn));
1185 if ((GET_CODE (PATTERN (insn)) == USE
1186 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1187 || (GET_CODE (PATTERN (insn)) == CLOBBER
1188 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1189 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1195 pnote = ®_NOTES (insn);
1198 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1199 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1200 || REG_NOTE_KIND (*pnote) == REG_INC
1201 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1202 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1203 *pnote = XEXP (*pnote, 1);
1205 pnote = &XEXP (*pnote, 1);
1209 add_auto_inc_notes (insn, PATTERN (insn));
1212 /* And simplify (subreg (reg)) if it appears as an operand. */
1213 cleanup_subreg_operands (insn);
1216 /* If we are doing stack checking, give a warning if this function's
1217 frame size is larger than we expect. */
1218 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1220 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1221 static int verbose_warned = 0;
1223 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1224 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1225 size += UNITS_PER_WORD;
1227 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1229 warning ("frame size too large for reliable stack checking");
1230 if (! verbose_warned)
1232 warning ("try reducing the number of local variables");
1238 /* Indicate that we no longer have known memory locations or constants. */
1239 if (reg_equiv_constant)
1240 free (reg_equiv_constant);
1241 reg_equiv_constant = 0;
1242 if (reg_equiv_memory_loc)
1243 free (reg_equiv_memory_loc);
1244 reg_equiv_memory_loc = 0;
1247 free (real_known_ptr);
1251 free (reg_equiv_mem);
1252 free (reg_equiv_init);
1253 free (reg_equiv_address);
1254 free (reg_max_ref_width);
1255 free (reg_old_renumber);
1256 free (pseudo_previous_regs);
1257 free (pseudo_forbidden_regs);
1259 CLEAR_HARD_REG_SET (used_spill_regs);
1260 for (i = 0; i < n_spills; i++)
1261 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1263 /* Free all the insn_chain structures at once. */
1264 obstack_free (&reload_obstack, reload_startobj);
1265 unused_insn_chains = 0;
1266 fixup_abnormal_edges ();
1271 /* Yet another special case. Unfortunately, reg-stack forces people to
1272 write incorrect clobbers in asm statements. These clobbers must not
1273 cause the register to appear in bad_spill_regs, otherwise we'll call
1274 fatal_insn later. We clear the corresponding regnos in the live
1275 register sets to avoid this.
1276 The whole thing is rather sick, I'm afraid. */
1279 maybe_fix_stack_asms ()
1282 const char *constraints[MAX_RECOG_OPERANDS];
1283 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1284 struct insn_chain *chain;
1286 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1289 HARD_REG_SET clobbered, allowed;
1292 if (! INSN_P (chain->insn)
1293 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1295 pat = PATTERN (chain->insn);
1296 if (GET_CODE (pat) != PARALLEL)
1299 CLEAR_HARD_REG_SET (clobbered);
1300 CLEAR_HARD_REG_SET (allowed);
1302 /* First, make a mask of all stack regs that are clobbered. */
1303 for (i = 0; i < XVECLEN (pat, 0); i++)
1305 rtx t = XVECEXP (pat, 0, i);
1306 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1307 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1310 /* Get the operand values and constraints out of the insn. */
1311 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1312 constraints, operand_mode);
1314 /* For every operand, see what registers are allowed. */
1315 for (i = 0; i < noperands; i++)
1317 const char *p = constraints[i];
1318 /* For every alternative, we compute the class of registers allowed
1319 for reloading in CLS, and merge its contents into the reg set
1321 int cls = (int) NO_REGS;
1327 if (c == '\0' || c == ',' || c == '#')
1329 /* End of one alternative - mark the regs in the current
1330 class, and reset the class. */
1331 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1336 } while (c != '\0' && c != ',');
1344 case '=': case '+': case '*': case '%': case '?': case '!':
1345 case '0': case '1': case '2': case '3': case '4': case 'm':
1346 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1347 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1348 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1353 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1358 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1362 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1367 /* Those of the registers which are clobbered, but allowed by the
1368 constraints, must be usable as reload registers. So clear them
1369 out of the life information. */
1370 AND_HARD_REG_SET (allowed, clobbered);
1371 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1372 if (TEST_HARD_REG_BIT (allowed, i))
1374 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1375 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1382 /* Copy the global variables n_reloads and rld into the corresponding elts
1385 copy_reloads (chain)
1386 struct insn_chain *chain;
1388 chain->n_reloads = n_reloads;
1390 = (struct reload *) obstack_alloc (&reload_obstack,
1391 n_reloads * sizeof (struct reload));
1392 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1393 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1396 /* Walk the chain of insns, and determine for each whether it needs reloads
1397 and/or eliminations. Build the corresponding insns_need_reload list, and
1398 set something_needs_elimination as appropriate. */
1400 calculate_needs_all_insns (global)
1403 struct insn_chain **pprev_reload = &insns_need_reload;
1404 struct insn_chain *chain, *next = 0;
1406 something_needs_elimination = 0;
1408 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1409 for (chain = reload_insn_chain; chain != 0; chain = next)
1411 rtx insn = chain->insn;
1415 /* Clear out the shortcuts. */
1416 chain->n_reloads = 0;
1417 chain->need_elim = 0;
1418 chain->need_reload = 0;
1419 chain->need_operand_change = 0;
1421 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1422 include REG_LABEL), we need to see what effects this has on the
1423 known offsets at labels. */
1425 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1426 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1427 set_label_offsets (insn, insn, 0);
1431 rtx old_body = PATTERN (insn);
1432 int old_code = INSN_CODE (insn);
1433 rtx old_notes = REG_NOTES (insn);
1434 int did_elimination = 0;
1435 int operands_changed = 0;
1436 rtx set = single_set (insn);
1438 /* Skip insns that only set an equivalence. */
1439 if (set && GET_CODE (SET_DEST (set)) == REG
1440 && reg_renumber[REGNO (SET_DEST (set))] < 0
1441 && reg_equiv_constant[REGNO (SET_DEST (set))])
1444 /* If needed, eliminate any eliminable registers. */
1445 if (num_eliminable || num_eliminable_invariants)
1446 did_elimination = eliminate_regs_in_insn (insn, 0);
1448 /* Analyze the instruction. */
1449 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1450 global, spill_reg_order);
1452 /* If a no-op set needs more than one reload, this is likely
1453 to be something that needs input address reloads. We
1454 can't get rid of this cleanly later, and it is of no use
1455 anyway, so discard it now.
1456 We only do this when expensive_optimizations is enabled,
1457 since this complements reload inheritance / output
1458 reload deletion, and it can make debugging harder. */
1459 if (flag_expensive_optimizations && n_reloads > 1)
1461 rtx set = single_set (insn);
1463 && SET_SRC (set) == SET_DEST (set)
1464 && GET_CODE (SET_SRC (set)) == REG
1465 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1468 /* Delete it from the reload chain */
1470 chain->prev->next = next;
1472 reload_insn_chain = next;
1474 next->prev = chain->prev;
1475 chain->next = unused_insn_chains;
1476 unused_insn_chains = chain;
1481 update_eliminable_offsets ();
1483 /* Remember for later shortcuts which insns had any reloads or
1484 register eliminations. */
1485 chain->need_elim = did_elimination;
1486 chain->need_reload = n_reloads > 0;
1487 chain->need_operand_change = operands_changed;
1489 /* Discard any register replacements done. */
1490 if (did_elimination)
1492 obstack_free (&reload_obstack, reload_insn_firstobj);
1493 PATTERN (insn) = old_body;
1494 INSN_CODE (insn) = old_code;
1495 REG_NOTES (insn) = old_notes;
1496 something_needs_elimination = 1;
1499 something_needs_operands_changed |= operands_changed;
1503 copy_reloads (chain);
1504 *pprev_reload = chain;
1505 pprev_reload = &chain->next_need_reload;
1512 /* Comparison function for qsort to decide which of two reloads
1513 should be handled first. *P1 and *P2 are the reload numbers. */
1516 reload_reg_class_lower (r1p, r2p)
1520 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1523 /* Consider required reloads before optional ones. */
1524 t = rld[r1].optional - rld[r2].optional;
1528 /* Count all solitary classes before non-solitary ones. */
1529 t = ((reg_class_size[(int) rld[r2].class] == 1)
1530 - (reg_class_size[(int) rld[r1].class] == 1));
1534 /* Aside from solitaires, consider all multi-reg groups first. */
1535 t = rld[r2].nregs - rld[r1].nregs;
1539 /* Consider reloads in order of increasing reg-class number. */
1540 t = (int) rld[r1].class - (int) rld[r2].class;
1544 /* If reloads are equally urgent, sort by reload number,
1545 so that the results of qsort leave nothing to chance. */
1549 /* The cost of spilling each hard reg. */
1550 static int spill_cost[FIRST_PSEUDO_REGISTER];
1552 /* When spilling multiple hard registers, we use SPILL_COST for the first
1553 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1554 only the first hard reg for a multi-reg pseudo. */
1555 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1557 /* Update the spill cost arrays, considering that pseudo REG is live. */
1563 int freq = REG_FREQ (reg);
1564 int r = reg_renumber[reg];
1567 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1568 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1571 SET_REGNO_REG_SET (&pseudos_counted, reg);
1576 spill_add_cost[r] += freq;
1578 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1580 spill_cost[r + nregs] += freq;
1583 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1584 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1587 order_regs_for_reload (chain)
1588 struct insn_chain *chain;
1591 HARD_REG_SET used_by_pseudos;
1592 HARD_REG_SET used_by_pseudos2;
1594 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1596 memset (spill_cost, 0, sizeof spill_cost);
1597 memset (spill_add_cost, 0, sizeof spill_add_cost);
1599 /* Count number of uses of each hard reg by pseudo regs allocated to it
1600 and then order them by decreasing use. First exclude hard registers
1601 that are live in or across this insn. */
1603 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1604 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1605 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1606 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1608 /* Now find out which pseudos are allocated to it, and update
1610 CLEAR_REG_SET (&pseudos_counted);
1612 EXECUTE_IF_SET_IN_REG_SET
1613 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1617 EXECUTE_IF_SET_IN_REG_SET
1618 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1622 CLEAR_REG_SET (&pseudos_counted);
1625 /* Vector of reload-numbers showing the order in which the reloads should
1627 static short reload_order[MAX_RELOADS];
1629 /* This is used to keep track of the spill regs used in one insn. */
1630 static HARD_REG_SET used_spill_regs_local;
1632 /* We decided to spill hard register SPILLED, which has a size of
1633 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1634 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1635 update SPILL_COST/SPILL_ADD_COST. */
1638 count_spilled_pseudo (spilled, spilled_nregs, reg)
1639 int spilled, spilled_nregs, reg;
1641 int r = reg_renumber[reg];
1642 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1644 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1645 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1648 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1650 spill_add_cost[r] -= REG_FREQ (reg);
1652 spill_cost[r + nregs] -= REG_FREQ (reg);
1655 /* Find reload register to use for reload number ORDER. */
1658 find_reg (chain, order)
1659 struct insn_chain *chain;
1662 int rnum = reload_order[order];
1663 struct reload *rl = rld + rnum;
1664 int best_cost = INT_MAX;
1668 HARD_REG_SET not_usable;
1669 HARD_REG_SET used_by_other_reload;
1671 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1672 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1673 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1675 CLEAR_HARD_REG_SET (used_by_other_reload);
1676 for (k = 0; k < order; k++)
1678 int other = reload_order[k];
1680 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1681 for (j = 0; j < rld[other].nregs; j++)
1682 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1685 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1687 unsigned int regno = i;
1689 if (! TEST_HARD_REG_BIT (not_usable, regno)
1690 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1691 && HARD_REGNO_MODE_OK (regno, rl->mode))
1693 int this_cost = spill_cost[regno];
1695 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1697 for (j = 1; j < this_nregs; j++)
1699 this_cost += spill_add_cost[regno + j];
1700 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1701 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1706 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1708 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1710 if (this_cost < best_cost
1711 /* Among registers with equal cost, prefer caller-saved ones, or
1712 use REG_ALLOC_ORDER if it is defined. */
1713 || (this_cost == best_cost
1714 #ifdef REG_ALLOC_ORDER
1715 && (inv_reg_alloc_order[regno]
1716 < inv_reg_alloc_order[best_reg])
1718 && call_used_regs[regno]
1719 && ! call_used_regs[best_reg]
1724 best_cost = this_cost;
1732 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1734 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1735 rl->regno = best_reg;
1737 EXECUTE_IF_SET_IN_REG_SET
1738 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1740 count_spilled_pseudo (best_reg, rl->nregs, j);
1743 EXECUTE_IF_SET_IN_REG_SET
1744 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1746 count_spilled_pseudo (best_reg, rl->nregs, j);
1749 for (i = 0; i < rl->nregs; i++)
1751 if (spill_cost[best_reg + i] != 0
1752 || spill_add_cost[best_reg + i] != 0)
1754 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1759 /* Find more reload regs to satisfy the remaining need of an insn, which
1761 Do it by ascending class number, since otherwise a reg
1762 might be spilled for a big class and might fail to count
1763 for a smaller class even though it belongs to that class. */
1766 find_reload_regs (chain)
1767 struct insn_chain *chain;
1771 /* In order to be certain of getting the registers we need,
1772 we must sort the reloads into order of increasing register class.
1773 Then our grabbing of reload registers will parallel the process
1774 that provided the reload registers. */
1775 for (i = 0; i < chain->n_reloads; i++)
1777 /* Show whether this reload already has a hard reg. */
1778 if (chain->rld[i].reg_rtx)
1780 int regno = REGNO (chain->rld[i].reg_rtx);
1781 chain->rld[i].regno = regno;
1783 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1786 chain->rld[i].regno = -1;
1787 reload_order[i] = i;
1790 n_reloads = chain->n_reloads;
1791 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1793 CLEAR_HARD_REG_SET (used_spill_regs_local);
1796 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1798 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1800 /* Compute the order of preference for hard registers to spill. */
1802 order_regs_for_reload (chain);
1804 for (i = 0; i < n_reloads; i++)
1806 int r = reload_order[i];
1808 /* Ignore reloads that got marked inoperative. */
1809 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1810 && ! rld[r].optional
1811 && rld[r].regno == -1)
1812 if (! find_reg (chain, i))
1814 spill_failure (chain->insn, rld[r].class);
1820 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1821 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1823 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1827 select_reload_regs ()
1829 struct insn_chain *chain;
1831 /* Try to satisfy the needs for each insn. */
1832 for (chain = insns_need_reload; chain != 0;
1833 chain = chain->next_need_reload)
1834 find_reload_regs (chain);
1837 /* Delete all insns that were inserted by emit_caller_save_insns during
1840 delete_caller_save_insns ()
1842 struct insn_chain *c = reload_insn_chain;
1846 while (c != 0 && c->is_caller_save_insn)
1848 struct insn_chain *next = c->next;
1851 if (c == reload_insn_chain)
1852 reload_insn_chain = next;
1856 next->prev = c->prev;
1858 c->prev->next = next;
1859 c->next = unused_insn_chains;
1860 unused_insn_chains = c;
1868 /* Handle the failure to find a register to spill.
1869 INSN should be one of the insns which needed this particular spill reg. */
1872 spill_failure (insn, class)
1874 enum reg_class class;
1876 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1877 if (asm_noperands (PATTERN (insn)) >= 0)
1878 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1879 reg_class_names[class]);
1882 error ("Unable to find a register to spill in class `%s'.",
1883 reg_class_names[class]);
1884 fatal_insn ("This is the insn:", insn);
1888 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1889 data that is dead in INSN. */
1892 delete_dead_insn (insn)
1895 rtx prev = prev_real_insn (insn);
1898 /* If the previous insn sets a register that dies in our insn, delete it
1900 if (prev && GET_CODE (PATTERN (prev)) == SET
1901 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1902 && reg_mentioned_p (prev_dest, PATTERN (insn))
1903 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1904 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1905 delete_dead_insn (prev);
1907 PUT_CODE (insn, NOTE);
1908 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1909 NOTE_SOURCE_FILE (insn) = 0;
1912 /* Modify the home of pseudo-reg I.
1913 The new home is present in reg_renumber[I].
1915 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1916 or it may be -1, meaning there is none or it is not relevant.
1917 This is used so that all pseudos spilled from a given hard reg
1918 can share one stack slot. */
1921 alter_reg (i, from_reg)
1925 /* When outputting an inline function, this can happen
1926 for a reg that isn't actually used. */
1927 if (regno_reg_rtx[i] == 0)
1930 /* If the reg got changed to a MEM at rtl-generation time,
1932 if (GET_CODE (regno_reg_rtx[i]) != REG)
1935 /* Modify the reg-rtx to contain the new hard reg
1936 number or else to contain its pseudo reg number. */
1937 REGNO (regno_reg_rtx[i])
1938 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1940 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1941 allocate a stack slot for it. */
1943 if (reg_renumber[i] < 0
1944 && REG_N_REFS (i) > 0
1945 && reg_equiv_constant[i] == 0
1946 && reg_equiv_memory_loc[i] == 0)
1949 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1950 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1953 /* Each pseudo reg has an inherent size which comes from its own mode,
1954 and a total size which provides room for paradoxical subregs
1955 which refer to the pseudo reg in wider modes.
1957 We can use a slot already allocated if it provides both
1958 enough inherent space and enough total space.
1959 Otherwise, we allocate a new slot, making sure that it has no less
1960 inherent space, and no less total space, then the previous slot. */
1963 /* No known place to spill from => no slot to reuse. */
1964 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1965 inherent_size == total_size ? 0 : -1);
1966 if (BYTES_BIG_ENDIAN)
1967 /* Cancel the big-endian correction done in assign_stack_local.
1968 Get the address of the beginning of the slot.
1969 This is so we can do a big-endian correction unconditionally
1971 adjust = inherent_size - total_size;
1973 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1975 /* Nothing can alias this slot except this pseudo. */
1976 set_mem_alias_set (x, new_alias_set ());
1979 /* Reuse a stack slot if possible. */
1980 else if (spill_stack_slot[from_reg] != 0
1981 && spill_stack_slot_width[from_reg] >= total_size
1982 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1984 x = spill_stack_slot[from_reg];
1986 /* Allocate a bigger slot. */
1989 /* Compute maximum size needed, both for inherent size
1990 and for total size. */
1991 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1994 if (spill_stack_slot[from_reg])
1996 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1998 mode = GET_MODE (spill_stack_slot[from_reg]);
1999 if (spill_stack_slot_width[from_reg] > total_size)
2000 total_size = spill_stack_slot_width[from_reg];
2003 /* Make a slot with that size. */
2004 x = assign_stack_local (mode, total_size,
2005 inherent_size == total_size ? 0 : -1);
2008 /* All pseudos mapped to this slot can alias each other. */
2009 if (spill_stack_slot[from_reg])
2010 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2012 set_mem_alias_set (x, new_alias_set ());
2014 if (BYTES_BIG_ENDIAN)
2016 /* Cancel the big-endian correction done in assign_stack_local.
2017 Get the address of the beginning of the slot.
2018 This is so we can do a big-endian correction unconditionally
2020 adjust = GET_MODE_SIZE (mode) - total_size;
2022 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2025 plus_constant (XEXP (x, 0), adjust));
2028 spill_stack_slot[from_reg] = stack_slot;
2029 spill_stack_slot_width[from_reg] = total_size;
2032 /* On a big endian machine, the "address" of the slot
2033 is the address of the low part that fits its inherent mode. */
2034 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2035 adjust += (total_size - inherent_size);
2037 /* If we have any adjustment to make, or if the stack slot is the
2038 wrong mode, make a new stack slot. */
2039 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2040 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2042 /* Save the stack slot for later. */
2043 reg_equiv_memory_loc[i] = x;
2047 /* Mark the slots in regs_ever_live for the hard regs
2048 used by pseudo-reg number REGNO. */
2051 mark_home_live (regno)
2054 register int i, lim;
2056 i = reg_renumber[regno];
2059 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2061 regs_ever_live[i++] = 1;
2064 /* This function handles the tracking of elimination offsets around branches.
2066 X is a piece of RTL being scanned.
2068 INSN is the insn that it came from, if any.
2070 INITIAL_P is non-zero if we are to set the offset to be the initial
2071 offset and zero if we are setting the offset of the label to be the
2075 set_label_offsets (x, insn, initial_p)
2080 enum rtx_code code = GET_CODE (x);
2083 struct elim_table *p;
2088 if (LABEL_REF_NONLOCAL_P (x))
2093 /* ... fall through ... */
2096 /* If we know nothing about this label, set the desired offsets. Note
2097 that this sets the offset at a label to be the offset before a label
2098 if we don't know anything about the label. This is not correct for
2099 the label after a BARRIER, but is the best guess we can make. If
2100 we guessed wrong, we will suppress an elimination that might have
2101 been possible had we been able to guess correctly. */
2103 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2105 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2106 offsets_at[CODE_LABEL_NUMBER (x)][i]
2107 = (initial_p ? reg_eliminate[i].initial_offset
2108 : reg_eliminate[i].offset);
2109 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2112 /* Otherwise, if this is the definition of a label and it is
2113 preceded by a BARRIER, set our offsets to the known offset of
2117 && (tem = prev_nonnote_insn (insn)) != 0
2118 && GET_CODE (tem) == BARRIER)
2119 set_offsets_for_label (insn);
2121 /* If neither of the above cases is true, compare each offset
2122 with those previously recorded and suppress any eliminations
2123 where the offsets disagree. */
2125 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2126 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2127 != (initial_p ? reg_eliminate[i].initial_offset
2128 : reg_eliminate[i].offset))
2129 reg_eliminate[i].can_eliminate = 0;
2134 set_label_offsets (PATTERN (insn), insn, initial_p);
2136 /* ... fall through ... */
2140 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2141 and hence must have all eliminations at their initial offsets. */
2142 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2143 if (REG_NOTE_KIND (tem) == REG_LABEL)
2144 set_label_offsets (XEXP (tem, 0), insn, 1);
2150 /* Each of the labels in the parallel or address vector must be
2151 at their initial offsets. We want the first field for PARALLEL
2152 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2154 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2155 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2160 /* We only care about setting PC. If the source is not RETURN,
2161 IF_THEN_ELSE, or a label, disable any eliminations not at
2162 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2163 isn't one of those possibilities. For branches to a label,
2164 call ourselves recursively.
2166 Note that this can disable elimination unnecessarily when we have
2167 a non-local goto since it will look like a non-constant jump to
2168 someplace in the current function. This isn't a significant
2169 problem since such jumps will normally be when all elimination
2170 pairs are back to their initial offsets. */
2172 if (SET_DEST (x) != pc_rtx)
2175 switch (GET_CODE (SET_SRC (x)))
2182 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2186 tem = XEXP (SET_SRC (x), 1);
2187 if (GET_CODE (tem) == LABEL_REF)
2188 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2189 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2192 tem = XEXP (SET_SRC (x), 2);
2193 if (GET_CODE (tem) == LABEL_REF)
2194 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2195 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2203 /* If we reach here, all eliminations must be at their initial
2204 offset because we are doing a jump to a variable address. */
2205 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2206 if (p->offset != p->initial_offset)
2207 p->can_eliminate = 0;
2215 /* Scan X and replace any eliminable registers (such as fp) with a
2216 replacement (such as sp), plus an offset.
2218 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2219 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2220 MEM, we are allowed to replace a sum of a register and the constant zero
2221 with the register, which we cannot do outside a MEM. In addition, we need
2222 to record the fact that a register is referenced outside a MEM.
2224 If INSN is an insn, it is the insn containing X. If we replace a REG
2225 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2226 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2227 the REG is being modified.
2229 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2230 That's used when we eliminate in expressions stored in notes.
2231 This means, do not set ref_outside_mem even if the reference
2234 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2235 replacements done assuming all offsets are at their initial values. If
2236 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2237 encounter, return the actual location so that find_reloads will do
2238 the proper thing. */
2241 eliminate_regs (x, mem_mode, insn)
2243 enum machine_mode mem_mode;
2246 enum rtx_code code = GET_CODE (x);
2247 struct elim_table *ep;
2254 if (! current_function_decl)
2273 /* This is only for the benefit of the debugging backends, which call
2274 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2275 removed after CSE. */
2276 new = eliminate_regs (XEXP (x, 0), 0, insn);
2277 if (GET_CODE (new) == MEM)
2278 return XEXP (new, 0);
2284 /* First handle the case where we encounter a bare register that
2285 is eliminable. Replace it with a PLUS. */
2286 if (regno < FIRST_PSEUDO_REGISTER)
2288 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2290 if (ep->from_rtx == x && ep->can_eliminate)
2291 return plus_constant (ep->to_rtx, ep->previous_offset);
2294 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2295 && reg_equiv_constant[regno]
2296 && ! CONSTANT_P (reg_equiv_constant[regno]))
2297 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2301 /* You might think handling MINUS in a manner similar to PLUS is a
2302 good idea. It is not. It has been tried multiple times and every
2303 time the change has had to have been reverted.
2305 Other parts of reload know a PLUS is special (gen_reload for example)
2306 and require special code to handle code a reloaded PLUS operand.
2308 Also consider backends where the flags register is clobbered by a
2309 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2310 lea instruction comes to mind). If we try to reload a MINUS, we
2311 may kill the flags register that was holding a useful value.
2313 So, please before trying to handle MINUS, consider reload as a
2314 whole instead of this little section as well as the backend issues. */
2316 /* If this is the sum of an eliminable register and a constant, rework
2318 if (GET_CODE (XEXP (x, 0)) == REG
2319 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2320 && CONSTANT_P (XEXP (x, 1)))
2322 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2324 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2326 /* The only time we want to replace a PLUS with a REG (this
2327 occurs when the constant operand of the PLUS is the negative
2328 of the offset) is when we are inside a MEM. We won't want
2329 to do so at other times because that would change the
2330 structure of the insn in a way that reload can't handle.
2331 We special-case the commonest situation in
2332 eliminate_regs_in_insn, so just replace a PLUS with a
2333 PLUS here, unless inside a MEM. */
2334 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2335 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2338 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2339 plus_constant (XEXP (x, 1),
2340 ep->previous_offset));
2343 /* If the register is not eliminable, we are done since the other
2344 operand is a constant. */
2348 /* If this is part of an address, we want to bring any constant to the
2349 outermost PLUS. We will do this by doing register replacement in
2350 our operands and seeing if a constant shows up in one of them.
2352 Note that there is no risk of modifying the structure of the insn,
2353 since we only get called for its operands, thus we are either
2354 modifying the address inside a MEM, or something like an address
2355 operand of a load-address insn. */
2358 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2359 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2361 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2363 /* If one side is a PLUS and the other side is a pseudo that
2364 didn't get a hard register but has a reg_equiv_constant,
2365 we must replace the constant here since it may no longer
2366 be in the position of any operand. */
2367 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2368 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2369 && reg_renumber[REGNO (new1)] < 0
2370 && reg_equiv_constant != 0
2371 && reg_equiv_constant[REGNO (new1)] != 0)
2372 new1 = reg_equiv_constant[REGNO (new1)];
2373 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2374 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2375 && reg_renumber[REGNO (new0)] < 0
2376 && reg_equiv_constant[REGNO (new0)] != 0)
2377 new0 = reg_equiv_constant[REGNO (new0)];
2379 new = form_sum (new0, new1);
2381 /* As above, if we are not inside a MEM we do not want to
2382 turn a PLUS into something else. We might try to do so here
2383 for an addition of 0 if we aren't optimizing. */
2384 if (! mem_mode && GET_CODE (new) != PLUS)
2385 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2393 /* If this is the product of an eliminable register and a
2394 constant, apply the distribute law and move the constant out
2395 so that we have (plus (mult ..) ..). This is needed in order
2396 to keep load-address insns valid. This case is pathological.
2397 We ignore the possibility of overflow here. */
2398 if (GET_CODE (XEXP (x, 0)) == REG
2399 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2400 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2401 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2403 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2406 /* Refs inside notes don't count for this purpose. */
2407 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2408 || GET_CODE (insn) == INSN_LIST)))
2409 ep->ref_outside_mem = 1;
2412 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2413 ep->previous_offset * INTVAL (XEXP (x, 1)));
2416 /* ... fall through ... */
2420 /* See comments before PLUS about handling MINUS. */
2422 case DIV: case UDIV:
2423 case MOD: case UMOD:
2424 case AND: case IOR: case XOR:
2425 case ROTATERT: case ROTATE:
2426 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2428 case GE: case GT: case GEU: case GTU:
2429 case LE: case LT: case LEU: case LTU:
2431 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2433 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2435 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2436 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2441 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2444 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2445 if (new != XEXP (x, 0))
2447 /* If this is a REG_DEAD note, it is not valid anymore.
2448 Using the eliminated version could result in creating a
2449 REG_DEAD note for the stack or frame pointer. */
2450 if (GET_MODE (x) == REG_DEAD)
2452 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2455 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2459 /* ... fall through ... */
2462 /* Now do eliminations in the rest of the chain. If this was
2463 an EXPR_LIST, this might result in allocating more memory than is
2464 strictly needed, but it simplifies the code. */
2467 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2468 if (new != XEXP (x, 1))
2469 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2477 case STRICT_LOW_PART:
2479 case SIGN_EXTEND: case ZERO_EXTEND:
2480 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2481 case FLOAT: case FIX:
2482 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2486 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2487 if (new != XEXP (x, 0))
2488 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2492 /* Similar to above processing, but preserve SUBREG_BYTE.
2493 Convert (subreg (mem)) to (mem) if not paradoxical.
2494 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2495 pseudo didn't get a hard reg, we must replace this with the
2496 eliminated version of the memory location because push_reloads
2497 may do the replacement in certain circumstances. */
2498 if (GET_CODE (SUBREG_REG (x)) == REG
2499 && (GET_MODE_SIZE (GET_MODE (x))
2500 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2501 && reg_equiv_memory_loc != 0
2502 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2504 new = SUBREG_REG (x);
2507 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2509 if (new != SUBREG_REG (x))
2511 int x_size = GET_MODE_SIZE (GET_MODE (x));
2512 int new_size = GET_MODE_SIZE (GET_MODE (new));
2514 if (GET_CODE (new) == MEM
2515 && ((x_size < new_size
2516 #ifdef WORD_REGISTER_OPERATIONS
2517 /* On these machines, combine can create rtl of the form
2518 (set (subreg:m1 (reg:m2 R) 0) ...)
2519 where m1 < m2, and expects something interesting to
2520 happen to the entire word. Moreover, it will use the
2521 (reg:m2 R) later, expecting all bits to be preserved.
2522 So if the number of words is the same, preserve the
2523 subreg so that push_reloads can see it. */
2524 && ! ((x_size - 1) / UNITS_PER_WORD
2525 == (new_size -1 ) / UNITS_PER_WORD)
2528 || x_size == new_size)
2531 int offset = SUBREG_BYTE (x);
2532 enum machine_mode mode = GET_MODE (x);
2534 PUT_MODE (new, mode);
2535 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2539 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2545 /* This is only for the benefit of the debugging backends, which call
2546 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2547 removed after CSE. */
2548 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2549 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2551 /* Our only special processing is to pass the mode of the MEM to our
2552 recursive call and copy the flags. While we are here, handle this
2553 case more efficiently. */
2555 replace_equiv_address_nv (x,
2556 eliminate_regs (XEXP (x, 0),
2557 GET_MODE (x), insn));
2560 /* Handle insn_list USE that a call to a pure function may generate. */
2561 new = eliminate_regs (XEXP (x, 0), 0, insn);
2562 if (new != XEXP (x, 0))
2563 return gen_rtx_USE (GET_MODE (x), new);
2575 /* Process each of our operands recursively. If any have changed, make a
2577 fmt = GET_RTX_FORMAT (code);
2578 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2582 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2583 if (new != XEXP (x, i) && ! copied)
2585 rtx new_x = rtx_alloc (code);
2587 (sizeof (*new_x) - sizeof (new_x->fld)
2588 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2594 else if (*fmt == 'E')
2597 for (j = 0; j < XVECLEN (x, i); j++)
2599 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2600 if (new != XVECEXP (x, i, j) && ! copied_vec)
2602 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2606 rtx new_x = rtx_alloc (code);
2608 (sizeof (*new_x) - sizeof (new_x->fld)
2609 + (sizeof (new_x->fld[0])
2610 * GET_RTX_LENGTH (code))));
2614 XVEC (x, i) = new_v;
2617 XVECEXP (x, i, j) = new;
2625 /* Scan rtx X for modifications of elimination target registers. Update
2626 the table of eliminables to reflect the changed state. MEM_MODE is
2627 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2630 elimination_effects (x, mem_mode)
2632 enum machine_mode mem_mode;
2635 enum rtx_code code = GET_CODE (x);
2636 struct elim_table *ep;
2662 /* First handle the case where we encounter a bare register that
2663 is eliminable. Replace it with a PLUS. */
2664 if (regno < FIRST_PSEUDO_REGISTER)
2666 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2668 if (ep->from_rtx == x && ep->can_eliminate)
2671 ep->ref_outside_mem = 1;
2676 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2677 && reg_equiv_constant[regno]
2678 && ! CONSTANT_P (reg_equiv_constant[regno]))
2679 elimination_effects (reg_equiv_constant[regno], mem_mode);
2688 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2689 if (ep->to_rtx == XEXP (x, 0))
2691 int size = GET_MODE_SIZE (mem_mode);
2693 /* If more bytes than MEM_MODE are pushed, account for them. */
2694 #ifdef PUSH_ROUNDING
2695 if (ep->to_rtx == stack_pointer_rtx)
2696 size = PUSH_ROUNDING (size);
2698 if (code == PRE_DEC || code == POST_DEC)
2700 else if (code == PRE_INC || code == POST_INC)
2702 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2703 && GET_CODE (XEXP (x, 1)) == PLUS
2704 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2705 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2706 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2709 /* These two aren't unary operators. */
2710 if (code == POST_MODIFY || code == PRE_MODIFY)
2713 /* Fall through to generic unary operation case. */
2714 case STRICT_LOW_PART:
2716 case SIGN_EXTEND: case ZERO_EXTEND:
2717 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2718 case FLOAT: case FIX:
2719 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2723 elimination_effects (XEXP (x, 0), mem_mode);
2727 if (GET_CODE (SUBREG_REG (x)) == REG
2728 && (GET_MODE_SIZE (GET_MODE (x))
2729 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2730 && reg_equiv_memory_loc != 0
2731 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2734 elimination_effects (SUBREG_REG (x), mem_mode);
2738 /* If using a register that is the source of an eliminate we still
2739 think can be performed, note it cannot be performed since we don't
2740 know how this register is used. */
2741 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2742 if (ep->from_rtx == XEXP (x, 0))
2743 ep->can_eliminate = 0;
2745 elimination_effects (XEXP (x, 0), mem_mode);
2749 /* If clobbering a register that is the replacement register for an
2750 elimination we still think can be performed, note that it cannot
2751 be performed. Otherwise, we need not be concerned about it. */
2752 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2753 if (ep->to_rtx == XEXP (x, 0))
2754 ep->can_eliminate = 0;
2756 elimination_effects (XEXP (x, 0), mem_mode);
2760 /* Check for setting a register that we know about. */
2761 if (GET_CODE (SET_DEST (x)) == REG)
2763 /* See if this is setting the replacement register for an
2766 If DEST is the hard frame pointer, we do nothing because we
2767 assume that all assignments to the frame pointer are for
2768 non-local gotos and are being done at a time when they are valid
2769 and do not disturb anything else. Some machines want to
2770 eliminate a fake argument pointer (or even a fake frame pointer)
2771 with either the real frame or the stack pointer. Assignments to
2772 the hard frame pointer must not prevent this elimination. */
2774 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2776 if (ep->to_rtx == SET_DEST (x)
2777 && SET_DEST (x) != hard_frame_pointer_rtx)
2779 /* If it is being incremented, adjust the offset. Otherwise,
2780 this elimination can't be done. */
2781 rtx src = SET_SRC (x);
2783 if (GET_CODE (src) == PLUS
2784 && XEXP (src, 0) == SET_DEST (x)
2785 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2786 ep->offset -= INTVAL (XEXP (src, 1));
2788 ep->can_eliminate = 0;
2792 elimination_effects (SET_DEST (x), 0);
2793 elimination_effects (SET_SRC (x), 0);
2797 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2800 /* Our only special processing is to pass the mode of the MEM to our
2802 elimination_effects (XEXP (x, 0), GET_MODE (x));
2809 fmt = GET_RTX_FORMAT (code);
2810 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2813 elimination_effects (XEXP (x, i), mem_mode);
2814 else if (*fmt == 'E')
2815 for (j = 0; j < XVECLEN (x, i); j++)
2816 elimination_effects (XVECEXP (x, i, j), mem_mode);
2820 /* Descend through rtx X and verify that no references to eliminable registers
2821 remain. If any do remain, mark the involved register as not
2825 check_eliminable_occurrences (x)
2835 code = GET_CODE (x);
2837 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2839 struct elim_table *ep;
2841 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2842 if (ep->from_rtx == x && ep->can_eliminate)
2843 ep->can_eliminate = 0;
2847 fmt = GET_RTX_FORMAT (code);
2848 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2851 check_eliminable_occurrences (XEXP (x, i));
2852 else if (*fmt == 'E')
2855 for (j = 0; j < XVECLEN (x, i); j++)
2856 check_eliminable_occurrences (XVECEXP (x, i, j));
2861 /* Scan INSN and eliminate all eliminable registers in it.
2863 If REPLACE is nonzero, do the replacement destructively. Also
2864 delete the insn as dead it if it is setting an eliminable register.
2866 If REPLACE is zero, do all our allocations in reload_obstack.
2868 If no eliminations were done and this insn doesn't require any elimination
2869 processing (these are not identical conditions: it might be updating sp,
2870 but not referencing fp; this needs to be seen during reload_as_needed so
2871 that the offset between fp and sp can be taken into consideration), zero
2872 is returned. Otherwise, 1 is returned. */
2875 eliminate_regs_in_insn (insn, replace)
2879 int icode = recog_memoized (insn);
2880 rtx old_body = PATTERN (insn);
2881 int insn_is_asm = asm_noperands (old_body) >= 0;
2882 rtx old_set = single_set (insn);
2886 rtx substed_operand[MAX_RECOG_OPERANDS];
2887 rtx orig_operand[MAX_RECOG_OPERANDS];
2888 struct elim_table *ep;
2890 if (! insn_is_asm && icode < 0)
2892 if (GET_CODE (PATTERN (insn)) == USE
2893 || GET_CODE (PATTERN (insn)) == CLOBBER
2894 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2895 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2896 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2901 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2902 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2904 /* Check for setting an eliminable register. */
2905 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2906 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2908 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2909 /* If this is setting the frame pointer register to the
2910 hardware frame pointer register and this is an elimination
2911 that will be done (tested above), this insn is really
2912 adjusting the frame pointer downward to compensate for
2913 the adjustment done before a nonlocal goto. */
2914 if (ep->from == FRAME_POINTER_REGNUM
2915 && ep->to == HARD_FRAME_POINTER_REGNUM)
2917 rtx src = SET_SRC (old_set);
2918 int offset = 0, ok = 0;
2919 rtx prev_insn, prev_set;
2921 if (src == ep->to_rtx)
2923 else if (GET_CODE (src) == PLUS
2924 && GET_CODE (XEXP (src, 0)) == CONST_INT
2925 && XEXP (src, 1) == ep->to_rtx)
2926 offset = INTVAL (XEXP (src, 0)), ok = 1;
2927 else if (GET_CODE (src) == PLUS
2928 && GET_CODE (XEXP (src, 1)) == CONST_INT
2929 && XEXP (src, 0) == ep->to_rtx)
2930 offset = INTVAL (XEXP (src, 1)), ok = 1;
2931 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2932 && (prev_set = single_set (prev_insn)) != 0
2933 && rtx_equal_p (SET_DEST (prev_set), src))
2935 src = SET_SRC (prev_set);
2936 if (src == ep->to_rtx)
2938 else if (GET_CODE (src) == PLUS
2939 && GET_CODE (XEXP (src, 0)) == CONST_INT
2940 && XEXP (src, 1) == ep->to_rtx)
2941 offset = INTVAL (XEXP (src, 0)), ok = 1;
2942 else if (GET_CODE (src) == PLUS
2943 && GET_CODE (XEXP (src, 1)) == CONST_INT
2944 && XEXP (src, 0) == ep->to_rtx)
2945 offset = INTVAL (XEXP (src, 1)), ok = 1;
2951 = plus_constant (ep->to_rtx, offset - ep->offset);
2953 new_body = old_body;
2956 new_body = copy_insn (old_body);
2957 if (REG_NOTES (insn))
2958 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2960 PATTERN (insn) = new_body;
2961 old_set = single_set (insn);
2963 /* First see if this insn remains valid when we
2964 make the change. If not, keep the INSN_CODE
2965 the same and let reload fit it up. */
2966 validate_change (insn, &SET_SRC (old_set), src, 1);
2967 validate_change (insn, &SET_DEST (old_set),
2969 if (! apply_change_group ())
2971 SET_SRC (old_set) = src;
2972 SET_DEST (old_set) = ep->to_rtx;
2981 /* In this case this insn isn't serving a useful purpose. We
2982 will delete it in reload_as_needed once we know that this
2983 elimination is, in fact, being done.
2985 If REPLACE isn't set, we can't delete this insn, but needn't
2986 process it since it won't be used unless something changes. */
2989 delete_dead_insn (insn);
2997 /* We allow one special case which happens to work on all machines we
2998 currently support: a single set with the source being a PLUS of an
2999 eliminable register and a constant. */
3001 && GET_CODE (SET_DEST (old_set)) == REG
3002 && GET_CODE (SET_SRC (old_set)) == PLUS
3003 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3004 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3005 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3007 rtx reg = XEXP (SET_SRC (old_set), 0);
3008 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3010 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3011 if (ep->from_rtx == reg && ep->can_eliminate)
3013 offset += ep->offset;
3018 /* We assume here that if we need a PARALLEL with
3019 CLOBBERs for this assignment, we can do with the
3020 MATCH_SCRATCHes that add_clobbers allocates.
3021 There's not much we can do if that doesn't work. */
3022 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3026 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3029 rtvec vec = rtvec_alloc (num_clobbers + 1);
3031 vec->elem[0] = PATTERN (insn);
3032 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3033 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3035 if (INSN_CODE (insn) < 0)
3040 new_body = old_body;
3043 new_body = copy_insn (old_body);
3044 if (REG_NOTES (insn))
3045 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3047 PATTERN (insn) = new_body;
3048 old_set = single_set (insn);
3050 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3051 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3054 /* This can't have an effect on elimination offsets, so skip right
3060 /* Determine the effects of this insn on elimination offsets. */
3061 elimination_effects (old_body, 0);
3063 /* Eliminate all eliminable registers occurring in operands that
3064 can be handled by reload. */
3065 extract_insn (insn);
3067 for (i = 0; i < recog_data.n_operands; i++)
3069 orig_operand[i] = recog_data.operand[i];
3070 substed_operand[i] = recog_data.operand[i];
3072 /* For an asm statement, every operand is eliminable. */
3073 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3075 /* Check for setting a register that we know about. */
3076 if (recog_data.operand_type[i] != OP_IN
3077 && GET_CODE (orig_operand[i]) == REG)
3079 /* If we are assigning to a register that can be eliminated, it
3080 must be as part of a PARALLEL, since the code above handles
3081 single SETs. We must indicate that we can no longer
3082 eliminate this reg. */
3083 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3085 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3086 ep->can_eliminate = 0;
3089 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3090 replace ? insn : NULL_RTX);
3091 if (substed_operand[i] != orig_operand[i])
3092 val = any_changes = 1;
3093 /* Terminate the search in check_eliminable_occurrences at
3095 *recog_data.operand_loc[i] = 0;
3097 /* If an output operand changed from a REG to a MEM and INSN is an
3098 insn, write a CLOBBER insn. */
3099 if (recog_data.operand_type[i] != OP_IN
3100 && GET_CODE (orig_operand[i]) == REG
3101 && GET_CODE (substed_operand[i]) == MEM
3103 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3108 for (i = 0; i < recog_data.n_dups; i++)
3109 *recog_data.dup_loc[i]
3110 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3112 /* If any eliminable remain, they aren't eliminable anymore. */
3113 check_eliminable_occurrences (old_body);
3115 /* Substitute the operands; the new values are in the substed_operand
3117 for (i = 0; i < recog_data.n_operands; i++)
3118 *recog_data.operand_loc[i] = substed_operand[i];
3119 for (i = 0; i < recog_data.n_dups; i++)
3120 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3122 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3123 re-recognize the insn. We do this in case we had a simple addition
3124 but now can do this as a load-address. This saves an insn in this
3126 If re-recognition fails, the old insn code number will still be used,
3127 and some register operands may have changed into PLUS expressions.
3128 These will be handled by find_reloads by loading them into a register
3133 /* If we aren't replacing things permanently and we changed something,
3134 make another copy to ensure that all the RTL is new. Otherwise
3135 things can go wrong if find_reload swaps commutative operands
3136 and one is inside RTL that has been copied while the other is not. */
3137 new_body = old_body;
3140 new_body = copy_insn (old_body);
3141 if (REG_NOTES (insn))
3142 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3144 PATTERN (insn) = new_body;
3146 /* If we had a move insn but now we don't, rerecognize it. This will
3147 cause spurious re-recognition if the old move had a PARALLEL since
3148 the new one still will, but we can't call single_set without
3149 having put NEW_BODY into the insn and the re-recognition won't
3150 hurt in this rare case. */
3151 /* ??? Why this huge if statement - why don't we just rerecognize the
3155 && ((GET_CODE (SET_SRC (old_set)) == REG
3156 && (GET_CODE (new_body) != SET
3157 || GET_CODE (SET_SRC (new_body)) != REG))
3158 /* If this was a load from or store to memory, compare
3159 the MEM in recog_data.operand to the one in the insn.
3160 If they are not equal, then rerecognize the insn. */
3162 && ((GET_CODE (SET_SRC (old_set)) == MEM
3163 && SET_SRC (old_set) != recog_data.operand[1])
3164 || (GET_CODE (SET_DEST (old_set)) == MEM
3165 && SET_DEST (old_set) != recog_data.operand[0])))
3166 /* If this was an add insn before, rerecognize. */
3167 || GET_CODE (SET_SRC (old_set)) == PLUS))
3169 int new_icode = recog (PATTERN (insn), insn, 0);
3171 INSN_CODE (insn) = icode;
3175 /* Restore the old body. If there were any changes to it, we made a copy
3176 of it while the changes were still in place, so we'll correctly return
3177 a modified insn below. */
3180 /* Restore the old body. */
3181 for (i = 0; i < recog_data.n_operands; i++)
3182 *recog_data.operand_loc[i] = orig_operand[i];
3183 for (i = 0; i < recog_data.n_dups; i++)
3184 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3187 /* Update all elimination pairs to reflect the status after the current
3188 insn. The changes we make were determined by the earlier call to
3189 elimination_effects.
3191 We also detect a cases where register elimination cannot be done,
3192 namely, if a register would be both changed and referenced outside a MEM
3193 in the resulting insn since such an insn is often undefined and, even if
3194 not, we cannot know what meaning will be given to it. Note that it is
3195 valid to have a register used in an address in an insn that changes it
3196 (presumably with a pre- or post-increment or decrement).
3198 If anything changes, return nonzero. */
3200 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3202 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3203 ep->can_eliminate = 0;
3205 ep->ref_outside_mem = 0;
3207 if (ep->previous_offset != ep->offset)
3212 /* If we changed something, perform elimination in REG_NOTES. This is
3213 needed even when REPLACE is zero because a REG_DEAD note might refer
3214 to a register that we eliminate and could cause a different number
3215 of spill registers to be needed in the final reload pass than in
3217 if (val && REG_NOTES (insn) != 0)
3218 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3223 /* Loop through all elimination pairs.
3224 Recalculate the number not at initial offset.
3226 Compute the maximum offset (minimum offset if the stack does not
3227 grow downward) for each elimination pair. */
3230 update_eliminable_offsets ()
3232 struct elim_table *ep;
3234 num_not_at_initial_offset = 0;
3235 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3237 ep->previous_offset = ep->offset;
3238 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3239 num_not_at_initial_offset++;
3243 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3244 replacement we currently believe is valid, mark it as not eliminable if X
3245 modifies DEST in any way other than by adding a constant integer to it.
3247 If DEST is the frame pointer, we do nothing because we assume that
3248 all assignments to the hard frame pointer are nonlocal gotos and are being
3249 done at a time when they are valid and do not disturb anything else.
3250 Some machines want to eliminate a fake argument pointer with either the
3251 frame or stack pointer. Assignments to the hard frame pointer must not
3252 prevent this elimination.
3254 Called via note_stores from reload before starting its passes to scan
3255 the insns of the function. */
3258 mark_not_eliminable (dest, x, data)
3261 void *data ATTRIBUTE_UNUSED;
3263 register unsigned int i;
3265 /* A SUBREG of a hard register here is just changing its mode. We should
3266 not see a SUBREG of an eliminable hard register, but check just in
3268 if (GET_CODE (dest) == SUBREG)
3269 dest = SUBREG_REG (dest);
3271 if (dest == hard_frame_pointer_rtx)
3274 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3275 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3276 && (GET_CODE (x) != SET
3277 || GET_CODE (SET_SRC (x)) != PLUS
3278 || XEXP (SET_SRC (x), 0) != dest
3279 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3281 reg_eliminate[i].can_eliminate_previous
3282 = reg_eliminate[i].can_eliminate = 0;
3287 /* Verify that the initial elimination offsets did not change since the
3288 last call to set_initial_elim_offsets. This is used to catch cases
3289 where something illegal happened during reload_as_needed that could
3290 cause incorrect code to be generated if we did not check for it. */
3293 verify_initial_elim_offsets ()
3297 #ifdef ELIMINABLE_REGS
3298 struct elim_table *ep;
3300 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3302 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3303 if (t != ep->initial_offset)
3307 INITIAL_FRAME_POINTER_OFFSET (t);
3308 if (t != reg_eliminate[0].initial_offset)
3313 /* Reset all offsets on eliminable registers to their initial values. */
3316 set_initial_elim_offsets ()
3318 struct elim_table *ep = reg_eliminate;
3320 #ifdef ELIMINABLE_REGS
3321 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3323 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3324 ep->previous_offset = ep->offset = ep->initial_offset;
3327 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3328 ep->previous_offset = ep->offset = ep->initial_offset;
3331 num_not_at_initial_offset = 0;
3334 /* Initialize the known label offsets.
3335 Set a known offset for each forced label to be at the initial offset
3336 of each elimination. We do this because we assume that all
3337 computed jumps occur from a location where each elimination is
3338 at its initial offset.
3339 For all other labels, show that we don't know the offsets. */
3342 set_initial_label_offsets ()
3345 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3347 for (x = forced_labels; x; x = XEXP (x, 1))
3349 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3352 /* Set all elimination offsets to the known values for the code label given
3356 set_offsets_for_label (insn)
3360 int label_nr = CODE_LABEL_NUMBER (insn);
3361 struct elim_table *ep;
3363 num_not_at_initial_offset = 0;
3364 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3366 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3367 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3368 num_not_at_initial_offset++;
3372 /* See if anything that happened changes which eliminations are valid.
3373 For example, on the Sparc, whether or not the frame pointer can
3374 be eliminated can depend on what registers have been used. We need
3375 not check some conditions again (such as flag_omit_frame_pointer)
3376 since they can't have changed. */
3379 update_eliminables (pset)
3382 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3383 int previous_frame_pointer_needed = frame_pointer_needed;
3385 struct elim_table *ep;
3387 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3388 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3389 #ifdef ELIMINABLE_REGS
3390 || ! CAN_ELIMINATE (ep->from, ep->to)
3393 ep->can_eliminate = 0;
3395 /* Look for the case where we have discovered that we can't replace
3396 register A with register B and that means that we will now be
3397 trying to replace register A with register C. This means we can
3398 no longer replace register C with register B and we need to disable
3399 such an elimination, if it exists. This occurs often with A == ap,
3400 B == sp, and C == fp. */
3402 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3404 struct elim_table *op;
3405 register int new_to = -1;
3407 if (! ep->can_eliminate && ep->can_eliminate_previous)
3409 /* Find the current elimination for ep->from, if there is a
3411 for (op = reg_eliminate;
3412 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3413 if (op->from == ep->from && op->can_eliminate)
3419 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3421 for (op = reg_eliminate;
3422 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3423 if (op->from == new_to && op->to == ep->to)
3424 op->can_eliminate = 0;
3428 /* See if any registers that we thought we could eliminate the previous
3429 time are no longer eliminable. If so, something has changed and we
3430 must spill the register. Also, recompute the number of eliminable
3431 registers and see if the frame pointer is needed; it is if there is
3432 no elimination of the frame pointer that we can perform. */
3434 frame_pointer_needed = 1;
3435 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3437 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3438 && ep->to != HARD_FRAME_POINTER_REGNUM)
3439 frame_pointer_needed = 0;
3441 if (! ep->can_eliminate && ep->can_eliminate_previous)
3443 ep->can_eliminate_previous = 0;
3444 SET_HARD_REG_BIT (*pset, ep->from);
3449 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3450 /* If we didn't need a frame pointer last time, but we do now, spill
3451 the hard frame pointer. */
3452 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3453 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3457 /* Initialize the table of registers to eliminate. */
3462 struct elim_table *ep;
3463 #ifdef ELIMINABLE_REGS
3464 struct elim_table_1 *ep1;
3468 reg_eliminate = (struct elim_table *)
3469 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3471 /* Does this function require a frame pointer? */
3473 frame_pointer_needed = (! flag_omit_frame_pointer
3474 #ifdef EXIT_IGNORE_STACK
3475 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3476 and restore sp for alloca. So we can't eliminate
3477 the frame pointer in that case. At some point,
3478 we should improve this by emitting the
3479 sp-adjusting insns for this case. */
3480 || (current_function_calls_alloca
3481 && EXIT_IGNORE_STACK)
3483 || FRAME_POINTER_REQUIRED);
3487 #ifdef ELIMINABLE_REGS
3488 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3489 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3491 ep->from = ep1->from;
3493 ep->can_eliminate = ep->can_eliminate_previous
3494 = (CAN_ELIMINATE (ep->from, ep->to)
3495 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3498 reg_eliminate[0].from = reg_eliminate_1[0].from;
3499 reg_eliminate[0].to = reg_eliminate_1[0].to;
3500 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3501 = ! frame_pointer_needed;
3504 /* Count the number of eliminable registers and build the FROM and TO
3505 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3506 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3507 We depend on this. */
3508 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3510 num_eliminable += ep->can_eliminate;
3511 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3512 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3516 /* Kick all pseudos out of hard register REGNO.
3518 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3519 because we found we can't eliminate some register. In the case, no pseudos
3520 are allowed to be in the register, even if they are only in a block that
3521 doesn't require spill registers, unlike the case when we are spilling this
3522 hard reg to produce another spill register.
3524 Return nonzero if any pseudos needed to be kicked out. */
3527 spill_hard_reg (regno, cant_eliminate)
3535 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3536 regs_ever_live[regno] = 1;
3539 /* Spill every pseudo reg that was allocated to this reg
3540 or to something that overlaps this reg. */
3542 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3543 if (reg_renumber[i] >= 0
3544 && (unsigned int) reg_renumber[i] <= regno
3545 && ((unsigned int) reg_renumber[i]
3546 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3547 PSEUDO_REGNO_MODE (i))
3549 SET_REGNO_REG_SET (&spilled_pseudos, i);
3552 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3553 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3556 ior_hard_reg_set (set1, set2)
3557 HARD_REG_SET *set1, *set2;
3559 IOR_HARD_REG_SET (*set1, *set2);
3562 /* After find_reload_regs has been run for all insn that need reloads,
3563 and/or spill_hard_regs was called, this function is used to actually
3564 spill pseudo registers and try to reallocate them. It also sets up the
3565 spill_regs array for use by choose_reload_regs. */
3568 finish_spills (global)
3571 struct insn_chain *chain;
3572 int something_changed = 0;
3575 /* Build the spill_regs array for the function. */
3576 /* If there are some registers still to eliminate and one of the spill regs
3577 wasn't ever used before, additional stack space may have to be
3578 allocated to store this register. Thus, we may have changed the offset
3579 between the stack and frame pointers, so mark that something has changed.
3581 One might think that we need only set VAL to 1 if this is a call-used
3582 register. However, the set of registers that must be saved by the
3583 prologue is not identical to the call-used set. For example, the
3584 register used by the call insn for the return PC is a call-used register,
3585 but must be saved by the prologue. */
3588 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3589 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3591 spill_reg_order[i] = n_spills;
3592 spill_regs[n_spills++] = i;
3593 if (num_eliminable && ! regs_ever_live[i])
3594 something_changed = 1;
3595 regs_ever_live[i] = 1;
3598 spill_reg_order[i] = -1;
3600 EXECUTE_IF_SET_IN_REG_SET
3601 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3603 /* Record the current hard register the pseudo is allocated to in
3604 pseudo_previous_regs so we avoid reallocating it to the same
3605 hard reg in a later pass. */
3606 if (reg_renumber[i] < 0)
3609 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3610 /* Mark it as no longer having a hard register home. */
3611 reg_renumber[i] = -1;
3612 /* We will need to scan everything again. */
3613 something_changed = 1;
3616 /* Retry global register allocation if possible. */
3619 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3620 /* For every insn that needs reloads, set the registers used as spill
3621 regs in pseudo_forbidden_regs for every pseudo live across the
3623 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3625 EXECUTE_IF_SET_IN_REG_SET
3626 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3628 ior_hard_reg_set (pseudo_forbidden_regs + i,
3629 &chain->used_spill_regs);
3631 EXECUTE_IF_SET_IN_REG_SET
3632 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3634 ior_hard_reg_set (pseudo_forbidden_regs + i,
3635 &chain->used_spill_regs);
3639 /* Retry allocating the spilled pseudos. For each reg, merge the
3640 various reg sets that indicate which hard regs can't be used,
3641 and call retry_global_alloc.
3642 We change spill_pseudos here to only contain pseudos that did not
3643 get a new hard register. */
3644 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3645 if (reg_old_renumber[i] != reg_renumber[i])
3647 HARD_REG_SET forbidden;
3648 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3649 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3650 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3651 retry_global_alloc (i, forbidden);
3652 if (reg_renumber[i] >= 0)
3653 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3657 /* Fix up the register information in the insn chain.
3658 This involves deleting those of the spilled pseudos which did not get
3659 a new hard register home from the live_{before,after} sets. */
3660 for (chain = reload_insn_chain; chain; chain = chain->next)
3662 HARD_REG_SET used_by_pseudos;
3663 HARD_REG_SET used_by_pseudos2;
3665 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3666 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3668 /* Mark any unallocated hard regs as available for spills. That
3669 makes inheritance work somewhat better. */
3670 if (chain->need_reload)
3672 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3673 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3674 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3676 /* Save the old value for the sanity test below. */
3677 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3679 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3680 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3681 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3682 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3684 /* Make sure we only enlarge the set. */
3685 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3691 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3692 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3694 int regno = reg_renumber[i];
3695 if (reg_old_renumber[i] == regno)
3698 alter_reg (i, reg_old_renumber[i]);
3699 reg_old_renumber[i] = regno;
3703 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3705 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3706 i, reg_renumber[i]);
3710 return something_changed;
3713 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3714 Also mark any hard registers used to store user variables as
3715 forbidden from being used for spill registers. */
3718 scan_paradoxical_subregs (x)
3722 register const char *fmt;
3723 register enum rtx_code code = GET_CODE (x);
3729 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3730 && REG_USERVAR_P (x))
3731 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3747 if (GET_CODE (SUBREG_REG (x)) == REG
3748 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3749 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3750 = GET_MODE_SIZE (GET_MODE (x));
3757 fmt = GET_RTX_FORMAT (code);
3758 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3761 scan_paradoxical_subregs (XEXP (x, i));
3762 else if (fmt[i] == 'E')
3765 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3766 scan_paradoxical_subregs (XVECEXP (x, i, j));
3771 /* Reload pseudo-registers into hard regs around each insn as needed.
3772 Additional register load insns are output before the insn that needs it
3773 and perhaps store insns after insns that modify the reloaded pseudo reg.
3775 reg_last_reload_reg and reg_reloaded_contents keep track of
3776 which registers are already available in reload registers.
3777 We update these for the reloads that we perform,
3778 as the insns are scanned. */
3781 reload_as_needed (live_known)
3784 struct insn_chain *chain;
3785 #if defined (AUTO_INC_DEC)
3790 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3791 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3792 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3793 reg_has_output_reload = (char *) xmalloc (max_regno);
3794 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3796 set_initial_elim_offsets ();
3798 for (chain = reload_insn_chain; chain; chain = chain->next)
3801 rtx insn = chain->insn;
3802 rtx old_next = NEXT_INSN (insn);
3804 /* If we pass a label, copy the offsets from the label information
3805 into the current offsets of each elimination. */
3806 if (GET_CODE (insn) == CODE_LABEL)
3807 set_offsets_for_label (insn);
3809 else if (INSN_P (insn))
3811 rtx oldpat = PATTERN (insn);
3813 /* If this is a USE and CLOBBER of a MEM, ensure that any
3814 references to eliminable registers have been removed. */
3816 if ((GET_CODE (PATTERN (insn)) == USE
3817 || GET_CODE (PATTERN (insn)) == CLOBBER)
3818 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3819 XEXP (XEXP (PATTERN (insn), 0), 0)
3820 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3821 GET_MODE (XEXP (PATTERN (insn), 0)),
3824 /* If we need to do register elimination processing, do so.
3825 This might delete the insn, in which case we are done. */
3826 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3828 eliminate_regs_in_insn (insn, 1);
3829 if (GET_CODE (insn) == NOTE)
3831 update_eliminable_offsets ();
3836 /* If need_elim is nonzero but need_reload is zero, one might think
3837 that we could simply set n_reloads to 0. However, find_reloads
3838 could have done some manipulation of the insn (such as swapping
3839 commutative operands), and these manipulations are lost during
3840 the first pass for every insn that needs register elimination.
3841 So the actions of find_reloads must be redone here. */
3843 if (! chain->need_elim && ! chain->need_reload
3844 && ! chain->need_operand_change)
3846 /* First find the pseudo regs that must be reloaded for this insn.
3847 This info is returned in the tables reload_... (see reload.h).
3848 Also modify the body of INSN by substituting RELOAD
3849 rtx's for those pseudo regs. */
3852 memset (reg_has_output_reload, 0, max_regno);
3853 CLEAR_HARD_REG_SET (reg_is_output_reload);
3855 find_reloads (insn, 1, spill_indirect_levels, live_known,
3861 rtx next = NEXT_INSN (insn);
3864 prev = PREV_INSN (insn);
3866 /* Now compute which reload regs to reload them into. Perhaps
3867 reusing reload regs from previous insns, or else output
3868 load insns to reload them. Maybe output store insns too.
3869 Record the choices of reload reg in reload_reg_rtx. */
3870 choose_reload_regs (chain);
3872 /* Merge any reloads that we didn't combine for fear of
3873 increasing the number of spill registers needed but now
3874 discover can be safely merged. */
3875 if (SMALL_REGISTER_CLASSES)
3876 merge_assigned_reloads (insn);
3878 /* Generate the insns to reload operands into or out of
3879 their reload regs. */
3880 emit_reload_insns (chain);
3882 /* Substitute the chosen reload regs from reload_reg_rtx
3883 into the insn's body (or perhaps into the bodies of other
3884 load and store insn that we just made for reloading
3885 and that we moved the structure into). */
3886 subst_reloads (insn);
3888 /* If this was an ASM, make sure that all the reload insns
3889 we have generated are valid. If not, give an error
3892 if (asm_noperands (PATTERN (insn)) >= 0)
3893 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3894 if (p != insn && INSN_P (p)
3895 && (recog_memoized (p) < 0
3896 || (extract_insn (p), ! constrain_operands (1))))
3898 error_for_asm (insn,
3899 "`asm' operand requires impossible reload");
3904 if (num_eliminable && chain->need_elim)
3905 update_eliminable_offsets ();
3907 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3908 is no longer validly lying around to save a future reload.
3909 Note that this does not detect pseudos that were reloaded
3910 for this insn in order to be stored in
3911 (obeying register constraints). That is correct; such reload
3912 registers ARE still valid. */
3913 note_stores (oldpat, forget_old_reloads_1, NULL);
3915 /* There may have been CLOBBER insns placed after INSN. So scan
3916 between INSN and NEXT and use them to forget old reloads. */
3917 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3918 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3919 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3922 /* Likewise for regs altered by auto-increment in this insn.
3923 REG_INC notes have been changed by reloading:
3924 find_reloads_address_1 records substitutions for them,
3925 which have been performed by subst_reloads above. */
3926 for (i = n_reloads - 1; i >= 0; i--)
3928 rtx in_reg = rld[i].in_reg;
3931 enum rtx_code code = GET_CODE (in_reg);
3932 /* PRE_INC / PRE_DEC will have the reload register ending up
3933 with the same value as the stack slot, but that doesn't
3934 hold true for POST_INC / POST_DEC. Either we have to
3935 convert the memory access to a true POST_INC / POST_DEC,
3936 or we can't use the reload register for inheritance. */
3937 if ((code == POST_INC || code == POST_DEC)
3938 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3939 REGNO (rld[i].reg_rtx))
3940 /* Make sure it is the inc/dec pseudo, and not
3941 some other (e.g. output operand) pseudo. */
3942 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3943 == REGNO (XEXP (in_reg, 0))))
3946 rtx reload_reg = rld[i].reg_rtx;
3947 enum machine_mode mode = GET_MODE (reload_reg);
3951 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3953 /* We really want to ignore REG_INC notes here, so
3954 use PATTERN (p) as argument to reg_set_p . */
3955 if (reg_set_p (reload_reg, PATTERN (p)))
3957 n = count_occurrences (PATTERN (p), reload_reg, 0);
3962 n = validate_replace_rtx (reload_reg,
3963 gen_rtx (code, mode,
3967 /* We must also verify that the constraints
3968 are met after the replacement. */
3971 n = constrain_operands (1);
3975 /* If the constraints were not met, then
3976 undo the replacement. */
3979 validate_replace_rtx (gen_rtx (code, mode,
3991 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3993 /* Mark this as having an output reload so that the
3994 REG_INC processing code below won't invalidate
3995 the reload for inheritance. */
3996 SET_HARD_REG_BIT (reg_is_output_reload,
3997 REGNO (reload_reg));
3998 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4001 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4004 else if ((code == PRE_INC || code == PRE_DEC)
4005 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4006 REGNO (rld[i].reg_rtx))
4007 /* Make sure it is the inc/dec pseudo, and not
4008 some other (e.g. output operand) pseudo. */
4009 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4010 == REGNO (XEXP (in_reg, 0))))
4012 SET_HARD_REG_BIT (reg_is_output_reload,
4013 REGNO (rld[i].reg_rtx));
4014 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4018 /* If a pseudo that got a hard register is auto-incremented,
4019 we must purge records of copying it into pseudos without
4021 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4022 if (REG_NOTE_KIND (x) == REG_INC)
4024 /* See if this pseudo reg was reloaded in this insn.
4025 If so, its last-reload info is still valid
4026 because it is based on this insn's reload. */
4027 for (i = 0; i < n_reloads; i++)
4028 if (rld[i].out == XEXP (x, 0))
4032 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4036 /* A reload reg's contents are unknown after a label. */
4037 if (GET_CODE (insn) == CODE_LABEL)
4038 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4040 /* Don't assume a reload reg is still good after a call insn
4041 if it is a call-used reg. */
4042 else if (GET_CODE (insn) == CALL_INSN)
4043 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4047 free (reg_last_reload_reg);
4048 free (reg_has_output_reload);
4051 /* Discard all record of any value reloaded from X,
4052 or reloaded in X from someplace else;
4053 unless X is an output reload reg of the current insn.
4055 X may be a hard reg (the reload reg)
4056 or it may be a pseudo reg that was reloaded from. */
4059 forget_old_reloads_1 (x, ignored, data)
4061 rtx ignored ATTRIBUTE_UNUSED;
4062 void *data ATTRIBUTE_UNUSED;
4068 /* note_stores does give us subregs of hard regs,
4069 subreg_regno_offset will abort if it is not a hard reg. */
4070 while (GET_CODE (x) == SUBREG)
4072 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4073 GET_MODE (SUBREG_REG (x)),
4079 if (GET_CODE (x) != REG)
4082 regno = REGNO (x) + offset;
4084 if (regno >= FIRST_PSEUDO_REGISTER)
4090 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4091 /* Storing into a spilled-reg invalidates its contents.
4092 This can happen if a block-local pseudo is allocated to that reg
4093 and it wasn't spilled because this block's total need is 0.
4094 Then some insn might have an optional reload and use this reg. */
4095 for (i = 0; i < nr; i++)
4096 /* But don't do this if the reg actually serves as an output
4097 reload reg in the current instruction. */
4099 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4101 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4102 spill_reg_store[regno + i] = 0;
4106 /* Since value of X has changed,
4107 forget any value previously copied from it. */
4110 /* But don't forget a copy if this is the output reload
4111 that establishes the copy's validity. */
4112 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4113 reg_last_reload_reg[regno + nr] = 0;
4116 /* The following HARD_REG_SETs indicate when each hard register is
4117 used for a reload of various parts of the current insn. */
4119 /* If reg is unavailable for all reloads. */
4120 static HARD_REG_SET reload_reg_unavailable;
4121 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4122 static HARD_REG_SET reload_reg_used;
4123 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4124 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4125 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4126 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4127 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4128 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4129 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4130 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4131 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4132 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4133 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4134 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4135 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4136 static HARD_REG_SET reload_reg_used_in_op_addr;
4137 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4138 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4139 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4140 static HARD_REG_SET reload_reg_used_in_insn;
4141 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4142 static HARD_REG_SET reload_reg_used_in_other_addr;
4144 /* If reg is in use as a reload reg for any sort of reload. */
4145 static HARD_REG_SET reload_reg_used_at_all;
4147 /* If reg is use as an inherited reload. We just mark the first register
4149 static HARD_REG_SET reload_reg_used_for_inherit;
4151 /* Records which hard regs are used in any way, either as explicit use or
4152 by being allocated to a pseudo during any point of the current insn. */
4153 static HARD_REG_SET reg_used_in_insn;
4155 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4156 TYPE. MODE is used to indicate how many consecutive regs are
4160 mark_reload_reg_in_use (regno, opnum, type, mode)
4163 enum reload_type type;
4164 enum machine_mode mode;
4166 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4169 for (i = regno; i < nregs + regno; i++)
4174 SET_HARD_REG_BIT (reload_reg_used, i);
4177 case RELOAD_FOR_INPUT_ADDRESS:
4178 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4181 case RELOAD_FOR_INPADDR_ADDRESS:
4182 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4185 case RELOAD_FOR_OUTPUT_ADDRESS:
4186 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4189 case RELOAD_FOR_OUTADDR_ADDRESS:
4190 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4193 case RELOAD_FOR_OPERAND_ADDRESS:
4194 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4197 case RELOAD_FOR_OPADDR_ADDR:
4198 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4201 case RELOAD_FOR_OTHER_ADDRESS:
4202 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4205 case RELOAD_FOR_INPUT:
4206 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4209 case RELOAD_FOR_OUTPUT:
4210 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4213 case RELOAD_FOR_INSN:
4214 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4218 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4222 /* Similarly, but show REGNO is no longer in use for a reload. */
4225 clear_reload_reg_in_use (regno, opnum, type, mode)
4228 enum reload_type type;
4229 enum machine_mode mode;
4231 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4232 unsigned int start_regno, end_regno, r;
4234 /* A complication is that for some reload types, inheritance might
4235 allow multiple reloads of the same types to share a reload register.
4236 We set check_opnum if we have to check only reloads with the same
4237 operand number, and check_any if we have to check all reloads. */
4238 int check_opnum = 0;
4240 HARD_REG_SET *used_in_set;
4245 used_in_set = &reload_reg_used;
4248 case RELOAD_FOR_INPUT_ADDRESS:
4249 used_in_set = &reload_reg_used_in_input_addr[opnum];
4252 case RELOAD_FOR_INPADDR_ADDRESS:
4254 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4257 case RELOAD_FOR_OUTPUT_ADDRESS:
4258 used_in_set = &reload_reg_used_in_output_addr[opnum];
4261 case RELOAD_FOR_OUTADDR_ADDRESS:
4263 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4266 case RELOAD_FOR_OPERAND_ADDRESS:
4267 used_in_set = &reload_reg_used_in_op_addr;
4270 case RELOAD_FOR_OPADDR_ADDR:
4272 used_in_set = &reload_reg_used_in_op_addr_reload;
4275 case RELOAD_FOR_OTHER_ADDRESS:
4276 used_in_set = &reload_reg_used_in_other_addr;
4280 case RELOAD_FOR_INPUT:
4281 used_in_set = &reload_reg_used_in_input[opnum];
4284 case RELOAD_FOR_OUTPUT:
4285 used_in_set = &reload_reg_used_in_output[opnum];
4288 case RELOAD_FOR_INSN:
4289 used_in_set = &reload_reg_used_in_insn;
4294 /* We resolve conflicts with remaining reloads of the same type by
4295 excluding the intervals of of reload registers by them from the
4296 interval of freed reload registers. Since we only keep track of
4297 one set of interval bounds, we might have to exclude somewhat
4298 more then what would be necessary if we used a HARD_REG_SET here.
4299 But this should only happen very infrequently, so there should
4300 be no reason to worry about it. */
4302 start_regno = regno;
4303 end_regno = regno + nregs;
4304 if (check_opnum || check_any)
4306 for (i = n_reloads - 1; i >= 0; i--)
4308 if (rld[i].when_needed == type
4309 && (check_any || rld[i].opnum == opnum)
4312 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4313 unsigned int conflict_end
4315 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4317 /* If there is an overlap with the first to-be-freed register,
4318 adjust the interval start. */
4319 if (conflict_start <= start_regno && conflict_end > start_regno)
4320 start_regno = conflict_end;
4321 /* Otherwise, if there is a conflict with one of the other
4322 to-be-freed registers, adjust the interval end. */
4323 if (conflict_start > start_regno && conflict_start < end_regno)
4324 end_regno = conflict_start;
4329 for (r = start_regno; r < end_regno; r++)
4330 CLEAR_HARD_REG_BIT (*used_in_set, r);
4333 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4334 specified by OPNUM and TYPE. */
4337 reload_reg_free_p (regno, opnum, type)
4340 enum reload_type type;
4344 /* In use for a RELOAD_OTHER means it's not available for anything. */
4345 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4346 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4352 /* In use for anything means we can't use it for RELOAD_OTHER. */
4353 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4354 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4355 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4358 for (i = 0; i < reload_n_operands; i++)
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4361 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4362 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4363 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4364 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4369 case RELOAD_FOR_INPUT:
4370 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4371 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4374 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4377 /* If it is used for some other input, can't use it. */
4378 for (i = 0; i < reload_n_operands; i++)
4379 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4382 /* If it is used in a later operand's address, can't use it. */
4383 for (i = opnum + 1; i < reload_n_operands; i++)
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4385 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4390 case RELOAD_FOR_INPUT_ADDRESS:
4391 /* Can't use a register if it is used for an input address for this
4392 operand or used as an input in an earlier one. */
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4394 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4397 for (i = 0; i < opnum; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4403 case RELOAD_FOR_INPADDR_ADDRESS:
4404 /* Can't use a register if it is used for an input address
4405 for this operand or used as an input in an earlier
4407 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4410 for (i = 0; i < opnum; i++)
4411 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4416 case RELOAD_FOR_OUTPUT_ADDRESS:
4417 /* Can't use a register if it is used for an output address for this
4418 operand or used as an output in this or a later operand. */
4419 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4422 for (i = opnum; i < reload_n_operands; i++)
4423 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4428 case RELOAD_FOR_OUTADDR_ADDRESS:
4429 /* Can't use a register if it is used for an output address
4430 for this operand or used as an output in this or a
4432 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4435 for (i = opnum; i < reload_n_operands; i++)
4436 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4441 case RELOAD_FOR_OPERAND_ADDRESS:
4442 for (i = 0; i < reload_n_operands; i++)
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4446 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4447 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4449 case RELOAD_FOR_OPADDR_ADDR:
4450 for (i = 0; i < reload_n_operands; i++)
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4454 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4456 case RELOAD_FOR_OUTPUT:
4457 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4458 outputs, or an operand address for this or an earlier output. */
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4462 for (i = 0; i < reload_n_operands; i++)
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4466 for (i = 0; i <= opnum; i++)
4467 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4468 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4473 case RELOAD_FOR_INSN:
4474 for (i = 0; i < reload_n_operands; i++)
4475 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4476 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4479 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4480 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4482 case RELOAD_FOR_OTHER_ADDRESS:
4483 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4488 /* Return 1 if the value in reload reg REGNO, as used by a reload
4489 needed for the part of the insn specified by OPNUM and TYPE,
4490 is still available in REGNO at the end of the insn.
4492 We can assume that the reload reg was already tested for availability
4493 at the time it is needed, and we should not check this again,
4494 in case the reg has already been marked in use. */
4497 reload_reg_reaches_end_p (regno, opnum, type)
4500 enum reload_type type;
4507 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4508 its value must reach the end. */
4511 /* If this use is for part of the insn,
4512 its value reaches if no subsequent part uses the same register.
4513 Just like the above function, don't try to do this with lots
4516 case RELOAD_FOR_OTHER_ADDRESS:
4517 /* Here we check for everything else, since these don't conflict
4518 with anything else and everything comes later. */
4520 for (i = 0; i < reload_n_operands; i++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4523 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4526 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4529 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4530 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4531 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4533 case RELOAD_FOR_INPUT_ADDRESS:
4534 case RELOAD_FOR_INPADDR_ADDRESS:
4535 /* Similar, except that we check only for this and subsequent inputs
4536 and the address of only subsequent inputs and we do not need
4537 to check for RELOAD_OTHER objects since they are known not to
4540 for (i = opnum; i < reload_n_operands; i++)
4541 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4544 for (i = opnum + 1; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4549 for (i = 0; i < reload_n_operands; i++)
4550 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4551 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4552 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4558 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4559 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4560 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4562 case RELOAD_FOR_INPUT:
4563 /* Similar to input address, except we start at the next operand for
4564 both input and input address and we do not check for
4565 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4568 for (i = opnum + 1; i < reload_n_operands; i++)
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4574 /* ... fall through ... */
4576 case RELOAD_FOR_OPERAND_ADDRESS:
4577 /* Check outputs and their addresses. */
4579 for (i = 0; i < reload_n_operands; i++)
4580 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4582 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4585 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4587 case RELOAD_FOR_OPADDR_ADDR:
4588 for (i = 0; i < reload_n_operands; i++)
4589 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4590 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4591 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4594 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4595 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4596 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4598 case RELOAD_FOR_INSN:
4599 /* These conflict with other outputs with RELOAD_OTHER. So
4600 we need only check for output addresses. */
4604 /* ... fall through ... */
4606 case RELOAD_FOR_OUTPUT:
4607 case RELOAD_FOR_OUTPUT_ADDRESS:
4608 case RELOAD_FOR_OUTADDR_ADDRESS:
4609 /* We already know these can't conflict with a later output. So the
4610 only thing to check are later output addresses. */
4611 for (i = opnum + 1; i < reload_n_operands; i++)
4612 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4613 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4622 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4625 This function uses the same algorithm as reload_reg_free_p above. */
4628 reloads_conflict (r1, r2)
4631 enum reload_type r1_type = rld[r1].when_needed;
4632 enum reload_type r2_type = rld[r2].when_needed;
4633 int r1_opnum = rld[r1].opnum;
4634 int r2_opnum = rld[r2].opnum;
4636 /* RELOAD_OTHER conflicts with everything. */
4637 if (r2_type == RELOAD_OTHER)
4640 /* Otherwise, check conflicts differently for each type. */
4644 case RELOAD_FOR_INPUT:
4645 return (r2_type == RELOAD_FOR_INSN
4646 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4647 || r2_type == RELOAD_FOR_OPADDR_ADDR
4648 || r2_type == RELOAD_FOR_INPUT
4649 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4650 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4651 && r2_opnum > r1_opnum));
4653 case RELOAD_FOR_INPUT_ADDRESS:
4654 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4655 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4657 case RELOAD_FOR_INPADDR_ADDRESS:
4658 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4659 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4661 case RELOAD_FOR_OUTPUT_ADDRESS:
4662 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4663 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4665 case RELOAD_FOR_OUTADDR_ADDRESS:
4666 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4667 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4669 case RELOAD_FOR_OPERAND_ADDRESS:
4670 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4671 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4673 case RELOAD_FOR_OPADDR_ADDR:
4674 return (r2_type == RELOAD_FOR_INPUT
4675 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4677 case RELOAD_FOR_OUTPUT:
4678 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4679 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4680 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4681 && r2_opnum <= r1_opnum));
4683 case RELOAD_FOR_INSN:
4684 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4685 || r2_type == RELOAD_FOR_INSN
4686 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4688 case RELOAD_FOR_OTHER_ADDRESS:
4689 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4699 /* Indexed by reload number, 1 if incoming value
4700 inherited from previous insns. */
4701 char reload_inherited[MAX_RELOADS];
4703 /* For an inherited reload, this is the insn the reload was inherited from,
4704 if we know it. Otherwise, this is 0. */
4705 rtx reload_inheritance_insn[MAX_RELOADS];
4707 /* If non-zero, this is a place to get the value of the reload,
4708 rather than using reload_in. */
4709 rtx reload_override_in[MAX_RELOADS];
4711 /* For each reload, the hard register number of the register used,
4712 or -1 if we did not need a register for this reload. */
4713 int reload_spill_index[MAX_RELOADS];
4715 /* Subroutine of free_for_value_p, used to check a single register.
4716 START_REGNO is the starting regno of the full reload register
4717 (possibly comprising multiple hard registers) that we are considering. */
4720 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4721 reloadnum, ignore_address_reloads)
4722 int start_regno, regno;
4724 enum reload_type type;
4727 int ignore_address_reloads;
4730 /* Set if we see an input reload that must not share its reload register
4731 with any new earlyclobber, but might otherwise share the reload
4732 register with an output or input-output reload. */
4733 int check_earlyclobber = 0;
4737 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4740 if (out == const0_rtx)
4746 /* We use some pseudo 'time' value to check if the lifetimes of the
4747 new register use would overlap with the one of a previous reload
4748 that is not read-only or uses a different value.
4749 The 'time' used doesn't have to be linear in any shape or form, just
4751 Some reload types use different 'buckets' for each operand.
4752 So there are MAX_RECOG_OPERANDS different time values for each
4754 We compute TIME1 as the time when the register for the prospective
4755 new reload ceases to be live, and TIME2 for each existing
4756 reload as the time when that the reload register of that reload
4758 Where there is little to be gained by exact lifetime calculations,
4759 we just make conservative assumptions, i.e. a longer lifetime;
4760 this is done in the 'default:' cases. */
4763 case RELOAD_FOR_OTHER_ADDRESS:
4764 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4765 time1 = copy ? 0 : 1;
4768 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4770 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4771 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4772 respectively, to the time values for these, we get distinct time
4773 values. To get distinct time values for each operand, we have to
4774 multiply opnum by at least three. We round that up to four because
4775 multiply by four is often cheaper. */
4776 case RELOAD_FOR_INPADDR_ADDRESS:
4777 time1 = opnum * 4 + 2;
4779 case RELOAD_FOR_INPUT_ADDRESS:
4780 time1 = opnum * 4 + 3;
4782 case RELOAD_FOR_INPUT:
4783 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4784 executes (inclusive). */
4785 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4787 case RELOAD_FOR_OPADDR_ADDR:
4789 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4790 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4792 case RELOAD_FOR_OPERAND_ADDRESS:
4793 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4795 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4797 case RELOAD_FOR_OUTADDR_ADDRESS:
4798 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4800 case RELOAD_FOR_OUTPUT_ADDRESS:
4801 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4804 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4807 for (i = 0; i < n_reloads; i++)
4809 rtx reg = rld[i].reg_rtx;
4810 if (reg && GET_CODE (reg) == REG
4811 && ((unsigned) regno - true_regnum (reg)
4812 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4815 rtx other_input = rld[i].in;
4817 /* If the other reload loads the same input value, that
4818 will not cause a conflict only if it's loading it into
4819 the same register. */
4820 if (true_regnum (reg) != start_regno)
4821 other_input = NULL_RTX;
4822 if (! other_input || ! rtx_equal_p (other_input, value)
4823 || rld[i].out || out)
4826 switch (rld[i].when_needed)
4828 case RELOAD_FOR_OTHER_ADDRESS:
4831 case RELOAD_FOR_INPADDR_ADDRESS:
4832 /* find_reloads makes sure that a
4833 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4834 by at most one - the first -
4835 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4836 address reload is inherited, the address address reload
4837 goes away, so we can ignore this conflict. */
4838 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4839 && ignore_address_reloads
4840 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4841 Then the address address is still needed to store
4842 back the new address. */
4843 && ! rld[reloadnum].out)
4845 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4846 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4848 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4849 && ignore_address_reloads
4850 /* Unless we are reloading an auto_inc expression. */
4851 && ! rld[reloadnum].out)
4853 time2 = rld[i].opnum * 4 + 2;
4855 case RELOAD_FOR_INPUT_ADDRESS:
4856 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4857 && ignore_address_reloads
4858 && ! rld[reloadnum].out)
4860 time2 = rld[i].opnum * 4 + 3;
4862 case RELOAD_FOR_INPUT:
4863 time2 = rld[i].opnum * 4 + 4;
4864 check_earlyclobber = 1;
4866 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4867 == MAX_RECOG_OPERAND * 4 */
4868 case RELOAD_FOR_OPADDR_ADDR:
4869 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4870 && ignore_address_reloads
4871 && ! rld[reloadnum].out)
4873 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4875 case RELOAD_FOR_OPERAND_ADDRESS:
4876 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4877 check_earlyclobber = 1;
4879 case RELOAD_FOR_INSN:
4880 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4882 case RELOAD_FOR_OUTPUT:
4883 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4884 instruction is executed. */
4885 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4887 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4888 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4890 case RELOAD_FOR_OUTADDR_ADDRESS:
4891 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4892 && ignore_address_reloads
4893 && ! rld[reloadnum].out)
4895 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4897 case RELOAD_FOR_OUTPUT_ADDRESS:
4898 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4901 /* If there is no conflict in the input part, handle this
4902 like an output reload. */
4903 if (! rld[i].in || rtx_equal_p (other_input, value))
4905 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4906 /* Earlyclobbered outputs must conflict with inputs. */
4907 if (earlyclobber_operand_p (rld[i].out))
4908 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4913 /* RELOAD_OTHER might be live beyond instruction execution,
4914 but this is not obvious when we set time2 = 1. So check
4915 here if there might be a problem with the new reload
4916 clobbering the register used by the RELOAD_OTHER. */
4924 && (! rld[i].in || rld[i].out
4925 || ! rtx_equal_p (other_input, value)))
4926 || (out && rld[reloadnum].out_reg
4927 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4933 /* Earlyclobbered outputs must conflict with inputs. */
4934 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4940 /* Return 1 if the value in reload reg REGNO, as used by a reload
4941 needed for the part of the insn specified by OPNUM and TYPE,
4942 may be used to load VALUE into it.
4944 MODE is the mode in which the register is used, this is needed to
4945 determine how many hard regs to test.
4947 Other read-only reloads with the same value do not conflict
4948 unless OUT is non-zero and these other reloads have to live while
4949 output reloads live.
4950 If OUT is CONST0_RTX, this is a special case: it means that the
4951 test should not be for using register REGNO as reload register, but
4952 for copying from register REGNO into the reload register.
4954 RELOADNUM is the number of the reload we want to load this value for;
4955 a reload does not conflict with itself.
4957 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4958 reloads that load an address for the very reload we are considering.
4960 The caller has to make sure that there is no conflict with the return
4964 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4965 ignore_address_reloads)
4967 enum machine_mode mode;
4969 enum reload_type type;
4972 int ignore_address_reloads;
4974 int nregs = HARD_REGNO_NREGS (regno, mode);
4976 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4977 value, out, reloadnum,
4978 ignore_address_reloads))
4983 /* Determine whether the reload reg X overlaps any rtx'es used for
4984 overriding inheritance. Return nonzero if so. */
4987 conflicts_with_override (x)
4991 for (i = 0; i < n_reloads; i++)
4992 if (reload_override_in[i]
4993 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4998 /* Give an error message saying we failed to find a reload for INSN,
4999 and clear out reload R. */
5001 failed_reload (insn, r)
5005 if (asm_noperands (PATTERN (insn)) < 0)
5006 /* It's the compiler's fault. */
5007 fatal_insn ("Could not find a spill register", insn);
5009 /* It's the user's fault; the operand's mode and constraint
5010 don't match. Disable this reload so we don't crash in final. */
5011 error_for_asm (insn,
5012 "`asm' operand constraint incompatible with operand size");
5016 rld[r].optional = 1;
5017 rld[r].secondary_p = 1;
5020 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5021 for reload R. If it's valid, get an rtx for it. Return nonzero if
5024 set_reload_reg (i, r)
5028 rtx reg = spill_reg_rtx[i];
5030 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5031 spill_reg_rtx[i] = reg
5032 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5034 regno = true_regnum (reg);
5036 /* Detect when the reload reg can't hold the reload mode.
5037 This used to be one `if', but Sequent compiler can't handle that. */
5038 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5040 enum machine_mode test_mode = VOIDmode;
5042 test_mode = GET_MODE (rld[r].in);
5043 /* If rld[r].in has VOIDmode, it means we will load it
5044 in whatever mode the reload reg has: to wit, rld[r].mode.
5045 We have already tested that for validity. */
5046 /* Aside from that, we need to test that the expressions
5047 to reload from or into have modes which are valid for this
5048 reload register. Otherwise the reload insns would be invalid. */
5049 if (! (rld[r].in != 0 && test_mode != VOIDmode
5050 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5051 if (! (rld[r].out != 0
5052 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5054 /* The reg is OK. */
5057 /* Mark as in use for this insn the reload regs we use
5059 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5060 rld[r].when_needed, rld[r].mode);
5062 rld[r].reg_rtx = reg;
5063 reload_spill_index[r] = spill_regs[i];
5070 /* Find a spill register to use as a reload register for reload R.
5071 LAST_RELOAD is non-zero if this is the last reload for the insn being
5074 Set rld[R].reg_rtx to the register allocated.
5076 We return 1 if successful, or 0 if we couldn't find a spill reg and
5077 we didn't change anything. */
5080 allocate_reload_reg (chain, r, last_reload)
5081 struct insn_chain *chain ATTRIBUTE_UNUSED;
5087 /* If we put this reload ahead, thinking it is a group,
5088 then insist on finding a group. Otherwise we can grab a
5089 reg that some other reload needs.
5090 (That can happen when we have a 68000 DATA_OR_FP_REG
5091 which is a group of data regs or one fp reg.)
5092 We need not be so restrictive if there are no more reloads
5095 ??? Really it would be nicer to have smarter handling
5096 for that kind of reg class, where a problem like this is normal.
5097 Perhaps those classes should be avoided for reloading
5098 by use of more alternatives. */
5100 int force_group = rld[r].nregs > 1 && ! last_reload;
5102 /* If we want a single register and haven't yet found one,
5103 take any reg in the right class and not in use.
5104 If we want a consecutive group, here is where we look for it.
5106 We use two passes so we can first look for reload regs to
5107 reuse, which are already in use for other reloads in this insn,
5108 and only then use additional registers.
5109 I think that maximizing reuse is needed to make sure we don't
5110 run out of reload regs. Suppose we have three reloads, and
5111 reloads A and B can share regs. These need two regs.
5112 Suppose A and B are given different regs.
5113 That leaves none for C. */
5114 for (pass = 0; pass < 2; pass++)
5116 /* I is the index in spill_regs.
5117 We advance it round-robin between insns to use all spill regs
5118 equally, so that inherited reloads have a chance
5119 of leapfrogging each other. */
5123 for (count = 0; count < n_spills; count++)
5125 int class = (int) rld[r].class;
5131 regnum = spill_regs[i];
5133 if ((reload_reg_free_p (regnum, rld[r].opnum,
5136 /* We check reload_reg_used to make sure we
5137 don't clobber the return register. */
5138 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5139 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5140 rld[r].when_needed, rld[r].in,
5142 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5143 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5144 /* Look first for regs to share, then for unshared. But
5145 don't share regs used for inherited reloads; they are
5146 the ones we want to preserve. */
5148 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5150 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5153 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5154 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5155 (on 68000) got us two FP regs. If NR is 1,
5156 we would reject both of them. */
5159 /* If we need only one reg, we have already won. */
5162 /* But reject a single reg if we demand a group. */
5167 /* Otherwise check that as many consecutive regs as we need
5168 are available here. */
5171 int regno = regnum + nr - 1;
5172 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5173 && spill_reg_order[regno] >= 0
5174 && reload_reg_free_p (regno, rld[r].opnum,
5175 rld[r].when_needed)))
5184 /* If we found something on pass 1, omit pass 2. */
5185 if (count < n_spills)
5189 /* We should have found a spill register by now. */
5190 if (count >= n_spills)
5193 /* I is the index in SPILL_REG_RTX of the reload register we are to
5194 allocate. Get an rtx for it and find its register number. */
5196 return set_reload_reg (i, r);
5199 /* Initialize all the tables needed to allocate reload registers.
5200 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5201 is the array we use to restore the reg_rtx field for every reload. */
5204 choose_reload_regs_init (chain, save_reload_reg_rtx)
5205 struct insn_chain *chain;
5206 rtx *save_reload_reg_rtx;
5210 for (i = 0; i < n_reloads; i++)
5211 rld[i].reg_rtx = save_reload_reg_rtx[i];
5213 memset (reload_inherited, 0, MAX_RELOADS);
5214 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5215 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5217 CLEAR_HARD_REG_SET (reload_reg_used);
5218 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5219 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5220 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5221 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5222 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5224 CLEAR_HARD_REG_SET (reg_used_in_insn);
5227 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5228 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5229 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5230 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5231 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5232 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5235 for (i = 0; i < reload_n_operands; i++)
5237 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5239 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5240 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5241 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5242 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5245 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5247 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5249 for (i = 0; i < n_reloads; i++)
5250 /* If we have already decided to use a certain register,
5251 don't use it in another way. */
5253 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5254 rld[i].when_needed, rld[i].mode);
5257 /* Assign hard reg targets for the pseudo-registers we must reload
5258 into hard regs for this insn.
5259 Also output the instructions to copy them in and out of the hard regs.
5261 For machines with register classes, we are responsible for
5262 finding a reload reg in the proper class. */
5265 choose_reload_regs (chain)
5266 struct insn_chain *chain;
5268 rtx insn = chain->insn;
5270 unsigned int max_group_size = 1;
5271 enum reg_class group_class = NO_REGS;
5272 int pass, win, inheritance;
5274 rtx save_reload_reg_rtx[MAX_RELOADS];
5276 /* In order to be certain of getting the registers we need,
5277 we must sort the reloads into order of increasing register class.
5278 Then our grabbing of reload registers will parallel the process
5279 that provided the reload registers.
5281 Also note whether any of the reloads wants a consecutive group of regs.
5282 If so, record the maximum size of the group desired and what
5283 register class contains all the groups needed by this insn. */
5285 for (j = 0; j < n_reloads; j++)
5287 reload_order[j] = j;
5288 reload_spill_index[j] = -1;
5290 if (rld[j].nregs > 1)
5292 max_group_size = MAX (rld[j].nregs, max_group_size);
5294 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5297 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5301 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5303 /* If -O, try first with inheritance, then turning it off.
5304 If not -O, don't do inheritance.
5305 Using inheritance when not optimizing leads to paradoxes
5306 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5307 because one side of the comparison might be inherited. */
5309 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5311 choose_reload_regs_init (chain, save_reload_reg_rtx);
5313 /* Process the reloads in order of preference just found.
5314 Beyond this point, subregs can be found in reload_reg_rtx.
5316 This used to look for an existing reloaded home for all of the
5317 reloads, and only then perform any new reloads. But that could lose
5318 if the reloads were done out of reg-class order because a later
5319 reload with a looser constraint might have an old home in a register
5320 needed by an earlier reload with a tighter constraint.
5322 To solve this, we make two passes over the reloads, in the order
5323 described above. In the first pass we try to inherit a reload
5324 from a previous insn. If there is a later reload that needs a
5325 class that is a proper subset of the class being processed, we must
5326 also allocate a spill register during the first pass.
5328 Then make a second pass over the reloads to allocate any reloads
5329 that haven't been given registers yet. */
5331 for (j = 0; j < n_reloads; j++)
5333 register int r = reload_order[j];
5334 rtx search_equiv = NULL_RTX;
5336 /* Ignore reloads that got marked inoperative. */
5337 if (rld[r].out == 0 && rld[r].in == 0
5338 && ! rld[r].secondary_p)
5341 /* If find_reloads chose to use reload_in or reload_out as a reload
5342 register, we don't need to chose one. Otherwise, try even if it
5343 found one since we might save an insn if we find the value lying
5345 Try also when reload_in is a pseudo without a hard reg. */
5346 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5347 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5348 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5349 && GET_CODE (rld[r].in) != MEM
5350 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5353 #if 0 /* No longer needed for correct operation.
5354 It might give better code, or might not; worth an experiment? */
5355 /* If this is an optional reload, we can't inherit from earlier insns
5356 until we are sure that any non-optional reloads have been allocated.
5357 The following code takes advantage of the fact that optional reloads
5358 are at the end of reload_order. */
5359 if (rld[r].optional != 0)
5360 for (i = 0; i < j; i++)
5361 if ((rld[reload_order[i]].out != 0
5362 || rld[reload_order[i]].in != 0
5363 || rld[reload_order[i]].secondary_p)
5364 && ! rld[reload_order[i]].optional
5365 && rld[reload_order[i]].reg_rtx == 0)
5366 allocate_reload_reg (chain, reload_order[i], 0);
5369 /* First see if this pseudo is already available as reloaded
5370 for a previous insn. We cannot try to inherit for reloads
5371 that are smaller than the maximum number of registers needed
5372 for groups unless the register we would allocate cannot be used
5375 We could check here to see if this is a secondary reload for
5376 an object that is already in a register of the desired class.
5377 This would avoid the need for the secondary reload register.
5378 But this is complex because we can't easily determine what
5379 objects might want to be loaded via this reload. So let a
5380 register be allocated here. In `emit_reload_insns' we suppress
5381 one of the loads in the case described above. */
5386 register int regno = -1;
5387 enum machine_mode mode = VOIDmode;
5391 else if (GET_CODE (rld[r].in) == REG)
5393 regno = REGNO (rld[r].in);
5394 mode = GET_MODE (rld[r].in);
5396 else if (GET_CODE (rld[r].in_reg) == REG)
5398 regno = REGNO (rld[r].in_reg);
5399 mode = GET_MODE (rld[r].in_reg);
5401 else if (GET_CODE (rld[r].in_reg) == SUBREG
5402 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5404 byte = SUBREG_BYTE (rld[r].in_reg);
5405 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5406 if (regno < FIRST_PSEUDO_REGISTER)
5407 regno = subreg_regno (rld[r].in_reg);
5408 mode = GET_MODE (rld[r].in_reg);
5411 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5412 || GET_CODE (rld[r].in_reg) == PRE_DEC
5413 || GET_CODE (rld[r].in_reg) == POST_INC
5414 || GET_CODE (rld[r].in_reg) == POST_DEC)
5415 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5417 regno = REGNO (XEXP (rld[r].in_reg, 0));
5418 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5419 rld[r].out = rld[r].in;
5423 /* This won't work, since REGNO can be a pseudo reg number.
5424 Also, it takes much more hair to keep track of all the things
5425 that can invalidate an inherited reload of part of a pseudoreg. */
5426 else if (GET_CODE (rld[r].in) == SUBREG
5427 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5428 regno = subreg_regno (rld[r].in);
5431 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5433 enum reg_class class = rld[r].class, last_class;
5434 rtx last_reg = reg_last_reload_reg[regno];
5435 enum machine_mode need_mode;
5437 i = REGNO (last_reg);
5438 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5439 last_class = REGNO_REG_CLASS (i);
5445 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5446 GET_MODE_CLASS (mode));
5449 #ifdef CLASS_CANNOT_CHANGE_MODE
5451 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5452 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5454 : (GET_MODE_SIZE (GET_MODE (last_reg))
5455 >= GET_MODE_SIZE (need_mode)))
5457 (GET_MODE_SIZE (GET_MODE (last_reg))
5458 >= GET_MODE_SIZE (need_mode))
5460 && reg_reloaded_contents[i] == regno
5461 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5462 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5463 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5464 /* Even if we can't use this register as a reload
5465 register, we might use it for reload_override_in,
5466 if copying it to the desired class is cheap
5468 || ((REGISTER_MOVE_COST (mode, last_class, class)
5469 < MEMORY_MOVE_COST (mode, class, 1))
5470 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5471 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5475 #ifdef SECONDARY_MEMORY_NEEDED
5476 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5481 && (rld[r].nregs == max_group_size
5482 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5484 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5485 rld[r].when_needed, rld[r].in,
5488 /* If a group is needed, verify that all the subsequent
5489 registers still have their values intact. */
5490 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5493 for (k = 1; k < nr; k++)
5494 if (reg_reloaded_contents[i + k] != regno
5495 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5503 last_reg = (GET_MODE (last_reg) == mode
5504 ? last_reg : gen_rtx_REG (mode, i));
5507 for (k = 0; k < nr; k++)
5508 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5511 /* We found a register that contains the
5512 value we need. If this register is the
5513 same as an `earlyclobber' operand of the
5514 current insn, just mark it as a place to
5515 reload from since we can't use it as the
5516 reload register itself. */
5518 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5519 if (reg_overlap_mentioned_for_reload_p
5520 (reg_last_reload_reg[regno],
5521 reload_earlyclobbers[i1]))
5524 if (i1 != n_earlyclobbers
5525 || ! (free_for_value_p (i, rld[r].mode,
5527 rld[r].when_needed, rld[r].in,
5529 /* Don't use it if we'd clobber a pseudo reg. */
5530 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5532 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5533 /* Don't clobber the frame pointer. */
5534 || (i == HARD_FRAME_POINTER_REGNUM
5536 /* Don't really use the inherited spill reg
5537 if we need it wider than we've got it. */
5538 || (GET_MODE_SIZE (rld[r].mode)
5539 > GET_MODE_SIZE (mode))
5542 /* If find_reloads chose reload_out as reload
5543 register, stay with it - that leaves the
5544 inherited register for subsequent reloads. */
5545 || (rld[r].out && rld[r].reg_rtx
5546 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5548 if (! rld[r].optional)
5550 reload_override_in[r] = last_reg;
5551 reload_inheritance_insn[r]
5552 = reg_reloaded_insn[i];
5558 /* We can use this as a reload reg. */
5559 /* Mark the register as in use for this part of
5561 mark_reload_reg_in_use (i,
5565 rld[r].reg_rtx = last_reg;
5566 reload_inherited[r] = 1;
5567 reload_inheritance_insn[r]
5568 = reg_reloaded_insn[i];
5569 reload_spill_index[r] = i;
5570 for (k = 0; k < nr; k++)
5571 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5579 /* Here's another way to see if the value is already lying around. */
5582 && ! reload_inherited[r]
5584 && (CONSTANT_P (rld[r].in)
5585 || GET_CODE (rld[r].in) == PLUS
5586 || GET_CODE (rld[r].in) == REG
5587 || GET_CODE (rld[r].in) == MEM)
5588 && (rld[r].nregs == max_group_size
5589 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5590 search_equiv = rld[r].in;
5591 /* If this is an output reload from a simple move insn, look
5592 if an equivalence for the input is available. */
5593 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5595 rtx set = single_set (insn);
5598 && rtx_equal_p (rld[r].out, SET_DEST (set))
5599 && CONSTANT_P (SET_SRC (set)))
5600 search_equiv = SET_SRC (set);
5606 = find_equiv_reg (search_equiv, insn, rld[r].class,
5607 -1, NULL, 0, rld[r].mode);
5612 if (GET_CODE (equiv) == REG)
5613 regno = REGNO (equiv);
5614 else if (GET_CODE (equiv) == SUBREG)
5616 /* This must be a SUBREG of a hard register.
5617 Make a new REG since this might be used in an
5618 address and not all machines support SUBREGs
5620 regno = subreg_regno (equiv);
5621 equiv = gen_rtx_REG (rld[r].mode, regno);
5627 /* If we found a spill reg, reject it unless it is free
5628 and of the desired class. */
5630 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5631 && ! free_for_value_p (regno, rld[r].mode,
5632 rld[r].opnum, rld[r].when_needed,
5633 rld[r].in, rld[r].out, r, 1))
5634 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5638 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5641 /* We found a register that contains the value we need.
5642 If this register is the same as an `earlyclobber' operand
5643 of the current insn, just mark it as a place to reload from
5644 since we can't use it as the reload register itself. */
5647 for (i = 0; i < n_earlyclobbers; i++)
5648 if (reg_overlap_mentioned_for_reload_p (equiv,
5649 reload_earlyclobbers[i]))
5651 if (! rld[r].optional)
5652 reload_override_in[r] = equiv;
5657 /* If the equiv register we have found is explicitly clobbered
5658 in the current insn, it depends on the reload type if we
5659 can use it, use it for reload_override_in, or not at all.
5660 In particular, we then can't use EQUIV for a
5661 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5665 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5666 switch (rld[r].when_needed)
5668 case RELOAD_FOR_OTHER_ADDRESS:
5669 case RELOAD_FOR_INPADDR_ADDRESS:
5670 case RELOAD_FOR_INPUT_ADDRESS:
5671 case RELOAD_FOR_OPADDR_ADDR:
5674 case RELOAD_FOR_INPUT:
5675 case RELOAD_FOR_OPERAND_ADDRESS:
5676 if (! rld[r].optional)
5677 reload_override_in[r] = equiv;
5683 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5684 switch (rld[r].when_needed)
5686 case RELOAD_FOR_OTHER_ADDRESS:
5687 case RELOAD_FOR_INPADDR_ADDRESS:
5688 case RELOAD_FOR_INPUT_ADDRESS:
5689 case RELOAD_FOR_OPADDR_ADDR:
5690 case RELOAD_FOR_OPERAND_ADDRESS:
5691 case RELOAD_FOR_INPUT:
5694 if (! rld[r].optional)
5695 reload_override_in[r] = equiv;
5703 /* If we found an equivalent reg, say no code need be generated
5704 to load it, and use it as our reload reg. */
5705 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5707 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5709 rld[r].reg_rtx = equiv;
5710 reload_inherited[r] = 1;
5712 /* If reg_reloaded_valid is not set for this register,
5713 there might be a stale spill_reg_store lying around.
5714 We must clear it, since otherwise emit_reload_insns
5715 might delete the store. */
5716 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5717 spill_reg_store[regno] = NULL_RTX;
5718 /* If any of the hard registers in EQUIV are spill
5719 registers, mark them as in use for this insn. */
5720 for (k = 0; k < nr; k++)
5722 i = spill_reg_order[regno + k];
5725 mark_reload_reg_in_use (regno, rld[r].opnum,
5728 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5735 /* If we found a register to use already, or if this is an optional
5736 reload, we are done. */
5737 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5741 /* No longer needed for correct operation. Might or might
5742 not give better code on the average. Want to experiment? */
5744 /* See if there is a later reload that has a class different from our
5745 class that intersects our class or that requires less register
5746 than our reload. If so, we must allocate a register to this
5747 reload now, since that reload might inherit a previous reload
5748 and take the only available register in our class. Don't do this
5749 for optional reloads since they will force all previous reloads
5750 to be allocated. Also don't do this for reloads that have been
5753 for (i = j + 1; i < n_reloads; i++)
5755 int s = reload_order[i];
5757 if ((rld[s].in == 0 && rld[s].out == 0
5758 && ! rld[s].secondary_p)
5762 if ((rld[s].class != rld[r].class
5763 && reg_classes_intersect_p (rld[r].class,
5765 || rld[s].nregs < rld[r].nregs)
5772 allocate_reload_reg (chain, r, j == n_reloads - 1);
5776 /* Now allocate reload registers for anything non-optional that
5777 didn't get one yet. */
5778 for (j = 0; j < n_reloads; j++)
5780 register int r = reload_order[j];
5782 /* Ignore reloads that got marked inoperative. */
5783 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5786 /* Skip reloads that already have a register allocated or are
5788 if (rld[r].reg_rtx != 0 || rld[r].optional)
5791 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5795 /* If that loop got all the way, we have won. */
5802 /* Loop around and try without any inheritance. */
5807 /* First undo everything done by the failed attempt
5808 to allocate with inheritance. */
5809 choose_reload_regs_init (chain, save_reload_reg_rtx);
5811 /* Some sanity tests to verify that the reloads found in the first
5812 pass are identical to the ones we have now. */
5813 if (chain->n_reloads != n_reloads)
5816 for (i = 0; i < n_reloads; i++)
5818 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5820 if (chain->rld[i].when_needed != rld[i].when_needed)
5822 for (j = 0; j < n_spills; j++)
5823 if (spill_regs[j] == chain->rld[i].regno)
5824 if (! set_reload_reg (j, i))
5825 failed_reload (chain->insn, i);
5829 /* If we thought we could inherit a reload, because it seemed that
5830 nothing else wanted the same reload register earlier in the insn,
5831 verify that assumption, now that all reloads have been assigned.
5832 Likewise for reloads where reload_override_in has been set. */
5834 /* If doing expensive optimizations, do one preliminary pass that doesn't
5835 cancel any inheritance, but removes reloads that have been needed only
5836 for reloads that we know can be inherited. */
5837 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5839 for (j = 0; j < n_reloads; j++)
5841 register int r = reload_order[j];
5843 if (reload_inherited[r] && rld[r].reg_rtx)
5844 check_reg = rld[r].reg_rtx;
5845 else if (reload_override_in[r]
5846 && (GET_CODE (reload_override_in[r]) == REG
5847 || GET_CODE (reload_override_in[r]) == SUBREG))
5848 check_reg = reload_override_in[r];
5851 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5852 rld[r].opnum, rld[r].when_needed, rld[r].in,
5853 (reload_inherited[r]
5854 ? rld[r].out : const0_rtx),
5859 reload_inherited[r] = 0;
5860 reload_override_in[r] = 0;
5862 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5863 reload_override_in, then we do not need its related
5864 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5865 likewise for other reload types.
5866 We handle this by removing a reload when its only replacement
5867 is mentioned in reload_in of the reload we are going to inherit.
5868 A special case are auto_inc expressions; even if the input is
5869 inherited, we still need the address for the output. We can
5870 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5871 If we suceeded removing some reload and we are doing a preliminary
5872 pass just to remove such reloads, make another pass, since the
5873 removal of one reload might allow us to inherit another one. */
5875 && rld[r].out != rld[r].in
5876 && remove_address_replacements (rld[r].in) && pass)
5881 /* Now that reload_override_in is known valid,
5882 actually override reload_in. */
5883 for (j = 0; j < n_reloads; j++)
5884 if (reload_override_in[j])
5885 rld[j].in = reload_override_in[j];
5887 /* If this reload won't be done because it has been cancelled or is
5888 optional and not inherited, clear reload_reg_rtx so other
5889 routines (such as subst_reloads) don't get confused. */
5890 for (j = 0; j < n_reloads; j++)
5891 if (rld[j].reg_rtx != 0
5892 && ((rld[j].optional && ! reload_inherited[j])
5893 || (rld[j].in == 0 && rld[j].out == 0
5894 && ! rld[j].secondary_p)))
5896 int regno = true_regnum (rld[j].reg_rtx);
5898 if (spill_reg_order[regno] >= 0)
5899 clear_reload_reg_in_use (regno, rld[j].opnum,
5900 rld[j].when_needed, rld[j].mode);
5902 reload_spill_index[j] = -1;
5905 /* Record which pseudos and which spill regs have output reloads. */
5906 for (j = 0; j < n_reloads; j++)
5908 register int r = reload_order[j];
5910 i = reload_spill_index[r];
5912 /* I is nonneg if this reload uses a register.
5913 If rld[r].reg_rtx is 0, this is an optional reload
5914 that we opted to ignore. */
5915 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5916 && rld[r].reg_rtx != 0)
5918 register int nregno = REGNO (rld[r].out_reg);
5921 if (nregno < FIRST_PSEUDO_REGISTER)
5922 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5925 reg_has_output_reload[nregno + nr] = 1;
5929 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5931 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5934 if (rld[r].when_needed != RELOAD_OTHER
5935 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5936 && rld[r].when_needed != RELOAD_FOR_INSN)
5942 /* Deallocate the reload register for reload R. This is called from
5943 remove_address_replacements. */
5946 deallocate_reload_reg (r)
5951 if (! rld[r].reg_rtx)
5953 regno = true_regnum (rld[r].reg_rtx);
5955 if (spill_reg_order[regno] >= 0)
5956 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5958 reload_spill_index[r] = -1;
5961 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5962 reloads of the same item for fear that we might not have enough reload
5963 registers. However, normally they will get the same reload register
5964 and hence actually need not be loaded twice.
5966 Here we check for the most common case of this phenomenon: when we have
5967 a number of reloads for the same object, each of which were allocated
5968 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5969 reload, and is not modified in the insn itself. If we find such,
5970 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5971 This will not increase the number of spill registers needed and will
5972 prevent redundant code. */
5975 merge_assigned_reloads (insn)
5980 /* Scan all the reloads looking for ones that only load values and
5981 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5982 assigned and not modified by INSN. */
5984 for (i = 0; i < n_reloads; i++)
5986 int conflicting_input = 0;
5987 int max_input_address_opnum = -1;
5988 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5990 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5991 || rld[i].out != 0 || rld[i].reg_rtx == 0
5992 || reg_set_p (rld[i].reg_rtx, insn))
5995 /* Look at all other reloads. Ensure that the only use of this
5996 reload_reg_rtx is in a reload that just loads the same value
5997 as we do. Note that any secondary reloads must be of the identical
5998 class since the values, modes, and result registers are the
5999 same, so we need not do anything with any secondary reloads. */
6001 for (j = 0; j < n_reloads; j++)
6003 if (i == j || rld[j].reg_rtx == 0
6004 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6008 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6009 && rld[j].opnum > max_input_address_opnum)
6010 max_input_address_opnum = rld[j].opnum;
6012 /* If the reload regs aren't exactly the same (e.g, different modes)
6013 or if the values are different, we can't merge this reload.
6014 But if it is an input reload, we might still merge
6015 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6017 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6018 || rld[j].out != 0 || rld[j].in == 0
6019 || ! rtx_equal_p (rld[i].in, rld[j].in))
6021 if (rld[j].when_needed != RELOAD_FOR_INPUT
6022 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6023 || rld[i].opnum > rld[j].opnum)
6024 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6026 conflicting_input = 1;
6027 if (min_conflicting_input_opnum > rld[j].opnum)
6028 min_conflicting_input_opnum = rld[j].opnum;
6032 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6033 we, in fact, found any matching reloads. */
6036 && max_input_address_opnum <= min_conflicting_input_opnum)
6038 for (j = 0; j < n_reloads; j++)
6039 if (i != j && rld[j].reg_rtx != 0
6040 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6041 && (! conflicting_input
6042 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6043 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6045 rld[i].when_needed = RELOAD_OTHER;
6047 reload_spill_index[j] = -1;
6048 transfer_replacements (i, j);
6051 /* If this is now RELOAD_OTHER, look for any reloads that load
6052 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6053 if they were for inputs, RELOAD_OTHER for outputs. Note that
6054 this test is equivalent to looking for reloads for this operand
6057 if (rld[i].when_needed == RELOAD_OTHER)
6058 for (j = 0; j < n_reloads; j++)
6060 && rld[j].when_needed != RELOAD_OTHER
6061 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6064 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6065 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6066 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6071 /* These arrays are filled by emit_reload_insns and its subroutines. */
6072 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6073 static rtx other_input_address_reload_insns = 0;
6074 static rtx other_input_reload_insns = 0;
6075 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6076 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6077 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6078 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6079 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6080 static rtx operand_reload_insns = 0;
6081 static rtx other_operand_reload_insns = 0;
6082 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6084 /* Values to be put in spill_reg_store are put here first. */
6085 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6086 static HARD_REG_SET reg_reloaded_died;
6088 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6089 has the number J. OLD contains the value to be used as input. */
6092 emit_input_reload_insns (chain, rl, old, j)
6093 struct insn_chain *chain;
6098 rtx insn = chain->insn;
6099 register rtx reloadreg = rl->reg_rtx;
6100 rtx oldequiv_reg = 0;
6103 enum machine_mode mode;
6106 /* Determine the mode to reload in.
6107 This is very tricky because we have three to choose from.
6108 There is the mode the insn operand wants (rl->inmode).
6109 There is the mode of the reload register RELOADREG.
6110 There is the intrinsic mode of the operand, which we could find
6111 by stripping some SUBREGs.
6112 It turns out that RELOADREG's mode is irrelevant:
6113 we can change that arbitrarily.
6115 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6116 then the reload reg may not support QImode moves, so use SImode.
6117 If foo is in memory due to spilling a pseudo reg, this is safe,
6118 because the QImode value is in the least significant part of a
6119 slot big enough for a SImode. If foo is some other sort of
6120 memory reference, then it is impossible to reload this case,
6121 so previous passes had better make sure this never happens.
6123 Then consider a one-word union which has SImode and one of its
6124 members is a float, being fetched as (SUBREG:SF union:SI).
6125 We must fetch that as SFmode because we could be loading into
6126 a float-only register. In this case OLD's mode is correct.
6128 Consider an immediate integer: it has VOIDmode. Here we need
6129 to get a mode from something else.
6131 In some cases, there is a fourth mode, the operand's
6132 containing mode. If the insn specifies a containing mode for
6133 this operand, it overrides all others.
6135 I am not sure whether the algorithm here is always right,
6136 but it does the right things in those cases. */
6138 mode = GET_MODE (old);
6139 if (mode == VOIDmode)
6142 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6143 /* If we need a secondary register for this operation, see if
6144 the value is already in a register in that class. Don't
6145 do this if the secondary register will be used as a scratch
6148 if (rl->secondary_in_reload >= 0
6149 && rl->secondary_in_icode == CODE_FOR_nothing
6152 = find_equiv_reg (old, insn,
6153 rld[rl->secondary_in_reload].class,
6157 /* If reloading from memory, see if there is a register
6158 that already holds the same value. If so, reload from there.
6159 We can pass 0 as the reload_reg_p argument because
6160 any other reload has either already been emitted,
6161 in which case find_equiv_reg will see the reload-insn,
6162 or has yet to be emitted, in which case it doesn't matter
6163 because we will use this equiv reg right away. */
6165 if (oldequiv == 0 && optimize
6166 && (GET_CODE (old) == MEM
6167 || (GET_CODE (old) == REG
6168 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6169 && reg_renumber[REGNO (old)] < 0)))
6170 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6174 unsigned int regno = true_regnum (oldequiv);
6176 /* Don't use OLDEQUIV if any other reload changes it at an
6177 earlier stage of this insn or at this stage. */
6178 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6179 rl->in, const0_rtx, j, 0))
6182 /* If it is no cheaper to copy from OLDEQUIV into the
6183 reload register than it would be to move from memory,
6184 don't use it. Likewise, if we need a secondary register
6188 && ((REGNO_REG_CLASS (regno) != rl->class
6189 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6191 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6192 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6193 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6197 #ifdef SECONDARY_MEMORY_NEEDED
6198 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6206 /* delete_output_reload is only invoked properly if old contains
6207 the original pseudo register. Since this is replaced with a
6208 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6209 find the pseudo in RELOAD_IN_REG. */
6211 && reload_override_in[j]
6212 && GET_CODE (rl->in_reg) == REG)
6219 else if (GET_CODE (oldequiv) == REG)
6220 oldequiv_reg = oldequiv;
6221 else if (GET_CODE (oldequiv) == SUBREG)
6222 oldequiv_reg = SUBREG_REG (oldequiv);
6224 /* If we are reloading from a register that was recently stored in
6225 with an output-reload, see if we can prove there was
6226 actually no need to store the old value in it. */
6228 if (optimize && GET_CODE (oldequiv) == REG
6229 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6230 && spill_reg_store[REGNO (oldequiv)]
6231 && GET_CODE (old) == REG
6232 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6233 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6235 delete_output_reload (insn, j, REGNO (oldequiv));
6237 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6238 then load RELOADREG from OLDEQUIV. Note that we cannot use
6239 gen_lowpart_common since it can do the wrong thing when
6240 RELOADREG has a multi-word mode. Note that RELOADREG
6241 must always be a REG here. */
6243 if (GET_MODE (reloadreg) != mode)
6244 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6245 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6246 oldequiv = SUBREG_REG (oldequiv);
6247 if (GET_MODE (oldequiv) != VOIDmode
6248 && mode != GET_MODE (oldequiv))
6249 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6251 /* Switch to the right place to emit the reload insns. */
6252 switch (rl->when_needed)
6255 where = &other_input_reload_insns;
6257 case RELOAD_FOR_INPUT:
6258 where = &input_reload_insns[rl->opnum];
6260 case RELOAD_FOR_INPUT_ADDRESS:
6261 where = &input_address_reload_insns[rl->opnum];
6263 case RELOAD_FOR_INPADDR_ADDRESS:
6264 where = &inpaddr_address_reload_insns[rl->opnum];
6266 case RELOAD_FOR_OUTPUT_ADDRESS:
6267 where = &output_address_reload_insns[rl->opnum];
6269 case RELOAD_FOR_OUTADDR_ADDRESS:
6270 where = &outaddr_address_reload_insns[rl->opnum];
6272 case RELOAD_FOR_OPERAND_ADDRESS:
6273 where = &operand_reload_insns;
6275 case RELOAD_FOR_OPADDR_ADDR:
6276 where = &other_operand_reload_insns;
6278 case RELOAD_FOR_OTHER_ADDRESS:
6279 where = &other_input_address_reload_insns;
6285 push_to_sequence (*where);
6287 /* Auto-increment addresses must be reloaded in a special way. */
6288 if (rl->out && ! rl->out_reg)
6290 /* We are not going to bother supporting the case where a
6291 incremented register can't be copied directly from
6292 OLDEQUIV since this seems highly unlikely. */
6293 if (rl->secondary_in_reload >= 0)
6296 if (reload_inherited[j])
6297 oldequiv = reloadreg;
6299 old = XEXP (rl->in_reg, 0);
6301 if (optimize && GET_CODE (oldequiv) == REG
6302 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6303 && spill_reg_store[REGNO (oldequiv)]
6304 && GET_CODE (old) == REG
6305 && (dead_or_set_p (insn,
6306 spill_reg_stored_to[REGNO (oldequiv)])
6307 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6309 delete_output_reload (insn, j, REGNO (oldequiv));
6311 /* Prevent normal processing of this reload. */
6313 /* Output a special code sequence for this case. */
6314 new_spill_reg_store[REGNO (reloadreg)]
6315 = inc_for_reload (reloadreg, oldequiv, rl->out,
6319 /* If we are reloading a pseudo-register that was set by the previous
6320 insn, see if we can get rid of that pseudo-register entirely
6321 by redirecting the previous insn into our reload register. */
6323 else if (optimize && GET_CODE (old) == REG
6324 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6325 && dead_or_set_p (insn, old)
6326 /* This is unsafe if some other reload
6327 uses the same reg first. */
6328 && ! conflicts_with_override (reloadreg)
6329 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6330 rl->when_needed, old, rl->out, j, 0))
6332 rtx temp = PREV_INSN (insn);
6333 while (temp && GET_CODE (temp) == NOTE)
6334 temp = PREV_INSN (temp);
6336 && GET_CODE (temp) == INSN
6337 && GET_CODE (PATTERN (temp)) == SET
6338 && SET_DEST (PATTERN (temp)) == old
6339 /* Make sure we can access insn_operand_constraint. */
6340 && asm_noperands (PATTERN (temp)) < 0
6341 /* This is unsafe if prev insn rejects our reload reg. */
6342 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6344 /* This is unsafe if operand occurs more than once in current
6345 insn. Perhaps some occurrences aren't reloaded. */
6346 && count_occurrences (PATTERN (insn), old, 0) == 1
6347 /* Don't risk splitting a matching pair of operands. */
6348 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6350 /* Store into the reload register instead of the pseudo. */
6351 SET_DEST (PATTERN (temp)) = reloadreg;
6353 /* If the previous insn is an output reload, the source is
6354 a reload register, and its spill_reg_store entry will
6355 contain the previous destination. This is now
6357 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6358 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6360 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6361 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6364 /* If these are the only uses of the pseudo reg,
6365 pretend for GDB it lives in the reload reg we used. */
6366 if (REG_N_DEATHS (REGNO (old)) == 1
6367 && REG_N_SETS (REGNO (old)) == 1)
6369 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6370 alter_reg (REGNO (old), -1);
6376 /* We can't do that, so output an insn to load RELOADREG. */
6378 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6379 /* If we have a secondary reload, pick up the secondary register
6380 and icode, if any. If OLDEQUIV and OLD are different or
6381 if this is an in-out reload, recompute whether or not we
6382 still need a secondary register and what the icode should
6383 be. If we still need a secondary register and the class or
6384 icode is different, go back to reloading from OLD if using
6385 OLDEQUIV means that we got the wrong type of register. We
6386 cannot have different class or icode due to an in-out reload
6387 because we don't make such reloads when both the input and
6388 output need secondary reload registers. */
6390 if (! special && rl->secondary_in_reload >= 0)
6392 rtx second_reload_reg = 0;
6393 int secondary_reload = rl->secondary_in_reload;
6394 rtx real_oldequiv = oldequiv;
6397 enum insn_code icode;
6399 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6400 and similarly for OLD.
6401 See comments in get_secondary_reload in reload.c. */
6402 /* If it is a pseudo that cannot be replaced with its
6403 equivalent MEM, we must fall back to reload_in, which
6404 will have all the necessary substitutions registered.
6405 Likewise for a pseudo that can't be replaced with its
6406 equivalent constant.
6408 Take extra care for subregs of such pseudos. Note that
6409 we cannot use reg_equiv_mem in this case because it is
6410 not in the right mode. */
6413 if (GET_CODE (tmp) == SUBREG)
6414 tmp = SUBREG_REG (tmp);
6415 if (GET_CODE (tmp) == REG
6416 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6417 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6418 || reg_equiv_constant[REGNO (tmp)] != 0))
6420 if (! reg_equiv_mem[REGNO (tmp)]
6421 || num_not_at_initial_offset
6422 || GET_CODE (oldequiv) == SUBREG)
6423 real_oldequiv = rl->in;
6425 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6429 if (GET_CODE (tmp) == SUBREG)
6430 tmp = SUBREG_REG (tmp);
6431 if (GET_CODE (tmp) == REG
6432 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6433 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6434 || reg_equiv_constant[REGNO (tmp)] != 0))
6436 if (! reg_equiv_mem[REGNO (tmp)]
6437 || num_not_at_initial_offset
6438 || GET_CODE (old) == SUBREG)
6441 real_old = reg_equiv_mem[REGNO (tmp)];
6444 second_reload_reg = rld[secondary_reload].reg_rtx;
6445 icode = rl->secondary_in_icode;
6447 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6448 || (rl->in != 0 && rl->out != 0))
6450 enum reg_class new_class
6451 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6452 mode, real_oldequiv);
6454 if (new_class == NO_REGS)
6455 second_reload_reg = 0;
6458 enum insn_code new_icode;
6459 enum machine_mode new_mode;
6461 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6462 REGNO (second_reload_reg)))
6463 oldequiv = old, real_oldequiv = real_old;
6466 new_icode = reload_in_optab[(int) mode];
6467 if (new_icode != CODE_FOR_nothing
6468 && ((insn_data[(int) new_icode].operand[0].predicate
6469 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6471 || (insn_data[(int) new_icode].operand[1].predicate
6472 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6473 (real_oldequiv, mode)))))
6474 new_icode = CODE_FOR_nothing;
6476 if (new_icode == CODE_FOR_nothing)
6479 new_mode = insn_data[(int) new_icode].operand[2].mode;
6481 if (GET_MODE (second_reload_reg) != new_mode)
6483 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6485 oldequiv = old, real_oldequiv = real_old;
6488 = gen_rtx_REG (new_mode,
6489 REGNO (second_reload_reg));
6495 /* If we still need a secondary reload register, check
6496 to see if it is being used as a scratch or intermediate
6497 register and generate code appropriately. If we need
6498 a scratch register, use REAL_OLDEQUIV since the form of
6499 the insn may depend on the actual address if it is
6502 if (second_reload_reg)
6504 if (icode != CODE_FOR_nothing)
6506 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6507 second_reload_reg));
6512 /* See if we need a scratch register to load the
6513 intermediate register (a tertiary reload). */
6514 enum insn_code tertiary_icode
6515 = rld[secondary_reload].secondary_in_icode;
6517 if (tertiary_icode != CODE_FOR_nothing)
6519 rtx third_reload_reg
6520 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6522 emit_insn ((GEN_FCN (tertiary_icode)
6523 (second_reload_reg, real_oldequiv,
6524 third_reload_reg)));
6527 gen_reload (second_reload_reg, real_oldequiv,
6531 oldequiv = second_reload_reg;
6537 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6539 rtx real_oldequiv = oldequiv;
6541 if ((GET_CODE (oldequiv) == REG
6542 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6543 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6544 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6545 || (GET_CODE (oldequiv) == SUBREG
6546 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6547 && (REGNO (SUBREG_REG (oldequiv))
6548 >= FIRST_PSEUDO_REGISTER)
6549 && ((reg_equiv_memory_loc
6550 [REGNO (SUBREG_REG (oldequiv))] != 0)
6551 || (reg_equiv_constant
6552 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6553 || (CONSTANT_P (oldequiv)
6554 && PREFERRED_RELOAD_CLASS (oldequiv,
6555 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6556 real_oldequiv = rl->in;
6557 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6561 if (flag_non_call_exceptions)
6562 copy_eh_notes (insn, get_insns ());
6564 /* End this sequence. */
6565 *where = get_insns ();
6568 /* Update reload_override_in so that delete_address_reloads_1
6569 can see the actual register usage. */
6571 reload_override_in[j] = oldequiv;
6574 /* Generate insns to for the output reload RL, which is for the insn described
6575 by CHAIN and has the number J. */
6577 emit_output_reload_insns (chain, rl, j)
6578 struct insn_chain *chain;
6582 rtx reloadreg = rl->reg_rtx;
6583 rtx insn = chain->insn;
6586 enum machine_mode mode = GET_MODE (old);
6589 if (rl->when_needed == RELOAD_OTHER)
6592 push_to_sequence (output_reload_insns[rl->opnum]);
6594 /* Determine the mode to reload in.
6595 See comments above (for input reloading). */
6597 if (mode == VOIDmode)
6599 /* VOIDmode should never happen for an output. */
6600 if (asm_noperands (PATTERN (insn)) < 0)
6601 /* It's the compiler's fault. */
6602 fatal_insn ("VOIDmode on an output", insn);
6603 error_for_asm (insn, "output operand is constant in `asm'");
6604 /* Prevent crash--use something we know is valid. */
6606 old = gen_rtx_REG (mode, REGNO (reloadreg));
6609 if (GET_MODE (reloadreg) != mode)
6610 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6612 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6614 /* If we need two reload regs, set RELOADREG to the intermediate
6615 one, since it will be stored into OLD. We might need a secondary
6616 register only for an input reload, so check again here. */
6618 if (rl->secondary_out_reload >= 0)
6622 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6623 && reg_equiv_mem[REGNO (old)] != 0)
6624 real_old = reg_equiv_mem[REGNO (old)];
6626 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6630 rtx second_reloadreg = reloadreg;
6631 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6633 /* See if RELOADREG is to be used as a scratch register
6634 or as an intermediate register. */
6635 if (rl->secondary_out_icode != CODE_FOR_nothing)
6637 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6638 (real_old, second_reloadreg, reloadreg)));
6643 /* See if we need both a scratch and intermediate reload
6646 int secondary_reload = rl->secondary_out_reload;
6647 enum insn_code tertiary_icode
6648 = rld[secondary_reload].secondary_out_icode;
6650 if (GET_MODE (reloadreg) != mode)
6651 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6653 if (tertiary_icode != CODE_FOR_nothing)
6656 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6659 /* Copy primary reload reg to secondary reload reg.
6660 (Note that these have been swapped above, then
6661 secondary reload reg to OLD using our insn.) */
6663 /* If REAL_OLD is a paradoxical SUBREG, remove it
6664 and try to put the opposite SUBREG on
6666 if (GET_CODE (real_old) == SUBREG
6667 && (GET_MODE_SIZE (GET_MODE (real_old))
6668 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6669 && 0 != (tem = gen_lowpart_common
6670 (GET_MODE (SUBREG_REG (real_old)),
6672 real_old = SUBREG_REG (real_old), reloadreg = tem;
6674 gen_reload (reloadreg, second_reloadreg,
6675 rl->opnum, rl->when_needed);
6676 emit_insn ((GEN_FCN (tertiary_icode)
6677 (real_old, reloadreg, third_reloadreg)));
6682 /* Copy between the reload regs here and then to
6685 gen_reload (reloadreg, second_reloadreg,
6686 rl->opnum, rl->when_needed);
6692 /* Output the last reload insn. */
6697 /* Don't output the last reload if OLD is not the dest of
6698 INSN and is in the src and is clobbered by INSN. */
6699 if (! flag_expensive_optimizations
6700 || GET_CODE (old) != REG
6701 || !(set = single_set (insn))
6702 || rtx_equal_p (old, SET_DEST (set))
6703 || !reg_mentioned_p (old, SET_SRC (set))
6704 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6705 gen_reload (old, reloadreg, rl->opnum,
6709 /* Look at all insns we emitted, just to be safe. */
6710 for (p = get_insns (); p; p = NEXT_INSN (p))
6713 rtx pat = PATTERN (p);
6715 /* If this output reload doesn't come from a spill reg,
6716 clear any memory of reloaded copies of the pseudo reg.
6717 If this output reload comes from a spill reg,
6718 reg_has_output_reload will make this do nothing. */
6719 note_stores (pat, forget_old_reloads_1, NULL);
6721 if (reg_mentioned_p (rl->reg_rtx, pat))
6723 rtx set = single_set (insn);
6724 if (reload_spill_index[j] < 0
6726 && SET_SRC (set) == rl->reg_rtx)
6728 int src = REGNO (SET_SRC (set));
6730 reload_spill_index[j] = src;
6731 SET_HARD_REG_BIT (reg_is_output_reload, src);
6732 if (find_regno_note (insn, REG_DEAD, src))
6733 SET_HARD_REG_BIT (reg_reloaded_died, src);
6735 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6737 int s = rl->secondary_out_reload;
6738 set = single_set (p);
6739 /* If this reload copies only to the secondary reload
6740 register, the secondary reload does the actual
6742 if (s >= 0 && set == NULL_RTX)
6743 /* We can't tell what function the secondary reload
6744 has and where the actual store to the pseudo is
6745 made; leave new_spill_reg_store alone. */
6748 && SET_SRC (set) == rl->reg_rtx
6749 && SET_DEST (set) == rld[s].reg_rtx)
6751 /* Usually the next instruction will be the
6752 secondary reload insn; if we can confirm
6753 that it is, setting new_spill_reg_store to
6754 that insn will allow an extra optimization. */
6755 rtx s_reg = rld[s].reg_rtx;
6756 rtx next = NEXT_INSN (p);
6757 rld[s].out = rl->out;
6758 rld[s].out_reg = rl->out_reg;
6759 set = single_set (next);
6760 if (set && SET_SRC (set) == s_reg
6761 && ! new_spill_reg_store[REGNO (s_reg)])
6763 SET_HARD_REG_BIT (reg_is_output_reload,
6765 new_spill_reg_store[REGNO (s_reg)] = next;
6769 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6774 if (rl->when_needed == RELOAD_OTHER)
6776 emit_insns (other_output_reload_insns[rl->opnum]);
6777 other_output_reload_insns[rl->opnum] = get_insns ();
6780 output_reload_insns[rl->opnum] = get_insns ();
6782 if (flag_non_call_exceptions)
6783 copy_eh_notes (insn, get_insns ());
6788 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6789 and has the number J. */
6791 do_input_reload (chain, rl, j)
6792 struct insn_chain *chain;
6796 int expect_occurrences = 1;
6797 rtx insn = chain->insn;
6798 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6799 ? rl->in_reg : rl->in);
6802 /* AUTO_INC reloads need to be handled even if inherited. We got an
6803 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6804 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6805 && ! rtx_equal_p (rl->reg_rtx, old)
6806 && rl->reg_rtx != 0)
6807 emit_input_reload_insns (chain, rld + j, old, j);
6809 /* When inheriting a wider reload, we have a MEM in rl->in,
6810 e.g. inheriting a SImode output reload for
6811 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6812 if (optimize && reload_inherited[j] && rl->in
6813 && GET_CODE (rl->in) == MEM
6814 && GET_CODE (rl->in_reg) == MEM
6815 && reload_spill_index[j] >= 0
6816 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6819 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6820 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6823 /* If we are reloading a register that was recently stored in with an
6824 output-reload, see if we can prove there was
6825 actually no need to store the old value in it. */
6828 && (reload_inherited[j] || reload_override_in[j])
6830 && GET_CODE (rl->reg_rtx) == REG
6831 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6833 /* There doesn't seem to be any reason to restrict this to pseudos
6834 and doing so loses in the case where we are copying from a
6835 register of the wrong class. */
6836 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6837 >= FIRST_PSEUDO_REGISTER)
6839 /* The insn might have already some references to stackslots
6840 replaced by MEMs, while reload_out_reg still names the
6842 && (dead_or_set_p (insn,
6843 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6844 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6846 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6849 /* Do output reloading for reload RL, which is for the insn described by
6850 CHAIN and has the number J.
6851 ??? At some point we need to support handling output reloads of
6852 JUMP_INSNs or insns that set cc0. */
6854 do_output_reload (chain, rl, j)
6855 struct insn_chain *chain;
6860 rtx insn = chain->insn;
6861 /* If this is an output reload that stores something that is
6862 not loaded in this same reload, see if we can eliminate a previous
6864 rtx pseudo = rl->out_reg;
6867 && GET_CODE (pseudo) == REG
6868 && ! rtx_equal_p (rl->in_reg, pseudo)
6869 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6870 && reg_last_reload_reg[REGNO (pseudo)])
6872 int pseudo_no = REGNO (pseudo);
6873 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6875 /* We don't need to test full validity of last_regno for
6876 inherit here; we only want to know if the store actually
6877 matches the pseudo. */
6878 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6879 && reg_reloaded_contents[last_regno] == pseudo_no
6880 && spill_reg_store[last_regno]
6881 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6882 delete_output_reload (insn, j, last_regno);
6887 || rl->reg_rtx == old
6888 || rl->reg_rtx == 0)
6891 /* An output operand that dies right away does need a reload,
6892 but need not be copied from it. Show the new location in the
6894 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6895 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6897 XEXP (note, 0) = rl->reg_rtx;
6900 /* Likewise for a SUBREG of an operand that dies. */
6901 else if (GET_CODE (old) == SUBREG
6902 && GET_CODE (SUBREG_REG (old)) == REG
6903 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6906 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6910 else if (GET_CODE (old) == SCRATCH)
6911 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6912 but we don't want to make an output reload. */
6915 /* If is a JUMP_INSN, we can't support output reloads yet. */
6916 if (GET_CODE (insn) == JUMP_INSN)
6919 emit_output_reload_insns (chain, rld + j, j);
6922 /* Output insns to reload values in and out of the chosen reload regs. */
6925 emit_reload_insns (chain)
6926 struct insn_chain *chain;
6928 rtx insn = chain->insn;
6932 CLEAR_HARD_REG_SET (reg_reloaded_died);
6934 for (j = 0; j < reload_n_operands; j++)
6935 input_reload_insns[j] = input_address_reload_insns[j]
6936 = inpaddr_address_reload_insns[j]
6937 = output_reload_insns[j] = output_address_reload_insns[j]
6938 = outaddr_address_reload_insns[j]
6939 = other_output_reload_insns[j] = 0;
6940 other_input_address_reload_insns = 0;
6941 other_input_reload_insns = 0;
6942 operand_reload_insns = 0;
6943 other_operand_reload_insns = 0;
6945 /* Dump reloads into the dump file. */
6948 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6949 debug_reload_to_stream (rtl_dump_file);
6952 /* Now output the instructions to copy the data into and out of the
6953 reload registers. Do these in the order that the reloads were reported,
6954 since reloads of base and index registers precede reloads of operands
6955 and the operands may need the base and index registers reloaded. */
6957 for (j = 0; j < n_reloads; j++)
6960 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6961 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6963 do_input_reload (chain, rld + j, j);
6964 do_output_reload (chain, rld + j, j);
6967 /* Now write all the insns we made for reloads in the order expected by
6968 the allocation functions. Prior to the insn being reloaded, we write
6969 the following reloads:
6971 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6973 RELOAD_OTHER reloads.
6975 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6976 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6977 RELOAD_FOR_INPUT reload for the operand.
6979 RELOAD_FOR_OPADDR_ADDRS reloads.
6981 RELOAD_FOR_OPERAND_ADDRESS reloads.
6983 After the insn being reloaded, we write the following:
6985 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6986 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6987 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6988 reloads for the operand. The RELOAD_OTHER output reloads are
6989 output in descending order by reload number. */
6991 emit_insns_before (other_input_address_reload_insns, insn);
6992 emit_insns_before (other_input_reload_insns, insn);
6994 for (j = 0; j < reload_n_operands; j++)
6996 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6997 emit_insns_before (input_address_reload_insns[j], insn);
6998 emit_insns_before (input_reload_insns[j], insn);
7001 emit_insns_before (other_operand_reload_insns, insn);
7002 emit_insns_before (operand_reload_insns, insn);
7004 for (j = 0; j < reload_n_operands; j++)
7006 rtx x = emit_insns_after (outaddr_address_reload_insns[j], insn);
7007 x = emit_insns_after (output_address_reload_insns[j], x);
7008 x = emit_insns_after (output_reload_insns[j], x);
7009 emit_insns_after (other_output_reload_insns[j], x);
7012 /* For all the spill regs newly reloaded in this instruction,
7013 record what they were reloaded from, so subsequent instructions
7014 can inherit the reloads.
7016 Update spill_reg_store for the reloads of this insn.
7017 Copy the elements that were updated in the loop above. */
7019 for (j = 0; j < n_reloads; j++)
7021 register int r = reload_order[j];
7022 register int i = reload_spill_index[r];
7024 /* If this is a non-inherited input reload from a pseudo, we must
7025 clear any memory of a previous store to the same pseudo. Only do
7026 something if there will not be an output reload for the pseudo
7028 if (rld[r].in_reg != 0
7029 && ! (reload_inherited[r] || reload_override_in[r]))
7031 rtx reg = rld[r].in_reg;
7033 if (GET_CODE (reg) == SUBREG)
7034 reg = SUBREG_REG (reg);
7036 if (GET_CODE (reg) == REG
7037 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7038 && ! reg_has_output_reload[REGNO (reg)])
7040 int nregno = REGNO (reg);
7042 if (reg_last_reload_reg[nregno])
7044 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7046 if (reg_reloaded_contents[last_regno] == nregno)
7047 spill_reg_store[last_regno] = 0;
7052 /* I is nonneg if this reload used a register.
7053 If rld[r].reg_rtx is 0, this is an optional reload
7054 that we opted to ignore. */
7056 if (i >= 0 && rld[r].reg_rtx != 0)
7058 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7060 int part_reaches_end = 0;
7061 int all_reaches_end = 1;
7063 /* For a multi register reload, we need to check if all or part
7064 of the value lives to the end. */
7065 for (k = 0; k < nr; k++)
7067 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7068 rld[r].when_needed))
7069 part_reaches_end = 1;
7071 all_reaches_end = 0;
7074 /* Ignore reloads that don't reach the end of the insn in
7076 if (all_reaches_end)
7078 /* First, clear out memory of what used to be in this spill reg.
7079 If consecutive registers are used, clear them all. */
7081 for (k = 0; k < nr; k++)
7082 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7084 /* Maybe the spill reg contains a copy of reload_out. */
7086 && (GET_CODE (rld[r].out) == REG
7090 || GET_CODE (rld[r].out_reg) == REG))
7092 rtx out = (GET_CODE (rld[r].out) == REG
7096 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7097 register int nregno = REGNO (out);
7098 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7099 : HARD_REGNO_NREGS (nregno,
7100 GET_MODE (rld[r].reg_rtx)));
7102 spill_reg_store[i] = new_spill_reg_store[i];
7103 spill_reg_stored_to[i] = out;
7104 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7106 /* If NREGNO is a hard register, it may occupy more than
7107 one register. If it does, say what is in the
7108 rest of the registers assuming that both registers
7109 agree on how many words the object takes. If not,
7110 invalidate the subsequent registers. */
7112 if (nregno < FIRST_PSEUDO_REGISTER)
7113 for (k = 1; k < nnr; k++)
7114 reg_last_reload_reg[nregno + k]
7116 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7117 REGNO (rld[r].reg_rtx) + k)
7120 /* Now do the inverse operation. */
7121 for (k = 0; k < nr; k++)
7123 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7124 reg_reloaded_contents[i + k]
7125 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7128 reg_reloaded_insn[i + k] = insn;
7129 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7133 /* Maybe the spill reg contains a copy of reload_in. Only do
7134 something if there will not be an output reload for
7135 the register being reloaded. */
7136 else if (rld[r].out_reg == 0
7138 && ((GET_CODE (rld[r].in) == REG
7139 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7140 && ! reg_has_output_reload[REGNO (rld[r].in)])
7141 || (GET_CODE (rld[r].in_reg) == REG
7142 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7143 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7145 register int nregno;
7148 if (GET_CODE (rld[r].in) == REG
7149 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7150 nregno = REGNO (rld[r].in);
7151 else if (GET_CODE (rld[r].in_reg) == REG)
7152 nregno = REGNO (rld[r].in_reg);
7154 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7156 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7157 : HARD_REGNO_NREGS (nregno,
7158 GET_MODE (rld[r].reg_rtx)));
7160 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7162 if (nregno < FIRST_PSEUDO_REGISTER)
7163 for (k = 1; k < nnr; k++)
7164 reg_last_reload_reg[nregno + k]
7166 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7167 REGNO (rld[r].reg_rtx) + k)
7170 /* Unless we inherited this reload, show we haven't
7171 recently done a store.
7172 Previous stores of inherited auto_inc expressions
7173 also have to be discarded. */
7174 if (! reload_inherited[r]
7175 || (rld[r].out && ! rld[r].out_reg))
7176 spill_reg_store[i] = 0;
7178 for (k = 0; k < nr; k++)
7180 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7181 reg_reloaded_contents[i + k]
7182 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7185 reg_reloaded_insn[i + k] = insn;
7186 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7191 /* However, if part of the reload reaches the end, then we must
7192 invalidate the old info for the part that survives to the end. */
7193 else if (part_reaches_end)
7195 for (k = 0; k < nr; k++)
7196 if (reload_reg_reaches_end_p (i + k,
7198 rld[r].when_needed))
7199 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7203 /* The following if-statement was #if 0'd in 1.34 (or before...).
7204 It's reenabled in 1.35 because supposedly nothing else
7205 deals with this problem. */
7207 /* If a register gets output-reloaded from a non-spill register,
7208 that invalidates any previous reloaded copy of it.
7209 But forget_old_reloads_1 won't get to see it, because
7210 it thinks only about the original insn. So invalidate it here. */
7211 if (i < 0 && rld[r].out != 0
7212 && (GET_CODE (rld[r].out) == REG
7213 || (GET_CODE (rld[r].out) == MEM
7214 && GET_CODE (rld[r].out_reg) == REG)))
7216 rtx out = (GET_CODE (rld[r].out) == REG
7217 ? rld[r].out : rld[r].out_reg);
7218 register int nregno = REGNO (out);
7219 if (nregno >= FIRST_PSEUDO_REGISTER)
7221 rtx src_reg, store_insn = NULL_RTX;
7223 reg_last_reload_reg[nregno] = 0;
7225 /* If we can find a hard register that is stored, record
7226 the storing insn so that we may delete this insn with
7227 delete_output_reload. */
7228 src_reg = rld[r].reg_rtx;
7230 /* If this is an optional reload, try to find the source reg
7231 from an input reload. */
7234 rtx set = single_set (insn);
7235 if (set && SET_DEST (set) == rld[r].out)
7239 src_reg = SET_SRC (set);
7241 for (k = 0; k < n_reloads; k++)
7243 if (rld[k].in == src_reg)
7245 src_reg = rld[k].reg_rtx;
7252 store_insn = new_spill_reg_store[REGNO (src_reg)];
7253 if (src_reg && GET_CODE (src_reg) == REG
7254 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7256 int src_regno = REGNO (src_reg);
7257 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7258 /* The place where to find a death note varies with
7259 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7260 necessarily checked exactly in the code that moves
7261 notes, so just check both locations. */
7262 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7263 if (! note && store_insn)
7264 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7267 spill_reg_store[src_regno + nr] = store_insn;
7268 spill_reg_stored_to[src_regno + nr] = out;
7269 reg_reloaded_contents[src_regno + nr] = nregno;
7270 reg_reloaded_insn[src_regno + nr] = store_insn;
7271 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7272 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7273 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7275 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7277 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7279 reg_last_reload_reg[nregno] = src_reg;
7284 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7286 while (num_regs-- > 0)
7287 reg_last_reload_reg[nregno + num_regs] = 0;
7291 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7294 /* Emit code to perform a reload from IN (which may be a reload register) to
7295 OUT (which may also be a reload register). IN or OUT is from operand
7296 OPNUM with reload type TYPE.
7298 Returns first insn emitted. */
7301 gen_reload (out, in, opnum, type)
7305 enum reload_type type;
7307 rtx last = get_last_insn ();
7310 /* If IN is a paradoxical SUBREG, remove it and try to put the
7311 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7312 if (GET_CODE (in) == SUBREG
7313 && (GET_MODE_SIZE (GET_MODE (in))
7314 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7315 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7316 in = SUBREG_REG (in), out = tem;
7317 else if (GET_CODE (out) == SUBREG
7318 && (GET_MODE_SIZE (GET_MODE (out))
7319 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7320 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7321 out = SUBREG_REG (out), in = tem;
7323 /* How to do this reload can get quite tricky. Normally, we are being
7324 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7325 register that didn't get a hard register. In that case we can just
7326 call emit_move_insn.
7328 We can also be asked to reload a PLUS that adds a register or a MEM to
7329 another register, constant or MEM. This can occur during frame pointer
7330 elimination and while reloading addresses. This case is handled by
7331 trying to emit a single insn to perform the add. If it is not valid,
7332 we use a two insn sequence.
7334 Finally, we could be called to handle an 'o' constraint by putting
7335 an address into a register. In that case, we first try to do this
7336 with a named pattern of "reload_load_address". If no such pattern
7337 exists, we just emit a SET insn and hope for the best (it will normally
7338 be valid on machines that use 'o').
7340 This entire process is made complex because reload will never
7341 process the insns we generate here and so we must ensure that
7342 they will fit their constraints and also by the fact that parts of
7343 IN might be being reloaded separately and replaced with spill registers.
7344 Because of this, we are, in some sense, just guessing the right approach
7345 here. The one listed above seems to work.
7347 ??? At some point, this whole thing needs to be rethought. */
7349 if (GET_CODE (in) == PLUS
7350 && (GET_CODE (XEXP (in, 0)) == REG
7351 || GET_CODE (XEXP (in, 0)) == SUBREG
7352 || GET_CODE (XEXP (in, 0)) == MEM)
7353 && (GET_CODE (XEXP (in, 1)) == REG
7354 || GET_CODE (XEXP (in, 1)) == SUBREG
7355 || CONSTANT_P (XEXP (in, 1))
7356 || GET_CODE (XEXP (in, 1)) == MEM))
7358 /* We need to compute the sum of a register or a MEM and another
7359 register, constant, or MEM, and put it into the reload
7360 register. The best possible way of doing this is if the machine
7361 has a three-operand ADD insn that accepts the required operands.
7363 The simplest approach is to try to generate such an insn and see if it
7364 is recognized and matches its constraints. If so, it can be used.
7366 It might be better not to actually emit the insn unless it is valid,
7367 but we need to pass the insn as an operand to `recog' and
7368 `extract_insn' and it is simpler to emit and then delete the insn if
7369 not valid than to dummy things up. */
7371 rtx op0, op1, tem, insn;
7374 op0 = find_replacement (&XEXP (in, 0));
7375 op1 = find_replacement (&XEXP (in, 1));
7377 /* Since constraint checking is strict, commutativity won't be
7378 checked, so we need to do that here to avoid spurious failure
7379 if the add instruction is two-address and the second operand
7380 of the add is the same as the reload reg, which is frequently
7381 the case. If the insn would be A = B + A, rearrange it so
7382 it will be A = A + B as constrain_operands expects. */
7384 if (GET_CODE (XEXP (in, 1)) == REG
7385 && REGNO (out) == REGNO (XEXP (in, 1)))
7386 tem = op0, op0 = op1, op1 = tem;
7388 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7389 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7391 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7392 code = recog_memoized (insn);
7396 extract_insn (insn);
7397 /* We want constrain operands to treat this insn strictly in
7398 its validity determination, i.e., the way it would after reload
7400 if (constrain_operands (1))
7404 delete_insns_since (last);
7406 /* If that failed, we must use a conservative two-insn sequence.
7408 Use a move to copy one operand into the reload register. Prefer
7409 to reload a constant, MEM or pseudo since the move patterns can
7410 handle an arbitrary operand. If OP1 is not a constant, MEM or
7411 pseudo and OP1 is not a valid operand for an add instruction, then
7414 After reloading one of the operands into the reload register, add
7415 the reload register to the output register.
7417 If there is another way to do this for a specific machine, a
7418 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7421 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7423 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7424 || (GET_CODE (op1) == REG
7425 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7426 || (code != CODE_FOR_nothing
7427 && ! ((*insn_data[code].operand[2].predicate)
7428 (op1, insn_data[code].operand[2].mode))))
7429 tem = op0, op0 = op1, op1 = tem;
7431 gen_reload (out, op0, opnum, type);
7433 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7434 This fixes a problem on the 32K where the stack pointer cannot
7435 be used as an operand of an add insn. */
7437 if (rtx_equal_p (op0, op1))
7440 insn = emit_insn (gen_add2_insn (out, op1));
7442 /* If that failed, copy the address register to the reload register.
7443 Then add the constant to the reload register. */
7445 code = recog_memoized (insn);
7449 extract_insn (insn);
7450 /* We want constrain operands to treat this insn strictly in
7451 its validity determination, i.e., the way it would after reload
7453 if (constrain_operands (1))
7455 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7457 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7462 delete_insns_since (last);
7464 gen_reload (out, op1, opnum, type);
7465 insn = emit_insn (gen_add2_insn (out, op0));
7466 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7469 #ifdef SECONDARY_MEMORY_NEEDED
7470 /* If we need a memory location to do the move, do it that way. */
7471 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7472 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7473 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7474 REGNO_REG_CLASS (REGNO (out)),
7477 /* Get the memory to use and rewrite both registers to its mode. */
7478 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7480 if (GET_MODE (loc) != GET_MODE (out))
7481 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7483 if (GET_MODE (loc) != GET_MODE (in))
7484 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7486 gen_reload (loc, in, opnum, type);
7487 gen_reload (out, loc, opnum, type);
7491 /* If IN is a simple operand, use gen_move_insn. */
7492 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7493 emit_insn (gen_move_insn (out, in));
7495 #ifdef HAVE_reload_load_address
7496 else if (HAVE_reload_load_address)
7497 emit_insn (gen_reload_load_address (out, in));
7500 /* Otherwise, just write (set OUT IN) and hope for the best. */
7502 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7504 /* Return the first insn emitted.
7505 We can not just return get_last_insn, because there may have
7506 been multiple instructions emitted. Also note that gen_move_insn may
7507 emit more than one insn itself, so we can not assume that there is one
7508 insn emitted per emit_insn_before call. */
7510 return last ? NEXT_INSN (last) : get_insns ();
7513 /* Delete a previously made output-reload
7514 whose result we now believe is not needed.
7515 First we double-check.
7517 INSN is the insn now being processed.
7518 LAST_RELOAD_REG is the hard register number for which we want to delete
7519 the last output reload.
7520 J is the reload-number that originally used REG. The caller has made
7521 certain that reload J doesn't use REG any longer for input. */
7524 delete_output_reload (insn, j, last_reload_reg)
7527 int last_reload_reg;
7529 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7530 rtx reg = spill_reg_stored_to[last_reload_reg];
7533 int n_inherited = 0;
7537 /* Get the raw pseudo-register referred to. */
7539 while (GET_CODE (reg) == SUBREG)
7540 reg = SUBREG_REG (reg);
7541 substed = reg_equiv_memory_loc[REGNO (reg)];
7543 /* This is unsafe if the operand occurs more often in the current
7544 insn than it is inherited. */
7545 for (k = n_reloads - 1; k >= 0; k--)
7547 rtx reg2 = rld[k].in;
7550 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7551 reg2 = rld[k].in_reg;
7553 if (rld[k].out && ! rld[k].out_reg)
7554 reg2 = XEXP (rld[k].in_reg, 0);
7556 while (GET_CODE (reg2) == SUBREG)
7557 reg2 = SUBREG_REG (reg2);
7558 if (rtx_equal_p (reg2, reg))
7560 if (reload_inherited[k] || reload_override_in[k] || k == j)
7563 reg2 = rld[k].out_reg;
7566 while (GET_CODE (reg2) == SUBREG)
7567 reg2 = XEXP (reg2, 0);
7568 if (rtx_equal_p (reg2, reg))
7575 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7577 n_occurrences += count_occurrences (PATTERN (insn),
7578 eliminate_regs (substed, 0,
7580 if (n_occurrences > n_inherited)
7583 /* If the pseudo-reg we are reloading is no longer referenced
7584 anywhere between the store into it and here,
7585 and no jumps or labels intervene, then the value can get
7586 here through the reload reg alone.
7587 Otherwise, give up--return. */
7588 for (i1 = NEXT_INSN (output_reload_insn);
7589 i1 != insn; i1 = NEXT_INSN (i1))
7591 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7593 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7594 && reg_mentioned_p (reg, PATTERN (i1)))
7596 /* If this is USE in front of INSN, we only have to check that
7597 there are no more references than accounted for by inheritance. */
7598 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7600 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7601 i1 = NEXT_INSN (i1);
7603 if (n_occurrences <= n_inherited && i1 == insn)
7609 /* The caller has already checked that REG dies or is set in INSN.
7610 It has also checked that we are optimizing, and thus some inaccurancies
7611 in the debugging information are acceptable.
7612 So we could just delete output_reload_insn.
7613 But in some cases we can improve the debugging information without
7614 sacrificing optimization - maybe even improving the code:
7615 See if the pseudo reg has been completely replaced
7616 with reload regs. If so, delete the store insn
7617 and forget we had a stack slot for the pseudo. */
7618 if (rld[j].out != rld[j].in
7619 && REG_N_DEATHS (REGNO (reg)) == 1
7620 && REG_N_SETS (REGNO (reg)) == 1
7621 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7622 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7626 /* We know that it was used only between here
7627 and the beginning of the current basic block.
7628 (We also know that the last use before INSN was
7629 the output reload we are thinking of deleting, but never mind that.)
7630 Search that range; see if any ref remains. */
7631 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7633 rtx set = single_set (i2);
7635 /* Uses which just store in the pseudo don't count,
7636 since if they are the only uses, they are dead. */
7637 if (set != 0 && SET_DEST (set) == reg)
7639 if (GET_CODE (i2) == CODE_LABEL
7640 || GET_CODE (i2) == JUMP_INSN)
7642 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7643 && reg_mentioned_p (reg, PATTERN (i2)))
7645 /* Some other ref remains; just delete the output reload we
7647 delete_address_reloads (output_reload_insn, insn);
7648 delete_insn (output_reload_insn);
7653 /* Delete the now-dead stores into this pseudo. */
7654 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7656 rtx set = single_set (i2);
7658 if (set != 0 && SET_DEST (set) == reg)
7660 delete_address_reloads (i2, insn);
7661 /* This might be a basic block head,
7662 thus don't use delete_insn. */
7665 if (GET_CODE (i2) == CODE_LABEL
7666 || GET_CODE (i2) == JUMP_INSN)
7670 /* For the debugging info,
7671 say the pseudo lives in this reload reg. */
7672 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7673 alter_reg (REGNO (reg), -1);
7675 delete_address_reloads (output_reload_insn, insn);
7676 delete_insn (output_reload_insn);
7680 /* We are going to delete DEAD_INSN. Recursively delete loads of
7681 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7682 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7684 delete_address_reloads (dead_insn, current_insn)
7685 rtx dead_insn, current_insn;
7687 rtx set = single_set (dead_insn);
7688 rtx set2, dst, prev, next;
7691 rtx dst = SET_DEST (set);
7692 if (GET_CODE (dst) == MEM)
7693 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7695 /* If we deleted the store from a reloaded post_{in,de}c expression,
7696 we can delete the matching adds. */
7697 prev = PREV_INSN (dead_insn);
7698 next = NEXT_INSN (dead_insn);
7699 if (! prev || ! next)
7701 set = single_set (next);
7702 set2 = single_set (prev);
7704 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7705 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7706 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7708 dst = SET_DEST (set);
7709 if (! rtx_equal_p (dst, SET_DEST (set2))
7710 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7711 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7712 || (INTVAL (XEXP (SET_SRC (set), 1))
7713 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7715 delete_related_insns (prev);
7716 delete_related_insns (next);
7719 /* Subfunction of delete_address_reloads: process registers found in X. */
7721 delete_address_reloads_1 (dead_insn, x, current_insn)
7722 rtx dead_insn, x, current_insn;
7724 rtx prev, set, dst, i2;
7726 enum rtx_code code = GET_CODE (x);
7730 const char *fmt = GET_RTX_FORMAT (code);
7731 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7734 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7735 else if (fmt[i] == 'E')
7737 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7738 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7745 if (spill_reg_order[REGNO (x)] < 0)
7748 /* Scan backwards for the insn that sets x. This might be a way back due
7750 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7752 code = GET_CODE (prev);
7753 if (code == CODE_LABEL || code == JUMP_INSN)
7755 if (GET_RTX_CLASS (code) != 'i')
7757 if (reg_set_p (x, PATTERN (prev)))
7759 if (reg_referenced_p (x, PATTERN (prev)))
7762 if (! prev || INSN_UID (prev) < reload_first_uid)
7764 /* Check that PREV only sets the reload register. */
7765 set = single_set (prev);
7768 dst = SET_DEST (set);
7769 if (GET_CODE (dst) != REG
7770 || ! rtx_equal_p (dst, x))
7772 if (! reg_set_p (dst, PATTERN (dead_insn)))
7774 /* Check if DST was used in a later insn -
7775 it might have been inherited. */
7776 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7778 if (GET_CODE (i2) == CODE_LABEL)
7782 if (reg_referenced_p (dst, PATTERN (i2)))
7784 /* If there is a reference to the register in the current insn,
7785 it might be loaded in a non-inherited reload. If no other
7786 reload uses it, that means the register is set before
7788 if (i2 == current_insn)
7790 for (j = n_reloads - 1; j >= 0; j--)
7791 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7792 || reload_override_in[j] == dst)
7794 for (j = n_reloads - 1; j >= 0; j--)
7795 if (rld[j].in && rld[j].reg_rtx == dst)
7802 if (GET_CODE (i2) == JUMP_INSN)
7804 /* If DST is still live at CURRENT_INSN, check if it is used for
7805 any reload. Note that even if CURRENT_INSN sets DST, we still
7806 have to check the reloads. */
7807 if (i2 == current_insn)
7809 for (j = n_reloads - 1; j >= 0; j--)
7810 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7811 || reload_override_in[j] == dst)
7813 /* ??? We can't finish the loop here, because dst might be
7814 allocated to a pseudo in this block if no reload in this
7815 block needs any of the clsses containing DST - see
7816 spill_hard_reg. There is no easy way to tell this, so we
7817 have to scan till the end of the basic block. */
7819 if (reg_set_p (dst, PATTERN (i2)))
7823 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7824 reg_reloaded_contents[REGNO (dst)] = -1;
7828 /* Output reload-insns to reload VALUE into RELOADREG.
7829 VALUE is an autoincrement or autodecrement RTX whose operand
7830 is a register or memory location;
7831 so reloading involves incrementing that location.
7832 IN is either identical to VALUE, or some cheaper place to reload from.
7834 INC_AMOUNT is the number to increment or decrement by (always positive).
7835 This cannot be deduced from VALUE.
7837 Return the instruction that stores into RELOADREG. */
7840 inc_for_reload (reloadreg, in, value, inc_amount)
7845 /* REG or MEM to be copied and incremented. */
7846 rtx incloc = XEXP (value, 0);
7847 /* Nonzero if increment after copying. */
7848 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7854 rtx real_in = in == value ? XEXP (in, 0) : in;
7856 /* No hard register is equivalent to this register after
7857 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7858 we could inc/dec that register as well (maybe even using it for
7859 the source), but I'm not sure it's worth worrying about. */
7860 if (GET_CODE (incloc) == REG)
7861 reg_last_reload_reg[REGNO (incloc)] = 0;
7863 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7864 inc_amount = -inc_amount;
7866 inc = GEN_INT (inc_amount);
7868 /* If this is post-increment, first copy the location to the reload reg. */
7869 if (post && real_in != reloadreg)
7870 emit_insn (gen_move_insn (reloadreg, real_in));
7874 /* See if we can directly increment INCLOC. Use a method similar to
7875 that in gen_reload. */
7877 last = get_last_insn ();
7878 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7879 gen_rtx_PLUS (GET_MODE (incloc),
7882 code = recog_memoized (add_insn);
7885 extract_insn (add_insn);
7886 if (constrain_operands (1))
7888 /* If this is a pre-increment and we have incremented the value
7889 where it lives, copy the incremented value to RELOADREG to
7890 be used as an address. */
7893 emit_insn (gen_move_insn (reloadreg, incloc));
7898 delete_insns_since (last);
7901 /* If couldn't do the increment directly, must increment in RELOADREG.
7902 The way we do this depends on whether this is pre- or post-increment.
7903 For pre-increment, copy INCLOC to the reload register, increment it
7904 there, then save back. */
7908 if (in != reloadreg)
7909 emit_insn (gen_move_insn (reloadreg, real_in));
7910 emit_insn (gen_add2_insn (reloadreg, inc));
7911 store = emit_insn (gen_move_insn (incloc, reloadreg));
7916 Because this might be a jump insn or a compare, and because RELOADREG
7917 may not be available after the insn in an input reload, we must do
7918 the incrementation before the insn being reloaded for.
7920 We have already copied IN to RELOADREG. Increment the copy in
7921 RELOADREG, save that back, then decrement RELOADREG so it has
7922 the original value. */
7924 emit_insn (gen_add2_insn (reloadreg, inc));
7925 store = emit_insn (gen_move_insn (incloc, reloadreg));
7926 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7932 /* Return 1 if we are certain that the constraint-string STRING allows
7933 the hard register REG. Return 0 if we can't be sure of this. */
7936 constraint_accepts_reg_p (string, reg)
7941 int regno = true_regnum (reg);
7944 /* Initialize for first alternative. */
7946 /* Check that each alternative contains `g' or `r'. */
7948 switch (c = *string++)
7951 /* If an alternative lacks `g' or `r', we lose. */
7954 /* If an alternative lacks `g' or `r', we lose. */
7957 /* Initialize for next alternative. */
7962 /* Any general reg wins for this alternative. */
7963 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7967 /* Any reg in specified class wins for this alternative. */
7969 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7971 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7977 /* INSN is a no-op; delete it.
7978 If this sets the return value of the function, we must keep a USE around,
7979 in case this is in a different basic block than the final USE. Otherwise,
7980 we could loose important register lifeness information on
7981 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7982 spills: subsequent passes assume that spill registers are dead at the end
7984 VALUE must be the return value in such a case, NULL otherwise. */
7986 reload_cse_delete_noop_set (insn, value)
7991 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7992 INSN_CODE (insn) = -1;
7993 REG_NOTES (insn) = NULL_RTX;
7999 /* See whether a single set SET is a noop. */
8001 reload_cse_noop_set_p (set)
8004 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8007 /* Try to simplify INSN. */
8009 reload_cse_simplify (insn)
8012 rtx body = PATTERN (insn);
8014 if (GET_CODE (body) == SET)
8018 /* Simplify even if we may think it is a no-op.
8019 We may think a memory load of a value smaller than WORD_SIZE
8020 is redundant because we haven't taken into account possible
8021 implicit extension. reload_cse_simplify_set() will bring
8022 this out, so it's safer to simplify before we delete. */
8023 count += reload_cse_simplify_set (body, insn);
8025 if (!count && reload_cse_noop_set_p (body))
8027 rtx value = SET_DEST (body);
8028 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8030 reload_cse_delete_noop_set (insn, value);
8035 apply_change_group ();
8037 reload_cse_simplify_operands (insn);
8039 else if (GET_CODE (body) == PARALLEL)
8043 rtx value = NULL_RTX;
8045 /* If every action in a PARALLEL is a noop, we can delete
8046 the entire PARALLEL. */
8047 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8049 rtx part = XVECEXP (body, 0, i);
8050 if (GET_CODE (part) == SET)
8052 if (! reload_cse_noop_set_p (part))
8054 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8058 value = SET_DEST (part);
8061 else if (GET_CODE (part) != CLOBBER)
8067 reload_cse_delete_noop_set (insn, value);
8068 /* We're done with this insn. */
8072 /* It's not a no-op, but we can try to simplify it. */
8073 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8074 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8075 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8078 apply_change_group ();
8080 reload_cse_simplify_operands (insn);
8084 /* Do a very simple CSE pass over the hard registers.
8086 This function detects no-op moves where we happened to assign two
8087 different pseudo-registers to the same hard register, and then
8088 copied one to the other. Reload will generate a useless
8089 instruction copying a register to itself.
8091 This function also detects cases where we load a value from memory
8092 into two different registers, and (if memory is more expensive than
8093 registers) changes it to simply copy the first register into the
8096 Another optimization is performed that scans the operands of each
8097 instruction to see whether the value is already available in a
8098 hard register. It then replaces the operand with the hard register
8099 if possible, much like an optional reload would. */
8102 reload_cse_regs_1 (first)
8108 init_alias_analysis ();
8110 for (insn = first; insn; insn = NEXT_INSN (insn))
8113 reload_cse_simplify (insn);
8115 cselib_process_insn (insn);
8119 end_alias_analysis ();
8123 /* Call cse / combine like post-reload optimization phases.
8124 FIRST is the first instruction. */
8126 reload_cse_regs (first)
8129 reload_cse_regs_1 (first);
8131 reload_cse_move2add (first);
8132 if (flag_expensive_optimizations)
8133 reload_cse_regs_1 (first);
8136 /* Try to simplify a single SET instruction. SET is the set pattern.
8137 INSN is the instruction it came from.
8138 This function only handles one case: if we set a register to a value
8139 which is not a register, we try to find that value in some other register
8140 and change the set into a register copy. */
8143 reload_cse_simplify_set (set, insn)
8150 enum reg_class dclass;
8153 struct elt_loc_list *l;
8154 #ifdef LOAD_EXTEND_OP
8155 enum rtx_code extend_op = NIL;
8158 dreg = true_regnum (SET_DEST (set));
8162 src = SET_SRC (set);
8163 if (side_effects_p (src) || true_regnum (src) >= 0)
8166 dclass = REGNO_REG_CLASS (dreg);
8168 #ifdef LOAD_EXTEND_OP
8169 /* When replacing a memory with a register, we need to honor assumptions
8170 that combine made wrt the contents of sign bits. We'll do this by
8171 generating an extend instruction instead of a reg->reg copy. Thus
8172 the destination must be a register that we can widen. */
8173 if (GET_CODE (src) == MEM
8174 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8175 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8176 && GET_CODE (SET_DEST (set)) != REG)
8180 /* If memory loads are cheaper than register copies, don't change them. */
8181 if (GET_CODE (src) == MEM)
8182 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8183 else if (CONSTANT_P (src))
8184 old_cost = rtx_cost (src, SET);
8185 else if (GET_CODE (src) == REG)
8186 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8187 REGNO_REG_CLASS (REGNO (src)), dclass);
8190 old_cost = rtx_cost (src, SET);
8192 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8195 for (l = val->locs; l; l = l->next)
8197 rtx this_rtx = l->loc;
8200 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8202 #ifdef LOAD_EXTEND_OP
8203 if (extend_op != NIL)
8205 HOST_WIDE_INT this_val;
8207 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8208 constants, such as SYMBOL_REF, cannot be extended. */
8209 if (GET_CODE (this_rtx) != CONST_INT)
8212 this_val = INTVAL (this_rtx);
8216 this_val &= GET_MODE_MASK (GET_MODE (src));
8219 /* ??? In theory we're already extended. */
8220 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8225 this_rtx = GEN_INT (this_val);
8228 this_cost = rtx_cost (this_rtx, SET);
8230 else if (GET_CODE (this_rtx) == REG)
8232 #ifdef LOAD_EXTEND_OP
8233 if (extend_op != NIL)
8235 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8236 this_cost = rtx_cost (this_rtx, SET);
8240 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8241 REGNO_REG_CLASS (REGNO (this_rtx)),
8247 /* If equal costs, prefer registers over anything else. That
8248 tends to lead to smaller instructions on some machines. */
8249 if (this_cost < old_cost
8250 || (this_cost == old_cost
8251 && GET_CODE (this_rtx) == REG
8252 && GET_CODE (SET_SRC (set)) != REG))
8254 #ifdef LOAD_EXTEND_OP
8255 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8256 && extend_op != NIL)
8258 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8259 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8260 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8264 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8265 old_cost = this_cost, did_change = 1;
8272 /* Try to replace operands in INSN with equivalent values that are already
8273 in registers. This can be viewed as optional reloading.
8275 For each non-register operand in the insn, see if any hard regs are
8276 known to be equivalent to that operand. Record the alternatives which
8277 can accept these hard registers. Among all alternatives, select the
8278 ones which are better or equal to the one currently matching, where
8279 "better" is in terms of '?' and '!' constraints. Among the remaining
8280 alternatives, select the one which replaces most operands with
8284 reload_cse_simplify_operands (insn)
8289 /* For each operand, all registers that are equivalent to it. */
8290 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8292 const char *constraints[MAX_RECOG_OPERANDS];
8294 /* Vector recording how bad an alternative is. */
8295 int *alternative_reject;
8296 /* Vector recording how many registers can be introduced by choosing
8297 this alternative. */
8298 int *alternative_nregs;
8299 /* Array of vectors recording, for each operand and each alternative,
8300 which hard register to substitute, or -1 if the operand should be
8302 int *op_alt_regno[MAX_RECOG_OPERANDS];
8303 /* Array of alternatives, sorted in order of decreasing desirability. */
8304 int *alternative_order;
8305 rtx reg = gen_rtx_REG (VOIDmode, -1);
8307 extract_insn (insn);
8309 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8312 /* Figure out which alternative currently matches. */
8313 if (! constrain_operands (1))
8314 fatal_insn_not_found (insn);
8316 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8317 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8318 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8319 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8320 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8322 /* For each operand, find out which regs are equivalent. */
8323 for (i = 0; i < recog_data.n_operands; i++)
8326 struct elt_loc_list *l;
8328 CLEAR_HARD_REG_SET (equiv_regs[i]);
8330 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8331 right, so avoid the problem here. Likewise if we have a constant
8332 and the insn pattern doesn't tell us the mode we need. */
8333 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8334 || (CONSTANT_P (recog_data.operand[i])
8335 && recog_data.operand_mode[i] == VOIDmode))
8338 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8342 for (l = v->locs; l; l = l->next)
8343 if (GET_CODE (l->loc) == REG)
8344 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8347 for (i = 0; i < recog_data.n_operands; i++)
8349 enum machine_mode mode;
8353 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8354 for (j = 0; j < recog_data.n_alternatives; j++)
8355 op_alt_regno[i][j] = -1;
8357 p = constraints[i] = recog_data.constraints[i];
8358 mode = recog_data.operand_mode[i];
8360 /* Add the reject values for each alternative given by the constraints
8361 for this operand. */
8369 alternative_reject[j] += 3;
8371 alternative_reject[j] += 300;
8374 /* We won't change operands which are already registers. We
8375 also don't want to modify output operands. */
8376 regno = true_regnum (recog_data.operand[i]);
8378 || constraints[i][0] == '='
8379 || constraints[i][0] == '+')
8382 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8384 int class = (int) NO_REGS;
8386 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8389 REGNO (reg) = regno;
8390 PUT_MODE (reg, mode);
8392 /* We found a register equal to this operand. Now look for all
8393 alternatives that can accept this register and have not been
8394 assigned a register they can use yet. */
8403 case '=': case '+': case '?':
8404 case '#': case '&': case '!':
8406 case '0': case '1': case '2': case '3': case '4':
8407 case '5': case '6': case '7': case '8': case '9':
8408 case 'm': case '<': case '>': case 'V': case 'o':
8409 case 'E': case 'F': case 'G': case 'H':
8410 case 's': case 'i': case 'n':
8411 case 'I': case 'J': case 'K': case 'L':
8412 case 'M': case 'N': case 'O': case 'P':
8414 /* These don't say anything we care about. */
8418 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8423 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8426 case ',': case '\0':
8427 /* See if REGNO fits this alternative, and set it up as the
8428 replacement register if we don't have one for this
8429 alternative yet and the operand being replaced is not
8430 a cheap CONST_INT. */
8431 if (op_alt_regno[i][j] == -1
8432 && reg_fits_class_p (reg, class, 0, mode)
8433 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8434 || (rtx_cost (recog_data.operand[i], SET)
8435 > rtx_cost (reg, SET))))
8437 alternative_nregs[j]++;
8438 op_alt_regno[i][j] = regno;
8450 /* Record all alternatives which are better or equal to the currently
8451 matching one in the alternative_order array. */
8452 for (i = j = 0; i < recog_data.n_alternatives; i++)
8453 if (alternative_reject[i] <= alternative_reject[which_alternative])
8454 alternative_order[j++] = i;
8455 recog_data.n_alternatives = j;
8457 /* Sort it. Given a small number of alternatives, a dumb algorithm
8458 won't hurt too much. */
8459 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8462 int best_reject = alternative_reject[alternative_order[i]];
8463 int best_nregs = alternative_nregs[alternative_order[i]];
8466 for (j = i + 1; j < recog_data.n_alternatives; j++)
8468 int this_reject = alternative_reject[alternative_order[j]];
8469 int this_nregs = alternative_nregs[alternative_order[j]];
8471 if (this_reject < best_reject
8472 || (this_reject == best_reject && this_nregs < best_nregs))
8475 best_reject = this_reject;
8476 best_nregs = this_nregs;
8480 tmp = alternative_order[best];
8481 alternative_order[best] = alternative_order[i];
8482 alternative_order[i] = tmp;
8485 /* Substitute the operands as determined by op_alt_regno for the best
8487 j = alternative_order[0];
8489 for (i = 0; i < recog_data.n_operands; i++)
8491 enum machine_mode mode = recog_data.operand_mode[i];
8492 if (op_alt_regno[i][j] == -1)
8495 validate_change (insn, recog_data.operand_loc[i],
8496 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8499 for (i = recog_data.n_dups - 1; i >= 0; i--)
8501 int op = recog_data.dup_num[i];
8502 enum machine_mode mode = recog_data.operand_mode[op];
8504 if (op_alt_regno[op][j] == -1)
8507 validate_change (insn, recog_data.dup_loc[i],
8508 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8511 return apply_change_group ();
8514 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8516 This code might also be useful when reload gave up on reg+reg addresssing
8517 because of clashes between the return register and INDEX_REG_CLASS. */
8519 /* The maximum number of uses of a register we can keep track of to
8520 replace them with reg+reg addressing. */
8521 #define RELOAD_COMBINE_MAX_USES 6
8523 /* INSN is the insn where a register has ben used, and USEP points to the
8524 location of the register within the rtl. */
8525 struct reg_use { rtx insn, *usep; };
8527 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8528 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8529 indicates where it becomes live again.
8530 Otherwise, USE_INDEX is the index of the last encountered use of the
8531 register (which is first among these we have seen since we scan backwards),
8532 OFFSET contains the constant offset that is added to the register in
8533 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8534 last, of these uses.
8535 STORE_RUID is always meaningful if we only want to use a value in a
8536 register in a different place: it denotes the next insn in the insn
8537 stream (i.e. the last ecountered) that sets or clobbers the register. */
8540 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8545 } reg_state[FIRST_PSEUDO_REGISTER];
8547 /* Reverse linear uid. This is increased in reload_combine while scanning
8548 the instructions from last to first. It is used to set last_label_ruid
8549 and the store_ruid / use_ruid fields in reg_state. */
8550 static int reload_combine_ruid;
8552 #define LABEL_LIVE(LABEL) \
8553 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8559 int first_index_reg = -1;
8560 int last_index_reg = 0;
8563 int last_label_ruid;
8564 int min_labelno, n_labels;
8565 HARD_REG_SET ever_live_at_start, *label_live;
8567 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8568 reload has already used it where appropriate, so there is no use in
8569 trying to generate it now. */
8570 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8573 /* To avoid wasting too much time later searching for an index register,
8574 determine the minimum and maximum index register numbers. */
8575 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8576 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8578 if (first_index_reg == -1)
8579 first_index_reg = r;
8584 /* If no index register is available, we can quit now. */
8585 if (first_index_reg == -1)
8588 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8589 information is a bit fuzzy immediately after reload, but it's
8590 still good enough to determine which registers are live at a jump
8592 min_labelno = get_first_label_num ();
8593 n_labels = max_label_num () - min_labelno;
8594 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8595 CLEAR_HARD_REG_SET (ever_live_at_start);
8597 for (i = n_basic_blocks - 1; i >= 0; i--)
8599 insn = BLOCK_HEAD (i);
8600 if (GET_CODE (insn) == CODE_LABEL)
8604 REG_SET_TO_HARD_REG_SET (live,
8605 BASIC_BLOCK (i)->global_live_at_start);
8606 compute_use_by_pseudos (&live,
8607 BASIC_BLOCK (i)->global_live_at_start);
8608 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8609 IOR_HARD_REG_SET (ever_live_at_start, live);
8613 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8614 last_label_ruid = reload_combine_ruid = 0;
8615 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8617 reg_state[r].store_ruid = reload_combine_ruid;
8619 reg_state[r].use_index = -1;
8621 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8624 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8628 /* We cannot do our optimization across labels. Invalidating all the use
8629 information we have would be costly, so we just note where the label
8630 is and then later disable any optimization that would cross it. */
8631 if (GET_CODE (insn) == CODE_LABEL)
8632 last_label_ruid = reload_combine_ruid;
8633 else if (GET_CODE (insn) == BARRIER)
8634 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8635 if (! fixed_regs[r])
8636 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8638 if (! INSN_P (insn))
8641 reload_combine_ruid++;
8643 /* Look for (set (REGX) (CONST_INT))
8644 (set (REGX) (PLUS (REGX) (REGY)))
8646 ... (MEM (REGX)) ...
8648 (set (REGZ) (CONST_INT))
8650 ... (MEM (PLUS (REGZ) (REGY)))... .
8652 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8653 and that we know all uses of REGX before it dies. */
8654 set = single_set (insn);
8656 && GET_CODE (SET_DEST (set)) == REG
8657 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8658 GET_MODE (SET_DEST (set)))
8660 && GET_CODE (SET_SRC (set)) == PLUS
8661 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8662 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8663 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8665 rtx reg = SET_DEST (set);
8666 rtx plus = SET_SRC (set);
8667 rtx base = XEXP (plus, 1);
8668 rtx prev = prev_nonnote_insn (insn);
8669 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8670 unsigned int regno = REGNO (reg);
8671 rtx const_reg = NULL_RTX;
8672 rtx reg_sum = NULL_RTX;
8674 /* Now, we need an index register.
8675 We'll set index_reg to this index register, const_reg to the
8676 register that is to be loaded with the constant
8677 (denoted as REGZ in the substitution illustration above),
8678 and reg_sum to the register-register that we want to use to
8679 substitute uses of REG (typically in MEMs) with.
8680 First check REG and BASE for being index registers;
8681 we can use them even if they are not dead. */
8682 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8683 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8691 /* Otherwise, look for a free index register. Since we have
8692 checked above that neiter REG nor BASE are index registers,
8693 if we find anything at all, it will be different from these
8695 for (i = first_index_reg; i <= last_index_reg; i++)
8697 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8699 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8700 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8701 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8703 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8705 const_reg = index_reg;
8706 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8712 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8713 (REGY), i.e. BASE, is not clobbered before the last use we'll
8716 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8717 && rtx_equal_p (SET_DEST (prev_set), reg)
8718 && reg_state[regno].use_index >= 0
8719 && (reg_state[REGNO (base)].store_ruid
8720 <= reg_state[regno].use_ruid)
8725 /* Change destination register and, if necessary, the
8726 constant value in PREV, the constant loading instruction. */
8727 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8728 if (reg_state[regno].offset != const0_rtx)
8729 validate_change (prev,
8730 &SET_SRC (prev_set),
8731 GEN_INT (INTVAL (SET_SRC (prev_set))
8732 + INTVAL (reg_state[regno].offset)),
8735 /* Now for every use of REG that we have recorded, replace REG
8737 for (i = reg_state[regno].use_index;
8738 i < RELOAD_COMBINE_MAX_USES; i++)
8739 validate_change (reg_state[regno].reg_use[i].insn,
8740 reg_state[regno].reg_use[i].usep,
8743 if (apply_change_group ())
8747 /* Delete the reg-reg addition. */
8750 if (reg_state[regno].offset != const0_rtx)
8751 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8753 for (np = ®_NOTES (prev); *np;)
8755 if (REG_NOTE_KIND (*np) == REG_EQUAL
8756 || REG_NOTE_KIND (*np) == REG_EQUIV)
8757 *np = XEXP (*np, 1);
8759 np = &XEXP (*np, 1);
8762 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8763 reg_state[REGNO (const_reg)].store_ruid
8764 = reload_combine_ruid;
8770 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8772 if (GET_CODE (insn) == CALL_INSN)
8776 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8777 if (call_used_regs[r])
8779 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8780 reg_state[r].store_ruid = reload_combine_ruid;
8783 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8784 link = XEXP (link, 1))
8786 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8787 if (GET_CODE (usage_rtx) == REG)
8790 unsigned int start_reg = REGNO (usage_rtx);
8791 unsigned int num_regs =
8792 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8793 unsigned int end_reg = start_reg + num_regs - 1;
8794 for (i = start_reg; i <= end_reg; i++)
8795 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8797 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8798 reg_state[i].store_ruid = reload_combine_ruid;
8801 reg_state[i].use_index = -1;
8806 else if (GET_CODE (insn) == JUMP_INSN
8807 && GET_CODE (PATTERN (insn)) != RETURN)
8809 /* Non-spill registers might be used at the call destination in
8810 some unknown fashion, so we have to mark the unknown use. */
8813 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8814 && JUMP_LABEL (insn))
8815 live = &LABEL_LIVE (JUMP_LABEL (insn));
8817 live = &ever_live_at_start;
8819 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8820 if (TEST_HARD_REG_BIT (*live, i))
8821 reg_state[i].use_index = -1;
8824 reload_combine_note_use (&PATTERN (insn), insn);
8825 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8827 if (REG_NOTE_KIND (note) == REG_INC
8828 && GET_CODE (XEXP (note, 0)) == REG)
8830 int regno = REGNO (XEXP (note, 0));
8832 reg_state[regno].store_ruid = reload_combine_ruid;
8833 reg_state[regno].use_index = -1;
8841 /* Check if DST is a register or a subreg of a register; if it is,
8842 update reg_state[regno].store_ruid and reg_state[regno].use_index
8843 accordingly. Called via note_stores from reload_combine. */
8846 reload_combine_note_store (dst, set, data)
8848 void *data ATTRIBUTE_UNUSED;
8852 enum machine_mode mode = GET_MODE (dst);
8854 if (GET_CODE (dst) == SUBREG)
8856 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8857 GET_MODE (SUBREG_REG (dst)),
8860 dst = SUBREG_REG (dst);
8862 if (GET_CODE (dst) != REG)
8864 regno += REGNO (dst);
8866 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8867 careful with registers / register parts that are not full words.
8869 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8870 if (GET_CODE (set) != SET
8871 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8872 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8873 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8875 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8877 reg_state[i].use_index = -1;
8878 reg_state[i].store_ruid = reload_combine_ruid;
8883 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8885 reg_state[i].store_ruid = reload_combine_ruid;
8886 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8891 /* XP points to a piece of rtl that has to be checked for any uses of
8893 *XP is the pattern of INSN, or a part of it.
8894 Called from reload_combine, and recursively by itself. */
8896 reload_combine_note_use (xp, insn)
8900 enum rtx_code code = x->code;
8903 rtx offset = const0_rtx; /* For the REG case below. */
8908 if (GET_CODE (SET_DEST (x)) == REG)
8910 reload_combine_note_use (&SET_SRC (x), insn);
8916 /* If this is the USE of a return value, we can't change it. */
8917 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8919 /* Mark the return register as used in an unknown fashion. */
8920 rtx reg = XEXP (x, 0);
8921 int regno = REGNO (reg);
8922 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8924 while (--nregs >= 0)
8925 reg_state[regno + nregs].use_index = -1;
8931 if (GET_CODE (SET_DEST (x)) == REG)
8936 /* We are interested in (plus (reg) (const_int)) . */
8937 if (GET_CODE (XEXP (x, 0)) != REG
8938 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8940 offset = XEXP (x, 1);
8945 int regno = REGNO (x);
8949 /* Some spurious USEs of pseudo registers might remain.
8950 Just ignore them. */
8951 if (regno >= FIRST_PSEUDO_REGISTER)
8954 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8956 /* We can't substitute into multi-hard-reg uses. */
8959 while (--nregs >= 0)
8960 reg_state[regno + nregs].use_index = -1;
8964 /* If this register is already used in some unknown fashion, we
8966 If we decrement the index from zero to -1, we can't store more
8967 uses, so this register becomes used in an unknown fashion. */
8968 use_index = --reg_state[regno].use_index;
8972 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8974 /* We have found another use for a register that is already
8975 used later. Check if the offsets match; if not, mark the
8976 register as used in an unknown fashion. */
8977 if (! rtx_equal_p (offset, reg_state[regno].offset))
8979 reg_state[regno].use_index = -1;
8985 /* This is the first use of this register we have seen since we
8986 marked it as dead. */
8987 reg_state[regno].offset = offset;
8988 reg_state[regno].use_ruid = reload_combine_ruid;
8990 reg_state[regno].reg_use[use_index].insn = insn;
8991 reg_state[regno].reg_use[use_index].usep = xp;
8999 /* Recursively process the components of X. */
9000 fmt = GET_RTX_FORMAT (code);
9001 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9004 reload_combine_note_use (&XEXP (x, i), insn);
9005 else if (fmt[i] == 'E')
9007 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9008 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9013 /* See if we can reduce the cost of a constant by replacing a move
9014 with an add. We track situations in which a register is set to a
9015 constant or to a register plus a constant. */
9016 /* We cannot do our optimization across labels. Invalidating all the
9017 information about register contents we have would be costly, so we
9018 use move2add_last_label_luid to note where the label is and then
9019 later disable any optimization that would cross it.
9020 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9021 reg_set_luid[n] is greater than last_label_luid[n] . */
9022 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9024 /* If reg_base_reg[n] is negative, register n has been set to
9025 reg_offset[n] in mode reg_mode[n] .
9026 If reg_base_reg[n] is non-negative, register n has been set to the
9027 sum of reg_offset[n] and the value of register reg_base_reg[n]
9028 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9029 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9030 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9031 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9033 /* move2add_luid is linearily increased while scanning the instructions
9034 from first to last. It is used to set reg_set_luid in
9035 reload_cse_move2add and move2add_note_store. */
9036 static int move2add_luid;
9038 /* move2add_last_label_luid is set whenever a label is found. Labels
9039 invalidate all previously collected reg_offset data. */
9040 static int move2add_last_label_luid;
9042 /* Generate a CONST_INT and force it in the range of MODE. */
9044 static HOST_WIDE_INT
9045 sext_for_mode (mode, value)
9046 enum machine_mode mode;
9047 HOST_WIDE_INT value;
9049 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9050 int width = GET_MODE_BITSIZE (mode);
9052 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9054 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9055 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9056 cval |= (HOST_WIDE_INT) -1 << width;
9061 /* ??? We don't know how zero / sign extension is handled, hence we
9062 can't go from a narrower to a wider mode. */
9063 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9064 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9065 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9066 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9067 GET_MODE_BITSIZE (INMODE))))
9070 reload_cse_move2add (first)
9076 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9077 reg_set_luid[i] = 0;
9079 move2add_last_label_luid = 0;
9081 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9085 if (GET_CODE (insn) == CODE_LABEL)
9087 move2add_last_label_luid = move2add_luid;
9088 /* We're going to increment move2add_luid twice after a
9089 label, so that we can use move2add_last_label_luid + 1 as
9090 the luid for constants. */
9094 if (! INSN_P (insn))
9096 pat = PATTERN (insn);
9097 /* For simplicity, we only perform this optimization on
9098 straightforward SETs. */
9099 if (GET_CODE (pat) == SET
9100 && GET_CODE (SET_DEST (pat)) == REG)
9102 rtx reg = SET_DEST (pat);
9103 int regno = REGNO (reg);
9104 rtx src = SET_SRC (pat);
9106 /* Check if we have valid information on the contents of this
9107 register in the mode of REG. */
9108 if (reg_set_luid[regno] > move2add_last_label_luid
9109 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9111 /* Try to transform (set (REGX) (CONST_INT A))
9113 (set (REGX) (CONST_INT B))
9115 (set (REGX) (CONST_INT A))
9117 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9119 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9122 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9124 - reg_offset[regno]));
9125 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9126 use (set (reg) (reg)) instead.
9127 We don't delete this insn, nor do we convert it into a
9128 note, to avoid losing register notes or the return
9129 value flag. jump2 already knowns how to get rid of
9131 if (new_src == const0_rtx)
9132 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9133 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9134 && have_add2_insn (reg, new_src))
9135 success = validate_change (insn, &PATTERN (insn),
9136 gen_add2_insn (reg, new_src), 0);
9137 reg_set_luid[regno] = move2add_luid;
9138 reg_mode[regno] = GET_MODE (reg);
9139 reg_offset[regno] = INTVAL (src);
9143 /* Try to transform (set (REGX) (REGY))
9144 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9147 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9150 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9152 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9153 else if (GET_CODE (src) == REG
9154 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9155 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9156 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9157 reg_mode[REGNO (src)]))
9159 rtx next = next_nonnote_insn (insn);
9162 set = single_set (next);
9164 && SET_DEST (set) == reg
9165 && GET_CODE (SET_SRC (set)) == PLUS
9166 && XEXP (SET_SRC (set), 0) == reg
9167 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9169 rtx src3 = XEXP (SET_SRC (set), 1);
9170 HOST_WIDE_INT added_offset = INTVAL (src3);
9171 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9172 HOST_WIDE_INT regno_offset = reg_offset[regno];
9173 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9179 if (new_src == const0_rtx)
9180 /* See above why we create (set (reg) (reg)) here. */
9182 = validate_change (next, &SET_SRC (set), reg, 0);
9183 else if ((rtx_cost (new_src, PLUS)
9184 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9185 && have_add2_insn (reg, new_src))
9187 = validate_change (next, &PATTERN (next),
9188 gen_add2_insn (reg, new_src), 0);
9192 reg_mode[regno] = GET_MODE (reg);
9193 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9202 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9204 if (REG_NOTE_KIND (note) == REG_INC
9205 && GET_CODE (XEXP (note, 0)) == REG)
9207 /* Reset the information about this register. */
9208 int regno = REGNO (XEXP (note, 0));
9209 if (regno < FIRST_PSEUDO_REGISTER)
9210 reg_set_luid[regno] = 0;
9213 note_stores (PATTERN (insn), move2add_note_store, NULL);
9214 /* If this is a CALL_INSN, all call used registers are stored with
9216 if (GET_CODE (insn) == CALL_INSN)
9218 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9220 if (call_used_regs[i])
9221 /* Reset the information about this register. */
9222 reg_set_luid[i] = 0;
9228 /* SET is a SET or CLOBBER that sets DST.
9229 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9230 Called from reload_cse_move2add via note_stores. */
9233 move2add_note_store (dst, set, data)
9235 void *data ATTRIBUTE_UNUSED;
9237 unsigned int regno = 0;
9239 enum machine_mode mode = GET_MODE (dst);
9241 if (GET_CODE (dst) == SUBREG)
9243 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9244 GET_MODE (SUBREG_REG (dst)),
9247 dst = SUBREG_REG (dst);
9250 /* Some targets do argument pushes without adding REG_INC notes. */
9252 if (GET_CODE (dst) == MEM)
9254 dst = XEXP (dst, 0);
9255 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC
9256 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9257 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9260 if (GET_CODE (dst) != REG)
9263 regno += REGNO (dst);
9265 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9266 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9267 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9268 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9270 rtx src = SET_SRC (set);
9272 HOST_WIDE_INT offset;
9274 /* This may be different from mode, if SET_DEST (set) is a
9276 enum machine_mode dst_mode = GET_MODE (dst);
9278 switch (GET_CODE (src))
9281 if (GET_CODE (XEXP (src, 0)) == REG)
9283 base_reg = XEXP (src, 0);
9285 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9286 offset = INTVAL (XEXP (src, 1));
9287 else if (GET_CODE (XEXP (src, 1)) == REG
9288 && (reg_set_luid[REGNO (XEXP (src, 1))]
9289 > move2add_last_label_luid)
9290 && (MODES_OK_FOR_MOVE2ADD
9291 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9293 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9294 offset = reg_offset[REGNO (XEXP (src, 1))];
9295 /* Maybe the first register is known to be a
9297 else if (reg_set_luid[REGNO (base_reg)]
9298 > move2add_last_label_luid
9299 && (MODES_OK_FOR_MOVE2ADD
9300 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9301 && reg_base_reg[REGNO (base_reg)] < 0)
9303 offset = reg_offset[REGNO (base_reg)];
9304 base_reg = XEXP (src, 1);
9323 /* Start tracking the register as a constant. */
9324 reg_base_reg[regno] = -1;
9325 reg_offset[regno] = INTVAL (SET_SRC (set));
9326 /* We assign the same luid to all registers set to constants. */
9327 reg_set_luid[regno] = move2add_last_label_luid + 1;
9328 reg_mode[regno] = mode;
9333 /* Invalidate the contents of the register. */
9334 reg_set_luid[regno] = 0;
9338 base_regno = REGNO (base_reg);
9339 /* If information about the base register is not valid, set it
9340 up as a new base register, pretending its value is known
9341 starting from the current insn. */
9342 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9344 reg_base_reg[base_regno] = base_regno;
9345 reg_offset[base_regno] = 0;
9346 reg_set_luid[base_regno] = move2add_luid;
9347 reg_mode[base_regno] = mode;
9349 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9350 reg_mode[base_regno]))
9353 reg_mode[regno] = mode;
9355 /* Copy base information from our base register. */
9356 reg_set_luid[regno] = reg_set_luid[base_regno];
9357 reg_base_reg[regno] = reg_base_reg[base_regno];
9359 /* Compute the sum of the offsets or constants. */
9360 reg_offset[regno] = sext_for_mode (dst_mode,
9362 + reg_offset[base_regno]);
9366 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9368 for (i = regno; i < endregno; i++)
9369 /* Reset the information about this register. */
9370 reg_set_luid[i] = 0;
9376 add_auto_inc_notes (insn, x)
9380 enum rtx_code code = GET_CODE (x);
9384 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9387 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9391 /* Scan all the operand sub-expressions. */
9392 fmt = GET_RTX_FORMAT (code);
9393 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9396 add_auto_inc_notes (insn, XEXP (x, i));
9397 else if (fmt[i] == 'E')
9398 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9399 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9404 /* Copy EH notes from an insn to its reloads. */
9406 copy_eh_notes (insn, x)
9410 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9413 for (; x != 0; x = NEXT_INSN (x))
9415 if (may_trap_p (PATTERN (x)))
9417 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
9423 /* This is used by reload pass, that does emit some instructions after
9424 abnormal calls moving basic block end, but in fact it wants to emit
9425 them on the edge. Looks for abnormal call edges, find backward the
9426 proper call and fix the damage.
9428 Similar handle instructions throwing exceptions internally. */
9430 fixup_abnormal_edges ()
9433 bool inserted = false;
9435 for (i = 0; i < n_basic_blocks; i++)
9437 basic_block bb = BASIC_BLOCK (i);
9440 /* Look for cases we are interested in - an calls or instructions causing
9442 for (e = bb->succ; e; e = e->succ_next)
9444 if (e->flags & EDGE_ABNORMAL_CALL)
9446 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
9447 == (EDGE_ABNORMAL | EDGE_EH))
9450 if (e && GET_CODE (bb->end) != CALL_INSN && !can_throw_internal (bb->end))
9452 rtx insn = bb->end, stop = NEXT_INSN (bb->end);
9454 for (e = bb->succ; e; e = e->succ_next)
9455 if (e->flags & EDGE_FALLTHRU)
9457 /* Get past the new insns generated. Allow notes, as the insns may
9458 be already deleted. */
9459 while ((GET_CODE (insn) == INSN || GET_CODE (insn) == NOTE)
9460 && !can_throw_internal (insn)
9461 && insn != bb->head)
9462 insn = PREV_INSN (insn);
9463 if (GET_CODE (insn) != CALL_INSN && !can_throw_internal (insn))
9467 insn = NEXT_INSN (insn);
9468 while (insn && insn != stop)
9470 next = NEXT_INSN (insn);
9473 insert_insn_on_edge (PATTERN (insn), e);
9481 commit_edge_insertions ();
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