1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
35 #include "basic-block.h"
43 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
44 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 #ifndef REGISTER_MOVE_COST
82 #define REGISTER_MOVE_COST(m, x, y) 2
86 #define LOCAL_REGNO(REGNO) 0
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx *reg_last_reload_reg;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static char *reg_has_output_reload;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload;
101 /* Element N is the constant value to which pseudo reg N is equivalent,
102 or zero if pseudo reg N is not equivalent to a constant.
103 find_reloads looks at this in order to replace pseudo reg N
104 with the constant it stands for. */
105 rtx *reg_equiv_constant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
114 This is used when the address is not valid as a memory address
115 (because its displacement is too big for the machine.) */
116 rtx *reg_equiv_address;
118 /* Element N is the memory slot to which pseudo reg N is equivalent,
119 or zero if pseudo reg N is not equivalent to a memory slot. */
122 /* Widest width in which each pseudo reg is referred to (via subreg). */
123 static unsigned int *reg_max_ref_width;
125 /* Element N is the list of insns that initialized reg N from its equivalent
126 constant or memory slot. */
127 static rtx *reg_equiv_init;
129 /* Vector to remember old contents of reg_renumber before spilling. */
130 static short *reg_old_renumber;
132 /* During reload_as_needed, element N contains the last pseudo regno reloaded
133 into hard register N. If that pseudo reg occupied more than one register,
134 reg_reloaded_contents points to that pseudo for each spill register in
135 use; all of these must remain set for an inheritance to occur. */
136 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
138 /* During reload_as_needed, element N contains the insn for which
139 hard register N was last used. Its contents are significant only
140 when reg_reloaded_valid is set for this register. */
141 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
143 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
144 static HARD_REG_SET reg_reloaded_valid;
145 /* Indicate if the register was dead at the end of the reload.
146 This is only valid if reg_reloaded_contents is set and valid. */
147 static HARD_REG_SET reg_reloaded_dead;
149 /* Number of spill-regs so far; number of valid elements of spill_regs. */
152 /* In parallel with spill_regs, contains REG rtx's for those regs.
153 Holds the last rtx used for any given reg, or 0 if it has never
154 been used for spilling yet. This rtx is reused, provided it has
156 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
158 /* In parallel with spill_regs, contains nonzero for a spill reg
159 that was stored after the last time it was used.
160 The precise value is the insn generated to do the store. */
161 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
163 /* This is the register that was stored with spill_reg_store. This is a
164 copy of reload_out / reload_out_reg when the value was stored; if
165 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
166 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
168 /* This table is the inverse mapping of spill_regs:
169 indexed by hard reg number,
170 it contains the position of that reg in spill_regs,
171 or -1 for something that is not in spill_regs.
173 ?!? This is no longer accurate. */
174 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates registers that can't be used as spill registers for
177 the currently processed insn. These are the hard registers which are live
178 during the insn, but not allocated to pseudos, as well as fixed
180 static HARD_REG_SET bad_spill_regs;
182 /* These are the hard registers that can't be used as spill register for any
183 insn. This includes registers used for user variables and registers that
184 we can't eliminate. A register that appears in this set also can't be used
185 to retry register allocation. */
186 static HARD_REG_SET bad_spill_regs_global;
188 /* Describes order of use of registers for reloading
189 of spilled pseudo-registers. `n_spills' is the number of
190 elements that are actually valid; new ones are added at the end.
192 Both spill_regs and spill_reg_order are used on two occasions:
193 once during find_reload_regs, where they keep track of the spill registers
194 for a single insn, but also during reload_as_needed where they show all
195 the registers ever used by reload. For the latter case, the information
196 is calculated during finish_spills. */
197 static short spill_regs[FIRST_PSEUDO_REGISTER];
199 /* This vector of reg sets indicates, for each pseudo, which hard registers
200 may not be used for retrying global allocation because the register was
201 formerly spilled from one of them. If we allowed reallocating a pseudo to
202 a register that it was already allocated to, reload might not
204 static HARD_REG_SET *pseudo_previous_regs;
206 /* This vector of reg sets indicates, for each pseudo, which hard
207 registers may not be used for retrying global allocation because they
208 are used as spill registers during one of the insns in which the
210 static HARD_REG_SET *pseudo_forbidden_regs;
212 /* All hard regs that have been used as spill registers for any insn are
213 marked in this set. */
214 static HARD_REG_SET used_spill_regs;
216 /* Index of last register assigned as a spill register. We allocate in
217 a round-robin fashion. */
218 static int last_spill_reg;
220 /* Nonzero if indirect addressing is supported on the machine; this means
221 that spilling (REG n) does not require reloading it into a register in
222 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
223 value indicates the level of indirect addressing supported, e.g., two
224 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
226 static char spill_indirect_levels;
228 /* Nonzero if indirect addressing is supported when the innermost MEM is
229 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
230 which these are valid is the same as spill_indirect_levels, above. */
231 char indirect_symref_ok;
233 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
234 char double_reg_address_ok;
236 /* Record the stack slot for each spilled hard register. */
237 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
239 /* Width allocated so far for that stack slot. */
240 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
242 /* Record which pseudos needed to be spilled. */
243 static regset_head spilled_pseudos;
245 /* Used for communication between order_regs_for_reload and count_pseudo.
246 Used to avoid counting one pseudo twice. */
247 static regset_head pseudos_counted;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress = 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
265 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory allocated in copy_reloads during calculate_needs_all_insns. */
278 char *reload_firstobj;
280 /* This points before all local rtl generated by register elimination.
281 Used to quickly free all memory after processing one insn. */
282 static char *reload_insn_firstobj;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
292 extern tree current_function_decl;
294 extern union tree_node *current_function_decl;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 int initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset; /* Current offset between the two regs. */
314 int previous_offset; /* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table *reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at;
365 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
367 /* Number of labels in the current function. */
369 static int num_labels;
371 static void replace_pseudos_in_call_usage PARAMS((rtx *,
374 static void maybe_fix_stack_asms PARAMS ((void));
375 static void copy_reloads PARAMS ((struct insn_chain *));
376 static void calculate_needs_all_insns PARAMS ((int));
377 static int find_reg PARAMS ((struct insn_chain *, int));
378 static void find_reload_regs PARAMS ((struct insn_chain *));
379 static void select_reload_regs PARAMS ((void));
380 static void delete_caller_save_insns PARAMS ((void));
382 static void spill_failure PARAMS ((rtx, enum reg_class));
383 static void count_spilled_pseudo PARAMS ((int, int, int));
384 static void delete_dead_insn PARAMS ((rtx));
385 static void alter_reg PARAMS ((int, int));
386 static void set_label_offsets PARAMS ((rtx, rtx, int));
387 static void check_eliminable_occurrences PARAMS ((rtx));
388 static void elimination_effects PARAMS ((rtx, enum machine_mode));
389 static int eliminate_regs_in_insn PARAMS ((rtx, int));
390 static void update_eliminable_offsets PARAMS ((void));
391 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
392 static void set_initial_elim_offsets PARAMS ((void));
393 static void verify_initial_elim_offsets PARAMS ((void));
394 static void set_initial_label_offsets PARAMS ((void));
395 static void set_offsets_for_label PARAMS ((rtx));
396 static void init_elim_table PARAMS ((void));
397 static void update_eliminables PARAMS ((HARD_REG_SET *));
398 static void spill_hard_reg PARAMS ((unsigned int, int));
399 static int finish_spills PARAMS ((int));
400 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
401 static void scan_paradoxical_subregs PARAMS ((rtx));
402 static void count_pseudo PARAMS ((int));
403 static void order_regs_for_reload PARAMS ((struct insn_chain *));
404 static void reload_as_needed PARAMS ((int));
405 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
406 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
407 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
410 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
413 static int reload_reg_free_p PARAMS ((unsigned int, int,
415 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
417 rtx, rtx, int, int));
418 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
419 enum reload_type, rtx, rtx,
421 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
423 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
425 static int conflicts_with_override PARAMS ((rtx));
426 static void failed_reload PARAMS ((rtx, int));
427 static int set_reload_reg PARAMS ((int, int));
428 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
429 static void choose_reload_regs PARAMS ((struct insn_chain *));
430 static void merge_assigned_reloads PARAMS ((rtx));
431 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, rtx, int));
433 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_input_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void do_output_reload PARAMS ((struct insn_chain *,
438 struct reload *, int));
439 static void emit_reload_insns PARAMS ((struct insn_chain *));
440 static void delete_output_reload PARAMS ((rtx, int, int));
441 static void delete_address_reloads PARAMS ((rtx, rtx));
442 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
443 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
444 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
445 static void reload_cse_regs_1 PARAMS ((rtx));
446 static int reload_cse_noop_set_p PARAMS ((rtx));
447 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
448 static int reload_cse_simplify_operands PARAMS ((rtx));
449 static void reload_combine PARAMS ((void));
450 static void reload_combine_note_use PARAMS ((rtx *, rtx));
451 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
452 static void reload_cse_move2add PARAMS ((rtx));
453 static void move2add_note_store PARAMS ((rtx, rtx, void *));
455 static void add_auto_inc_notes PARAMS ((rtx, rtx));
457 static void copy_eh_notes PARAMS ((rtx, rtx));
458 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
460 static void failed_reload PARAMS ((rtx, int));
461 static int set_reload_reg PARAMS ((int, int));
462 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
463 static void reload_cse_simplify PARAMS ((rtx));
464 extern void dump_needs PARAMS ((struct insn_chain *));
466 /* Initialize the reload pass once per compilation. */
473 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
474 Set spill_indirect_levels to the number of levels such addressing is
475 permitted, zero if it is not permitted at all. */
478 = gen_rtx_MEM (Pmode,
481 LAST_VIRTUAL_REGISTER + 1),
483 spill_indirect_levels = 0;
485 while (memory_address_p (QImode, tem))
487 spill_indirect_levels++;
488 tem = gen_rtx_MEM (Pmode, tem);
491 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
493 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
494 indirect_symref_ok = memory_address_p (QImode, tem);
496 /* See if reg+reg is a valid (and offsettable) address. */
498 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
500 tem = gen_rtx_PLUS (Pmode,
501 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
502 gen_rtx_REG (Pmode, i));
504 /* This way, we make sure that reg+reg is an offsettable address. */
505 tem = plus_constant (tem, 4);
507 if (memory_address_p (QImode, tem))
509 double_reg_address_ok = 1;
514 /* Initialize obstack for our rtl allocation. */
515 gcc_obstack_init (&reload_obstack);
516 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
518 INIT_REG_SET (&spilled_pseudos);
519 INIT_REG_SET (&pseudos_counted);
522 /* List of insn chains that are currently unused. */
523 static struct insn_chain *unused_insn_chains = 0;
525 /* Allocate an empty insn_chain structure. */
529 struct insn_chain *c;
531 if (unused_insn_chains == 0)
533 c = (struct insn_chain *)
534 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
535 INIT_REG_SET (&c->live_throughout);
536 INIT_REG_SET (&c->dead_or_set);
540 c = unused_insn_chains;
541 unused_insn_chains = c->next;
543 c->is_caller_save_insn = 0;
544 c->need_operand_change = 0;
550 /* Small utility function to set all regs in hard reg set TO which are
551 allocated to pseudos in regset FROM. */
554 compute_use_by_pseudos (to, from)
560 EXECUTE_IF_SET_IN_REG_SET
561 (from, FIRST_PSEUDO_REGISTER, regno,
563 int r = reg_renumber[regno];
568 /* reload_combine uses the information from
569 BASIC_BLOCK->global_live_at_start, which might still
570 contain registers that have not actually been allocated
571 since they have an equivalence. */
572 if (! reload_completed)
577 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
579 SET_HARD_REG_BIT (*to, r + nregs);
584 /* Replace all pseudos found in LOC with their corresponding
588 replace_pseudos_in_call_usage (loc, mem_mode, usage)
590 enum machine_mode mem_mode;
604 unsigned int regno = REGNO (x);
606 if (regno < FIRST_PSEUDO_REGISTER)
609 x = eliminate_regs (x, mem_mode, usage);
613 replace_pseudos_in_call_usage (loc, mem_mode, usage);
617 if (reg_equiv_constant[regno])
618 *loc = reg_equiv_constant[regno];
619 else if (reg_equiv_mem[regno])
620 *loc = reg_equiv_mem[regno];
621 else if (reg_equiv_address[regno])
622 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
623 else if (GET_CODE (regno_reg_rtx[regno]) != REG
624 || REGNO (regno_reg_rtx[regno]) != regno)
625 *loc = regno_reg_rtx[regno];
631 else if (code == MEM)
633 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
637 /* Process each of our operands recursively. */
638 fmt = GET_RTX_FORMAT (code);
639 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
641 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
642 else if (*fmt == 'E')
643 for (j = 0; j < XVECLEN (x, i); j++)
644 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
648 /* Global variables used by reload and its subroutines. */
650 /* Set during calculate_needs if an insn needs register elimination. */
651 static int something_needs_elimination;
652 /* Set during calculate_needs if an insn needs an operand changed. */
653 int something_needs_operands_changed;
655 /* Nonzero means we couldn't get enough spill regs. */
658 /* Main entry point for the reload pass.
660 FIRST is the first insn of the function being compiled.
662 GLOBAL nonzero means we were called from global_alloc
663 and should attempt to reallocate any pseudoregs that we
664 displace from hard regs we will use for reloads.
665 If GLOBAL is zero, we do not have enough information to do that,
666 so any pseudo reg that is spilled must go to the stack.
668 Return value is nonzero if reload failed
669 and we must not do any more for this function. */
672 reload (first, global)
678 register struct elim_table *ep;
680 /* The two pointers used to track the true location of the memory used
681 for label offsets. */
682 char *real_known_ptr = NULL;
683 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
685 /* Make sure even insns with volatile mem refs are recognizable. */
690 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
692 /* Make sure that the last insn in the chain
693 is not something that needs reloading. */
694 emit_note (NULL, NOTE_INSN_DELETED);
696 /* Enable find_equiv_reg to distinguish insns made by reload. */
697 reload_first_uid = get_max_uid ();
699 #ifdef SECONDARY_MEMORY_NEEDED
700 /* Initialize the secondary memory table. */
701 clear_secondary_mem ();
704 /* We don't have a stack slot for any spill reg yet. */
705 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
706 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
708 /* Initialize the save area information for caller-save, in case some
712 /* Compute which hard registers are now in use
713 as homes for pseudo registers.
714 This is done here rather than (eg) in global_alloc
715 because this point is reached even if not optimizing. */
716 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
719 /* A function that receives a nonlocal goto must save all call-saved
721 if (current_function_has_nonlocal_label)
722 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
723 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
724 regs_ever_live[i] = 1;
726 /* Find all the pseudo registers that didn't get hard regs
727 but do have known equivalent constants or memory slots.
728 These include parameters (known equivalent to parameter slots)
729 and cse'd or loop-moved constant memory addresses.
731 Record constant equivalents in reg_equiv_constant
732 so they will be substituted by find_reloads.
733 Record memory equivalents in reg_mem_equiv so they can
734 be substituted eventually by altering the REG-rtx's. */
736 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
740 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
741 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
742 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
743 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
744 pseudo_forbidden_regs
745 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
747 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
749 CLEAR_HARD_REG_SET (bad_spill_regs_global);
751 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
752 Also find all paradoxical subregs and find largest such for each pseudo.
753 On machines with small register classes, record hard registers that
754 are used for user variables. These can never be used for spills.
755 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
756 caller-saved registers must be marked live. */
758 num_eliminable_invariants = 0;
759 for (insn = first; insn; insn = NEXT_INSN (insn))
761 rtx set = single_set (insn);
763 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
764 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
766 if (! call_used_regs[i])
767 regs_ever_live[i] = 1;
769 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
771 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
773 #ifdef LEGITIMATE_PIC_OPERAND_P
774 && (! function_invariant_p (XEXP (note, 0))
776 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
780 rtx x = XEXP (note, 0);
781 i = REGNO (SET_DEST (set));
782 if (i > LAST_VIRTUAL_REGISTER)
784 if (GET_CODE (x) == MEM)
786 /* If the operand is a PLUS, the MEM may be shared,
787 so make sure we have an unshared copy here. */
788 if (GET_CODE (XEXP (x, 0)) == PLUS)
791 reg_equiv_memory_loc[i] = x;
793 else if (function_invariant_p (x))
795 if (GET_CODE (x) == PLUS)
797 /* This is PLUS of frame pointer and a constant,
798 and might be shared. Unshare it. */
799 reg_equiv_constant[i] = copy_rtx (x);
800 num_eliminable_invariants++;
802 else if (x == frame_pointer_rtx
803 || x == arg_pointer_rtx)
805 reg_equiv_constant[i] = x;
806 num_eliminable_invariants++;
808 else if (LEGITIMATE_CONSTANT_P (x))
809 reg_equiv_constant[i] = x;
811 reg_equiv_memory_loc[i]
812 = force_const_mem (GET_MODE (SET_DEST (set)), x);
817 /* If this register is being made equivalent to a MEM
818 and the MEM is not SET_SRC, the equivalencing insn
819 is one with the MEM as a SET_DEST and it occurs later.
820 So don't mark this insn now. */
821 if (GET_CODE (x) != MEM
822 || rtx_equal_p (SET_SRC (set), x))
824 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
829 /* If this insn is setting a MEM from a register equivalent to it,
830 this is the equivalencing insn. */
831 else if (set && GET_CODE (SET_DEST (set)) == MEM
832 && GET_CODE (SET_SRC (set)) == REG
833 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
834 && rtx_equal_p (SET_DEST (set),
835 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
836 reg_equiv_init[REGNO (SET_SRC (set))]
837 = gen_rtx_INSN_LIST (VOIDmode, insn,
838 reg_equiv_init[REGNO (SET_SRC (set))]);
841 scan_paradoxical_subregs (PATTERN (insn));
846 num_labels = max_label_num () - get_first_label_num ();
848 /* Allocate the tables used to store offset information at labels. */
849 /* We used to use alloca here, but the size of what it would try to
850 allocate would occasionally cause it to exceed the stack limit and
851 cause a core dump. */
852 real_known_ptr = xmalloc (num_labels);
854 = (int (*)[NUM_ELIMINABLE_REGS])
855 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
857 offsets_known_at = real_known_ptr - get_first_label_num ();
859 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
861 /* Alter each pseudo-reg rtx to contain its hard reg number.
862 Assign stack slots to the pseudos that lack hard regs or equivalents.
863 Do not touch virtual registers. */
865 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
868 /* If we have some registers we think can be eliminated, scan all insns to
869 see if there is an insn that sets one of these registers to something
870 other than itself plus a constant. If so, the register cannot be
871 eliminated. Doing this scan here eliminates an extra pass through the
872 main reload loop in the most common case where register elimination
874 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
875 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
876 || GET_CODE (insn) == CALL_INSN)
877 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
879 maybe_fix_stack_asms ();
881 insns_need_reload = 0;
882 something_needs_elimination = 0;
884 /* Initialize to -1, which means take the first spill register. */
887 /* Spill any hard regs that we know we can't eliminate. */
888 CLEAR_HARD_REG_SET (used_spill_regs);
889 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
890 if (! ep->can_eliminate)
891 spill_hard_reg (ep->from, 1);
893 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
894 if (frame_pointer_needed)
895 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
897 finish_spills (global);
899 /* From now on, we may need to generate moves differently. We may also
900 allow modifications of insns which cause them to not be recognized.
901 Any such modifications will be cleaned up during reload itself. */
902 reload_in_progress = 1;
904 /* This loop scans the entire function each go-round
905 and repeats until one repetition spills no additional hard regs. */
908 int something_changed;
911 HOST_WIDE_INT starting_frame_size;
913 /* Round size of stack frame to stack_alignment_needed. This must be done
914 here because the stack size may be a part of the offset computation
915 for register elimination, and there might have been new stack slots
916 created in the last iteration of this loop. */
917 if (cfun->stack_alignment_needed)
918 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
920 starting_frame_size = get_frame_size ();
922 set_initial_elim_offsets ();
923 set_initial_label_offsets ();
925 /* For each pseudo register that has an equivalent location defined,
926 try to eliminate any eliminable registers (such as the frame pointer)
927 assuming initial offsets for the replacement register, which
930 If the resulting location is directly addressable, substitute
931 the MEM we just got directly for the old REG.
933 If it is not addressable but is a constant or the sum of a hard reg
934 and constant, it is probably not addressable because the constant is
935 out of range, in that case record the address; we will generate
936 hairy code to compute the address in a register each time it is
937 needed. Similarly if it is a hard register, but one that is not
938 valid as an address register.
940 If the location is not addressable, but does not have one of the
941 above forms, assign a stack slot. We have to do this to avoid the
942 potential of producing lots of reloads if, e.g., a location involves
943 a pseudo that didn't get a hard register and has an equivalent memory
944 location that also involves a pseudo that didn't get a hard register.
946 Perhaps at some point we will improve reload_when_needed handling
947 so this problem goes away. But that's very hairy. */
949 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
950 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
952 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
954 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
956 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
957 else if (CONSTANT_P (XEXP (x, 0))
958 || (GET_CODE (XEXP (x, 0)) == REG
959 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
960 || (GET_CODE (XEXP (x, 0)) == PLUS
961 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
962 && (REGNO (XEXP (XEXP (x, 0), 0))
963 < FIRST_PSEUDO_REGISTER)
964 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
965 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
968 /* Make a new stack slot. Then indicate that something
969 changed so we go back and recompute offsets for
970 eliminable registers because the allocation of memory
971 below might change some offset. reg_equiv_{mem,address}
972 will be set up for this pseudo on the next pass around
974 reg_equiv_memory_loc[i] = 0;
975 reg_equiv_init[i] = 0;
980 if (caller_save_needed)
983 /* If we allocated another stack slot, redo elimination bookkeeping. */
984 if (starting_frame_size != get_frame_size ())
987 if (caller_save_needed)
989 save_call_clobbered_regs ();
990 /* That might have allocated new insn_chain structures. */
991 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
994 calculate_needs_all_insns (global);
996 CLEAR_REG_SET (&spilled_pseudos);
999 something_changed = 0;
1001 /* If we allocated any new memory locations, make another pass
1002 since it might have changed elimination offsets. */
1003 if (starting_frame_size != get_frame_size ())
1004 something_changed = 1;
1007 HARD_REG_SET to_spill;
1008 CLEAR_HARD_REG_SET (to_spill);
1009 update_eliminables (&to_spill);
1010 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1011 if (TEST_HARD_REG_BIT (to_spill, i))
1013 spill_hard_reg (i, 1);
1016 /* Regardless of the state of spills, if we previously had
1017 a register that we thought we could eliminate, but no can
1018 not eliminate, we must run another pass.
1020 Consider pseudos which have an entry in reg_equiv_* which
1021 reference an eliminable register. We must make another pass
1022 to update reg_equiv_* so that we do not substitute in the
1023 old value from when we thought the elimination could be
1025 something_changed = 1;
1029 select_reload_regs ();
1033 if (insns_need_reload != 0 || did_spill)
1034 something_changed |= finish_spills (global);
1036 if (! something_changed)
1039 if (caller_save_needed)
1040 delete_caller_save_insns ();
1042 obstack_free (&reload_obstack, reload_firstobj);
1045 /* If global-alloc was run, notify it of any register eliminations we have
1048 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1049 if (ep->can_eliminate)
1050 mark_elimination (ep->from, ep->to);
1052 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1053 If that insn didn't set the register (i.e., it copied the register to
1054 memory), just delete that insn instead of the equivalencing insn plus
1055 anything now dead. If we call delete_dead_insn on that insn, we may
1056 delete the insn that actually sets the register if the register dies
1057 there and that is incorrect. */
1059 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1061 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1064 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1066 rtx equiv_insn = XEXP (list, 0);
1067 if (GET_CODE (equiv_insn) == NOTE)
1069 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1070 delete_dead_insn (equiv_insn);
1073 PUT_CODE (equiv_insn, NOTE);
1074 NOTE_SOURCE_FILE (equiv_insn) = 0;
1075 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1081 /* Use the reload registers where necessary
1082 by generating move instructions to move the must-be-register
1083 values into or out of the reload registers. */
1085 if (insns_need_reload != 0 || something_needs_elimination
1086 || something_needs_operands_changed)
1088 HOST_WIDE_INT old_frame_size = get_frame_size ();
1090 reload_as_needed (global);
1092 if (old_frame_size != get_frame_size ())
1096 verify_initial_elim_offsets ();
1099 /* If we were able to eliminate the frame pointer, show that it is no
1100 longer live at the start of any basic block. If it ls live by
1101 virtue of being in a pseudo, that pseudo will be marked live
1102 and hence the frame pointer will be known to be live via that
1105 if (! frame_pointer_needed)
1106 for (i = 0; i < n_basic_blocks; i++)
1107 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1108 HARD_FRAME_POINTER_REGNUM);
1110 /* Come here (with failure set nonzero) if we can't get enough spill regs
1111 and we decide not to abort about it. */
1114 CLEAR_REG_SET (&spilled_pseudos);
1115 reload_in_progress = 0;
1117 /* Now eliminate all pseudo regs by modifying them into
1118 their equivalent memory references.
1119 The REG-rtx's for the pseudos are modified in place,
1120 so all insns that used to refer to them now refer to memory.
1122 For a reg that has a reg_equiv_address, all those insns
1123 were changed by reloading so that no insns refer to it any longer;
1124 but the DECL_RTL of a variable decl may refer to it,
1125 and if so this causes the debugging info to mention the variable. */
1127 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1132 int is_readonly = 0;
1134 if (reg_equiv_memory_loc[i])
1136 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1137 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1138 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1141 if (reg_equiv_mem[i])
1142 addr = XEXP (reg_equiv_mem[i], 0);
1144 if (reg_equiv_address[i])
1145 addr = reg_equiv_address[i];
1149 if (reg_renumber[i] < 0)
1151 rtx reg = regno_reg_rtx[i];
1152 PUT_CODE (reg, MEM);
1153 XEXP (reg, 0) = addr;
1154 REG_USERVAR_P (reg) = 0;
1155 RTX_UNCHANGING_P (reg) = is_readonly;
1156 MEM_IN_STRUCT_P (reg) = in_struct;
1157 MEM_SCALAR_P (reg) = is_scalar;
1158 /* We have no alias information about this newly created
1160 MEM_ALIAS_SET (reg) = 0;
1162 else if (reg_equiv_mem[i])
1163 XEXP (reg_equiv_mem[i], 0) = addr;
1167 /* We must set reload_completed now since the cleanup_subreg_operands call
1168 below will re-recognize each insn and reload may have generated insns
1169 which are only valid during and after reload. */
1170 reload_completed = 1;
1172 /* Make a pass over all the insns and delete all USEs which we inserted
1173 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1174 notes. Delete all CLOBBER insns that don't refer to the return value
1175 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1176 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1177 and regenerate REG_INC notes that may have been moved around. */
1179 for (insn = first; insn; insn = NEXT_INSN (insn))
1184 if (GET_CODE (insn) == CALL_INSN)
1185 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1187 CALL_INSN_FUNCTION_USAGE (insn));
1189 if ((GET_CODE (PATTERN (insn)) == USE
1190 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1191 || (GET_CODE (PATTERN (insn)) == CLOBBER
1192 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1193 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1195 PUT_CODE (insn, NOTE);
1196 NOTE_SOURCE_FILE (insn) = 0;
1197 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1201 pnote = ®_NOTES (insn);
1204 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1205 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1206 || REG_NOTE_KIND (*pnote) == REG_INC
1207 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1208 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1209 *pnote = XEXP (*pnote, 1);
1211 pnote = &XEXP (*pnote, 1);
1215 add_auto_inc_notes (insn, PATTERN (insn));
1218 /* And simplify (subreg (reg)) if it appears as an operand. */
1219 cleanup_subreg_operands (insn);
1222 /* If we are doing stack checking, give a warning if this function's
1223 frame size is larger than we expect. */
1224 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1226 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1227 static int verbose_warned = 0;
1229 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1230 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1231 size += UNITS_PER_WORD;
1233 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1235 warning ("frame size too large for reliable stack checking");
1236 if (! verbose_warned)
1238 warning ("try reducing the number of local variables");
1244 /* Indicate that we no longer have known memory locations or constants. */
1245 if (reg_equiv_constant)
1246 free (reg_equiv_constant);
1247 reg_equiv_constant = 0;
1248 if (reg_equiv_memory_loc)
1249 free (reg_equiv_memory_loc);
1250 reg_equiv_memory_loc = 0;
1253 free (real_known_ptr);
1257 free (reg_equiv_mem);
1258 free (reg_equiv_init);
1259 free (reg_equiv_address);
1260 free (reg_max_ref_width);
1261 free (reg_old_renumber);
1262 free (pseudo_previous_regs);
1263 free (pseudo_forbidden_regs);
1265 CLEAR_HARD_REG_SET (used_spill_regs);
1266 for (i = 0; i < n_spills; i++)
1267 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1269 /* Free all the insn_chain structures at once. */
1270 obstack_free (&reload_obstack, reload_startobj);
1271 unused_insn_chains = 0;
1276 /* Yet another special case. Unfortunately, reg-stack forces people to
1277 write incorrect clobbers in asm statements. These clobbers must not
1278 cause the register to appear in bad_spill_regs, otherwise we'll call
1279 fatal_insn later. We clear the corresponding regnos in the live
1280 register sets to avoid this.
1281 The whole thing is rather sick, I'm afraid. */
1284 maybe_fix_stack_asms ()
1287 const char *constraints[MAX_RECOG_OPERANDS];
1288 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1289 struct insn_chain *chain;
1291 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1294 HARD_REG_SET clobbered, allowed;
1297 if (! INSN_P (chain->insn)
1298 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1300 pat = PATTERN (chain->insn);
1301 if (GET_CODE (pat) != PARALLEL)
1304 CLEAR_HARD_REG_SET (clobbered);
1305 CLEAR_HARD_REG_SET (allowed);
1307 /* First, make a mask of all stack regs that are clobbered. */
1308 for (i = 0; i < XVECLEN (pat, 0); i++)
1310 rtx t = XVECEXP (pat, 0, i);
1311 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1312 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1315 /* Get the operand values and constraints out of the insn. */
1316 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1317 constraints, operand_mode);
1319 /* For every operand, see what registers are allowed. */
1320 for (i = 0; i < noperands; i++)
1322 const char *p = constraints[i];
1323 /* For every alternative, we compute the class of registers allowed
1324 for reloading in CLS, and merge its contents into the reg set
1326 int cls = (int) NO_REGS;
1332 if (c == '\0' || c == ',' || c == '#')
1334 /* End of one alternative - mark the regs in the current
1335 class, and reset the class. */
1336 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1341 } while (c != '\0' && c != ',');
1349 case '=': case '+': case '*': case '%': case '?': case '!':
1350 case '0': case '1': case '2': case '3': case '4': case 'm':
1351 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1352 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1353 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1358 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1363 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1367 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1372 /* Those of the registers which are clobbered, but allowed by the
1373 constraints, must be usable as reload registers. So clear them
1374 out of the life information. */
1375 AND_HARD_REG_SET (allowed, clobbered);
1376 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1377 if (TEST_HARD_REG_BIT (allowed, i))
1379 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1380 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1387 /* Copy the global variables n_reloads and rld into the corresponding elts
1390 copy_reloads (chain)
1391 struct insn_chain *chain;
1393 chain->n_reloads = n_reloads;
1395 = (struct reload *) obstack_alloc (&reload_obstack,
1396 n_reloads * sizeof (struct reload));
1397 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1398 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1401 /* Walk the chain of insns, and determine for each whether it needs reloads
1402 and/or eliminations. Build the corresponding insns_need_reload list, and
1403 set something_needs_elimination as appropriate. */
1405 calculate_needs_all_insns (global)
1408 struct insn_chain **pprev_reload = &insns_need_reload;
1409 struct insn_chain *chain, *next = 0;
1411 something_needs_elimination = 0;
1413 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1414 for (chain = reload_insn_chain; chain != 0; chain = next)
1416 rtx insn = chain->insn;
1420 /* Clear out the shortcuts. */
1421 chain->n_reloads = 0;
1422 chain->need_elim = 0;
1423 chain->need_reload = 0;
1424 chain->need_operand_change = 0;
1426 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1427 include REG_LABEL), we need to see what effects this has on the
1428 known offsets at labels. */
1430 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1431 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1432 set_label_offsets (insn, insn, 0);
1436 rtx old_body = PATTERN (insn);
1437 int old_code = INSN_CODE (insn);
1438 rtx old_notes = REG_NOTES (insn);
1439 int did_elimination = 0;
1440 int operands_changed = 0;
1441 rtx set = single_set (insn);
1443 /* Skip insns that only set an equivalence. */
1444 if (set && GET_CODE (SET_DEST (set)) == REG
1445 && reg_renumber[REGNO (SET_DEST (set))] < 0
1446 && reg_equiv_constant[REGNO (SET_DEST (set))])
1449 /* If needed, eliminate any eliminable registers. */
1450 if (num_eliminable || num_eliminable_invariants)
1451 did_elimination = eliminate_regs_in_insn (insn, 0);
1453 /* Analyze the instruction. */
1454 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1455 global, spill_reg_order);
1457 /* If a no-op set needs more than one reload, this is likely
1458 to be something that needs input address reloads. We
1459 can't get rid of this cleanly later, and it is of no use
1460 anyway, so discard it now.
1461 We only do this when expensive_optimizations is enabled,
1462 since this complements reload inheritance / output
1463 reload deletion, and it can make debugging harder. */
1464 if (flag_expensive_optimizations && n_reloads > 1)
1466 rtx set = single_set (insn);
1468 && SET_SRC (set) == SET_DEST (set)
1469 && GET_CODE (SET_SRC (set)) == REG
1470 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1472 PUT_CODE (insn, NOTE);
1473 NOTE_SOURCE_FILE (insn) = 0;
1474 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1475 /* Delete it from the reload chain */
1477 chain->prev->next = next;
1479 reload_insn_chain = next;
1481 next->prev = chain->prev;
1482 chain->next = unused_insn_chains;
1483 unused_insn_chains = chain;
1488 update_eliminable_offsets ();
1490 /* Remember for later shortcuts which insns had any reloads or
1491 register eliminations. */
1492 chain->need_elim = did_elimination;
1493 chain->need_reload = n_reloads > 0;
1494 chain->need_operand_change = operands_changed;
1496 /* Discard any register replacements done. */
1497 if (did_elimination)
1499 obstack_free (&reload_obstack, reload_insn_firstobj);
1500 PATTERN (insn) = old_body;
1501 INSN_CODE (insn) = old_code;
1502 REG_NOTES (insn) = old_notes;
1503 something_needs_elimination = 1;
1506 something_needs_operands_changed |= operands_changed;
1510 copy_reloads (chain);
1511 *pprev_reload = chain;
1512 pprev_reload = &chain->next_need_reload;
1519 /* Comparison function for qsort to decide which of two reloads
1520 should be handled first. *P1 and *P2 are the reload numbers. */
1523 reload_reg_class_lower (r1p, r2p)
1527 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1530 /* Consider required reloads before optional ones. */
1531 t = rld[r1].optional - rld[r2].optional;
1535 /* Count all solitary classes before non-solitary ones. */
1536 t = ((reg_class_size[(int) rld[r2].class] == 1)
1537 - (reg_class_size[(int) rld[r1].class] == 1));
1541 /* Aside from solitaires, consider all multi-reg groups first. */
1542 t = rld[r2].nregs - rld[r1].nregs;
1546 /* Consider reloads in order of increasing reg-class number. */
1547 t = (int) rld[r1].class - (int) rld[r2].class;
1551 /* If reloads are equally urgent, sort by reload number,
1552 so that the results of qsort leave nothing to chance. */
1556 /* The cost of spilling each hard reg. */
1557 static int spill_cost[FIRST_PSEUDO_REGISTER];
1559 /* When spilling multiple hard registers, we use SPILL_COST for the first
1560 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1561 only the first hard reg for a multi-reg pseudo. */
1562 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1564 /* Update the spill cost arrays, considering that pseudo REG is live. */
1570 int freq = REG_FREQ (reg);
1571 int r = reg_renumber[reg];
1574 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1575 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1578 SET_REGNO_REG_SET (&pseudos_counted, reg);
1583 spill_add_cost[r] += freq;
1585 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1587 spill_cost[r + nregs] += freq;
1590 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1591 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1594 order_regs_for_reload (chain)
1595 struct insn_chain *chain;
1598 HARD_REG_SET used_by_pseudos;
1599 HARD_REG_SET used_by_pseudos2;
1601 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1603 memset (spill_cost, 0, sizeof spill_cost);
1604 memset (spill_add_cost, 0, sizeof spill_add_cost);
1606 /* Count number of uses of each hard reg by pseudo regs allocated to it
1607 and then order them by decreasing use. First exclude hard registers
1608 that are live in or across this insn. */
1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1611 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1612 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1613 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1615 /* Now find out which pseudos are allocated to it, and update
1617 CLEAR_REG_SET (&pseudos_counted);
1619 EXECUTE_IF_SET_IN_REG_SET
1620 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1624 EXECUTE_IF_SET_IN_REG_SET
1625 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1629 CLEAR_REG_SET (&pseudos_counted);
1632 /* Vector of reload-numbers showing the order in which the reloads should
1634 static short reload_order[MAX_RELOADS];
1636 /* This is used to keep track of the spill regs used in one insn. */
1637 static HARD_REG_SET used_spill_regs_local;
1639 /* We decided to spill hard register SPILLED, which has a size of
1640 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1641 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1642 update SPILL_COST/SPILL_ADD_COST. */
1645 count_spilled_pseudo (spilled, spilled_nregs, reg)
1646 int spilled, spilled_nregs, reg;
1648 int r = reg_renumber[reg];
1649 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1651 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1652 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1655 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1657 spill_add_cost[r] -= REG_FREQ (reg);
1659 spill_cost[r + nregs] -= REG_FREQ (reg);
1662 /* Find reload register to use for reload number ORDER. */
1665 find_reg (chain, order)
1666 struct insn_chain *chain;
1669 int rnum = reload_order[order];
1670 struct reload *rl = rld + rnum;
1671 int best_cost = INT_MAX;
1675 HARD_REG_SET not_usable;
1676 HARD_REG_SET used_by_other_reload;
1678 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1679 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1680 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1682 CLEAR_HARD_REG_SET (used_by_other_reload);
1683 for (k = 0; k < order; k++)
1685 int other = reload_order[k];
1687 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1688 for (j = 0; j < rld[other].nregs; j++)
1689 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1692 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1694 unsigned int regno = i;
1696 if (! TEST_HARD_REG_BIT (not_usable, regno)
1697 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1698 && HARD_REGNO_MODE_OK (regno, rl->mode))
1700 int this_cost = spill_cost[regno];
1702 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1704 for (j = 1; j < this_nregs; j++)
1706 this_cost += spill_add_cost[regno + j];
1707 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1708 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1713 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1715 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1717 if (this_cost < best_cost
1718 /* Among registers with equal cost, prefer caller-saved ones, or
1719 use REG_ALLOC_ORDER if it is defined. */
1720 || (this_cost == best_cost
1721 #ifdef REG_ALLOC_ORDER
1722 && (inv_reg_alloc_order[regno]
1723 < inv_reg_alloc_order[best_reg])
1725 && call_used_regs[regno]
1726 && ! call_used_regs[best_reg]
1731 best_cost = this_cost;
1739 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1741 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1742 rl->regno = best_reg;
1744 EXECUTE_IF_SET_IN_REG_SET
1745 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1747 count_spilled_pseudo (best_reg, rl->nregs, j);
1750 EXECUTE_IF_SET_IN_REG_SET
1751 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1753 count_spilled_pseudo (best_reg, rl->nregs, j);
1756 for (i = 0; i < rl->nregs; i++)
1758 if (spill_cost[best_reg + i] != 0
1759 || spill_add_cost[best_reg + i] != 0)
1761 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1766 /* Find more reload regs to satisfy the remaining need of an insn, which
1768 Do it by ascending class number, since otherwise a reg
1769 might be spilled for a big class and might fail to count
1770 for a smaller class even though it belongs to that class. */
1773 find_reload_regs (chain)
1774 struct insn_chain *chain;
1778 /* In order to be certain of getting the registers we need,
1779 we must sort the reloads into order of increasing register class.
1780 Then our grabbing of reload registers will parallel the process
1781 that provided the reload registers. */
1782 for (i = 0; i < chain->n_reloads; i++)
1784 /* Show whether this reload already has a hard reg. */
1785 if (chain->rld[i].reg_rtx)
1787 int regno = REGNO (chain->rld[i].reg_rtx);
1788 chain->rld[i].regno = regno;
1790 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1793 chain->rld[i].regno = -1;
1794 reload_order[i] = i;
1797 n_reloads = chain->n_reloads;
1798 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1800 CLEAR_HARD_REG_SET (used_spill_regs_local);
1803 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1805 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1807 /* Compute the order of preference for hard registers to spill. */
1809 order_regs_for_reload (chain);
1811 for (i = 0; i < n_reloads; i++)
1813 int r = reload_order[i];
1815 /* Ignore reloads that got marked inoperative. */
1816 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1817 && ! rld[r].optional
1818 && rld[r].regno == -1)
1819 if (! find_reg (chain, i))
1821 spill_failure (chain->insn, rld[r].class);
1827 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1828 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1830 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1834 select_reload_regs ()
1836 struct insn_chain *chain;
1838 /* Try to satisfy the needs for each insn. */
1839 for (chain = insns_need_reload; chain != 0;
1840 chain = chain->next_need_reload)
1841 find_reload_regs (chain);
1844 /* Delete all insns that were inserted by emit_caller_save_insns during
1847 delete_caller_save_insns ()
1849 struct insn_chain *c = reload_insn_chain;
1853 while (c != 0 && c->is_caller_save_insn)
1855 struct insn_chain *next = c->next;
1858 if (insn == BLOCK_HEAD (c->block))
1859 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1860 if (insn == BLOCK_END (c->block))
1861 BLOCK_END (c->block) = PREV_INSN (insn);
1862 if (c == reload_insn_chain)
1863 reload_insn_chain = next;
1865 if (NEXT_INSN (insn) != 0)
1866 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1867 if (PREV_INSN (insn) != 0)
1868 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1871 next->prev = c->prev;
1873 c->prev->next = next;
1874 c->next = unused_insn_chains;
1875 unused_insn_chains = c;
1883 /* Handle the failure to find a register to spill.
1884 INSN should be one of the insns which needed this particular spill reg. */
1887 spill_failure (insn, class)
1889 enum reg_class class;
1891 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1892 if (asm_noperands (PATTERN (insn)) >= 0)
1893 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1894 reg_class_names[class]);
1897 error ("Unable to find a register to spill in class `%s'.",
1898 reg_class_names[class]);
1899 fatal_insn ("This is the insn:", insn);
1903 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1904 data that is dead in INSN. */
1907 delete_dead_insn (insn)
1910 rtx prev = prev_real_insn (insn);
1913 /* If the previous insn sets a register that dies in our insn, delete it
1915 if (prev && GET_CODE (PATTERN (prev)) == SET
1916 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1917 && reg_mentioned_p (prev_dest, PATTERN (insn))
1918 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1919 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1920 delete_dead_insn (prev);
1922 PUT_CODE (insn, NOTE);
1923 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1924 NOTE_SOURCE_FILE (insn) = 0;
1927 /* Modify the home of pseudo-reg I.
1928 The new home is present in reg_renumber[I].
1930 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1931 or it may be -1, meaning there is none or it is not relevant.
1932 This is used so that all pseudos spilled from a given hard reg
1933 can share one stack slot. */
1936 alter_reg (i, from_reg)
1940 /* When outputting an inline function, this can happen
1941 for a reg that isn't actually used. */
1942 if (regno_reg_rtx[i] == 0)
1945 /* If the reg got changed to a MEM at rtl-generation time,
1947 if (GET_CODE (regno_reg_rtx[i]) != REG)
1950 /* Modify the reg-rtx to contain the new hard reg
1951 number or else to contain its pseudo reg number. */
1952 REGNO (regno_reg_rtx[i])
1953 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1955 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1956 allocate a stack slot for it. */
1958 if (reg_renumber[i] < 0
1959 && REG_N_REFS (i) > 0
1960 && reg_equiv_constant[i] == 0
1961 && reg_equiv_memory_loc[i] == 0)
1964 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1965 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1968 /* Each pseudo reg has an inherent size which comes from its own mode,
1969 and a total size which provides room for paradoxical subregs
1970 which refer to the pseudo reg in wider modes.
1972 We can use a slot already allocated if it provides both
1973 enough inherent space and enough total space.
1974 Otherwise, we allocate a new slot, making sure that it has no less
1975 inherent space, and no less total space, then the previous slot. */
1978 /* No known place to spill from => no slot to reuse. */
1979 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1980 inherent_size == total_size ? 0 : -1);
1981 if (BYTES_BIG_ENDIAN)
1982 /* Cancel the big-endian correction done in assign_stack_local.
1983 Get the address of the beginning of the slot.
1984 This is so we can do a big-endian correction unconditionally
1986 adjust = inherent_size - total_size;
1988 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1990 /* Nothing can alias this slot except this pseudo. */
1991 MEM_ALIAS_SET (x) = new_alias_set ();
1994 /* Reuse a stack slot if possible. */
1995 else if (spill_stack_slot[from_reg] != 0
1996 && spill_stack_slot_width[from_reg] >= total_size
1997 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1999 x = spill_stack_slot[from_reg];
2001 /* Allocate a bigger slot. */
2004 /* Compute maximum size needed, both for inherent size
2005 and for total size. */
2006 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2009 if (spill_stack_slot[from_reg])
2011 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2013 mode = GET_MODE (spill_stack_slot[from_reg]);
2014 if (spill_stack_slot_width[from_reg] > total_size)
2015 total_size = spill_stack_slot_width[from_reg];
2018 /* Make a slot with that size. */
2019 x = assign_stack_local (mode, total_size,
2020 inherent_size == total_size ? 0 : -1);
2023 /* All pseudos mapped to this slot can alias each other. */
2024 if (spill_stack_slot[from_reg])
2025 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2027 MEM_ALIAS_SET (x) = new_alias_set ();
2029 if (BYTES_BIG_ENDIAN)
2031 /* Cancel the big-endian correction done in assign_stack_local.
2032 Get the address of the beginning of the slot.
2033 This is so we can do a big-endian correction unconditionally
2035 adjust = GET_MODE_SIZE (mode) - total_size;
2037 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2040 plus_constant (XEXP (x, 0), adjust));
2043 spill_stack_slot[from_reg] = stack_slot;
2044 spill_stack_slot_width[from_reg] = total_size;
2047 /* On a big endian machine, the "address" of the slot
2048 is the address of the low part that fits its inherent mode. */
2049 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2050 adjust += (total_size - inherent_size);
2052 /* If we have any adjustment to make, or if the stack slot is the
2053 wrong mode, make a new stack slot. */
2054 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2055 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2057 /* Save the stack slot for later. */
2058 reg_equiv_memory_loc[i] = x;
2062 /* Mark the slots in regs_ever_live for the hard regs
2063 used by pseudo-reg number REGNO. */
2066 mark_home_live (regno)
2069 register int i, lim;
2071 i = reg_renumber[regno];
2074 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2076 regs_ever_live[i++] = 1;
2079 /* This function handles the tracking of elimination offsets around branches.
2081 X is a piece of RTL being scanned.
2083 INSN is the insn that it came from, if any.
2085 INITIAL_P is non-zero if we are to set the offset to be the initial
2086 offset and zero if we are setting the offset of the label to be the
2090 set_label_offsets (x, insn, initial_p)
2095 enum rtx_code code = GET_CODE (x);
2098 struct elim_table *p;
2103 if (LABEL_REF_NONLOCAL_P (x))
2108 /* ... fall through ... */
2111 /* If we know nothing about this label, set the desired offsets. Note
2112 that this sets the offset at a label to be the offset before a label
2113 if we don't know anything about the label. This is not correct for
2114 the label after a BARRIER, but is the best guess we can make. If
2115 we guessed wrong, we will suppress an elimination that might have
2116 been possible had we been able to guess correctly. */
2118 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2120 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2121 offsets_at[CODE_LABEL_NUMBER (x)][i]
2122 = (initial_p ? reg_eliminate[i].initial_offset
2123 : reg_eliminate[i].offset);
2124 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2127 /* Otherwise, if this is the definition of a label and it is
2128 preceded by a BARRIER, set our offsets to the known offset of
2132 && (tem = prev_nonnote_insn (insn)) != 0
2133 && GET_CODE (tem) == BARRIER)
2134 set_offsets_for_label (insn);
2136 /* If neither of the above cases is true, compare each offset
2137 with those previously recorded and suppress any eliminations
2138 where the offsets disagree. */
2140 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2141 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2142 != (initial_p ? reg_eliminate[i].initial_offset
2143 : reg_eliminate[i].offset))
2144 reg_eliminate[i].can_eliminate = 0;
2149 set_label_offsets (PATTERN (insn), insn, initial_p);
2151 /* ... fall through ... */
2155 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2156 and hence must have all eliminations at their initial offsets. */
2157 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2158 if (REG_NOTE_KIND (tem) == REG_LABEL)
2159 set_label_offsets (XEXP (tem, 0), insn, 1);
2165 /* Each of the labels in the parallel or address vector must be
2166 at their initial offsets. We want the first field for PARALLEL
2167 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2169 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2170 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2175 /* We only care about setting PC. If the source is not RETURN,
2176 IF_THEN_ELSE, or a label, disable any eliminations not at
2177 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2178 isn't one of those possibilities. For branches to a label,
2179 call ourselves recursively.
2181 Note that this can disable elimination unnecessarily when we have
2182 a non-local goto since it will look like a non-constant jump to
2183 someplace in the current function. This isn't a significant
2184 problem since such jumps will normally be when all elimination
2185 pairs are back to their initial offsets. */
2187 if (SET_DEST (x) != pc_rtx)
2190 switch (GET_CODE (SET_SRC (x)))
2197 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2201 tem = XEXP (SET_SRC (x), 1);
2202 if (GET_CODE (tem) == LABEL_REF)
2203 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2204 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2207 tem = XEXP (SET_SRC (x), 2);
2208 if (GET_CODE (tem) == LABEL_REF)
2209 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2210 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2218 /* If we reach here, all eliminations must be at their initial
2219 offset because we are doing a jump to a variable address. */
2220 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2221 if (p->offset != p->initial_offset)
2222 p->can_eliminate = 0;
2230 /* Scan X and replace any eliminable registers (such as fp) with a
2231 replacement (such as sp), plus an offset.
2233 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2234 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2235 MEM, we are allowed to replace a sum of a register and the constant zero
2236 with the register, which we cannot do outside a MEM. In addition, we need
2237 to record the fact that a register is referenced outside a MEM.
2239 If INSN is an insn, it is the insn containing X. If we replace a REG
2240 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2241 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2242 the REG is being modified.
2244 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2245 That's used when we eliminate in expressions stored in notes.
2246 This means, do not set ref_outside_mem even if the reference
2249 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2250 replacements done assuming all offsets are at their initial values. If
2251 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2252 encounter, return the actual location so that find_reloads will do
2253 the proper thing. */
2256 eliminate_regs (x, mem_mode, insn)
2258 enum machine_mode mem_mode;
2261 enum rtx_code code = GET_CODE (x);
2262 struct elim_table *ep;
2269 if (! current_function_decl)
2288 /* This is only for the benefit of the debugging backends, which call
2289 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2290 removed after CSE. */
2291 new = eliminate_regs (XEXP (x, 0), 0, insn);
2292 if (GET_CODE (new) == MEM)
2293 return XEXP (new, 0);
2299 /* First handle the case where we encounter a bare register that
2300 is eliminable. Replace it with a PLUS. */
2301 if (regno < FIRST_PSEUDO_REGISTER)
2303 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2305 if (ep->from_rtx == x && ep->can_eliminate)
2306 return plus_constant (ep->to_rtx, ep->previous_offset);
2309 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2310 && reg_equiv_constant[regno]
2311 && ! CONSTANT_P (reg_equiv_constant[regno]))
2312 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2316 /* You might think handling MINUS in a manner similar to PLUS is a
2317 good idea. It is not. It has been tried multiple times and every
2318 time the change has had to have been reverted.
2320 Other parts of reload know a PLUS is special (gen_reload for example)
2321 and require special code to handle code a reloaded PLUS operand.
2323 Also consider backends where the flags register is clobbered by a
2324 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2325 lea instruction comes to mind). If we try to reload a MINUS, we
2326 may kill the flags register that was holding a useful value.
2328 So, please before trying to handle MINUS, consider reload as a
2329 whole instead of this little section as well as the backend issues. */
2331 /* If this is the sum of an eliminable register and a constant, rework
2333 if (GET_CODE (XEXP (x, 0)) == REG
2334 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2335 && CONSTANT_P (XEXP (x, 1)))
2337 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2339 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2341 /* The only time we want to replace a PLUS with a REG (this
2342 occurs when the constant operand of the PLUS is the negative
2343 of the offset) is when we are inside a MEM. We won't want
2344 to do so at other times because that would change the
2345 structure of the insn in a way that reload can't handle.
2346 We special-case the commonest situation in
2347 eliminate_regs_in_insn, so just replace a PLUS with a
2348 PLUS here, unless inside a MEM. */
2349 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2350 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2353 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2354 plus_constant (XEXP (x, 1),
2355 ep->previous_offset));
2358 /* If the register is not eliminable, we are done since the other
2359 operand is a constant. */
2363 /* If this is part of an address, we want to bring any constant to the
2364 outermost PLUS. We will do this by doing register replacement in
2365 our operands and seeing if a constant shows up in one of them.
2367 Note that there is no risk of modifying the structure of the insn,
2368 since we only get called for its operands, thus we are either
2369 modifying the address inside a MEM, or something like an address
2370 operand of a load-address insn. */
2373 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2374 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2376 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2378 /* If one side is a PLUS and the other side is a pseudo that
2379 didn't get a hard register but has a reg_equiv_constant,
2380 we must replace the constant here since it may no longer
2381 be in the position of any operand. */
2382 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2383 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2384 && reg_renumber[REGNO (new1)] < 0
2385 && reg_equiv_constant != 0
2386 && reg_equiv_constant[REGNO (new1)] != 0)
2387 new1 = reg_equiv_constant[REGNO (new1)];
2388 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2389 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2390 && reg_renumber[REGNO (new0)] < 0
2391 && reg_equiv_constant[REGNO (new0)] != 0)
2392 new0 = reg_equiv_constant[REGNO (new0)];
2394 new = form_sum (new0, new1);
2396 /* As above, if we are not inside a MEM we do not want to
2397 turn a PLUS into something else. We might try to do so here
2398 for an addition of 0 if we aren't optimizing. */
2399 if (! mem_mode && GET_CODE (new) != PLUS)
2400 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2408 /* If this is the product of an eliminable register and a
2409 constant, apply the distribute law and move the constant out
2410 so that we have (plus (mult ..) ..). This is needed in order
2411 to keep load-address insns valid. This case is pathological.
2412 We ignore the possibility of overflow here. */
2413 if (GET_CODE (XEXP (x, 0)) == REG
2414 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2415 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2416 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2418 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2421 /* Refs inside notes don't count for this purpose. */
2422 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2423 || GET_CODE (insn) == INSN_LIST)))
2424 ep->ref_outside_mem = 1;
2427 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2428 ep->previous_offset * INTVAL (XEXP (x, 1)));
2431 /* ... fall through ... */
2435 /* See comments before PLUS about handling MINUS. */
2437 case DIV: case UDIV:
2438 case MOD: case UMOD:
2439 case AND: case IOR: case XOR:
2440 case ROTATERT: case ROTATE:
2441 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2443 case GE: case GT: case GEU: case GTU:
2444 case LE: case LT: case LEU: case LTU:
2446 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2448 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2450 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2451 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2456 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2459 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2460 if (new != XEXP (x, 0))
2462 /* If this is a REG_DEAD note, it is not valid anymore.
2463 Using the eliminated version could result in creating a
2464 REG_DEAD note for the stack or frame pointer. */
2465 if (GET_MODE (x) == REG_DEAD)
2467 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2470 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2474 /* ... fall through ... */
2477 /* Now do eliminations in the rest of the chain. If this was
2478 an EXPR_LIST, this might result in allocating more memory than is
2479 strictly needed, but it simplifies the code. */
2482 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2483 if (new != XEXP (x, 1))
2484 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2492 case STRICT_LOW_PART:
2494 case SIGN_EXTEND: case ZERO_EXTEND:
2495 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2496 case FLOAT: case FIX:
2497 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2501 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2502 if (new != XEXP (x, 0))
2503 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2507 /* Similar to above processing, but preserve SUBREG_BYTE.
2508 Convert (subreg (mem)) to (mem) if not paradoxical.
2509 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2510 pseudo didn't get a hard reg, we must replace this with the
2511 eliminated version of the memory location because push_reloads
2512 may do the replacement in certain circumstances. */
2513 if (GET_CODE (SUBREG_REG (x)) == REG
2514 && (GET_MODE_SIZE (GET_MODE (x))
2515 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2516 && reg_equiv_memory_loc != 0
2517 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2519 new = SUBREG_REG (x);
2522 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2524 if (new != SUBREG_REG (x))
2526 int x_size = GET_MODE_SIZE (GET_MODE (x));
2527 int new_size = GET_MODE_SIZE (GET_MODE (new));
2529 if (GET_CODE (new) == MEM
2530 && ((x_size < new_size
2531 #ifdef WORD_REGISTER_OPERATIONS
2532 /* On these machines, combine can create rtl of the form
2533 (set (subreg:m1 (reg:m2 R) 0) ...)
2534 where m1 < m2, and expects something interesting to
2535 happen to the entire word. Moreover, it will use the
2536 (reg:m2 R) later, expecting all bits to be preserved.
2537 So if the number of words is the same, preserve the
2538 subreg so that push_reloads can see it. */
2539 && ! ((x_size - 1) / UNITS_PER_WORD
2540 == (new_size -1 ) / UNITS_PER_WORD)
2543 || x_size == new_size)
2546 int offset = SUBREG_BYTE (x);
2547 enum machine_mode mode = GET_MODE (x);
2549 PUT_MODE (new, mode);
2550 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2554 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2560 /* This is only for the benefit of the debugging backends, which call
2561 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2562 removed after CSE. */
2563 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2564 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2566 /* Our only special processing is to pass the mode of the MEM to our
2567 recursive call and copy the flags. While we are here, handle this
2568 case more efficiently. */
2570 replace_equiv_address_nv (x,
2571 eliminate_regs (XEXP (x, 0),
2572 GET_MODE (x), insn));
2575 /* Handle insn_list USE that a call to a pure function may generate. */
2576 new = eliminate_regs (XEXP (x, 0), 0, insn);
2577 if (new != XEXP (x, 0))
2578 return gen_rtx_USE (GET_MODE (x), new);
2590 /* Process each of our operands recursively. If any have changed, make a
2592 fmt = GET_RTX_FORMAT (code);
2593 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2597 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2598 if (new != XEXP (x, i) && ! copied)
2600 rtx new_x = rtx_alloc (code);
2602 (sizeof (*new_x) - sizeof (new_x->fld)
2603 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2609 else if (*fmt == 'E')
2612 for (j = 0; j < XVECLEN (x, i); j++)
2614 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2615 if (new != XVECEXP (x, i, j) && ! copied_vec)
2617 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2621 rtx new_x = rtx_alloc (code);
2623 (sizeof (*new_x) - sizeof (new_x->fld)
2624 + (sizeof (new_x->fld[0])
2625 * GET_RTX_LENGTH (code))));
2629 XVEC (x, i) = new_v;
2632 XVECEXP (x, i, j) = new;
2640 /* Scan rtx X for modifications of elimination target registers. Update
2641 the table of eliminables to reflect the changed state. MEM_MODE is
2642 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2645 elimination_effects (x, mem_mode)
2647 enum machine_mode mem_mode;
2650 enum rtx_code code = GET_CODE (x);
2651 struct elim_table *ep;
2677 /* First handle the case where we encounter a bare register that
2678 is eliminable. Replace it with a PLUS. */
2679 if (regno < FIRST_PSEUDO_REGISTER)
2681 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2683 if (ep->from_rtx == x && ep->can_eliminate)
2686 ep->ref_outside_mem = 1;
2691 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2692 && reg_equiv_constant[regno]
2693 && ! CONSTANT_P (reg_equiv_constant[regno]))
2694 elimination_effects (reg_equiv_constant[regno], mem_mode);
2703 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2704 if (ep->to_rtx == XEXP (x, 0))
2706 int size = GET_MODE_SIZE (mem_mode);
2708 /* If more bytes than MEM_MODE are pushed, account for them. */
2709 #ifdef PUSH_ROUNDING
2710 if (ep->to_rtx == stack_pointer_rtx)
2711 size = PUSH_ROUNDING (size);
2713 if (code == PRE_DEC || code == POST_DEC)
2715 else if (code == PRE_INC || code == POST_INC)
2717 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2718 && GET_CODE (XEXP (x, 1)) == PLUS
2719 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2720 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2721 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2724 /* These two aren't unary operators. */
2725 if (code == POST_MODIFY || code == PRE_MODIFY)
2728 /* Fall through to generic unary operation case. */
2729 case STRICT_LOW_PART:
2731 case SIGN_EXTEND: case ZERO_EXTEND:
2732 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2733 case FLOAT: case FIX:
2734 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2738 elimination_effects (XEXP (x, 0), mem_mode);
2742 if (GET_CODE (SUBREG_REG (x)) == REG
2743 && (GET_MODE_SIZE (GET_MODE (x))
2744 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2745 && reg_equiv_memory_loc != 0
2746 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2749 elimination_effects (SUBREG_REG (x), mem_mode);
2753 /* If using a register that is the source of an eliminate we still
2754 think can be performed, note it cannot be performed since we don't
2755 know how this register is used. */
2756 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2757 if (ep->from_rtx == XEXP (x, 0))
2758 ep->can_eliminate = 0;
2760 elimination_effects (XEXP (x, 0), mem_mode);
2764 /* If clobbering a register that is the replacement register for an
2765 elimination we still think can be performed, note that it cannot
2766 be performed. Otherwise, we need not be concerned about it. */
2767 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2768 if (ep->to_rtx == XEXP (x, 0))
2769 ep->can_eliminate = 0;
2771 elimination_effects (XEXP (x, 0), mem_mode);
2775 /* Check for setting a register that we know about. */
2776 if (GET_CODE (SET_DEST (x)) == REG)
2778 /* See if this is setting the replacement register for an
2781 If DEST is the hard frame pointer, we do nothing because we
2782 assume that all assignments to the frame pointer are for
2783 non-local gotos and are being done at a time when they are valid
2784 and do not disturb anything else. Some machines want to
2785 eliminate a fake argument pointer (or even a fake frame pointer)
2786 with either the real frame or the stack pointer. Assignments to
2787 the hard frame pointer must not prevent this elimination. */
2789 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2791 if (ep->to_rtx == SET_DEST (x)
2792 && SET_DEST (x) != hard_frame_pointer_rtx)
2794 /* If it is being incremented, adjust the offset. Otherwise,
2795 this elimination can't be done. */
2796 rtx src = SET_SRC (x);
2798 if (GET_CODE (src) == PLUS
2799 && XEXP (src, 0) == SET_DEST (x)
2800 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2801 ep->offset -= INTVAL (XEXP (src, 1));
2803 ep->can_eliminate = 0;
2807 elimination_effects (SET_DEST (x), 0);
2808 elimination_effects (SET_SRC (x), 0);
2812 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2815 /* Our only special processing is to pass the mode of the MEM to our
2817 elimination_effects (XEXP (x, 0), GET_MODE (x));
2824 fmt = GET_RTX_FORMAT (code);
2825 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2828 elimination_effects (XEXP (x, i), mem_mode);
2829 else if (*fmt == 'E')
2830 for (j = 0; j < XVECLEN (x, i); j++)
2831 elimination_effects (XVECEXP (x, i, j), mem_mode);
2835 /* Descend through rtx X and verify that no references to eliminable registers
2836 remain. If any do remain, mark the involved register as not
2840 check_eliminable_occurrences (x)
2850 code = GET_CODE (x);
2852 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2854 struct elim_table *ep;
2856 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2857 if (ep->from_rtx == x && ep->can_eliminate)
2858 ep->can_eliminate = 0;
2862 fmt = GET_RTX_FORMAT (code);
2863 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2866 check_eliminable_occurrences (XEXP (x, i));
2867 else if (*fmt == 'E')
2870 for (j = 0; j < XVECLEN (x, i); j++)
2871 check_eliminable_occurrences (XVECEXP (x, i, j));
2876 /* Scan INSN and eliminate all eliminable registers in it.
2878 If REPLACE is nonzero, do the replacement destructively. Also
2879 delete the insn as dead it if it is setting an eliminable register.
2881 If REPLACE is zero, do all our allocations in reload_obstack.
2883 If no eliminations were done and this insn doesn't require any elimination
2884 processing (these are not identical conditions: it might be updating sp,
2885 but not referencing fp; this needs to be seen during reload_as_needed so
2886 that the offset between fp and sp can be taken into consideration), zero
2887 is returned. Otherwise, 1 is returned. */
2890 eliminate_regs_in_insn (insn, replace)
2894 int icode = recog_memoized (insn);
2895 rtx old_body = PATTERN (insn);
2896 int insn_is_asm = asm_noperands (old_body) >= 0;
2897 rtx old_set = single_set (insn);
2901 rtx substed_operand[MAX_RECOG_OPERANDS];
2902 rtx orig_operand[MAX_RECOG_OPERANDS];
2903 struct elim_table *ep;
2905 if (! insn_is_asm && icode < 0)
2907 if (GET_CODE (PATTERN (insn)) == USE
2908 || GET_CODE (PATTERN (insn)) == CLOBBER
2909 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2910 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2911 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2916 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2917 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2919 /* Check for setting an eliminable register. */
2920 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2921 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2923 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2924 /* If this is setting the frame pointer register to the
2925 hardware frame pointer register and this is an elimination
2926 that will be done (tested above), this insn is really
2927 adjusting the frame pointer downward to compensate for
2928 the adjustment done before a nonlocal goto. */
2929 if (ep->from == FRAME_POINTER_REGNUM
2930 && ep->to == HARD_FRAME_POINTER_REGNUM)
2932 rtx src = SET_SRC (old_set);
2933 int offset = 0, ok = 0;
2934 rtx prev_insn, prev_set;
2936 if (src == ep->to_rtx)
2938 else if (GET_CODE (src) == PLUS
2939 && GET_CODE (XEXP (src, 0)) == CONST_INT
2940 && XEXP (src, 1) == ep->to_rtx)
2941 offset = INTVAL (XEXP (src, 0)), ok = 1;
2942 else if (GET_CODE (src) == PLUS
2943 && GET_CODE (XEXP (src, 1)) == CONST_INT
2944 && XEXP (src, 0) == ep->to_rtx)
2945 offset = INTVAL (XEXP (src, 1)), ok = 1;
2946 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2947 && (prev_set = single_set (prev_insn)) != 0
2948 && rtx_equal_p (SET_DEST (prev_set), src))
2950 src = SET_SRC (prev_set);
2951 if (src == ep->to_rtx)
2953 else if (GET_CODE (src) == PLUS
2954 && GET_CODE (XEXP (src, 0)) == CONST_INT
2955 && XEXP (src, 1) == ep->to_rtx)
2956 offset = INTVAL (XEXP (src, 0)), ok = 1;
2957 else if (GET_CODE (src) == PLUS
2958 && GET_CODE (XEXP (src, 1)) == CONST_INT
2959 && XEXP (src, 0) == ep->to_rtx)
2960 offset = INTVAL (XEXP (src, 1)), ok = 1;
2968 = plus_constant (ep->to_rtx, offset - ep->offset);
2970 /* First see if this insn remains valid when we
2971 make the change. If not, keep the INSN_CODE
2972 the same and let reload fit it up. */
2973 validate_change (insn, &SET_SRC (old_set), src, 1);
2974 validate_change (insn, &SET_DEST (old_set),
2976 if (! apply_change_group ())
2978 SET_SRC (old_set) = src;
2979 SET_DEST (old_set) = ep->to_rtx;
2989 /* In this case this insn isn't serving a useful purpose. We
2990 will delete it in reload_as_needed once we know that this
2991 elimination is, in fact, being done.
2993 If REPLACE isn't set, we can't delete this insn, but needn't
2994 process it since it won't be used unless something changes. */
2997 delete_dead_insn (insn);
3005 /* We allow one special case which happens to work on all machines we
3006 currently support: a single set with the source being a PLUS of an
3007 eliminable register and a constant. */
3009 && GET_CODE (SET_DEST (old_set)) == REG
3010 && GET_CODE (SET_SRC (old_set)) == PLUS
3011 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3012 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3013 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3015 rtx reg = XEXP (SET_SRC (old_set), 0);
3016 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3018 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3019 if (ep->from_rtx == reg && ep->can_eliminate)
3021 offset += ep->offset;
3026 /* We assume here that if we need a PARALLEL with
3027 CLOBBERs for this assignment, we can do with the
3028 MATCH_SCRATCHes that add_clobbers allocates.
3029 There's not much we can do if that doesn't work. */
3030 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3034 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3037 rtvec vec = rtvec_alloc (num_clobbers + 1);
3039 vec->elem[0] = PATTERN (insn);
3040 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3041 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3043 if (INSN_CODE (insn) < 0)
3048 new_body = old_body;
3051 new_body = copy_insn (old_body);
3052 if (REG_NOTES (insn))
3053 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3055 PATTERN (insn) = new_body;
3056 old_set = single_set (insn);
3058 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3059 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3062 /* This can't have an effect on elimination offsets, so skip right
3068 /* Determine the effects of this insn on elimination offsets. */
3069 elimination_effects (old_body, 0);
3071 /* Eliminate all eliminable registers occurring in operands that
3072 can be handled by reload. */
3073 extract_insn (insn);
3075 for (i = 0; i < recog_data.n_operands; i++)
3077 orig_operand[i] = recog_data.operand[i];
3078 substed_operand[i] = recog_data.operand[i];
3080 /* For an asm statement, every operand is eliminable. */
3081 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3083 /* Check for setting a register that we know about. */
3084 if (recog_data.operand_type[i] != OP_IN
3085 && GET_CODE (orig_operand[i]) == REG)
3087 /* If we are assigning to a register that can be eliminated, it
3088 must be as part of a PARALLEL, since the code above handles
3089 single SETs. We must indicate that we can no longer
3090 eliminate this reg. */
3091 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3093 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3094 ep->can_eliminate = 0;
3097 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3098 replace ? insn : NULL_RTX);
3099 if (substed_operand[i] != orig_operand[i])
3100 val = any_changes = 1;
3101 /* Terminate the search in check_eliminable_occurrences at
3103 *recog_data.operand_loc[i] = 0;
3105 /* If an output operand changed from a REG to a MEM and INSN is an
3106 insn, write a CLOBBER insn. */
3107 if (recog_data.operand_type[i] != OP_IN
3108 && GET_CODE (orig_operand[i]) == REG
3109 && GET_CODE (substed_operand[i]) == MEM
3111 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3116 for (i = 0; i < recog_data.n_dups; i++)
3117 *recog_data.dup_loc[i]
3118 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3120 /* If any eliminable remain, they aren't eliminable anymore. */
3121 check_eliminable_occurrences (old_body);
3123 /* Substitute the operands; the new values are in the substed_operand
3125 for (i = 0; i < recog_data.n_operands; i++)
3126 *recog_data.operand_loc[i] = substed_operand[i];
3127 for (i = 0; i < recog_data.n_dups; i++)
3128 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3130 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3131 re-recognize the insn. We do this in case we had a simple addition
3132 but now can do this as a load-address. This saves an insn in this
3134 If re-recognition fails, the old insn code number will still be used,
3135 and some register operands may have changed into PLUS expressions.
3136 These will be handled by find_reloads by loading them into a register
3141 /* If we aren't replacing things permanently and we changed something,
3142 make another copy to ensure that all the RTL is new. Otherwise
3143 things can go wrong if find_reload swaps commutative operands
3144 and one is inside RTL that has been copied while the other is not. */
3145 new_body = old_body;
3148 new_body = copy_insn (old_body);
3149 if (REG_NOTES (insn))
3150 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3152 PATTERN (insn) = new_body;
3154 /* If we had a move insn but now we don't, rerecognize it. This will
3155 cause spurious re-recognition if the old move had a PARALLEL since
3156 the new one still will, but we can't call single_set without
3157 having put NEW_BODY into the insn and the re-recognition won't
3158 hurt in this rare case. */
3159 /* ??? Why this huge if statement - why don't we just rerecognize the
3163 && ((GET_CODE (SET_SRC (old_set)) == REG
3164 && (GET_CODE (new_body) != SET
3165 || GET_CODE (SET_SRC (new_body)) != REG))
3166 /* If this was a load from or store to memory, compare
3167 the MEM in recog_data.operand to the one in the insn.
3168 If they are not equal, then rerecognize the insn. */
3170 && ((GET_CODE (SET_SRC (old_set)) == MEM
3171 && SET_SRC (old_set) != recog_data.operand[1])
3172 || (GET_CODE (SET_DEST (old_set)) == MEM
3173 && SET_DEST (old_set) != recog_data.operand[0])))
3174 /* If this was an add insn before, rerecognize. */
3175 || GET_CODE (SET_SRC (old_set)) == PLUS))
3177 int new_icode = recog (PATTERN (insn), insn, 0);
3179 INSN_CODE (insn) = icode;
3183 /* Restore the old body. If there were any changes to it, we made a copy
3184 of it while the changes were still in place, so we'll correctly return
3185 a modified insn below. */
3188 /* Restore the old body. */
3189 for (i = 0; i < recog_data.n_operands; i++)
3190 *recog_data.operand_loc[i] = orig_operand[i];
3191 for (i = 0; i < recog_data.n_dups; i++)
3192 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3195 /* Update all elimination pairs to reflect the status after the current
3196 insn. The changes we make were determined by the earlier call to
3197 elimination_effects.
3199 We also detect a cases where register elimination cannot be done,
3200 namely, if a register would be both changed and referenced outside a MEM
3201 in the resulting insn since such an insn is often undefined and, even if
3202 not, we cannot know what meaning will be given to it. Note that it is
3203 valid to have a register used in an address in an insn that changes it
3204 (presumably with a pre- or post-increment or decrement).
3206 If anything changes, return nonzero. */
3208 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3210 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3211 ep->can_eliminate = 0;
3213 ep->ref_outside_mem = 0;
3215 if (ep->previous_offset != ep->offset)
3220 /* If we changed something, perform elimination in REG_NOTES. This is
3221 needed even when REPLACE is zero because a REG_DEAD note might refer
3222 to a register that we eliminate and could cause a different number
3223 of spill registers to be needed in the final reload pass than in
3225 if (val && REG_NOTES (insn) != 0)
3226 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3231 /* Loop through all elimination pairs.
3232 Recalculate the number not at initial offset.
3234 Compute the maximum offset (minimum offset if the stack does not
3235 grow downward) for each elimination pair. */
3238 update_eliminable_offsets ()
3240 struct elim_table *ep;
3242 num_not_at_initial_offset = 0;
3243 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3245 ep->previous_offset = ep->offset;
3246 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3247 num_not_at_initial_offset++;
3251 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3252 replacement we currently believe is valid, mark it as not eliminable if X
3253 modifies DEST in any way other than by adding a constant integer to it.
3255 If DEST is the frame pointer, we do nothing because we assume that
3256 all assignments to the hard frame pointer are nonlocal gotos and are being
3257 done at a time when they are valid and do not disturb anything else.
3258 Some machines want to eliminate a fake argument pointer with either the
3259 frame or stack pointer. Assignments to the hard frame pointer must not
3260 prevent this elimination.
3262 Called via note_stores from reload before starting its passes to scan
3263 the insns of the function. */
3266 mark_not_eliminable (dest, x, data)
3269 void *data ATTRIBUTE_UNUSED;
3271 register unsigned int i;
3273 /* A SUBREG of a hard register here is just changing its mode. We should
3274 not see a SUBREG of an eliminable hard register, but check just in
3276 if (GET_CODE (dest) == SUBREG)
3277 dest = SUBREG_REG (dest);
3279 if (dest == hard_frame_pointer_rtx)
3282 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3283 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3284 && (GET_CODE (x) != SET
3285 || GET_CODE (SET_SRC (x)) != PLUS
3286 || XEXP (SET_SRC (x), 0) != dest
3287 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3289 reg_eliminate[i].can_eliminate_previous
3290 = reg_eliminate[i].can_eliminate = 0;
3295 /* Verify that the initial elimination offsets did not change since the
3296 last call to set_initial_elim_offsets. This is used to catch cases
3297 where something illegal happened during reload_as_needed that could
3298 cause incorrect code to be generated if we did not check for it. */
3301 verify_initial_elim_offsets ()
3305 #ifdef ELIMINABLE_REGS
3306 struct elim_table *ep;
3308 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3310 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3311 if (t != ep->initial_offset)
3315 INITIAL_FRAME_POINTER_OFFSET (t);
3316 if (t != reg_eliminate[0].initial_offset)
3321 /* Reset all offsets on eliminable registers to their initial values. */
3324 set_initial_elim_offsets ()
3326 struct elim_table *ep = reg_eliminate;
3328 #ifdef ELIMINABLE_REGS
3329 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3331 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3332 ep->previous_offset = ep->offset = ep->initial_offset;
3335 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3336 ep->previous_offset = ep->offset = ep->initial_offset;
3339 num_not_at_initial_offset = 0;
3342 /* Initialize the known label offsets.
3343 Set a known offset for each forced label to be at the initial offset
3344 of each elimination. We do this because we assume that all
3345 computed jumps occur from a location where each elimination is
3346 at its initial offset.
3347 For all other labels, show that we don't know the offsets. */
3350 set_initial_label_offsets ()
3353 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3355 for (x = forced_labels; x; x = XEXP (x, 1))
3357 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3360 /* Set all elimination offsets to the known values for the code label given
3364 set_offsets_for_label (insn)
3368 int label_nr = CODE_LABEL_NUMBER (insn);
3369 struct elim_table *ep;
3371 num_not_at_initial_offset = 0;
3372 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3374 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3375 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3376 num_not_at_initial_offset++;
3380 /* See if anything that happened changes which eliminations are valid.
3381 For example, on the Sparc, whether or not the frame pointer can
3382 be eliminated can depend on what registers have been used. We need
3383 not check some conditions again (such as flag_omit_frame_pointer)
3384 since they can't have changed. */
3387 update_eliminables (pset)
3390 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3391 int previous_frame_pointer_needed = frame_pointer_needed;
3393 struct elim_table *ep;
3395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3396 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3397 #ifdef ELIMINABLE_REGS
3398 || ! CAN_ELIMINATE (ep->from, ep->to)
3401 ep->can_eliminate = 0;
3403 /* Look for the case where we have discovered that we can't replace
3404 register A with register B and that means that we will now be
3405 trying to replace register A with register C. This means we can
3406 no longer replace register C with register B and we need to disable
3407 such an elimination, if it exists. This occurs often with A == ap,
3408 B == sp, and C == fp. */
3410 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3412 struct elim_table *op;
3413 register int new_to = -1;
3415 if (! ep->can_eliminate && ep->can_eliminate_previous)
3417 /* Find the current elimination for ep->from, if there is a
3419 for (op = reg_eliminate;
3420 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3421 if (op->from == ep->from && op->can_eliminate)
3427 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3429 for (op = reg_eliminate;
3430 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3431 if (op->from == new_to && op->to == ep->to)
3432 op->can_eliminate = 0;
3436 /* See if any registers that we thought we could eliminate the previous
3437 time are no longer eliminable. If so, something has changed and we
3438 must spill the register. Also, recompute the number of eliminable
3439 registers and see if the frame pointer is needed; it is if there is
3440 no elimination of the frame pointer that we can perform. */
3442 frame_pointer_needed = 1;
3443 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3445 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3446 && ep->to != HARD_FRAME_POINTER_REGNUM)
3447 frame_pointer_needed = 0;
3449 if (! ep->can_eliminate && ep->can_eliminate_previous)
3451 ep->can_eliminate_previous = 0;
3452 SET_HARD_REG_BIT (*pset, ep->from);
3457 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3458 /* If we didn't need a frame pointer last time, but we do now, spill
3459 the hard frame pointer. */
3460 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3461 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3465 /* Initialize the table of registers to eliminate. */
3470 struct elim_table *ep;
3471 #ifdef ELIMINABLE_REGS
3472 struct elim_table_1 *ep1;
3476 reg_eliminate = (struct elim_table *)
3477 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3479 /* Does this function require a frame pointer? */
3481 frame_pointer_needed = (! flag_omit_frame_pointer
3482 #ifdef EXIT_IGNORE_STACK
3483 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3484 and restore sp for alloca. So we can't eliminate
3485 the frame pointer in that case. At some point,
3486 we should improve this by emitting the
3487 sp-adjusting insns for this case. */
3488 || (current_function_calls_alloca
3489 && EXIT_IGNORE_STACK)
3491 || FRAME_POINTER_REQUIRED);
3495 #ifdef ELIMINABLE_REGS
3496 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3497 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3499 ep->from = ep1->from;
3501 ep->can_eliminate = ep->can_eliminate_previous
3502 = (CAN_ELIMINATE (ep->from, ep->to)
3503 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3506 reg_eliminate[0].from = reg_eliminate_1[0].from;
3507 reg_eliminate[0].to = reg_eliminate_1[0].to;
3508 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3509 = ! frame_pointer_needed;
3512 /* Count the number of eliminable registers and build the FROM and TO
3513 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3514 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3515 We depend on this. */
3516 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3518 num_eliminable += ep->can_eliminate;
3519 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3520 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3524 /* Kick all pseudos out of hard register REGNO.
3526 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3527 because we found we can't eliminate some register. In the case, no pseudos
3528 are allowed to be in the register, even if they are only in a block that
3529 doesn't require spill registers, unlike the case when we are spilling this
3530 hard reg to produce another spill register.
3532 Return nonzero if any pseudos needed to be kicked out. */
3535 spill_hard_reg (regno, cant_eliminate)
3543 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3544 regs_ever_live[regno] = 1;
3547 /* Spill every pseudo reg that was allocated to this reg
3548 or to something that overlaps this reg. */
3550 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3551 if (reg_renumber[i] >= 0
3552 && (unsigned int) reg_renumber[i] <= regno
3553 && ((unsigned int) reg_renumber[i]
3554 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3555 PSEUDO_REGNO_MODE (i))
3557 SET_REGNO_REG_SET (&spilled_pseudos, i);
3560 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3561 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3564 ior_hard_reg_set (set1, set2)
3565 HARD_REG_SET *set1, *set2;
3567 IOR_HARD_REG_SET (*set1, *set2);
3570 /* After find_reload_regs has been run for all insn that need reloads,
3571 and/or spill_hard_regs was called, this function is used to actually
3572 spill pseudo registers and try to reallocate them. It also sets up the
3573 spill_regs array for use by choose_reload_regs. */
3576 finish_spills (global)
3579 struct insn_chain *chain;
3580 int something_changed = 0;
3583 /* Build the spill_regs array for the function. */
3584 /* If there are some registers still to eliminate and one of the spill regs
3585 wasn't ever used before, additional stack space may have to be
3586 allocated to store this register. Thus, we may have changed the offset
3587 between the stack and frame pointers, so mark that something has changed.
3589 One might think that we need only set VAL to 1 if this is a call-used
3590 register. However, the set of registers that must be saved by the
3591 prologue is not identical to the call-used set. For example, the
3592 register used by the call insn for the return PC is a call-used register,
3593 but must be saved by the prologue. */
3596 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3597 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3599 spill_reg_order[i] = n_spills;
3600 spill_regs[n_spills++] = i;
3601 if (num_eliminable && ! regs_ever_live[i])
3602 something_changed = 1;
3603 regs_ever_live[i] = 1;
3606 spill_reg_order[i] = -1;
3608 EXECUTE_IF_SET_IN_REG_SET
3609 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3611 /* Record the current hard register the pseudo is allocated to in
3612 pseudo_previous_regs so we avoid reallocating it to the same
3613 hard reg in a later pass. */
3614 if (reg_renumber[i] < 0)
3617 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3618 /* Mark it as no longer having a hard register home. */
3619 reg_renumber[i] = -1;
3620 /* We will need to scan everything again. */
3621 something_changed = 1;
3624 /* Retry global register allocation if possible. */
3627 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3628 /* For every insn that needs reloads, set the registers used as spill
3629 regs in pseudo_forbidden_regs for every pseudo live across the
3631 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3633 EXECUTE_IF_SET_IN_REG_SET
3634 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3636 ior_hard_reg_set (pseudo_forbidden_regs + i,
3637 &chain->used_spill_regs);
3639 EXECUTE_IF_SET_IN_REG_SET
3640 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3642 ior_hard_reg_set (pseudo_forbidden_regs + i,
3643 &chain->used_spill_regs);
3647 /* Retry allocating the spilled pseudos. For each reg, merge the
3648 various reg sets that indicate which hard regs can't be used,
3649 and call retry_global_alloc.
3650 We change spill_pseudos here to only contain pseudos that did not
3651 get a new hard register. */
3652 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3653 if (reg_old_renumber[i] != reg_renumber[i])
3655 HARD_REG_SET forbidden;
3656 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3657 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3658 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3659 retry_global_alloc (i, forbidden);
3660 if (reg_renumber[i] >= 0)
3661 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3665 /* Fix up the register information in the insn chain.
3666 This involves deleting those of the spilled pseudos which did not get
3667 a new hard register home from the live_{before,after} sets. */
3668 for (chain = reload_insn_chain; chain; chain = chain->next)
3670 HARD_REG_SET used_by_pseudos;
3671 HARD_REG_SET used_by_pseudos2;
3673 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3674 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3676 /* Mark any unallocated hard regs as available for spills. That
3677 makes inheritance work somewhat better. */
3678 if (chain->need_reload)
3680 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3681 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3682 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3684 /* Save the old value for the sanity test below. */
3685 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3687 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3688 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3689 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3690 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3692 /* Make sure we only enlarge the set. */
3693 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3699 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3700 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3702 int regno = reg_renumber[i];
3703 if (reg_old_renumber[i] == regno)
3706 alter_reg (i, reg_old_renumber[i]);
3707 reg_old_renumber[i] = regno;
3711 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3713 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3714 i, reg_renumber[i]);
3718 return something_changed;
3721 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3722 Also mark any hard registers used to store user variables as
3723 forbidden from being used for spill registers. */
3726 scan_paradoxical_subregs (x)
3730 register const char *fmt;
3731 register enum rtx_code code = GET_CODE (x);
3737 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3738 && REG_USERVAR_P (x))
3739 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3755 if (GET_CODE (SUBREG_REG (x)) == REG
3756 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3757 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3758 = GET_MODE_SIZE (GET_MODE (x));
3765 fmt = GET_RTX_FORMAT (code);
3766 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3769 scan_paradoxical_subregs (XEXP (x, i));
3770 else if (fmt[i] == 'E')
3773 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3774 scan_paradoxical_subregs (XVECEXP (x, i, j));
3779 /* Reload pseudo-registers into hard regs around each insn as needed.
3780 Additional register load insns are output before the insn that needs it
3781 and perhaps store insns after insns that modify the reloaded pseudo reg.
3783 reg_last_reload_reg and reg_reloaded_contents keep track of
3784 which registers are already available in reload registers.
3785 We update these for the reloads that we perform,
3786 as the insns are scanned. */
3789 reload_as_needed (live_known)
3792 struct insn_chain *chain;
3793 #if defined (AUTO_INC_DEC)
3798 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3799 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3800 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3801 reg_has_output_reload = (char *) xmalloc (max_regno);
3802 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3804 set_initial_elim_offsets ();
3806 for (chain = reload_insn_chain; chain; chain = chain->next)
3809 rtx insn = chain->insn;
3810 rtx old_next = NEXT_INSN (insn);
3812 /* If we pass a label, copy the offsets from the label information
3813 into the current offsets of each elimination. */
3814 if (GET_CODE (insn) == CODE_LABEL)
3815 set_offsets_for_label (insn);
3817 else if (INSN_P (insn))
3819 rtx oldpat = PATTERN (insn);
3821 /* If this is a USE and CLOBBER of a MEM, ensure that any
3822 references to eliminable registers have been removed. */
3824 if ((GET_CODE (PATTERN (insn)) == USE
3825 || GET_CODE (PATTERN (insn)) == CLOBBER)
3826 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3827 XEXP (XEXP (PATTERN (insn), 0), 0)
3828 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3829 GET_MODE (XEXP (PATTERN (insn), 0)),
3832 /* If we need to do register elimination processing, do so.
3833 This might delete the insn, in which case we are done. */
3834 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3836 eliminate_regs_in_insn (insn, 1);
3837 if (GET_CODE (insn) == NOTE)
3839 update_eliminable_offsets ();
3844 /* If need_elim is nonzero but need_reload is zero, one might think
3845 that we could simply set n_reloads to 0. However, find_reloads
3846 could have done some manipulation of the insn (such as swapping
3847 commutative operands), and these manipulations are lost during
3848 the first pass for every insn that needs register elimination.
3849 So the actions of find_reloads must be redone here. */
3851 if (! chain->need_elim && ! chain->need_reload
3852 && ! chain->need_operand_change)
3854 /* First find the pseudo regs that must be reloaded for this insn.
3855 This info is returned in the tables reload_... (see reload.h).
3856 Also modify the body of INSN by substituting RELOAD
3857 rtx's for those pseudo regs. */
3860 memset (reg_has_output_reload, 0, max_regno);
3861 CLEAR_HARD_REG_SET (reg_is_output_reload);
3863 find_reloads (insn, 1, spill_indirect_levels, live_known,
3869 rtx next = NEXT_INSN (insn);
3872 prev = PREV_INSN (insn);
3874 /* Now compute which reload regs to reload them into. Perhaps
3875 reusing reload regs from previous insns, or else output
3876 load insns to reload them. Maybe output store insns too.
3877 Record the choices of reload reg in reload_reg_rtx. */
3878 choose_reload_regs (chain);
3880 /* Merge any reloads that we didn't combine for fear of
3881 increasing the number of spill registers needed but now
3882 discover can be safely merged. */
3883 if (SMALL_REGISTER_CLASSES)
3884 merge_assigned_reloads (insn);
3886 /* Generate the insns to reload operands into or out of
3887 their reload regs. */
3888 emit_reload_insns (chain);
3890 /* Substitute the chosen reload regs from reload_reg_rtx
3891 into the insn's body (or perhaps into the bodies of other
3892 load and store insn that we just made for reloading
3893 and that we moved the structure into). */
3894 subst_reloads (insn);
3896 /* If this was an ASM, make sure that all the reload insns
3897 we have generated are valid. If not, give an error
3900 if (asm_noperands (PATTERN (insn)) >= 0)
3901 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3902 if (p != insn && INSN_P (p)
3903 && (recog_memoized (p) < 0
3904 || (extract_insn (p), ! constrain_operands (1))))
3906 error_for_asm (insn,
3907 "`asm' operand requires impossible reload");
3909 NOTE_SOURCE_FILE (p) = 0;
3910 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3914 if (num_eliminable && chain->need_elim)
3915 update_eliminable_offsets ();
3917 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3918 is no longer validly lying around to save a future reload.
3919 Note that this does not detect pseudos that were reloaded
3920 for this insn in order to be stored in
3921 (obeying register constraints). That is correct; such reload
3922 registers ARE still valid. */
3923 note_stores (oldpat, forget_old_reloads_1, NULL);
3925 /* There may have been CLOBBER insns placed after INSN. So scan
3926 between INSN and NEXT and use them to forget old reloads. */
3927 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3928 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3929 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3932 /* Likewise for regs altered by auto-increment in this insn.
3933 REG_INC notes have been changed by reloading:
3934 find_reloads_address_1 records substitutions for them,
3935 which have been performed by subst_reloads above. */
3936 for (i = n_reloads - 1; i >= 0; i--)
3938 rtx in_reg = rld[i].in_reg;
3941 enum rtx_code code = GET_CODE (in_reg);
3942 /* PRE_INC / PRE_DEC will have the reload register ending up
3943 with the same value as the stack slot, but that doesn't
3944 hold true for POST_INC / POST_DEC. Either we have to
3945 convert the memory access to a true POST_INC / POST_DEC,
3946 or we can't use the reload register for inheritance. */
3947 if ((code == POST_INC || code == POST_DEC)
3948 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3949 REGNO (rld[i].reg_rtx))
3950 /* Make sure it is the inc/dec pseudo, and not
3951 some other (e.g. output operand) pseudo. */
3952 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3953 == REGNO (XEXP (in_reg, 0))))
3956 rtx reload_reg = rld[i].reg_rtx;
3957 enum machine_mode mode = GET_MODE (reload_reg);
3961 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3963 /* We really want to ignore REG_INC notes here, so
3964 use PATTERN (p) as argument to reg_set_p . */
3965 if (reg_set_p (reload_reg, PATTERN (p)))
3967 n = count_occurrences (PATTERN (p), reload_reg, 0);
3972 n = validate_replace_rtx (reload_reg,
3973 gen_rtx (code, mode,
3977 /* We must also verify that the constraints
3978 are met after the replacement. */
3981 n = constrain_operands (1);
3985 /* If the constraints were not met, then
3986 undo the replacement. */
3989 validate_replace_rtx (gen_rtx (code, mode,
4001 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4003 /* Mark this as having an output reload so that the
4004 REG_INC processing code below won't invalidate
4005 the reload for inheritance. */
4006 SET_HARD_REG_BIT (reg_is_output_reload,
4007 REGNO (reload_reg));
4008 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4011 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4014 else if ((code == PRE_INC || code == PRE_DEC)
4015 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4016 REGNO (rld[i].reg_rtx))
4017 /* Make sure it is the inc/dec pseudo, and not
4018 some other (e.g. output operand) pseudo. */
4019 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4020 == REGNO (XEXP (in_reg, 0))))
4022 SET_HARD_REG_BIT (reg_is_output_reload,
4023 REGNO (rld[i].reg_rtx));
4024 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4028 /* If a pseudo that got a hard register is auto-incremented,
4029 we must purge records of copying it into pseudos without
4031 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4032 if (REG_NOTE_KIND (x) == REG_INC)
4034 /* See if this pseudo reg was reloaded in this insn.
4035 If so, its last-reload info is still valid
4036 because it is based on this insn's reload. */
4037 for (i = 0; i < n_reloads; i++)
4038 if (rld[i].out == XEXP (x, 0))
4042 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4046 /* A reload reg's contents are unknown after a label. */
4047 if (GET_CODE (insn) == CODE_LABEL)
4048 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4050 /* Don't assume a reload reg is still good after a call insn
4051 if it is a call-used reg. */
4052 else if (GET_CODE (insn) == CALL_INSN)
4053 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4057 free (reg_last_reload_reg);
4058 free (reg_has_output_reload);
4061 /* Discard all record of any value reloaded from X,
4062 or reloaded in X from someplace else;
4063 unless X is an output reload reg of the current insn.
4065 X may be a hard reg (the reload reg)
4066 or it may be a pseudo reg that was reloaded from. */
4069 forget_old_reloads_1 (x, ignored, data)
4071 rtx ignored ATTRIBUTE_UNUSED;
4072 void *data ATTRIBUTE_UNUSED;
4078 /* note_stores does give us subregs of hard regs,
4079 subreg_regno_offset will abort if it is not a hard reg. */
4080 while (GET_CODE (x) == SUBREG)
4082 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4083 GET_MODE (SUBREG_REG (x)),
4089 if (GET_CODE (x) != REG)
4092 regno = REGNO (x) + offset;
4094 if (regno >= FIRST_PSEUDO_REGISTER)
4100 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4101 /* Storing into a spilled-reg invalidates its contents.
4102 This can happen if a block-local pseudo is allocated to that reg
4103 and it wasn't spilled because this block's total need is 0.
4104 Then some insn might have an optional reload and use this reg. */
4105 for (i = 0; i < nr; i++)
4106 /* But don't do this if the reg actually serves as an output
4107 reload reg in the current instruction. */
4109 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4111 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4112 spill_reg_store[regno + i] = 0;
4116 /* Since value of X has changed,
4117 forget any value previously copied from it. */
4120 /* But don't forget a copy if this is the output reload
4121 that establishes the copy's validity. */
4122 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4123 reg_last_reload_reg[regno + nr] = 0;
4126 /* The following HARD_REG_SETs indicate when each hard register is
4127 used for a reload of various parts of the current insn. */
4129 /* If reg is unavailable for all reloads. */
4130 static HARD_REG_SET reload_reg_unavailable;
4131 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4132 static HARD_REG_SET reload_reg_used;
4133 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4134 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4135 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4136 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4137 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4138 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4139 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4140 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4141 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4142 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4143 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4144 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4145 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4146 static HARD_REG_SET reload_reg_used_in_op_addr;
4147 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4148 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4149 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4150 static HARD_REG_SET reload_reg_used_in_insn;
4151 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4152 static HARD_REG_SET reload_reg_used_in_other_addr;
4154 /* If reg is in use as a reload reg for any sort of reload. */
4155 static HARD_REG_SET reload_reg_used_at_all;
4157 /* If reg is use as an inherited reload. We just mark the first register
4159 static HARD_REG_SET reload_reg_used_for_inherit;
4161 /* Records which hard regs are used in any way, either as explicit use or
4162 by being allocated to a pseudo during any point of the current insn. */
4163 static HARD_REG_SET reg_used_in_insn;
4165 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4166 TYPE. MODE is used to indicate how many consecutive regs are
4170 mark_reload_reg_in_use (regno, opnum, type, mode)
4173 enum reload_type type;
4174 enum machine_mode mode;
4176 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4179 for (i = regno; i < nregs + regno; i++)
4184 SET_HARD_REG_BIT (reload_reg_used, i);
4187 case RELOAD_FOR_INPUT_ADDRESS:
4188 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4191 case RELOAD_FOR_INPADDR_ADDRESS:
4192 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4195 case RELOAD_FOR_OUTPUT_ADDRESS:
4196 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4199 case RELOAD_FOR_OUTADDR_ADDRESS:
4200 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4203 case RELOAD_FOR_OPERAND_ADDRESS:
4204 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4207 case RELOAD_FOR_OPADDR_ADDR:
4208 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4211 case RELOAD_FOR_OTHER_ADDRESS:
4212 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4215 case RELOAD_FOR_INPUT:
4216 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4219 case RELOAD_FOR_OUTPUT:
4220 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4223 case RELOAD_FOR_INSN:
4224 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4228 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4232 /* Similarly, but show REGNO is no longer in use for a reload. */
4235 clear_reload_reg_in_use (regno, opnum, type, mode)
4238 enum reload_type type;
4239 enum machine_mode mode;
4241 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4242 unsigned int start_regno, end_regno, r;
4244 /* A complication is that for some reload types, inheritance might
4245 allow multiple reloads of the same types to share a reload register.
4246 We set check_opnum if we have to check only reloads with the same
4247 operand number, and check_any if we have to check all reloads. */
4248 int check_opnum = 0;
4250 HARD_REG_SET *used_in_set;
4255 used_in_set = &reload_reg_used;
4258 case RELOAD_FOR_INPUT_ADDRESS:
4259 used_in_set = &reload_reg_used_in_input_addr[opnum];
4262 case RELOAD_FOR_INPADDR_ADDRESS:
4264 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4267 case RELOAD_FOR_OUTPUT_ADDRESS:
4268 used_in_set = &reload_reg_used_in_output_addr[opnum];
4271 case RELOAD_FOR_OUTADDR_ADDRESS:
4273 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4276 case RELOAD_FOR_OPERAND_ADDRESS:
4277 used_in_set = &reload_reg_used_in_op_addr;
4280 case RELOAD_FOR_OPADDR_ADDR:
4282 used_in_set = &reload_reg_used_in_op_addr_reload;
4285 case RELOAD_FOR_OTHER_ADDRESS:
4286 used_in_set = &reload_reg_used_in_other_addr;
4290 case RELOAD_FOR_INPUT:
4291 used_in_set = &reload_reg_used_in_input[opnum];
4294 case RELOAD_FOR_OUTPUT:
4295 used_in_set = &reload_reg_used_in_output[opnum];
4298 case RELOAD_FOR_INSN:
4299 used_in_set = &reload_reg_used_in_insn;
4304 /* We resolve conflicts with remaining reloads of the same type by
4305 excluding the intervals of of reload registers by them from the
4306 interval of freed reload registers. Since we only keep track of
4307 one set of interval bounds, we might have to exclude somewhat
4308 more then what would be necessary if we used a HARD_REG_SET here.
4309 But this should only happen very infrequently, so there should
4310 be no reason to worry about it. */
4312 start_regno = regno;
4313 end_regno = regno + nregs;
4314 if (check_opnum || check_any)
4316 for (i = n_reloads - 1; i >= 0; i--)
4318 if (rld[i].when_needed == type
4319 && (check_any || rld[i].opnum == opnum)
4322 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4323 unsigned int conflict_end
4325 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4327 /* If there is an overlap with the first to-be-freed register,
4328 adjust the interval start. */
4329 if (conflict_start <= start_regno && conflict_end > start_regno)
4330 start_regno = conflict_end;
4331 /* Otherwise, if there is a conflict with one of the other
4332 to-be-freed registers, adjust the interval end. */
4333 if (conflict_start > start_regno && conflict_start < end_regno)
4334 end_regno = conflict_start;
4339 for (r = start_regno; r < end_regno; r++)
4340 CLEAR_HARD_REG_BIT (*used_in_set, r);
4343 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4344 specified by OPNUM and TYPE. */
4347 reload_reg_free_p (regno, opnum, type)
4350 enum reload_type type;
4354 /* In use for a RELOAD_OTHER means it's not available for anything. */
4355 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4356 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4362 /* In use for anything means we can't use it for RELOAD_OTHER. */
4363 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4364 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4365 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4368 for (i = 0; i < reload_n_operands; i++)
4369 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4370 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4371 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4372 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4373 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4374 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4379 case RELOAD_FOR_INPUT:
4380 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4384 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4387 /* If it is used for some other input, can't use it. */
4388 for (i = 0; i < reload_n_operands; i++)
4389 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4392 /* If it is used in a later operand's address, can't use it. */
4393 for (i = opnum + 1; i < reload_n_operands; i++)
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4395 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4400 case RELOAD_FOR_INPUT_ADDRESS:
4401 /* Can't use a register if it is used for an input address for this
4402 operand or used as an input in an earlier one. */
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4407 for (i = 0; i < opnum; i++)
4408 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4413 case RELOAD_FOR_INPADDR_ADDRESS:
4414 /* Can't use a register if it is used for an input address
4415 for this operand or used as an input in an earlier
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4420 for (i = 0; i < opnum; i++)
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4426 case RELOAD_FOR_OUTPUT_ADDRESS:
4427 /* Can't use a register if it is used for an output address for this
4428 operand or used as an output in this or a later operand. */
4429 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4432 for (i = opnum; i < reload_n_operands; i++)
4433 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4438 case RELOAD_FOR_OUTADDR_ADDRESS:
4439 /* Can't use a register if it is used for an output address
4440 for this operand or used as an output in this or a
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4445 for (i = opnum; i < reload_n_operands; i++)
4446 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4451 case RELOAD_FOR_OPERAND_ADDRESS:
4452 for (i = 0; i < reload_n_operands; i++)
4453 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4456 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4457 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4459 case RELOAD_FOR_OPADDR_ADDR:
4460 for (i = 0; i < reload_n_operands; i++)
4461 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4464 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4466 case RELOAD_FOR_OUTPUT:
4467 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4468 outputs, or an operand address for this or an earlier output. */
4469 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4472 for (i = 0; i < reload_n_operands; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4476 for (i = 0; i <= opnum; i++)
4477 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4478 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4483 case RELOAD_FOR_INSN:
4484 for (i = 0; i < reload_n_operands; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4489 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4490 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4492 case RELOAD_FOR_OTHER_ADDRESS:
4493 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4498 /* Return 1 if the value in reload reg REGNO, as used by a reload
4499 needed for the part of the insn specified by OPNUM and TYPE,
4500 is still available in REGNO at the end of the insn.
4502 We can assume that the reload reg was already tested for availability
4503 at the time it is needed, and we should not check this again,
4504 in case the reg has already been marked in use. */
4507 reload_reg_reaches_end_p (regno, opnum, type)
4510 enum reload_type type;
4517 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4518 its value must reach the end. */
4521 /* If this use is for part of the insn,
4522 its value reaches if no subsequent part uses the same register.
4523 Just like the above function, don't try to do this with lots
4526 case RELOAD_FOR_OTHER_ADDRESS:
4527 /* Here we check for everything else, since these don't conflict
4528 with anything else and everything comes later. */
4530 for (i = 0; i < reload_n_operands; i++)
4531 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4532 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4533 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4534 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4535 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4536 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4539 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4540 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4541 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4543 case RELOAD_FOR_INPUT_ADDRESS:
4544 case RELOAD_FOR_INPADDR_ADDRESS:
4545 /* Similar, except that we check only for this and subsequent inputs
4546 and the address of only subsequent inputs and we do not need
4547 to check for RELOAD_OTHER objects since they are known not to
4550 for (i = opnum; i < reload_n_operands; i++)
4551 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4554 for (i = opnum + 1; i < reload_n_operands; i++)
4555 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4556 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4559 for (i = 0; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4561 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4562 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4568 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4569 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4570 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4572 case RELOAD_FOR_INPUT:
4573 /* Similar to input address, except we start at the next operand for
4574 both input and input address and we do not check for
4575 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4578 for (i = opnum + 1; i < reload_n_operands; i++)
4579 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4580 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4581 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4584 /* ... fall through ... */
4586 case RELOAD_FOR_OPERAND_ADDRESS:
4587 /* Check outputs and their addresses. */
4589 for (i = 0; i < reload_n_operands; i++)
4590 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4591 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4592 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4595 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4597 case RELOAD_FOR_OPADDR_ADDR:
4598 for (i = 0; i < reload_n_operands; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4604 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4605 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4606 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4608 case RELOAD_FOR_INSN:
4609 /* These conflict with other outputs with RELOAD_OTHER. So
4610 we need only check for output addresses. */
4614 /* ... fall through ... */
4616 case RELOAD_FOR_OUTPUT:
4617 case RELOAD_FOR_OUTPUT_ADDRESS:
4618 case RELOAD_FOR_OUTADDR_ADDRESS:
4619 /* We already know these can't conflict with a later output. So the
4620 only thing to check are later output addresses. */
4621 for (i = opnum + 1; i < reload_n_operands; i++)
4622 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4623 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4632 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4635 This function uses the same algorithm as reload_reg_free_p above. */
4638 reloads_conflict (r1, r2)
4641 enum reload_type r1_type = rld[r1].when_needed;
4642 enum reload_type r2_type = rld[r2].when_needed;
4643 int r1_opnum = rld[r1].opnum;
4644 int r2_opnum = rld[r2].opnum;
4646 /* RELOAD_OTHER conflicts with everything. */
4647 if (r2_type == RELOAD_OTHER)
4650 /* Otherwise, check conflicts differently for each type. */
4654 case RELOAD_FOR_INPUT:
4655 return (r2_type == RELOAD_FOR_INSN
4656 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4657 || r2_type == RELOAD_FOR_OPADDR_ADDR
4658 || r2_type == RELOAD_FOR_INPUT
4659 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4660 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4661 && r2_opnum > r1_opnum));
4663 case RELOAD_FOR_INPUT_ADDRESS:
4664 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4665 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4667 case RELOAD_FOR_INPADDR_ADDRESS:
4668 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4669 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4671 case RELOAD_FOR_OUTPUT_ADDRESS:
4672 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4673 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4675 case RELOAD_FOR_OUTADDR_ADDRESS:
4676 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4677 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4679 case RELOAD_FOR_OPERAND_ADDRESS:
4680 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4681 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4683 case RELOAD_FOR_OPADDR_ADDR:
4684 return (r2_type == RELOAD_FOR_INPUT
4685 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4687 case RELOAD_FOR_OUTPUT:
4688 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4689 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4690 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4691 && r2_opnum <= r1_opnum));
4693 case RELOAD_FOR_INSN:
4694 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4695 || r2_type == RELOAD_FOR_INSN
4696 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4698 case RELOAD_FOR_OTHER_ADDRESS:
4699 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4709 /* Indexed by reload number, 1 if incoming value
4710 inherited from previous insns. */
4711 char reload_inherited[MAX_RELOADS];
4713 /* For an inherited reload, this is the insn the reload was inherited from,
4714 if we know it. Otherwise, this is 0. */
4715 rtx reload_inheritance_insn[MAX_RELOADS];
4717 /* If non-zero, this is a place to get the value of the reload,
4718 rather than using reload_in. */
4719 rtx reload_override_in[MAX_RELOADS];
4721 /* For each reload, the hard register number of the register used,
4722 or -1 if we did not need a register for this reload. */
4723 int reload_spill_index[MAX_RELOADS];
4725 /* Subroutine of free_for_value_p, used to check a single register.
4726 START_REGNO is the starting regno of the full reload register
4727 (possibly comprising multiple hard registers) that we are considering. */
4730 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4731 reloadnum, ignore_address_reloads)
4732 int start_regno, regno;
4734 enum reload_type type;
4737 int ignore_address_reloads;
4740 /* Set if we see an input reload that must not share its reload register
4741 with any new earlyclobber, but might otherwise share the reload
4742 register with an output or input-output reload. */
4743 int check_earlyclobber = 0;
4747 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4750 if (out == const0_rtx)
4756 /* We use some pseudo 'time' value to check if the lifetimes of the
4757 new register use would overlap with the one of a previous reload
4758 that is not read-only or uses a different value.
4759 The 'time' used doesn't have to be linear in any shape or form, just
4761 Some reload types use different 'buckets' for each operand.
4762 So there are MAX_RECOG_OPERANDS different time values for each
4764 We compute TIME1 as the time when the register for the prospective
4765 new reload ceases to be live, and TIME2 for each existing
4766 reload as the time when that the reload register of that reload
4768 Where there is little to be gained by exact lifetime calculations,
4769 we just make conservative assumptions, i.e. a longer lifetime;
4770 this is done in the 'default:' cases. */
4773 case RELOAD_FOR_OTHER_ADDRESS:
4774 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4775 time1 = copy ? 0 : 1;
4778 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4780 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4781 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4782 respectively, to the time values for these, we get distinct time
4783 values. To get distinct time values for each operand, we have to
4784 multiply opnum by at least three. We round that up to four because
4785 multiply by four is often cheaper. */
4786 case RELOAD_FOR_INPADDR_ADDRESS:
4787 time1 = opnum * 4 + 2;
4789 case RELOAD_FOR_INPUT_ADDRESS:
4790 time1 = opnum * 4 + 3;
4792 case RELOAD_FOR_INPUT:
4793 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4794 executes (inclusive). */
4795 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4797 case RELOAD_FOR_OPADDR_ADDR:
4799 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4800 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4802 case RELOAD_FOR_OPERAND_ADDRESS:
4803 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4805 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4807 case RELOAD_FOR_OUTADDR_ADDRESS:
4808 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4810 case RELOAD_FOR_OUTPUT_ADDRESS:
4811 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4814 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4817 for (i = 0; i < n_reloads; i++)
4819 rtx reg = rld[i].reg_rtx;
4820 if (reg && GET_CODE (reg) == REG
4821 && ((unsigned) regno - true_regnum (reg)
4822 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4825 rtx other_input = rld[i].in;
4827 /* If the other reload loads the same input value, that
4828 will not cause a conflict only if it's loading it into
4829 the same register. */
4830 if (true_regnum (reg) != start_regno)
4831 other_input = NULL_RTX;
4832 if (! other_input || ! rtx_equal_p (other_input, value)
4833 || rld[i].out || out)
4836 switch (rld[i].when_needed)
4838 case RELOAD_FOR_OTHER_ADDRESS:
4841 case RELOAD_FOR_INPADDR_ADDRESS:
4842 /* find_reloads makes sure that a
4843 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4844 by at most one - the first -
4845 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4846 address reload is inherited, the address address reload
4847 goes away, so we can ignore this conflict. */
4848 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4849 && ignore_address_reloads
4850 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4851 Then the address address is still needed to store
4852 back the new address. */
4853 && ! rld[reloadnum].out)
4855 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4856 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4858 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4859 && ignore_address_reloads
4860 /* Unless we are reloading an auto_inc expression. */
4861 && ! rld[reloadnum].out)
4863 time2 = rld[i].opnum * 4 + 2;
4865 case RELOAD_FOR_INPUT_ADDRESS:
4866 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4867 && ignore_address_reloads
4868 && ! rld[reloadnum].out)
4870 time2 = rld[i].opnum * 4 + 3;
4872 case RELOAD_FOR_INPUT:
4873 time2 = rld[i].opnum * 4 + 4;
4874 check_earlyclobber = 1;
4876 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4877 == MAX_RECOG_OPERAND * 4 */
4878 case RELOAD_FOR_OPADDR_ADDR:
4879 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4880 && ignore_address_reloads
4881 && ! rld[reloadnum].out)
4883 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4885 case RELOAD_FOR_OPERAND_ADDRESS:
4886 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4887 check_earlyclobber = 1;
4889 case RELOAD_FOR_INSN:
4890 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4892 case RELOAD_FOR_OUTPUT:
4893 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4894 instruction is executed. */
4895 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4897 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4898 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4900 case RELOAD_FOR_OUTADDR_ADDRESS:
4901 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4902 && ignore_address_reloads
4903 && ! rld[reloadnum].out)
4905 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4907 case RELOAD_FOR_OUTPUT_ADDRESS:
4908 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4911 /* If there is no conflict in the input part, handle this
4912 like an output reload. */
4913 if (! rld[i].in || rtx_equal_p (other_input, value))
4915 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4916 /* Earlyclobbered outputs must conflict with inputs. */
4917 if (earlyclobber_operand_p (rld[i].out))
4918 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4923 /* RELOAD_OTHER might be live beyond instruction execution,
4924 but this is not obvious when we set time2 = 1. So check
4925 here if there might be a problem with the new reload
4926 clobbering the register used by the RELOAD_OTHER. */
4934 && (! rld[i].in || rld[i].out
4935 || ! rtx_equal_p (other_input, value)))
4936 || (out && rld[reloadnum].out_reg
4937 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4943 /* Earlyclobbered outputs must conflict with inputs. */
4944 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4950 /* Return 1 if the value in reload reg REGNO, as used by a reload
4951 needed for the part of the insn specified by OPNUM and TYPE,
4952 may be used to load VALUE into it.
4954 MODE is the mode in which the register is used, this is needed to
4955 determine how many hard regs to test.
4957 Other read-only reloads with the same value do not conflict
4958 unless OUT is non-zero and these other reloads have to live while
4959 output reloads live.
4960 If OUT is CONST0_RTX, this is a special case: it means that the
4961 test should not be for using register REGNO as reload register, but
4962 for copying from register REGNO into the reload register.
4964 RELOADNUM is the number of the reload we want to load this value for;
4965 a reload does not conflict with itself.
4967 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4968 reloads that load an address for the very reload we are considering.
4970 The caller has to make sure that there is no conflict with the return
4974 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4975 ignore_address_reloads)
4977 enum machine_mode mode;
4979 enum reload_type type;
4982 int ignore_address_reloads;
4984 int nregs = HARD_REGNO_NREGS (regno, mode);
4986 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4987 value, out, reloadnum,
4988 ignore_address_reloads))
4993 /* Determine whether the reload reg X overlaps any rtx'es used for
4994 overriding inheritance. Return nonzero if so. */
4997 conflicts_with_override (x)
5001 for (i = 0; i < n_reloads; i++)
5002 if (reload_override_in[i]
5003 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5008 /* Give an error message saying we failed to find a reload for INSN,
5009 and clear out reload R. */
5011 failed_reload (insn, r)
5015 if (asm_noperands (PATTERN (insn)) < 0)
5016 /* It's the compiler's fault. */
5017 fatal_insn ("Could not find a spill register", insn);
5019 /* It's the user's fault; the operand's mode and constraint
5020 don't match. Disable this reload so we don't crash in final. */
5021 error_for_asm (insn,
5022 "`asm' operand constraint incompatible with operand size");
5026 rld[r].optional = 1;
5027 rld[r].secondary_p = 1;
5030 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5031 for reload R. If it's valid, get an rtx for it. Return nonzero if
5034 set_reload_reg (i, r)
5038 rtx reg = spill_reg_rtx[i];
5040 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5041 spill_reg_rtx[i] = reg
5042 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5044 regno = true_regnum (reg);
5046 /* Detect when the reload reg can't hold the reload mode.
5047 This used to be one `if', but Sequent compiler can't handle that. */
5048 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5050 enum machine_mode test_mode = VOIDmode;
5052 test_mode = GET_MODE (rld[r].in);
5053 /* If rld[r].in has VOIDmode, it means we will load it
5054 in whatever mode the reload reg has: to wit, rld[r].mode.
5055 We have already tested that for validity. */
5056 /* Aside from that, we need to test that the expressions
5057 to reload from or into have modes which are valid for this
5058 reload register. Otherwise the reload insns would be invalid. */
5059 if (! (rld[r].in != 0 && test_mode != VOIDmode
5060 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5061 if (! (rld[r].out != 0
5062 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5064 /* The reg is OK. */
5067 /* Mark as in use for this insn the reload regs we use
5069 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5070 rld[r].when_needed, rld[r].mode);
5072 rld[r].reg_rtx = reg;
5073 reload_spill_index[r] = spill_regs[i];
5080 /* Find a spill register to use as a reload register for reload R.
5081 LAST_RELOAD is non-zero if this is the last reload for the insn being
5084 Set rld[R].reg_rtx to the register allocated.
5086 We return 1 if successful, or 0 if we couldn't find a spill reg and
5087 we didn't change anything. */
5090 allocate_reload_reg (chain, r, last_reload)
5091 struct insn_chain *chain ATTRIBUTE_UNUSED;
5097 /* If we put this reload ahead, thinking it is a group,
5098 then insist on finding a group. Otherwise we can grab a
5099 reg that some other reload needs.
5100 (That can happen when we have a 68000 DATA_OR_FP_REG
5101 which is a group of data regs or one fp reg.)
5102 We need not be so restrictive if there are no more reloads
5105 ??? Really it would be nicer to have smarter handling
5106 for that kind of reg class, where a problem like this is normal.
5107 Perhaps those classes should be avoided for reloading
5108 by use of more alternatives. */
5110 int force_group = rld[r].nregs > 1 && ! last_reload;
5112 /* If we want a single register and haven't yet found one,
5113 take any reg in the right class and not in use.
5114 If we want a consecutive group, here is where we look for it.
5116 We use two passes so we can first look for reload regs to
5117 reuse, which are already in use for other reloads in this insn,
5118 and only then use additional registers.
5119 I think that maximizing reuse is needed to make sure we don't
5120 run out of reload regs. Suppose we have three reloads, and
5121 reloads A and B can share regs. These need two regs.
5122 Suppose A and B are given different regs.
5123 That leaves none for C. */
5124 for (pass = 0; pass < 2; pass++)
5126 /* I is the index in spill_regs.
5127 We advance it round-robin between insns to use all spill regs
5128 equally, so that inherited reloads have a chance
5129 of leapfrogging each other. */
5133 for (count = 0; count < n_spills; count++)
5135 int class = (int) rld[r].class;
5141 regnum = spill_regs[i];
5143 if ((reload_reg_free_p (regnum, rld[r].opnum,
5146 /* We check reload_reg_used to make sure we
5147 don't clobber the return register. */
5148 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5149 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5150 rld[r].when_needed, rld[r].in,
5152 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5153 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5154 /* Look first for regs to share, then for unshared. But
5155 don't share regs used for inherited reloads; they are
5156 the ones we want to preserve. */
5158 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5160 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5163 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5164 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5165 (on 68000) got us two FP regs. If NR is 1,
5166 we would reject both of them. */
5169 /* If we need only one reg, we have already won. */
5172 /* But reject a single reg if we demand a group. */
5177 /* Otherwise check that as many consecutive regs as we need
5178 are available here. */
5181 int regno = regnum + nr - 1;
5182 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5183 && spill_reg_order[regno] >= 0
5184 && reload_reg_free_p (regno, rld[r].opnum,
5185 rld[r].when_needed)))
5194 /* If we found something on pass 1, omit pass 2. */
5195 if (count < n_spills)
5199 /* We should have found a spill register by now. */
5200 if (count >= n_spills)
5203 /* I is the index in SPILL_REG_RTX of the reload register we are to
5204 allocate. Get an rtx for it and find its register number. */
5206 return set_reload_reg (i, r);
5209 /* Initialize all the tables needed to allocate reload registers.
5210 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5211 is the array we use to restore the reg_rtx field for every reload. */
5214 choose_reload_regs_init (chain, save_reload_reg_rtx)
5215 struct insn_chain *chain;
5216 rtx *save_reload_reg_rtx;
5220 for (i = 0; i < n_reloads; i++)
5221 rld[i].reg_rtx = save_reload_reg_rtx[i];
5223 memset (reload_inherited, 0, MAX_RELOADS);
5224 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5225 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5227 CLEAR_HARD_REG_SET (reload_reg_used);
5228 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5229 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5230 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5231 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5232 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5234 CLEAR_HARD_REG_SET (reg_used_in_insn);
5237 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5238 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5239 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5240 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5241 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5242 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5245 for (i = 0; i < reload_n_operands; i++)
5247 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5248 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5249 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5250 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5251 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5252 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5255 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5257 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5259 for (i = 0; i < n_reloads; i++)
5260 /* If we have already decided to use a certain register,
5261 don't use it in another way. */
5263 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5264 rld[i].when_needed, rld[i].mode);
5267 /* Assign hard reg targets for the pseudo-registers we must reload
5268 into hard regs for this insn.
5269 Also output the instructions to copy them in and out of the hard regs.
5271 For machines with register classes, we are responsible for
5272 finding a reload reg in the proper class. */
5275 choose_reload_regs (chain)
5276 struct insn_chain *chain;
5278 rtx insn = chain->insn;
5280 unsigned int max_group_size = 1;
5281 enum reg_class group_class = NO_REGS;
5282 int pass, win, inheritance;
5284 rtx save_reload_reg_rtx[MAX_RELOADS];
5286 /* In order to be certain of getting the registers we need,
5287 we must sort the reloads into order of increasing register class.
5288 Then our grabbing of reload registers will parallel the process
5289 that provided the reload registers.
5291 Also note whether any of the reloads wants a consecutive group of regs.
5292 If so, record the maximum size of the group desired and what
5293 register class contains all the groups needed by this insn. */
5295 for (j = 0; j < n_reloads; j++)
5297 reload_order[j] = j;
5298 reload_spill_index[j] = -1;
5300 if (rld[j].nregs > 1)
5302 max_group_size = MAX (rld[j].nregs, max_group_size);
5304 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5307 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5311 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5313 /* If -O, try first with inheritance, then turning it off.
5314 If not -O, don't do inheritance.
5315 Using inheritance when not optimizing leads to paradoxes
5316 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5317 because one side of the comparison might be inherited. */
5319 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5321 choose_reload_regs_init (chain, save_reload_reg_rtx);
5323 /* Process the reloads in order of preference just found.
5324 Beyond this point, subregs can be found in reload_reg_rtx.
5326 This used to look for an existing reloaded home for all of the
5327 reloads, and only then perform any new reloads. But that could lose
5328 if the reloads were done out of reg-class order because a later
5329 reload with a looser constraint might have an old home in a register
5330 needed by an earlier reload with a tighter constraint.
5332 To solve this, we make two passes over the reloads, in the order
5333 described above. In the first pass we try to inherit a reload
5334 from a previous insn. If there is a later reload that needs a
5335 class that is a proper subset of the class being processed, we must
5336 also allocate a spill register during the first pass.
5338 Then make a second pass over the reloads to allocate any reloads
5339 that haven't been given registers yet. */
5341 for (j = 0; j < n_reloads; j++)
5343 register int r = reload_order[j];
5344 rtx search_equiv = NULL_RTX;
5346 /* Ignore reloads that got marked inoperative. */
5347 if (rld[r].out == 0 && rld[r].in == 0
5348 && ! rld[r].secondary_p)
5351 /* If find_reloads chose to use reload_in or reload_out as a reload
5352 register, we don't need to chose one. Otherwise, try even if it
5353 found one since we might save an insn if we find the value lying
5355 Try also when reload_in is a pseudo without a hard reg. */
5356 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5357 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5358 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5359 && GET_CODE (rld[r].in) != MEM
5360 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5363 #if 0 /* No longer needed for correct operation.
5364 It might give better code, or might not; worth an experiment? */
5365 /* If this is an optional reload, we can't inherit from earlier insns
5366 until we are sure that any non-optional reloads have been allocated.
5367 The following code takes advantage of the fact that optional reloads
5368 are at the end of reload_order. */
5369 if (rld[r].optional != 0)
5370 for (i = 0; i < j; i++)
5371 if ((rld[reload_order[i]].out != 0
5372 || rld[reload_order[i]].in != 0
5373 || rld[reload_order[i]].secondary_p)
5374 && ! rld[reload_order[i]].optional
5375 && rld[reload_order[i]].reg_rtx == 0)
5376 allocate_reload_reg (chain, reload_order[i], 0);
5379 /* First see if this pseudo is already available as reloaded
5380 for a previous insn. We cannot try to inherit for reloads
5381 that are smaller than the maximum number of registers needed
5382 for groups unless the register we would allocate cannot be used
5385 We could check here to see if this is a secondary reload for
5386 an object that is already in a register of the desired class.
5387 This would avoid the need for the secondary reload register.
5388 But this is complex because we can't easily determine what
5389 objects might want to be loaded via this reload. So let a
5390 register be allocated here. In `emit_reload_insns' we suppress
5391 one of the loads in the case described above. */
5396 register int regno = -1;
5397 enum machine_mode mode = VOIDmode;
5401 else if (GET_CODE (rld[r].in) == REG)
5403 regno = REGNO (rld[r].in);
5404 mode = GET_MODE (rld[r].in);
5406 else if (GET_CODE (rld[r].in_reg) == REG)
5408 regno = REGNO (rld[r].in_reg);
5409 mode = GET_MODE (rld[r].in_reg);
5411 else if (GET_CODE (rld[r].in_reg) == SUBREG
5412 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5414 byte = SUBREG_BYTE (rld[r].in_reg);
5415 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5416 if (regno < FIRST_PSEUDO_REGISTER)
5417 regno = subreg_regno (rld[r].in_reg);
5418 mode = GET_MODE (rld[r].in_reg);
5421 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5422 || GET_CODE (rld[r].in_reg) == PRE_DEC
5423 || GET_CODE (rld[r].in_reg) == POST_INC
5424 || GET_CODE (rld[r].in_reg) == POST_DEC)
5425 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5427 regno = REGNO (XEXP (rld[r].in_reg, 0));
5428 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5429 rld[r].out = rld[r].in;
5433 /* This won't work, since REGNO can be a pseudo reg number.
5434 Also, it takes much more hair to keep track of all the things
5435 that can invalidate an inherited reload of part of a pseudoreg. */
5436 else if (GET_CODE (rld[r].in) == SUBREG
5437 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5438 regno = subreg_regno (rld[r].in);
5441 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5443 enum reg_class class = rld[r].class, last_class;
5444 rtx last_reg = reg_last_reload_reg[regno];
5445 enum machine_mode need_mode;
5447 i = REGNO (last_reg);
5448 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5449 last_class = REGNO_REG_CLASS (i);
5455 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5456 GET_MODE_CLASS (mode));
5459 #ifdef CLASS_CANNOT_CHANGE_MODE
5461 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5462 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5464 : (GET_MODE_SIZE (GET_MODE (last_reg))
5465 >= GET_MODE_SIZE (need_mode)))
5467 (GET_MODE_SIZE (GET_MODE (last_reg))
5468 >= GET_MODE_SIZE (need_mode))
5470 && reg_reloaded_contents[i] == regno
5471 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5472 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5473 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5474 /* Even if we can't use this register as a reload
5475 register, we might use it for reload_override_in,
5476 if copying it to the desired class is cheap
5478 || ((REGISTER_MOVE_COST (mode, last_class, class)
5479 < MEMORY_MOVE_COST (mode, class, 1))
5480 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5481 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5485 #ifdef SECONDARY_MEMORY_NEEDED
5486 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5491 && (rld[r].nregs == max_group_size
5492 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5494 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5495 rld[r].when_needed, rld[r].in,
5498 /* If a group is needed, verify that all the subsequent
5499 registers still have their values intact. */
5500 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5503 for (k = 1; k < nr; k++)
5504 if (reg_reloaded_contents[i + k] != regno
5505 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5512 last_reg = (GET_MODE (last_reg) == mode
5513 ? last_reg : gen_rtx_REG (mode, i));
5515 /* We found a register that contains the
5516 value we need. If this register is the
5517 same as an `earlyclobber' operand of the
5518 current insn, just mark it as a place to
5519 reload from since we can't use it as the
5520 reload register itself. */
5522 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5523 if (reg_overlap_mentioned_for_reload_p
5524 (reg_last_reload_reg[regno],
5525 reload_earlyclobbers[i1]))
5528 if (i1 != n_earlyclobbers
5529 || ! (free_for_value_p (i, rld[r].mode,
5531 rld[r].when_needed, rld[r].in,
5533 /* Don't use it if we'd clobber a pseudo reg. */
5534 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5536 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5537 /* Don't clobber the frame pointer. */
5538 || (i == HARD_FRAME_POINTER_REGNUM
5540 /* Don't really use the inherited spill reg
5541 if we need it wider than we've got it. */
5542 || (GET_MODE_SIZE (rld[r].mode)
5543 > GET_MODE_SIZE (mode))
5544 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5547 /* If find_reloads chose reload_out as reload
5548 register, stay with it - that leaves the
5549 inherited register for subsequent reloads. */
5550 || (rld[r].out && rld[r].reg_rtx
5551 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5553 if (! rld[r].optional)
5555 reload_override_in[r] = last_reg;
5556 reload_inheritance_insn[r]
5557 = reg_reloaded_insn[i];
5563 /* We can use this as a reload reg. */
5564 /* Mark the register as in use for this part of
5566 mark_reload_reg_in_use (i,
5570 rld[r].reg_rtx = last_reg;
5571 reload_inherited[r] = 1;
5572 reload_inheritance_insn[r]
5573 = reg_reloaded_insn[i];
5574 reload_spill_index[r] = i;
5575 for (k = 0; k < nr; k++)
5576 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5584 /* Here's another way to see if the value is already lying around. */
5587 && ! reload_inherited[r]
5589 && (CONSTANT_P (rld[r].in)
5590 || GET_CODE (rld[r].in) == PLUS
5591 || GET_CODE (rld[r].in) == REG
5592 || GET_CODE (rld[r].in) == MEM)
5593 && (rld[r].nregs == max_group_size
5594 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5595 search_equiv = rld[r].in;
5596 /* If this is an output reload from a simple move insn, look
5597 if an equivalence for the input is available. */
5598 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5600 rtx set = single_set (insn);
5603 && rtx_equal_p (rld[r].out, SET_DEST (set))
5604 && CONSTANT_P (SET_SRC (set)))
5605 search_equiv = SET_SRC (set);
5611 = find_equiv_reg (search_equiv, insn, rld[r].class,
5612 -1, NULL, 0, rld[r].mode);
5617 if (GET_CODE (equiv) == REG)
5618 regno = REGNO (equiv);
5619 else if (GET_CODE (equiv) == SUBREG)
5621 /* This must be a SUBREG of a hard register.
5622 Make a new REG since this might be used in an
5623 address and not all machines support SUBREGs
5625 regno = subreg_regno (equiv);
5626 equiv = gen_rtx_REG (rld[r].mode, regno);
5632 /* If we found a spill reg, reject it unless it is free
5633 and of the desired class. */
5635 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5636 && ! free_for_value_p (regno, rld[r].mode,
5637 rld[r].opnum, rld[r].when_needed,
5638 rld[r].in, rld[r].out, r, 1))
5639 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5643 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5646 /* We found a register that contains the value we need.
5647 If this register is the same as an `earlyclobber' operand
5648 of the current insn, just mark it as a place to reload from
5649 since we can't use it as the reload register itself. */
5652 for (i = 0; i < n_earlyclobbers; i++)
5653 if (reg_overlap_mentioned_for_reload_p (equiv,
5654 reload_earlyclobbers[i]))
5656 if (! rld[r].optional)
5657 reload_override_in[r] = equiv;
5662 /* If the equiv register we have found is explicitly clobbered
5663 in the current insn, it depends on the reload type if we
5664 can use it, use it for reload_override_in, or not at all.
5665 In particular, we then can't use EQUIV for a
5666 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5670 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5671 switch (rld[r].when_needed)
5673 case RELOAD_FOR_OTHER_ADDRESS:
5674 case RELOAD_FOR_INPADDR_ADDRESS:
5675 case RELOAD_FOR_INPUT_ADDRESS:
5676 case RELOAD_FOR_OPADDR_ADDR:
5679 case RELOAD_FOR_INPUT:
5680 case RELOAD_FOR_OPERAND_ADDRESS:
5681 if (! rld[r].optional)
5682 reload_override_in[r] = equiv;
5688 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5689 switch (rld[r].when_needed)
5691 case RELOAD_FOR_OTHER_ADDRESS:
5692 case RELOAD_FOR_INPADDR_ADDRESS:
5693 case RELOAD_FOR_INPUT_ADDRESS:
5694 case RELOAD_FOR_OPADDR_ADDR:
5695 case RELOAD_FOR_OPERAND_ADDRESS:
5696 case RELOAD_FOR_INPUT:
5699 if (! rld[r].optional)
5700 reload_override_in[r] = equiv;
5708 /* If we found an equivalent reg, say no code need be generated
5709 to load it, and use it as our reload reg. */
5710 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5712 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5714 rld[r].reg_rtx = equiv;
5715 reload_inherited[r] = 1;
5717 /* If reg_reloaded_valid is not set for this register,
5718 there might be a stale spill_reg_store lying around.
5719 We must clear it, since otherwise emit_reload_insns
5720 might delete the store. */
5721 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5722 spill_reg_store[regno] = NULL_RTX;
5723 /* If any of the hard registers in EQUIV are spill
5724 registers, mark them as in use for this insn. */
5725 for (k = 0; k < nr; k++)
5727 i = spill_reg_order[regno + k];
5730 mark_reload_reg_in_use (regno, rld[r].opnum,
5733 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5740 /* If we found a register to use already, or if this is an optional
5741 reload, we are done. */
5742 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5746 /* No longer needed for correct operation. Might or might
5747 not give better code on the average. Want to experiment? */
5749 /* See if there is a later reload that has a class different from our
5750 class that intersects our class or that requires less register
5751 than our reload. If so, we must allocate a register to this
5752 reload now, since that reload might inherit a previous reload
5753 and take the only available register in our class. Don't do this
5754 for optional reloads since they will force all previous reloads
5755 to be allocated. Also don't do this for reloads that have been
5758 for (i = j + 1; i < n_reloads; i++)
5760 int s = reload_order[i];
5762 if ((rld[s].in == 0 && rld[s].out == 0
5763 && ! rld[s].secondary_p)
5767 if ((rld[s].class != rld[r].class
5768 && reg_classes_intersect_p (rld[r].class,
5770 || rld[s].nregs < rld[r].nregs)
5777 allocate_reload_reg (chain, r, j == n_reloads - 1);
5781 /* Now allocate reload registers for anything non-optional that
5782 didn't get one yet. */
5783 for (j = 0; j < n_reloads; j++)
5785 register int r = reload_order[j];
5787 /* Ignore reloads that got marked inoperative. */
5788 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5791 /* Skip reloads that already have a register allocated or are
5793 if (rld[r].reg_rtx != 0 || rld[r].optional)
5796 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5800 /* If that loop got all the way, we have won. */
5807 /* Loop around and try without any inheritance. */
5812 /* First undo everything done by the failed attempt
5813 to allocate with inheritance. */
5814 choose_reload_regs_init (chain, save_reload_reg_rtx);
5816 /* Some sanity tests to verify that the reloads found in the first
5817 pass are identical to the ones we have now. */
5818 if (chain->n_reloads != n_reloads)
5821 for (i = 0; i < n_reloads; i++)
5823 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5825 if (chain->rld[i].when_needed != rld[i].when_needed)
5827 for (j = 0; j < n_spills; j++)
5828 if (spill_regs[j] == chain->rld[i].regno)
5829 if (! set_reload_reg (j, i))
5830 failed_reload (chain->insn, i);
5834 /* If we thought we could inherit a reload, because it seemed that
5835 nothing else wanted the same reload register earlier in the insn,
5836 verify that assumption, now that all reloads have been assigned.
5837 Likewise for reloads where reload_override_in has been set. */
5839 /* If doing expensive optimizations, do one preliminary pass that doesn't
5840 cancel any inheritance, but removes reloads that have been needed only
5841 for reloads that we know can be inherited. */
5842 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5844 for (j = 0; j < n_reloads; j++)
5846 register int r = reload_order[j];
5848 if (reload_inherited[r] && rld[r].reg_rtx)
5849 check_reg = rld[r].reg_rtx;
5850 else if (reload_override_in[r]
5851 && (GET_CODE (reload_override_in[r]) == REG
5852 || GET_CODE (reload_override_in[r]) == SUBREG))
5853 check_reg = reload_override_in[r];
5856 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5857 rld[r].opnum, rld[r].when_needed, rld[r].in,
5858 (reload_inherited[r]
5859 ? rld[r].out : const0_rtx),
5864 reload_inherited[r] = 0;
5865 reload_override_in[r] = 0;
5867 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5868 reload_override_in, then we do not need its related
5869 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5870 likewise for other reload types.
5871 We handle this by removing a reload when its only replacement
5872 is mentioned in reload_in of the reload we are going to inherit.
5873 A special case are auto_inc expressions; even if the input is
5874 inherited, we still need the address for the output. We can
5875 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5876 If we suceeded removing some reload and we are doing a preliminary
5877 pass just to remove such reloads, make another pass, since the
5878 removal of one reload might allow us to inherit another one. */
5880 && rld[r].out != rld[r].in
5881 && remove_address_replacements (rld[r].in) && pass)
5886 /* Now that reload_override_in is known valid,
5887 actually override reload_in. */
5888 for (j = 0; j < n_reloads; j++)
5889 if (reload_override_in[j])
5890 rld[j].in = reload_override_in[j];
5892 /* If this reload won't be done because it has been cancelled or is
5893 optional and not inherited, clear reload_reg_rtx so other
5894 routines (such as subst_reloads) don't get confused. */
5895 for (j = 0; j < n_reloads; j++)
5896 if (rld[j].reg_rtx != 0
5897 && ((rld[j].optional && ! reload_inherited[j])
5898 || (rld[j].in == 0 && rld[j].out == 0
5899 && ! rld[j].secondary_p)))
5901 int regno = true_regnum (rld[j].reg_rtx);
5903 if (spill_reg_order[regno] >= 0)
5904 clear_reload_reg_in_use (regno, rld[j].opnum,
5905 rld[j].when_needed, rld[j].mode);
5907 reload_spill_index[j] = -1;
5910 /* Record which pseudos and which spill regs have output reloads. */
5911 for (j = 0; j < n_reloads; j++)
5913 register int r = reload_order[j];
5915 i = reload_spill_index[r];
5917 /* I is nonneg if this reload uses a register.
5918 If rld[r].reg_rtx is 0, this is an optional reload
5919 that we opted to ignore. */
5920 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5921 && rld[r].reg_rtx != 0)
5923 register int nregno = REGNO (rld[r].out_reg);
5926 if (nregno < FIRST_PSEUDO_REGISTER)
5927 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5930 reg_has_output_reload[nregno + nr] = 1;
5934 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5936 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5939 if (rld[r].when_needed != RELOAD_OTHER
5940 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5941 && rld[r].when_needed != RELOAD_FOR_INSN)
5947 /* Deallocate the reload register for reload R. This is called from
5948 remove_address_replacements. */
5951 deallocate_reload_reg (r)
5956 if (! rld[r].reg_rtx)
5958 regno = true_regnum (rld[r].reg_rtx);
5960 if (spill_reg_order[regno] >= 0)
5961 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5963 reload_spill_index[r] = -1;
5966 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5967 reloads of the same item for fear that we might not have enough reload
5968 registers. However, normally they will get the same reload register
5969 and hence actually need not be loaded twice.
5971 Here we check for the most common case of this phenomenon: when we have
5972 a number of reloads for the same object, each of which were allocated
5973 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5974 reload, and is not modified in the insn itself. If we find such,
5975 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5976 This will not increase the number of spill registers needed and will
5977 prevent redundant code. */
5980 merge_assigned_reloads (insn)
5985 /* Scan all the reloads looking for ones that only load values and
5986 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5987 assigned and not modified by INSN. */
5989 for (i = 0; i < n_reloads; i++)
5991 int conflicting_input = 0;
5992 int max_input_address_opnum = -1;
5993 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5995 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5996 || rld[i].out != 0 || rld[i].reg_rtx == 0
5997 || reg_set_p (rld[i].reg_rtx, insn))
6000 /* Look at all other reloads. Ensure that the only use of this
6001 reload_reg_rtx is in a reload that just loads the same value
6002 as we do. Note that any secondary reloads must be of the identical
6003 class since the values, modes, and result registers are the
6004 same, so we need not do anything with any secondary reloads. */
6006 for (j = 0; j < n_reloads; j++)
6008 if (i == j || rld[j].reg_rtx == 0
6009 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6013 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6014 && rld[j].opnum > max_input_address_opnum)
6015 max_input_address_opnum = rld[j].opnum;
6017 /* If the reload regs aren't exactly the same (e.g, different modes)
6018 or if the values are different, we can't merge this reload.
6019 But if it is an input reload, we might still merge
6020 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6022 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6023 || rld[j].out != 0 || rld[j].in == 0
6024 || ! rtx_equal_p (rld[i].in, rld[j].in))
6026 if (rld[j].when_needed != RELOAD_FOR_INPUT
6027 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6028 || rld[i].opnum > rld[j].opnum)
6029 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6031 conflicting_input = 1;
6032 if (min_conflicting_input_opnum > rld[j].opnum)
6033 min_conflicting_input_opnum = rld[j].opnum;
6037 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6038 we, in fact, found any matching reloads. */
6041 && max_input_address_opnum <= min_conflicting_input_opnum)
6043 for (j = 0; j < n_reloads; j++)
6044 if (i != j && rld[j].reg_rtx != 0
6045 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6046 && (! conflicting_input
6047 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6048 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6050 rld[i].when_needed = RELOAD_OTHER;
6052 reload_spill_index[j] = -1;
6053 transfer_replacements (i, j);
6056 /* If this is now RELOAD_OTHER, look for any reloads that load
6057 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6058 if they were for inputs, RELOAD_OTHER for outputs. Note that
6059 this test is equivalent to looking for reloads for this operand
6062 if (rld[i].when_needed == RELOAD_OTHER)
6063 for (j = 0; j < n_reloads; j++)
6065 && rld[i].when_needed != RELOAD_OTHER
6066 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6069 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6070 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6071 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6076 /* These arrays are filled by emit_reload_insns and its subroutines. */
6077 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6078 static rtx other_input_address_reload_insns = 0;
6079 static rtx other_input_reload_insns = 0;
6080 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6081 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6082 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6083 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6084 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6085 static rtx operand_reload_insns = 0;
6086 static rtx other_operand_reload_insns = 0;
6087 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6089 /* Values to be put in spill_reg_store are put here first. */
6090 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6091 static HARD_REG_SET reg_reloaded_died;
6093 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6094 has the number J. OLD contains the value to be used as input. */
6097 emit_input_reload_insns (chain, rl, old, j)
6098 struct insn_chain *chain;
6103 rtx insn = chain->insn;
6104 register rtx reloadreg = rl->reg_rtx;
6105 rtx oldequiv_reg = 0;
6108 enum machine_mode mode;
6111 /* Determine the mode to reload in.
6112 This is very tricky because we have three to choose from.
6113 There is the mode the insn operand wants (rl->inmode).
6114 There is the mode of the reload register RELOADREG.
6115 There is the intrinsic mode of the operand, which we could find
6116 by stripping some SUBREGs.
6117 It turns out that RELOADREG's mode is irrelevant:
6118 we can change that arbitrarily.
6120 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6121 then the reload reg may not support QImode moves, so use SImode.
6122 If foo is in memory due to spilling a pseudo reg, this is safe,
6123 because the QImode value is in the least significant part of a
6124 slot big enough for a SImode. If foo is some other sort of
6125 memory reference, then it is impossible to reload this case,
6126 so previous passes had better make sure this never happens.
6128 Then consider a one-word union which has SImode and one of its
6129 members is a float, being fetched as (SUBREG:SF union:SI).
6130 We must fetch that as SFmode because we could be loading into
6131 a float-only register. In this case OLD's mode is correct.
6133 Consider an immediate integer: it has VOIDmode. Here we need
6134 to get a mode from something else.
6136 In some cases, there is a fourth mode, the operand's
6137 containing mode. If the insn specifies a containing mode for
6138 this operand, it overrides all others.
6140 I am not sure whether the algorithm here is always right,
6141 but it does the right things in those cases. */
6143 mode = GET_MODE (old);
6144 if (mode == VOIDmode)
6147 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6148 /* If we need a secondary register for this operation, see if
6149 the value is already in a register in that class. Don't
6150 do this if the secondary register will be used as a scratch
6153 if (rl->secondary_in_reload >= 0
6154 && rl->secondary_in_icode == CODE_FOR_nothing
6157 = find_equiv_reg (old, insn,
6158 rld[rl->secondary_in_reload].class,
6162 /* If reloading from memory, see if there is a register
6163 that already holds the same value. If so, reload from there.
6164 We can pass 0 as the reload_reg_p argument because
6165 any other reload has either already been emitted,
6166 in which case find_equiv_reg will see the reload-insn,
6167 or has yet to be emitted, in which case it doesn't matter
6168 because we will use this equiv reg right away. */
6170 if (oldequiv == 0 && optimize
6171 && (GET_CODE (old) == MEM
6172 || (GET_CODE (old) == REG
6173 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6174 && reg_renumber[REGNO (old)] < 0)))
6175 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6179 unsigned int regno = true_regnum (oldequiv);
6181 /* Don't use OLDEQUIV if any other reload changes it at an
6182 earlier stage of this insn or at this stage. */
6183 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6184 rl->in, const0_rtx, j, 0))
6187 /* If it is no cheaper to copy from OLDEQUIV into the
6188 reload register than it would be to move from memory,
6189 don't use it. Likewise, if we need a secondary register
6193 && ((REGNO_REG_CLASS (regno) != rl->class
6194 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6196 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6197 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6198 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6202 #ifdef SECONDARY_MEMORY_NEEDED
6203 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6211 /* delete_output_reload is only invoked properly if old contains
6212 the original pseudo register. Since this is replaced with a
6213 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6214 find the pseudo in RELOAD_IN_REG. */
6216 && reload_override_in[j]
6217 && GET_CODE (rl->in_reg) == REG)
6224 else if (GET_CODE (oldequiv) == REG)
6225 oldequiv_reg = oldequiv;
6226 else if (GET_CODE (oldequiv) == SUBREG)
6227 oldequiv_reg = SUBREG_REG (oldequiv);
6229 /* If we are reloading from a register that was recently stored in
6230 with an output-reload, see if we can prove there was
6231 actually no need to store the old value in it. */
6233 if (optimize && GET_CODE (oldequiv) == REG
6234 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6235 && spill_reg_store[REGNO (oldequiv)]
6236 && GET_CODE (old) == REG
6237 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6238 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6240 delete_output_reload (insn, j, REGNO (oldequiv));
6242 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6243 then load RELOADREG from OLDEQUIV. Note that we cannot use
6244 gen_lowpart_common since it can do the wrong thing when
6245 RELOADREG has a multi-word mode. Note that RELOADREG
6246 must always be a REG here. */
6248 if (GET_MODE (reloadreg) != mode)
6249 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6250 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6251 oldequiv = SUBREG_REG (oldequiv);
6252 if (GET_MODE (oldequiv) != VOIDmode
6253 && mode != GET_MODE (oldequiv))
6254 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6256 /* Switch to the right place to emit the reload insns. */
6257 switch (rl->when_needed)
6260 where = &other_input_reload_insns;
6262 case RELOAD_FOR_INPUT:
6263 where = &input_reload_insns[rl->opnum];
6265 case RELOAD_FOR_INPUT_ADDRESS:
6266 where = &input_address_reload_insns[rl->opnum];
6268 case RELOAD_FOR_INPADDR_ADDRESS:
6269 where = &inpaddr_address_reload_insns[rl->opnum];
6271 case RELOAD_FOR_OUTPUT_ADDRESS:
6272 where = &output_address_reload_insns[rl->opnum];
6274 case RELOAD_FOR_OUTADDR_ADDRESS:
6275 where = &outaddr_address_reload_insns[rl->opnum];
6277 case RELOAD_FOR_OPERAND_ADDRESS:
6278 where = &operand_reload_insns;
6280 case RELOAD_FOR_OPADDR_ADDR:
6281 where = &other_operand_reload_insns;
6283 case RELOAD_FOR_OTHER_ADDRESS:
6284 where = &other_input_address_reload_insns;
6290 push_to_sequence (*where);
6292 /* Auto-increment addresses must be reloaded in a special way. */
6293 if (rl->out && ! rl->out_reg)
6295 /* We are not going to bother supporting the case where a
6296 incremented register can't be copied directly from
6297 OLDEQUIV since this seems highly unlikely. */
6298 if (rl->secondary_in_reload >= 0)
6301 if (reload_inherited[j])
6302 oldequiv = reloadreg;
6304 old = XEXP (rl->in_reg, 0);
6306 if (optimize && GET_CODE (oldequiv) == REG
6307 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6308 && spill_reg_store[REGNO (oldequiv)]
6309 && GET_CODE (old) == REG
6310 && (dead_or_set_p (insn,
6311 spill_reg_stored_to[REGNO (oldequiv)])
6312 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6314 delete_output_reload (insn, j, REGNO (oldequiv));
6316 /* Prevent normal processing of this reload. */
6318 /* Output a special code sequence for this case. */
6319 new_spill_reg_store[REGNO (reloadreg)]
6320 = inc_for_reload (reloadreg, oldequiv, rl->out,
6324 /* If we are reloading a pseudo-register that was set by the previous
6325 insn, see if we can get rid of that pseudo-register entirely
6326 by redirecting the previous insn into our reload register. */
6328 else if (optimize && GET_CODE (old) == REG
6329 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6330 && dead_or_set_p (insn, old)
6331 /* This is unsafe if some other reload
6332 uses the same reg first. */
6333 && ! conflicts_with_override (reloadreg)
6334 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6335 rl->when_needed, old, rl->out, j, 0))
6337 rtx temp = PREV_INSN (insn);
6338 while (temp && GET_CODE (temp) == NOTE)
6339 temp = PREV_INSN (temp);
6341 && GET_CODE (temp) == INSN
6342 && GET_CODE (PATTERN (temp)) == SET
6343 && SET_DEST (PATTERN (temp)) == old
6344 /* Make sure we can access insn_operand_constraint. */
6345 && asm_noperands (PATTERN (temp)) < 0
6346 /* This is unsafe if prev insn rejects our reload reg. */
6347 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6349 /* This is unsafe if operand occurs more than once in current
6350 insn. Perhaps some occurrences aren't reloaded. */
6351 && count_occurrences (PATTERN (insn), old, 0) == 1
6352 /* Don't risk splitting a matching pair of operands. */
6353 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6355 /* Store into the reload register instead of the pseudo. */
6356 SET_DEST (PATTERN (temp)) = reloadreg;
6358 /* If the previous insn is an output reload, the source is
6359 a reload register, and its spill_reg_store entry will
6360 contain the previous destination. This is now
6362 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6363 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6365 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6366 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6369 /* If these are the only uses of the pseudo reg,
6370 pretend for GDB it lives in the reload reg we used. */
6371 if (REG_N_DEATHS (REGNO (old)) == 1
6372 && REG_N_SETS (REGNO (old)) == 1)
6374 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6375 alter_reg (REGNO (old), -1);
6381 /* We can't do that, so output an insn to load RELOADREG. */
6383 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6384 /* If we have a secondary reload, pick up the secondary register
6385 and icode, if any. If OLDEQUIV and OLD are different or
6386 if this is an in-out reload, recompute whether or not we
6387 still need a secondary register and what the icode should
6388 be. If we still need a secondary register and the class or
6389 icode is different, go back to reloading from OLD if using
6390 OLDEQUIV means that we got the wrong type of register. We
6391 cannot have different class or icode due to an in-out reload
6392 because we don't make such reloads when both the input and
6393 output need secondary reload registers. */
6395 if (! special && rl->secondary_in_reload >= 0)
6397 rtx second_reload_reg = 0;
6398 int secondary_reload = rl->secondary_in_reload;
6399 rtx real_oldequiv = oldequiv;
6402 enum insn_code icode;
6404 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6405 and similarly for OLD.
6406 See comments in get_secondary_reload in reload.c. */
6407 /* If it is a pseudo that cannot be replaced with its
6408 equivalent MEM, we must fall back to reload_in, which
6409 will have all the necessary substitutions registered.
6410 Likewise for a pseudo that can't be replaced with its
6411 equivalent constant.
6413 Take extra care for subregs of such pseudos. Note that
6414 we cannot use reg_equiv_mem in this case because it is
6415 not in the right mode. */
6418 if (GET_CODE (tmp) == SUBREG)
6419 tmp = SUBREG_REG (tmp);
6420 if (GET_CODE (tmp) == REG
6421 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6422 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6423 || reg_equiv_constant[REGNO (tmp)] != 0))
6425 if (! reg_equiv_mem[REGNO (tmp)]
6426 || num_not_at_initial_offset
6427 || GET_CODE (oldequiv) == SUBREG)
6428 real_oldequiv = rl->in;
6430 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6434 if (GET_CODE (tmp) == SUBREG)
6435 tmp = SUBREG_REG (tmp);
6436 if (GET_CODE (tmp) == REG
6437 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6438 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6439 || reg_equiv_constant[REGNO (tmp)] != 0))
6441 if (! reg_equiv_mem[REGNO (tmp)]
6442 || num_not_at_initial_offset
6443 || GET_CODE (old) == SUBREG)
6446 real_old = reg_equiv_mem[REGNO (tmp)];
6449 second_reload_reg = rld[secondary_reload].reg_rtx;
6450 icode = rl->secondary_in_icode;
6452 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6453 || (rl->in != 0 && rl->out != 0))
6455 enum reg_class new_class
6456 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6457 mode, real_oldequiv);
6459 if (new_class == NO_REGS)
6460 second_reload_reg = 0;
6463 enum insn_code new_icode;
6464 enum machine_mode new_mode;
6466 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6467 REGNO (second_reload_reg)))
6468 oldequiv = old, real_oldequiv = real_old;
6471 new_icode = reload_in_optab[(int) mode];
6472 if (new_icode != CODE_FOR_nothing
6473 && ((insn_data[(int) new_icode].operand[0].predicate
6474 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6476 || (insn_data[(int) new_icode].operand[1].predicate
6477 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6478 (real_oldequiv, mode)))))
6479 new_icode = CODE_FOR_nothing;
6481 if (new_icode == CODE_FOR_nothing)
6484 new_mode = insn_data[(int) new_icode].operand[2].mode;
6486 if (GET_MODE (second_reload_reg) != new_mode)
6488 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6490 oldequiv = old, real_oldequiv = real_old;
6493 = gen_rtx_REG (new_mode,
6494 REGNO (second_reload_reg));
6500 /* If we still need a secondary reload register, check
6501 to see if it is being used as a scratch or intermediate
6502 register and generate code appropriately. If we need
6503 a scratch register, use REAL_OLDEQUIV since the form of
6504 the insn may depend on the actual address if it is
6507 if (second_reload_reg)
6509 if (icode != CODE_FOR_nothing)
6511 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6512 second_reload_reg));
6517 /* See if we need a scratch register to load the
6518 intermediate register (a tertiary reload). */
6519 enum insn_code tertiary_icode
6520 = rld[secondary_reload].secondary_in_icode;
6522 if (tertiary_icode != CODE_FOR_nothing)
6524 rtx third_reload_reg
6525 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6527 emit_insn ((GEN_FCN (tertiary_icode)
6528 (second_reload_reg, real_oldequiv,
6529 third_reload_reg)));
6532 gen_reload (second_reload_reg, real_oldequiv,
6536 oldequiv = second_reload_reg;
6542 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6544 rtx real_oldequiv = oldequiv;
6546 if ((GET_CODE (oldequiv) == REG
6547 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6548 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6549 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6550 || (GET_CODE (oldequiv) == SUBREG
6551 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6552 && (REGNO (SUBREG_REG (oldequiv))
6553 >= FIRST_PSEUDO_REGISTER)
6554 && ((reg_equiv_memory_loc
6555 [REGNO (SUBREG_REG (oldequiv))] != 0)
6556 || (reg_equiv_constant
6557 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6558 || (CONSTANT_P (oldequiv)
6559 && PREFERRED_RELOAD_CLASS (oldequiv,
6560 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6561 real_oldequiv = rl->in;
6562 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6566 if (flag_non_call_exceptions)
6567 copy_eh_notes (insn, get_insns ());
6569 /* End this sequence. */
6570 *where = get_insns ();
6573 /* Update reload_override_in so that delete_address_reloads_1
6574 can see the actual register usage. */
6576 reload_override_in[j] = oldequiv;
6579 /* Generate insns to for the output reload RL, which is for the insn described
6580 by CHAIN and has the number J. */
6582 emit_output_reload_insns (chain, rl, j)
6583 struct insn_chain *chain;
6587 rtx reloadreg = rl->reg_rtx;
6588 rtx insn = chain->insn;
6591 enum machine_mode mode = GET_MODE (old);
6594 if (rl->when_needed == RELOAD_OTHER)
6597 push_to_sequence (output_reload_insns[rl->opnum]);
6599 /* Determine the mode to reload in.
6600 See comments above (for input reloading). */
6602 if (mode == VOIDmode)
6604 /* VOIDmode should never happen for an output. */
6605 if (asm_noperands (PATTERN (insn)) < 0)
6606 /* It's the compiler's fault. */
6607 fatal_insn ("VOIDmode on an output", insn);
6608 error_for_asm (insn, "output operand is constant in `asm'");
6609 /* Prevent crash--use something we know is valid. */
6611 old = gen_rtx_REG (mode, REGNO (reloadreg));
6614 if (GET_MODE (reloadreg) != mode)
6615 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6617 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6619 /* If we need two reload regs, set RELOADREG to the intermediate
6620 one, since it will be stored into OLD. We might need a secondary
6621 register only for an input reload, so check again here. */
6623 if (rl->secondary_out_reload >= 0)
6627 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6628 && reg_equiv_mem[REGNO (old)] != 0)
6629 real_old = reg_equiv_mem[REGNO (old)];
6631 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6635 rtx second_reloadreg = reloadreg;
6636 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6638 /* See if RELOADREG is to be used as a scratch register
6639 or as an intermediate register. */
6640 if (rl->secondary_out_icode != CODE_FOR_nothing)
6642 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6643 (real_old, second_reloadreg, reloadreg)));
6648 /* See if we need both a scratch and intermediate reload
6651 int secondary_reload = rl->secondary_out_reload;
6652 enum insn_code tertiary_icode
6653 = rld[secondary_reload].secondary_out_icode;
6655 if (GET_MODE (reloadreg) != mode)
6656 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6658 if (tertiary_icode != CODE_FOR_nothing)
6661 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6664 /* Copy primary reload reg to secondary reload reg.
6665 (Note that these have been swapped above, then
6666 secondary reload reg to OLD using our insn.) */
6668 /* If REAL_OLD is a paradoxical SUBREG, remove it
6669 and try to put the opposite SUBREG on
6671 if (GET_CODE (real_old) == SUBREG
6672 && (GET_MODE_SIZE (GET_MODE (real_old))
6673 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6674 && 0 != (tem = gen_lowpart_common
6675 (GET_MODE (SUBREG_REG (real_old)),
6677 real_old = SUBREG_REG (real_old), reloadreg = tem;
6679 gen_reload (reloadreg, second_reloadreg,
6680 rl->opnum, rl->when_needed);
6681 emit_insn ((GEN_FCN (tertiary_icode)
6682 (real_old, reloadreg, third_reloadreg)));
6687 /* Copy between the reload regs here and then to
6690 gen_reload (reloadreg, second_reloadreg,
6691 rl->opnum, rl->when_needed);
6697 /* Output the last reload insn. */
6702 /* Don't output the last reload if OLD is not the dest of
6703 INSN and is in the src and is clobbered by INSN. */
6704 if (! flag_expensive_optimizations
6705 || GET_CODE (old) != REG
6706 || !(set = single_set (insn))
6707 || rtx_equal_p (old, SET_DEST (set))
6708 || !reg_mentioned_p (old, SET_SRC (set))
6709 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6710 gen_reload (old, reloadreg, rl->opnum,
6714 /* Look at all insns we emitted, just to be safe. */
6715 for (p = get_insns (); p; p = NEXT_INSN (p))
6718 rtx pat = PATTERN (p);
6720 /* If this output reload doesn't come from a spill reg,
6721 clear any memory of reloaded copies of the pseudo reg.
6722 If this output reload comes from a spill reg,
6723 reg_has_output_reload will make this do nothing. */
6724 note_stores (pat, forget_old_reloads_1, NULL);
6726 if (reg_mentioned_p (rl->reg_rtx, pat))
6728 rtx set = single_set (insn);
6729 if (reload_spill_index[j] < 0
6731 && SET_SRC (set) == rl->reg_rtx)
6733 int src = REGNO (SET_SRC (set));
6735 reload_spill_index[j] = src;
6736 SET_HARD_REG_BIT (reg_is_output_reload, src);
6737 if (find_regno_note (insn, REG_DEAD, src))
6738 SET_HARD_REG_BIT (reg_reloaded_died, src);
6740 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6742 int s = rl->secondary_out_reload;
6743 set = single_set (p);
6744 /* If this reload copies only to the secondary reload
6745 register, the secondary reload does the actual
6747 if (s >= 0 && set == NULL_RTX)
6748 /* We can't tell what function the secondary reload
6749 has and where the actual store to the pseudo is
6750 made; leave new_spill_reg_store alone. */
6753 && SET_SRC (set) == rl->reg_rtx
6754 && SET_DEST (set) == rld[s].reg_rtx)
6756 /* Usually the next instruction will be the
6757 secondary reload insn; if we can confirm
6758 that it is, setting new_spill_reg_store to
6759 that insn will allow an extra optimization. */
6760 rtx s_reg = rld[s].reg_rtx;
6761 rtx next = NEXT_INSN (p);
6762 rld[s].out = rl->out;
6763 rld[s].out_reg = rl->out_reg;
6764 set = single_set (next);
6765 if (set && SET_SRC (set) == s_reg
6766 && ! new_spill_reg_store[REGNO (s_reg)])
6768 SET_HARD_REG_BIT (reg_is_output_reload,
6770 new_spill_reg_store[REGNO (s_reg)] = next;
6774 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6779 if (rl->when_needed == RELOAD_OTHER)
6781 emit_insns (other_output_reload_insns[rl->opnum]);
6782 other_output_reload_insns[rl->opnum] = get_insns ();
6785 output_reload_insns[rl->opnum] = get_insns ();
6787 if (flag_non_call_exceptions)
6788 copy_eh_notes (insn, get_insns ());
6793 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6794 and has the number J. */
6796 do_input_reload (chain, rl, j)
6797 struct insn_chain *chain;
6801 int expect_occurrences = 1;
6802 rtx insn = chain->insn;
6803 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6804 ? rl->in_reg : rl->in);
6807 /* AUTO_INC reloads need to be handled even if inherited. We got an
6808 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6809 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6810 && ! rtx_equal_p (rl->reg_rtx, old)
6811 && rl->reg_rtx != 0)
6812 emit_input_reload_insns (chain, rld + j, old, j);
6814 /* When inheriting a wider reload, we have a MEM in rl->in,
6815 e.g. inheriting a SImode output reload for
6816 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6817 if (optimize && reload_inherited[j] && rl->in
6818 && GET_CODE (rl->in) == MEM
6819 && GET_CODE (rl->in_reg) == MEM
6820 && reload_spill_index[j] >= 0
6821 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6824 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6825 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6828 /* If we are reloading a register that was recently stored in with an
6829 output-reload, see if we can prove there was
6830 actually no need to store the old value in it. */
6833 && (reload_inherited[j] || reload_override_in[j])
6835 && GET_CODE (rl->reg_rtx) == REG
6836 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6838 /* There doesn't seem to be any reason to restrict this to pseudos
6839 and doing so loses in the case where we are copying from a
6840 register of the wrong class. */
6841 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6842 >= FIRST_PSEUDO_REGISTER)
6844 /* The insn might have already some references to stackslots
6845 replaced by MEMs, while reload_out_reg still names the
6847 && (dead_or_set_p (insn,
6848 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6849 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6851 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6854 /* Do output reloading for reload RL, which is for the insn described by
6855 CHAIN and has the number J.
6856 ??? At some point we need to support handling output reloads of
6857 JUMP_INSNs or insns that set cc0. */
6859 do_output_reload (chain, rl, j)
6860 struct insn_chain *chain;
6865 rtx insn = chain->insn;
6866 /* If this is an output reload that stores something that is
6867 not loaded in this same reload, see if we can eliminate a previous
6869 rtx pseudo = rl->out_reg;
6872 && GET_CODE (pseudo) == REG
6873 && ! rtx_equal_p (rl->in_reg, pseudo)
6874 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6875 && reg_last_reload_reg[REGNO (pseudo)])
6877 int pseudo_no = REGNO (pseudo);
6878 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6880 /* We don't need to test full validity of last_regno for
6881 inherit here; we only want to know if the store actually
6882 matches the pseudo. */
6883 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6884 && reg_reloaded_contents[last_regno] == pseudo_no
6885 && spill_reg_store[last_regno]
6886 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6887 delete_output_reload (insn, j, last_regno);
6892 || rl->reg_rtx == old
6893 || rl->reg_rtx == 0)
6896 /* An output operand that dies right away does need a reload,
6897 but need not be copied from it. Show the new location in the
6899 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6900 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6902 XEXP (note, 0) = rl->reg_rtx;
6905 /* Likewise for a SUBREG of an operand that dies. */
6906 else if (GET_CODE (old) == SUBREG
6907 && GET_CODE (SUBREG_REG (old)) == REG
6908 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6911 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6915 else if (GET_CODE (old) == SCRATCH)
6916 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6917 but we don't want to make an output reload. */
6920 /* If is a JUMP_INSN, we can't support output reloads yet. */
6921 if (GET_CODE (insn) == JUMP_INSN)
6924 emit_output_reload_insns (chain, rld + j, j);
6927 /* Output insns to reload values in and out of the chosen reload regs. */
6930 emit_reload_insns (chain)
6931 struct insn_chain *chain;
6933 rtx insn = chain->insn;
6936 rtx following_insn = NEXT_INSN (insn);
6937 rtx before_insn = PREV_INSN (insn);
6939 CLEAR_HARD_REG_SET (reg_reloaded_died);
6941 for (j = 0; j < reload_n_operands; j++)
6942 input_reload_insns[j] = input_address_reload_insns[j]
6943 = inpaddr_address_reload_insns[j]
6944 = output_reload_insns[j] = output_address_reload_insns[j]
6945 = outaddr_address_reload_insns[j]
6946 = other_output_reload_insns[j] = 0;
6947 other_input_address_reload_insns = 0;
6948 other_input_reload_insns = 0;
6949 operand_reload_insns = 0;
6950 other_operand_reload_insns = 0;
6952 /* Dump reloads into the dump file. */
6955 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6956 debug_reload_to_stream (rtl_dump_file);
6959 /* Now output the instructions to copy the data into and out of the
6960 reload registers. Do these in the order that the reloads were reported,
6961 since reloads of base and index registers precede reloads of operands
6962 and the operands may need the base and index registers reloaded. */
6964 for (j = 0; j < n_reloads; j++)
6967 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6968 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6970 do_input_reload (chain, rld + j, j);
6971 do_output_reload (chain, rld + j, j);
6974 /* Now write all the insns we made for reloads in the order expected by
6975 the allocation functions. Prior to the insn being reloaded, we write
6976 the following reloads:
6978 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6980 RELOAD_OTHER reloads.
6982 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6983 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6984 RELOAD_FOR_INPUT reload for the operand.
6986 RELOAD_FOR_OPADDR_ADDRS reloads.
6988 RELOAD_FOR_OPERAND_ADDRESS reloads.
6990 After the insn being reloaded, we write the following:
6992 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6993 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6994 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6995 reloads for the operand. The RELOAD_OTHER output reloads are
6996 output in descending order by reload number. */
6998 emit_insns_before (other_input_address_reload_insns, insn);
6999 emit_insns_before (other_input_reload_insns, insn);
7001 for (j = 0; j < reload_n_operands; j++)
7003 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7004 emit_insns_before (input_address_reload_insns[j], insn);
7005 emit_insns_before (input_reload_insns[j], insn);
7008 emit_insns_before (other_operand_reload_insns, insn);
7009 emit_insns_before (operand_reload_insns, insn);
7011 for (j = 0; j < reload_n_operands; j++)
7013 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7014 emit_insns_before (output_address_reload_insns[j], following_insn);
7015 emit_insns_before (output_reload_insns[j], following_insn);
7016 emit_insns_before (other_output_reload_insns[j], following_insn);
7019 /* Keep basic block info up to date. */
7022 if (BLOCK_HEAD (chain->block) == insn)
7023 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7024 if (BLOCK_END (chain->block) == insn)
7025 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7028 /* For all the spill regs newly reloaded in this instruction,
7029 record what they were reloaded from, so subsequent instructions
7030 can inherit the reloads.
7032 Update spill_reg_store for the reloads of this insn.
7033 Copy the elements that were updated in the loop above. */
7035 for (j = 0; j < n_reloads; j++)
7037 register int r = reload_order[j];
7038 register int i = reload_spill_index[r];
7040 /* If this is a non-inherited input reload from a pseudo, we must
7041 clear any memory of a previous store to the same pseudo. Only do
7042 something if there will not be an output reload for the pseudo
7044 if (rld[r].in_reg != 0
7045 && ! (reload_inherited[r] || reload_override_in[r]))
7047 rtx reg = rld[r].in_reg;
7049 if (GET_CODE (reg) == SUBREG)
7050 reg = SUBREG_REG (reg);
7052 if (GET_CODE (reg) == REG
7053 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7054 && ! reg_has_output_reload[REGNO (reg)])
7056 int nregno = REGNO (reg);
7058 if (reg_last_reload_reg[nregno])
7060 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7062 if (reg_reloaded_contents[last_regno] == nregno)
7063 spill_reg_store[last_regno] = 0;
7068 /* I is nonneg if this reload used a register.
7069 If rld[r].reg_rtx is 0, this is an optional reload
7070 that we opted to ignore. */
7072 if (i >= 0 && rld[r].reg_rtx != 0)
7074 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7076 int part_reaches_end = 0;
7077 int all_reaches_end = 1;
7079 /* For a multi register reload, we need to check if all or part
7080 of the value lives to the end. */
7081 for (k = 0; k < nr; k++)
7083 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7084 rld[r].when_needed))
7085 part_reaches_end = 1;
7087 all_reaches_end = 0;
7090 /* Ignore reloads that don't reach the end of the insn in
7092 if (all_reaches_end)
7094 /* First, clear out memory of what used to be in this spill reg.
7095 If consecutive registers are used, clear them all. */
7097 for (k = 0; k < nr; k++)
7098 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7100 /* Maybe the spill reg contains a copy of reload_out. */
7102 && (GET_CODE (rld[r].out) == REG
7106 || GET_CODE (rld[r].out_reg) == REG))
7108 rtx out = (GET_CODE (rld[r].out) == REG
7112 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7113 register int nregno = REGNO (out);
7114 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7115 : HARD_REGNO_NREGS (nregno,
7116 GET_MODE (rld[r].reg_rtx)));
7118 spill_reg_store[i] = new_spill_reg_store[i];
7119 spill_reg_stored_to[i] = out;
7120 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7122 /* If NREGNO is a hard register, it may occupy more than
7123 one register. If it does, say what is in the
7124 rest of the registers assuming that both registers
7125 agree on how many words the object takes. If not,
7126 invalidate the subsequent registers. */
7128 if (nregno < FIRST_PSEUDO_REGISTER)
7129 for (k = 1; k < nnr; k++)
7130 reg_last_reload_reg[nregno + k]
7132 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7133 REGNO (rld[r].reg_rtx) + k)
7136 /* Now do the inverse operation. */
7137 for (k = 0; k < nr; k++)
7139 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7140 reg_reloaded_contents[i + k]
7141 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7144 reg_reloaded_insn[i + k] = insn;
7145 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7149 /* Maybe the spill reg contains a copy of reload_in. Only do
7150 something if there will not be an output reload for
7151 the register being reloaded. */
7152 else if (rld[r].out_reg == 0
7154 && ((GET_CODE (rld[r].in) == REG
7155 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7156 && ! reg_has_output_reload[REGNO (rld[r].in)])
7157 || (GET_CODE (rld[r].in_reg) == REG
7158 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7159 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7161 register int nregno;
7164 if (GET_CODE (rld[r].in) == REG
7165 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7166 nregno = REGNO (rld[r].in);
7167 else if (GET_CODE (rld[r].in_reg) == REG)
7168 nregno = REGNO (rld[r].in_reg);
7170 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7172 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7173 : HARD_REGNO_NREGS (nregno,
7174 GET_MODE (rld[r].reg_rtx)));
7176 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7178 if (nregno < FIRST_PSEUDO_REGISTER)
7179 for (k = 1; k < nnr; k++)
7180 reg_last_reload_reg[nregno + k]
7182 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7183 REGNO (rld[r].reg_rtx) + k)
7186 /* Unless we inherited this reload, show we haven't
7187 recently done a store.
7188 Previous stores of inherited auto_inc expressions
7189 also have to be discarded. */
7190 if (! reload_inherited[r]
7191 || (rld[r].out && ! rld[r].out_reg))
7192 spill_reg_store[i] = 0;
7194 for (k = 0; k < nr; k++)
7196 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7197 reg_reloaded_contents[i + k]
7198 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7201 reg_reloaded_insn[i + k] = insn;
7202 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7207 /* However, if part of the reload reaches the end, then we must
7208 invalidate the old info for the part that survives to the end. */
7209 else if (part_reaches_end)
7211 for (k = 0; k < nr; k++)
7212 if (reload_reg_reaches_end_p (i + k,
7214 rld[r].when_needed))
7215 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7219 /* The following if-statement was #if 0'd in 1.34 (or before...).
7220 It's reenabled in 1.35 because supposedly nothing else
7221 deals with this problem. */
7223 /* If a register gets output-reloaded from a non-spill register,
7224 that invalidates any previous reloaded copy of it.
7225 But forget_old_reloads_1 won't get to see it, because
7226 it thinks only about the original insn. So invalidate it here. */
7227 if (i < 0 && rld[r].out != 0
7228 && (GET_CODE (rld[r].out) == REG
7229 || (GET_CODE (rld[r].out) == MEM
7230 && GET_CODE (rld[r].out_reg) == REG)))
7232 rtx out = (GET_CODE (rld[r].out) == REG
7233 ? rld[r].out : rld[r].out_reg);
7234 register int nregno = REGNO (out);
7235 if (nregno >= FIRST_PSEUDO_REGISTER)
7237 rtx src_reg, store_insn = NULL_RTX;
7239 reg_last_reload_reg[nregno] = 0;
7241 /* If we can find a hard register that is stored, record
7242 the storing insn so that we may delete this insn with
7243 delete_output_reload. */
7244 src_reg = rld[r].reg_rtx;
7246 /* If this is an optional reload, try to find the source reg
7247 from an input reload. */
7250 rtx set = single_set (insn);
7251 if (set && SET_DEST (set) == rld[r].out)
7255 src_reg = SET_SRC (set);
7257 for (k = 0; k < n_reloads; k++)
7259 if (rld[k].in == src_reg)
7261 src_reg = rld[k].reg_rtx;
7268 store_insn = new_spill_reg_store[REGNO (src_reg)];
7269 if (src_reg && GET_CODE (src_reg) == REG
7270 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7272 int src_regno = REGNO (src_reg);
7273 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7274 /* The place where to find a death note varies with
7275 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7276 necessarily checked exactly in the code that moves
7277 notes, so just check both locations. */
7278 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7280 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7283 spill_reg_store[src_regno + nr] = store_insn;
7284 spill_reg_stored_to[src_regno + nr] = out;
7285 reg_reloaded_contents[src_regno + nr] = nregno;
7286 reg_reloaded_insn[src_regno + nr] = store_insn;
7287 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7288 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7289 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7291 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7293 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7295 reg_last_reload_reg[nregno] = src_reg;
7300 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7302 while (num_regs-- > 0)
7303 reg_last_reload_reg[nregno + num_regs] = 0;
7307 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7310 /* Emit code to perform a reload from IN (which may be a reload register) to
7311 OUT (which may also be a reload register). IN or OUT is from operand
7312 OPNUM with reload type TYPE.
7314 Returns first insn emitted. */
7317 gen_reload (out, in, opnum, type)
7321 enum reload_type type;
7323 rtx last = get_last_insn ();
7326 /* If IN is a paradoxical SUBREG, remove it and try to put the
7327 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7328 if (GET_CODE (in) == SUBREG
7329 && (GET_MODE_SIZE (GET_MODE (in))
7330 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7331 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7332 in = SUBREG_REG (in), out = tem;
7333 else if (GET_CODE (out) == SUBREG
7334 && (GET_MODE_SIZE (GET_MODE (out))
7335 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7336 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7337 out = SUBREG_REG (out), in = tem;
7339 /* How to do this reload can get quite tricky. Normally, we are being
7340 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7341 register that didn't get a hard register. In that case we can just
7342 call emit_move_insn.
7344 We can also be asked to reload a PLUS that adds a register or a MEM to
7345 another register, constant or MEM. This can occur during frame pointer
7346 elimination and while reloading addresses. This case is handled by
7347 trying to emit a single insn to perform the add. If it is not valid,
7348 we use a two insn sequence.
7350 Finally, we could be called to handle an 'o' constraint by putting
7351 an address into a register. In that case, we first try to do this
7352 with a named pattern of "reload_load_address". If no such pattern
7353 exists, we just emit a SET insn and hope for the best (it will normally
7354 be valid on machines that use 'o').
7356 This entire process is made complex because reload will never
7357 process the insns we generate here and so we must ensure that
7358 they will fit their constraints and also by the fact that parts of
7359 IN might be being reloaded separately and replaced with spill registers.
7360 Because of this, we are, in some sense, just guessing the right approach
7361 here. The one listed above seems to work.
7363 ??? At some point, this whole thing needs to be rethought. */
7365 if (GET_CODE (in) == PLUS
7366 && (GET_CODE (XEXP (in, 0)) == REG
7367 || GET_CODE (XEXP (in, 0)) == SUBREG
7368 || GET_CODE (XEXP (in, 0)) == MEM)
7369 && (GET_CODE (XEXP (in, 1)) == REG
7370 || GET_CODE (XEXP (in, 1)) == SUBREG
7371 || CONSTANT_P (XEXP (in, 1))
7372 || GET_CODE (XEXP (in, 1)) == MEM))
7374 /* We need to compute the sum of a register or a MEM and another
7375 register, constant, or MEM, and put it into the reload
7376 register. The best possible way of doing this is if the machine
7377 has a three-operand ADD insn that accepts the required operands.
7379 The simplest approach is to try to generate such an insn and see if it
7380 is recognized and matches its constraints. If so, it can be used.
7382 It might be better not to actually emit the insn unless it is valid,
7383 but we need to pass the insn as an operand to `recog' and
7384 `extract_insn' and it is simpler to emit and then delete the insn if
7385 not valid than to dummy things up. */
7387 rtx op0, op1, tem, insn;
7390 op0 = find_replacement (&XEXP (in, 0));
7391 op1 = find_replacement (&XEXP (in, 1));
7393 /* Since constraint checking is strict, commutativity won't be
7394 checked, so we need to do that here to avoid spurious failure
7395 if the add instruction is two-address and the second operand
7396 of the add is the same as the reload reg, which is frequently
7397 the case. If the insn would be A = B + A, rearrange it so
7398 it will be A = A + B as constrain_operands expects. */
7400 if (GET_CODE (XEXP (in, 1)) == REG
7401 && REGNO (out) == REGNO (XEXP (in, 1)))
7402 tem = op0, op0 = op1, op1 = tem;
7404 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7405 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7407 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7408 code = recog_memoized (insn);
7412 extract_insn (insn);
7413 /* We want constrain operands to treat this insn strictly in
7414 its validity determination, i.e., the way it would after reload
7416 if (constrain_operands (1))
7420 delete_insns_since (last);
7422 /* If that failed, we must use a conservative two-insn sequence.
7424 Use a move to copy one operand into the reload register. Prefer
7425 to reload a constant, MEM or pseudo since the move patterns can
7426 handle an arbitrary operand. If OP1 is not a constant, MEM or
7427 pseudo and OP1 is not a valid operand for an add instruction, then
7430 After reloading one of the operands into the reload register, add
7431 the reload register to the output register.
7433 If there is another way to do this for a specific machine, a
7434 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7437 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7439 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7440 || (GET_CODE (op1) == REG
7441 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7442 || (code != CODE_FOR_nothing
7443 && ! ((*insn_data[code].operand[2].predicate)
7444 (op1, insn_data[code].operand[2].mode))))
7445 tem = op0, op0 = op1, op1 = tem;
7447 gen_reload (out, op0, opnum, type);
7449 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7450 This fixes a problem on the 32K where the stack pointer cannot
7451 be used as an operand of an add insn. */
7453 if (rtx_equal_p (op0, op1))
7456 insn = emit_insn (gen_add2_insn (out, op1));
7458 /* If that failed, copy the address register to the reload register.
7459 Then add the constant to the reload register. */
7461 code = recog_memoized (insn);
7465 extract_insn (insn);
7466 /* We want constrain operands to treat this insn strictly in
7467 its validity determination, i.e., the way it would after reload
7469 if (constrain_operands (1))
7471 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7473 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7478 delete_insns_since (last);
7480 gen_reload (out, op1, opnum, type);
7481 insn = emit_insn (gen_add2_insn (out, op0));
7482 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7485 #ifdef SECONDARY_MEMORY_NEEDED
7486 /* If we need a memory location to do the move, do it that way. */
7487 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7488 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7489 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7490 REGNO_REG_CLASS (REGNO (out)),
7493 /* Get the memory to use and rewrite both registers to its mode. */
7494 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7496 if (GET_MODE (loc) != GET_MODE (out))
7497 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7499 if (GET_MODE (loc) != GET_MODE (in))
7500 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7502 gen_reload (loc, in, opnum, type);
7503 gen_reload (out, loc, opnum, type);
7507 /* If IN is a simple operand, use gen_move_insn. */
7508 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7509 emit_insn (gen_move_insn (out, in));
7511 #ifdef HAVE_reload_load_address
7512 else if (HAVE_reload_load_address)
7513 emit_insn (gen_reload_load_address (out, in));
7516 /* Otherwise, just write (set OUT IN) and hope for the best. */
7518 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7520 /* Return the first insn emitted.
7521 We can not just return get_last_insn, because there may have
7522 been multiple instructions emitted. Also note that gen_move_insn may
7523 emit more than one insn itself, so we can not assume that there is one
7524 insn emitted per emit_insn_before call. */
7526 return last ? NEXT_INSN (last) : get_insns ();
7529 /* Delete a previously made output-reload
7530 whose result we now believe is not needed.
7531 First we double-check.
7533 INSN is the insn now being processed.
7534 LAST_RELOAD_REG is the hard register number for which we want to delete
7535 the last output reload.
7536 J is the reload-number that originally used REG. The caller has made
7537 certain that reload J doesn't use REG any longer for input. */
7540 delete_output_reload (insn, j, last_reload_reg)
7543 int last_reload_reg;
7545 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7546 rtx reg = spill_reg_stored_to[last_reload_reg];
7549 int n_inherited = 0;
7553 /* Get the raw pseudo-register referred to. */
7555 while (GET_CODE (reg) == SUBREG)
7556 reg = SUBREG_REG (reg);
7557 substed = reg_equiv_memory_loc[REGNO (reg)];
7559 /* This is unsafe if the operand occurs more often in the current
7560 insn than it is inherited. */
7561 for (k = n_reloads - 1; k >= 0; k--)
7563 rtx reg2 = rld[k].in;
7566 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7567 reg2 = rld[k].in_reg;
7569 if (rld[k].out && ! rld[k].out_reg)
7570 reg2 = XEXP (rld[k].in_reg, 0);
7572 while (GET_CODE (reg2) == SUBREG)
7573 reg2 = SUBREG_REG (reg2);
7574 if (rtx_equal_p (reg2, reg))
7576 if (reload_inherited[k] || reload_override_in[k] || k == j)
7579 reg2 = rld[k].out_reg;
7582 while (GET_CODE (reg2) == SUBREG)
7583 reg2 = XEXP (reg2, 0);
7584 if (rtx_equal_p (reg2, reg))
7591 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7593 n_occurrences += count_occurrences (PATTERN (insn),
7594 eliminate_regs (substed, 0,
7596 if (n_occurrences > n_inherited)
7599 /* If the pseudo-reg we are reloading is no longer referenced
7600 anywhere between the store into it and here,
7601 and no jumps or labels intervene, then the value can get
7602 here through the reload reg alone.
7603 Otherwise, give up--return. */
7604 for (i1 = NEXT_INSN (output_reload_insn);
7605 i1 != insn; i1 = NEXT_INSN (i1))
7607 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7609 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7610 && reg_mentioned_p (reg, PATTERN (i1)))
7612 /* If this is USE in front of INSN, we only have to check that
7613 there are no more references than accounted for by inheritance. */
7614 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7616 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7617 i1 = NEXT_INSN (i1);
7619 if (n_occurrences <= n_inherited && i1 == insn)
7625 /* The caller has already checked that REG dies or is set in INSN.
7626 It has also checked that we are optimizing, and thus some inaccurancies
7627 in the debugging information are acceptable.
7628 So we could just delete output_reload_insn.
7629 But in some cases we can improve the debugging information without
7630 sacrificing optimization - maybe even improving the code:
7631 See if the pseudo reg has been completely replaced
7632 with reload regs. If so, delete the store insn
7633 and forget we had a stack slot for the pseudo. */
7634 if (rld[j].out != rld[j].in
7635 && REG_N_DEATHS (REGNO (reg)) == 1
7636 && REG_N_SETS (REGNO (reg)) == 1
7637 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7638 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7642 /* We know that it was used only between here
7643 and the beginning of the current basic block.
7644 (We also know that the last use before INSN was
7645 the output reload we are thinking of deleting, but never mind that.)
7646 Search that range; see if any ref remains. */
7647 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7649 rtx set = single_set (i2);
7651 /* Uses which just store in the pseudo don't count,
7652 since if they are the only uses, they are dead. */
7653 if (set != 0 && SET_DEST (set) == reg)
7655 if (GET_CODE (i2) == CODE_LABEL
7656 || GET_CODE (i2) == JUMP_INSN)
7658 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7659 && reg_mentioned_p (reg, PATTERN (i2)))
7661 /* Some other ref remains; just delete the output reload we
7663 delete_address_reloads (output_reload_insn, insn);
7664 PUT_CODE (output_reload_insn, NOTE);
7665 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7666 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7671 /* Delete the now-dead stores into this pseudo. */
7672 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7674 rtx set = single_set (i2);
7676 if (set != 0 && SET_DEST (set) == reg)
7678 delete_address_reloads (i2, insn);
7679 /* This might be a basic block head,
7680 thus don't use delete_insn. */
7681 PUT_CODE (i2, NOTE);
7682 NOTE_SOURCE_FILE (i2) = 0;
7683 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7685 if (GET_CODE (i2) == CODE_LABEL
7686 || GET_CODE (i2) == JUMP_INSN)
7690 /* For the debugging info,
7691 say the pseudo lives in this reload reg. */
7692 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7693 alter_reg (REGNO (reg), -1);
7695 delete_address_reloads (output_reload_insn, insn);
7696 PUT_CODE (output_reload_insn, NOTE);
7697 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7698 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7702 /* We are going to delete DEAD_INSN. Recursively delete loads of
7703 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7704 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7706 delete_address_reloads (dead_insn, current_insn)
7707 rtx dead_insn, current_insn;
7709 rtx set = single_set (dead_insn);
7710 rtx set2, dst, prev, next;
7713 rtx dst = SET_DEST (set);
7714 if (GET_CODE (dst) == MEM)
7715 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7717 /* If we deleted the store from a reloaded post_{in,de}c expression,
7718 we can delete the matching adds. */
7719 prev = PREV_INSN (dead_insn);
7720 next = NEXT_INSN (dead_insn);
7721 if (! prev || ! next)
7723 set = single_set (next);
7724 set2 = single_set (prev);
7726 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7727 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7728 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7730 dst = SET_DEST (set);
7731 if (! rtx_equal_p (dst, SET_DEST (set2))
7732 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7733 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7734 || (INTVAL (XEXP (SET_SRC (set), 1))
7735 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7741 /* Subfunction of delete_address_reloads: process registers found in X. */
7743 delete_address_reloads_1 (dead_insn, x, current_insn)
7744 rtx dead_insn, x, current_insn;
7746 rtx prev, set, dst, i2;
7748 enum rtx_code code = GET_CODE (x);
7752 const char *fmt = GET_RTX_FORMAT (code);
7753 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7756 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7757 else if (fmt[i] == 'E')
7759 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7760 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7767 if (spill_reg_order[REGNO (x)] < 0)
7770 /* Scan backwards for the insn that sets x. This might be a way back due
7772 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7774 code = GET_CODE (prev);
7775 if (code == CODE_LABEL || code == JUMP_INSN)
7777 if (GET_RTX_CLASS (code) != 'i')
7779 if (reg_set_p (x, PATTERN (prev)))
7781 if (reg_referenced_p (x, PATTERN (prev)))
7784 if (! prev || INSN_UID (prev) < reload_first_uid)
7786 /* Check that PREV only sets the reload register. */
7787 set = single_set (prev);
7790 dst = SET_DEST (set);
7791 if (GET_CODE (dst) != REG
7792 || ! rtx_equal_p (dst, x))
7794 if (! reg_set_p (dst, PATTERN (dead_insn)))
7796 /* Check if DST was used in a later insn -
7797 it might have been inherited. */
7798 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7800 if (GET_CODE (i2) == CODE_LABEL)
7804 if (reg_referenced_p (dst, PATTERN (i2)))
7806 /* If there is a reference to the register in the current insn,
7807 it might be loaded in a non-inherited reload. If no other
7808 reload uses it, that means the register is set before
7810 if (i2 == current_insn)
7812 for (j = n_reloads - 1; j >= 0; j--)
7813 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7814 || reload_override_in[j] == dst)
7816 for (j = n_reloads - 1; j >= 0; j--)
7817 if (rld[j].in && rld[j].reg_rtx == dst)
7824 if (GET_CODE (i2) == JUMP_INSN)
7826 /* If DST is still live at CURRENT_INSN, check if it is used for
7827 any reload. Note that even if CURRENT_INSN sets DST, we still
7828 have to check the reloads. */
7829 if (i2 == current_insn)
7831 for (j = n_reloads - 1; j >= 0; j--)
7832 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7833 || reload_override_in[j] == dst)
7835 /* ??? We can't finish the loop here, because dst might be
7836 allocated to a pseudo in this block if no reload in this
7837 block needs any of the clsses containing DST - see
7838 spill_hard_reg. There is no easy way to tell this, so we
7839 have to scan till the end of the basic block. */
7841 if (reg_set_p (dst, PATTERN (i2)))
7845 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7846 reg_reloaded_contents[REGNO (dst)] = -1;
7847 /* Can't use delete_insn here because PREV might be a basic block head. */
7848 PUT_CODE (prev, NOTE);
7849 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7850 NOTE_SOURCE_FILE (prev) = 0;
7853 /* Output reload-insns to reload VALUE into RELOADREG.
7854 VALUE is an autoincrement or autodecrement RTX whose operand
7855 is a register or memory location;
7856 so reloading involves incrementing that location.
7857 IN is either identical to VALUE, or some cheaper place to reload from.
7859 INC_AMOUNT is the number to increment or decrement by (always positive).
7860 This cannot be deduced from VALUE.
7862 Return the instruction that stores into RELOADREG. */
7865 inc_for_reload (reloadreg, in, value, inc_amount)
7870 /* REG or MEM to be copied and incremented. */
7871 rtx incloc = XEXP (value, 0);
7872 /* Nonzero if increment after copying. */
7873 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7879 rtx real_in = in == value ? XEXP (in, 0) : in;
7881 /* No hard register is equivalent to this register after
7882 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7883 we could inc/dec that register as well (maybe even using it for
7884 the source), but I'm not sure it's worth worrying about. */
7885 if (GET_CODE (incloc) == REG)
7886 reg_last_reload_reg[REGNO (incloc)] = 0;
7888 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7889 inc_amount = -inc_amount;
7891 inc = GEN_INT (inc_amount);
7893 /* If this is post-increment, first copy the location to the reload reg. */
7894 if (post && real_in != reloadreg)
7895 emit_insn (gen_move_insn (reloadreg, real_in));
7899 /* See if we can directly increment INCLOC. Use a method similar to
7900 that in gen_reload. */
7902 last = get_last_insn ();
7903 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7904 gen_rtx_PLUS (GET_MODE (incloc),
7907 code = recog_memoized (add_insn);
7910 extract_insn (add_insn);
7911 if (constrain_operands (1))
7913 /* If this is a pre-increment and we have incremented the value
7914 where it lives, copy the incremented value to RELOADREG to
7915 be used as an address. */
7918 emit_insn (gen_move_insn (reloadreg, incloc));
7923 delete_insns_since (last);
7926 /* If couldn't do the increment directly, must increment in RELOADREG.
7927 The way we do this depends on whether this is pre- or post-increment.
7928 For pre-increment, copy INCLOC to the reload register, increment it
7929 there, then save back. */
7933 if (in != reloadreg)
7934 emit_insn (gen_move_insn (reloadreg, real_in));
7935 emit_insn (gen_add2_insn (reloadreg, inc));
7936 store = emit_insn (gen_move_insn (incloc, reloadreg));
7941 Because this might be a jump insn or a compare, and because RELOADREG
7942 may not be available after the insn in an input reload, we must do
7943 the incrementation before the insn being reloaded for.
7945 We have already copied IN to RELOADREG. Increment the copy in
7946 RELOADREG, save that back, then decrement RELOADREG so it has
7947 the original value. */
7949 emit_insn (gen_add2_insn (reloadreg, inc));
7950 store = emit_insn (gen_move_insn (incloc, reloadreg));
7951 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7957 /* Return 1 if we are certain that the constraint-string STRING allows
7958 the hard register REG. Return 0 if we can't be sure of this. */
7961 constraint_accepts_reg_p (string, reg)
7966 int regno = true_regnum (reg);
7969 /* Initialize for first alternative. */
7971 /* Check that each alternative contains `g' or `r'. */
7973 switch (c = *string++)
7976 /* If an alternative lacks `g' or `r', we lose. */
7979 /* If an alternative lacks `g' or `r', we lose. */
7982 /* Initialize for next alternative. */
7987 /* Any general reg wins for this alternative. */
7988 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7992 /* Any reg in specified class wins for this alternative. */
7994 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7996 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8002 /* INSN is a no-op; delete it.
8003 If this sets the return value of the function, we must keep a USE around,
8004 in case this is in a different basic block than the final USE. Otherwise,
8005 we could loose important register lifeness information on
8006 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8007 spills: subsequent passes assume that spill registers are dead at the end
8009 VALUE must be the return value in such a case, NULL otherwise. */
8011 reload_cse_delete_noop_set (insn, value)
8016 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8017 INSN_CODE (insn) = -1;
8018 REG_NOTES (insn) = NULL_RTX;
8022 PUT_CODE (insn, NOTE);
8023 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8024 NOTE_SOURCE_FILE (insn) = 0;
8028 /* See whether a single set SET is a noop. */
8030 reload_cse_noop_set_p (set)
8033 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8036 /* Try to simplify INSN. */
8038 reload_cse_simplify (insn)
8041 rtx body = PATTERN (insn);
8043 if (GET_CODE (body) == SET)
8047 /* Simplify even if we may think it is a no-op.
8048 We may think a memory load of a value smaller than WORD_SIZE
8049 is redundant because we haven't taken into account possible
8050 implicit extension. reload_cse_simplify_set() will bring
8051 this out, so it's safer to simplify before we delete. */
8052 count += reload_cse_simplify_set (body, insn);
8054 if (!count && reload_cse_noop_set_p (body))
8056 rtx value = SET_DEST (body);
8057 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8059 reload_cse_delete_noop_set (insn, value);
8064 apply_change_group ();
8066 reload_cse_simplify_operands (insn);
8068 else if (GET_CODE (body) == PARALLEL)
8072 rtx value = NULL_RTX;
8074 /* If every action in a PARALLEL is a noop, we can delete
8075 the entire PARALLEL. */
8076 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8078 rtx part = XVECEXP (body, 0, i);
8079 if (GET_CODE (part) == SET)
8081 if (! reload_cse_noop_set_p (part))
8083 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8087 value = SET_DEST (part);
8090 else if (GET_CODE (part) != CLOBBER)
8096 reload_cse_delete_noop_set (insn, value);
8097 /* We're done with this insn. */
8101 /* It's not a no-op, but we can try to simplify it. */
8102 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8103 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8104 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8107 apply_change_group ();
8109 reload_cse_simplify_operands (insn);
8113 /* Do a very simple CSE pass over the hard registers.
8115 This function detects no-op moves where we happened to assign two
8116 different pseudo-registers to the same hard register, and then
8117 copied one to the other. Reload will generate a useless
8118 instruction copying a register to itself.
8120 This function also detects cases where we load a value from memory
8121 into two different registers, and (if memory is more expensive than
8122 registers) changes it to simply copy the first register into the
8125 Another optimization is performed that scans the operands of each
8126 instruction to see whether the value is already available in a
8127 hard register. It then replaces the operand with the hard register
8128 if possible, much like an optional reload would. */
8131 reload_cse_regs_1 (first)
8137 init_alias_analysis ();
8139 for (insn = first; insn; insn = NEXT_INSN (insn))
8142 reload_cse_simplify (insn);
8144 cselib_process_insn (insn);
8148 end_alias_analysis ();
8152 /* Call cse / combine like post-reload optimization phases.
8153 FIRST is the first instruction. */
8155 reload_cse_regs (first)
8158 reload_cse_regs_1 (first);
8160 reload_cse_move2add (first);
8161 if (flag_expensive_optimizations)
8162 reload_cse_regs_1 (first);
8165 /* Try to simplify a single SET instruction. SET is the set pattern.
8166 INSN is the instruction it came from.
8167 This function only handles one case: if we set a register to a value
8168 which is not a register, we try to find that value in some other register
8169 and change the set into a register copy. */
8172 reload_cse_simplify_set (set, insn)
8179 enum reg_class dclass;
8182 struct elt_loc_list *l;
8183 #ifdef LOAD_EXTEND_OP
8184 enum rtx_code extend_op = NIL;
8187 dreg = true_regnum (SET_DEST (set));
8191 src = SET_SRC (set);
8192 if (side_effects_p (src) || true_regnum (src) >= 0)
8195 dclass = REGNO_REG_CLASS (dreg);
8197 #ifdef LOAD_EXTEND_OP
8198 /* When replacing a memory with a register, we need to honor assumptions
8199 that combine made wrt the contents of sign bits. We'll do this by
8200 generating an extend instruction instead of a reg->reg copy. Thus
8201 the destination must be a register that we can widen. */
8202 if (GET_CODE (src) == MEM
8203 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8204 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8205 && GET_CODE (SET_DEST (set)) != REG)
8209 /* If memory loads are cheaper than register copies, don't change them. */
8210 if (GET_CODE (src) == MEM)
8211 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8212 else if (CONSTANT_P (src))
8213 old_cost = rtx_cost (src, SET);
8214 else if (GET_CODE (src) == REG)
8215 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8216 REGNO_REG_CLASS (REGNO (src)), dclass);
8219 old_cost = rtx_cost (src, SET);
8221 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8224 for (l = val->locs; l; l = l->next)
8226 rtx this_rtx = l->loc;
8229 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8231 #ifdef LOAD_EXTEND_OP
8232 if (extend_op != NIL)
8234 HOST_WIDE_INT this_val;
8236 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8237 constants, such as SYMBOL_REF, cannot be extended. */
8238 if (GET_CODE (this_rtx) != CONST_INT)
8241 this_val = INTVAL (this_rtx);
8245 this_val &= GET_MODE_MASK (GET_MODE (src));
8248 /* ??? In theory we're already extended. */
8249 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8254 this_rtx = GEN_INT (this_val);
8257 this_cost = rtx_cost (this_rtx, SET);
8259 else if (GET_CODE (this_rtx) == REG)
8261 #ifdef LOAD_EXTEND_OP
8262 if (extend_op != NIL)
8264 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8265 this_cost = rtx_cost (this_rtx, SET);
8269 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8270 REGNO_REG_CLASS (REGNO (this_rtx)),
8276 /* If equal costs, prefer registers over anything else. That
8277 tends to lead to smaller instructions on some machines. */
8278 if (this_cost < old_cost
8279 || (this_cost == old_cost
8280 && GET_CODE (this_rtx) == REG
8281 && GET_CODE (SET_SRC (set)) != REG))
8283 #ifdef LOAD_EXTEND_OP
8284 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8285 && extend_op != NIL)
8287 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8288 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8289 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8293 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8294 old_cost = this_cost, did_change = 1;
8301 /* Try to replace operands in INSN with equivalent values that are already
8302 in registers. This can be viewed as optional reloading.
8304 For each non-register operand in the insn, see if any hard regs are
8305 known to be equivalent to that operand. Record the alternatives which
8306 can accept these hard registers. Among all alternatives, select the
8307 ones which are better or equal to the one currently matching, where
8308 "better" is in terms of '?' and '!' constraints. Among the remaining
8309 alternatives, select the one which replaces most operands with
8313 reload_cse_simplify_operands (insn)
8318 /* For each operand, all registers that are equivalent to it. */
8319 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8321 const char *constraints[MAX_RECOG_OPERANDS];
8323 /* Vector recording how bad an alternative is. */
8324 int *alternative_reject;
8325 /* Vector recording how many registers can be introduced by choosing
8326 this alternative. */
8327 int *alternative_nregs;
8328 /* Array of vectors recording, for each operand and each alternative,
8329 which hard register to substitute, or -1 if the operand should be
8331 int *op_alt_regno[MAX_RECOG_OPERANDS];
8332 /* Array of alternatives, sorted in order of decreasing desirability. */
8333 int *alternative_order;
8334 rtx reg = gen_rtx_REG (VOIDmode, -1);
8336 extract_insn (insn);
8338 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8341 /* Figure out which alternative currently matches. */
8342 if (! constrain_operands (1))
8343 fatal_insn_not_found (insn);
8345 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8346 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8347 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8348 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8349 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8351 /* For each operand, find out which regs are equivalent. */
8352 for (i = 0; i < recog_data.n_operands; i++)
8355 struct elt_loc_list *l;
8357 CLEAR_HARD_REG_SET (equiv_regs[i]);
8359 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8360 right, so avoid the problem here. Likewise if we have a constant
8361 and the insn pattern doesn't tell us the mode we need. */
8362 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8363 || (CONSTANT_P (recog_data.operand[i])
8364 && recog_data.operand_mode[i] == VOIDmode))
8367 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8371 for (l = v->locs; l; l = l->next)
8372 if (GET_CODE (l->loc) == REG)
8373 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8376 for (i = 0; i < recog_data.n_operands; i++)
8378 enum machine_mode mode;
8382 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8383 for (j = 0; j < recog_data.n_alternatives; j++)
8384 op_alt_regno[i][j] = -1;
8386 p = constraints[i] = recog_data.constraints[i];
8387 mode = recog_data.operand_mode[i];
8389 /* Add the reject values for each alternative given by the constraints
8390 for this operand. */
8398 alternative_reject[j] += 3;
8400 alternative_reject[j] += 300;
8403 /* We won't change operands which are already registers. We
8404 also don't want to modify output operands. */
8405 regno = true_regnum (recog_data.operand[i]);
8407 || constraints[i][0] == '='
8408 || constraints[i][0] == '+')
8411 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8413 int class = (int) NO_REGS;
8415 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8418 REGNO (reg) = regno;
8419 PUT_MODE (reg, mode);
8421 /* We found a register equal to this operand. Now look for all
8422 alternatives that can accept this register and have not been
8423 assigned a register they can use yet. */
8432 case '=': case '+': case '?':
8433 case '#': case '&': case '!':
8435 case '0': case '1': case '2': case '3': case '4':
8436 case '5': case '6': case '7': case '8': case '9':
8437 case 'm': case '<': case '>': case 'V': case 'o':
8438 case 'E': case 'F': case 'G': case 'H':
8439 case 's': case 'i': case 'n':
8440 case 'I': case 'J': case 'K': case 'L':
8441 case 'M': case 'N': case 'O': case 'P':
8443 /* These don't say anything we care about. */
8447 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8452 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8455 case ',': case '\0':
8456 /* See if REGNO fits this alternative, and set it up as the
8457 replacement register if we don't have one for this
8458 alternative yet and the operand being replaced is not
8459 a cheap CONST_INT. */
8460 if (op_alt_regno[i][j] == -1
8461 && reg_fits_class_p (reg, class, 0, mode)
8462 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8463 || (rtx_cost (recog_data.operand[i], SET)
8464 > rtx_cost (reg, SET))))
8466 alternative_nregs[j]++;
8467 op_alt_regno[i][j] = regno;
8479 /* Record all alternatives which are better or equal to the currently
8480 matching one in the alternative_order array. */
8481 for (i = j = 0; i < recog_data.n_alternatives; i++)
8482 if (alternative_reject[i] <= alternative_reject[which_alternative])
8483 alternative_order[j++] = i;
8484 recog_data.n_alternatives = j;
8486 /* Sort it. Given a small number of alternatives, a dumb algorithm
8487 won't hurt too much. */
8488 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8491 int best_reject = alternative_reject[alternative_order[i]];
8492 int best_nregs = alternative_nregs[alternative_order[i]];
8495 for (j = i + 1; j < recog_data.n_alternatives; j++)
8497 int this_reject = alternative_reject[alternative_order[j]];
8498 int this_nregs = alternative_nregs[alternative_order[j]];
8500 if (this_reject < best_reject
8501 || (this_reject == best_reject && this_nregs < best_nregs))
8504 best_reject = this_reject;
8505 best_nregs = this_nregs;
8509 tmp = alternative_order[best];
8510 alternative_order[best] = alternative_order[i];
8511 alternative_order[i] = tmp;
8514 /* Substitute the operands as determined by op_alt_regno for the best
8516 j = alternative_order[0];
8518 for (i = 0; i < recog_data.n_operands; i++)
8520 enum machine_mode mode = recog_data.operand_mode[i];
8521 if (op_alt_regno[i][j] == -1)
8524 validate_change (insn, recog_data.operand_loc[i],
8525 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8528 for (i = recog_data.n_dups - 1; i >= 0; i--)
8530 int op = recog_data.dup_num[i];
8531 enum machine_mode mode = recog_data.operand_mode[op];
8533 if (op_alt_regno[op][j] == -1)
8536 validate_change (insn, recog_data.dup_loc[i],
8537 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8540 return apply_change_group ();
8543 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8545 This code might also be useful when reload gave up on reg+reg addresssing
8546 because of clashes between the return register and INDEX_REG_CLASS. */
8548 /* The maximum number of uses of a register we can keep track of to
8549 replace them with reg+reg addressing. */
8550 #define RELOAD_COMBINE_MAX_USES 6
8552 /* INSN is the insn where a register has ben used, and USEP points to the
8553 location of the register within the rtl. */
8554 struct reg_use { rtx insn, *usep; };
8556 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8557 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8558 indicates where it becomes live again.
8559 Otherwise, USE_INDEX is the index of the last encountered use of the
8560 register (which is first among these we have seen since we scan backwards),
8561 OFFSET contains the constant offset that is added to the register in
8562 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8563 last, of these uses.
8564 STORE_RUID is always meaningful if we only want to use a value in a
8565 register in a different place: it denotes the next insn in the insn
8566 stream (i.e. the last ecountered) that sets or clobbers the register. */
8569 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8574 } reg_state[FIRST_PSEUDO_REGISTER];
8576 /* Reverse linear uid. This is increased in reload_combine while scanning
8577 the instructions from last to first. It is used to set last_label_ruid
8578 and the store_ruid / use_ruid fields in reg_state. */
8579 static int reload_combine_ruid;
8581 #define LABEL_LIVE(LABEL) \
8582 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8588 int first_index_reg = -1;
8589 int last_index_reg = 0;
8592 int last_label_ruid;
8593 int min_labelno, n_labels;
8594 HARD_REG_SET ever_live_at_start, *label_live;
8596 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8597 reload has already used it where appropriate, so there is no use in
8598 trying to generate it now. */
8599 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8602 /* To avoid wasting too much time later searching for an index register,
8603 determine the minimum and maximum index register numbers. */
8604 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8605 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8607 if (first_index_reg == -1)
8608 first_index_reg = r;
8613 /* If no index register is available, we can quit now. */
8614 if (first_index_reg == -1)
8617 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8618 information is a bit fuzzy immediately after reload, but it's
8619 still good enough to determine which registers are live at a jump
8621 min_labelno = get_first_label_num ();
8622 n_labels = max_label_num () - min_labelno;
8623 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8624 CLEAR_HARD_REG_SET (ever_live_at_start);
8626 for (i = n_basic_blocks - 1; i >= 0; i--)
8628 insn = BLOCK_HEAD (i);
8629 if (GET_CODE (insn) == CODE_LABEL)
8633 REG_SET_TO_HARD_REG_SET (live,
8634 BASIC_BLOCK (i)->global_live_at_start);
8635 compute_use_by_pseudos (&live,
8636 BASIC_BLOCK (i)->global_live_at_start);
8637 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8638 IOR_HARD_REG_SET (ever_live_at_start, live);
8642 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8643 last_label_ruid = reload_combine_ruid = 0;
8644 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8646 reg_state[r].store_ruid = reload_combine_ruid;
8648 reg_state[r].use_index = -1;
8650 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8653 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8657 /* We cannot do our optimization across labels. Invalidating all the use
8658 information we have would be costly, so we just note where the label
8659 is and then later disable any optimization that would cross it. */
8660 if (GET_CODE (insn) == CODE_LABEL)
8661 last_label_ruid = reload_combine_ruid;
8662 else if (GET_CODE (insn) == BARRIER)
8663 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8664 if (! fixed_regs[r])
8665 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8667 if (! INSN_P (insn))
8670 reload_combine_ruid++;
8672 /* Look for (set (REGX) (CONST_INT))
8673 (set (REGX) (PLUS (REGX) (REGY)))
8675 ... (MEM (REGX)) ...
8677 (set (REGZ) (CONST_INT))
8679 ... (MEM (PLUS (REGZ) (REGY)))... .
8681 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8682 and that we know all uses of REGX before it dies. */
8683 set = single_set (insn);
8685 && GET_CODE (SET_DEST (set)) == REG
8686 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8687 GET_MODE (SET_DEST (set)))
8689 && GET_CODE (SET_SRC (set)) == PLUS
8690 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8691 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8692 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8694 rtx reg = SET_DEST (set);
8695 rtx plus = SET_SRC (set);
8696 rtx base = XEXP (plus, 1);
8697 rtx prev = prev_nonnote_insn (insn);
8698 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8699 unsigned int regno = REGNO (reg);
8700 rtx const_reg = NULL_RTX;
8701 rtx reg_sum = NULL_RTX;
8703 /* Now, we need an index register.
8704 We'll set index_reg to this index register, const_reg to the
8705 register that is to be loaded with the constant
8706 (denoted as REGZ in the substitution illustration above),
8707 and reg_sum to the register-register that we want to use to
8708 substitute uses of REG (typically in MEMs) with.
8709 First check REG and BASE for being index registers;
8710 we can use them even if they are not dead. */
8711 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8712 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8720 /* Otherwise, look for a free index register. Since we have
8721 checked above that neiter REG nor BASE are index registers,
8722 if we find anything at all, it will be different from these
8724 for (i = first_index_reg; i <= last_index_reg; i++)
8726 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8728 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8729 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8730 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8732 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8734 const_reg = index_reg;
8735 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8741 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8742 (REGY), i.e. BASE, is not clobbered before the last use we'll
8745 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8746 && rtx_equal_p (SET_DEST (prev_set), reg)
8747 && reg_state[regno].use_index >= 0
8748 && (reg_state[REGNO (base)].store_ruid
8749 <= reg_state[regno].use_ruid)
8754 /* Change destination register and, if necessary, the
8755 constant value in PREV, the constant loading instruction. */
8756 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8757 if (reg_state[regno].offset != const0_rtx)
8758 validate_change (prev,
8759 &SET_SRC (prev_set),
8760 GEN_INT (INTVAL (SET_SRC (prev_set))
8761 + INTVAL (reg_state[regno].offset)),
8764 /* Now for every use of REG that we have recorded, replace REG
8766 for (i = reg_state[regno].use_index;
8767 i < RELOAD_COMBINE_MAX_USES; i++)
8768 validate_change (reg_state[regno].reg_use[i].insn,
8769 reg_state[regno].reg_use[i].usep,
8772 if (apply_change_group ())
8776 /* Delete the reg-reg addition. */
8777 PUT_CODE (insn, NOTE);
8778 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8779 NOTE_SOURCE_FILE (insn) = 0;
8781 if (reg_state[regno].offset != const0_rtx)
8782 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8784 for (np = ®_NOTES (prev); *np;)
8786 if (REG_NOTE_KIND (*np) == REG_EQUAL
8787 || REG_NOTE_KIND (*np) == REG_EQUIV)
8788 *np = XEXP (*np, 1);
8790 np = &XEXP (*np, 1);
8793 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8794 reg_state[REGNO (const_reg)].store_ruid
8795 = reload_combine_ruid;
8801 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8803 if (GET_CODE (insn) == CALL_INSN)
8807 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8808 if (call_used_regs[r])
8810 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8811 reg_state[r].store_ruid = reload_combine_ruid;
8814 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8815 link = XEXP (link, 1))
8817 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8818 if (GET_CODE (usage_rtx) == REG)
8821 unsigned int start_reg = REGNO (usage_rtx);
8822 unsigned int num_regs =
8823 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8824 unsigned int end_reg = start_reg + num_regs - 1;
8825 for (i = start_reg; i <= end_reg; i++)
8826 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8828 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8829 reg_state[i].store_ruid = reload_combine_ruid;
8832 reg_state[i].use_index = -1;
8837 else if (GET_CODE (insn) == JUMP_INSN
8838 && GET_CODE (PATTERN (insn)) != RETURN)
8840 /* Non-spill registers might be used at the call destination in
8841 some unknown fashion, so we have to mark the unknown use. */
8844 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8845 && JUMP_LABEL (insn))
8846 live = &LABEL_LIVE (JUMP_LABEL (insn));
8848 live = &ever_live_at_start;
8850 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8851 if (TEST_HARD_REG_BIT (*live, i))
8852 reg_state[i].use_index = -1;
8855 reload_combine_note_use (&PATTERN (insn), insn);
8856 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8858 if (REG_NOTE_KIND (note) == REG_INC
8859 && GET_CODE (XEXP (note, 0)) == REG)
8861 int regno = REGNO (XEXP (note, 0));
8863 reg_state[regno].store_ruid = reload_combine_ruid;
8864 reg_state[regno].use_index = -1;
8872 /* Check if DST is a register or a subreg of a register; if it is,
8873 update reg_state[regno].store_ruid and reg_state[regno].use_index
8874 accordingly. Called via note_stores from reload_combine. */
8877 reload_combine_note_store (dst, set, data)
8879 void *data ATTRIBUTE_UNUSED;
8883 enum machine_mode mode = GET_MODE (dst);
8885 if (GET_CODE (dst) == SUBREG)
8887 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8888 GET_MODE (SUBREG_REG (dst)),
8891 dst = SUBREG_REG (dst);
8893 if (GET_CODE (dst) != REG)
8895 regno += REGNO (dst);
8897 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8898 careful with registers / register parts that are not full words.
8900 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8901 if (GET_CODE (set) != SET
8902 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8903 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8904 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8906 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8908 reg_state[i].use_index = -1;
8909 reg_state[i].store_ruid = reload_combine_ruid;
8914 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8916 reg_state[i].store_ruid = reload_combine_ruid;
8917 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8922 /* XP points to a piece of rtl that has to be checked for any uses of
8924 *XP is the pattern of INSN, or a part of it.
8925 Called from reload_combine, and recursively by itself. */
8927 reload_combine_note_use (xp, insn)
8931 enum rtx_code code = x->code;
8934 rtx offset = const0_rtx; /* For the REG case below. */
8939 if (GET_CODE (SET_DEST (x)) == REG)
8941 reload_combine_note_use (&SET_SRC (x), insn);
8947 /* If this is the USE of a return value, we can't change it. */
8948 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8950 /* Mark the return register as used in an unknown fashion. */
8951 rtx reg = XEXP (x, 0);
8952 int regno = REGNO (reg);
8953 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8955 while (--nregs >= 0)
8956 reg_state[regno + nregs].use_index = -1;
8962 if (GET_CODE (SET_DEST (x)) == REG)
8967 /* We are interested in (plus (reg) (const_int)) . */
8968 if (GET_CODE (XEXP (x, 0)) != REG
8969 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8971 offset = XEXP (x, 1);
8976 int regno = REGNO (x);
8980 /* Some spurious USEs of pseudo registers might remain.
8981 Just ignore them. */
8982 if (regno >= FIRST_PSEUDO_REGISTER)
8985 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8987 /* We can't substitute into multi-hard-reg uses. */
8990 while (--nregs >= 0)
8991 reg_state[regno + nregs].use_index = -1;
8995 /* If this register is already used in some unknown fashion, we
8997 If we decrement the index from zero to -1, we can't store more
8998 uses, so this register becomes used in an unknown fashion. */
8999 use_index = --reg_state[regno].use_index;
9003 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9005 /* We have found another use for a register that is already
9006 used later. Check if the offsets match; if not, mark the
9007 register as used in an unknown fashion. */
9008 if (! rtx_equal_p (offset, reg_state[regno].offset))
9010 reg_state[regno].use_index = -1;
9016 /* This is the first use of this register we have seen since we
9017 marked it as dead. */
9018 reg_state[regno].offset = offset;
9019 reg_state[regno].use_ruid = reload_combine_ruid;
9021 reg_state[regno].reg_use[use_index].insn = insn;
9022 reg_state[regno].reg_use[use_index].usep = xp;
9030 /* Recursively process the components of X. */
9031 fmt = GET_RTX_FORMAT (code);
9032 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9035 reload_combine_note_use (&XEXP (x, i), insn);
9036 else if (fmt[i] == 'E')
9038 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9039 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9044 /* See if we can reduce the cost of a constant by replacing a move
9045 with an add. We track situations in which a register is set to a
9046 constant or to a register plus a constant. */
9047 /* We cannot do our optimization across labels. Invalidating all the
9048 information about register contents we have would be costly, so we
9049 use move2add_last_label_luid to note where the label is and then
9050 later disable any optimization that would cross it.
9051 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9052 reg_set_luid[n] is greater than last_label_luid[n] . */
9053 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9055 /* If reg_base_reg[n] is negative, register n has been set to
9056 reg_offset[n] in mode reg_mode[n] .
9057 If reg_base_reg[n] is non-negative, register n has been set to the
9058 sum of reg_offset[n] and the value of register reg_base_reg[n]
9059 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9060 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9061 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9062 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9064 /* move2add_luid is linearily increased while scanning the instructions
9065 from first to last. It is used to set reg_set_luid in
9066 reload_cse_move2add and move2add_note_store. */
9067 static int move2add_luid;
9069 /* move2add_last_label_luid is set whenever a label is found. Labels
9070 invalidate all previously collected reg_offset data. */
9071 static int move2add_last_label_luid;
9073 /* Generate a CONST_INT and force it in the range of MODE. */
9075 static HOST_WIDE_INT
9076 sext_for_mode (mode, value)
9077 enum machine_mode mode;
9078 HOST_WIDE_INT value;
9080 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9081 int width = GET_MODE_BITSIZE (mode);
9083 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9085 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9086 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9087 cval |= (HOST_WIDE_INT) -1 << width;
9092 /* ??? We don't know how zero / sign extension is handled, hence we
9093 can't go from a narrower to a wider mode. */
9094 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9095 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9096 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9097 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9098 GET_MODE_BITSIZE (INMODE))))
9101 reload_cse_move2add (first)
9107 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9108 reg_set_luid[i] = 0;
9110 move2add_last_label_luid = 0;
9112 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9116 if (GET_CODE (insn) == CODE_LABEL)
9118 move2add_last_label_luid = move2add_luid;
9119 /* We're going to increment move2add_luid twice after a
9120 label, so that we can use move2add_last_label_luid + 1 as
9121 the luid for constants. */
9125 if (! INSN_P (insn))
9127 pat = PATTERN (insn);
9128 /* For simplicity, we only perform this optimization on
9129 straightforward SETs. */
9130 if (GET_CODE (pat) == SET
9131 && GET_CODE (SET_DEST (pat)) == REG)
9133 rtx reg = SET_DEST (pat);
9134 int regno = REGNO (reg);
9135 rtx src = SET_SRC (pat);
9137 /* Check if we have valid information on the contents of this
9138 register in the mode of REG. */
9139 if (reg_set_luid[regno] > move2add_last_label_luid
9140 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9142 /* Try to transform (set (REGX) (CONST_INT A))
9144 (set (REGX) (CONST_INT B))
9146 (set (REGX) (CONST_INT A))
9148 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9150 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9153 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9155 - reg_offset[regno]));
9156 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9157 use (set (reg) (reg)) instead.
9158 We don't delete this insn, nor do we convert it into a
9159 note, to avoid losing register notes or the return
9160 value flag. jump2 already knowns how to get rid of
9162 if (new_src == const0_rtx)
9163 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9164 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9165 && have_add2_insn (reg, new_src))
9166 success = validate_change (insn, &PATTERN (insn),
9167 gen_add2_insn (reg, new_src), 0);
9168 reg_set_luid[regno] = move2add_luid;
9169 reg_mode[regno] = GET_MODE (reg);
9170 reg_offset[regno] = INTVAL (src);
9174 /* Try to transform (set (REGX) (REGY))
9175 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9178 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9181 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9183 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9184 else if (GET_CODE (src) == REG
9185 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9186 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9187 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9188 reg_mode[REGNO (src)]))
9190 rtx next = next_nonnote_insn (insn);
9193 set = single_set (next);
9195 && SET_DEST (set) == reg
9196 && GET_CODE (SET_SRC (set)) == PLUS
9197 && XEXP (SET_SRC (set), 0) == reg
9198 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9200 rtx src3 = XEXP (SET_SRC (set), 1);
9201 HOST_WIDE_INT added_offset = INTVAL (src3);
9202 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9203 HOST_WIDE_INT regno_offset = reg_offset[regno];
9204 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9210 if (new_src == const0_rtx)
9211 /* See above why we create (set (reg) (reg)) here. */
9213 = validate_change (next, &SET_SRC (set), reg, 0);
9214 else if ((rtx_cost (new_src, PLUS)
9215 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9216 && have_add2_insn (reg, new_src))
9218 = validate_change (next, &PATTERN (next),
9219 gen_add2_insn (reg, new_src), 0);
9222 /* INSN might be the first insn in a basic block
9223 if the preceding insn is a conditional jump
9224 or a possible-throwing call. */
9225 PUT_CODE (insn, NOTE);
9226 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9227 NOTE_SOURCE_FILE (insn) = 0;
9230 reg_mode[regno] = GET_MODE (reg);
9231 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9240 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9242 if (REG_NOTE_KIND (note) == REG_INC
9243 && GET_CODE (XEXP (note, 0)) == REG)
9245 /* Reset the information about this register. */
9246 int regno = REGNO (XEXP (note, 0));
9247 if (regno < FIRST_PSEUDO_REGISTER)
9248 reg_set_luid[regno] = 0;
9251 note_stores (PATTERN (insn), move2add_note_store, NULL);
9252 /* If this is a CALL_INSN, all call used registers are stored with
9254 if (GET_CODE (insn) == CALL_INSN)
9256 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9258 if (call_used_regs[i])
9259 /* Reset the information about this register. */
9260 reg_set_luid[i] = 0;
9266 /* SET is a SET or CLOBBER that sets DST.
9267 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9268 Called from reload_cse_move2add via note_stores. */
9271 move2add_note_store (dst, set, data)
9273 void *data ATTRIBUTE_UNUSED;
9275 unsigned int regno = 0;
9277 enum machine_mode mode = GET_MODE (dst);
9279 if (GET_CODE (dst) == SUBREG)
9281 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9282 GET_MODE (SUBREG_REG (dst)),
9285 dst = SUBREG_REG (dst);
9288 /* Some targets do argument pushes without adding REG_INC notes. */
9290 if (GET_CODE (dst) == MEM)
9292 dst = XEXP (dst, 0);
9293 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9294 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9295 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9298 if (GET_CODE (dst) != REG)
9301 regno += REGNO (dst);
9303 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9304 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9305 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9306 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9308 rtx src = SET_SRC (set);
9310 HOST_WIDE_INT offset;
9312 /* This may be different from mode, if SET_DEST (set) is a
9314 enum machine_mode dst_mode = GET_MODE (dst);
9316 switch (GET_CODE (src))
9319 if (GET_CODE (XEXP (src, 0)) == REG)
9321 base_reg = XEXP (src, 0);
9323 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9324 offset = INTVAL (XEXP (src, 1));
9325 else if (GET_CODE (XEXP (src, 1)) == REG
9326 && (reg_set_luid[REGNO (XEXP (src, 1))]
9327 > move2add_last_label_luid)
9328 && (MODES_OK_FOR_MOVE2ADD
9329 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9331 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9332 offset = reg_offset[REGNO (XEXP (src, 1))];
9333 /* Maybe the first register is known to be a
9335 else if (reg_set_luid[REGNO (base_reg)]
9336 > move2add_last_label_luid
9337 && (MODES_OK_FOR_MOVE2ADD
9338 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9339 && reg_base_reg[REGNO (base_reg)] < 0)
9341 offset = reg_offset[REGNO (base_reg)];
9342 base_reg = XEXP (src, 1);
9361 /* Start tracking the register as a constant. */
9362 reg_base_reg[regno] = -1;
9363 reg_offset[regno] = INTVAL (SET_SRC (set));
9364 /* We assign the same luid to all registers set to constants. */
9365 reg_set_luid[regno] = move2add_last_label_luid + 1;
9366 reg_mode[regno] = mode;
9371 /* Invalidate the contents of the register. */
9372 reg_set_luid[regno] = 0;
9376 base_regno = REGNO (base_reg);
9377 /* If information about the base register is not valid, set it
9378 up as a new base register, pretending its value is known
9379 starting from the current insn. */
9380 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9382 reg_base_reg[base_regno] = base_regno;
9383 reg_offset[base_regno] = 0;
9384 reg_set_luid[base_regno] = move2add_luid;
9385 reg_mode[base_regno] = mode;
9387 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9388 reg_mode[base_regno]))
9391 reg_mode[regno] = mode;
9393 /* Copy base information from our base register. */
9394 reg_set_luid[regno] = reg_set_luid[base_regno];
9395 reg_base_reg[regno] = reg_base_reg[base_regno];
9397 /* Compute the sum of the offsets or constants. */
9398 reg_offset[regno] = sext_for_mode (dst_mode,
9400 + reg_offset[base_regno]);
9404 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9406 for (i = regno; i < endregno; i++)
9407 /* Reset the information about this register. */
9408 reg_set_luid[i] = 0;
9414 add_auto_inc_notes (insn, x)
9418 enum rtx_code code = GET_CODE (x);
9422 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9425 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9429 /* Scan all the operand sub-expressions. */
9430 fmt = GET_RTX_FORMAT (code);
9431 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9434 add_auto_inc_notes (insn, XEXP (x, i));
9435 else if (fmt[i] == 'E')
9436 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9437 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9442 /* Copy EH notes from an insn to its reloads. */
9444 copy_eh_notes (insn, x)
9448 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9451 for (; x != 0; x = NEXT_INSN (x))
9453 if (may_trap_p (PATTERN (x)))
9455 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
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