1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int function_invariant_p (rtx);
410 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
411 static int allocate_reload_reg (struct insn_chain *, int, int);
412 static int conflicts_with_override (rtx);
413 static void failed_reload (rtx, int);
414 static int set_reload_reg (int, int);
415 static void choose_reload_regs_init (struct insn_chain *, rtx *);
416 static void choose_reload_regs (struct insn_chain *);
417 static void merge_assigned_reloads (rtx);
418 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
420 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
422 static void do_input_reload (struct insn_chain *, struct reload *, int);
423 static void do_output_reload (struct insn_chain *, struct reload *, int);
424 static bool inherit_piecemeal_p (int, int);
425 static void emit_reload_insns (struct insn_chain *);
426 static void delete_output_reload (rtx, int, int);
427 static void delete_address_reloads (rtx, rtx);
428 static void delete_address_reloads_1 (rtx, rtx, rtx);
429 static rtx inc_for_reload (rtx, rtx, rtx, int);
431 static void add_auto_inc_notes (rtx, rtx);
433 static void copy_eh_notes (rtx, rtx);
435 /* Initialize the reload pass once per compilation. */
442 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
443 Set spill_indirect_levels to the number of levels such addressing is
444 permitted, zero if it is not permitted at all. */
447 = gen_rtx_MEM (Pmode,
450 LAST_VIRTUAL_REGISTER + 1),
452 spill_indirect_levels = 0;
454 while (memory_address_p (QImode, tem))
456 spill_indirect_levels++;
457 tem = gen_rtx_MEM (Pmode, tem);
460 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
462 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
463 indirect_symref_ok = memory_address_p (QImode, tem);
465 /* See if reg+reg is a valid (and offsettable) address. */
467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
469 tem = gen_rtx_PLUS (Pmode,
470 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
471 gen_rtx_REG (Pmode, i));
473 /* This way, we make sure that reg+reg is an offsettable address. */
474 tem = plus_constant (tem, 4);
476 if (memory_address_p (QImode, tem))
478 double_reg_address_ok = 1;
483 /* Initialize obstack for our rtl allocation. */
484 gcc_obstack_init (&reload_obstack);
485 reload_startobj = obstack_alloc (&reload_obstack, 0);
487 INIT_REG_SET (&spilled_pseudos);
488 INIT_REG_SET (&pseudos_counted);
489 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
492 /* List of insn chains that are currently unused. */
493 static struct insn_chain *unused_insn_chains = 0;
495 /* Allocate an empty insn_chain structure. */
497 new_insn_chain (void)
499 struct insn_chain *c;
501 if (unused_insn_chains == 0)
503 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
504 INIT_REG_SET (&c->live_throughout);
505 INIT_REG_SET (&c->dead_or_set);
509 c = unused_insn_chains;
510 unused_insn_chains = c->next;
512 c->is_caller_save_insn = 0;
513 c->need_operand_change = 0;
519 /* Small utility function to set all regs in hard reg set TO which are
520 allocated to pseudos in regset FROM. */
523 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
526 reg_set_iterator rsi;
528 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
530 int r = reg_renumber[regno];
535 /* reload_combine uses the information from
536 BASIC_BLOCK->global_live_at_start, which might still
537 contain registers that have not actually been allocated
538 since they have an equivalence. */
539 gcc_assert (reload_completed);
543 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
545 SET_HARD_REG_BIT (*to, r + nregs);
550 /* Replace all pseudos found in LOC with their corresponding
554 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
567 unsigned int regno = REGNO (x);
569 if (regno < FIRST_PSEUDO_REGISTER)
572 x = eliminate_regs (x, mem_mode, usage);
576 replace_pseudos_in (loc, mem_mode, usage);
580 if (reg_equiv_constant[regno])
581 *loc = reg_equiv_constant[regno];
582 else if (reg_equiv_mem[regno])
583 *loc = reg_equiv_mem[regno];
584 else if (reg_equiv_address[regno])
585 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
588 gcc_assert (!REG_P (regno_reg_rtx[regno])
589 || REGNO (regno_reg_rtx[regno]) != regno);
590 *loc = regno_reg_rtx[regno];
595 else if (code == MEM)
597 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
601 /* Process each of our operands recursively. */
602 fmt = GET_RTX_FORMAT (code);
603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
605 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
606 else if (*fmt == 'E')
607 for (j = 0; j < XVECLEN (x, i); j++)
608 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
612 /* Global variables used by reload and its subroutines. */
614 /* Set during calculate_needs if an insn needs register elimination. */
615 static int something_needs_elimination;
616 /* Set during calculate_needs if an insn needs an operand changed. */
617 int something_needs_operands_changed;
619 /* Nonzero means we couldn't get enough spill regs. */
622 /* Main entry point for the reload pass.
624 FIRST is the first insn of the function being compiled.
626 GLOBAL nonzero means we were called from global_alloc
627 and should attempt to reallocate any pseudoregs that we
628 displace from hard regs we will use for reloads.
629 If GLOBAL is zero, we do not have enough information to do that,
630 so any pseudo reg that is spilled must go to the stack.
632 Return value is nonzero if reload failed
633 and we must not do any more for this function. */
636 reload (rtx first, int global)
640 struct elim_table *ep;
643 /* Make sure even insns with volatile mem refs are recognizable. */
648 reload_firstobj = obstack_alloc (&reload_obstack, 0);
650 /* Make sure that the last insn in the chain
651 is not something that needs reloading. */
652 emit_note (NOTE_INSN_DELETED);
654 /* Enable find_equiv_reg to distinguish insns made by reload. */
655 reload_first_uid = get_max_uid ();
657 #ifdef SECONDARY_MEMORY_NEEDED
658 /* Initialize the secondary memory table. */
659 clear_secondary_mem ();
662 /* We don't have a stack slot for any spill reg yet. */
663 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
664 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
666 /* Initialize the save area information for caller-save, in case some
670 /* Compute which hard registers are now in use
671 as homes for pseudo registers.
672 This is done here rather than (eg) in global_alloc
673 because this point is reached even if not optimizing. */
674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
677 /* A function that receives a nonlocal goto must save all call-saved
679 if (current_function_has_nonlocal_label)
680 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
681 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
682 regs_ever_live[i] = 1;
684 #ifdef NON_SAVING_SETJMP
685 /* A function that calls setjmp should save and restore all the
686 call-saved registers on a system where longjmp clobbers them. */
687 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i])
691 regs_ever_live[i] = 1;
695 /* Find all the pseudo registers that didn't get hard regs
696 but do have known equivalent constants or memory slots.
697 These include parameters (known equivalent to parameter slots)
698 and cse'd or loop-moved constant memory addresses.
700 Record constant equivalents in reg_equiv_constant
701 so they will be substituted by find_reloads.
702 Record memory equivalents in reg_mem_equiv so they can
703 be substituted eventually by altering the REG-rtx's. */
705 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
706 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
707 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
708 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
709 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
710 reg_old_renumber = xcalloc (max_regno, sizeof (short));
711 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
712 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
713 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
715 CLEAR_HARD_REG_SET (bad_spill_regs_global);
717 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
718 to. Also find all paradoxical subregs and find largest such for
721 num_eliminable_invariants = 0;
722 for (insn = first; insn; insn = NEXT_INSN (insn))
724 rtx set = single_set (insn);
726 /* We may introduce USEs that we want to remove at the end, so
727 we'll mark them with QImode. Make sure there are no
728 previously-marked insns left by say regmove. */
729 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
730 && GET_MODE (insn) != VOIDmode)
731 PUT_MODE (insn, VOIDmode);
733 if (set != 0 && REG_P (SET_DEST (set)))
735 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
737 && (! function_invariant_p (XEXP (note, 0))
739 /* A function invariant is often CONSTANT_P but may
740 include a register. We promise to only pass
741 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
742 || (CONSTANT_P (XEXP (note, 0))
743 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
745 rtx x = XEXP (note, 0);
746 i = REGNO (SET_DEST (set));
747 if (i > LAST_VIRTUAL_REGISTER)
749 /* It can happen that a REG_EQUIV note contains a MEM
750 that is not a legitimate memory operand. As later
751 stages of reload assume that all addresses found
752 in the reg_equiv_* arrays were originally legitimate,
753 we ignore such REG_EQUIV notes. */
754 if (memory_operand (x, VOIDmode))
756 /* Always unshare the equivalence, so we can
757 substitute into this insn without touching the
759 reg_equiv_memory_loc[i] = copy_rtx (x);
761 else if (function_invariant_p (x))
763 if (GET_CODE (x) == PLUS)
765 /* This is PLUS of frame pointer and a constant,
766 and might be shared. Unshare it. */
767 reg_equiv_constant[i] = copy_rtx (x);
768 num_eliminable_invariants++;
770 else if (x == frame_pointer_rtx
771 || x == arg_pointer_rtx)
773 reg_equiv_constant[i] = x;
774 num_eliminable_invariants++;
776 else if (LEGITIMATE_CONSTANT_P (x))
777 reg_equiv_constant[i] = x;
780 reg_equiv_memory_loc[i]
781 = force_const_mem (GET_MODE (SET_DEST (set)), x);
782 if (!reg_equiv_memory_loc[i])
789 /* If this register is being made equivalent to a MEM
790 and the MEM is not SET_SRC, the equivalencing insn
791 is one with the MEM as a SET_DEST and it occurs later.
792 So don't mark this insn now. */
794 || rtx_equal_p (SET_SRC (set), x))
796 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
801 /* If this insn is setting a MEM from a register equivalent to it,
802 this is the equivalencing insn. */
803 else if (set && MEM_P (SET_DEST (set))
804 && REG_P (SET_SRC (set))
805 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
806 && rtx_equal_p (SET_DEST (set),
807 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
808 reg_equiv_init[REGNO (SET_SRC (set))]
809 = gen_rtx_INSN_LIST (VOIDmode, insn,
810 reg_equiv_init[REGNO (SET_SRC (set))]);
813 scan_paradoxical_subregs (PATTERN (insn));
818 first_label_num = get_first_label_num ();
819 num_labels = max_label_num () - first_label_num;
821 /* Allocate the tables used to store offset information at labels. */
822 /* We used to use alloca here, but the size of what it would try to
823 allocate would occasionally cause it to exceed the stack limit and
824 cause a core dump. */
825 offsets_known_at = xmalloc (num_labels);
826 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
828 /* Alter each pseudo-reg rtx to contain its hard reg number.
829 Assign stack slots to the pseudos that lack hard regs or equivalents.
830 Do not touch virtual registers. */
832 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
835 /* If we have some registers we think can be eliminated, scan all insns to
836 see if there is an insn that sets one of these registers to something
837 other than itself plus a constant. If so, the register cannot be
838 eliminated. Doing this scan here eliminates an extra pass through the
839 main reload loop in the most common case where register elimination
841 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
843 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
845 maybe_fix_stack_asms ();
847 insns_need_reload = 0;
848 something_needs_elimination = 0;
850 /* Initialize to -1, which means take the first spill register. */
853 /* Spill any hard regs that we know we can't eliminate. */
854 CLEAR_HARD_REG_SET (used_spill_regs);
855 /* There can be multiple ways to eliminate a register;
856 they should be listed adjacently.
857 Elimination for any register fails only if all possible ways fail. */
858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
861 int can_eliminate = 0;
864 can_eliminate |= ep->can_eliminate;
867 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
869 spill_hard_reg (from, 1);
872 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
873 if (frame_pointer_needed)
874 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
876 finish_spills (global);
878 /* From now on, we may need to generate moves differently. We may also
879 allow modifications of insns which cause them to not be recognized.
880 Any such modifications will be cleaned up during reload itself. */
881 reload_in_progress = 1;
883 /* This loop scans the entire function each go-round
884 and repeats until one repetition spills no additional hard regs. */
887 int something_changed;
890 HOST_WIDE_INT starting_frame_size;
892 /* Round size of stack frame to stack_alignment_needed. This must be done
893 here because the stack size may be a part of the offset computation
894 for register elimination, and there might have been new stack slots
895 created in the last iteration of this loop. */
896 if (cfun->stack_alignment_needed)
897 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
899 starting_frame_size = get_frame_size ();
901 set_initial_elim_offsets ();
902 set_initial_label_offsets ();
904 /* For each pseudo register that has an equivalent location defined,
905 try to eliminate any eliminable registers (such as the frame pointer)
906 assuming initial offsets for the replacement register, which
909 If the resulting location is directly addressable, substitute
910 the MEM we just got directly for the old REG.
912 If it is not addressable but is a constant or the sum of a hard reg
913 and constant, it is probably not addressable because the constant is
914 out of range, in that case record the address; we will generate
915 hairy code to compute the address in a register each time it is
916 needed. Similarly if it is a hard register, but one that is not
917 valid as an address register.
919 If the location is not addressable, but does not have one of the
920 above forms, assign a stack slot. We have to do this to avoid the
921 potential of producing lots of reloads if, e.g., a location involves
922 a pseudo that didn't get a hard register and has an equivalent memory
923 location that also involves a pseudo that didn't get a hard register.
925 Perhaps at some point we will improve reload_when_needed handling
926 so this problem goes away. But that's very hairy. */
928 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
929 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
931 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
933 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
935 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
936 else if (CONSTANT_P (XEXP (x, 0))
937 || (REG_P (XEXP (x, 0))
938 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
939 || (GET_CODE (XEXP (x, 0)) == PLUS
940 && REG_P (XEXP (XEXP (x, 0), 0))
941 && (REGNO (XEXP (XEXP (x, 0), 0))
942 < FIRST_PSEUDO_REGISTER)
943 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
944 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
947 /* Make a new stack slot. Then indicate that something
948 changed so we go back and recompute offsets for
949 eliminable registers because the allocation of memory
950 below might change some offset. reg_equiv_{mem,address}
951 will be set up for this pseudo on the next pass around
953 reg_equiv_memory_loc[i] = 0;
954 reg_equiv_init[i] = 0;
959 if (caller_save_needed)
962 /* If we allocated another stack slot, redo elimination bookkeeping. */
963 if (starting_frame_size != get_frame_size ())
966 if (caller_save_needed)
968 save_call_clobbered_regs ();
969 /* That might have allocated new insn_chain structures. */
970 reload_firstobj = obstack_alloc (&reload_obstack, 0);
973 calculate_needs_all_insns (global);
975 CLEAR_REG_SET (&spilled_pseudos);
978 something_changed = 0;
980 /* If we allocated any new memory locations, make another pass
981 since it might have changed elimination offsets. */
982 if (starting_frame_size != get_frame_size ())
983 something_changed = 1;
986 HARD_REG_SET to_spill;
987 CLEAR_HARD_REG_SET (to_spill);
988 update_eliminables (&to_spill);
989 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
990 if (TEST_HARD_REG_BIT (to_spill, i))
992 spill_hard_reg (i, 1);
995 /* Regardless of the state of spills, if we previously had
996 a register that we thought we could eliminate, but now can
997 not eliminate, we must run another pass.
999 Consider pseudos which have an entry in reg_equiv_* which
1000 reference an eliminable register. We must make another pass
1001 to update reg_equiv_* so that we do not substitute in the
1002 old value from when we thought the elimination could be
1004 something_changed = 1;
1008 select_reload_regs ();
1012 if (insns_need_reload != 0 || did_spill)
1013 something_changed |= finish_spills (global);
1015 if (! something_changed)
1018 if (caller_save_needed)
1019 delete_caller_save_insns ();
1021 obstack_free (&reload_obstack, reload_firstobj);
1024 /* If global-alloc was run, notify it of any register eliminations we have
1027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1028 if (ep->can_eliminate)
1029 mark_elimination (ep->from, ep->to);
1031 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1032 If that insn didn't set the register (i.e., it copied the register to
1033 memory), just delete that insn instead of the equivalencing insn plus
1034 anything now dead. If we call delete_dead_insn on that insn, we may
1035 delete the insn that actually sets the register if the register dies
1036 there and that is incorrect. */
1038 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1040 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1043 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1045 rtx equiv_insn = XEXP (list, 0);
1047 /* If we already deleted the insn or if it may trap, we can't
1048 delete it. The latter case shouldn't happen, but can
1049 if an insn has a variable address, gets a REG_EH_REGION
1050 note added to it, and then gets converted into an load
1051 from a constant address. */
1052 if (NOTE_P (equiv_insn)
1053 || can_throw_internal (equiv_insn))
1055 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1056 delete_dead_insn (equiv_insn);
1058 SET_INSN_DELETED (equiv_insn);
1063 /* Use the reload registers where necessary
1064 by generating move instructions to move the must-be-register
1065 values into or out of the reload registers. */
1067 if (insns_need_reload != 0 || something_needs_elimination
1068 || something_needs_operands_changed)
1070 HOST_WIDE_INT old_frame_size = get_frame_size ();
1072 reload_as_needed (global);
1074 gcc_assert (old_frame_size == get_frame_size ());
1077 verify_initial_elim_offsets ();
1080 /* If we were able to eliminate the frame pointer, show that it is no
1081 longer live at the start of any basic block. If it ls live by
1082 virtue of being in a pseudo, that pseudo will be marked live
1083 and hence the frame pointer will be known to be live via that
1086 if (! frame_pointer_needed)
1088 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1089 HARD_FRAME_POINTER_REGNUM);
1091 /* Come here (with failure set nonzero) if we can't get enough spill regs
1092 and we decide not to abort about it. */
1095 CLEAR_REG_SET (&spilled_pseudos);
1096 reload_in_progress = 0;
1098 /* Now eliminate all pseudo regs by modifying them into
1099 their equivalent memory references.
1100 The REG-rtx's for the pseudos are modified in place,
1101 so all insns that used to refer to them now refer to memory.
1103 For a reg that has a reg_equiv_address, all those insns
1104 were changed by reloading so that no insns refer to it any longer;
1105 but the DECL_RTL of a variable decl may refer to it,
1106 and if so this causes the debugging info to mention the variable. */
1108 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1112 if (reg_equiv_mem[i])
1113 addr = XEXP (reg_equiv_mem[i], 0);
1115 if (reg_equiv_address[i])
1116 addr = reg_equiv_address[i];
1120 if (reg_renumber[i] < 0)
1122 rtx reg = regno_reg_rtx[i];
1124 REG_USERVAR_P (reg) = 0;
1125 PUT_CODE (reg, MEM);
1126 XEXP (reg, 0) = addr;
1127 if (reg_equiv_memory_loc[i])
1128 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1131 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1132 MEM_ATTRS (reg) = 0;
1135 else if (reg_equiv_mem[i])
1136 XEXP (reg_equiv_mem[i], 0) = addr;
1140 /* We must set reload_completed now since the cleanup_subreg_operands call
1141 below will re-recognize each insn and reload may have generated insns
1142 which are only valid during and after reload. */
1143 reload_completed = 1;
1145 /* Make a pass over all the insns and delete all USEs which we inserted
1146 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1147 notes. Delete all CLOBBER insns, except those that refer to the return
1148 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1149 from misarranging variable-array code, and simplify (subreg (reg))
1150 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1151 are no longer useful or accurate. Strip and regenerate REG_INC notes
1152 that may have been moved around. */
1154 for (insn = first; insn; insn = NEXT_INSN (insn))
1160 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1161 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1163 if ((GET_CODE (PATTERN (insn)) == USE
1164 /* We mark with QImode USEs introduced by reload itself. */
1165 && (GET_MODE (insn) == QImode
1166 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1167 || (GET_CODE (PATTERN (insn)) == CLOBBER
1168 && (!MEM_P (XEXP (PATTERN (insn), 0))
1169 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1170 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1171 && XEXP (XEXP (PATTERN (insn), 0), 0)
1172 != stack_pointer_rtx))
1173 && (!REG_P (XEXP (PATTERN (insn), 0))
1174 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1180 /* Some CLOBBERs may survive until here and still reference unassigned
1181 pseudos with const equivalent, which may in turn cause ICE in later
1182 passes if the reference remains in place. */
1183 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1184 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1185 VOIDmode, PATTERN (insn));
1187 pnote = ®_NOTES (insn);
1190 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1191 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1192 || REG_NOTE_KIND (*pnote) == REG_INC
1193 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1194 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1195 *pnote = XEXP (*pnote, 1);
1197 pnote = &XEXP (*pnote, 1);
1201 add_auto_inc_notes (insn, PATTERN (insn));
1204 /* And simplify (subreg (reg)) if it appears as an operand. */
1205 cleanup_subreg_operands (insn);
1208 /* If we are doing stack checking, give a warning if this function's
1209 frame size is larger than we expect. */
1210 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1212 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1213 static int verbose_warned = 0;
1215 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1216 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1217 size += UNITS_PER_WORD;
1219 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1221 warning ("frame size too large for reliable stack checking");
1222 if (! verbose_warned)
1224 warning ("try reducing the number of local variables");
1230 /* Indicate that we no longer have known memory locations or constants. */
1231 if (reg_equiv_constant)
1232 free (reg_equiv_constant);
1233 reg_equiv_constant = 0;
1234 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1235 reg_equiv_memory_loc = 0;
1237 if (offsets_known_at)
1238 free (offsets_known_at);
1242 free (reg_equiv_mem);
1243 free (reg_equiv_init);
1244 free (reg_equiv_address);
1245 free (reg_max_ref_width);
1246 free (reg_old_renumber);
1247 free (pseudo_previous_regs);
1248 free (pseudo_forbidden_regs);
1250 CLEAR_HARD_REG_SET (used_spill_regs);
1251 for (i = 0; i < n_spills; i++)
1252 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1254 /* Free all the insn_chain structures at once. */
1255 obstack_free (&reload_obstack, reload_startobj);
1256 unused_insn_chains = 0;
1257 fixup_abnormal_edges ();
1259 /* Replacing pseudos with their memory equivalents might have
1260 created shared rtx. Subsequent passes would get confused
1261 by this, so unshare everything here. */
1262 unshare_all_rtl_again (first);
1264 #ifdef STACK_BOUNDARY
1265 /* init_emit has set the alignment of the hard frame pointer
1266 to STACK_BOUNDARY. It is very likely no longer valid if
1267 the hard frame pointer was used for register allocation. */
1268 if (!frame_pointer_needed)
1269 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1275 /* Yet another special case. Unfortunately, reg-stack forces people to
1276 write incorrect clobbers in asm statements. These clobbers must not
1277 cause the register to appear in bad_spill_regs, otherwise we'll call
1278 fatal_insn later. We clear the corresponding regnos in the live
1279 register sets to avoid this.
1280 The whole thing is rather sick, I'm afraid. */
1283 maybe_fix_stack_asms (void)
1286 const char *constraints[MAX_RECOG_OPERANDS];
1287 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1288 struct insn_chain *chain;
1290 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1293 HARD_REG_SET clobbered, allowed;
1296 if (! INSN_P (chain->insn)
1297 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1299 pat = PATTERN (chain->insn);
1300 if (GET_CODE (pat) != PARALLEL)
1303 CLEAR_HARD_REG_SET (clobbered);
1304 CLEAR_HARD_REG_SET (allowed);
1306 /* First, make a mask of all stack regs that are clobbered. */
1307 for (i = 0; i < XVECLEN (pat, 0); i++)
1309 rtx t = XVECEXP (pat, 0, i);
1310 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1311 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1314 /* Get the operand values and constraints out of the insn. */
1315 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1316 constraints, operand_mode);
1318 /* For every operand, see what registers are allowed. */
1319 for (i = 0; i < noperands; i++)
1321 const char *p = constraints[i];
1322 /* For every alternative, we compute the class of registers allowed
1323 for reloading in CLS, and merge its contents into the reg set
1325 int cls = (int) NO_REGS;
1331 if (c == '\0' || c == ',' || c == '#')
1333 /* End of one alternative - mark the regs in the current
1334 class, and reset the class. */
1335 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1341 } while (c != '\0' && c != ',');
1349 case '=': case '+': case '*': case '%': case '?': case '!':
1350 case '0': case '1': case '2': case '3': case '4': case 'm':
1351 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1352 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1353 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1358 cls = (int) reg_class_subunion[cls]
1359 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1364 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1368 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1369 cls = (int) reg_class_subunion[cls]
1370 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1372 cls = (int) reg_class_subunion[cls]
1373 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1375 p += CONSTRAINT_LEN (c, p);
1378 /* Those of the registers which are clobbered, but allowed by the
1379 constraints, must be usable as reload registers. So clear them
1380 out of the life information. */
1381 AND_HARD_REG_SET (allowed, clobbered);
1382 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1383 if (TEST_HARD_REG_BIT (allowed, i))
1385 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1386 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1393 /* Copy the global variables n_reloads and rld into the corresponding elts
1396 copy_reloads (struct insn_chain *chain)
1398 chain->n_reloads = n_reloads;
1399 chain->rld = obstack_alloc (&reload_obstack,
1400 n_reloads * sizeof (struct reload));
1401 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1402 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1405 /* Walk the chain of insns, and determine for each whether it needs reloads
1406 and/or eliminations. Build the corresponding insns_need_reload list, and
1407 set something_needs_elimination as appropriate. */
1409 calculate_needs_all_insns (int global)
1411 struct insn_chain **pprev_reload = &insns_need_reload;
1412 struct insn_chain *chain, *next = 0;
1414 something_needs_elimination = 0;
1416 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1417 for (chain = reload_insn_chain; chain != 0; chain = next)
1419 rtx insn = chain->insn;
1423 /* Clear out the shortcuts. */
1424 chain->n_reloads = 0;
1425 chain->need_elim = 0;
1426 chain->need_reload = 0;
1427 chain->need_operand_change = 0;
1429 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1430 include REG_LABEL), we need to see what effects this has on the
1431 known offsets at labels. */
1433 if (LABEL_P (insn) || JUMP_P (insn)
1434 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1435 set_label_offsets (insn, insn, 0);
1439 rtx old_body = PATTERN (insn);
1440 int old_code = INSN_CODE (insn);
1441 rtx old_notes = REG_NOTES (insn);
1442 int did_elimination = 0;
1443 int operands_changed = 0;
1444 rtx set = single_set (insn);
1446 /* Skip insns that only set an equivalence. */
1447 if (set && REG_P (SET_DEST (set))
1448 && reg_renumber[REGNO (SET_DEST (set))] < 0
1449 && reg_equiv_constant[REGNO (SET_DEST (set))])
1452 /* If needed, eliminate any eliminable registers. */
1453 if (num_eliminable || num_eliminable_invariants)
1454 did_elimination = eliminate_regs_in_insn (insn, 0);
1456 /* Analyze the instruction. */
1457 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1458 global, spill_reg_order);
1460 /* If a no-op set needs more than one reload, this is likely
1461 to be something that needs input address reloads. We
1462 can't get rid of this cleanly later, and it is of no use
1463 anyway, so discard it now.
1464 We only do this when expensive_optimizations is enabled,
1465 since this complements reload inheritance / output
1466 reload deletion, and it can make debugging harder. */
1467 if (flag_expensive_optimizations && n_reloads > 1)
1469 rtx set = single_set (insn);
1471 && SET_SRC (set) == SET_DEST (set)
1472 && REG_P (SET_SRC (set))
1473 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1476 /* Delete it from the reload chain. */
1478 chain->prev->next = next;
1480 reload_insn_chain = next;
1482 next->prev = chain->prev;
1483 chain->next = unused_insn_chains;
1484 unused_insn_chains = chain;
1489 update_eliminable_offsets ();
1491 /* Remember for later shortcuts which insns had any reloads or
1492 register eliminations. */
1493 chain->need_elim = did_elimination;
1494 chain->need_reload = n_reloads > 0;
1495 chain->need_operand_change = operands_changed;
1497 /* Discard any register replacements done. */
1498 if (did_elimination)
1500 obstack_free (&reload_obstack, reload_insn_firstobj);
1501 PATTERN (insn) = old_body;
1502 INSN_CODE (insn) = old_code;
1503 REG_NOTES (insn) = old_notes;
1504 something_needs_elimination = 1;
1507 something_needs_operands_changed |= operands_changed;
1511 copy_reloads (chain);
1512 *pprev_reload = chain;
1513 pprev_reload = &chain->next_need_reload;
1520 /* Comparison function for qsort to decide which of two reloads
1521 should be handled first. *P1 and *P2 are the reload numbers. */
1524 reload_reg_class_lower (const void *r1p, const void *r2p)
1526 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1529 /* Consider required reloads before optional ones. */
1530 t = rld[r1].optional - rld[r2].optional;
1534 /* Count all solitary classes before non-solitary ones. */
1535 t = ((reg_class_size[(int) rld[r2].class] == 1)
1536 - (reg_class_size[(int) rld[r1].class] == 1));
1540 /* Aside from solitaires, consider all multi-reg groups first. */
1541 t = rld[r2].nregs - rld[r1].nregs;
1545 /* Consider reloads in order of increasing reg-class number. */
1546 t = (int) rld[r1].class - (int) rld[r2].class;
1550 /* If reloads are equally urgent, sort by reload number,
1551 so that the results of qsort leave nothing to chance. */
1555 /* The cost of spilling each hard reg. */
1556 static int spill_cost[FIRST_PSEUDO_REGISTER];
1558 /* When spilling multiple hard registers, we use SPILL_COST for the first
1559 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1560 only the first hard reg for a multi-reg pseudo. */
1561 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1563 /* Update the spill cost arrays, considering that pseudo REG is live. */
1566 count_pseudo (int reg)
1568 int freq = REG_FREQ (reg);
1569 int r = reg_renumber[reg];
1572 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1573 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1576 SET_REGNO_REG_SET (&pseudos_counted, reg);
1578 gcc_assert (r >= 0);
1580 spill_add_cost[r] += freq;
1582 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1584 spill_cost[r + nregs] += freq;
1587 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1588 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1591 order_regs_for_reload (struct insn_chain *chain)
1594 HARD_REG_SET used_by_pseudos;
1595 HARD_REG_SET used_by_pseudos2;
1596 reg_set_iterator rsi;
1598 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1600 memset (spill_cost, 0, sizeof spill_cost);
1601 memset (spill_add_cost, 0, sizeof spill_add_cost);
1603 /* Count number of uses of each hard reg by pseudo regs allocated to it
1604 and then order them by decreasing use. First exclude hard registers
1605 that are live in or across this insn. */
1607 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1608 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1609 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1610 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1612 /* Now find out which pseudos are allocated to it, and update
1614 CLEAR_REG_SET (&pseudos_counted);
1616 EXECUTE_IF_SET_IN_REG_SET
1617 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1621 EXECUTE_IF_SET_IN_REG_SET
1622 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1626 CLEAR_REG_SET (&pseudos_counted);
1629 /* Vector of reload-numbers showing the order in which the reloads should
1631 static short reload_order[MAX_RELOADS];
1633 /* This is used to keep track of the spill regs used in one insn. */
1634 static HARD_REG_SET used_spill_regs_local;
1636 /* We decided to spill hard register SPILLED, which has a size of
1637 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1638 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1639 update SPILL_COST/SPILL_ADD_COST. */
1642 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1644 int r = reg_renumber[reg];
1645 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1647 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1648 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1651 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1653 spill_add_cost[r] -= REG_FREQ (reg);
1655 spill_cost[r + nregs] -= REG_FREQ (reg);
1658 /* Find reload register to use for reload number ORDER. */
1661 find_reg (struct insn_chain *chain, int order)
1663 int rnum = reload_order[order];
1664 struct reload *rl = rld + rnum;
1665 int best_cost = INT_MAX;
1669 HARD_REG_SET not_usable;
1670 HARD_REG_SET used_by_other_reload;
1671 reg_set_iterator rsi;
1673 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1674 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1675 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1677 CLEAR_HARD_REG_SET (used_by_other_reload);
1678 for (k = 0; k < order; k++)
1680 int other = reload_order[k];
1682 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1683 for (j = 0; j < rld[other].nregs; j++)
1684 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1687 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1689 unsigned int regno = i;
1691 if (! TEST_HARD_REG_BIT (not_usable, regno)
1692 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1693 && HARD_REGNO_MODE_OK (regno, rl->mode))
1695 int this_cost = spill_cost[regno];
1697 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1699 for (j = 1; j < this_nregs; j++)
1701 this_cost += spill_add_cost[regno + j];
1702 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1703 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1708 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1710 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1712 if (this_cost < best_cost
1713 /* Among registers with equal cost, prefer caller-saved ones, or
1714 use REG_ALLOC_ORDER if it is defined. */
1715 || (this_cost == best_cost
1716 #ifdef REG_ALLOC_ORDER
1717 && (inv_reg_alloc_order[regno]
1718 < inv_reg_alloc_order[best_reg])
1720 && call_used_regs[regno]
1721 && ! call_used_regs[best_reg]
1726 best_cost = this_cost;
1734 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1736 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1737 rl->regno = best_reg;
1739 EXECUTE_IF_SET_IN_REG_SET
1740 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1742 count_spilled_pseudo (best_reg, rl->nregs, j);
1745 EXECUTE_IF_SET_IN_REG_SET
1746 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1748 count_spilled_pseudo (best_reg, rl->nregs, j);
1751 for (i = 0; i < rl->nregs; i++)
1753 gcc_assert (spill_cost[best_reg + i] == 0);
1754 gcc_assert (spill_add_cost[best_reg + i] == 0);
1755 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1760 /* Find more reload regs to satisfy the remaining need of an insn, which
1762 Do it by ascending class number, since otherwise a reg
1763 might be spilled for a big class and might fail to count
1764 for a smaller class even though it belongs to that class. */
1767 find_reload_regs (struct insn_chain *chain)
1771 /* In order to be certain of getting the registers we need,
1772 we must sort the reloads into order of increasing register class.
1773 Then our grabbing of reload registers will parallel the process
1774 that provided the reload registers. */
1775 for (i = 0; i < chain->n_reloads; i++)
1777 /* Show whether this reload already has a hard reg. */
1778 if (chain->rld[i].reg_rtx)
1780 int regno = REGNO (chain->rld[i].reg_rtx);
1781 chain->rld[i].regno = regno;
1783 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1786 chain->rld[i].regno = -1;
1787 reload_order[i] = i;
1790 n_reloads = chain->n_reloads;
1791 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1793 CLEAR_HARD_REG_SET (used_spill_regs_local);
1796 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1798 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1800 /* Compute the order of preference for hard registers to spill. */
1802 order_regs_for_reload (chain);
1804 for (i = 0; i < n_reloads; i++)
1806 int r = reload_order[i];
1808 /* Ignore reloads that got marked inoperative. */
1809 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1810 && ! rld[r].optional
1811 && rld[r].regno == -1)
1812 if (! find_reg (chain, i))
1814 spill_failure (chain->insn, rld[r].class);
1820 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1821 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1823 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1827 select_reload_regs (void)
1829 struct insn_chain *chain;
1831 /* Try to satisfy the needs for each insn. */
1832 for (chain = insns_need_reload; chain != 0;
1833 chain = chain->next_need_reload)
1834 find_reload_regs (chain);
1837 /* Delete all insns that were inserted by emit_caller_save_insns during
1840 delete_caller_save_insns (void)
1842 struct insn_chain *c = reload_insn_chain;
1846 while (c != 0 && c->is_caller_save_insn)
1848 struct insn_chain *next = c->next;
1851 if (c == reload_insn_chain)
1852 reload_insn_chain = next;
1856 next->prev = c->prev;
1858 c->prev->next = next;
1859 c->next = unused_insn_chains;
1860 unused_insn_chains = c;
1868 /* Handle the failure to find a register to spill.
1869 INSN should be one of the insns which needed this particular spill reg. */
1872 spill_failure (rtx insn, enum reg_class class)
1874 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1875 if (asm_noperands (PATTERN (insn)) >= 0)
1876 error_for_asm (insn, "can't find a register in class %qs while "
1877 "reloading %<asm%>",
1878 reg_class_names[class]);
1881 error ("unable to find a register to spill in class %qs",
1882 reg_class_names[class]);
1883 fatal_insn ("this is the insn:", insn);
1887 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1888 data that is dead in INSN. */
1891 delete_dead_insn (rtx insn)
1893 rtx prev = prev_real_insn (insn);
1896 /* If the previous insn sets a register that dies in our insn, delete it
1898 if (prev && GET_CODE (PATTERN (prev)) == SET
1899 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1900 && reg_mentioned_p (prev_dest, PATTERN (insn))
1901 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1902 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1903 delete_dead_insn (prev);
1905 SET_INSN_DELETED (insn);
1908 /* Modify the home of pseudo-reg I.
1909 The new home is present in reg_renumber[I].
1911 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1912 or it may be -1, meaning there is none or it is not relevant.
1913 This is used so that all pseudos spilled from a given hard reg
1914 can share one stack slot. */
1917 alter_reg (int i, int from_reg)
1919 /* When outputting an inline function, this can happen
1920 for a reg that isn't actually used. */
1921 if (regno_reg_rtx[i] == 0)
1924 /* If the reg got changed to a MEM at rtl-generation time,
1926 if (!REG_P (regno_reg_rtx[i]))
1929 /* Modify the reg-rtx to contain the new hard reg
1930 number or else to contain its pseudo reg number. */
1931 REGNO (regno_reg_rtx[i])
1932 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1934 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1935 allocate a stack slot for it. */
1937 if (reg_renumber[i] < 0
1938 && REG_N_REFS (i) > 0
1939 && reg_equiv_constant[i] == 0
1940 && reg_equiv_memory_loc[i] == 0)
1943 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1944 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1947 /* Each pseudo reg has an inherent size which comes from its own mode,
1948 and a total size which provides room for paradoxical subregs
1949 which refer to the pseudo reg in wider modes.
1951 We can use a slot already allocated if it provides both
1952 enough inherent space and enough total space.
1953 Otherwise, we allocate a new slot, making sure that it has no less
1954 inherent space, and no less total space, then the previous slot. */
1957 /* No known place to spill from => no slot to reuse. */
1958 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1959 inherent_size == total_size ? 0 : -1);
1960 if (BYTES_BIG_ENDIAN)
1961 /* Cancel the big-endian correction done in assign_stack_local.
1962 Get the address of the beginning of the slot.
1963 This is so we can do a big-endian correction unconditionally
1965 adjust = inherent_size - total_size;
1967 /* Nothing can alias this slot except this pseudo. */
1968 set_mem_alias_set (x, new_alias_set ());
1971 /* Reuse a stack slot if possible. */
1972 else if (spill_stack_slot[from_reg] != 0
1973 && spill_stack_slot_width[from_reg] >= total_size
1974 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1976 x = spill_stack_slot[from_reg];
1978 /* Allocate a bigger slot. */
1981 /* Compute maximum size needed, both for inherent size
1982 and for total size. */
1983 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1986 if (spill_stack_slot[from_reg])
1988 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1990 mode = GET_MODE (spill_stack_slot[from_reg]);
1991 if (spill_stack_slot_width[from_reg] > total_size)
1992 total_size = spill_stack_slot_width[from_reg];
1995 /* Make a slot with that size. */
1996 x = assign_stack_local (mode, total_size,
1997 inherent_size == total_size ? 0 : -1);
2000 /* All pseudos mapped to this slot can alias each other. */
2001 if (spill_stack_slot[from_reg])
2002 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2004 set_mem_alias_set (x, new_alias_set ());
2006 if (BYTES_BIG_ENDIAN)
2008 /* Cancel the big-endian correction done in assign_stack_local.
2009 Get the address of the beginning of the slot.
2010 This is so we can do a big-endian correction unconditionally
2012 adjust = GET_MODE_SIZE (mode) - total_size;
2015 = adjust_address_nv (x, mode_for_size (total_size
2021 spill_stack_slot[from_reg] = stack_slot;
2022 spill_stack_slot_width[from_reg] = total_size;
2025 /* On a big endian machine, the "address" of the slot
2026 is the address of the low part that fits its inherent mode. */
2027 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2028 adjust += (total_size - inherent_size);
2030 /* If we have any adjustment to make, or if the stack slot is the
2031 wrong mode, make a new stack slot. */
2032 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2034 /* If we have a decl for the original register, set it for the
2035 memory. If this is a shared MEM, make a copy. */
2036 if (REG_EXPR (regno_reg_rtx[i])
2037 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2039 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2041 /* We can do this only for the DECLs home pseudo, not for
2042 any copies of it, since otherwise when the stack slot
2043 is reused, nonoverlapping_memrefs_p might think they
2045 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2047 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2050 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2054 /* Save the stack slot for later. */
2055 reg_equiv_memory_loc[i] = x;
2059 /* Mark the slots in regs_ever_live for the hard regs
2060 used by pseudo-reg number REGNO. */
2063 mark_home_live (int regno)
2067 i = reg_renumber[regno];
2070 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2072 regs_ever_live[i++] = 1;
2075 /* This function handles the tracking of elimination offsets around branches.
2077 X is a piece of RTL being scanned.
2079 INSN is the insn that it came from, if any.
2081 INITIAL_P is nonzero if we are to set the offset to be the initial
2082 offset and zero if we are setting the offset of the label to be the
2086 set_label_offsets (rtx x, rtx insn, int initial_p)
2088 enum rtx_code code = GET_CODE (x);
2091 struct elim_table *p;
2096 if (LABEL_REF_NONLOCAL_P (x))
2101 /* ... fall through ... */
2104 /* If we know nothing about this label, set the desired offsets. Note
2105 that this sets the offset at a label to be the offset before a label
2106 if we don't know anything about the label. This is not correct for
2107 the label after a BARRIER, but is the best guess we can make. If
2108 we guessed wrong, we will suppress an elimination that might have
2109 been possible had we been able to guess correctly. */
2111 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2113 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2114 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2115 = (initial_p ? reg_eliminate[i].initial_offset
2116 : reg_eliminate[i].offset);
2117 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2120 /* Otherwise, if this is the definition of a label and it is
2121 preceded by a BARRIER, set our offsets to the known offset of
2125 && (tem = prev_nonnote_insn (insn)) != 0
2127 set_offsets_for_label (insn);
2129 /* If neither of the above cases is true, compare each offset
2130 with those previously recorded and suppress any eliminations
2131 where the offsets disagree. */
2133 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2134 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2135 != (initial_p ? reg_eliminate[i].initial_offset
2136 : reg_eliminate[i].offset))
2137 reg_eliminate[i].can_eliminate = 0;
2142 set_label_offsets (PATTERN (insn), insn, initial_p);
2144 /* ... fall through ... */
2148 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2149 and hence must have all eliminations at their initial offsets. */
2150 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2151 if (REG_NOTE_KIND (tem) == REG_LABEL)
2152 set_label_offsets (XEXP (tem, 0), insn, 1);
2158 /* Each of the labels in the parallel or address vector must be
2159 at their initial offsets. We want the first field for PARALLEL
2160 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2162 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2163 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2168 /* We only care about setting PC. If the source is not RETURN,
2169 IF_THEN_ELSE, or a label, disable any eliminations not at
2170 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2171 isn't one of those possibilities. For branches to a label,
2172 call ourselves recursively.
2174 Note that this can disable elimination unnecessarily when we have
2175 a non-local goto since it will look like a non-constant jump to
2176 someplace in the current function. This isn't a significant
2177 problem since such jumps will normally be when all elimination
2178 pairs are back to their initial offsets. */
2180 if (SET_DEST (x) != pc_rtx)
2183 switch (GET_CODE (SET_SRC (x)))
2190 set_label_offsets (SET_SRC (x), insn, initial_p);
2194 tem = XEXP (SET_SRC (x), 1);
2195 if (GET_CODE (tem) == LABEL_REF)
2196 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2197 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2200 tem = XEXP (SET_SRC (x), 2);
2201 if (GET_CODE (tem) == LABEL_REF)
2202 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2203 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2211 /* If we reach here, all eliminations must be at their initial
2212 offset because we are doing a jump to a variable address. */
2213 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2214 if (p->offset != p->initial_offset)
2215 p->can_eliminate = 0;
2223 /* Scan X and replace any eliminable registers (such as fp) with a
2224 replacement (such as sp), plus an offset.
2226 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2227 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2228 MEM, we are allowed to replace a sum of a register and the constant zero
2229 with the register, which we cannot do outside a MEM. In addition, we need
2230 to record the fact that a register is referenced outside a MEM.
2232 If INSN is an insn, it is the insn containing X. If we replace a REG
2233 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2234 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2235 the REG is being modified.
2237 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2238 That's used when we eliminate in expressions stored in notes.
2239 This means, do not set ref_outside_mem even if the reference
2242 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2243 replacements done assuming all offsets are at their initial values. If
2244 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2245 encounter, return the actual location so that find_reloads will do
2246 the proper thing. */
2249 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2251 enum rtx_code code = GET_CODE (x);
2252 struct elim_table *ep;
2259 if (! current_function_decl)
2281 /* First handle the case where we encounter a bare register that
2282 is eliminable. Replace it with a PLUS. */
2283 if (regno < FIRST_PSEUDO_REGISTER)
2285 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2287 if (ep->from_rtx == x && ep->can_eliminate)
2288 return plus_constant (ep->to_rtx, ep->previous_offset);
2291 else if (reg_renumber && reg_renumber[regno] < 0
2292 && reg_equiv_constant && reg_equiv_constant[regno]
2293 && ! CONSTANT_P (reg_equiv_constant[regno]))
2294 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2298 /* You might think handling MINUS in a manner similar to PLUS is a
2299 good idea. It is not. It has been tried multiple times and every
2300 time the change has had to have been reverted.
2302 Other parts of reload know a PLUS is special (gen_reload for example)
2303 and require special code to handle code a reloaded PLUS operand.
2305 Also consider backends where the flags register is clobbered by a
2306 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2307 lea instruction comes to mind). If we try to reload a MINUS, we
2308 may kill the flags register that was holding a useful value.
2310 So, please before trying to handle MINUS, consider reload as a
2311 whole instead of this little section as well as the backend issues. */
2313 /* If this is the sum of an eliminable register and a constant, rework
2315 if (REG_P (XEXP (x, 0))
2316 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2317 && CONSTANT_P (XEXP (x, 1)))
2319 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2321 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2323 /* The only time we want to replace a PLUS with a REG (this
2324 occurs when the constant operand of the PLUS is the negative
2325 of the offset) is when we are inside a MEM. We won't want
2326 to do so at other times because that would change the
2327 structure of the insn in a way that reload can't handle.
2328 We special-case the commonest situation in
2329 eliminate_regs_in_insn, so just replace a PLUS with a
2330 PLUS here, unless inside a MEM. */
2331 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2332 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2335 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2336 plus_constant (XEXP (x, 1),
2337 ep->previous_offset));
2340 /* If the register is not eliminable, we are done since the other
2341 operand is a constant. */
2345 /* If this is part of an address, we want to bring any constant to the
2346 outermost PLUS. We will do this by doing register replacement in
2347 our operands and seeing if a constant shows up in one of them.
2349 Note that there is no risk of modifying the structure of the insn,
2350 since we only get called for its operands, thus we are either
2351 modifying the address inside a MEM, or something like an address
2352 operand of a load-address insn. */
2355 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2356 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2358 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2360 /* If one side is a PLUS and the other side is a pseudo that
2361 didn't get a hard register but has a reg_equiv_constant,
2362 we must replace the constant here since it may no longer
2363 be in the position of any operand. */
2364 if (GET_CODE (new0) == PLUS && REG_P (new1)
2365 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2366 && reg_renumber[REGNO (new1)] < 0
2367 && reg_equiv_constant != 0
2368 && reg_equiv_constant[REGNO (new1)] != 0)
2369 new1 = reg_equiv_constant[REGNO (new1)];
2370 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2371 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2372 && reg_renumber[REGNO (new0)] < 0
2373 && reg_equiv_constant[REGNO (new0)] != 0)
2374 new0 = reg_equiv_constant[REGNO (new0)];
2376 new = form_sum (new0, new1);
2378 /* As above, if we are not inside a MEM we do not want to
2379 turn a PLUS into something else. We might try to do so here
2380 for an addition of 0 if we aren't optimizing. */
2381 if (! mem_mode && GET_CODE (new) != PLUS)
2382 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2390 /* If this is the product of an eliminable register and a
2391 constant, apply the distribute law and move the constant out
2392 so that we have (plus (mult ..) ..). This is needed in order
2393 to keep load-address insns valid. This case is pathological.
2394 We ignore the possibility of overflow here. */
2395 if (REG_P (XEXP (x, 0))
2396 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2397 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2398 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2400 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2403 /* Refs inside notes don't count for this purpose. */
2404 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2405 || GET_CODE (insn) == INSN_LIST)))
2406 ep->ref_outside_mem = 1;
2409 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2410 ep->previous_offset * INTVAL (XEXP (x, 1)));
2413 /* ... fall through ... */
2417 /* See comments before PLUS about handling MINUS. */
2419 case DIV: case UDIV:
2420 case MOD: case UMOD:
2421 case AND: case IOR: case XOR:
2422 case ROTATERT: case ROTATE:
2423 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2425 case GE: case GT: case GEU: case GTU:
2426 case LE: case LT: case LEU: case LTU:
2428 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2430 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2432 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2433 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2438 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2441 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2442 if (new != XEXP (x, 0))
2444 /* If this is a REG_DEAD note, it is not valid anymore.
2445 Using the eliminated version could result in creating a
2446 REG_DEAD note for the stack or frame pointer. */
2447 if (GET_MODE (x) == REG_DEAD)
2449 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2452 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2456 /* ... fall through ... */
2459 /* Now do eliminations in the rest of the chain. If this was
2460 an EXPR_LIST, this might result in allocating more memory than is
2461 strictly needed, but it simplifies the code. */
2464 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2465 if (new != XEXP (x, 1))
2467 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2475 case STRICT_LOW_PART:
2477 case SIGN_EXTEND: case ZERO_EXTEND:
2478 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2479 case FLOAT: case FIX:
2480 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2488 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2489 if (new != XEXP (x, 0))
2490 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2494 /* Similar to above processing, but preserve SUBREG_BYTE.
2495 Convert (subreg (mem)) to (mem) if not paradoxical.
2496 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2497 pseudo didn't get a hard reg, we must replace this with the
2498 eliminated version of the memory location because push_reload
2499 may do the replacement in certain circumstances. */
2500 if (REG_P (SUBREG_REG (x))
2501 && (GET_MODE_SIZE (GET_MODE (x))
2502 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2503 && reg_equiv_memory_loc != 0
2504 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2506 new = SUBREG_REG (x);
2509 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2511 if (new != SUBREG_REG (x))
2513 int x_size = GET_MODE_SIZE (GET_MODE (x));
2514 int new_size = GET_MODE_SIZE (GET_MODE (new));
2517 && ((x_size < new_size
2518 #ifdef WORD_REGISTER_OPERATIONS
2519 /* On these machines, combine can create rtl of the form
2520 (set (subreg:m1 (reg:m2 R) 0) ...)
2521 where m1 < m2, and expects something interesting to
2522 happen to the entire word. Moreover, it will use the
2523 (reg:m2 R) later, expecting all bits to be preserved.
2524 So if the number of words is the same, preserve the
2525 subreg so that push_reload can see it. */
2526 && ! ((x_size - 1) / UNITS_PER_WORD
2527 == (new_size -1 ) / UNITS_PER_WORD)
2530 || x_size == new_size)
2532 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2534 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2540 /* Our only special processing is to pass the mode of the MEM to our
2541 recursive call and copy the flags. While we are here, handle this
2542 case more efficiently. */
2544 replace_equiv_address_nv (x,
2545 eliminate_regs (XEXP (x, 0),
2546 GET_MODE (x), insn));
2549 /* Handle insn_list USE that a call to a pure function may generate. */
2550 new = eliminate_regs (XEXP (x, 0), 0, insn);
2551 if (new != XEXP (x, 0))
2552 return gen_rtx_USE (GET_MODE (x), new);
2564 /* Process each of our operands recursively. If any have changed, make a
2566 fmt = GET_RTX_FORMAT (code);
2567 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2571 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2572 if (new != XEXP (x, i) && ! copied)
2574 rtx new_x = rtx_alloc (code);
2575 memcpy (new_x, x, RTX_SIZE (code));
2581 else if (*fmt == 'E')
2584 for (j = 0; j < XVECLEN (x, i); j++)
2586 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2587 if (new != XVECEXP (x, i, j) && ! copied_vec)
2589 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2593 rtx new_x = rtx_alloc (code);
2594 memcpy (new_x, x, RTX_SIZE (code));
2598 XVEC (x, i) = new_v;
2601 XVECEXP (x, i, j) = new;
2609 /* Scan rtx X for modifications of elimination target registers. Update
2610 the table of eliminables to reflect the changed state. MEM_MODE is
2611 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2614 elimination_effects (rtx x, enum machine_mode mem_mode)
2616 enum rtx_code code = GET_CODE (x);
2617 struct elim_table *ep;
2641 /* First handle the case where we encounter a bare register that
2642 is eliminable. Replace it with a PLUS. */
2643 if (regno < FIRST_PSEUDO_REGISTER)
2645 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2647 if (ep->from_rtx == x && ep->can_eliminate)
2650 ep->ref_outside_mem = 1;
2655 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2656 && reg_equiv_constant[regno]
2657 && ! function_invariant_p (reg_equiv_constant[regno]))
2658 elimination_effects (reg_equiv_constant[regno], mem_mode);
2667 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2668 if (ep->to_rtx == XEXP (x, 0))
2670 int size = GET_MODE_SIZE (mem_mode);
2672 /* If more bytes than MEM_MODE are pushed, account for them. */
2673 #ifdef PUSH_ROUNDING
2674 if (ep->to_rtx == stack_pointer_rtx)
2675 size = PUSH_ROUNDING (size);
2677 if (code == PRE_DEC || code == POST_DEC)
2679 else if (code == PRE_INC || code == POST_INC)
2681 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2682 && GET_CODE (XEXP (x, 1)) == PLUS
2683 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2684 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2685 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2688 /* These two aren't unary operators. */
2689 if (code == POST_MODIFY || code == PRE_MODIFY)
2692 /* Fall through to generic unary operation case. */
2693 case STRICT_LOW_PART:
2695 case SIGN_EXTEND: case ZERO_EXTEND:
2696 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2697 case FLOAT: case FIX:
2698 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2706 elimination_effects (XEXP (x, 0), mem_mode);
2710 if (REG_P (SUBREG_REG (x))
2711 && (GET_MODE_SIZE (GET_MODE (x))
2712 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2713 && reg_equiv_memory_loc != 0
2714 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2717 elimination_effects (SUBREG_REG (x), mem_mode);
2721 /* If using a register that is the source of an eliminate we still
2722 think can be performed, note it cannot be performed since we don't
2723 know how this register is used. */
2724 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2725 if (ep->from_rtx == XEXP (x, 0))
2726 ep->can_eliminate = 0;
2728 elimination_effects (XEXP (x, 0), mem_mode);
2732 /* If clobbering a register that is the replacement register for an
2733 elimination we still think can be performed, note that it cannot
2734 be performed. Otherwise, we need not be concerned about it. */
2735 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2736 if (ep->to_rtx == XEXP (x, 0))
2737 ep->can_eliminate = 0;
2739 elimination_effects (XEXP (x, 0), mem_mode);
2743 /* Check for setting a register that we know about. */
2744 if (REG_P (SET_DEST (x)))
2746 /* See if this is setting the replacement register for an
2749 If DEST is the hard frame pointer, we do nothing because we
2750 assume that all assignments to the frame pointer are for
2751 non-local gotos and are being done at a time when they are valid
2752 and do not disturb anything else. Some machines want to
2753 eliminate a fake argument pointer (or even a fake frame pointer)
2754 with either the real frame or the stack pointer. Assignments to
2755 the hard frame pointer must not prevent this elimination. */
2757 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2759 if (ep->to_rtx == SET_DEST (x)
2760 && SET_DEST (x) != hard_frame_pointer_rtx)
2762 /* If it is being incremented, adjust the offset. Otherwise,
2763 this elimination can't be done. */
2764 rtx src = SET_SRC (x);
2766 if (GET_CODE (src) == PLUS
2767 && XEXP (src, 0) == SET_DEST (x)
2768 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2769 ep->offset -= INTVAL (XEXP (src, 1));
2771 ep->can_eliminate = 0;
2775 elimination_effects (SET_DEST (x), 0);
2776 elimination_effects (SET_SRC (x), 0);
2780 /* Our only special processing is to pass the mode of the MEM to our
2782 elimination_effects (XEXP (x, 0), GET_MODE (x));
2789 fmt = GET_RTX_FORMAT (code);
2790 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2793 elimination_effects (XEXP (x, i), mem_mode);
2794 else if (*fmt == 'E')
2795 for (j = 0; j < XVECLEN (x, i); j++)
2796 elimination_effects (XVECEXP (x, i, j), mem_mode);
2800 /* Descend through rtx X and verify that no references to eliminable registers
2801 remain. If any do remain, mark the involved register as not
2805 check_eliminable_occurrences (rtx x)
2814 code = GET_CODE (x);
2816 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2818 struct elim_table *ep;
2820 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2821 if (ep->from_rtx == x)
2822 ep->can_eliminate = 0;
2826 fmt = GET_RTX_FORMAT (code);
2827 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2830 check_eliminable_occurrences (XEXP (x, i));
2831 else if (*fmt == 'E')
2834 for (j = 0; j < XVECLEN (x, i); j++)
2835 check_eliminable_occurrences (XVECEXP (x, i, j));
2840 /* Scan INSN and eliminate all eliminable registers in it.
2842 If REPLACE is nonzero, do the replacement destructively. Also
2843 delete the insn as dead it if it is setting an eliminable register.
2845 If REPLACE is zero, do all our allocations in reload_obstack.
2847 If no eliminations were done and this insn doesn't require any elimination
2848 processing (these are not identical conditions: it might be updating sp,
2849 but not referencing fp; this needs to be seen during reload_as_needed so
2850 that the offset between fp and sp can be taken into consideration), zero
2851 is returned. Otherwise, 1 is returned. */
2854 eliminate_regs_in_insn (rtx insn, int replace)
2856 int icode = recog_memoized (insn);
2857 rtx old_body = PATTERN (insn);
2858 int insn_is_asm = asm_noperands (old_body) >= 0;
2859 rtx old_set = single_set (insn);
2863 rtx substed_operand[MAX_RECOG_OPERANDS];
2864 rtx orig_operand[MAX_RECOG_OPERANDS];
2865 struct elim_table *ep;
2868 if (! insn_is_asm && icode < 0)
2870 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2871 || GET_CODE (PATTERN (insn)) == CLOBBER
2872 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2873 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2874 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2878 if (old_set != 0 && REG_P (SET_DEST (old_set))
2879 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2881 /* Check for setting an eliminable register. */
2882 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2883 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2885 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2886 /* If this is setting the frame pointer register to the
2887 hardware frame pointer register and this is an elimination
2888 that will be done (tested above), this insn is really
2889 adjusting the frame pointer downward to compensate for
2890 the adjustment done before a nonlocal goto. */
2891 if (ep->from == FRAME_POINTER_REGNUM
2892 && ep->to == HARD_FRAME_POINTER_REGNUM)
2894 rtx base = SET_SRC (old_set);
2895 rtx base_insn = insn;
2896 HOST_WIDE_INT offset = 0;
2898 while (base != ep->to_rtx)
2900 rtx prev_insn, prev_set;
2902 if (GET_CODE (base) == PLUS
2903 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2905 offset += INTVAL (XEXP (base, 1));
2906 base = XEXP (base, 0);
2908 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2909 && (prev_set = single_set (prev_insn)) != 0
2910 && rtx_equal_p (SET_DEST (prev_set), base))
2912 base = SET_SRC (prev_set);
2913 base_insn = prev_insn;
2919 if (base == ep->to_rtx)
2922 = plus_constant (ep->to_rtx, offset - ep->offset);
2924 new_body = old_body;
2927 new_body = copy_insn (old_body);
2928 if (REG_NOTES (insn))
2929 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2931 PATTERN (insn) = new_body;
2932 old_set = single_set (insn);
2934 /* First see if this insn remains valid when we
2935 make the change. If not, keep the INSN_CODE
2936 the same and let reload fit it up. */
2937 validate_change (insn, &SET_SRC (old_set), src, 1);
2938 validate_change (insn, &SET_DEST (old_set),
2940 if (! apply_change_group ())
2942 SET_SRC (old_set) = src;
2943 SET_DEST (old_set) = ep->to_rtx;
2952 /* In this case this insn isn't serving a useful purpose. We
2953 will delete it in reload_as_needed once we know that this
2954 elimination is, in fact, being done.
2956 If REPLACE isn't set, we can't delete this insn, but needn't
2957 process it since it won't be used unless something changes. */
2960 delete_dead_insn (insn);
2968 /* We allow one special case which happens to work on all machines we
2969 currently support: a single set with the source or a REG_EQUAL
2970 note being a PLUS of an eliminable register and a constant. */
2972 if (old_set && REG_P (SET_DEST (old_set)))
2974 /* First see if the source is of the form (plus (reg) CST). */
2975 if (GET_CODE (SET_SRC (old_set)) == PLUS
2976 && REG_P (XEXP (SET_SRC (old_set), 0))
2977 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2978 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2979 plus_src = SET_SRC (old_set);
2980 else if (REG_P (SET_SRC (old_set)))
2982 /* Otherwise, see if we have a REG_EQUAL note of the form
2983 (plus (reg) CST). */
2985 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2987 if (REG_NOTE_KIND (links) == REG_EQUAL
2988 && GET_CODE (XEXP (links, 0)) == PLUS
2989 && REG_P (XEXP (XEXP (links, 0), 0))
2990 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2991 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
2993 plus_src = XEXP (links, 0);
3001 rtx reg = XEXP (plus_src, 0);
3002 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3004 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3005 if (ep->from_rtx == reg && ep->can_eliminate)
3007 offset += ep->offset;
3012 /* We assume here that if we need a PARALLEL with
3013 CLOBBERs for this assignment, we can do with the
3014 MATCH_SCRATCHes that add_clobbers allocates.
3015 There's not much we can do if that doesn't work. */
3016 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3020 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3023 rtvec vec = rtvec_alloc (num_clobbers + 1);
3025 vec->elem[0] = PATTERN (insn);
3026 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3027 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3029 gcc_assert (INSN_CODE (insn) >= 0);
3031 /* If we have a nonzero offset, and the source is already
3032 a simple REG, the following transformation would
3033 increase the cost of the insn by replacing a simple REG
3034 with (plus (reg sp) CST). So try only when plus_src
3035 comes from old_set proper, not REG_NOTES. */
3036 else if (SET_SRC (old_set) == plus_src)
3038 new_body = old_body;
3041 new_body = copy_insn (old_body);
3042 if (REG_NOTES (insn))
3043 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3045 PATTERN (insn) = new_body;
3046 old_set = single_set (insn);
3048 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3049 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3055 /* This can't have an effect on elimination offsets, so skip right
3061 /* Determine the effects of this insn on elimination offsets. */
3062 elimination_effects (old_body, 0);
3064 /* Eliminate all eliminable registers occurring in operands that
3065 can be handled by reload. */
3066 extract_insn (insn);
3067 for (i = 0; i < recog_data.n_operands; i++)
3069 orig_operand[i] = recog_data.operand[i];
3070 substed_operand[i] = recog_data.operand[i];
3072 /* For an asm statement, every operand is eliminable. */
3073 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3075 /* Check for setting a register that we know about. */
3076 if (recog_data.operand_type[i] != OP_IN
3077 && REG_P (orig_operand[i]))
3079 /* If we are assigning to a register that can be eliminated, it
3080 must be as part of a PARALLEL, since the code above handles
3081 single SETs. We must indicate that we can no longer
3082 eliminate this reg. */
3083 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3085 if (ep->from_rtx == orig_operand[i])
3086 ep->can_eliminate = 0;
3089 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3090 replace ? insn : NULL_RTX);
3091 if (substed_operand[i] != orig_operand[i])
3093 /* Terminate the search in check_eliminable_occurrences at
3095 *recog_data.operand_loc[i] = 0;
3097 /* If an output operand changed from a REG to a MEM and INSN is an
3098 insn, write a CLOBBER insn. */
3099 if (recog_data.operand_type[i] != OP_IN
3100 && REG_P (orig_operand[i])
3101 && MEM_P (substed_operand[i])
3103 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3108 for (i = 0; i < recog_data.n_dups; i++)
3109 *recog_data.dup_loc[i]
3110 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3112 /* If any eliminable remain, they aren't eliminable anymore. */
3113 check_eliminable_occurrences (old_body);
3115 /* Substitute the operands; the new values are in the substed_operand
3117 for (i = 0; i < recog_data.n_operands; i++)
3118 *recog_data.operand_loc[i] = substed_operand[i];
3119 for (i = 0; i < recog_data.n_dups; i++)
3120 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3122 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3123 re-recognize the insn. We do this in case we had a simple addition
3124 but now can do this as a load-address. This saves an insn in this
3126 If re-recognition fails, the old insn code number will still be used,
3127 and some register operands may have changed into PLUS expressions.
3128 These will be handled by find_reloads by loading them into a register
3133 /* If we aren't replacing things permanently and we changed something,
3134 make another copy to ensure that all the RTL is new. Otherwise
3135 things can go wrong if find_reload swaps commutative operands
3136 and one is inside RTL that has been copied while the other is not. */
3137 new_body = old_body;
3140 new_body = copy_insn (old_body);
3141 if (REG_NOTES (insn))
3142 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3144 PATTERN (insn) = new_body;
3146 /* If we had a move insn but now we don't, rerecognize it. This will
3147 cause spurious re-recognition if the old move had a PARALLEL since
3148 the new one still will, but we can't call single_set without
3149 having put NEW_BODY into the insn and the re-recognition won't
3150 hurt in this rare case. */
3151 /* ??? Why this huge if statement - why don't we just rerecognize the
3155 && ((REG_P (SET_SRC (old_set))
3156 && (GET_CODE (new_body) != SET
3157 || !REG_P (SET_SRC (new_body))))
3158 /* If this was a load from or store to memory, compare
3159 the MEM in recog_data.operand to the one in the insn.
3160 If they are not equal, then rerecognize the insn. */
3162 && ((MEM_P (SET_SRC (old_set))
3163 && SET_SRC (old_set) != recog_data.operand[1])
3164 || (MEM_P (SET_DEST (old_set))
3165 && SET_DEST (old_set) != recog_data.operand[0])))
3166 /* If this was an add insn before, rerecognize. */
3167 || GET_CODE (SET_SRC (old_set)) == PLUS))
3169 int new_icode = recog (PATTERN (insn), insn, 0);
3171 INSN_CODE (insn) = icode;
3175 /* Restore the old body. If there were any changes to it, we made a copy
3176 of it while the changes were still in place, so we'll correctly return
3177 a modified insn below. */
3180 /* Restore the old body. */
3181 for (i = 0; i < recog_data.n_operands; i++)
3182 *recog_data.operand_loc[i] = orig_operand[i];
3183 for (i = 0; i < recog_data.n_dups; i++)
3184 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3187 /* Update all elimination pairs to reflect the status after the current
3188 insn. The changes we make were determined by the earlier call to
3189 elimination_effects.
3191 We also detect cases where register elimination cannot be done,
3192 namely, if a register would be both changed and referenced outside a MEM
3193 in the resulting insn since such an insn is often undefined and, even if
3194 not, we cannot know what meaning will be given to it. Note that it is
3195 valid to have a register used in an address in an insn that changes it
3196 (presumably with a pre- or post-increment or decrement).
3198 If anything changes, return nonzero. */
3200 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3202 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3203 ep->can_eliminate = 0;
3205 ep->ref_outside_mem = 0;
3207 if (ep->previous_offset != ep->offset)
3212 /* If we changed something, perform elimination in REG_NOTES. This is
3213 needed even when REPLACE is zero because a REG_DEAD note might refer
3214 to a register that we eliminate and could cause a different number
3215 of spill registers to be needed in the final reload pass than in
3217 if (val && REG_NOTES (insn) != 0)
3218 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3223 /* Loop through all elimination pairs.
3224 Recalculate the number not at initial offset.
3226 Compute the maximum offset (minimum offset if the stack does not
3227 grow downward) for each elimination pair. */
3230 update_eliminable_offsets (void)
3232 struct elim_table *ep;
3234 num_not_at_initial_offset = 0;
3235 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3237 ep->previous_offset = ep->offset;
3238 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3239 num_not_at_initial_offset++;
3243 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3244 replacement we currently believe is valid, mark it as not eliminable if X
3245 modifies DEST in any way other than by adding a constant integer to it.
3247 If DEST is the frame pointer, we do nothing because we assume that
3248 all assignments to the hard frame pointer are nonlocal gotos and are being
3249 done at a time when they are valid and do not disturb anything else.
3250 Some machines want to eliminate a fake argument pointer with either the
3251 frame or stack pointer. Assignments to the hard frame pointer must not
3252 prevent this elimination.
3254 Called via note_stores from reload before starting its passes to scan
3255 the insns of the function. */
3258 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3262 /* A SUBREG of a hard register here is just changing its mode. We should
3263 not see a SUBREG of an eliminable hard register, but check just in
3265 if (GET_CODE (dest) == SUBREG)
3266 dest = SUBREG_REG (dest);
3268 if (dest == hard_frame_pointer_rtx)
3271 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3272 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3273 && (GET_CODE (x) != SET
3274 || GET_CODE (SET_SRC (x)) != PLUS
3275 || XEXP (SET_SRC (x), 0) != dest
3276 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3278 reg_eliminate[i].can_eliminate_previous
3279 = reg_eliminate[i].can_eliminate = 0;
3284 /* Verify that the initial elimination offsets did not change since the
3285 last call to set_initial_elim_offsets. This is used to catch cases
3286 where something illegal happened during reload_as_needed that could
3287 cause incorrect code to be generated if we did not check for it. */
3290 verify_initial_elim_offsets (void)
3294 #ifdef ELIMINABLE_REGS
3295 struct elim_table *ep;
3297 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3299 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3300 gcc_assert (t == ep->initial_offset);
3303 INITIAL_FRAME_POINTER_OFFSET (t);
3304 gcc_assert (t == reg_eliminate[0].initial_offset);
3308 /* Reset all offsets on eliminable registers to their initial values. */
3311 set_initial_elim_offsets (void)
3313 struct elim_table *ep = reg_eliminate;
3315 #ifdef ELIMINABLE_REGS
3316 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3318 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3319 ep->previous_offset = ep->offset = ep->initial_offset;
3322 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3323 ep->previous_offset = ep->offset = ep->initial_offset;
3326 num_not_at_initial_offset = 0;
3329 /* Initialize the known label offsets.
3330 Set a known offset for each forced label to be at the initial offset
3331 of each elimination. We do this because we assume that all
3332 computed jumps occur from a location where each elimination is
3333 at its initial offset.
3334 For all other labels, show that we don't know the offsets. */
3337 set_initial_label_offsets (void)
3340 memset (offsets_known_at, 0, num_labels);
3342 for (x = forced_labels; x; x = XEXP (x, 1))
3344 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3347 /* Set all elimination offsets to the known values for the code label given
3351 set_offsets_for_label (rtx insn)
3354 int label_nr = CODE_LABEL_NUMBER (insn);
3355 struct elim_table *ep;
3357 num_not_at_initial_offset = 0;
3358 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3360 ep->offset = ep->previous_offset
3361 = offsets_at[label_nr - first_label_num][i];
3362 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3363 num_not_at_initial_offset++;
3367 /* See if anything that happened changes which eliminations are valid.
3368 For example, on the SPARC, whether or not the frame pointer can
3369 be eliminated can depend on what registers have been used. We need
3370 not check some conditions again (such as flag_omit_frame_pointer)
3371 since they can't have changed. */
3374 update_eliminables (HARD_REG_SET *pset)
3376 int previous_frame_pointer_needed = frame_pointer_needed;
3377 struct elim_table *ep;
3379 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3380 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3381 #ifdef ELIMINABLE_REGS
3382 || ! CAN_ELIMINATE (ep->from, ep->to)
3385 ep->can_eliminate = 0;
3387 /* Look for the case where we have discovered that we can't replace
3388 register A with register B and that means that we will now be
3389 trying to replace register A with register C. This means we can
3390 no longer replace register C with register B and we need to disable
3391 such an elimination, if it exists. This occurs often with A == ap,
3392 B == sp, and C == fp. */
3394 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3396 struct elim_table *op;
3399 if (! ep->can_eliminate && ep->can_eliminate_previous)
3401 /* Find the current elimination for ep->from, if there is a
3403 for (op = reg_eliminate;
3404 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3405 if (op->from == ep->from && op->can_eliminate)
3411 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3413 for (op = reg_eliminate;
3414 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3415 if (op->from == new_to && op->to == ep->to)
3416 op->can_eliminate = 0;
3420 /* See if any registers that we thought we could eliminate the previous
3421 time are no longer eliminable. If so, something has changed and we
3422 must spill the register. Also, recompute the number of eliminable
3423 registers and see if the frame pointer is needed; it is if there is
3424 no elimination of the frame pointer that we can perform. */
3426 frame_pointer_needed = 1;
3427 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3429 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3430 && ep->to != HARD_FRAME_POINTER_REGNUM)
3431 frame_pointer_needed = 0;
3433 if (! ep->can_eliminate && ep->can_eliminate_previous)
3435 ep->can_eliminate_previous = 0;
3436 SET_HARD_REG_BIT (*pset, ep->from);
3441 /* If we didn't need a frame pointer last time, but we do now, spill
3442 the hard frame pointer. */
3443 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3444 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3447 /* Initialize the table of registers to eliminate. */
3450 init_elim_table (void)
3452 struct elim_table *ep;
3453 #ifdef ELIMINABLE_REGS
3454 const struct elim_table_1 *ep1;
3458 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3460 /* Does this function require a frame pointer? */
3462 frame_pointer_needed = (! flag_omit_frame_pointer
3463 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3464 and restore sp for alloca. So we can't eliminate
3465 the frame pointer in that case. At some point,
3466 we should improve this by emitting the
3467 sp-adjusting insns for this case. */
3468 || (current_function_calls_alloca
3469 && EXIT_IGNORE_STACK)
3470 || FRAME_POINTER_REQUIRED);
3474 #ifdef ELIMINABLE_REGS
3475 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3476 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3478 ep->from = ep1->from;
3480 ep->can_eliminate = ep->can_eliminate_previous
3481 = (CAN_ELIMINATE (ep->from, ep->to)
3482 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3485 reg_eliminate[0].from = reg_eliminate_1[0].from;
3486 reg_eliminate[0].to = reg_eliminate_1[0].to;
3487 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3488 = ! frame_pointer_needed;
3491 /* Count the number of eliminable registers and build the FROM and TO
3492 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3493 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3494 We depend on this. */
3495 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3497 num_eliminable += ep->can_eliminate;
3498 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3499 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3503 /* Kick all pseudos out of hard register REGNO.
3505 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3506 because we found we can't eliminate some register. In the case, no pseudos
3507 are allowed to be in the register, even if they are only in a block that
3508 doesn't require spill registers, unlike the case when we are spilling this
3509 hard reg to produce another spill register.
3511 Return nonzero if any pseudos needed to be kicked out. */
3514 spill_hard_reg (unsigned int regno, int cant_eliminate)
3520 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3521 regs_ever_live[regno] = 1;
3524 /* Spill every pseudo reg that was allocated to this reg
3525 or to something that overlaps this reg. */
3527 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3528 if (reg_renumber[i] >= 0
3529 && (unsigned int) reg_renumber[i] <= regno
3530 && ((unsigned int) reg_renumber[i]
3531 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3532 [PSEUDO_REGNO_MODE (i)]
3534 SET_REGNO_REG_SET (&spilled_pseudos, i);
3537 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3538 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3541 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3543 IOR_HARD_REG_SET (*set1, *set2);
3546 /* After find_reload_regs has been run for all insn that need reloads,
3547 and/or spill_hard_regs was called, this function is used to actually
3548 spill pseudo registers and try to reallocate them. It also sets up the
3549 spill_regs array for use by choose_reload_regs. */
3552 finish_spills (int global)
3554 struct insn_chain *chain;
3555 int something_changed = 0;
3557 reg_set_iterator rsi;
3559 /* Build the spill_regs array for the function. */
3560 /* If there are some registers still to eliminate and one of the spill regs
3561 wasn't ever used before, additional stack space may have to be
3562 allocated to store this register. Thus, we may have changed the offset
3563 between the stack and frame pointers, so mark that something has changed.
3565 One might think that we need only set VAL to 1 if this is a call-used
3566 register. However, the set of registers that must be saved by the
3567 prologue is not identical to the call-used set. For example, the
3568 register used by the call insn for the return PC is a call-used register,
3569 but must be saved by the prologue. */
3572 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3573 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3575 spill_reg_order[i] = n_spills;
3576 spill_regs[n_spills++] = i;
3577 if (num_eliminable && ! regs_ever_live[i])
3578 something_changed = 1;
3579 regs_ever_live[i] = 1;
3582 spill_reg_order[i] = -1;
3584 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3586 /* Record the current hard register the pseudo is allocated to in
3587 pseudo_previous_regs so we avoid reallocating it to the same
3588 hard reg in a later pass. */
3589 gcc_assert (reg_renumber[i] >= 0);
3591 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3592 /* Mark it as no longer having a hard register home. */
3593 reg_renumber[i] = -1;
3594 /* We will need to scan everything again. */
3595 something_changed = 1;
3598 /* Retry global register allocation if possible. */
3601 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3602 /* For every insn that needs reloads, set the registers used as spill
3603 regs in pseudo_forbidden_regs for every pseudo live across the
3605 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3607 EXECUTE_IF_SET_IN_REG_SET
3608 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3610 ior_hard_reg_set (pseudo_forbidden_regs + i,
3611 &chain->used_spill_regs);
3613 EXECUTE_IF_SET_IN_REG_SET
3614 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3616 ior_hard_reg_set (pseudo_forbidden_regs + i,
3617 &chain->used_spill_regs);
3621 /* Retry allocating the spilled pseudos. For each reg, merge the
3622 various reg sets that indicate which hard regs can't be used,
3623 and call retry_global_alloc.
3624 We change spill_pseudos here to only contain pseudos that did not
3625 get a new hard register. */
3626 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3627 if (reg_old_renumber[i] != reg_renumber[i])
3629 HARD_REG_SET forbidden;
3630 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3631 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3632 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3633 retry_global_alloc (i, forbidden);
3634 if (reg_renumber[i] >= 0)
3635 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3639 /* Fix up the register information in the insn chain.
3640 This involves deleting those of the spilled pseudos which did not get
3641 a new hard register home from the live_{before,after} sets. */
3642 for (chain = reload_insn_chain; chain; chain = chain->next)
3644 HARD_REG_SET used_by_pseudos;
3645 HARD_REG_SET used_by_pseudos2;
3647 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3648 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3650 /* Mark any unallocated hard regs as available for spills. That
3651 makes inheritance work somewhat better. */
3652 if (chain->need_reload)
3654 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3655 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3656 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3658 /* Save the old value for the sanity test below. */
3659 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3661 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3662 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3663 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3664 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3666 /* Make sure we only enlarge the set. */
3667 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3673 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3676 int regno = reg_renumber[i];
3677 if (reg_old_renumber[i] == regno)
3680 alter_reg (i, reg_old_renumber[i]);
3681 reg_old_renumber[i] = regno;
3685 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3687 fprintf (dump_file, " Register %d now in %d.\n\n",
3688 i, reg_renumber[i]);
3692 return something_changed;
3695 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3698 scan_paradoxical_subregs (rtx x)
3702 enum rtx_code code = GET_CODE (x);
3712 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3720 if (REG_P (SUBREG_REG (x))
3721 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3722 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3723 = GET_MODE_SIZE (GET_MODE (x));
3730 fmt = GET_RTX_FORMAT (code);
3731 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3734 scan_paradoxical_subregs (XEXP (x, i));
3735 else if (fmt[i] == 'E')
3738 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3739 scan_paradoxical_subregs (XVECEXP (x, i, j));
3744 /* Reload pseudo-registers into hard regs around each insn as needed.
3745 Additional register load insns are output before the insn that needs it
3746 and perhaps store insns after insns that modify the reloaded pseudo reg.
3748 reg_last_reload_reg and reg_reloaded_contents keep track of
3749 which registers are already available in reload registers.
3750 We update these for the reloads that we perform,
3751 as the insns are scanned. */
3754 reload_as_needed (int live_known)
3756 struct insn_chain *chain;
3757 #if defined (AUTO_INC_DEC)
3762 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3763 memset (spill_reg_store, 0, sizeof spill_reg_store);
3764 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3765 reg_has_output_reload = xmalloc (max_regno);
3766 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3767 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3769 set_initial_elim_offsets ();
3771 for (chain = reload_insn_chain; chain; chain = chain->next)
3774 rtx insn = chain->insn;
3775 rtx old_next = NEXT_INSN (insn);
3777 /* If we pass a label, copy the offsets from the label information
3778 into the current offsets of each elimination. */
3780 set_offsets_for_label (insn);
3782 else if (INSN_P (insn))
3784 rtx oldpat = copy_rtx (PATTERN (insn));
3786 /* If this is a USE and CLOBBER of a MEM, ensure that any
3787 references to eliminable registers have been removed. */
3789 if ((GET_CODE (PATTERN (insn)) == USE
3790 || GET_CODE (PATTERN (insn)) == CLOBBER)
3791 && MEM_P (XEXP (PATTERN (insn), 0)))
3792 XEXP (XEXP (PATTERN (insn), 0), 0)
3793 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3794 GET_MODE (XEXP (PATTERN (insn), 0)),
3797 /* If we need to do register elimination processing, do so.
3798 This might delete the insn, in which case we are done. */
3799 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3801 eliminate_regs_in_insn (insn, 1);
3804 update_eliminable_offsets ();
3809 /* If need_elim is nonzero but need_reload is zero, one might think
3810 that we could simply set n_reloads to 0. However, find_reloads
3811 could have done some manipulation of the insn (such as swapping
3812 commutative operands), and these manipulations are lost during
3813 the first pass for every insn that needs register elimination.
3814 So the actions of find_reloads must be redone here. */
3816 if (! chain->need_elim && ! chain->need_reload
3817 && ! chain->need_operand_change)
3819 /* First find the pseudo regs that must be reloaded for this insn.
3820 This info is returned in the tables reload_... (see reload.h).
3821 Also modify the body of INSN by substituting RELOAD
3822 rtx's for those pseudo regs. */
3825 memset (reg_has_output_reload, 0, max_regno);
3826 CLEAR_HARD_REG_SET (reg_is_output_reload);
3828 find_reloads (insn, 1, spill_indirect_levels, live_known,
3834 rtx next = NEXT_INSN (insn);
3837 prev = PREV_INSN (insn);
3839 /* Now compute which reload regs to reload them into. Perhaps
3840 reusing reload regs from previous insns, or else output
3841 load insns to reload them. Maybe output store insns too.
3842 Record the choices of reload reg in reload_reg_rtx. */
3843 choose_reload_regs (chain);
3845 /* Merge any reloads that we didn't combine for fear of
3846 increasing the number of spill registers needed but now
3847 discover can be safely merged. */
3848 if (SMALL_REGISTER_CLASSES)
3849 merge_assigned_reloads (insn);
3851 /* Generate the insns to reload operands into or out of
3852 their reload regs. */
3853 emit_reload_insns (chain);
3855 /* Substitute the chosen reload regs from reload_reg_rtx
3856 into the insn's body (or perhaps into the bodies of other
3857 load and store insn that we just made for reloading
3858 and that we moved the structure into). */
3859 subst_reloads (insn);
3861 /* If this was an ASM, make sure that all the reload insns
3862 we have generated are valid. If not, give an error
3865 if (asm_noperands (PATTERN (insn)) >= 0)
3866 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3867 if (p != insn && INSN_P (p)
3868 && GET_CODE (PATTERN (p)) != USE
3869 && (recog_memoized (p) < 0
3870 || (extract_insn (p), ! constrain_operands (1))))
3872 error_for_asm (insn,
3873 "%<asm%> operand requires "
3874 "impossible reload");
3879 if (num_eliminable && chain->need_elim)
3880 update_eliminable_offsets ();
3882 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3883 is no longer validly lying around to save a future reload.
3884 Note that this does not detect pseudos that were reloaded
3885 for this insn in order to be stored in
3886 (obeying register constraints). That is correct; such reload
3887 registers ARE still valid. */
3888 note_stores (oldpat, forget_old_reloads_1, NULL);
3890 /* There may have been CLOBBER insns placed after INSN. So scan
3891 between INSN and NEXT and use them to forget old reloads. */
3892 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3893 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3894 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3897 /* Likewise for regs altered by auto-increment in this insn.
3898 REG_INC notes have been changed by reloading:
3899 find_reloads_address_1 records substitutions for them,
3900 which have been performed by subst_reloads above. */
3901 for (i = n_reloads - 1; i >= 0; i--)
3903 rtx in_reg = rld[i].in_reg;
3906 enum rtx_code code = GET_CODE (in_reg);
3907 /* PRE_INC / PRE_DEC will have the reload register ending up
3908 with the same value as the stack slot, but that doesn't
3909 hold true for POST_INC / POST_DEC. Either we have to
3910 convert the memory access to a true POST_INC / POST_DEC,
3911 or we can't use the reload register for inheritance. */
3912 if ((code == POST_INC || code == POST_DEC)
3913 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3914 REGNO (rld[i].reg_rtx))
3915 /* Make sure it is the inc/dec pseudo, and not
3916 some other (e.g. output operand) pseudo. */
3917 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3918 == REGNO (XEXP (in_reg, 0))))
3921 rtx reload_reg = rld[i].reg_rtx;
3922 enum machine_mode mode = GET_MODE (reload_reg);
3926 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3928 /* We really want to ignore REG_INC notes here, so
3929 use PATTERN (p) as argument to reg_set_p . */
3930 if (reg_set_p (reload_reg, PATTERN (p)))
3932 n = count_occurrences (PATTERN (p), reload_reg, 0);
3937 n = validate_replace_rtx (reload_reg,
3938 gen_rtx_fmt_e (code,
3943 /* We must also verify that the constraints
3944 are met after the replacement. */
3947 n = constrain_operands (1);
3951 /* If the constraints were not met, then
3952 undo the replacement. */
3955 validate_replace_rtx (gen_rtx_fmt_e (code,
3968 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3970 /* Mark this as having an output reload so that the
3971 REG_INC processing code below won't invalidate
3972 the reload for inheritance. */
3973 SET_HARD_REG_BIT (reg_is_output_reload,
3974 REGNO (reload_reg));
3975 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3978 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3981 else if ((code == PRE_INC || code == PRE_DEC)
3982 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3983 REGNO (rld[i].reg_rtx))
3984 /* Make sure it is the inc/dec pseudo, and not
3985 some other (e.g. output operand) pseudo. */
3986 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3987 == REGNO (XEXP (in_reg, 0))))
3989 SET_HARD_REG_BIT (reg_is_output_reload,
3990 REGNO (rld[i].reg_rtx));
3991 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3995 /* If a pseudo that got a hard register is auto-incremented,
3996 we must purge records of copying it into pseudos without
3998 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3999 if (REG_NOTE_KIND (x) == REG_INC)
4001 /* See if this pseudo reg was reloaded in this insn.
4002 If so, its last-reload info is still valid
4003 because it is based on this insn's reload. */
4004 for (i = 0; i < n_reloads; i++)
4005 if (rld[i].out == XEXP (x, 0))
4009 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4013 /* A reload reg's contents are unknown after a label. */
4015 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4017 /* Don't assume a reload reg is still good after a call insn
4018 if it is a call-used reg, or if it contains a value that will
4019 be partially clobbered by the call. */
4020 else if (CALL_P (insn))
4022 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4023 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4028 free (reg_last_reload_reg);
4029 free (reg_has_output_reload);
4032 /* Discard all record of any value reloaded from X,
4033 or reloaded in X from someplace else;
4034 unless X is an output reload reg of the current insn.
4036 X may be a hard reg (the reload reg)
4037 or it may be a pseudo reg that was reloaded from. */
4040 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4041 void *data ATTRIBUTE_UNUSED)
4046 /* note_stores does give us subregs of hard regs,
4047 subreg_regno_offset will abort if it is not a hard reg. */
4048 while (GET_CODE (x) == SUBREG)
4050 /* We ignore the subreg offset when calculating the regno,
4051 because we are using the entire underlying hard register
4061 if (regno >= FIRST_PSEUDO_REGISTER)
4067 nr = hard_regno_nregs[regno][GET_MODE (x)];
4068 /* Storing into a spilled-reg invalidates its contents.
4069 This can happen if a block-local pseudo is allocated to that reg
4070 and it wasn't spilled because this block's total need is 0.
4071 Then some insn might have an optional reload and use this reg. */
4072 for (i = 0; i < nr; i++)
4073 /* But don't do this if the reg actually serves as an output
4074 reload reg in the current instruction. */
4076 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4078 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4079 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4080 spill_reg_store[regno + i] = 0;
4084 /* Since value of X has changed,
4085 forget any value previously copied from it. */
4088 /* But don't forget a copy if this is the output reload
4089 that establishes the copy's validity. */
4090 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4091 reg_last_reload_reg[regno + nr] = 0;
4094 /* The following HARD_REG_SETs indicate when each hard register is
4095 used for a reload of various parts of the current insn. */
4097 /* If reg is unavailable for all reloads. */
4098 static HARD_REG_SET reload_reg_unavailable;
4099 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4100 static HARD_REG_SET reload_reg_used;
4101 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4102 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4103 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4104 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4105 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4106 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4107 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4108 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4109 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4110 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4111 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4112 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4113 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4114 static HARD_REG_SET reload_reg_used_in_op_addr;
4115 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4116 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4117 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4118 static HARD_REG_SET reload_reg_used_in_insn;
4119 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4120 static HARD_REG_SET reload_reg_used_in_other_addr;
4122 /* If reg is in use as a reload reg for any sort of reload. */
4123 static HARD_REG_SET reload_reg_used_at_all;
4125 /* If reg is use as an inherited reload. We just mark the first register
4127 static HARD_REG_SET reload_reg_used_for_inherit;
4129 /* Records which hard regs are used in any way, either as explicit use or
4130 by being allocated to a pseudo during any point of the current insn. */
4131 static HARD_REG_SET reg_used_in_insn;
4133 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4134 TYPE. MODE is used to indicate how many consecutive regs are
4138 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4139 enum machine_mode mode)
4141 unsigned int nregs = hard_regno_nregs[regno][mode];
4144 for (i = regno; i < nregs + regno; i++)
4149 SET_HARD_REG_BIT (reload_reg_used, i);
4152 case RELOAD_FOR_INPUT_ADDRESS:
4153 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4156 case RELOAD_FOR_INPADDR_ADDRESS:
4157 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4160 case RELOAD_FOR_OUTPUT_ADDRESS:
4161 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4164 case RELOAD_FOR_OUTADDR_ADDRESS:
4165 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4168 case RELOAD_FOR_OPERAND_ADDRESS:
4169 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4172 case RELOAD_FOR_OPADDR_ADDR:
4173 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4176 case RELOAD_FOR_OTHER_ADDRESS:
4177 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4180 case RELOAD_FOR_INPUT:
4181 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4184 case RELOAD_FOR_OUTPUT:
4185 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4188 case RELOAD_FOR_INSN:
4189 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4193 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4197 /* Similarly, but show REGNO is no longer in use for a reload. */
4200 clear_reload_reg_in_use (unsigned int regno, int opnum,
4201 enum reload_type type, enum machine_mode mode)
4203 unsigned int nregs = hard_regno_nregs[regno][mode];
4204 unsigned int start_regno, end_regno, r;
4206 /* A complication is that for some reload types, inheritance might
4207 allow multiple reloads of the same types to share a reload register.
4208 We set check_opnum if we have to check only reloads with the same
4209 operand number, and check_any if we have to check all reloads. */
4210 int check_opnum = 0;
4212 HARD_REG_SET *used_in_set;
4217 used_in_set = &reload_reg_used;
4220 case RELOAD_FOR_INPUT_ADDRESS:
4221 used_in_set = &reload_reg_used_in_input_addr[opnum];
4224 case RELOAD_FOR_INPADDR_ADDRESS:
4226 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4229 case RELOAD_FOR_OUTPUT_ADDRESS:
4230 used_in_set = &reload_reg_used_in_output_addr[opnum];
4233 case RELOAD_FOR_OUTADDR_ADDRESS:
4235 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4238 case RELOAD_FOR_OPERAND_ADDRESS:
4239 used_in_set = &reload_reg_used_in_op_addr;
4242 case RELOAD_FOR_OPADDR_ADDR:
4244 used_in_set = &reload_reg_used_in_op_addr_reload;
4247 case RELOAD_FOR_OTHER_ADDRESS:
4248 used_in_set = &reload_reg_used_in_other_addr;
4252 case RELOAD_FOR_INPUT:
4253 used_in_set = &reload_reg_used_in_input[opnum];
4256 case RELOAD_FOR_OUTPUT:
4257 used_in_set = &reload_reg_used_in_output[opnum];
4260 case RELOAD_FOR_INSN:
4261 used_in_set = &reload_reg_used_in_insn;
4266 /* We resolve conflicts with remaining reloads of the same type by
4267 excluding the intervals of reload registers by them from the
4268 interval of freed reload registers. Since we only keep track of
4269 one set of interval bounds, we might have to exclude somewhat
4270 more than what would be necessary if we used a HARD_REG_SET here.
4271 But this should only happen very infrequently, so there should
4272 be no reason to worry about it. */
4274 start_regno = regno;
4275 end_regno = regno + nregs;
4276 if (check_opnum || check_any)
4278 for (i = n_reloads - 1; i >= 0; i--)
4280 if (rld[i].when_needed == type
4281 && (check_any || rld[i].opnum == opnum)
4284 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4285 unsigned int conflict_end
4287 + hard_regno_nregs[conflict_start][rld[i].mode]);
4289 /* If there is an overlap with the first to-be-freed register,
4290 adjust the interval start. */
4291 if (conflict_start <= start_regno && conflict_end > start_regno)
4292 start_regno = conflict_end;
4293 /* Otherwise, if there is a conflict with one of the other
4294 to-be-freed registers, adjust the interval end. */
4295 if (conflict_start > start_regno && conflict_start < end_regno)
4296 end_regno = conflict_start;
4301 for (r = start_regno; r < end_regno; r++)
4302 CLEAR_HARD_REG_BIT (*used_in_set, r);
4305 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4306 specified by OPNUM and TYPE. */
4309 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4313 /* In use for a RELOAD_OTHER means it's not available for anything. */
4314 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4315 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4321 /* In use for anything means we can't use it for RELOAD_OTHER. */
4322 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4323 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4324 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4325 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4328 for (i = 0; i < reload_n_operands; i++)
4329 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4330 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4331 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4332 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4333 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4334 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4339 case RELOAD_FOR_INPUT:
4340 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4341 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4344 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4347 /* If it is used for some other input, can't use it. */
4348 for (i = 0; i < reload_n_operands; i++)
4349 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4352 /* If it is used in a later operand's address, can't use it. */
4353 for (i = opnum + 1; i < reload_n_operands; i++)
4354 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4355 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4360 case RELOAD_FOR_INPUT_ADDRESS:
4361 /* Can't use a register if it is used for an input address for this
4362 operand or used as an input in an earlier one. */
4363 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4364 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4367 for (i = 0; i < opnum; i++)
4368 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4373 case RELOAD_FOR_INPADDR_ADDRESS:
4374 /* Can't use a register if it is used for an input address
4375 for this operand or used as an input in an earlier
4377 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4380 for (i = 0; i < opnum; i++)
4381 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4386 case RELOAD_FOR_OUTPUT_ADDRESS:
4387 /* Can't use a register if it is used for an output address for this
4388 operand or used as an output in this or a later operand. Note
4389 that multiple output operands are emitted in reverse order, so
4390 the conflicting ones are those with lower indices. */
4391 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4394 for (i = 0; i <= opnum; i++)
4395 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4400 case RELOAD_FOR_OUTADDR_ADDRESS:
4401 /* Can't use a register if it is used for an output address
4402 for this operand or used as an output in this or a
4403 later operand. Note that multiple output operands are
4404 emitted in reverse order, so the conflicting ones are
4405 those with lower indices. */
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4409 for (i = 0; i <= opnum; i++)
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4415 case RELOAD_FOR_OPERAND_ADDRESS:
4416 for (i = 0; i < reload_n_operands; i++)
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4420 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4421 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4423 case RELOAD_FOR_OPADDR_ADDR:
4424 for (i = 0; i < reload_n_operands; i++)
4425 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4428 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4430 case RELOAD_FOR_OUTPUT:
4431 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4432 outputs, or an operand address for this or an earlier output.
4433 Note that multiple output operands are emitted in reverse order,
4434 so the conflicting ones are those with higher indices. */
4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4438 for (i = 0; i < reload_n_operands; i++)
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4442 for (i = opnum; i < reload_n_operands; i++)
4443 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4449 case RELOAD_FOR_INSN:
4450 for (i = 0; i < reload_n_operands; i++)
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4452 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4455 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4456 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4458 case RELOAD_FOR_OTHER_ADDRESS:
4459 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4466 /* Return 1 if the value in reload reg REGNO, as used by a reload
4467 needed for the part of the insn specified by OPNUM and TYPE,
4468 is still available in REGNO at the end of the insn.
4470 We can assume that the reload reg was already tested for availability
4471 at the time it is needed, and we should not check this again,
4472 in case the reg has already been marked in use. */
4475 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4482 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4483 its value must reach the end. */
4486 /* If this use is for part of the insn,
4487 its value reaches if no subsequent part uses the same register.
4488 Just like the above function, don't try to do this with lots
4491 case RELOAD_FOR_OTHER_ADDRESS:
4492 /* Here we check for everything else, since these don't conflict
4493 with anything else and everything comes later. */
4495 for (i = 0; i < reload_n_operands; i++)
4496 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4497 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4498 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4499 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4500 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4501 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4504 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4505 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4506 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4507 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4509 case RELOAD_FOR_INPUT_ADDRESS:
4510 case RELOAD_FOR_INPADDR_ADDRESS:
4511 /* Similar, except that we check only for this and subsequent inputs
4512 and the address of only subsequent inputs and we do not need
4513 to check for RELOAD_OTHER objects since they are known not to
4516 for (i = opnum; i < reload_n_operands; i++)
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4520 for (i = opnum + 1; i < reload_n_operands; i++)
4521 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4522 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4525 for (i = 0; i < reload_n_operands; i++)
4526 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4527 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4528 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4531 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4534 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4535 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4536 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4538 case RELOAD_FOR_INPUT:
4539 /* Similar to input address, except we start at the next operand for
4540 both input and input address and we do not check for
4541 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4544 for (i = opnum + 1; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4547 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4550 /* ... fall through ... */
4552 case RELOAD_FOR_OPERAND_ADDRESS:
4553 /* Check outputs and their addresses. */
4555 for (i = 0; i < reload_n_operands; i++)
4556 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4557 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4558 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4561 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4563 case RELOAD_FOR_OPADDR_ADDR:
4564 for (i = 0; i < reload_n_operands; i++)
4565 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4566 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4567 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4570 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4571 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4572 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4574 case RELOAD_FOR_INSN:
4575 /* These conflict with other outputs with RELOAD_OTHER. So
4576 we need only check for output addresses. */
4578 opnum = reload_n_operands;
4580 /* ... fall through ... */
4582 case RELOAD_FOR_OUTPUT:
4583 case RELOAD_FOR_OUTPUT_ADDRESS:
4584 case RELOAD_FOR_OUTADDR_ADDRESS:
4585 /* We already know these can't conflict with a later output. So the
4586 only thing to check are later output addresses.
4587 Note that multiple output operands are emitted in reverse order,
4588 so the conflicting ones are those with lower indices. */
4589 for (i = 0; i < opnum; i++)
4590 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4591 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4601 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4604 This function uses the same algorithm as reload_reg_free_p above. */
4607 reloads_conflict (int r1, int r2)
4609 enum reload_type r1_type = rld[r1].when_needed;
4610 enum reload_type r2_type = rld[r2].when_needed;
4611 int r1_opnum = rld[r1].opnum;
4612 int r2_opnum = rld[r2].opnum;
4614 /* RELOAD_OTHER conflicts with everything. */
4615 if (r2_type == RELOAD_OTHER)
4618 /* Otherwise, check conflicts differently for each type. */
4622 case RELOAD_FOR_INPUT:
4623 return (r2_type == RELOAD_FOR_INSN
4624 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4625 || r2_type == RELOAD_FOR_OPADDR_ADDR
4626 || r2_type == RELOAD_FOR_INPUT
4627 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4628 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4629 && r2_opnum > r1_opnum));
4631 case RELOAD_FOR_INPUT_ADDRESS:
4632 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4633 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4635 case RELOAD_FOR_INPADDR_ADDRESS:
4636 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4637 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4639 case RELOAD_FOR_OUTPUT_ADDRESS:
4640 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4641 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4643 case RELOAD_FOR_OUTADDR_ADDRESS:
4644 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4645 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4647 case RELOAD_FOR_OPERAND_ADDRESS:
4648 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4649 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4651 case RELOAD_FOR_OPADDR_ADDR:
4652 return (r2_type == RELOAD_FOR_INPUT
4653 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4655 case RELOAD_FOR_OUTPUT:
4656 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4657 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4658 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4659 && r2_opnum >= r1_opnum));
4661 case RELOAD_FOR_INSN:
4662 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4663 || r2_type == RELOAD_FOR_INSN
4664 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4666 case RELOAD_FOR_OTHER_ADDRESS:
4667 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4677 /* Indexed by reload number, 1 if incoming value
4678 inherited from previous insns. */
4679 char reload_inherited[MAX_RELOADS];
4681 /* For an inherited reload, this is the insn the reload was inherited from,
4682 if we know it. Otherwise, this is 0. */
4683 rtx reload_inheritance_insn[MAX_RELOADS];
4685 /* If nonzero, this is a place to get the value of the reload,
4686 rather than using reload_in. */
4687 rtx reload_override_in[MAX_RELOADS];
4689 /* For each reload, the hard register number of the register used,
4690 or -1 if we did not need a register for this reload. */
4691 int reload_spill_index[MAX_RELOADS];
4693 /* Subroutine of free_for_value_p, used to check a single register.
4694 START_REGNO is the starting regno of the full reload register
4695 (possibly comprising multiple hard registers) that we are considering. */
4698 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4699 enum reload_type type, rtx value, rtx out,
4700 int reloadnum, int ignore_address_reloads)
4703 /* Set if we see an input reload that must not share its reload register
4704 with any new earlyclobber, but might otherwise share the reload
4705 register with an output or input-output reload. */
4706 int check_earlyclobber = 0;
4710 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4713 if (out == const0_rtx)
4719 /* We use some pseudo 'time' value to check if the lifetimes of the
4720 new register use would overlap with the one of a previous reload
4721 that is not read-only or uses a different value.
4722 The 'time' used doesn't have to be linear in any shape or form, just
4724 Some reload types use different 'buckets' for each operand.
4725 So there are MAX_RECOG_OPERANDS different time values for each
4727 We compute TIME1 as the time when the register for the prospective
4728 new reload ceases to be live, and TIME2 for each existing
4729 reload as the time when that the reload register of that reload
4731 Where there is little to be gained by exact lifetime calculations,
4732 we just make conservative assumptions, i.e. a longer lifetime;
4733 this is done in the 'default:' cases. */
4736 case RELOAD_FOR_OTHER_ADDRESS:
4737 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4738 time1 = copy ? 0 : 1;
4741 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4743 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4744 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4745 respectively, to the time values for these, we get distinct time
4746 values. To get distinct time values for each operand, we have to
4747 multiply opnum by at least three. We round that up to four because
4748 multiply by four is often cheaper. */
4749 case RELOAD_FOR_INPADDR_ADDRESS:
4750 time1 = opnum * 4 + 2;
4752 case RELOAD_FOR_INPUT_ADDRESS:
4753 time1 = opnum * 4 + 3;
4755 case RELOAD_FOR_INPUT:
4756 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4757 executes (inclusive). */
4758 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4760 case RELOAD_FOR_OPADDR_ADDR:
4762 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4763 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4765 case RELOAD_FOR_OPERAND_ADDRESS:
4766 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4768 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4770 case RELOAD_FOR_OUTADDR_ADDRESS:
4771 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4773 case RELOAD_FOR_OUTPUT_ADDRESS:
4774 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4777 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4780 for (i = 0; i < n_reloads; i++)
4782 rtx reg = rld[i].reg_rtx;
4783 if (reg && REG_P (reg)
4784 && ((unsigned) regno - true_regnum (reg)
4785 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4788 rtx other_input = rld[i].in;
4790 /* If the other reload loads the same input value, that
4791 will not cause a conflict only if it's loading it into
4792 the same register. */
4793 if (true_regnum (reg) != start_regno)
4794 other_input = NULL_RTX;
4795 if (! other_input || ! rtx_equal_p (other_input, value)
4796 || rld[i].out || out)
4799 switch (rld[i].when_needed)
4801 case RELOAD_FOR_OTHER_ADDRESS:
4804 case RELOAD_FOR_INPADDR_ADDRESS:
4805 /* find_reloads makes sure that a
4806 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4807 by at most one - the first -
4808 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4809 address reload is inherited, the address address reload
4810 goes away, so we can ignore this conflict. */
4811 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4812 && ignore_address_reloads
4813 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4814 Then the address address is still needed to store
4815 back the new address. */
4816 && ! rld[reloadnum].out)
4818 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4819 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4821 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4822 && ignore_address_reloads
4823 /* Unless we are reloading an auto_inc expression. */
4824 && ! rld[reloadnum].out)
4826 time2 = rld[i].opnum * 4 + 2;
4828 case RELOAD_FOR_INPUT_ADDRESS:
4829 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4830 && ignore_address_reloads
4831 && ! rld[reloadnum].out)
4833 time2 = rld[i].opnum * 4 + 3;
4835 case RELOAD_FOR_INPUT:
4836 time2 = rld[i].opnum * 4 + 4;
4837 check_earlyclobber = 1;
4839 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4840 == MAX_RECOG_OPERAND * 4 */
4841 case RELOAD_FOR_OPADDR_ADDR:
4842 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4843 && ignore_address_reloads
4844 && ! rld[reloadnum].out)
4846 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4848 case RELOAD_FOR_OPERAND_ADDRESS:
4849 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4850 check_earlyclobber = 1;
4852 case RELOAD_FOR_INSN:
4853 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4855 case RELOAD_FOR_OUTPUT:
4856 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4857 instruction is executed. */
4858 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4860 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4861 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4863 case RELOAD_FOR_OUTADDR_ADDRESS:
4864 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4865 && ignore_address_reloads
4866 && ! rld[reloadnum].out)
4868 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4870 case RELOAD_FOR_OUTPUT_ADDRESS:
4871 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4874 /* If there is no conflict in the input part, handle this
4875 like an output reload. */
4876 if (! rld[i].in || rtx_equal_p (other_input, value))
4878 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4879 /* Earlyclobbered outputs must conflict with inputs. */
4880 if (earlyclobber_operand_p (rld[i].out))
4881 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4886 /* RELOAD_OTHER might be live beyond instruction execution,
4887 but this is not obvious when we set time2 = 1. So check
4888 here if there might be a problem with the new reload
4889 clobbering the register used by the RELOAD_OTHER. */
4897 && (! rld[i].in || rld[i].out
4898 || ! rtx_equal_p (other_input, value)))
4899 || (out && rld[reloadnum].out_reg
4900 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4906 /* Earlyclobbered outputs must conflict with inputs. */
4907 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4913 /* Return 1 if the value in reload reg REGNO, as used by a reload
4914 needed for the part of the insn specified by OPNUM and TYPE,
4915 may be used to load VALUE into it.
4917 MODE is the mode in which the register is used, this is needed to
4918 determine how many hard regs to test.
4920 Other read-only reloads with the same value do not conflict
4921 unless OUT is nonzero and these other reloads have to live while
4922 output reloads live.
4923 If OUT is CONST0_RTX, this is a special case: it means that the
4924 test should not be for using register REGNO as reload register, but
4925 for copying from register REGNO into the reload register.
4927 RELOADNUM is the number of the reload we want to load this value for;
4928 a reload does not conflict with itself.
4930 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4931 reloads that load an address for the very reload we are considering.
4933 The caller has to make sure that there is no conflict with the return
4937 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4938 enum reload_type type, rtx value, rtx out, int reloadnum,
4939 int ignore_address_reloads)
4941 int nregs = hard_regno_nregs[regno][mode];
4943 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4944 value, out, reloadnum,
4945 ignore_address_reloads))
4950 /* Return nonzero if the rtx X is invariant over the current function. */
4951 /* ??? Actually, the places where we use this expect exactly what
4952 * is tested here, and not everything that is function invariant. In
4953 * particular, the frame pointer and arg pointer are special cased;
4954 * pic_offset_table_rtx is not, and this will cause aborts when we
4955 * go to spill these things to memory. */
4958 function_invariant_p (rtx x)
4962 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4964 if (GET_CODE (x) == PLUS
4965 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4966 && CONSTANT_P (XEXP (x, 1)))
4971 /* Determine whether the reload reg X overlaps any rtx'es used for
4972 overriding inheritance. Return nonzero if so. */
4975 conflicts_with_override (rtx x)
4978 for (i = 0; i < n_reloads; i++)
4979 if (reload_override_in[i]
4980 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4985 /* Give an error message saying we failed to find a reload for INSN,
4986 and clear out reload R. */
4988 failed_reload (rtx insn, int r)
4990 if (asm_noperands (PATTERN (insn)) < 0)
4991 /* It's the compiler's fault. */
4992 fatal_insn ("could not find a spill register", insn);
4994 /* It's the user's fault; the operand's mode and constraint
4995 don't match. Disable this reload so we don't crash in final. */
4996 error_for_asm (insn,
4997 "%<asm%> operand constraint incompatible with operand size");
5001 rld[r].optional = 1;
5002 rld[r].secondary_p = 1;
5005 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5006 for reload R. If it's valid, get an rtx for it. Return nonzero if
5009 set_reload_reg (int i, int r)
5012 rtx reg = spill_reg_rtx[i];
5014 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5015 spill_reg_rtx[i] = reg
5016 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5018 regno = true_regnum (reg);
5020 /* Detect when the reload reg can't hold the reload mode.
5021 This used to be one `if', but Sequent compiler can't handle that. */
5022 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5024 enum machine_mode test_mode = VOIDmode;
5026 test_mode = GET_MODE (rld[r].in);
5027 /* If rld[r].in has VOIDmode, it means we will load it
5028 in whatever mode the reload reg has: to wit, rld[r].mode.
5029 We have already tested that for validity. */
5030 /* Aside from that, we need to test that the expressions
5031 to reload from or into have modes which are valid for this
5032 reload register. Otherwise the reload insns would be invalid. */
5033 if (! (rld[r].in != 0 && test_mode != VOIDmode
5034 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5035 if (! (rld[r].out != 0
5036 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5038 /* The reg is OK. */
5041 /* Mark as in use for this insn the reload regs we use
5043 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5044 rld[r].when_needed, rld[r].mode);
5046 rld[r].reg_rtx = reg;
5047 reload_spill_index[r] = spill_regs[i];
5054 /* Find a spill register to use as a reload register for reload R.
5055 LAST_RELOAD is nonzero if this is the last reload for the insn being
5058 Set rld[R].reg_rtx to the register allocated.
5060 We return 1 if successful, or 0 if we couldn't find a spill reg and
5061 we didn't change anything. */
5064 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5069 /* If we put this reload ahead, thinking it is a group,
5070 then insist on finding a group. Otherwise we can grab a
5071 reg that some other reload needs.
5072 (That can happen when we have a 68000 DATA_OR_FP_REG
5073 which is a group of data regs or one fp reg.)
5074 We need not be so restrictive if there are no more reloads
5077 ??? Really it would be nicer to have smarter handling
5078 for that kind of reg class, where a problem like this is normal.
5079 Perhaps those classes should be avoided for reloading
5080 by use of more alternatives. */
5082 int force_group = rld[r].nregs > 1 && ! last_reload;
5084 /* If we want a single register and haven't yet found one,
5085 take any reg in the right class and not in use.
5086 If we want a consecutive group, here is where we look for it.
5088 We use two passes so we can first look for reload regs to
5089 reuse, which are already in use for other reloads in this insn,
5090 and only then use additional registers.
5091 I think that maximizing reuse is needed to make sure we don't
5092 run out of reload regs. Suppose we have three reloads, and
5093 reloads A and B can share regs. These need two regs.
5094 Suppose A and B are given different regs.
5095 That leaves none for C. */
5096 for (pass = 0; pass < 2; pass++)
5098 /* I is the index in spill_regs.
5099 We advance it round-robin between insns to use all spill regs
5100 equally, so that inherited reloads have a chance
5101 of leapfrogging each other. */
5105 for (count = 0; count < n_spills; count++)
5107 int class = (int) rld[r].class;
5113 regnum = spill_regs[i];
5115 if ((reload_reg_free_p (regnum, rld[r].opnum,
5118 /* We check reload_reg_used to make sure we
5119 don't clobber the return register. */
5120 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5121 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5122 rld[r].when_needed, rld[r].in,
5124 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5125 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5126 /* Look first for regs to share, then for unshared. But
5127 don't share regs used for inherited reloads; they are
5128 the ones we want to preserve. */
5130 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5132 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5135 int nr = hard_regno_nregs[regnum][rld[r].mode];
5136 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5137 (on 68000) got us two FP regs. If NR is 1,
5138 we would reject both of them. */
5141 /* If we need only one reg, we have already won. */
5144 /* But reject a single reg if we demand a group. */
5149 /* Otherwise check that as many consecutive regs as we need
5150 are available here. */
5153 int regno = regnum + nr - 1;
5154 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5155 && spill_reg_order[regno] >= 0
5156 && reload_reg_free_p (regno, rld[r].opnum,
5157 rld[r].when_needed)))
5166 /* If we found something on pass 1, omit pass 2. */
5167 if (count < n_spills)
5171 /* We should have found a spill register by now. */
5172 if (count >= n_spills)
5175 /* I is the index in SPILL_REG_RTX of the reload register we are to
5176 allocate. Get an rtx for it and find its register number. */
5178 return set_reload_reg (i, r);
5181 /* Initialize all the tables needed to allocate reload registers.
5182 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5183 is the array we use to restore the reg_rtx field for every reload. */
5186 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5190 for (i = 0; i < n_reloads; i++)
5191 rld[i].reg_rtx = save_reload_reg_rtx[i];
5193 memset (reload_inherited, 0, MAX_RELOADS);
5194 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5195 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5197 CLEAR_HARD_REG_SET (reload_reg_used);
5198 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5199 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5200 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5201 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5202 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5204 CLEAR_HARD_REG_SET (reg_used_in_insn);
5207 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5208 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5209 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5210 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5211 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5212 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5215 for (i = 0; i < reload_n_operands; i++)
5217 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5218 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5219 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5220 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5221 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5222 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5225 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5227 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5229 for (i = 0; i < n_reloads; i++)
5230 /* If we have already decided to use a certain register,
5231 don't use it in another way. */
5233 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5234 rld[i].when_needed, rld[i].mode);
5237 /* Assign hard reg targets for the pseudo-registers we must reload
5238 into hard regs for this insn.
5239 Also output the instructions to copy them in and out of the hard regs.
5241 For machines with register classes, we are responsible for
5242 finding a reload reg in the proper class. */
5245 choose_reload_regs (struct insn_chain *chain)
5247 rtx insn = chain->insn;
5249 unsigned int max_group_size = 1;
5250 enum reg_class group_class = NO_REGS;
5251 int pass, win, inheritance;
5253 rtx save_reload_reg_rtx[MAX_RELOADS];
5255 /* In order to be certain of getting the registers we need,
5256 we must sort the reloads into order of increasing register class.
5257 Then our grabbing of reload registers will parallel the process
5258 that provided the reload registers.
5260 Also note whether any of the reloads wants a consecutive group of regs.
5261 If so, record the maximum size of the group desired and what
5262 register class contains all the groups needed by this insn. */
5264 for (j = 0; j < n_reloads; j++)
5266 reload_order[j] = j;
5267 reload_spill_index[j] = -1;
5269 if (rld[j].nregs > 1)
5271 max_group_size = MAX (rld[j].nregs, max_group_size);
5273 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5276 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5280 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5282 /* If -O, try first with inheritance, then turning it off.
5283 If not -O, don't do inheritance.
5284 Using inheritance when not optimizing leads to paradoxes
5285 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5286 because one side of the comparison might be inherited. */
5288 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5290 choose_reload_regs_init (chain, save_reload_reg_rtx);
5292 /* Process the reloads in order of preference just found.
5293 Beyond this point, subregs can be found in reload_reg_rtx.
5295 This used to look for an existing reloaded home for all of the
5296 reloads, and only then perform any new reloads. But that could lose
5297 if the reloads were done out of reg-class order because a later
5298 reload with a looser constraint might have an old home in a register
5299 needed by an earlier reload with a tighter constraint.
5301 To solve this, we make two passes over the reloads, in the order
5302 described above. In the first pass we try to inherit a reload
5303 from a previous insn. If there is a later reload that needs a
5304 class that is a proper subset of the class being processed, we must
5305 also allocate a spill register during the first pass.
5307 Then make a second pass over the reloads to allocate any reloads
5308 that haven't been given registers yet. */
5310 for (j = 0; j < n_reloads; j++)
5312 int r = reload_order[j];
5313 rtx search_equiv = NULL_RTX;
5315 /* Ignore reloads that got marked inoperative. */
5316 if (rld[r].out == 0 && rld[r].in == 0
5317 && ! rld[r].secondary_p)
5320 /* If find_reloads chose to use reload_in or reload_out as a reload
5321 register, we don't need to chose one. Otherwise, try even if it
5322 found one since we might save an insn if we find the value lying
5324 Try also when reload_in is a pseudo without a hard reg. */
5325 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5326 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5327 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5328 && !MEM_P (rld[r].in)
5329 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5332 #if 0 /* No longer needed for correct operation.
5333 It might give better code, or might not; worth an experiment? */
5334 /* If this is an optional reload, we can't inherit from earlier insns
5335 until we are sure that any non-optional reloads have been allocated.
5336 The following code takes advantage of the fact that optional reloads
5337 are at the end of reload_order. */
5338 if (rld[r].optional != 0)
5339 for (i = 0; i < j; i++)
5340 if ((rld[reload_order[i]].out != 0
5341 || rld[reload_order[i]].in != 0
5342 || rld[reload_order[i]].secondary_p)
5343 && ! rld[reload_order[i]].optional
5344 && rld[reload_order[i]].reg_rtx == 0)
5345 allocate_reload_reg (chain, reload_order[i], 0);
5348 /* First see if this pseudo is already available as reloaded
5349 for a previous insn. We cannot try to inherit for reloads
5350 that are smaller than the maximum number of registers needed
5351 for groups unless the register we would allocate cannot be used
5354 We could check here to see if this is a secondary reload for
5355 an object that is already in a register of the desired class.
5356 This would avoid the need for the secondary reload register.
5357 But this is complex because we can't easily determine what
5358 objects might want to be loaded via this reload. So let a
5359 register be allocated here. In `emit_reload_insns' we suppress
5360 one of the loads in the case described above. */
5366 enum machine_mode mode = VOIDmode;
5370 else if (REG_P (rld[r].in))
5372 regno = REGNO (rld[r].in);
5373 mode = GET_MODE (rld[r].in);
5375 else if (REG_P (rld[r].in_reg))
5377 regno = REGNO (rld[r].in_reg);
5378 mode = GET_MODE (rld[r].in_reg);
5380 else if (GET_CODE (rld[r].in_reg) == SUBREG
5381 && REG_P (SUBREG_REG (rld[r].in_reg)))
5383 byte = SUBREG_BYTE (rld[r].in_reg);
5384 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5385 if (regno < FIRST_PSEUDO_REGISTER)
5386 regno = subreg_regno (rld[r].in_reg);
5387 mode = GET_MODE (rld[r].in_reg);
5390 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5391 || GET_CODE (rld[r].in_reg) == PRE_DEC
5392 || GET_CODE (rld[r].in_reg) == POST_INC
5393 || GET_CODE (rld[r].in_reg) == POST_DEC)
5394 && REG_P (XEXP (rld[r].in_reg, 0)))
5396 regno = REGNO (XEXP (rld[r].in_reg, 0));
5397 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5398 rld[r].out = rld[r].in;
5402 /* This won't work, since REGNO can be a pseudo reg number.
5403 Also, it takes much more hair to keep track of all the things
5404 that can invalidate an inherited reload of part of a pseudoreg. */
5405 else if (GET_CODE (rld[r].in) == SUBREG
5406 && REG_P (SUBREG_REG (rld[r].in)))
5407 regno = subreg_regno (rld[r].in);
5410 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5412 enum reg_class class = rld[r].class, last_class;
5413 rtx last_reg = reg_last_reload_reg[regno];
5414 enum machine_mode need_mode;
5416 i = REGNO (last_reg);
5417 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5418 last_class = REGNO_REG_CLASS (i);
5424 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5425 GET_MODE_CLASS (mode));
5428 #ifdef CANNOT_CHANGE_MODE_CLASS
5429 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5433 (GET_MODE_SIZE (GET_MODE (last_reg))
5434 >= GET_MODE_SIZE (need_mode))
5435 #ifdef CANNOT_CHANGE_MODE_CLASS
5438 && reg_reloaded_contents[i] == regno
5439 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5440 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5441 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5442 /* Even if we can't use this register as a reload
5443 register, we might use it for reload_override_in,
5444 if copying it to the desired class is cheap
5446 || ((REGISTER_MOVE_COST (mode, last_class, class)
5447 < MEMORY_MOVE_COST (mode, class, 1))
5448 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5449 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5453 #ifdef SECONDARY_MEMORY_NEEDED
5454 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5459 && (rld[r].nregs == max_group_size
5460 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5462 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5463 rld[r].when_needed, rld[r].in,
5466 /* If a group is needed, verify that all the subsequent
5467 registers still have their values intact. */
5468 int nr = hard_regno_nregs[i][rld[r].mode];
5471 for (k = 1; k < nr; k++)
5472 if (reg_reloaded_contents[i + k] != regno
5473 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5481 last_reg = (GET_MODE (last_reg) == mode
5482 ? last_reg : gen_rtx_REG (mode, i));
5485 for (k = 0; k < nr; k++)
5486 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5489 /* We found a register that contains the
5490 value we need. If this register is the
5491 same as an `earlyclobber' operand of the
5492 current insn, just mark it as a place to
5493 reload from since we can't use it as the
5494 reload register itself. */
5496 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5497 if (reg_overlap_mentioned_for_reload_p
5498 (reg_last_reload_reg[regno],
5499 reload_earlyclobbers[i1]))
5502 if (i1 != n_earlyclobbers
5503 || ! (free_for_value_p (i, rld[r].mode,
5505 rld[r].when_needed, rld[r].in,
5507 /* Don't use it if we'd clobber a pseudo reg. */
5508 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5510 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5511 /* Don't clobber the frame pointer. */
5512 || (i == HARD_FRAME_POINTER_REGNUM
5513 && frame_pointer_needed
5515 /* Don't really use the inherited spill reg
5516 if we need it wider than we've got it. */
5517 || (GET_MODE_SIZE (rld[r].mode)
5518 > GET_MODE_SIZE (mode))
5521 /* If find_reloads chose reload_out as reload
5522 register, stay with it - that leaves the
5523 inherited register for subsequent reloads. */
5524 || (rld[r].out && rld[r].reg_rtx
5525 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5527 if (! rld[r].optional)
5529 reload_override_in[r] = last_reg;
5530 reload_inheritance_insn[r]
5531 = reg_reloaded_insn[i];
5537 /* We can use this as a reload reg. */
5538 /* Mark the register as in use for this part of
5540 mark_reload_reg_in_use (i,
5544 rld[r].reg_rtx = last_reg;
5545 reload_inherited[r] = 1;
5546 reload_inheritance_insn[r]
5547 = reg_reloaded_insn[i];
5548 reload_spill_index[r] = i;
5549 for (k = 0; k < nr; k++)
5550 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5558 /* Here's another way to see if the value is already lying around. */
5561 && ! reload_inherited[r]
5563 && (CONSTANT_P (rld[r].in)
5564 || GET_CODE (rld[r].in) == PLUS
5565 || REG_P (rld[r].in)
5566 || MEM_P (rld[r].in))
5567 && (rld[r].nregs == max_group_size
5568 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5569 search_equiv = rld[r].in;
5570 /* If this is an output reload from a simple move insn, look
5571 if an equivalence for the input is available. */
5572 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5574 rtx set = single_set (insn);
5577 && rtx_equal_p (rld[r].out, SET_DEST (set))
5578 && CONSTANT_P (SET_SRC (set)))
5579 search_equiv = SET_SRC (set);
5585 = find_equiv_reg (search_equiv, insn, rld[r].class,
5586 -1, NULL, 0, rld[r].mode);
5592 regno = REGNO (equiv);
5595 /* This must be a SUBREG of a hard register.
5596 Make a new REG since this might be used in an
5597 address and not all machines support SUBREGs
5599 gcc_assert (GET_CODE (equiv) == SUBREG);
5600 regno = subreg_regno (equiv);
5601 equiv = gen_rtx_REG (rld[r].mode, regno);
5605 /* If we found a spill reg, reject it unless it is free
5606 and of the desired class. */
5610 int bad_for_class = 0;
5611 int max_regno = regno + rld[r].nregs;
5613 for (i = regno; i < max_regno; i++)
5615 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5617 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5622 && ! free_for_value_p (regno, rld[r].mode,
5623 rld[r].opnum, rld[r].when_needed,
5624 rld[r].in, rld[r].out, r, 1))
5629 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5632 /* We found a register that contains the value we need.
5633 If this register is the same as an `earlyclobber' operand
5634 of the current insn, just mark it as a place to reload from
5635 since we can't use it as the reload register itself. */
5638 for (i = 0; i < n_earlyclobbers; i++)
5639 if (reg_overlap_mentioned_for_reload_p (equiv,
5640 reload_earlyclobbers[i]))
5642 if (! rld[r].optional)
5643 reload_override_in[r] = equiv;
5648 /* If the equiv register we have found is explicitly clobbered
5649 in the current insn, it depends on the reload type if we
5650 can use it, use it for reload_override_in, or not at all.
5651 In particular, we then can't use EQUIV for a
5652 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5656 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5657 switch (rld[r].when_needed)
5659 case RELOAD_FOR_OTHER_ADDRESS:
5660 case RELOAD_FOR_INPADDR_ADDRESS:
5661 case RELOAD_FOR_INPUT_ADDRESS:
5662 case RELOAD_FOR_OPADDR_ADDR:
5665 case RELOAD_FOR_INPUT:
5666 case RELOAD_FOR_OPERAND_ADDRESS:
5667 if (! rld[r].optional)
5668 reload_override_in[r] = equiv;
5674 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5675 switch (rld[r].when_needed)
5677 case RELOAD_FOR_OTHER_ADDRESS:
5678 case RELOAD_FOR_INPADDR_ADDRESS:
5679 case RELOAD_FOR_INPUT_ADDRESS:
5680 case RELOAD_FOR_OPADDR_ADDR:
5681 case RELOAD_FOR_OPERAND_ADDRESS:
5682 case RELOAD_FOR_INPUT:
5685 if (! rld[r].optional)
5686 reload_override_in[r] = equiv;
5694 /* If we found an equivalent reg, say no code need be generated
5695 to load it, and use it as our reload reg. */
5697 && (regno != HARD_FRAME_POINTER_REGNUM
5698 || !frame_pointer_needed))
5700 int nr = hard_regno_nregs[regno][rld[r].mode];
5702 rld[r].reg_rtx = equiv;
5703 reload_inherited[r] = 1;
5705 /* If reg_reloaded_valid is not set for this register,
5706 there might be a stale spill_reg_store lying around.
5707 We must clear it, since otherwise emit_reload_insns
5708 might delete the store. */
5709 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5710 spill_reg_store[regno] = NULL_RTX;
5711 /* If any of the hard registers in EQUIV are spill
5712 registers, mark them as in use for this insn. */
5713 for (k = 0; k < nr; k++)
5715 i = spill_reg_order[regno + k];
5718 mark_reload_reg_in_use (regno, rld[r].opnum,
5721 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5728 /* If we found a register to use already, or if this is an optional
5729 reload, we are done. */
5730 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5734 /* No longer needed for correct operation. Might or might
5735 not give better code on the average. Want to experiment? */
5737 /* See if there is a later reload that has a class different from our
5738 class that intersects our class or that requires less register
5739 than our reload. If so, we must allocate a register to this
5740 reload now, since that reload might inherit a previous reload
5741 and take the only available register in our class. Don't do this
5742 for optional reloads since they will force all previous reloads
5743 to be allocated. Also don't do this for reloads that have been
5746 for (i = j + 1; i < n_reloads; i++)
5748 int s = reload_order[i];
5750 if ((rld[s].in == 0 && rld[s].out == 0
5751 && ! rld[s].secondary_p)
5755 if ((rld[s].class != rld[r].class
5756 && reg_classes_intersect_p (rld[r].class,
5758 || rld[s].nregs < rld[r].nregs)
5765 allocate_reload_reg (chain, r, j == n_reloads - 1);
5769 /* Now allocate reload registers for anything non-optional that
5770 didn't get one yet. */
5771 for (j = 0; j < n_reloads; j++)
5773 int r = reload_order[j];
5775 /* Ignore reloads that got marked inoperative. */
5776 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5779 /* Skip reloads that already have a register allocated or are
5781 if (rld[r].reg_rtx != 0 || rld[r].optional)
5784 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5788 /* If that loop got all the way, we have won. */
5795 /* Loop around and try without any inheritance. */
5800 /* First undo everything done by the failed attempt
5801 to allocate with inheritance. */
5802 choose_reload_regs_init (chain, save_reload_reg_rtx);
5804 /* Some sanity tests to verify that the reloads found in the first
5805 pass are identical to the ones we have now. */
5806 gcc_assert (chain->n_reloads == n_reloads);
5808 for (i = 0; i < n_reloads; i++)
5810 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5812 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5813 for (j = 0; j < n_spills; j++)
5814 if (spill_regs[j] == chain->rld[i].regno)
5815 if (! set_reload_reg (j, i))
5816 failed_reload (chain->insn, i);
5820 /* If we thought we could inherit a reload, because it seemed that
5821 nothing else wanted the same reload register earlier in the insn,
5822 verify that assumption, now that all reloads have been assigned.
5823 Likewise for reloads where reload_override_in has been set. */
5825 /* If doing expensive optimizations, do one preliminary pass that doesn't
5826 cancel any inheritance, but removes reloads that have been needed only
5827 for reloads that we know can be inherited. */
5828 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5830 for (j = 0; j < n_reloads; j++)
5832 int r = reload_order[j];
5834 if (reload_inherited[r] && rld[r].reg_rtx)
5835 check_reg = rld[r].reg_rtx;
5836 else if (reload_override_in[r]
5837 && (REG_P (reload_override_in[r])
5838 || GET_CODE (reload_override_in[r]) == SUBREG))
5839 check_reg = reload_override_in[r];
5842 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5843 rld[r].opnum, rld[r].when_needed, rld[r].in,
5844 (reload_inherited[r]
5845 ? rld[r].out : const0_rtx),
5850 reload_inherited[r] = 0;
5851 reload_override_in[r] = 0;
5853 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5854 reload_override_in, then we do not need its related
5855 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5856 likewise for other reload types.
5857 We handle this by removing a reload when its only replacement
5858 is mentioned in reload_in of the reload we are going to inherit.
5859 A special case are auto_inc expressions; even if the input is
5860 inherited, we still need the address for the output. We can
5861 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5862 If we succeeded removing some reload and we are doing a preliminary
5863 pass just to remove such reloads, make another pass, since the
5864 removal of one reload might allow us to inherit another one. */
5866 && rld[r].out != rld[r].in
5867 && remove_address_replacements (rld[r].in) && pass)
5872 /* Now that reload_override_in is known valid,
5873 actually override reload_in. */
5874 for (j = 0; j < n_reloads; j++)
5875 if (reload_override_in[j])
5876 rld[j].in = reload_override_in[j];
5878 /* If this reload won't be done because it has been canceled or is
5879 optional and not inherited, clear reload_reg_rtx so other
5880 routines (such as subst_reloads) don't get confused. */
5881 for (j = 0; j < n_reloads; j++)
5882 if (rld[j].reg_rtx != 0
5883 && ((rld[j].optional && ! reload_inherited[j])
5884 || (rld[j].in == 0 && rld[j].out == 0
5885 && ! rld[j].secondary_p)))
5887 int regno = true_regnum (rld[j].reg_rtx);
5889 if (spill_reg_order[regno] >= 0)
5890 clear_reload_reg_in_use (regno, rld[j].opnum,
5891 rld[j].when_needed, rld[j].mode);
5893 reload_spill_index[j] = -1;
5896 /* Record which pseudos and which spill regs have output reloads. */
5897 for (j = 0; j < n_reloads; j++)
5899 int r = reload_order[j];
5901 i = reload_spill_index[r];
5903 /* I is nonneg if this reload uses a register.
5904 If rld[r].reg_rtx is 0, this is an optional reload
5905 that we opted to ignore. */
5906 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5907 && rld[r].reg_rtx != 0)
5909 int nregno = REGNO (rld[r].out_reg);
5912 if (nregno < FIRST_PSEUDO_REGISTER)
5913 nr = hard_regno_nregs[nregno][rld[r].mode];
5916 reg_has_output_reload[nregno + nr] = 1;
5920 nr = hard_regno_nregs[i][rld[r].mode];
5922 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5925 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5926 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5927 || rld[r].when_needed == RELOAD_FOR_INSN);
5932 /* Deallocate the reload register for reload R. This is called from
5933 remove_address_replacements. */
5936 deallocate_reload_reg (int r)
5940 if (! rld[r].reg_rtx)
5942 regno = true_regnum (rld[r].reg_rtx);
5944 if (spill_reg_order[regno] >= 0)
5945 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5947 reload_spill_index[r] = -1;
5950 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5951 reloads of the same item for fear that we might not have enough reload
5952 registers. However, normally they will get the same reload register
5953 and hence actually need not be loaded twice.
5955 Here we check for the most common case of this phenomenon: when we have
5956 a number of reloads for the same object, each of which were allocated
5957 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5958 reload, and is not modified in the insn itself. If we find such,
5959 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5960 This will not increase the number of spill registers needed and will
5961 prevent redundant code. */
5964 merge_assigned_reloads (rtx insn)
5968 /* Scan all the reloads looking for ones that only load values and
5969 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5970 assigned and not modified by INSN. */
5972 for (i = 0; i < n_reloads; i++)
5974 int conflicting_input = 0;
5975 int max_input_address_opnum = -1;
5976 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5978 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5979 || rld[i].out != 0 || rld[i].reg_rtx == 0
5980 || reg_set_p (rld[i].reg_rtx, insn))
5983 /* Look at all other reloads. Ensure that the only use of this
5984 reload_reg_rtx is in a reload that just loads the same value
5985 as we do. Note that any secondary reloads must be of the identical
5986 class since the values, modes, and result registers are the
5987 same, so we need not do anything with any secondary reloads. */
5989 for (j = 0; j < n_reloads; j++)
5991 if (i == j || rld[j].reg_rtx == 0
5992 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5996 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5997 && rld[j].opnum > max_input_address_opnum)
5998 max_input_address_opnum = rld[j].opnum;
6000 /* If the reload regs aren't exactly the same (e.g, different modes)
6001 or if the values are different, we can't merge this reload.
6002 But if it is an input reload, we might still merge
6003 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6005 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6006 || rld[j].out != 0 || rld[j].in == 0
6007 || ! rtx_equal_p (rld[i].in, rld[j].in))
6009 if (rld[j].when_needed != RELOAD_FOR_INPUT
6010 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6011 || rld[i].opnum > rld[j].opnum)
6012 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6014 conflicting_input = 1;
6015 if (min_conflicting_input_opnum > rld[j].opnum)
6016 min_conflicting_input_opnum = rld[j].opnum;
6020 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6021 we, in fact, found any matching reloads. */
6024 && max_input_address_opnum <= min_conflicting_input_opnum)
6026 for (j = 0; j < n_reloads; j++)
6027 if (i != j && rld[j].reg_rtx != 0
6028 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6029 && (! conflicting_input
6030 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6031 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6033 rld[i].when_needed = RELOAD_OTHER;
6035 reload_spill_index[j] = -1;
6036 transfer_replacements (i, j);
6039 /* If this is now RELOAD_OTHER, look for any reloads that load
6040 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6041 if they were for inputs, RELOAD_OTHER for outputs. Note that
6042 this test is equivalent to looking for reloads for this operand
6044 /* We must take special care when there are two or more reloads to
6045 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6046 same value or a part of it; we must not change its type if there
6047 is a conflicting input. */
6049 if (rld[i].when_needed == RELOAD_OTHER)
6050 for (j = 0; j < n_reloads; j++)
6052 && rld[j].when_needed != RELOAD_OTHER
6053 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6054 && (! conflicting_input
6055 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6056 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6057 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6063 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6064 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6065 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6067 /* Check to see if we accidentally converted two reloads
6068 that use the same reload register with different inputs
6069 to the same type. If so, the resulting code won't work,
6072 for (k = 0; k < j; k++)
6073 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6074 || rld[k].when_needed != rld[j].when_needed
6075 || !rtx_equal_p (rld[k].reg_rtx,
6077 || rtx_equal_p (rld[k].in,
6084 /* These arrays are filled by emit_reload_insns and its subroutines. */
6085 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6086 static rtx other_input_address_reload_insns = 0;
6087 static rtx other_input_reload_insns = 0;
6088 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6090 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6091 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6092 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6093 static rtx operand_reload_insns = 0;
6094 static rtx other_operand_reload_insns = 0;
6095 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6097 /* Values to be put in spill_reg_store are put here first. */
6098 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6099 static HARD_REG_SET reg_reloaded_died;
6101 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6102 has the number J. OLD contains the value to be used as input. */
6105 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6108 rtx insn = chain->insn;
6109 rtx reloadreg = rl->reg_rtx;
6110 rtx oldequiv_reg = 0;
6113 enum machine_mode mode;
6116 /* Determine the mode to reload in.
6117 This is very tricky because we have three to choose from.
6118 There is the mode the insn operand wants (rl->inmode).
6119 There is the mode of the reload register RELOADREG.
6120 There is the intrinsic mode of the operand, which we could find
6121 by stripping some SUBREGs.
6122 It turns out that RELOADREG's mode is irrelevant:
6123 we can change that arbitrarily.
6125 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6126 then the reload reg may not support QImode moves, so use SImode.
6127 If foo is in memory due to spilling a pseudo reg, this is safe,
6128 because the QImode value is in the least significant part of a
6129 slot big enough for a SImode. If foo is some other sort of
6130 memory reference, then it is impossible to reload this case,
6131 so previous passes had better make sure this never happens.
6133 Then consider a one-word union which has SImode and one of its
6134 members is a float, being fetched as (SUBREG:SF union:SI).
6135 We must fetch that as SFmode because we could be loading into
6136 a float-only register. In this case OLD's mode is correct.
6138 Consider an immediate integer: it has VOIDmode. Here we need
6139 to get a mode from something else.
6141 In some cases, there is a fourth mode, the operand's
6142 containing mode. If the insn specifies a containing mode for
6143 this operand, it overrides all others.
6145 I am not sure whether the algorithm here is always right,
6146 but it does the right things in those cases. */
6148 mode = GET_MODE (old);
6149 if (mode == VOIDmode)
6152 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6153 /* If we need a secondary register for this operation, see if
6154 the value is already in a register in that class. Don't
6155 do this if the secondary register will be used as a scratch
6158 if (rl->secondary_in_reload >= 0
6159 && rl->secondary_in_icode == CODE_FOR_nothing
6162 = find_equiv_reg (old, insn,
6163 rld[rl->secondary_in_reload].class,
6167 /* If reloading from memory, see if there is a register
6168 that already holds the same value. If so, reload from there.
6169 We can pass 0 as the reload_reg_p argument because
6170 any other reload has either already been emitted,
6171 in which case find_equiv_reg will see the reload-insn,
6172 or has yet to be emitted, in which case it doesn't matter
6173 because we will use this equiv reg right away. */
6175 if (oldequiv == 0 && optimize
6178 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6179 && reg_renumber[REGNO (old)] < 0)))
6180 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6184 unsigned int regno = true_regnum (oldequiv);
6186 /* Don't use OLDEQUIV if any other reload changes it at an
6187 earlier stage of this insn or at this stage. */
6188 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6189 rl->in, const0_rtx, j, 0))
6192 /* If it is no cheaper to copy from OLDEQUIV into the
6193 reload register than it would be to move from memory,
6194 don't use it. Likewise, if we need a secondary register
6198 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6199 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6201 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6202 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6203 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6207 #ifdef SECONDARY_MEMORY_NEEDED
6208 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6216 /* delete_output_reload is only invoked properly if old contains
6217 the original pseudo register. Since this is replaced with a
6218 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6219 find the pseudo in RELOAD_IN_REG. */
6221 && reload_override_in[j]
6222 && REG_P (rl->in_reg))
6229 else if (REG_P (oldequiv))
6230 oldequiv_reg = oldequiv;
6231 else if (GET_CODE (oldequiv) == SUBREG)
6232 oldequiv_reg = SUBREG_REG (oldequiv);
6234 /* If we are reloading from a register that was recently stored in
6235 with an output-reload, see if we can prove there was
6236 actually no need to store the old value in it. */
6238 if (optimize && REG_P (oldequiv)
6239 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6240 && spill_reg_store[REGNO (oldequiv)]
6242 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6243 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6245 delete_output_reload (insn, j, REGNO (oldequiv));
6247 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6248 then load RELOADREG from OLDEQUIV. Note that we cannot use
6249 gen_lowpart_common since it can do the wrong thing when
6250 RELOADREG has a multi-word mode. Note that RELOADREG
6251 must always be a REG here. */
6253 if (GET_MODE (reloadreg) != mode)
6254 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6255 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6256 oldequiv = SUBREG_REG (oldequiv);
6257 if (GET_MODE (oldequiv) != VOIDmode
6258 && mode != GET_MODE (oldequiv))
6259 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6261 /* Switch to the right place to emit the reload insns. */
6262 switch (rl->when_needed)
6265 where = &other_input_reload_insns;
6267 case RELOAD_FOR_INPUT:
6268 where = &input_reload_insns[rl->opnum];
6270 case RELOAD_FOR_INPUT_ADDRESS:
6271 where = &input_address_reload_insns[rl->opnum];
6273 case RELOAD_FOR_INPADDR_ADDRESS:
6274 where = &inpaddr_address_reload_insns[rl->opnum];
6276 case RELOAD_FOR_OUTPUT_ADDRESS:
6277 where = &output_address_reload_insns[rl->opnum];
6279 case RELOAD_FOR_OUTADDR_ADDRESS:
6280 where = &outaddr_address_reload_insns[rl->opnum];
6282 case RELOAD_FOR_OPERAND_ADDRESS:
6283 where = &operand_reload_insns;
6285 case RELOAD_FOR_OPADDR_ADDR:
6286 where = &other_operand_reload_insns;
6288 case RELOAD_FOR_OTHER_ADDRESS:
6289 where = &other_input_address_reload_insns;
6295 push_to_sequence (*where);
6297 /* Auto-increment addresses must be reloaded in a special way. */
6298 if (rl->out && ! rl->out_reg)
6300 /* We are not going to bother supporting the case where a
6301 incremented register can't be copied directly from
6302 OLDEQUIV since this seems highly unlikely. */
6303 gcc_assert (rl->secondary_in_reload < 0);
6305 if (reload_inherited[j])
6306 oldequiv = reloadreg;
6308 old = XEXP (rl->in_reg, 0);
6310 if (optimize && REG_P (oldequiv)
6311 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6312 && spill_reg_store[REGNO (oldequiv)]
6314 && (dead_or_set_p (insn,
6315 spill_reg_stored_to[REGNO (oldequiv)])
6316 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6318 delete_output_reload (insn, j, REGNO (oldequiv));
6320 /* Prevent normal processing of this reload. */
6322 /* Output a special code sequence for this case. */
6323 new_spill_reg_store[REGNO (reloadreg)]
6324 = inc_for_reload (reloadreg, oldequiv, rl->out,
6328 /* If we are reloading a pseudo-register that was set by the previous
6329 insn, see if we can get rid of that pseudo-register entirely
6330 by redirecting the previous insn into our reload register. */
6332 else if (optimize && REG_P (old)
6333 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6334 && dead_or_set_p (insn, old)
6335 /* This is unsafe if some other reload
6336 uses the same reg first. */
6337 && ! conflicts_with_override (reloadreg)
6338 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6339 rl->when_needed, old, rl->out, j, 0))
6341 rtx temp = PREV_INSN (insn);
6342 while (temp && NOTE_P (temp))
6343 temp = PREV_INSN (temp);
6345 && NONJUMP_INSN_P (temp)
6346 && GET_CODE (PATTERN (temp)) == SET
6347 && SET_DEST (PATTERN (temp)) == old
6348 /* Make sure we can access insn_operand_constraint. */
6349 && asm_noperands (PATTERN (temp)) < 0
6350 /* This is unsafe if operand occurs more than once in current
6351 insn. Perhaps some occurrences aren't reloaded. */
6352 && count_occurrences (PATTERN (insn), old, 0) == 1)
6354 rtx old = SET_DEST (PATTERN (temp));
6355 /* Store into the reload register instead of the pseudo. */
6356 SET_DEST (PATTERN (temp)) = reloadreg;
6358 /* Verify that resulting insn is valid. */
6359 extract_insn (temp);
6360 if (constrain_operands (1))
6362 /* If the previous insn is an output reload, the source is
6363 a reload register, and its spill_reg_store entry will
6364 contain the previous destination. This is now
6366 if (REG_P (SET_SRC (PATTERN (temp)))
6367 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6369 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6370 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6373 /* If these are the only uses of the pseudo reg,
6374 pretend for GDB it lives in the reload reg we used. */
6375 if (REG_N_DEATHS (REGNO (old)) == 1
6376 && REG_N_SETS (REGNO (old)) == 1)
6378 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6379 alter_reg (REGNO (old), -1);
6385 SET_DEST (PATTERN (temp)) = old;
6390 /* We can't do that, so output an insn to load RELOADREG. */
6392 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6393 /* If we have a secondary reload, pick up the secondary register
6394 and icode, if any. If OLDEQUIV and OLD are different or
6395 if this is an in-out reload, recompute whether or not we
6396 still need a secondary register and what the icode should
6397 be. If we still need a secondary register and the class or
6398 icode is different, go back to reloading from OLD if using
6399 OLDEQUIV means that we got the wrong type of register. We
6400 cannot have different class or icode due to an in-out reload
6401 because we don't make such reloads when both the input and
6402 output need secondary reload registers. */
6404 if (! special && rl->secondary_in_reload >= 0)
6406 rtx second_reload_reg = 0;
6407 int secondary_reload = rl->secondary_in_reload;
6408 rtx real_oldequiv = oldequiv;
6411 enum insn_code icode;
6413 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6414 and similarly for OLD.
6415 See comments in get_secondary_reload in reload.c. */
6416 /* If it is a pseudo that cannot be replaced with its
6417 equivalent MEM, we must fall back to reload_in, which
6418 will have all the necessary substitutions registered.
6419 Likewise for a pseudo that can't be replaced with its
6420 equivalent constant.
6422 Take extra care for subregs of such pseudos. Note that
6423 we cannot use reg_equiv_mem in this case because it is
6424 not in the right mode. */
6427 if (GET_CODE (tmp) == SUBREG)
6428 tmp = SUBREG_REG (tmp);
6430 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6431 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6432 || reg_equiv_constant[REGNO (tmp)] != 0))
6434 if (! reg_equiv_mem[REGNO (tmp)]
6435 || num_not_at_initial_offset
6436 || GET_CODE (oldequiv) == SUBREG)
6437 real_oldequiv = rl->in;
6439 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6443 if (GET_CODE (tmp) == SUBREG)
6444 tmp = SUBREG_REG (tmp);
6446 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6447 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6448 || reg_equiv_constant[REGNO (tmp)] != 0))
6450 if (! reg_equiv_mem[REGNO (tmp)]
6451 || num_not_at_initial_offset
6452 || GET_CODE (old) == SUBREG)
6455 real_old = reg_equiv_mem[REGNO (tmp)];
6458 second_reload_reg = rld[secondary_reload].reg_rtx;
6459 icode = rl->secondary_in_icode;
6461 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6462 || (rl->in != 0 && rl->out != 0))
6464 enum reg_class new_class
6465 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6466 mode, real_oldequiv);
6468 if (new_class == NO_REGS)
6469 second_reload_reg = 0;
6472 enum insn_code new_icode;
6473 enum machine_mode new_mode;
6475 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6476 REGNO (second_reload_reg)))
6477 oldequiv = old, real_oldequiv = real_old;
6480 new_icode = reload_in_optab[(int) mode];
6481 if (new_icode != CODE_FOR_nothing
6482 && ((insn_data[(int) new_icode].operand[0].predicate
6483 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6485 || (insn_data[(int) new_icode].operand[1].predicate
6486 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6487 (real_oldequiv, mode)))))
6488 new_icode = CODE_FOR_nothing;
6490 if (new_icode == CODE_FOR_nothing)
6493 new_mode = insn_data[(int) new_icode].operand[2].mode;
6495 if (GET_MODE (second_reload_reg) != new_mode)
6497 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6499 oldequiv = old, real_oldequiv = real_old;
6502 = reload_adjust_reg_for_mode (second_reload_reg,
6509 /* If we still need a secondary reload register, check
6510 to see if it is being used as a scratch or intermediate
6511 register and generate code appropriately. If we need
6512 a scratch register, use REAL_OLDEQUIV since the form of
6513 the insn may depend on the actual address if it is
6516 if (second_reload_reg)
6518 if (icode != CODE_FOR_nothing)
6520 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6521 second_reload_reg));
6526 /* See if we need a scratch register to load the
6527 intermediate register (a tertiary reload). */
6528 enum insn_code tertiary_icode
6529 = rld[secondary_reload].secondary_in_icode;
6531 if (tertiary_icode != CODE_FOR_nothing)
6533 rtx third_reload_reg
6534 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6536 emit_insn ((GEN_FCN (tertiary_icode)
6537 (second_reload_reg, real_oldequiv,
6538 third_reload_reg)));
6541 gen_reload (second_reload_reg, real_oldequiv,
6545 oldequiv = second_reload_reg;
6551 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6553 rtx real_oldequiv = oldequiv;
6555 if ((REG_P (oldequiv)
6556 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6557 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6558 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6559 || (GET_CODE (oldequiv) == SUBREG
6560 && REG_P (SUBREG_REG (oldequiv))
6561 && (REGNO (SUBREG_REG (oldequiv))
6562 >= FIRST_PSEUDO_REGISTER)
6563 && ((reg_equiv_memory_loc
6564 [REGNO (SUBREG_REG (oldequiv))] != 0)
6565 || (reg_equiv_constant
6566 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6567 || (CONSTANT_P (oldequiv)
6568 && (PREFERRED_RELOAD_CLASS (oldequiv,
6569 REGNO_REG_CLASS (REGNO (reloadreg)))
6571 real_oldequiv = rl->in;
6572 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6576 if (flag_non_call_exceptions)
6577 copy_eh_notes (insn, get_insns ());
6579 /* End this sequence. */
6580 *where = get_insns ();
6583 /* Update reload_override_in so that delete_address_reloads_1
6584 can see the actual register usage. */
6586 reload_override_in[j] = oldequiv;
6589 /* Generate insns to for the output reload RL, which is for the insn described
6590 by CHAIN and has the number J. */
6592 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6595 rtx reloadreg = rl->reg_rtx;
6596 rtx insn = chain->insn;
6599 enum machine_mode mode = GET_MODE (old);
6602 if (rl->when_needed == RELOAD_OTHER)
6605 push_to_sequence (output_reload_insns[rl->opnum]);
6607 /* Determine the mode to reload in.
6608 See comments above (for input reloading). */
6610 if (mode == VOIDmode)
6612 /* VOIDmode should never happen for an output. */
6613 if (asm_noperands (PATTERN (insn)) < 0)
6614 /* It's the compiler's fault. */
6615 fatal_insn ("VOIDmode on an output", insn);
6616 error_for_asm (insn, "output operand is constant in %<asm%>");
6617 /* Prevent crash--use something we know is valid. */
6619 old = gen_rtx_REG (mode, REGNO (reloadreg));
6622 if (GET_MODE (reloadreg) != mode)
6623 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6625 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6627 /* If we need two reload regs, set RELOADREG to the intermediate
6628 one, since it will be stored into OLD. We might need a secondary
6629 register only for an input reload, so check again here. */
6631 if (rl->secondary_out_reload >= 0)
6635 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6636 && reg_equiv_mem[REGNO (old)] != 0)
6637 real_old = reg_equiv_mem[REGNO (old)];
6639 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6643 rtx second_reloadreg = reloadreg;
6644 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6646 /* See if RELOADREG is to be used as a scratch register
6647 or as an intermediate register. */
6648 if (rl->secondary_out_icode != CODE_FOR_nothing)
6650 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6651 (real_old, second_reloadreg, reloadreg)));
6656 /* See if we need both a scratch and intermediate reload
6659 int secondary_reload = rl->secondary_out_reload;
6660 enum insn_code tertiary_icode
6661 = rld[secondary_reload].secondary_out_icode;
6663 if (GET_MODE (reloadreg) != mode)
6664 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6666 if (tertiary_icode != CODE_FOR_nothing)
6669 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6672 /* Copy primary reload reg to secondary reload reg.
6673 (Note that these have been swapped above, then
6674 secondary reload reg to OLD using our insn.) */
6676 /* If REAL_OLD is a paradoxical SUBREG, remove it
6677 and try to put the opposite SUBREG on
6679 if (GET_CODE (real_old) == SUBREG
6680 && (GET_MODE_SIZE (GET_MODE (real_old))
6681 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6682 && 0 != (tem = gen_lowpart_common
6683 (GET_MODE (SUBREG_REG (real_old)),
6685 real_old = SUBREG_REG (real_old), reloadreg = tem;
6687 gen_reload (reloadreg, second_reloadreg,
6688 rl->opnum, rl->when_needed);
6689 emit_insn ((GEN_FCN (tertiary_icode)
6690 (real_old, reloadreg, third_reloadreg)));
6695 /* Copy between the reload regs here and then to
6698 gen_reload (reloadreg, second_reloadreg,
6699 rl->opnum, rl->when_needed);
6705 /* Output the last reload insn. */
6710 /* Don't output the last reload if OLD is not the dest of
6711 INSN and is in the src and is clobbered by INSN. */
6712 if (! flag_expensive_optimizations
6714 || !(set = single_set (insn))
6715 || rtx_equal_p (old, SET_DEST (set))
6716 || !reg_mentioned_p (old, SET_SRC (set))
6717 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6718 gen_reload (old, reloadreg, rl->opnum,
6722 /* Look at all insns we emitted, just to be safe. */
6723 for (p = get_insns (); p; p = NEXT_INSN (p))
6726 rtx pat = PATTERN (p);
6728 /* If this output reload doesn't come from a spill reg,
6729 clear any memory of reloaded copies of the pseudo reg.
6730 If this output reload comes from a spill reg,
6731 reg_has_output_reload will make this do nothing. */
6732 note_stores (pat, forget_old_reloads_1, NULL);
6734 if (reg_mentioned_p (rl->reg_rtx, pat))
6736 rtx set = single_set (insn);
6737 if (reload_spill_index[j] < 0
6739 && SET_SRC (set) == rl->reg_rtx)
6741 int src = REGNO (SET_SRC (set));
6743 reload_spill_index[j] = src;
6744 SET_HARD_REG_BIT (reg_is_output_reload, src);
6745 if (find_regno_note (insn, REG_DEAD, src))
6746 SET_HARD_REG_BIT (reg_reloaded_died, src);
6748 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6750 int s = rl->secondary_out_reload;
6751 set = single_set (p);
6752 /* If this reload copies only to the secondary reload
6753 register, the secondary reload does the actual
6755 if (s >= 0 && set == NULL_RTX)
6756 /* We can't tell what function the secondary reload
6757 has and where the actual store to the pseudo is
6758 made; leave new_spill_reg_store alone. */
6761 && SET_SRC (set) == rl->reg_rtx
6762 && SET_DEST (set) == rld[s].reg_rtx)
6764 /* Usually the next instruction will be the
6765 secondary reload insn; if we can confirm
6766 that it is, setting new_spill_reg_store to
6767 that insn will allow an extra optimization. */
6768 rtx s_reg = rld[s].reg_rtx;
6769 rtx next = NEXT_INSN (p);
6770 rld[s].out = rl->out;
6771 rld[s].out_reg = rl->out_reg;
6772 set = single_set (next);
6773 if (set && SET_SRC (set) == s_reg
6774 && ! new_spill_reg_store[REGNO (s_reg)])
6776 SET_HARD_REG_BIT (reg_is_output_reload,
6778 new_spill_reg_store[REGNO (s_reg)] = next;
6782 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6787 if (rl->when_needed == RELOAD_OTHER)
6789 emit_insn (other_output_reload_insns[rl->opnum]);
6790 other_output_reload_insns[rl->opnum] = get_insns ();
6793 output_reload_insns[rl->opnum] = get_insns ();
6795 if (flag_non_call_exceptions)
6796 copy_eh_notes (insn, get_insns ());
6801 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6802 and has the number J. */
6804 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6806 rtx insn = chain->insn;
6807 rtx old = (rl->in && MEM_P (rl->in)
6808 ? rl->in_reg : rl->in);
6811 /* AUTO_INC reloads need to be handled even if inherited. We got an
6812 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6813 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6814 && ! rtx_equal_p (rl->reg_rtx, old)
6815 && rl->reg_rtx != 0)
6816 emit_input_reload_insns (chain, rld + j, old, j);
6818 /* When inheriting a wider reload, we have a MEM in rl->in,
6819 e.g. inheriting a SImode output reload for
6820 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6821 if (optimize && reload_inherited[j] && rl->in
6823 && MEM_P (rl->in_reg)
6824 && reload_spill_index[j] >= 0
6825 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6826 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6828 /* If we are reloading a register that was recently stored in with an
6829 output-reload, see if we can prove there was
6830 actually no need to store the old value in it. */
6833 && (reload_inherited[j] || reload_override_in[j])
6835 && REG_P (rl->reg_rtx)
6836 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6838 /* There doesn't seem to be any reason to restrict this to pseudos
6839 and doing so loses in the case where we are copying from a
6840 register of the wrong class. */
6841 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6842 >= FIRST_PSEUDO_REGISTER)
6844 /* The insn might have already some references to stackslots
6845 replaced by MEMs, while reload_out_reg still names the
6847 && (dead_or_set_p (insn,
6848 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6849 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6851 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6854 /* Do output reloading for reload RL, which is for the insn described by
6855 CHAIN and has the number J.
6856 ??? At some point we need to support handling output reloads of
6857 JUMP_INSNs or insns that set cc0. */
6859 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6862 rtx insn = chain->insn;
6863 /* If this is an output reload that stores something that is
6864 not loaded in this same reload, see if we can eliminate a previous
6866 rtx pseudo = rl->out_reg;
6871 && ! rtx_equal_p (rl->in_reg, pseudo)
6872 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6873 && reg_last_reload_reg[REGNO (pseudo)])
6875 int pseudo_no = REGNO (pseudo);
6876 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6878 /* We don't need to test full validity of last_regno for
6879 inherit here; we only want to know if the store actually
6880 matches the pseudo. */
6881 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6882 && reg_reloaded_contents[last_regno] == pseudo_no
6883 && spill_reg_store[last_regno]
6884 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6885 delete_output_reload (insn, j, last_regno);
6890 || rl->reg_rtx == old
6891 || rl->reg_rtx == 0)
6894 /* An output operand that dies right away does need a reload,
6895 but need not be copied from it. Show the new location in the
6897 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6898 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6900 XEXP (note, 0) = rl->reg_rtx;
6903 /* Likewise for a SUBREG of an operand that dies. */
6904 else if (GET_CODE (old) == SUBREG
6905 && REG_P (SUBREG_REG (old))
6906 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6909 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6913 else if (GET_CODE (old) == SCRATCH)
6914 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6915 but we don't want to make an output reload. */
6918 /* If is a JUMP_INSN, we can't support output reloads yet. */
6919 gcc_assert (!JUMP_P (insn));
6921 emit_output_reload_insns (chain, rld + j, j);
6924 /* Reload number R reloads from or to a group of hard registers starting at
6925 register REGNO. Return true if it can be treated for inheritance purposes
6926 like a group of reloads, each one reloading a single hard register.
6927 The caller has already checked that the spill register and REGNO use
6928 the same number of registers to store the reload value. */
6931 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6933 #ifdef CANNOT_CHANGE_MODE_CLASS
6934 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6935 GET_MODE (rld[r].reg_rtx),
6936 reg_raw_mode[reload_spill_index[r]])
6937 && !REG_CANNOT_CHANGE_MODE_P (regno,
6938 GET_MODE (rld[r].reg_rtx),
6939 reg_raw_mode[regno]));
6945 /* Output insns to reload values in and out of the chosen reload regs. */
6948 emit_reload_insns (struct insn_chain *chain)
6950 rtx insn = chain->insn;
6954 CLEAR_HARD_REG_SET (reg_reloaded_died);
6956 for (j = 0; j < reload_n_operands; j++)
6957 input_reload_insns[j] = input_address_reload_insns[j]
6958 = inpaddr_address_reload_insns[j]
6959 = output_reload_insns[j] = output_address_reload_insns[j]
6960 = outaddr_address_reload_insns[j]
6961 = other_output_reload_insns[j] = 0;
6962 other_input_address_reload_insns = 0;
6963 other_input_reload_insns = 0;
6964 operand_reload_insns = 0;
6965 other_operand_reload_insns = 0;
6967 /* Dump reloads into the dump file. */
6970 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6971 debug_reload_to_stream (dump_file);
6974 /* Now output the instructions to copy the data into and out of the
6975 reload registers. Do these in the order that the reloads were reported,
6976 since reloads of base and index registers precede reloads of operands
6977 and the operands may need the base and index registers reloaded. */
6979 for (j = 0; j < n_reloads; j++)
6982 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6983 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6985 do_input_reload (chain, rld + j, j);
6986 do_output_reload (chain, rld + j, j);
6989 /* Now write all the insns we made for reloads in the order expected by
6990 the allocation functions. Prior to the insn being reloaded, we write
6991 the following reloads:
6993 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6995 RELOAD_OTHER reloads.
6997 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6998 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6999 RELOAD_FOR_INPUT reload for the operand.
7001 RELOAD_FOR_OPADDR_ADDRS reloads.
7003 RELOAD_FOR_OPERAND_ADDRESS reloads.
7005 After the insn being reloaded, we write the following:
7007 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7008 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7009 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7010 reloads for the operand. The RELOAD_OTHER output reloads are
7011 output in descending order by reload number. */
7013 emit_insn_before (other_input_address_reload_insns, insn);
7014 emit_insn_before (other_input_reload_insns, insn);
7016 for (j = 0; j < reload_n_operands; j++)
7018 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7019 emit_insn_before (input_address_reload_insns[j], insn);
7020 emit_insn_before (input_reload_insns[j], insn);
7023 emit_insn_before (other_operand_reload_insns, insn);
7024 emit_insn_before (operand_reload_insns, insn);
7026 for (j = 0; j < reload_n_operands; j++)
7028 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7029 x = emit_insn_after (output_address_reload_insns[j], x);
7030 x = emit_insn_after (output_reload_insns[j], x);
7031 emit_insn_after (other_output_reload_insns[j], x);
7034 /* For all the spill regs newly reloaded in this instruction,
7035 record what they were reloaded from, so subsequent instructions
7036 can inherit the reloads.
7038 Update spill_reg_store for the reloads of this insn.
7039 Copy the elements that were updated in the loop above. */
7041 for (j = 0; j < n_reloads; j++)
7043 int r = reload_order[j];
7044 int i = reload_spill_index[r];
7046 /* If this is a non-inherited input reload from a pseudo, we must
7047 clear any memory of a previous store to the same pseudo. Only do
7048 something if there will not be an output reload for the pseudo
7050 if (rld[r].in_reg != 0
7051 && ! (reload_inherited[r] || reload_override_in[r]))
7053 rtx reg = rld[r].in_reg;
7055 if (GET_CODE (reg) == SUBREG)
7056 reg = SUBREG_REG (reg);
7059 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7060 && ! reg_has_output_reload[REGNO (reg)])
7062 int nregno = REGNO (reg);
7064 if (reg_last_reload_reg[nregno])
7066 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7068 if (reg_reloaded_contents[last_regno] == nregno)
7069 spill_reg_store[last_regno] = 0;
7074 /* I is nonneg if this reload used a register.
7075 If rld[r].reg_rtx is 0, this is an optional reload
7076 that we opted to ignore. */
7078 if (i >= 0 && rld[r].reg_rtx != 0)
7080 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7082 int part_reaches_end = 0;
7083 int all_reaches_end = 1;
7085 /* For a multi register reload, we need to check if all or part
7086 of the value lives to the end. */
7087 for (k = 0; k < nr; k++)
7089 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7090 rld[r].when_needed))
7091 part_reaches_end = 1;
7093 all_reaches_end = 0;
7096 /* Ignore reloads that don't reach the end of the insn in
7098 if (all_reaches_end)
7100 /* First, clear out memory of what used to be in this spill reg.
7101 If consecutive registers are used, clear them all. */
7103 for (k = 0; k < nr; k++)
7105 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7106 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7109 /* Maybe the spill reg contains a copy of reload_out. */
7111 && (REG_P (rld[r].out)
7115 || REG_P (rld[r].out_reg)))
7117 rtx out = (REG_P (rld[r].out)
7121 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7122 int nregno = REGNO (out);
7123 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7124 : hard_regno_nregs[nregno]
7125 [GET_MODE (rld[r].reg_rtx)]);
7128 spill_reg_store[i] = new_spill_reg_store[i];
7129 spill_reg_stored_to[i] = out;
7130 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7132 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7134 && inherit_piecemeal_p (r, nregno));
7136 /* If NREGNO is a hard register, it may occupy more than
7137 one register. If it does, say what is in the
7138 rest of the registers assuming that both registers
7139 agree on how many words the object takes. If not,
7140 invalidate the subsequent registers. */
7142 if (nregno < FIRST_PSEUDO_REGISTER)
7143 for (k = 1; k < nnr; k++)
7144 reg_last_reload_reg[nregno + k]
7146 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7149 /* Now do the inverse operation. */
7150 for (k = 0; k < nr; k++)
7152 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7153 reg_reloaded_contents[i + k]
7154 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7157 reg_reloaded_insn[i + k] = insn;
7158 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7159 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7160 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7164 /* Maybe the spill reg contains a copy of reload_in. Only do
7165 something if there will not be an output reload for
7166 the register being reloaded. */
7167 else if (rld[r].out_reg == 0
7169 && ((REG_P (rld[r].in)
7170 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7171 && ! reg_has_output_reload[REGNO (rld[r].in)])
7172 || (REG_P (rld[r].in_reg)
7173 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7174 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7181 if (REG_P (rld[r].in)
7182 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7184 else if (REG_P (rld[r].in_reg))
7187 in = XEXP (rld[r].in_reg, 0);
7188 nregno = REGNO (in);
7190 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7191 : hard_regno_nregs[nregno]
7192 [GET_MODE (rld[r].reg_rtx)]);
7194 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7196 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7198 && inherit_piecemeal_p (r, nregno));
7200 if (nregno < FIRST_PSEUDO_REGISTER)
7201 for (k = 1; k < nnr; k++)
7202 reg_last_reload_reg[nregno + k]
7204 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7207 /* Unless we inherited this reload, show we haven't
7208 recently done a store.
7209 Previous stores of inherited auto_inc expressions
7210 also have to be discarded. */
7211 if (! reload_inherited[r]
7212 || (rld[r].out && ! rld[r].out_reg))
7213 spill_reg_store[i] = 0;
7215 for (k = 0; k < nr; k++)
7217 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7218 reg_reloaded_contents[i + k]
7219 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7222 reg_reloaded_insn[i + k] = insn;
7223 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7224 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7225 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7230 /* However, if part of the reload reaches the end, then we must
7231 invalidate the old info for the part that survives to the end. */
7232 else if (part_reaches_end)
7234 for (k = 0; k < nr; k++)
7235 if (reload_reg_reaches_end_p (i + k,
7237 rld[r].when_needed))
7238 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7242 /* The following if-statement was #if 0'd in 1.34 (or before...).
7243 It's reenabled in 1.35 because supposedly nothing else
7244 deals with this problem. */
7246 /* If a register gets output-reloaded from a non-spill register,
7247 that invalidates any previous reloaded copy of it.
7248 But forget_old_reloads_1 won't get to see it, because
7249 it thinks only about the original insn. So invalidate it here. */
7250 if (i < 0 && rld[r].out != 0
7251 && (REG_P (rld[r].out)
7252 || (MEM_P (rld[r].out)
7253 && REG_P (rld[r].out_reg))))
7255 rtx out = (REG_P (rld[r].out)
7256 ? rld[r].out : rld[r].out_reg);
7257 int nregno = REGNO (out);
7258 if (nregno >= FIRST_PSEUDO_REGISTER)
7260 rtx src_reg, store_insn = NULL_RTX;
7262 reg_last_reload_reg[nregno] = 0;
7264 /* If we can find a hard register that is stored, record
7265 the storing insn so that we may delete this insn with
7266 delete_output_reload. */
7267 src_reg = rld[r].reg_rtx;
7269 /* If this is an optional reload, try to find the source reg
7270 from an input reload. */
7273 rtx set = single_set (insn);
7274 if (set && SET_DEST (set) == rld[r].out)
7278 src_reg = SET_SRC (set);
7280 for (k = 0; k < n_reloads; k++)
7282 if (rld[k].in == src_reg)
7284 src_reg = rld[k].reg_rtx;
7291 store_insn = new_spill_reg_store[REGNO (src_reg)];
7292 if (src_reg && REG_P (src_reg)
7293 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7295 int src_regno = REGNO (src_reg);
7296 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7297 /* The place where to find a death note varies with
7298 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7299 necessarily checked exactly in the code that moves
7300 notes, so just check both locations. */
7301 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7302 if (! note && store_insn)
7303 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7306 spill_reg_store[src_regno + nr] = store_insn;
7307 spill_reg_stored_to[src_regno + nr] = out;
7308 reg_reloaded_contents[src_regno + nr] = nregno;
7309 reg_reloaded_insn[src_regno + nr] = store_insn;
7310 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7311 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7312 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7313 GET_MODE (src_reg)))
7314 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7316 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7318 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7320 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7322 reg_last_reload_reg[nregno] = src_reg;
7323 /* We have to set reg_has_output_reload here, or else
7324 forget_old_reloads_1 will clear reg_last_reload_reg
7326 reg_has_output_reload[nregno] = 1;
7331 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7333 while (num_regs-- > 0)
7334 reg_last_reload_reg[nregno + num_regs] = 0;
7338 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7341 /* Emit code to perform a reload from IN (which may be a reload register) to
7342 OUT (which may also be a reload register). IN or OUT is from operand
7343 OPNUM with reload type TYPE.
7345 Returns first insn emitted. */
7348 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7350 rtx last = get_last_insn ();
7353 /* If IN is a paradoxical SUBREG, remove it and try to put the
7354 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7355 if (GET_CODE (in) == SUBREG
7356 && (GET_MODE_SIZE (GET_MODE (in))
7357 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7358 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7359 in = SUBREG_REG (in), out = tem;
7360 else if (GET_CODE (out) == SUBREG
7361 && (GET_MODE_SIZE (GET_MODE (out))
7362 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7363 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7364 out = SUBREG_REG (out), in = tem;
7366 /* How to do this reload can get quite tricky. Normally, we are being
7367 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7368 register that didn't get a hard register. In that case we can just
7369 call emit_move_insn.
7371 We can also be asked to reload a PLUS that adds a register or a MEM to
7372 another register, constant or MEM. This can occur during frame pointer
7373 elimination and while reloading addresses. This case is handled by
7374 trying to emit a single insn to perform the add. If it is not valid,
7375 we use a two insn sequence.
7377 Finally, we could be called to handle an 'o' constraint by putting
7378 an address into a register. In that case, we first try to do this
7379 with a named pattern of "reload_load_address". If no such pattern
7380 exists, we just emit a SET insn and hope for the best (it will normally
7381 be valid on machines that use 'o').
7383 This entire process is made complex because reload will never
7384 process the insns we generate here and so we must ensure that
7385 they will fit their constraints and also by the fact that parts of
7386 IN might be being reloaded separately and replaced with spill registers.
7387 Because of this, we are, in some sense, just guessing the right approach
7388 here. The one listed above seems to work.
7390 ??? At some point, this whole thing needs to be rethought. */
7392 if (GET_CODE (in) == PLUS
7393 && (REG_P (XEXP (in, 0))
7394 || GET_CODE (XEXP (in, 0)) == SUBREG
7395 || MEM_P (XEXP (in, 0)))
7396 && (REG_P (XEXP (in, 1))
7397 || GET_CODE (XEXP (in, 1)) == SUBREG
7398 || CONSTANT_P (XEXP (in, 1))
7399 || MEM_P (XEXP (in, 1))))
7401 /* We need to compute the sum of a register or a MEM and another
7402 register, constant, or MEM, and put it into the reload
7403 register. The best possible way of doing this is if the machine
7404 has a three-operand ADD insn that accepts the required operands.
7406 The simplest approach is to try to generate such an insn and see if it
7407 is recognized and matches its constraints. If so, it can be used.
7409 It might be better not to actually emit the insn unless it is valid,
7410 but we need to pass the insn as an operand to `recog' and
7411 `extract_insn' and it is simpler to emit and then delete the insn if
7412 not valid than to dummy things up. */
7414 rtx op0, op1, tem, insn;
7417 op0 = find_replacement (&XEXP (in, 0));
7418 op1 = find_replacement (&XEXP (in, 1));
7420 /* Since constraint checking is strict, commutativity won't be
7421 checked, so we need to do that here to avoid spurious failure
7422 if the add instruction is two-address and the second operand
7423 of the add is the same as the reload reg, which is frequently
7424 the case. If the insn would be A = B + A, rearrange it so
7425 it will be A = A + B as constrain_operands expects. */
7427 if (REG_P (XEXP (in, 1))
7428 && REGNO (out) == REGNO (XEXP (in, 1)))
7429 tem = op0, op0 = op1, op1 = tem;
7431 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7432 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7434 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7435 code = recog_memoized (insn);
7439 extract_insn (insn);
7440 /* We want constrain operands to treat this insn strictly in
7441 its validity determination, i.e., the way it would after reload
7443 if (constrain_operands (1))
7447 delete_insns_since (last);
7449 /* If that failed, we must use a conservative two-insn sequence.
7451 Use a move to copy one operand into the reload register. Prefer
7452 to reload a constant, MEM or pseudo since the move patterns can
7453 handle an arbitrary operand. If OP1 is not a constant, MEM or
7454 pseudo and OP1 is not a valid operand for an add instruction, then
7457 After reloading one of the operands into the reload register, add
7458 the reload register to the output register.
7460 If there is another way to do this for a specific machine, a
7461 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7464 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7466 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7468 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7469 || (code != CODE_FOR_nothing
7470 && ! ((*insn_data[code].operand[2].predicate)
7471 (op1, insn_data[code].operand[2].mode))))
7472 tem = op0, op0 = op1, op1 = tem;
7474 gen_reload (out, op0, opnum, type);
7476 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7477 This fixes a problem on the 32K where the stack pointer cannot
7478 be used as an operand of an add insn. */
7480 if (rtx_equal_p (op0, op1))
7483 insn = emit_insn (gen_add2_insn (out, op1));
7485 /* If that failed, copy the address register to the reload register.
7486 Then add the constant to the reload register. */
7488 code = recog_memoized (insn);
7492 extract_insn (insn);
7493 /* We want constrain operands to treat this insn strictly in
7494 its validity determination, i.e., the way it would after reload
7496 if (constrain_operands (1))
7498 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7500 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7505 delete_insns_since (last);
7507 gen_reload (out, op1, opnum, type);
7508 insn = emit_insn (gen_add2_insn (out, op0));
7509 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7512 #ifdef SECONDARY_MEMORY_NEEDED
7513 /* If we need a memory location to do the move, do it that way. */
7514 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7515 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7516 && (REG_P (out) || GET_CODE (out) == SUBREG)
7517 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7518 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7519 REGNO_REG_CLASS (reg_or_subregno (out)),
7522 /* Get the memory to use and rewrite both registers to its mode. */
7523 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7525 if (GET_MODE (loc) != GET_MODE (out))
7526 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7528 if (GET_MODE (loc) != GET_MODE (in))
7529 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7531 gen_reload (loc, in, opnum, type);
7532 gen_reload (out, loc, opnum, type);
7536 /* If IN is a simple operand, use gen_move_insn. */
7537 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7538 emit_insn (gen_move_insn (out, in));
7540 #ifdef HAVE_reload_load_address
7541 else if (HAVE_reload_load_address)
7542 emit_insn (gen_reload_load_address (out, in));
7545 /* Otherwise, just write (set OUT IN) and hope for the best. */
7547 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7549 /* Return the first insn emitted.
7550 We can not just return get_last_insn, because there may have
7551 been multiple instructions emitted. Also note that gen_move_insn may
7552 emit more than one insn itself, so we can not assume that there is one
7553 insn emitted per emit_insn_before call. */
7555 return last ? NEXT_INSN (last) : get_insns ();
7558 /* Delete a previously made output-reload whose result we now believe
7559 is not needed. First we double-check.
7561 INSN is the insn now being processed.
7562 LAST_RELOAD_REG is the hard register number for which we want to delete
7563 the last output reload.
7564 J is the reload-number that originally used REG. The caller has made
7565 certain that reload J doesn't use REG any longer for input. */
7568 delete_output_reload (rtx insn, int j, int last_reload_reg)
7570 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7571 rtx reg = spill_reg_stored_to[last_reload_reg];
7574 int n_inherited = 0;
7578 /* It is possible that this reload has been only used to set another reload
7579 we eliminated earlier and thus deleted this instruction too. */
7580 if (INSN_DELETED_P (output_reload_insn))
7583 /* Get the raw pseudo-register referred to. */
7585 while (GET_CODE (reg) == SUBREG)
7586 reg = SUBREG_REG (reg);
7587 substed = reg_equiv_memory_loc[REGNO (reg)];
7589 /* This is unsafe if the operand occurs more often in the current
7590 insn than it is inherited. */
7591 for (k = n_reloads - 1; k >= 0; k--)
7593 rtx reg2 = rld[k].in;
7596 if (MEM_P (reg2) || reload_override_in[k])
7597 reg2 = rld[k].in_reg;
7599 if (rld[k].out && ! rld[k].out_reg)
7600 reg2 = XEXP (rld[k].in_reg, 0);
7602 while (GET_CODE (reg2) == SUBREG)
7603 reg2 = SUBREG_REG (reg2);
7604 if (rtx_equal_p (reg2, reg))
7606 if (reload_inherited[k] || reload_override_in[k] || k == j)
7609 reg2 = rld[k].out_reg;
7612 while (GET_CODE (reg2) == SUBREG)
7613 reg2 = XEXP (reg2, 0);
7614 if (rtx_equal_p (reg2, reg))
7621 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7623 n_occurrences += count_occurrences (PATTERN (insn),
7624 eliminate_regs (substed, 0,
7626 if (n_occurrences > n_inherited)
7629 /* If the pseudo-reg we are reloading is no longer referenced
7630 anywhere between the store into it and here,
7631 and no jumps or labels intervene, then the value can get
7632 here through the reload reg alone.
7633 Otherwise, give up--return. */
7634 for (i1 = NEXT_INSN (output_reload_insn);
7635 i1 != insn; i1 = NEXT_INSN (i1))
7637 if (LABEL_P (i1) || JUMP_P (i1))
7639 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7640 && reg_mentioned_p (reg, PATTERN (i1)))
7642 /* If this is USE in front of INSN, we only have to check that
7643 there are no more references than accounted for by inheritance. */
7644 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7646 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7647 i1 = NEXT_INSN (i1);
7649 if (n_occurrences <= n_inherited && i1 == insn)
7655 /* We will be deleting the insn. Remove the spill reg information. */
7656 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7658 spill_reg_store[last_reload_reg + k] = 0;
7659 spill_reg_stored_to[last_reload_reg + k] = 0;
7662 /* The caller has already checked that REG dies or is set in INSN.
7663 It has also checked that we are optimizing, and thus some
7664 inaccuracies in the debugging information are acceptable.
7665 So we could just delete output_reload_insn. But in some cases
7666 we can improve the debugging information without sacrificing
7667 optimization - maybe even improving the code: See if the pseudo
7668 reg has been completely replaced with reload regs. If so, delete
7669 the store insn and forget we had a stack slot for the pseudo. */
7670 if (rld[j].out != rld[j].in
7671 && REG_N_DEATHS (REGNO (reg)) == 1
7672 && REG_N_SETS (REGNO (reg)) == 1
7673 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7674 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7678 /* We know that it was used only between here and the beginning of
7679 the current basic block. (We also know that the last use before
7680 INSN was the output reload we are thinking of deleting, but never
7681 mind that.) Search that range; see if any ref remains. */
7682 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7684 rtx set = single_set (i2);
7686 /* Uses which just store in the pseudo don't count,
7687 since if they are the only uses, they are dead. */
7688 if (set != 0 && SET_DEST (set) == reg)
7693 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7694 && reg_mentioned_p (reg, PATTERN (i2)))
7696 /* Some other ref remains; just delete the output reload we
7698 delete_address_reloads (output_reload_insn, insn);
7699 delete_insn (output_reload_insn);
7704 /* Delete the now-dead stores into this pseudo. Note that this
7705 loop also takes care of deleting output_reload_insn. */
7706 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7708 rtx set = single_set (i2);
7710 if (set != 0 && SET_DEST (set) == reg)
7712 delete_address_reloads (i2, insn);
7720 /* For the debugging info, say the pseudo lives in this reload reg. */
7721 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7722 alter_reg (REGNO (reg), -1);
7726 delete_address_reloads (output_reload_insn, insn);
7727 delete_insn (output_reload_insn);
7731 /* We are going to delete DEAD_INSN. Recursively delete loads of
7732 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7733 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7735 delete_address_reloads (rtx dead_insn, rtx current_insn)
7737 rtx set = single_set (dead_insn);
7738 rtx set2, dst, prev, next;
7741 rtx dst = SET_DEST (set);
7743 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7745 /* If we deleted the store from a reloaded post_{in,de}c expression,
7746 we can delete the matching adds. */
7747 prev = PREV_INSN (dead_insn);
7748 next = NEXT_INSN (dead_insn);
7749 if (! prev || ! next)
7751 set = single_set (next);
7752 set2 = single_set (prev);
7754 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7755 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7756 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7758 dst = SET_DEST (set);
7759 if (! rtx_equal_p (dst, SET_DEST (set2))
7760 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7761 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7762 || (INTVAL (XEXP (SET_SRC (set), 1))
7763 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7765 delete_related_insns (prev);
7766 delete_related_insns (next);
7769 /* Subfunction of delete_address_reloads: process registers found in X. */
7771 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7773 rtx prev, set, dst, i2;
7775 enum rtx_code code = GET_CODE (x);
7779 const char *fmt = GET_RTX_FORMAT (code);
7780 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7783 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7784 else if (fmt[i] == 'E')
7786 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7787 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7794 if (spill_reg_order[REGNO (x)] < 0)
7797 /* Scan backwards for the insn that sets x. This might be a way back due
7799 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7801 code = GET_CODE (prev);
7802 if (code == CODE_LABEL || code == JUMP_INSN)
7806 if (reg_set_p (x, PATTERN (prev)))
7808 if (reg_referenced_p (x, PATTERN (prev)))
7811 if (! prev || INSN_UID (prev) < reload_first_uid)
7813 /* Check that PREV only sets the reload register. */
7814 set = single_set (prev);
7817 dst = SET_DEST (set);
7819 || ! rtx_equal_p (dst, x))
7821 if (! reg_set_p (dst, PATTERN (dead_insn)))
7823 /* Check if DST was used in a later insn -
7824 it might have been inherited. */
7825 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7831 if (reg_referenced_p (dst, PATTERN (i2)))
7833 /* If there is a reference to the register in the current insn,
7834 it might be loaded in a non-inherited reload. If no other
7835 reload uses it, that means the register is set before
7837 if (i2 == current_insn)
7839 for (j = n_reloads - 1; j >= 0; j--)
7840 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7841 || reload_override_in[j] == dst)
7843 for (j = n_reloads - 1; j >= 0; j--)
7844 if (rld[j].in && rld[j].reg_rtx == dst)
7853 /* If DST is still live at CURRENT_INSN, check if it is used for
7854 any reload. Note that even if CURRENT_INSN sets DST, we still
7855 have to check the reloads. */
7856 if (i2 == current_insn)
7858 for (j = n_reloads - 1; j >= 0; j--)
7859 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7860 || reload_override_in[j] == dst)
7862 /* ??? We can't finish the loop here, because dst might be
7863 allocated to a pseudo in this block if no reload in this
7864 block needs any of the classes containing DST - see
7865 spill_hard_reg. There is no easy way to tell this, so we
7866 have to scan till the end of the basic block. */
7868 if (reg_set_p (dst, PATTERN (i2)))
7872 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7873 reg_reloaded_contents[REGNO (dst)] = -1;
7877 /* Output reload-insns to reload VALUE into RELOADREG.
7878 VALUE is an autoincrement or autodecrement RTX whose operand
7879 is a register or memory location;
7880 so reloading involves incrementing that location.
7881 IN is either identical to VALUE, or some cheaper place to reload from.
7883 INC_AMOUNT is the number to increment or decrement by (always positive).
7884 This cannot be deduced from VALUE.
7886 Return the instruction that stores into RELOADREG. */
7889 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7891 /* REG or MEM to be copied and incremented. */
7892 rtx incloc = XEXP (value, 0);
7893 /* Nonzero if increment after copying. */
7894 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7900 rtx real_in = in == value ? XEXP (in, 0) : in;
7902 /* No hard register is equivalent to this register after
7903 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7904 we could inc/dec that register as well (maybe even using it for
7905 the source), but I'm not sure it's worth worrying about. */
7907 reg_last_reload_reg[REGNO (incloc)] = 0;
7909 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7910 inc_amount = -inc_amount;
7912 inc = GEN_INT (inc_amount);
7914 /* If this is post-increment, first copy the location to the reload reg. */
7915 if (post && real_in != reloadreg)
7916 emit_insn (gen_move_insn (reloadreg, real_in));
7920 /* See if we can directly increment INCLOC. Use a method similar to
7921 that in gen_reload. */
7923 last = get_last_insn ();
7924 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7925 gen_rtx_PLUS (GET_MODE (incloc),
7928 code = recog_memoized (add_insn);
7931 extract_insn (add_insn);
7932 if (constrain_operands (1))
7934 /* If this is a pre-increment and we have incremented the value
7935 where it lives, copy the incremented value to RELOADREG to
7936 be used as an address. */
7939 emit_insn (gen_move_insn (reloadreg, incloc));
7944 delete_insns_since (last);
7947 /* If couldn't do the increment directly, must increment in RELOADREG.
7948 The way we do this depends on whether this is pre- or post-increment.
7949 For pre-increment, copy INCLOC to the reload register, increment it
7950 there, then save back. */
7954 if (in != reloadreg)
7955 emit_insn (gen_move_insn (reloadreg, real_in));
7956 emit_insn (gen_add2_insn (reloadreg, inc));
7957 store = emit_insn (gen_move_insn (incloc, reloadreg));
7962 Because this might be a jump insn or a compare, and because RELOADREG
7963 may not be available after the insn in an input reload, we must do
7964 the incrementation before the insn being reloaded for.
7966 We have already copied IN to RELOADREG. Increment the copy in
7967 RELOADREG, save that back, then decrement RELOADREG so it has
7968 the original value. */
7970 emit_insn (gen_add2_insn (reloadreg, inc));
7971 store = emit_insn (gen_move_insn (incloc, reloadreg));
7972 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7980 add_auto_inc_notes (rtx insn, rtx x)
7982 enum rtx_code code = GET_CODE (x);
7986 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7989 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7993 /* Scan all the operand sub-expressions. */
7994 fmt = GET_RTX_FORMAT (code);
7995 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7998 add_auto_inc_notes (insn, XEXP (x, i));
7999 else if (fmt[i] == 'E')
8000 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8001 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8006 /* Copy EH notes from an insn to its reloads. */
8008 copy_eh_notes (rtx insn, rtx x)
8010 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8013 for (; x != 0; x = NEXT_INSN (x))
8015 if (may_trap_p (PATTERN (x)))
8017 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8023 /* This is used by reload pass, that does emit some instructions after
8024 abnormal calls moving basic block end, but in fact it wants to emit
8025 them on the edge. Looks for abnormal call edges, find backward the
8026 proper call and fix the damage.
8028 Similar handle instructions throwing exceptions internally. */
8030 fixup_abnormal_edges (void)
8032 bool inserted = false;
8040 /* Look for cases we are interested in - calls or instructions causing
8042 FOR_EACH_EDGE (e, ei, bb->succs)
8044 if (e->flags & EDGE_ABNORMAL_CALL)
8046 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8047 == (EDGE_ABNORMAL | EDGE_EH))
8050 if (e && !CALL_P (BB_END (bb))
8051 && !can_throw_internal (BB_END (bb)))
8053 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8055 FOR_EACH_EDGE (e, ei, bb->succs)
8056 if (e->flags & EDGE_FALLTHRU)
8058 /* Get past the new insns generated. Allow notes, as the insns may
8059 be already deleted. */
8060 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8061 && !can_throw_internal (insn)
8062 && insn != BB_HEAD (bb))
8063 insn = PREV_INSN (insn);
8064 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8067 insn = NEXT_INSN (insn);
8068 while (insn && insn != stop)
8070 next = NEXT_INSN (insn);
8075 /* Sometimes there's still the return value USE.
8076 If it's placed after a trapping call (i.e. that
8077 call is the last insn anyway), we have no fallthru
8078 edge. Simply delete this use and don't try to insert
8079 on the non-existent edge. */
8080 if (GET_CODE (PATTERN (insn)) != USE)
8082 /* We're not deleting it, we're moving it. */
8083 INSN_DELETED_P (insn) = 0;
8084 PREV_INSN (insn) = NULL_RTX;
8085 NEXT_INSN (insn) = NULL_RTX;
8087 insert_insn_on_edge (insn, e);
8094 /* We've possibly turned single trapping insn into multiple ones. */
8095 if (flag_non_call_exceptions)
8098 blocks = sbitmap_alloc (last_basic_block);
8099 sbitmap_ones (blocks);
8100 find_many_sub_basic_blocks (blocks);
8103 commit_edge_insertions ();
OSDN Git Service
