1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
27 #include "hard-reg-set.h"
31 #include "insn-config.h"
32 #include "insn-flags.h"
33 #include "insn-codes.h"
38 #include "basic-block.h"
46 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
47 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
85 #ifndef REGISTER_MOVE_COST
86 #define REGISTER_MOVE_COST(x, y) 2
90 #define LOCAL_REGNO(REGNO) 0
93 /* During reload_as_needed, element N contains a REG rtx for the hard reg
94 into which reg N has been reloaded (perhaps for a previous insn). */
95 static rtx *reg_last_reload_reg;
97 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
98 for an output reload that stores into reg N. */
99 static char *reg_has_output_reload;
101 /* Indicates which hard regs are reload-registers for an output reload
102 in the current insn. */
103 static HARD_REG_SET reg_is_output_reload;
105 /* Element N is the constant value to which pseudo reg N is equivalent,
106 or zero if pseudo reg N is not equivalent to a constant.
107 find_reloads looks at this in order to replace pseudo reg N
108 with the constant it stands for. */
109 rtx *reg_equiv_constant;
111 /* Element N is a memory location to which pseudo reg N is equivalent,
112 prior to any register elimination (such as frame pointer to stack
113 pointer). Depending on whether or not it is a valid address, this value
114 is transferred to either reg_equiv_address or reg_equiv_mem. */
115 rtx *reg_equiv_memory_loc;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Widest width in which each pseudo reg is referred to (via subreg). */
127 static unsigned int *reg_max_ref_width;
129 /* Element N is the list of insns that initialized reg N from its equivalent
130 constant or memory slot. */
131 static rtx *reg_equiv_init;
133 /* Vector to remember old contents of reg_renumber before spilling. */
134 static short *reg_old_renumber;
136 /* During reload_as_needed, element N contains the last pseudo regno reloaded
137 into hard register N. If that pseudo reg occupied more than one register,
138 reg_reloaded_contents points to that pseudo for each spill register in
139 use; all of these must remain set for an inheritance to occur. */
140 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
142 /* During reload_as_needed, element N contains the insn for which
143 hard register N was last used. Its contents are significant only
144 when reg_reloaded_valid is set for this register. */
145 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
147 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
148 static HARD_REG_SET reg_reloaded_valid;
149 /* Indicate if the register was dead at the end of the reload.
150 This is only valid if reg_reloaded_contents is set and valid. */
151 static HARD_REG_SET reg_reloaded_dead;
153 /* Number of spill-regs so far; number of valid elements of spill_regs. */
156 /* In parallel with spill_regs, contains REG rtx's for those regs.
157 Holds the last rtx used for any given reg, or 0 if it has never
158 been used for spilling yet. This rtx is reused, provided it has
160 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
162 /* In parallel with spill_regs, contains nonzero for a spill reg
163 that was stored after the last time it was used.
164 The precise value is the insn generated to do the store. */
165 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
167 /* This is the register that was stored with spill_reg_store. This is a
168 copy of reload_out / reload_out_reg when the value was stored; if
169 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
170 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
172 /* This table is the inverse mapping of spill_regs:
173 indexed by hard reg number,
174 it contains the position of that reg in spill_regs,
175 or -1 for something that is not in spill_regs.
177 ?!? This is no longer accurate. */
178 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
180 /* This reg set indicates registers that can't be used as spill registers for
181 the currently processed insn. These are the hard registers which are live
182 during the insn, but not allocated to pseudos, as well as fixed
184 static HARD_REG_SET bad_spill_regs;
186 /* These are the hard registers that can't be used as spill register for any
187 insn. This includes registers used for user variables and registers that
188 we can't eliminate. A register that appears in this set also can't be used
189 to retry register allocation. */
190 static HARD_REG_SET bad_spill_regs_global;
192 /* Describes order of use of registers for reloading
193 of spilled pseudo-registers. `n_spills' is the number of
194 elements that are actually valid; new ones are added at the end.
196 Both spill_regs and spill_reg_order are used on two occasions:
197 once during find_reload_regs, where they keep track of the spill registers
198 for a single insn, but also during reload_as_needed where they show all
199 the registers ever used by reload. For the latter case, the information
200 is calculated during finish_spills. */
201 static short spill_regs[FIRST_PSEUDO_REGISTER];
203 /* This vector of reg sets indicates, for each pseudo, which hard registers
204 may not be used for retrying global allocation because the register was
205 formerly spilled from one of them. If we allowed reallocating a pseudo to
206 a register that it was already allocated to, reload might not
208 static HARD_REG_SET *pseudo_previous_regs;
210 /* This vector of reg sets indicates, for each pseudo, which hard
211 registers may not be used for retrying global allocation because they
212 are used as spill registers during one of the insns in which the
214 static HARD_REG_SET *pseudo_forbidden_regs;
216 /* All hard regs that have been used as spill registers for any insn are
217 marked in this set. */
218 static HARD_REG_SET used_spill_regs;
220 /* Index of last register assigned as a spill register. We allocate in
221 a round-robin fashion. */
222 static int last_spill_reg;
224 /* Nonzero if indirect addressing is supported on the machine; this means
225 that spilling (REG n) does not require reloading it into a register in
226 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
227 value indicates the level of indirect addressing supported, e.g., two
228 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
230 static char spill_indirect_levels;
232 /* Nonzero if indirect addressing is supported when the innermost MEM is
233 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
234 which these are valid is the same as spill_indirect_levels, above. */
235 char indirect_symref_ok;
237 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
238 char double_reg_address_ok;
240 /* Record the stack slot for each spilled hard register. */
241 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
243 /* Width allocated so far for that stack slot. */
244 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
246 /* Record which pseudos needed to be spilled. */
247 static regset_head spilled_pseudos;
249 /* Used for communication between order_regs_for_reload and count_pseudo.
250 Used to avoid counting one pseudo twice. */
251 static regset_head pseudos_counted;
253 /* First uid used by insns created by reload in this function.
254 Used in find_equiv_reg. */
255 int reload_first_uid;
257 /* Flag set by local-alloc or global-alloc if anything is live in
258 a call-clobbered reg across calls. */
259 int caller_save_needed;
261 /* Set to 1 while reload_as_needed is operating.
262 Required by some machines to handle any generated moves differently. */
263 int reload_in_progress = 0;
265 /* These arrays record the insn_code of insns that may be needed to
266 perform input and output reloads of special objects. They provide a
267 place to pass a scratch register. */
268 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
269 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
271 /* This obstack is used for allocation of rtl during register elimination.
272 The allocated storage can be freed once find_reloads has processed the
274 struct obstack reload_obstack;
276 /* Points to the beginning of the reload_obstack. All insn_chain structures
277 are allocated first. */
278 char *reload_startobj;
280 /* The point after all insn_chain structures. Used to quickly deallocate
281 memory allocated in copy_reloads during calculate_needs_all_insns. */
282 char *reload_firstobj;
284 /* This points before all local rtl generated by register elimination.
285 Used to quickly free all memory after processing one insn. */
286 static char *reload_insn_firstobj;
288 #define obstack_chunk_alloc xmalloc
289 #define obstack_chunk_free free
291 /* List of insn_chain instructions, one for every insn that reload needs to
293 struct insn_chain *reload_insn_chain;
296 extern tree current_function_decl;
298 extern union tree_node *current_function_decl;
301 /* List of all insns needing reloads. */
302 static struct insn_chain *insns_need_reload;
304 /* This structure is used to record information about register eliminations.
305 Each array entry describes one possible way of eliminating a register
306 in favor of another. If there is more than one way of eliminating a
307 particular register, the most preferred should be specified first. */
311 int from; /* Register number to be eliminated. */
312 int to; /* Register number used as replacement. */
313 int initial_offset; /* Initial difference between values. */
314 int can_eliminate; /* Non-zero if this elimination can be done. */
315 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
316 insns made by reload. */
317 int offset; /* Current offset between the two regs. */
318 int previous_offset; /* Offset at end of previous insn. */
319 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
320 rtx from_rtx; /* REG rtx for the register to be eliminated.
321 We cannot simply compare the number since
322 we might then spuriously replace a hard
323 register corresponding to a pseudo
324 assigned to the reg to be eliminated. */
325 rtx to_rtx; /* REG rtx for the replacement. */
328 static struct elim_table * reg_eliminate = 0;
330 /* This is an intermediate structure to initialize the table. It has
331 exactly the members provided by ELIMINABLE_REGS. */
332 static struct elim_table_1
336 } reg_eliminate_1[] =
338 /* If a set of eliminable registers was specified, define the table from it.
339 Otherwise, default to the normal case of the frame pointer being
340 replaced by the stack pointer. */
342 #ifdef ELIMINABLE_REGS
345 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
348 #define NUM_ELIMINABLE_REGS (sizeof reg_eliminate_1/sizeof reg_eliminate_1[0])
350 /* Record the number of pending eliminations that have an offset not equal
351 to their initial offset. If non-zero, we use a new copy of each
352 replacement result in any insns encountered. */
353 int num_not_at_initial_offset;
355 /* Count the number of registers that we may be able to eliminate. */
356 static int num_eliminable;
357 /* And the number of registers that are equivalent to a constant that
358 can be eliminated to frame_pointer / arg_pointer + constant. */
359 static int num_eliminable_invariants;
361 /* For each label, we record the offset of each elimination. If we reach
362 a label by more than one path and an offset differs, we cannot do the
363 elimination. This information is indexed by the number of the label.
364 The first table is an array of flags that records whether we have yet
365 encountered a label and the second table is an array of arrays, one
366 entry in the latter array for each elimination. */
368 static char *offsets_known_at;
369 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
371 /* Number of labels in the current function. */
373 static int num_labels;
375 static void maybe_fix_stack_asms PARAMS ((void));
376 static void copy_reloads PARAMS ((struct insn_chain *));
377 static void calculate_needs_all_insns PARAMS ((int));
378 static int find_reg PARAMS ((struct insn_chain *, int,
380 static void find_reload_regs PARAMS ((struct insn_chain *, FILE *));
381 static void select_reload_regs PARAMS ((FILE *));
382 static void delete_caller_save_insns PARAMS ((void));
384 static void spill_failure PARAMS ((rtx, enum reg_class));
385 static void count_spilled_pseudo PARAMS ((int, int, int));
386 static void delete_dead_insn PARAMS ((rtx));
387 static void alter_reg PARAMS ((int, int));
388 static void set_label_offsets PARAMS ((rtx, rtx, int));
389 static void check_eliminable_occurrences PARAMS ((rtx));
390 static void elimination_effects PARAMS ((rtx, enum machine_mode));
391 static int eliminate_regs_in_insn PARAMS ((rtx, int));
392 static void update_eliminable_offsets PARAMS ((void));
393 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
394 static void set_initial_elim_offsets PARAMS ((void));
395 static void verify_initial_elim_offsets PARAMS ((void));
396 static void set_initial_label_offsets PARAMS ((void));
397 static void set_offsets_for_label PARAMS ((rtx));
398 static void init_elim_table PARAMS ((void));
399 static void update_eliminables PARAMS ((HARD_REG_SET *));
400 static void spill_hard_reg PARAMS ((unsigned int, FILE *, int));
401 static int finish_spills PARAMS ((int, FILE *));
402 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
403 static void scan_paradoxical_subregs PARAMS ((rtx));
404 static void count_pseudo PARAMS ((int));
405 static void order_regs_for_reload PARAMS ((struct insn_chain *));
406 static void reload_as_needed PARAMS ((int));
407 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
408 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
409 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
412 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
415 static int reload_reg_free_p PARAMS ((unsigned int, int,
417 static int reload_reg_free_for_value_p PARAMS ((int, int, enum reload_type,
418 rtx, rtx, int, int));
419 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
421 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
423 static void failed_reload PARAMS ((rtx, int));
424 static int set_reload_reg PARAMS ((int, int));
425 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
426 static void choose_reload_regs PARAMS ((struct insn_chain *));
427 static void merge_assigned_reloads PARAMS ((rtx));
428 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
429 struct reload *, rtx, int));
430 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
431 struct reload *, int));
432 static void do_input_reload PARAMS ((struct insn_chain *,
433 struct reload *, int));
434 static void do_output_reload PARAMS ((struct insn_chain *,
435 struct reload *, int));
436 static void emit_reload_insns PARAMS ((struct insn_chain *));
437 static void delete_output_reload PARAMS ((rtx, int, int));
438 static void delete_address_reloads PARAMS ((rtx, rtx));
439 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
440 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
441 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
442 static void reload_cse_regs_1 PARAMS ((rtx));
443 static int reload_cse_noop_set_p PARAMS ((rtx));
444 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
445 static int reload_cse_simplify_operands PARAMS ((rtx));
446 static void reload_combine PARAMS ((void));
447 static void reload_combine_note_use PARAMS ((rtx *, rtx));
448 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
449 static void reload_cse_move2add PARAMS ((rtx));
450 static void move2add_note_store PARAMS ((rtx, rtx, void *));
452 static void add_auto_inc_notes PARAMS ((rtx, rtx));
454 static rtx gen_mode_int PARAMS ((enum machine_mode,
456 static void failed_reload PARAMS ((rtx, int));
457 static int set_reload_reg PARAMS ((int, int));
458 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
459 static void reload_cse_simplify PARAMS ((rtx));
460 extern void dump_needs PARAMS ((struct insn_chain *, FILE *));
462 /* Initialize the reload pass once per compilation. */
469 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
470 Set spill_indirect_levels to the number of levels such addressing is
471 permitted, zero if it is not permitted at all. */
474 = gen_rtx_MEM (Pmode,
477 LAST_VIRTUAL_REGISTER + 1),
479 spill_indirect_levels = 0;
481 while (memory_address_p (QImode, tem))
483 spill_indirect_levels++;
484 tem = gen_rtx_MEM (Pmode, tem);
487 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
489 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
490 indirect_symref_ok = memory_address_p (QImode, tem);
492 /* See if reg+reg is a valid (and offsettable) address. */
494 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
496 tem = gen_rtx_PLUS (Pmode,
497 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
498 gen_rtx_REG (Pmode, i));
500 /* This way, we make sure that reg+reg is an offsettable address. */
501 tem = plus_constant (tem, 4);
503 if (memory_address_p (QImode, tem))
505 double_reg_address_ok = 1;
510 /* Initialize obstack for our rtl allocation. */
511 gcc_obstack_init (&reload_obstack);
512 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
514 INIT_REG_SET (&spilled_pseudos);
515 INIT_REG_SET (&pseudos_counted);
518 /* List of insn chains that are currently unused. */
519 static struct insn_chain *unused_insn_chains = 0;
521 /* Allocate an empty insn_chain structure. */
525 struct insn_chain *c;
527 if (unused_insn_chains == 0)
529 c = (struct insn_chain *)
530 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
531 INIT_REG_SET (&c->live_throughout);
532 INIT_REG_SET (&c->dead_or_set);
536 c = unused_insn_chains;
537 unused_insn_chains = c->next;
539 c->is_caller_save_insn = 0;
540 c->need_operand_change = 0;
546 /* Small utility function to set all regs in hard reg set TO which are
547 allocated to pseudos in regset FROM. */
550 compute_use_by_pseudos (to, from)
556 EXECUTE_IF_SET_IN_REG_SET
557 (from, FIRST_PSEUDO_REGISTER, regno,
559 int r = reg_renumber[regno];
564 /* reload_combine uses the information from
565 BASIC_BLOCK->global_live_at_start, which might still
566 contain registers that have not actually been allocated
567 since they have an equivalence. */
568 if (! reload_completed)
573 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
575 SET_HARD_REG_BIT (*to, r + nregs);
580 /* Global variables used by reload and its subroutines. */
582 /* Set during calculate_needs if an insn needs register elimination. */
583 static int something_needs_elimination;
584 /* Set during calculate_needs if an insn needs an operand changed. */
585 int something_needs_operands_changed;
587 /* Nonzero means we couldn't get enough spill regs. */
590 /* Main entry point for the reload pass.
592 FIRST is the first insn of the function being compiled.
594 GLOBAL nonzero means we were called from global_alloc
595 and should attempt to reallocate any pseudoregs that we
596 displace from hard regs we will use for reloads.
597 If GLOBAL is zero, we do not have enough information to do that,
598 so any pseudo reg that is spilled must go to the stack.
600 DUMPFILE is the global-reg debugging dump file stream, or 0.
601 If it is nonzero, messages are written to it to describe
602 which registers are seized as reload regs, which pseudo regs
603 are spilled from them, and where the pseudo regs are reallocated to.
605 Return value is nonzero if reload failed
606 and we must not do any more for this function. */
609 reload (first, global, dumpfile)
616 register struct elim_table *ep;
618 /* The two pointers used to track the true location of the memory used
619 for label offsets. */
620 char *real_known_ptr = NULL_PTR;
621 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
623 /* Make sure even insns with volatile mem refs are recognizable. */
628 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
630 /* Make sure that the last insn in the chain
631 is not something that needs reloading. */
632 emit_note (NULL_PTR, NOTE_INSN_DELETED);
634 /* Enable find_equiv_reg to distinguish insns made by reload. */
635 reload_first_uid = get_max_uid ();
637 #ifdef SECONDARY_MEMORY_NEEDED
638 /* Initialize the secondary memory table. */
639 clear_secondary_mem ();
642 /* We don't have a stack slot for any spill reg yet. */
643 bzero ((char *) spill_stack_slot, sizeof spill_stack_slot);
644 bzero ((char *) spill_stack_slot_width, sizeof spill_stack_slot_width);
646 /* Initialize the save area information for caller-save, in case some
650 /* Compute which hard registers are now in use
651 as homes for pseudo registers.
652 This is done here rather than (eg) in global_alloc
653 because this point is reached even if not optimizing. */
654 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
657 /* A function that receives a nonlocal goto must save all call-saved
659 if (current_function_has_nonlocal_label)
660 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
661 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
662 regs_ever_live[i] = 1;
664 /* Find all the pseudo registers that didn't get hard regs
665 but do have known equivalent constants or memory slots.
666 These include parameters (known equivalent to parameter slots)
667 and cse'd or loop-moved constant memory addresses.
669 Record constant equivalents in reg_equiv_constant
670 so they will be substituted by find_reloads.
671 Record memory equivalents in reg_mem_equiv so they can
672 be substituted eventually by altering the REG-rtx's. */
674 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
675 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
676 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
677 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
678 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
679 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
680 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
681 bcopy ((PTR) reg_renumber, (PTR) reg_old_renumber, max_regno * sizeof (short));
682 pseudo_forbidden_regs
683 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
685 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
687 CLEAR_HARD_REG_SET (bad_spill_regs_global);
689 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
690 Also find all paradoxical subregs and find largest such for each pseudo.
691 On machines with small register classes, record hard registers that
692 are used for user variables. These can never be used for spills.
693 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
694 caller-saved registers must be marked live. */
696 num_eliminable_invariants = 0;
697 for (insn = first; insn; insn = NEXT_INSN (insn))
699 rtx set = single_set (insn);
701 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
702 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
703 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
704 if (! call_used_regs[i])
705 regs_ever_live[i] = 1;
707 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
709 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
711 #ifdef LEGITIMATE_PIC_OPERAND_P
712 && (! function_invariant_p (XEXP (note, 0))
714 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
718 rtx x = XEXP (note, 0);
719 i = REGNO (SET_DEST (set));
720 if (i > LAST_VIRTUAL_REGISTER)
722 if (GET_CODE (x) == MEM)
724 /* If the operand is a PLUS, the MEM may be shared,
725 so make sure we have an unshared copy here. */
726 if (GET_CODE (XEXP (x, 0)) == PLUS)
729 reg_equiv_memory_loc[i] = x;
731 else if (function_invariant_p (x))
733 if (GET_CODE (x) == PLUS)
735 /* This is PLUS of frame pointer and a constant,
736 and might be shared. Unshare it. */
737 reg_equiv_constant[i] = copy_rtx (x);
738 num_eliminable_invariants++;
740 else if (x == frame_pointer_rtx
741 || x == arg_pointer_rtx)
743 reg_equiv_constant[i] = x;
744 num_eliminable_invariants++;
746 else if (LEGITIMATE_CONSTANT_P (x))
747 reg_equiv_constant[i] = x;
749 reg_equiv_memory_loc[i]
750 = force_const_mem (GET_MODE (SET_DEST (set)), x);
755 /* If this register is being made equivalent to a MEM
756 and the MEM is not SET_SRC, the equivalencing insn
757 is one with the MEM as a SET_DEST and it occurs later.
758 So don't mark this insn now. */
759 if (GET_CODE (x) != MEM
760 || rtx_equal_p (SET_SRC (set), x))
762 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
767 /* If this insn is setting a MEM from a register equivalent to it,
768 this is the equivalencing insn. */
769 else if (set && GET_CODE (SET_DEST (set)) == MEM
770 && GET_CODE (SET_SRC (set)) == REG
771 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
772 && rtx_equal_p (SET_DEST (set),
773 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
774 reg_equiv_init[REGNO (SET_SRC (set))]
775 = gen_rtx_INSN_LIST (VOIDmode, insn,
776 reg_equiv_init[REGNO (SET_SRC (set))]);
779 scan_paradoxical_subregs (PATTERN (insn));
784 num_labels = max_label_num () - get_first_label_num ();
786 /* Allocate the tables used to store offset information at labels. */
787 /* We used to use alloca here, but the size of what it would try to
788 allocate would occasionally cause it to exceed the stack limit and
789 cause a core dump. */
790 real_known_ptr = xmalloc (num_labels);
792 = (int (*)[NUM_ELIMINABLE_REGS])
793 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
795 offsets_known_at = real_known_ptr - get_first_label_num ();
797 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
799 /* Alter each pseudo-reg rtx to contain its hard reg number.
800 Assign stack slots to the pseudos that lack hard regs or equivalents.
801 Do not touch virtual registers. */
803 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
806 /* If we have some registers we think can be eliminated, scan all insns to
807 see if there is an insn that sets one of these registers to something
808 other than itself plus a constant. If so, the register cannot be
809 eliminated. Doing this scan here eliminates an extra pass through the
810 main reload loop in the most common case where register elimination
812 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
813 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
814 || GET_CODE (insn) == CALL_INSN)
815 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
817 maybe_fix_stack_asms ();
819 insns_need_reload = 0;
820 something_needs_elimination = 0;
822 /* Initialize to -1, which means take the first spill register. */
825 /* Spill any hard regs that we know we can't eliminate. */
826 CLEAR_HARD_REG_SET (used_spill_regs);
827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
828 if (! ep->can_eliminate)
829 spill_hard_reg (ep->from, dumpfile, 1);
831 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
832 if (frame_pointer_needed)
833 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, dumpfile, 1);
835 finish_spills (global, dumpfile);
837 /* From now on, we may need to generate moves differently. We may also
838 allow modifications of insns which cause them to not be recognized.
839 Any such modifications will be cleaned up during reload itself. */
840 reload_in_progress = 1;
842 /* This loop scans the entire function each go-round
843 and repeats until one repetition spills no additional hard regs. */
846 int something_changed;
849 HOST_WIDE_INT starting_frame_size;
851 /* Round size of stack frame to stack_alignment_needed. This must be done
852 here because the stack size may be a part of the offset computation
853 for register elimination, and there might have been new stack slots
854 created in the last iteration of this loop. */
855 if (cfun->stack_alignment_needed)
856 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
858 starting_frame_size = get_frame_size ();
860 set_initial_elim_offsets ();
861 set_initial_label_offsets ();
863 /* For each pseudo register that has an equivalent location defined,
864 try to eliminate any eliminable registers (such as the frame pointer)
865 assuming initial offsets for the replacement register, which
868 If the resulting location is directly addressable, substitute
869 the MEM we just got directly for the old REG.
871 If it is not addressable but is a constant or the sum of a hard reg
872 and constant, it is probably not addressable because the constant is
873 out of range, in that case record the address; we will generate
874 hairy code to compute the address in a register each time it is
875 needed. Similarly if it is a hard register, but one that is not
876 valid as an address register.
878 If the location is not addressable, but does not have one of the
879 above forms, assign a stack slot. We have to do this to avoid the
880 potential of producing lots of reloads if, e.g., a location involves
881 a pseudo that didn't get a hard register and has an equivalent memory
882 location that also involves a pseudo that didn't get a hard register.
884 Perhaps at some point we will improve reload_when_needed handling
885 so this problem goes away. But that's very hairy. */
887 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
888 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
890 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
892 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
894 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
895 else if (CONSTANT_P (XEXP (x, 0))
896 || (GET_CODE (XEXP (x, 0)) == REG
897 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
898 || (GET_CODE (XEXP (x, 0)) == PLUS
899 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
900 && (REGNO (XEXP (XEXP (x, 0), 0))
901 < FIRST_PSEUDO_REGISTER)
902 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
903 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
906 /* Make a new stack slot. Then indicate that something
907 changed so we go back and recompute offsets for
908 eliminable registers because the allocation of memory
909 below might change some offset. reg_equiv_{mem,address}
910 will be set up for this pseudo on the next pass around
912 reg_equiv_memory_loc[i] = 0;
913 reg_equiv_init[i] = 0;
918 if (caller_save_needed)
921 /* If we allocated another stack slot, redo elimination bookkeeping. */
922 if (starting_frame_size != get_frame_size ())
925 if (caller_save_needed)
927 save_call_clobbered_regs ();
928 /* That might have allocated new insn_chain structures. */
929 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
932 calculate_needs_all_insns (global);
934 CLEAR_REG_SET (&spilled_pseudos);
937 something_changed = 0;
939 /* If we allocated any new memory locations, make another pass
940 since it might have changed elimination offsets. */
941 if (starting_frame_size != get_frame_size ())
942 something_changed = 1;
945 HARD_REG_SET to_spill;
946 CLEAR_HARD_REG_SET (to_spill);
947 update_eliminables (&to_spill);
948 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
949 if (TEST_HARD_REG_BIT (to_spill, i))
951 spill_hard_reg (i, dumpfile, 1);
954 /* Regardless of the state of spills, if we previously had
955 a register that we thought we could eliminate, but no can
956 not eliminate, we must run another pass.
958 Consider pseudos which have an entry in reg_equiv_* which
959 reference an eliminable register. We must make another pass
960 to update reg_equiv_* so that we do not substitute in the
961 old value from when we thought the elimination could be
963 something_changed = 1;
967 select_reload_regs (dumpfile);
971 if (insns_need_reload != 0 || did_spill)
972 something_changed |= finish_spills (global, dumpfile);
974 if (! something_changed)
977 if (caller_save_needed)
978 delete_caller_save_insns ();
980 obstack_free (&reload_obstack, reload_firstobj);
983 /* If global-alloc was run, notify it of any register eliminations we have
986 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
987 if (ep->can_eliminate)
988 mark_elimination (ep->from, ep->to);
990 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
991 If that insn didn't set the register (i.e., it copied the register to
992 memory), just delete that insn instead of the equivalencing insn plus
993 anything now dead. If we call delete_dead_insn on that insn, we may
994 delete the insn that actually sets the register if the register dies
995 there and that is incorrect. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
999 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1002 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1004 rtx equiv_insn = XEXP (list, 0);
1005 if (GET_CODE (equiv_insn) == NOTE)
1007 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1008 delete_dead_insn (equiv_insn);
1011 PUT_CODE (equiv_insn, NOTE);
1012 NOTE_SOURCE_FILE (equiv_insn) = 0;
1013 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1019 /* Use the reload registers where necessary
1020 by generating move instructions to move the must-be-register
1021 values into or out of the reload registers. */
1023 if (insns_need_reload != 0 || something_needs_elimination
1024 || something_needs_operands_changed)
1026 int old_frame_size = get_frame_size ();
1028 reload_as_needed (global);
1030 if (old_frame_size != get_frame_size ())
1034 verify_initial_elim_offsets ();
1037 /* If we were able to eliminate the frame pointer, show that it is no
1038 longer live at the start of any basic block. If it ls live by
1039 virtue of being in a pseudo, that pseudo will be marked live
1040 and hence the frame pointer will be known to be live via that
1043 if (! frame_pointer_needed)
1044 for (i = 0; i < n_basic_blocks; i++)
1045 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1046 HARD_FRAME_POINTER_REGNUM);
1048 /* Come here (with failure set nonzero) if we can't get enough spill regs
1049 and we decide not to abort about it. */
1052 CLEAR_REG_SET (&spilled_pseudos);
1053 reload_in_progress = 0;
1055 /* Now eliminate all pseudo regs by modifying them into
1056 their equivalent memory references.
1057 The REG-rtx's for the pseudos are modified in place,
1058 so all insns that used to refer to them now refer to memory.
1060 For a reg that has a reg_equiv_address, all those insns
1061 were changed by reloading so that no insns refer to it any longer;
1062 but the DECL_RTL of a variable decl may refer to it,
1063 and if so this causes the debugging info to mention the variable. */
1065 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1070 int is_readonly = 0;
1072 if (reg_equiv_memory_loc[i])
1074 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1075 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1076 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1079 if (reg_equiv_mem[i])
1080 addr = XEXP (reg_equiv_mem[i], 0);
1082 if (reg_equiv_address[i])
1083 addr = reg_equiv_address[i];
1087 if (reg_renumber[i] < 0)
1089 rtx reg = regno_reg_rtx[i];
1090 PUT_CODE (reg, MEM);
1091 XEXP (reg, 0) = addr;
1092 REG_USERVAR_P (reg) = 0;
1093 RTX_UNCHANGING_P (reg) = is_readonly;
1094 MEM_IN_STRUCT_P (reg) = in_struct;
1095 MEM_SCALAR_P (reg) = is_scalar;
1096 /* We have no alias information about this newly created
1098 MEM_ALIAS_SET (reg) = 0;
1100 else if (reg_equiv_mem[i])
1101 XEXP (reg_equiv_mem[i], 0) = addr;
1105 /* We must set reload_completed now since the cleanup_subreg_operands call
1106 below will re-recognize each insn and reload may have generated insns
1107 which are only valid during and after reload. */
1108 reload_completed = 1;
1110 /* Make a pass over all the insns and delete all USEs which we inserted
1111 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1112 notes. Delete all CLOBBER insns that don't refer to the return value
1113 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1114 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1115 and regenerate REG_INC notes that may have been moved around. */
1117 for (insn = first; insn; insn = NEXT_INSN (insn))
1122 if ((GET_CODE (PATTERN (insn)) == USE
1123 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1124 || (GET_CODE (PATTERN (insn)) == CLOBBER
1125 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1126 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1128 PUT_CODE (insn, NOTE);
1129 NOTE_SOURCE_FILE (insn) = 0;
1130 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1134 pnote = ®_NOTES (insn);
1137 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1138 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1139 || REG_NOTE_KIND (*pnote) == REG_INC
1140 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1141 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1142 *pnote = XEXP (*pnote, 1);
1144 pnote = &XEXP (*pnote, 1);
1148 add_auto_inc_notes (insn, PATTERN (insn));
1151 /* And simplify (subreg (reg)) if it appears as an operand. */
1152 cleanup_subreg_operands (insn);
1155 /* If we are doing stack checking, give a warning if this function's
1156 frame size is larger than we expect. */
1157 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1159 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1160 static int verbose_warned = 0;
1162 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1163 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1164 size += UNITS_PER_WORD;
1166 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1168 warning ("frame size too large for reliable stack checking");
1169 if (! verbose_warned)
1171 warning ("try reducing the number of local variables");
1177 /* Indicate that we no longer have known memory locations or constants. */
1178 if (reg_equiv_constant)
1179 free (reg_equiv_constant);
1180 reg_equiv_constant = 0;
1181 if (reg_equiv_memory_loc)
1182 free (reg_equiv_memory_loc);
1183 reg_equiv_memory_loc = 0;
1186 free (real_known_ptr);
1190 free (reg_equiv_mem);
1191 free (reg_equiv_init);
1192 free (reg_equiv_address);
1193 free (reg_max_ref_width);
1194 free (reg_old_renumber);
1195 free (pseudo_previous_regs);
1196 free (pseudo_forbidden_regs);
1198 CLEAR_HARD_REG_SET (used_spill_regs);
1199 for (i = 0; i < n_spills; i++)
1200 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1202 /* Free all the insn_chain structures at once. */
1203 obstack_free (&reload_obstack, reload_startobj);
1204 unused_insn_chains = 0;
1209 /* Yet another special case. Unfortunately, reg-stack forces people to
1210 write incorrect clobbers in asm statements. These clobbers must not
1211 cause the register to appear in bad_spill_regs, otherwise we'll call
1212 fatal_insn later. We clear the corresponding regnos in the live
1213 register sets to avoid this.
1214 The whole thing is rather sick, I'm afraid. */
1217 maybe_fix_stack_asms ()
1220 const char *constraints[MAX_RECOG_OPERANDS];
1221 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1222 struct insn_chain *chain;
1224 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1227 HARD_REG_SET clobbered, allowed;
1230 if (! INSN_P (chain->insn)
1231 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1233 pat = PATTERN (chain->insn);
1234 if (GET_CODE (pat) != PARALLEL)
1237 CLEAR_HARD_REG_SET (clobbered);
1238 CLEAR_HARD_REG_SET (allowed);
1240 /* First, make a mask of all stack regs that are clobbered. */
1241 for (i = 0; i < XVECLEN (pat, 0); i++)
1243 rtx t = XVECEXP (pat, 0, i);
1244 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1245 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1248 /* Get the operand values and constraints out of the insn. */
1249 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1250 constraints, operand_mode);
1252 /* For every operand, see what registers are allowed. */
1253 for (i = 0; i < noperands; i++)
1255 const char *p = constraints[i];
1256 /* For every alternative, we compute the class of registers allowed
1257 for reloading in CLS, and merge its contents into the reg set
1259 int cls = (int) NO_REGS;
1265 if (c == '\0' || c == ',' || c == '#')
1267 /* End of one alternative - mark the regs in the current
1268 class, and reset the class. */
1269 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1274 } while (c != '\0' && c != ',');
1282 case '=': case '+': case '*': case '%': case '?': case '!':
1283 case '0': case '1': case '2': case '3': case '4': case 'm':
1284 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1285 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1286 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1288 #ifdef EXTRA_CONSTRAINT
1289 case 'Q': case 'R': case 'S': case 'T': case 'U':
1294 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1299 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1303 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1308 /* Those of the registers which are clobbered, but allowed by the
1309 constraints, must be usable as reload registers. So clear them
1310 out of the life information. */
1311 AND_HARD_REG_SET (allowed, clobbered);
1312 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1313 if (TEST_HARD_REG_BIT (allowed, i))
1315 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1316 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1323 /* Copy the global variables n_reloads and rld into the corresponding elts
1326 copy_reloads (chain)
1327 struct insn_chain *chain;
1329 chain->n_reloads = n_reloads;
1331 = (struct reload *) obstack_alloc (&reload_obstack,
1332 n_reloads * sizeof (struct reload));
1333 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1334 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1337 /* Walk the chain of insns, and determine for each whether it needs reloads
1338 and/or eliminations. Build the corresponding insns_need_reload list, and
1339 set something_needs_elimination as appropriate. */
1341 calculate_needs_all_insns (global)
1344 struct insn_chain **pprev_reload = &insns_need_reload;
1345 struct insn_chain *chain;
1347 something_needs_elimination = 0;
1349 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1350 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1352 rtx insn = chain->insn;
1354 /* Clear out the shortcuts. */
1355 chain->n_reloads = 0;
1356 chain->need_elim = 0;
1357 chain->need_reload = 0;
1358 chain->need_operand_change = 0;
1360 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1361 include REG_LABEL), we need to see what effects this has on the
1362 known offsets at labels. */
1364 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1365 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1366 set_label_offsets (insn, insn, 0);
1370 rtx old_body = PATTERN (insn);
1371 int old_code = INSN_CODE (insn);
1372 rtx old_notes = REG_NOTES (insn);
1373 int did_elimination = 0;
1374 int operands_changed = 0;
1375 rtx set = single_set (insn);
1377 /* Skip insns that only set an equivalence. */
1378 if (set && GET_CODE (SET_DEST (set)) == REG
1379 && reg_renumber[REGNO (SET_DEST (set))] < 0
1380 && reg_equiv_constant[REGNO (SET_DEST (set))])
1383 /* If needed, eliminate any eliminable registers. */
1384 if (num_eliminable || num_eliminable_invariants)
1385 did_elimination = eliminate_regs_in_insn (insn, 0);
1387 /* Analyze the instruction. */
1388 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1389 global, spill_reg_order);
1391 /* If a no-op set needs more than one reload, this is likely
1392 to be something that needs input address reloads. We
1393 can't get rid of this cleanly later, and it is of no use
1394 anyway, so discard it now.
1395 We only do this when expensive_optimizations is enabled,
1396 since this complements reload inheritance / output
1397 reload deletion, and it can make debugging harder. */
1398 if (flag_expensive_optimizations && n_reloads > 1)
1400 rtx set = single_set (insn);
1402 && SET_SRC (set) == SET_DEST (set)
1403 && GET_CODE (SET_SRC (set)) == REG
1404 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1406 PUT_CODE (insn, NOTE);
1407 NOTE_SOURCE_FILE (insn) = 0;
1408 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1413 update_eliminable_offsets ();
1415 /* Remember for later shortcuts which insns had any reloads or
1416 register eliminations. */
1417 chain->need_elim = did_elimination;
1418 chain->need_reload = n_reloads > 0;
1419 chain->need_operand_change = operands_changed;
1421 /* Discard any register replacements done. */
1422 if (did_elimination)
1424 obstack_free (&reload_obstack, reload_insn_firstobj);
1425 PATTERN (insn) = old_body;
1426 INSN_CODE (insn) = old_code;
1427 REG_NOTES (insn) = old_notes;
1428 something_needs_elimination = 1;
1431 something_needs_operands_changed |= operands_changed;
1435 copy_reloads (chain);
1436 *pprev_reload = chain;
1437 pprev_reload = &chain->next_need_reload;
1444 /* Comparison function for qsort to decide which of two reloads
1445 should be handled first. *P1 and *P2 are the reload numbers. */
1448 reload_reg_class_lower (r1p, r2p)
1452 register int r1 = *(const short *)r1p, r2 = *(const short *)r2p;
1455 /* Consider required reloads before optional ones. */
1456 t = rld[r1].optional - rld[r2].optional;
1460 /* Count all solitary classes before non-solitary ones. */
1461 t = ((reg_class_size[(int) rld[r2].class] == 1)
1462 - (reg_class_size[(int) rld[r1].class] == 1));
1466 /* Aside from solitaires, consider all multi-reg groups first. */
1467 t = rld[r2].nregs - rld[r1].nregs;
1471 /* Consider reloads in order of increasing reg-class number. */
1472 t = (int) rld[r1].class - (int) rld[r2].class;
1476 /* If reloads are equally urgent, sort by reload number,
1477 so that the results of qsort leave nothing to chance. */
1481 /* The cost of spilling each hard reg. */
1482 static int spill_cost[FIRST_PSEUDO_REGISTER];
1484 /* When spilling multiple hard registers, we use SPILL_COST for the first
1485 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1486 only the first hard reg for a multi-reg pseudo. */
1487 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1489 /* Update the spill cost arrays, considering that pseudo REG is live. */
1495 int n_refs = REG_N_REFS (reg);
1496 int r = reg_renumber[reg];
1499 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1500 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1503 SET_REGNO_REG_SET (&pseudos_counted, reg);
1508 spill_add_cost[r] += n_refs;
1510 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1512 spill_cost[r + nregs] += n_refs;
1515 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1516 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1519 order_regs_for_reload (chain)
1520 struct insn_chain *chain;
1523 HARD_REG_SET used_by_pseudos;
1524 HARD_REG_SET used_by_pseudos2;
1526 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1528 memset (spill_cost, 0, sizeof spill_cost);
1529 memset (spill_add_cost, 0, sizeof spill_add_cost);
1531 /* Count number of uses of each hard reg by pseudo regs allocated to it
1532 and then order them by decreasing use. First exclude hard registers
1533 that are live in or across this insn. */
1535 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1536 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1537 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1538 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1540 /* Now find out which pseudos are allocated to it, and update
1542 CLEAR_REG_SET (&pseudos_counted);
1544 EXECUTE_IF_SET_IN_REG_SET
1545 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1549 EXECUTE_IF_SET_IN_REG_SET
1550 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1554 CLEAR_REG_SET (&pseudos_counted);
1557 /* Vector of reload-numbers showing the order in which the reloads should
1559 static short reload_order[MAX_RELOADS];
1561 /* This is used to keep track of the spill regs used in one insn. */
1562 static HARD_REG_SET used_spill_regs_local;
1564 /* We decided to spill hard register SPILLED, which has a size of
1565 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1566 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1567 update SPILL_COST/SPILL_ADD_COST. */
1570 count_spilled_pseudo (spilled, spilled_nregs, reg)
1571 int spilled, spilled_nregs, reg;
1573 int r = reg_renumber[reg];
1574 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1576 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1577 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1580 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1582 spill_add_cost[r] -= REG_N_REFS (reg);
1584 spill_cost[r + nregs] -= REG_N_REFS (reg);
1587 /* Find reload register to use for reload number ORDER. */
1590 find_reg (chain, order, dumpfile)
1591 struct insn_chain *chain;
1595 int rnum = reload_order[order];
1596 struct reload *rl = rld + rnum;
1597 int best_cost = INT_MAX;
1601 HARD_REG_SET not_usable;
1602 HARD_REG_SET used_by_other_reload;
1604 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1605 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1606 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1608 CLEAR_HARD_REG_SET (used_by_other_reload);
1609 for (k = 0; k < order; k++)
1611 int other = reload_order[k];
1613 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1614 for (j = 0; j < rld[other].nregs; j++)
1615 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1618 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1620 unsigned int regno = i;
1622 if (! TEST_HARD_REG_BIT (not_usable, regno)
1623 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1624 && HARD_REGNO_MODE_OK (regno, rl->mode))
1626 int this_cost = spill_cost[regno];
1628 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1630 for (j = 1; j < this_nregs; j++)
1632 this_cost += spill_add_cost[regno + j];
1633 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1634 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1639 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1641 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1643 if (this_cost < best_cost
1644 /* Among registers with equal cost, prefer caller-saved ones, or
1645 use REG_ALLOC_ORDER if it is defined. */
1646 || (this_cost == best_cost
1647 #ifdef REG_ALLOC_ORDER
1648 && (inv_reg_alloc_order[regno]
1649 < inv_reg_alloc_order[best_reg])
1651 && call_used_regs[regno]
1652 && ! call_used_regs[best_reg]
1657 best_cost = this_cost;
1665 fprintf (dumpfile, "Using reg %d for reload %d\n", best_reg, rnum);
1667 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1668 rl->regno = best_reg;
1670 EXECUTE_IF_SET_IN_REG_SET
1671 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1673 count_spilled_pseudo (best_reg, rl->nregs, j);
1676 EXECUTE_IF_SET_IN_REG_SET
1677 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1679 count_spilled_pseudo (best_reg, rl->nregs, j);
1682 for (i = 0; i < rl->nregs; i++)
1684 if (spill_cost[best_reg + i] != 0
1685 || spill_add_cost[best_reg + i] != 0)
1687 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1692 /* Find more reload regs to satisfy the remaining need of an insn, which
1694 Do it by ascending class number, since otherwise a reg
1695 might be spilled for a big class and might fail to count
1696 for a smaller class even though it belongs to that class. */
1699 find_reload_regs (chain, dumpfile)
1700 struct insn_chain *chain;
1705 /* In order to be certain of getting the registers we need,
1706 we must sort the reloads into order of increasing register class.
1707 Then our grabbing of reload registers will parallel the process
1708 that provided the reload registers. */
1709 for (i = 0; i < chain->n_reloads; i++)
1711 /* Show whether this reload already has a hard reg. */
1712 if (chain->rld[i].reg_rtx)
1714 int regno = REGNO (chain->rld[i].reg_rtx);
1715 chain->rld[i].regno = regno;
1717 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1720 chain->rld[i].regno = -1;
1721 reload_order[i] = i;
1724 n_reloads = chain->n_reloads;
1725 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1727 CLEAR_HARD_REG_SET (used_spill_regs_local);
1730 fprintf (dumpfile, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1732 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1734 /* Compute the order of preference for hard registers to spill. */
1736 order_regs_for_reload (chain);
1738 for (i = 0; i < n_reloads; i++)
1740 int r = reload_order[i];
1742 /* Ignore reloads that got marked inoperative. */
1743 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1744 && ! rld[r].optional
1745 && rld[r].regno == -1)
1746 if (! find_reg (chain, i, dumpfile))
1748 spill_failure (chain->insn, rld[r].class);
1754 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1755 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1757 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1761 select_reload_regs (dumpfile)
1764 struct insn_chain *chain;
1766 /* Try to satisfy the needs for each insn. */
1767 for (chain = insns_need_reload; chain != 0;
1768 chain = chain->next_need_reload)
1769 find_reload_regs (chain, dumpfile);
1772 /* Delete all insns that were inserted by emit_caller_save_insns during
1775 delete_caller_save_insns ()
1777 struct insn_chain *c = reload_insn_chain;
1781 while (c != 0 && c->is_caller_save_insn)
1783 struct insn_chain *next = c->next;
1786 if (insn == BLOCK_HEAD (c->block))
1787 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1788 if (insn == BLOCK_END (c->block))
1789 BLOCK_END (c->block) = PREV_INSN (insn);
1790 if (c == reload_insn_chain)
1791 reload_insn_chain = next;
1793 if (NEXT_INSN (insn) != 0)
1794 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1795 if (PREV_INSN (insn) != 0)
1796 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1799 next->prev = c->prev;
1801 c->prev->next = next;
1802 c->next = unused_insn_chains;
1803 unused_insn_chains = c;
1811 /* Handle the failure to find a register to spill.
1812 INSN should be one of the insns which needed this particular spill reg. */
1815 spill_failure (insn, class)
1817 enum reg_class class;
1819 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1820 if (asm_noperands (PATTERN (insn)) >= 0)
1821 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1822 reg_class_names[class]);
1825 error ("Unable to find a register to spill in class `%s'.",
1826 reg_class_names[class]);
1827 fatal_insn ("This is the insn:", insn);
1831 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1832 data that is dead in INSN. */
1835 delete_dead_insn (insn)
1838 rtx prev = prev_real_insn (insn);
1841 /* If the previous insn sets a register that dies in our insn, delete it
1843 if (prev && GET_CODE (PATTERN (prev)) == SET
1844 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1845 && reg_mentioned_p (prev_dest, PATTERN (insn))
1846 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1847 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1848 delete_dead_insn (prev);
1850 PUT_CODE (insn, NOTE);
1851 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1852 NOTE_SOURCE_FILE (insn) = 0;
1855 /* Modify the home of pseudo-reg I.
1856 The new home is present in reg_renumber[I].
1858 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1859 or it may be -1, meaning there is none or it is not relevant.
1860 This is used so that all pseudos spilled from a given hard reg
1861 can share one stack slot. */
1864 alter_reg (i, from_reg)
1868 /* When outputting an inline function, this can happen
1869 for a reg that isn't actually used. */
1870 if (regno_reg_rtx[i] == 0)
1873 /* If the reg got changed to a MEM at rtl-generation time,
1875 if (GET_CODE (regno_reg_rtx[i]) != REG)
1878 /* Modify the reg-rtx to contain the new hard reg
1879 number or else to contain its pseudo reg number. */
1880 REGNO (regno_reg_rtx[i])
1881 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1883 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1884 allocate a stack slot for it. */
1886 if (reg_renumber[i] < 0
1887 && REG_N_REFS (i) > 0
1888 && reg_equiv_constant[i] == 0
1889 && reg_equiv_memory_loc[i] == 0)
1892 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1893 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1896 /* Each pseudo reg has an inherent size which comes from its own mode,
1897 and a total size which provides room for paradoxical subregs
1898 which refer to the pseudo reg in wider modes.
1900 We can use a slot already allocated if it provides both
1901 enough inherent space and enough total space.
1902 Otherwise, we allocate a new slot, making sure that it has no less
1903 inherent space, and no less total space, then the previous slot. */
1906 /* No known place to spill from => no slot to reuse. */
1907 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1908 inherent_size == total_size ? 0 : -1);
1909 if (BYTES_BIG_ENDIAN)
1910 /* Cancel the big-endian correction done in assign_stack_local.
1911 Get the address of the beginning of the slot.
1912 This is so we can do a big-endian correction unconditionally
1914 adjust = inherent_size - total_size;
1916 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1918 /* Nothing can alias this slot except this pseudo. */
1919 MEM_ALIAS_SET (x) = new_alias_set ();
1922 /* Reuse a stack slot if possible. */
1923 else if (spill_stack_slot[from_reg] != 0
1924 && spill_stack_slot_width[from_reg] >= total_size
1925 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1927 x = spill_stack_slot[from_reg];
1929 /* Allocate a bigger slot. */
1932 /* Compute maximum size needed, both for inherent size
1933 and for total size. */
1934 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1937 if (spill_stack_slot[from_reg])
1939 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1941 mode = GET_MODE (spill_stack_slot[from_reg]);
1942 if (spill_stack_slot_width[from_reg] > total_size)
1943 total_size = spill_stack_slot_width[from_reg];
1946 /* Make a slot with that size. */
1947 x = assign_stack_local (mode, total_size,
1948 inherent_size == total_size ? 0 : -1);
1951 /* All pseudos mapped to this slot can alias each other. */
1952 if (spill_stack_slot[from_reg])
1953 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
1955 MEM_ALIAS_SET (x) = new_alias_set ();
1957 if (BYTES_BIG_ENDIAN)
1959 /* Cancel the big-endian correction done in assign_stack_local.
1960 Get the address of the beginning of the slot.
1961 This is so we can do a big-endian correction unconditionally
1963 adjust = GET_MODE_SIZE (mode) - total_size;
1965 stack_slot = gen_rtx_MEM (mode_for_size (total_size
1968 plus_constant (XEXP (x, 0), adjust));
1971 spill_stack_slot[from_reg] = stack_slot;
1972 spill_stack_slot_width[from_reg] = total_size;
1975 /* On a big endian machine, the "address" of the slot
1976 is the address of the low part that fits its inherent mode. */
1977 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
1978 adjust += (total_size - inherent_size);
1980 /* If we have any adjustment to make, or if the stack slot is the
1981 wrong mode, make a new stack slot. */
1982 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
1984 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
1985 plus_constant (XEXP (x, 0), adjust));
1987 MEM_COPY_ATTRIBUTES (new, x);
1991 /* Save the stack slot for later. */
1992 reg_equiv_memory_loc[i] = x;
1996 /* Mark the slots in regs_ever_live for the hard regs
1997 used by pseudo-reg number REGNO. */
2000 mark_home_live (regno)
2003 register int i, lim;
2005 i = reg_renumber[regno];
2008 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2010 regs_ever_live[i++] = 1;
2013 /* This function handles the tracking of elimination offsets around branches.
2015 X is a piece of RTL being scanned.
2017 INSN is the insn that it came from, if any.
2019 INITIAL_P is non-zero if we are to set the offset to be the initial
2020 offset and zero if we are setting the offset of the label to be the
2024 set_label_offsets (x, insn, initial_p)
2029 enum rtx_code code = GET_CODE (x);
2032 struct elim_table *p;
2037 if (LABEL_REF_NONLOCAL_P (x))
2042 /* ... fall through ... */
2045 /* If we know nothing about this label, set the desired offsets. Note
2046 that this sets the offset at a label to be the offset before a label
2047 if we don't know anything about the label. This is not correct for
2048 the label after a BARRIER, but is the best guess we can make. If
2049 we guessed wrong, we will suppress an elimination that might have
2050 been possible had we been able to guess correctly. */
2052 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2054 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2055 offsets_at[CODE_LABEL_NUMBER (x)][i]
2056 = (initial_p ? reg_eliminate[i].initial_offset
2057 : reg_eliminate[i].offset);
2058 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2061 /* Otherwise, if this is the definition of a label and it is
2062 preceded by a BARRIER, set our offsets to the known offset of
2066 && (tem = prev_nonnote_insn (insn)) != 0
2067 && GET_CODE (tem) == BARRIER)
2068 set_offsets_for_label (insn);
2070 /* If neither of the above cases is true, compare each offset
2071 with those previously recorded and suppress any eliminations
2072 where the offsets disagree. */
2074 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2075 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2076 != (initial_p ? reg_eliminate[i].initial_offset
2077 : reg_eliminate[i].offset))
2078 reg_eliminate[i].can_eliminate = 0;
2083 set_label_offsets (PATTERN (insn), insn, initial_p);
2085 /* ... fall through ... */
2089 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2090 and hence must have all eliminations at their initial offsets. */
2091 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2092 if (REG_NOTE_KIND (tem) == REG_LABEL)
2093 set_label_offsets (XEXP (tem, 0), insn, 1);
2098 /* Each of the labels in the address vector must be at their initial
2099 offsets. We want the first field for ADDR_VEC and the second
2100 field for ADDR_DIFF_VEC. */
2102 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2103 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2108 /* We only care about setting PC. If the source is not RETURN,
2109 IF_THEN_ELSE, or a label, disable any eliminations not at
2110 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2111 isn't one of those possibilities. For branches to a label,
2112 call ourselves recursively.
2114 Note that this can disable elimination unnecessarily when we have
2115 a non-local goto since it will look like a non-constant jump to
2116 someplace in the current function. This isn't a significant
2117 problem since such jumps will normally be when all elimination
2118 pairs are back to their initial offsets. */
2120 if (SET_DEST (x) != pc_rtx)
2123 switch (GET_CODE (SET_SRC (x)))
2130 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2134 tem = XEXP (SET_SRC (x), 1);
2135 if (GET_CODE (tem) == LABEL_REF)
2136 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2137 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2140 tem = XEXP (SET_SRC (x), 2);
2141 if (GET_CODE (tem) == LABEL_REF)
2142 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2143 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2151 /* If we reach here, all eliminations must be at their initial
2152 offset because we are doing a jump to a variable address. */
2153 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2154 if (p->offset != p->initial_offset)
2155 p->can_eliminate = 0;
2163 /* Scan X and replace any eliminable registers (such as fp) with a
2164 replacement (such as sp), plus an offset.
2166 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2167 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2168 MEM, we are allowed to replace a sum of a register and the constant zero
2169 with the register, which we cannot do outside a MEM. In addition, we need
2170 to record the fact that a register is referenced outside a MEM.
2172 If INSN is an insn, it is the insn containing X. If we replace a REG
2173 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2174 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2175 the REG is being modified.
2177 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2178 That's used when we eliminate in expressions stored in notes.
2179 This means, do not set ref_outside_mem even if the reference
2182 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2183 replacements done assuming all offsets are at their initial values. If
2184 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2185 encounter, return the actual location so that find_reloads will do
2186 the proper thing. */
2189 eliminate_regs (x, mem_mode, insn)
2191 enum machine_mode mem_mode;
2194 enum rtx_code code = GET_CODE (x);
2195 struct elim_table *ep;
2202 if (! current_function_decl)
2221 /* This is only for the benefit of the debugging backends, which call
2222 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2223 removed after CSE. */
2224 new = eliminate_regs (XEXP (x, 0), 0, insn);
2225 if (GET_CODE (new) == MEM)
2226 return XEXP (new, 0);
2232 /* First handle the case where we encounter a bare register that
2233 is eliminable. Replace it with a PLUS. */
2234 if (regno < FIRST_PSEUDO_REGISTER)
2236 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2238 if (ep->from_rtx == x && ep->can_eliminate)
2239 return plus_constant (ep->to_rtx, ep->previous_offset);
2242 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2243 && reg_equiv_constant[regno]
2244 && ! CONSTANT_P (reg_equiv_constant[regno]))
2245 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2249 /* You might think handling MINUS in a manner similar to PLUS is a
2250 good idea. It is not. It has been tried multiple times and every
2251 time the change has had to have been reverted.
2253 Other parts of reload know a PLUS is special (gen_reload for example)
2254 and require special code to handle code a reloaded PLUS operand.
2256 Also consider backends where the flags register is clobbered by a
2257 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2258 lea instruction comes to mind). If we try to reload a MINUS, we
2259 may kill the flags register that was holding a useful value.
2261 So, please before trying to handle MINUS, consider reload as a
2262 whole instead of this little section as well as the backend issues. */
2264 /* If this is the sum of an eliminable register and a constant, rework
2266 if (GET_CODE (XEXP (x, 0)) == REG
2267 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2268 && CONSTANT_P (XEXP (x, 1)))
2270 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2272 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2274 /* The only time we want to replace a PLUS with a REG (this
2275 occurs when the constant operand of the PLUS is the negative
2276 of the offset) is when we are inside a MEM. We won't want
2277 to do so at other times because that would change the
2278 structure of the insn in a way that reload can't handle.
2279 We special-case the commonest situation in
2280 eliminate_regs_in_insn, so just replace a PLUS with a
2281 PLUS here, unless inside a MEM. */
2282 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2283 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2286 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2287 plus_constant (XEXP (x, 1),
2288 ep->previous_offset));
2291 /* If the register is not eliminable, we are done since the other
2292 operand is a constant. */
2296 /* If this is part of an address, we want to bring any constant to the
2297 outermost PLUS. We will do this by doing register replacement in
2298 our operands and seeing if a constant shows up in one of them.
2300 Note that there is no risk of modifying the structure of the insn,
2301 since we only get called for its operands, thus we are either
2302 modifying the address inside a MEM, or something like an address
2303 operand of a load-address insn. */
2306 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2307 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2309 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2311 /* If one side is a PLUS and the other side is a pseudo that
2312 didn't get a hard register but has a reg_equiv_constant,
2313 we must replace the constant here since it may no longer
2314 be in the position of any operand. */
2315 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2316 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2317 && reg_renumber[REGNO (new1)] < 0
2318 && reg_equiv_constant != 0
2319 && reg_equiv_constant[REGNO (new1)] != 0)
2320 new1 = reg_equiv_constant[REGNO (new1)];
2321 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2322 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2323 && reg_renumber[REGNO (new0)] < 0
2324 && reg_equiv_constant[REGNO (new0)] != 0)
2325 new0 = reg_equiv_constant[REGNO (new0)];
2327 new = form_sum (new0, new1);
2329 /* As above, if we are not inside a MEM we do not want to
2330 turn a PLUS into something else. We might try to do so here
2331 for an addition of 0 if we aren't optimizing. */
2332 if (! mem_mode && GET_CODE (new) != PLUS)
2333 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2341 /* If this is the product of an eliminable register and a
2342 constant, apply the distribute law and move the constant out
2343 so that we have (plus (mult ..) ..). This is needed in order
2344 to keep load-address insns valid. This case is pathological.
2345 We ignore the possibility of overflow here. */
2346 if (GET_CODE (XEXP (x, 0)) == REG
2347 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2348 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2349 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2351 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2354 /* Refs inside notes don't count for this purpose. */
2355 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2356 || GET_CODE (insn) == INSN_LIST)))
2357 ep->ref_outside_mem = 1;
2360 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2361 ep->previous_offset * INTVAL (XEXP (x, 1)));
2364 /* ... fall through ... */
2368 /* See comments before PLUS about handling MINUS. */
2370 case DIV: case UDIV:
2371 case MOD: case UMOD:
2372 case AND: case IOR: case XOR:
2373 case ROTATERT: case ROTATE:
2374 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2376 case GE: case GT: case GEU: case GTU:
2377 case LE: case LT: case LEU: case LTU:
2379 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2381 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2383 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2384 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2389 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2392 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2393 if (new != XEXP (x, 0))
2395 /* If this is a REG_DEAD note, it is not valid anymore.
2396 Using the eliminated version could result in creating a
2397 REG_DEAD note for the stack or frame pointer. */
2398 if (GET_MODE (x) == REG_DEAD)
2400 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2403 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2407 /* ... fall through ... */
2410 /* Now do eliminations in the rest of the chain. If this was
2411 an EXPR_LIST, this might result in allocating more memory than is
2412 strictly needed, but it simplifies the code. */
2415 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2416 if (new != XEXP (x, 1))
2417 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2425 case STRICT_LOW_PART:
2427 case SIGN_EXTEND: case ZERO_EXTEND:
2428 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2429 case FLOAT: case FIX:
2430 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2434 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2435 if (new != XEXP (x, 0))
2436 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2440 /* Similar to above processing, but preserve SUBREG_WORD.
2441 Convert (subreg (mem)) to (mem) if not paradoxical.
2442 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2443 pseudo didn't get a hard reg, we must replace this with the
2444 eliminated version of the memory location because push_reloads
2445 may do the replacement in certain circumstances. */
2446 if (GET_CODE (SUBREG_REG (x)) == REG
2447 && (GET_MODE_SIZE (GET_MODE (x))
2448 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2449 && reg_equiv_memory_loc != 0
2450 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2452 new = SUBREG_REG (x);
2455 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2457 if (new != XEXP (x, 0))
2459 int x_size = GET_MODE_SIZE (GET_MODE (x));
2460 int new_size = GET_MODE_SIZE (GET_MODE (new));
2462 if (GET_CODE (new) == MEM
2463 && ((x_size < new_size
2464 #ifdef WORD_REGISTER_OPERATIONS
2465 /* On these machines, combine can create rtl of the form
2466 (set (subreg:m1 (reg:m2 R) 0) ...)
2467 where m1 < m2, and expects something interesting to
2468 happen to the entire word. Moreover, it will use the
2469 (reg:m2 R) later, expecting all bits to be preserved.
2470 So if the number of words is the same, preserve the
2471 subreg so that push_reloads can see it. */
2472 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2475 || (x_size == new_size))
2478 int offset = SUBREG_WORD (x) * UNITS_PER_WORD;
2479 enum machine_mode mode = GET_MODE (x);
2481 if (BYTES_BIG_ENDIAN)
2482 offset += (MIN (UNITS_PER_WORD,
2483 GET_MODE_SIZE (GET_MODE (new)))
2484 - MIN (UNITS_PER_WORD, GET_MODE_SIZE (mode)));
2486 PUT_MODE (new, mode);
2487 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2491 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_WORD (x));
2497 /* This is only for the benefit of the debugging backends, which call
2498 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2499 removed after CSE. */
2500 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2501 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2503 /* Our only special processing is to pass the mode of the MEM to our
2504 recursive call and copy the flags. While we are here, handle this
2505 case more efficiently. */
2506 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2507 if (new != XEXP (x, 0))
2509 new = gen_rtx_MEM (GET_MODE (x), new);
2510 MEM_COPY_ATTRIBUTES (new, x);
2526 /* Process each of our operands recursively. If any have changed, make a
2528 fmt = GET_RTX_FORMAT (code);
2529 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2533 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2534 if (new != XEXP (x, i) && ! copied)
2536 rtx new_x = rtx_alloc (code);
2537 bcopy ((char *) x, (char *) new_x,
2538 (sizeof (*new_x) - sizeof (new_x->fld)
2539 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2545 else if (*fmt == 'E')
2548 for (j = 0; j < XVECLEN (x, i); j++)
2550 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2551 if (new != XVECEXP (x, i, j) && ! copied_vec)
2553 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2557 rtx new_x = rtx_alloc (code);
2558 bcopy ((char *) x, (char *) new_x,
2559 (sizeof (*new_x) - sizeof (new_x->fld)
2560 + (sizeof (new_x->fld[0])
2561 * GET_RTX_LENGTH (code))));
2565 XVEC (x, i) = new_v;
2568 XVECEXP (x, i, j) = new;
2576 /* Scan rtx X for modifications of elimination target registers. Update
2577 the table of eliminables to reflect the changed state. MEM_MODE is
2578 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2581 elimination_effects (x, mem_mode)
2583 enum machine_mode mem_mode;
2586 enum rtx_code code = GET_CODE (x);
2587 struct elim_table *ep;
2613 /* First handle the case where we encounter a bare register that
2614 is eliminable. Replace it with a PLUS. */
2615 if (regno < FIRST_PSEUDO_REGISTER)
2617 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2619 if (ep->from_rtx == x && ep->can_eliminate)
2622 ep->ref_outside_mem = 1;
2627 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2628 && reg_equiv_constant[regno]
2629 && ! CONSTANT_P (reg_equiv_constant[regno]))
2630 elimination_effects (reg_equiv_constant[regno], mem_mode);
2639 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2640 if (ep->to_rtx == XEXP (x, 0))
2642 int size = GET_MODE_SIZE (mem_mode);
2644 /* If more bytes than MEM_MODE are pushed, account for them. */
2645 #ifdef PUSH_ROUNDING
2646 if (ep->to_rtx == stack_pointer_rtx)
2647 size = PUSH_ROUNDING (size);
2649 if (code == PRE_DEC || code == POST_DEC)
2651 else if (code == PRE_INC || code == POST_INC)
2653 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2654 && GET_CODE (XEXP (x, 1)) == PLUS
2655 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2656 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2657 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2660 /* These two aren't unary operators. */
2661 if (code == POST_MODIFY || code == PRE_MODIFY)
2664 /* Fall through to generic unary operation case. */
2665 case STRICT_LOW_PART:
2667 case SIGN_EXTEND: case ZERO_EXTEND:
2668 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2669 case FLOAT: case FIX:
2670 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2674 elimination_effects (XEXP (x, 0), mem_mode);
2678 if (GET_CODE (SUBREG_REG (x)) == REG
2679 && (GET_MODE_SIZE (GET_MODE (x))
2680 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2681 && reg_equiv_memory_loc != 0
2682 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2685 elimination_effects (SUBREG_REG (x), mem_mode);
2689 /* If using a register that is the source of an eliminate we still
2690 think can be performed, note it cannot be performed since we don't
2691 know how this register is used. */
2692 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2693 if (ep->from_rtx == XEXP (x, 0))
2694 ep->can_eliminate = 0;
2696 elimination_effects (XEXP (x, 0), mem_mode);
2700 /* If clobbering a register that is the replacement register for an
2701 elimination we still think can be performed, note that it cannot
2702 be performed. Otherwise, we need not be concerned about it. */
2703 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2704 if (ep->to_rtx == XEXP (x, 0))
2705 ep->can_eliminate = 0;
2707 elimination_effects (XEXP (x, 0), mem_mode);
2711 /* Check for setting a register that we know about. */
2712 if (GET_CODE (SET_DEST (x)) == REG)
2714 /* See if this is setting the replacement register for an
2717 If DEST is the hard frame pointer, we do nothing because we
2718 assume that all assignments to the frame pointer are for
2719 non-local gotos and are being done at a time when they are valid
2720 and do not disturb anything else. Some machines want to
2721 eliminate a fake argument pointer (or even a fake frame pointer)
2722 with either the real frame or the stack pointer. Assignments to
2723 the hard frame pointer must not prevent this elimination. */
2725 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2727 if (ep->to_rtx == SET_DEST (x)
2728 && SET_DEST (x) != hard_frame_pointer_rtx)
2730 /* If it is being incremented, adjust the offset. Otherwise,
2731 this elimination can't be done. */
2732 rtx src = SET_SRC (x);
2734 if (GET_CODE (src) == PLUS
2735 && XEXP (src, 0) == SET_DEST (x)
2736 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2737 ep->offset -= INTVAL (XEXP (src, 1));
2739 ep->can_eliminate = 0;
2743 elimination_effects (SET_DEST (x), 0);
2744 elimination_effects (SET_SRC (x), 0);
2748 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2751 /* Our only special processing is to pass the mode of the MEM to our
2753 elimination_effects (XEXP (x, 0), GET_MODE (x));
2760 fmt = GET_RTX_FORMAT (code);
2761 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2764 elimination_effects (XEXP (x, i), mem_mode);
2765 else if (*fmt == 'E')
2766 for (j = 0; j < XVECLEN (x, i); j++)
2767 elimination_effects (XVECEXP (x, i, j), mem_mode);
2771 /* Descend through rtx X and verify that no references to eliminable registers
2772 remain. If any do remain, mark the involved register as not
2776 check_eliminable_occurrences (x)
2786 code = GET_CODE (x);
2788 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2790 struct elim_table *ep;
2792 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2793 if (ep->from_rtx == x && ep->can_eliminate)
2794 ep->can_eliminate = 0;
2798 fmt = GET_RTX_FORMAT (code);
2799 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2802 check_eliminable_occurrences (XEXP (x, i));
2803 else if (*fmt == 'E')
2806 for (j = 0; j < XVECLEN (x, i); j++)
2807 check_eliminable_occurrences (XVECEXP (x, i, j));
2812 /* Scan INSN and eliminate all eliminable registers in it.
2814 If REPLACE is nonzero, do the replacement destructively. Also
2815 delete the insn as dead it if it is setting an eliminable register.
2817 If REPLACE is zero, do all our allocations in reload_obstack.
2819 If no eliminations were done and this insn doesn't require any elimination
2820 processing (these are not identical conditions: it might be updating sp,
2821 but not referencing fp; this needs to be seen during reload_as_needed so
2822 that the offset between fp and sp can be taken into consideration), zero
2823 is returned. Otherwise, 1 is returned. */
2826 eliminate_regs_in_insn (insn, replace)
2830 int icode = recog_memoized (insn);
2831 rtx old_body = PATTERN (insn);
2832 int insn_is_asm = asm_noperands (old_body) >= 0;
2833 rtx old_set = single_set (insn);
2837 rtx substed_operand[MAX_RECOG_OPERANDS];
2838 rtx orig_operand[MAX_RECOG_OPERANDS];
2839 struct elim_table *ep;
2841 if (! insn_is_asm && icode < 0)
2843 if (GET_CODE (PATTERN (insn)) == USE
2844 || GET_CODE (PATTERN (insn)) == CLOBBER
2845 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2846 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2847 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2853 push_obstacks (&reload_obstack, &reload_obstack);
2855 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2856 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2858 /* Check for setting an eliminable register. */
2859 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2860 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2862 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2863 /* If this is setting the frame pointer register to the
2864 hardware frame pointer register and this is an elimination
2865 that will be done (tested above), this insn is really
2866 adjusting the frame pointer downward to compensate for
2867 the adjustment done before a nonlocal goto. */
2868 if (ep->from == FRAME_POINTER_REGNUM
2869 && ep->to == HARD_FRAME_POINTER_REGNUM)
2871 rtx src = SET_SRC (old_set);
2872 int offset = 0, ok = 0;
2873 rtx prev_insn, prev_set;
2875 if (src == ep->to_rtx)
2877 else if (GET_CODE (src) == PLUS
2878 && GET_CODE (XEXP (src, 0)) == CONST_INT
2879 && XEXP (src, 1) == ep->to_rtx)
2880 offset = INTVAL (XEXP (src, 0)), ok = 1;
2881 else if (GET_CODE (src) == PLUS
2882 && GET_CODE (XEXP (src, 1)) == CONST_INT
2883 && XEXP (src, 0) == ep->to_rtx)
2884 offset = INTVAL (XEXP (src, 1)), ok = 1;
2885 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2886 && (prev_set = single_set (prev_insn)) != 0
2887 && rtx_equal_p (SET_DEST (prev_set), src))
2889 src = SET_SRC (prev_set);
2890 if (src == ep->to_rtx)
2892 else if (GET_CODE (src) == PLUS
2893 && GET_CODE (XEXP (src, 0)) == CONST_INT
2894 && XEXP (src, 1) == ep->to_rtx)
2895 offset = INTVAL (XEXP (src, 0)), ok = 1;
2896 else if (GET_CODE (src) == PLUS
2897 && GET_CODE (XEXP (src, 1)) == CONST_INT
2898 && XEXP (src, 0) == ep->to_rtx)
2899 offset = INTVAL (XEXP (src, 1)), ok = 1;
2907 = plus_constant (ep->to_rtx, offset - ep->offset);
2909 /* First see if this insn remains valid when we
2910 make the change. If not, keep the INSN_CODE
2911 the same and let reload fit it up. */
2912 validate_change (insn, &SET_SRC (old_set), src, 1);
2913 validate_change (insn, &SET_DEST (old_set),
2915 if (! apply_change_group ())
2917 SET_SRC (old_set) = src;
2918 SET_DEST (old_set) = ep->to_rtx;
2928 /* In this case this insn isn't serving a useful purpose. We
2929 will delete it in reload_as_needed once we know that this
2930 elimination is, in fact, being done.
2932 If REPLACE isn't set, we can't delete this insn, but needn't
2933 process it since it won't be used unless something changes. */
2936 delete_dead_insn (insn);
2944 /* We allow one special case which happens to work on all machines we
2945 currently support: a single set with the source being a PLUS of an
2946 eliminable register and a constant. */
2948 && GET_CODE (SET_SRC (old_set)) == PLUS
2949 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
2950 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2951 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2953 rtx reg = XEXP (SET_SRC (old_set), 0);
2954 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
2956 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2957 if (ep->from_rtx == reg && ep->can_eliminate)
2959 offset += ep->offset;
2963 /* We assume here that we don't need a PARALLEL of
2964 any CLOBBERs for this assignment. There's not
2965 much we can do if we do need it. */
2966 PATTERN (insn) = gen_rtx_SET (VOIDmode,
2969 INSN_CODE (insn) = recog (PATTERN (insn), insn, 0);
2970 if (INSN_CODE (insn) < 0)
2975 new_body = old_body;
2978 new_body = copy_insn (old_body);
2979 if (REG_NOTES (insn))
2980 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2982 PATTERN (insn) = new_body;
2983 old_set = single_set (insn);
2985 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
2986 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
2989 /* This can't have an effect on elimination offsets, so skip right
2995 /* Determine the effects of this insn on elimination offsets. */
2996 elimination_effects (old_body, 0);
2998 /* Eliminate all eliminable registers occurring in operands that
2999 can be handled by reload. */
3000 extract_insn (insn);
3002 for (i = 0; i < recog_data.n_operands; i++)
3004 orig_operand[i] = recog_data.operand[i];
3005 substed_operand[i] = recog_data.operand[i];
3007 /* For an asm statement, every operand is eliminable. */
3008 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3010 /* Check for setting a register that we know about. */
3011 if (recog_data.operand_type[i] != OP_IN
3012 && GET_CODE (orig_operand[i]) == REG)
3014 /* If we are assigning to a register that can be eliminated, it
3015 must be as part of a PARALLEL, since the code above handles
3016 single SETs. We must indicate that we can no longer
3017 eliminate this reg. */
3018 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3020 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3021 ep->can_eliminate = 0;
3024 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3025 replace ? insn : NULL_RTX);
3026 if (substed_operand[i] != orig_operand[i])
3027 val = any_changes = 1;
3028 /* Terminate the search in check_eliminable_occurrences at
3030 *recog_data.operand_loc[i] = 0;
3032 /* If an output operand changed from a REG to a MEM and INSN is an
3033 insn, write a CLOBBER insn. */
3034 if (recog_data.operand_type[i] != OP_IN
3035 && GET_CODE (orig_operand[i]) == REG
3036 && GET_CODE (substed_operand[i]) == MEM
3038 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3043 for (i = 0; i < recog_data.n_dups; i++)
3044 *recog_data.dup_loc[i]
3045 = *recog_data.operand_loc[(int)recog_data.dup_num[i]];
3047 /* If any eliminable remain, they aren't eliminable anymore. */
3048 check_eliminable_occurrences (old_body);
3050 /* Substitute the operands; the new values are in the substed_operand
3052 for (i = 0; i < recog_data.n_operands; i++)
3053 *recog_data.operand_loc[i] = substed_operand[i];
3054 for (i = 0; i < recog_data.n_dups; i++)
3055 *recog_data.dup_loc[i] = substed_operand[(int)recog_data.dup_num[i]];
3057 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3058 re-recognize the insn. We do this in case we had a simple addition
3059 but now can do this as a load-address. This saves an insn in this
3061 If re-recognition fails, the old insn code number will still be used,
3062 and some register operands may have changed into PLUS expressions.
3063 These will be handled by find_reloads by loading them into a register
3068 /* If we aren't replacing things permanently and we changed something,
3069 make another copy to ensure that all the RTL is new. Otherwise
3070 things can go wrong if find_reload swaps commutative operands
3071 and one is inside RTL that has been copied while the other is not. */
3072 new_body = old_body;
3075 new_body = copy_insn (old_body);
3076 if (REG_NOTES (insn))
3077 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3079 PATTERN (insn) = new_body;
3081 /* If we had a move insn but now we don't, rerecognize it. This will
3082 cause spurious re-recognition if the old move had a PARALLEL since
3083 the new one still will, but we can't call single_set without
3084 having put NEW_BODY into the insn and the re-recognition won't
3085 hurt in this rare case. */
3086 /* ??? Why this huge if statement - why don't we just rerecognize the
3090 && ((GET_CODE (SET_SRC (old_set)) == REG
3091 && (GET_CODE (new_body) != SET
3092 || GET_CODE (SET_SRC (new_body)) != REG))
3093 /* If this was a load from or store to memory, compare
3094 the MEM in recog_data.operand to the one in the insn.
3095 If they are not equal, then rerecognize the insn. */
3097 && ((GET_CODE (SET_SRC (old_set)) == MEM
3098 && SET_SRC (old_set) != recog_data.operand[1])
3099 || (GET_CODE (SET_DEST (old_set)) == MEM
3100 && SET_DEST (old_set) != recog_data.operand[0])))
3101 /* If this was an add insn before, rerecognize. */
3102 || GET_CODE (SET_SRC (old_set)) == PLUS))
3104 int new_icode = recog (PATTERN (insn), insn, 0);
3106 INSN_CODE (insn) = icode;
3110 /* Restore the old body. If there were any changes to it, we made a copy
3111 of it while the changes were still in place, so we'll correctly return
3112 a modified insn below. */
3115 /* Restore the old body. */
3116 for (i = 0; i < recog_data.n_operands; i++)
3117 *recog_data.operand_loc[i] = orig_operand[i];
3118 for (i = 0; i < recog_data.n_dups; i++)
3119 *recog_data.dup_loc[i] = orig_operand[(int)recog_data.dup_num[i]];
3122 /* Update all elimination pairs to reflect the status after the current
3123 insn. The changes we make were determined by the earlier call to
3124 elimination_effects.
3126 We also detect a cases where register elimination cannot be done,
3127 namely, if a register would be both changed and referenced outside a MEM
3128 in the resulting insn since such an insn is often undefined and, even if
3129 not, we cannot know what meaning will be given to it. Note that it is
3130 valid to have a register used in an address in an insn that changes it
3131 (presumably with a pre- or post-increment or decrement).
3133 If anything changes, return nonzero. */
3135 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3137 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3138 ep->can_eliminate = 0;
3140 ep->ref_outside_mem = 0;
3142 if (ep->previous_offset != ep->offset)
3147 /* If we changed something, perform elimination in REG_NOTES. This is
3148 needed even when REPLACE is zero because a REG_DEAD note might refer
3149 to a register that we eliminate and could cause a different number
3150 of spill registers to be needed in the final reload pass than in
3152 if (val && REG_NOTES (insn) != 0)
3153 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3161 /* Loop through all elimination pairs.
3162 Recalculate the number not at initial offset.
3164 Compute the maximum offset (minimum offset if the stack does not
3165 grow downward) for each elimination pair. */
3168 update_eliminable_offsets ()
3170 struct elim_table *ep;
3172 num_not_at_initial_offset = 0;
3173 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3175 ep->previous_offset = ep->offset;
3176 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3177 num_not_at_initial_offset++;
3181 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3182 replacement we currently believe is valid, mark it as not eliminable if X
3183 modifies DEST in any way other than by adding a constant integer to it.
3185 If DEST is the frame pointer, we do nothing because we assume that
3186 all assignments to the hard frame pointer are nonlocal gotos and are being
3187 done at a time when they are valid and do not disturb anything else.
3188 Some machines want to eliminate a fake argument pointer with either the
3189 frame or stack pointer. Assignments to the hard frame pointer must not
3190 prevent this elimination.
3192 Called via note_stores from reload before starting its passes to scan
3193 the insns of the function. */
3196 mark_not_eliminable (dest, x, data)
3199 void *data ATTRIBUTE_UNUSED;
3201 register unsigned int i;
3203 /* A SUBREG of a hard register here is just changing its mode. We should
3204 not see a SUBREG of an eliminable hard register, but check just in
3206 if (GET_CODE (dest) == SUBREG)
3207 dest = SUBREG_REG (dest);
3209 if (dest == hard_frame_pointer_rtx)
3212 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3213 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3214 && (GET_CODE (x) != SET
3215 || GET_CODE (SET_SRC (x)) != PLUS
3216 || XEXP (SET_SRC (x), 0) != dest
3217 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3219 reg_eliminate[i].can_eliminate_previous
3220 = reg_eliminate[i].can_eliminate = 0;
3225 /* Verify that the initial elimination offsets did not change since the
3226 last call to set_initial_elim_offsets. This is used to catch cases
3227 where something illegal happened during reload_as_needed that could
3228 cause incorrect code to be generated if we did not check for it. */
3231 verify_initial_elim_offsets ()
3235 #ifdef ELIMINABLE_REGS
3236 struct elim_table *ep;
3238 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3240 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3241 if (t != ep->initial_offset)
3245 INITIAL_FRAME_POINTER_OFFSET (t);
3246 if (t != reg_eliminate[0].initial_offset)
3251 /* Reset all offsets on eliminable registers to their initial values. */
3254 set_initial_elim_offsets ()
3256 struct elim_table *ep = reg_eliminate;
3258 #ifdef ELIMINABLE_REGS
3259 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3261 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3262 ep->previous_offset = ep->offset = ep->initial_offset;
3265 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3266 ep->previous_offset = ep->offset = ep->initial_offset;
3269 num_not_at_initial_offset = 0;
3272 /* Initialize the known label offsets.
3273 Set a known offset for each forced label to be at the initial offset
3274 of each elimination. We do this because we assume that all
3275 computed jumps occur from a location where each elimination is
3276 at its initial offset.
3277 For all other labels, show that we don't know the offsets. */
3280 set_initial_label_offsets ()
3283 bzero ((char *) &offsets_known_at[get_first_label_num ()], num_labels);
3285 for (x = forced_labels; x; x = XEXP (x, 1))
3287 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3290 /* Set all elimination offsets to the known values for the code label given
3294 set_offsets_for_label (insn)
3298 int label_nr = CODE_LABEL_NUMBER (insn);
3299 struct elim_table *ep;
3301 num_not_at_initial_offset = 0;
3302 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3304 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3305 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3306 num_not_at_initial_offset++;
3310 /* See if anything that happened changes which eliminations are valid.
3311 For example, on the Sparc, whether or not the frame pointer can
3312 be eliminated can depend on what registers have been used. We need
3313 not check some conditions again (such as flag_omit_frame_pointer)
3314 since they can't have changed. */
3317 update_eliminables (pset)
3320 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3321 int previous_frame_pointer_needed = frame_pointer_needed;
3323 struct elim_table *ep;
3325 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3326 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3327 #ifdef ELIMINABLE_REGS
3328 || ! CAN_ELIMINATE (ep->from, ep->to)
3331 ep->can_eliminate = 0;
3333 /* Look for the case where we have discovered that we can't replace
3334 register A with register B and that means that we will now be
3335 trying to replace register A with register C. This means we can
3336 no longer replace register C with register B and we need to disable
3337 such an elimination, if it exists. This occurs often with A == ap,
3338 B == sp, and C == fp. */
3340 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3342 struct elim_table *op;
3343 register int new_to = -1;
3345 if (! ep->can_eliminate && ep->can_eliminate_previous)
3347 /* Find the current elimination for ep->from, if there is a
3349 for (op = reg_eliminate;
3350 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3351 if (op->from == ep->from && op->can_eliminate)
3357 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3359 for (op = reg_eliminate;
3360 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3361 if (op->from == new_to && op->to == ep->to)
3362 op->can_eliminate = 0;
3366 /* See if any registers that we thought we could eliminate the previous
3367 time are no longer eliminable. If so, something has changed and we
3368 must spill the register. Also, recompute the number of eliminable
3369 registers and see if the frame pointer is needed; it is if there is
3370 no elimination of the frame pointer that we can perform. */
3372 frame_pointer_needed = 1;
3373 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3375 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3376 && ep->to != HARD_FRAME_POINTER_REGNUM)
3377 frame_pointer_needed = 0;
3379 if (! ep->can_eliminate && ep->can_eliminate_previous)
3381 ep->can_eliminate_previous = 0;
3382 SET_HARD_REG_BIT (*pset, ep->from);
3387 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3388 /* If we didn't need a frame pointer last time, but we do now, spill
3389 the hard frame pointer. */
3390 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3391 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3395 /* Initialize the table of registers to eliminate. */
3400 struct elim_table *ep;
3401 #ifdef ELIMINABLE_REGS
3402 struct elim_table_1 *ep1;
3406 reg_eliminate = (struct elim_table *)
3407 xcalloc(sizeof(struct elim_table), NUM_ELIMINABLE_REGS);
3409 /* Does this function require a frame pointer? */
3411 frame_pointer_needed = (! flag_omit_frame_pointer
3412 #ifdef EXIT_IGNORE_STACK
3413 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3414 and restore sp for alloca. So we can't eliminate
3415 the frame pointer in that case. At some point,
3416 we should improve this by emitting the
3417 sp-adjusting insns for this case. */
3418 || (current_function_calls_alloca
3419 && EXIT_IGNORE_STACK)
3421 || FRAME_POINTER_REQUIRED);
3425 #ifdef ELIMINABLE_REGS
3426 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3427 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3429 ep->from = ep1->from;
3431 ep->can_eliminate = ep->can_eliminate_previous
3432 = (CAN_ELIMINATE (ep->from, ep->to)
3433 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3436 reg_eliminate[0].from = reg_eliminate_1[0].from;
3437 reg_eliminate[0].to = reg_eliminate_1[0].to;
3438 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3439 = ! frame_pointer_needed;
3442 /* Count the number of eliminable registers and build the FROM and TO
3443 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3444 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3445 We depend on this. */
3446 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3448 num_eliminable += ep->can_eliminate;
3449 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3450 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3454 /* Kick all pseudos out of hard register REGNO.
3455 If DUMPFILE is nonzero, log actions taken on that file.
3457 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3458 because we found we can't eliminate some register. In the case, no pseudos
3459 are allowed to be in the register, even if they are only in a block that
3460 doesn't require spill registers, unlike the case when we are spilling this
3461 hard reg to produce another spill register.
3463 Return nonzero if any pseudos needed to be kicked out. */
3466 spill_hard_reg (regno, dumpfile, cant_eliminate)
3468 FILE *dumpfile ATTRIBUTE_UNUSED;
3475 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3476 regs_ever_live[regno] = 1;
3479 /* Spill every pseudo reg that was allocated to this reg
3480 or to something that overlaps this reg. */
3482 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3483 if (reg_renumber[i] >= 0
3484 && (unsigned int) reg_renumber[i] <= regno
3485 && ((unsigned int) reg_renumber[i]
3486 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3487 PSEUDO_REGNO_MODE (i))
3489 SET_REGNO_REG_SET (&spilled_pseudos, i);
3492 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3493 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3496 ior_hard_reg_set (set1, set2)
3497 HARD_REG_SET *set1, *set2;
3499 IOR_HARD_REG_SET (*set1, *set2);
3502 /* After find_reload_regs has been run for all insn that need reloads,
3503 and/or spill_hard_regs was called, this function is used to actually
3504 spill pseudo registers and try to reallocate them. It also sets up the
3505 spill_regs array for use by choose_reload_regs. */
3508 finish_spills (global, dumpfile)
3512 struct insn_chain *chain;
3513 int something_changed = 0;
3516 /* Build the spill_regs array for the function. */
3517 /* If there are some registers still to eliminate and one of the spill regs
3518 wasn't ever used before, additional stack space may have to be
3519 allocated to store this register. Thus, we may have changed the offset
3520 between the stack and frame pointers, so mark that something has changed.
3522 One might think that we need only set VAL to 1 if this is a call-used
3523 register. However, the set of registers that must be saved by the
3524 prologue is not identical to the call-used set. For example, the
3525 register used by the call insn for the return PC is a call-used register,
3526 but must be saved by the prologue. */
3529 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3530 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3532 spill_reg_order[i] = n_spills;
3533 spill_regs[n_spills++] = i;
3534 if (num_eliminable && ! regs_ever_live[i])
3535 something_changed = 1;
3536 regs_ever_live[i] = 1;
3539 spill_reg_order[i] = -1;
3541 EXECUTE_IF_SET_IN_REG_SET
3542 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3544 /* Record the current hard register the pseudo is allocated to in
3545 pseudo_previous_regs so we avoid reallocating it to the same
3546 hard reg in a later pass. */
3547 if (reg_renumber[i] < 0)
3550 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3551 /* Mark it as no longer having a hard register home. */
3552 reg_renumber[i] = -1;
3553 /* We will need to scan everything again. */
3554 something_changed = 1;
3557 /* Retry global register allocation if possible. */
3560 bzero ((char *) pseudo_forbidden_regs, max_regno * sizeof (HARD_REG_SET));
3561 /* For every insn that needs reloads, set the registers used as spill
3562 regs in pseudo_forbidden_regs for every pseudo live across the
3564 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3566 EXECUTE_IF_SET_IN_REG_SET
3567 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3569 ior_hard_reg_set (pseudo_forbidden_regs + i,
3570 &chain->used_spill_regs);
3572 EXECUTE_IF_SET_IN_REG_SET
3573 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3575 ior_hard_reg_set (pseudo_forbidden_regs + i,
3576 &chain->used_spill_regs);
3580 /* Retry allocating the spilled pseudos. For each reg, merge the
3581 various reg sets that indicate which hard regs can't be used,
3582 and call retry_global_alloc.
3583 We change spill_pseudos here to only contain pseudos that did not
3584 get a new hard register. */
3585 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3586 if (reg_old_renumber[i] != reg_renumber[i])
3588 HARD_REG_SET forbidden;
3589 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3590 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3591 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3592 retry_global_alloc (i, forbidden);
3593 if (reg_renumber[i] >= 0)
3594 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3598 /* Fix up the register information in the insn chain.
3599 This involves deleting those of the spilled pseudos which did not get
3600 a new hard register home from the live_{before,after} sets. */
3601 for (chain = reload_insn_chain; chain; chain = chain->next)
3603 HARD_REG_SET used_by_pseudos;
3604 HARD_REG_SET used_by_pseudos2;
3606 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3607 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3609 /* Mark any unallocated hard regs as available for spills. That
3610 makes inheritance work somewhat better. */
3611 if (chain->need_reload)
3613 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3614 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3615 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3617 /* Save the old value for the sanity test below. */
3618 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3620 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3621 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3622 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3623 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3625 /* Make sure we only enlarge the set. */
3626 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3632 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3633 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3635 int regno = reg_renumber[i];
3636 if (reg_old_renumber[i] == regno)
3639 alter_reg (i, reg_old_renumber[i]);
3640 reg_old_renumber[i] = regno;
3644 fprintf (dumpfile, " Register %d now on stack.\n\n", i);
3646 fprintf (dumpfile, " Register %d now in %d.\n\n",
3647 i, reg_renumber[i]);
3651 return something_changed;
3654 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3655 Also mark any hard registers used to store user variables as
3656 forbidden from being used for spill registers. */
3659 scan_paradoxical_subregs (x)
3663 register const char *fmt;
3664 register enum rtx_code code = GET_CODE (x);
3670 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3671 && REG_USERVAR_P (x))
3672 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3688 if (GET_CODE (SUBREG_REG (x)) == REG
3689 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3690 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3691 = GET_MODE_SIZE (GET_MODE (x));
3698 fmt = GET_RTX_FORMAT (code);
3699 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3702 scan_paradoxical_subregs (XEXP (x, i));
3703 else if (fmt[i] == 'E')
3706 for (j = XVECLEN (x, i) - 1; j >=0; j--)
3707 scan_paradoxical_subregs (XVECEXP (x, i, j));
3712 /* Reload pseudo-registers into hard regs around each insn as needed.
3713 Additional register load insns are output before the insn that needs it
3714 and perhaps store insns after insns that modify the reloaded pseudo reg.
3716 reg_last_reload_reg and reg_reloaded_contents keep track of
3717 which registers are already available in reload registers.
3718 We update these for the reloads that we perform,
3719 as the insns are scanned. */
3722 reload_as_needed (live_known)
3725 struct insn_chain *chain;
3726 #if defined (AUTO_INC_DEC)
3731 bzero ((char *) spill_reg_rtx, sizeof spill_reg_rtx);
3732 bzero ((char *) spill_reg_store, sizeof spill_reg_store);
3733 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3734 reg_has_output_reload = (char *) xmalloc (max_regno);
3735 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3737 set_initial_elim_offsets ();
3739 for (chain = reload_insn_chain; chain; chain = chain->next)
3742 rtx insn = chain->insn;
3743 rtx old_next = NEXT_INSN (insn);
3745 /* If we pass a label, copy the offsets from the label information
3746 into the current offsets of each elimination. */
3747 if (GET_CODE (insn) == CODE_LABEL)
3748 set_offsets_for_label (insn);
3750 else if (INSN_P (insn))
3752 rtx oldpat = PATTERN (insn);
3754 /* If this is a USE and CLOBBER of a MEM, ensure that any
3755 references to eliminable registers have been removed. */
3757 if ((GET_CODE (PATTERN (insn)) == USE
3758 || GET_CODE (PATTERN (insn)) == CLOBBER)
3759 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3760 XEXP (XEXP (PATTERN (insn), 0), 0)
3761 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3762 GET_MODE (XEXP (PATTERN (insn), 0)),
3765 /* If we need to do register elimination processing, do so.
3766 This might delete the insn, in which case we are done. */
3767 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3769 eliminate_regs_in_insn (insn, 1);
3770 if (GET_CODE (insn) == NOTE)
3772 update_eliminable_offsets ();
3777 /* If need_elim is nonzero but need_reload is zero, one might think
3778 that we could simply set n_reloads to 0. However, find_reloads
3779 could have done some manipulation of the insn (such as swapping
3780 commutative operands), and these manipulations are lost during
3781 the first pass for every insn that needs register elimination.
3782 So the actions of find_reloads must be redone here. */
3784 if (! chain->need_elim && ! chain->need_reload
3785 && ! chain->need_operand_change)
3787 /* First find the pseudo regs that must be reloaded for this insn.
3788 This info is returned in the tables reload_... (see reload.h).
3789 Also modify the body of INSN by substituting RELOAD
3790 rtx's for those pseudo regs. */
3793 bzero (reg_has_output_reload, max_regno);
3794 CLEAR_HARD_REG_SET (reg_is_output_reload);
3796 find_reloads (insn, 1, spill_indirect_levels, live_known,
3800 if (num_eliminable && chain->need_elim)
3801 update_eliminable_offsets ();
3805 rtx next = NEXT_INSN (insn);
3808 prev = PREV_INSN (insn);
3810 /* Now compute which reload regs to reload them into. Perhaps
3811 reusing reload regs from previous insns, or else output
3812 load insns to reload them. Maybe output store insns too.
3813 Record the choices of reload reg in reload_reg_rtx. */
3814 choose_reload_regs (chain);
3816 /* Merge any reloads that we didn't combine for fear of
3817 increasing the number of spill registers needed but now
3818 discover can be safely merged. */
3819 if (SMALL_REGISTER_CLASSES)
3820 merge_assigned_reloads (insn);
3822 /* Generate the insns to reload operands into or out of
3823 their reload regs. */
3824 emit_reload_insns (chain);
3826 /* Substitute the chosen reload regs from reload_reg_rtx
3827 into the insn's body (or perhaps into the bodies of other
3828 load and store insn that we just made for reloading
3829 and that we moved the structure into). */
3832 /* If this was an ASM, make sure that all the reload insns
3833 we have generated are valid. If not, give an error
3836 if (asm_noperands (PATTERN (insn)) >= 0)
3837 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3838 if (p != insn && INSN_P (p)
3839 && (recog_memoized (p) < 0
3840 || (extract_insn (p), ! constrain_operands (1))))
3842 error_for_asm (insn,
3843 "`asm' operand requires impossible reload");
3845 NOTE_SOURCE_FILE (p) = 0;
3846 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3849 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3850 is no longer validly lying around to save a future reload.
3851 Note that this does not detect pseudos that were reloaded
3852 for this insn in order to be stored in
3853 (obeying register constraints). That is correct; such reload
3854 registers ARE still valid. */
3855 note_stores (oldpat, forget_old_reloads_1, NULL);
3857 /* There may have been CLOBBER insns placed after INSN. So scan
3858 between INSN and NEXT and use them to forget old reloads. */
3859 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3860 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3861 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3864 /* Likewise for regs altered by auto-increment in this insn.
3865 REG_INC notes have been changed by reloading:
3866 find_reloads_address_1 records substitutions for them,
3867 which have been performed by subst_reloads above. */
3868 for (i = n_reloads - 1; i >= 0; i--)
3870 rtx in_reg = rld[i].in_reg;
3873 enum rtx_code code = GET_CODE (in_reg);
3874 /* PRE_INC / PRE_DEC will have the reload register ending up
3875 with the same value as the stack slot, but that doesn't
3876 hold true for POST_INC / POST_DEC. Either we have to
3877 convert the memory access to a true POST_INC / POST_DEC,
3878 or we can't use the reload register for inheritance. */
3879 if ((code == POST_INC || code == POST_DEC)
3880 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3881 REGNO (rld[i].reg_rtx))
3882 /* Make sure it is the inc/dec pseudo, and not
3883 some other (e.g. output operand) pseudo. */
3884 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3885 == REGNO (XEXP (in_reg, 0))))
3888 rtx reload_reg = rld[i].reg_rtx;
3889 enum machine_mode mode = GET_MODE (reload_reg);
3893 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3895 /* We really want to ignore REG_INC notes here, so
3896 use PATTERN (p) as argument to reg_set_p . */
3897 if (reg_set_p (reload_reg, PATTERN (p)))
3899 n = count_occurrences (PATTERN (p), reload_reg, 0);
3904 n = validate_replace_rtx (reload_reg,
3905 gen_rtx (code, mode,
3909 /* We must also verify that the constraints
3910 are met after the replacement. */
3913 n = constrain_operands (1);
3917 /* If the constraints were not met, then
3918 undo the replacement. */
3921 validate_replace_rtx (gen_rtx (code, mode,
3933 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3935 /* Mark this as having an output reload so that the
3936 REG_INC processing code below won't invalidate
3937 the reload for inheritance. */
3938 SET_HARD_REG_BIT (reg_is_output_reload,
3939 REGNO (reload_reg));
3940 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3943 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3946 else if ((code == PRE_INC || code == PRE_DEC)
3947 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3948 REGNO (rld[i].reg_rtx))
3949 /* Make sure it is the inc/dec pseudo, and not
3950 some other (e.g. output operand) pseudo. */
3951 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3952 == REGNO (XEXP (in_reg, 0))))
3954 SET_HARD_REG_BIT (reg_is_output_reload,
3955 REGNO (rld[i].reg_rtx));
3956 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3960 /* If a pseudo that got a hard register is auto-incremented,
3961 we must purge records of copying it into pseudos without
3963 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3964 if (REG_NOTE_KIND (x) == REG_INC)
3966 /* See if this pseudo reg was reloaded in this insn.
3967 If so, its last-reload info is still valid
3968 because it is based on this insn's reload. */
3969 for (i = 0; i < n_reloads; i++)
3970 if (rld[i].out == XEXP (x, 0))
3974 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
3978 /* A reload reg's contents are unknown after a label. */
3979 if (GET_CODE (insn) == CODE_LABEL)
3980 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3982 /* Don't assume a reload reg is still good after a call insn
3983 if it is a call-used reg. */
3984 else if (GET_CODE (insn) == CALL_INSN)
3985 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
3989 free (reg_last_reload_reg);
3990 free (reg_has_output_reload);
3993 /* Discard all record of any value reloaded from X,
3994 or reloaded in X from someplace else;
3995 unless X is an output reload reg of the current insn.
3997 X may be a hard reg (the reload reg)
3998 or it may be a pseudo reg that was reloaded from. */
4001 forget_old_reloads_1 (x, ignored, data)
4003 rtx ignored ATTRIBUTE_UNUSED;
4004 void *data ATTRIBUTE_UNUSED;
4010 /* note_stores does give us subregs of hard regs. */
4011 while (GET_CODE (x) == SUBREG)
4013 offset += SUBREG_WORD (x);
4017 if (GET_CODE (x) != REG)
4020 regno = REGNO (x) + offset;
4022 if (regno >= FIRST_PSEUDO_REGISTER)
4028 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4029 /* Storing into a spilled-reg invalidates its contents.
4030 This can happen if a block-local pseudo is allocated to that reg
4031 and it wasn't spilled because this block's total need is 0.
4032 Then some insn might have an optional reload and use this reg. */
4033 for (i = 0; i < nr; i++)
4034 /* But don't do this if the reg actually serves as an output
4035 reload reg in the current instruction. */
4037 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4038 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4041 /* Since value of X has changed,
4042 forget any value previously copied from it. */
4045 /* But don't forget a copy if this is the output reload
4046 that establishes the copy's validity. */
4047 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4048 reg_last_reload_reg[regno + nr] = 0;
4051 /* The following HARD_REG_SETs indicate when each hard register is
4052 used for a reload of various parts of the current insn. */
4054 /* If reg is unavailable for all reloads. */
4055 static HARD_REG_SET reload_reg_unavailable;
4056 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4057 static HARD_REG_SET reload_reg_used;
4058 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4059 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4060 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4061 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4062 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4063 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4064 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4065 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4066 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4067 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4068 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4069 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4070 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4071 static HARD_REG_SET reload_reg_used_in_op_addr;
4072 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4073 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4074 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4075 static HARD_REG_SET reload_reg_used_in_insn;
4076 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4077 static HARD_REG_SET reload_reg_used_in_other_addr;
4079 /* If reg is in use as a reload reg for any sort of reload. */
4080 static HARD_REG_SET reload_reg_used_at_all;
4082 /* If reg is use as an inherited reload. We just mark the first register
4084 static HARD_REG_SET reload_reg_used_for_inherit;
4086 /* Records which hard regs are used in any way, either as explicit use or
4087 by being allocated to a pseudo during any point of the current insn. */
4088 static HARD_REG_SET reg_used_in_insn;
4090 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4091 TYPE. MODE is used to indicate how many consecutive regs are
4095 mark_reload_reg_in_use (regno, opnum, type, mode)
4098 enum reload_type type;
4099 enum machine_mode mode;
4101 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4104 for (i = regno; i < nregs + regno; i++)
4109 SET_HARD_REG_BIT (reload_reg_used, i);
4112 case RELOAD_FOR_INPUT_ADDRESS:
4113 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4116 case RELOAD_FOR_INPADDR_ADDRESS:
4117 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4120 case RELOAD_FOR_OUTPUT_ADDRESS:
4121 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4124 case RELOAD_FOR_OUTADDR_ADDRESS:
4125 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4128 case RELOAD_FOR_OPERAND_ADDRESS:
4129 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4132 case RELOAD_FOR_OPADDR_ADDR:
4133 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4136 case RELOAD_FOR_OTHER_ADDRESS:
4137 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4140 case RELOAD_FOR_INPUT:
4141 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4144 case RELOAD_FOR_OUTPUT:
4145 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4148 case RELOAD_FOR_INSN:
4149 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4153 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4157 /* Similarly, but show REGNO is no longer in use for a reload. */
4160 clear_reload_reg_in_use (regno, opnum, type, mode)
4163 enum reload_type type;
4164 enum machine_mode mode;
4166 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4167 unsigned int start_regno, end_regno, r;
4169 /* A complication is that for some reload types, inheritance might
4170 allow multiple reloads of the same types to share a reload register.
4171 We set check_opnum if we have to check only reloads with the same
4172 operand number, and check_any if we have to check all reloads. */
4173 int check_opnum = 0;
4175 HARD_REG_SET *used_in_set;
4180 used_in_set = &reload_reg_used;
4183 case RELOAD_FOR_INPUT_ADDRESS:
4184 used_in_set = &reload_reg_used_in_input_addr[opnum];
4187 case RELOAD_FOR_INPADDR_ADDRESS:
4189 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4192 case RELOAD_FOR_OUTPUT_ADDRESS:
4193 used_in_set = &reload_reg_used_in_output_addr[opnum];
4196 case RELOAD_FOR_OUTADDR_ADDRESS:
4198 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4201 case RELOAD_FOR_OPERAND_ADDRESS:
4202 used_in_set = &reload_reg_used_in_op_addr;
4205 case RELOAD_FOR_OPADDR_ADDR:
4207 used_in_set = &reload_reg_used_in_op_addr_reload;
4210 case RELOAD_FOR_OTHER_ADDRESS:
4211 used_in_set = &reload_reg_used_in_other_addr;
4215 case RELOAD_FOR_INPUT:
4216 used_in_set = &reload_reg_used_in_input[opnum];
4219 case RELOAD_FOR_OUTPUT:
4220 used_in_set = &reload_reg_used_in_output[opnum];
4223 case RELOAD_FOR_INSN:
4224 used_in_set = &reload_reg_used_in_insn;
4229 /* We resolve conflicts with remaining reloads of the same type by
4230 excluding the intervals of of reload registers by them from the
4231 interval of freed reload registers. Since we only keep track of
4232 one set of interval bounds, we might have to exclude somewhat
4233 more then what would be necessary if we used a HARD_REG_SET here.
4234 But this should only happen very infrequently, so there should
4235 be no reason to worry about it. */
4237 start_regno = regno;
4238 end_regno = regno + nregs;
4239 if (check_opnum || check_any)
4241 for (i = n_reloads - 1; i >= 0; i--)
4243 if (rld[i].when_needed == type
4244 && (check_any || rld[i].opnum == opnum)
4247 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4248 unsigned int conflict_end
4250 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4252 /* If there is an overlap with the first to-be-freed register,
4253 adjust the interval start. */
4254 if (conflict_start <= start_regno && conflict_end > start_regno)
4255 start_regno = conflict_end;
4256 /* Otherwise, if there is a conflict with one of the other
4257 to-be-freed registers, adjust the interval end. */
4258 if (conflict_start > start_regno && conflict_start < end_regno)
4259 end_regno = conflict_start;
4264 for (r = start_regno; r < end_regno; r++)
4265 CLEAR_HARD_REG_BIT (*used_in_set, r);
4268 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4269 specified by OPNUM and TYPE. */
4272 reload_reg_free_p (regno, opnum, type)
4275 enum reload_type type;
4279 /* In use for a RELOAD_OTHER means it's not available for anything. */
4280 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4281 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4287 /* In use for anything means we can't use it for RELOAD_OTHER. */
4288 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4289 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4290 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4293 for (i = 0; i < reload_n_operands; i++)
4294 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4295 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4296 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4297 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4298 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4299 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4304 case RELOAD_FOR_INPUT:
4305 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4306 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4309 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4312 /* If it is used for some other input, can't use it. */
4313 for (i = 0; i < reload_n_operands; i++)
4314 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4317 /* If it is used in a later operand's address, can't use it. */
4318 for (i = opnum + 1; i < reload_n_operands; i++)
4319 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4320 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4325 case RELOAD_FOR_INPUT_ADDRESS:
4326 /* Can't use a register if it is used for an input address for this
4327 operand or used as an input in an earlier one. */
4328 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4329 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4332 for (i = 0; i < opnum; i++)
4333 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4338 case RELOAD_FOR_INPADDR_ADDRESS:
4339 /* Can't use a register if it is used for an input address
4340 for this operand or used as an input in an earlier
4342 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4345 for (i = 0; i < opnum; i++)
4346 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4351 case RELOAD_FOR_OUTPUT_ADDRESS:
4352 /* Can't use a register if it is used for an output address for this
4353 operand or used as an output in this or a later operand. */
4354 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4357 for (i = opnum; i < reload_n_operands; i++)
4358 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4363 case RELOAD_FOR_OUTADDR_ADDRESS:
4364 /* Can't use a register if it is used for an output address
4365 for this operand or used as an output in this or a
4367 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4370 for (i = opnum; i < reload_n_operands; i++)
4371 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4376 case RELOAD_FOR_OPERAND_ADDRESS:
4377 for (i = 0; i < reload_n_operands; i++)
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4381 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4382 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4384 case RELOAD_FOR_OPADDR_ADDR:
4385 for (i = 0; i < reload_n_operands; i++)
4386 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4389 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4391 case RELOAD_FOR_OUTPUT:
4392 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4393 outputs, or an operand address for this or an earlier output. */
4394 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4397 for (i = 0; i < reload_n_operands; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4401 for (i = 0; i <= opnum; i++)
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4403 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4408 case RELOAD_FOR_INSN:
4409 for (i = 0; i < reload_n_operands; i++)
4410 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4411 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4414 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4415 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4417 case RELOAD_FOR_OTHER_ADDRESS:
4418 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4423 /* Return 1 if the value in reload reg REGNO, as used by a reload
4424 needed for the part of the insn specified by OPNUM and TYPE,
4425 is still available in REGNO at the end of the insn.
4427 We can assume that the reload reg was already tested for availability
4428 at the time it is needed, and we should not check this again,
4429 in case the reg has already been marked in use. */
4432 reload_reg_reaches_end_p (regno, opnum, type)
4435 enum reload_type type;
4442 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4443 its value must reach the end. */
4446 /* If this use is for part of the insn,
4447 its value reaches if no subsequent part uses the same register.
4448 Just like the above function, don't try to do this with lots
4451 case RELOAD_FOR_OTHER_ADDRESS:
4452 /* Here we check for everything else, since these don't conflict
4453 with anything else and everything comes later. */
4455 for (i = 0; i < reload_n_operands; i++)
4456 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4457 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4458 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4459 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4460 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4461 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4464 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4465 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4466 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4468 case RELOAD_FOR_INPUT_ADDRESS:
4469 case RELOAD_FOR_INPADDR_ADDRESS:
4470 /* Similar, except that we check only for this and subsequent inputs
4471 and the address of only subsequent inputs and we do not need
4472 to check for RELOAD_OTHER objects since they are known not to
4475 for (i = opnum; i < reload_n_operands; i++)
4476 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4479 for (i = opnum + 1; i < reload_n_operands; i++)
4480 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4481 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4484 for (i = 0; i < reload_n_operands; i++)
4485 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4486 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4490 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4493 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4494 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4496 case RELOAD_FOR_INPUT:
4497 /* Similar to input address, except we start at the next operand for
4498 both input and input address and we do not check for
4499 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4502 for (i = opnum + 1; i < reload_n_operands; i++)
4503 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4504 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4505 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4508 /* ... fall through ... */
4510 case RELOAD_FOR_OPERAND_ADDRESS:
4511 /* Check outputs and their addresses. */
4513 for (i = 0; i < reload_n_operands; i++)
4514 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4515 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4516 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4521 case RELOAD_FOR_OPADDR_ADDR:
4522 for (i = 0; i < reload_n_operands; i++)
4523 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4525 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4528 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4529 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno));
4531 case RELOAD_FOR_INSN:
4532 /* These conflict with other outputs with RELOAD_OTHER. So
4533 we need only check for output addresses. */
4537 /* ... fall through ... */
4539 case RELOAD_FOR_OUTPUT:
4540 case RELOAD_FOR_OUTPUT_ADDRESS:
4541 case RELOAD_FOR_OUTADDR_ADDRESS:
4542 /* We already know these can't conflict with a later output. So the
4543 only thing to check are later output addresses. */
4544 for (i = opnum + 1; i < reload_n_operands; i++)
4545 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4546 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4555 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4558 This function uses the same algorithm as reload_reg_free_p above. */
4561 reloads_conflict (r1, r2)
4564 enum reload_type r1_type = rld[r1].when_needed;
4565 enum reload_type r2_type = rld[r2].when_needed;
4566 int r1_opnum = rld[r1].opnum;
4567 int r2_opnum = rld[r2].opnum;
4569 /* RELOAD_OTHER conflicts with everything. */
4570 if (r2_type == RELOAD_OTHER)
4573 /* Otherwise, check conflicts differently for each type. */
4577 case RELOAD_FOR_INPUT:
4578 return (r2_type == RELOAD_FOR_INSN
4579 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4580 || r2_type == RELOAD_FOR_OPADDR_ADDR
4581 || r2_type == RELOAD_FOR_INPUT
4582 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4583 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4584 && r2_opnum > r1_opnum));
4586 case RELOAD_FOR_INPUT_ADDRESS:
4587 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4588 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4590 case RELOAD_FOR_INPADDR_ADDRESS:
4591 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4592 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4594 case RELOAD_FOR_OUTPUT_ADDRESS:
4595 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4596 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4598 case RELOAD_FOR_OUTADDR_ADDRESS:
4599 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4600 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4602 case RELOAD_FOR_OPERAND_ADDRESS:
4603 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4604 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4606 case RELOAD_FOR_OPADDR_ADDR:
4607 return (r2_type == RELOAD_FOR_INPUT
4608 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4610 case RELOAD_FOR_OUTPUT:
4611 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4612 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4613 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4614 && r2_opnum <= r1_opnum));
4616 case RELOAD_FOR_INSN:
4617 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4618 || r2_type == RELOAD_FOR_INSN
4619 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4621 case RELOAD_FOR_OTHER_ADDRESS:
4622 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4632 /* Indexed by reload number, 1 if incoming value
4633 inherited from previous insns. */
4634 char reload_inherited[MAX_RELOADS];
4636 /* For an inherited reload, this is the insn the reload was inherited from,
4637 if we know it. Otherwise, this is 0. */
4638 rtx reload_inheritance_insn[MAX_RELOADS];
4640 /* If non-zero, this is a place to get the value of the reload,
4641 rather than using reload_in. */
4642 rtx reload_override_in[MAX_RELOADS];
4644 /* For each reload, the hard register number of the register used,
4645 or -1 if we did not need a register for this reload. */
4646 int reload_spill_index[MAX_RELOADS];
4648 /* Return 1 if the value in reload reg REGNO, as used by a reload
4649 needed for the part of the insn specified by OPNUM and TYPE,
4650 may be used to load VALUE into it.
4652 Other read-only reloads with the same value do not conflict
4653 unless OUT is non-zero and these other reloads have to live while
4654 output reloads live.
4655 If OUT is CONST0_RTX, this is a special case: it means that the
4656 test should not be for using register REGNO as reload register, but
4657 for copying from register REGNO into the reload register.
4659 RELOADNUM is the number of the reload we want to load this value for;
4660 a reload does not conflict with itself.
4662 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4663 reloads that load an address for the very reload we are considering.
4665 The caller has to make sure that there is no conflict with the return
4668 reload_reg_free_for_value_p (regno, opnum, type, value, out, reloadnum,
4669 ignore_address_reloads)
4672 enum reload_type type;
4675 int ignore_address_reloads;
4678 /* Set if we see an input reload that must not share its reload register
4679 with any new earlyclobber, but might otherwise share the reload
4680 register with an output or input-output reload. */
4681 int check_earlyclobber = 0;
4685 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4688 if (out == const0_rtx)
4694 /* We use some pseudo 'time' value to check if the lifetimes of the
4695 new register use would overlap with the one of a previous reload
4696 that is not read-only or uses a different value.
4697 The 'time' used doesn't have to be linear in any shape or form, just
4699 Some reload types use different 'buckets' for each operand.
4700 So there are MAX_RECOG_OPERANDS different time values for each
4702 We compute TIME1 as the time when the register for the prospective
4703 new reload ceases to be live, and TIME2 for each existing
4704 reload as the time when that the reload register of that reload
4706 Where there is little to be gained by exact lifetime calculations,
4707 we just make conservative assumptions, i.e. a longer lifetime;
4708 this is done in the 'default:' cases. */
4711 case RELOAD_FOR_OTHER_ADDRESS:
4712 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4713 time1 = copy ? 0 : 1;
4716 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4718 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4719 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4720 respectively, to the time values for these, we get distinct time
4721 values. To get distinct time values for each operand, we have to
4722 multiply opnum by at least three. We round that up to four because
4723 multiply by four is often cheaper. */
4724 case RELOAD_FOR_INPADDR_ADDRESS:
4725 time1 = opnum * 4 + 2;
4727 case RELOAD_FOR_INPUT_ADDRESS:
4728 time1 = opnum * 4 + 3;
4730 case RELOAD_FOR_INPUT:
4731 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4732 executes (inclusive). */
4733 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4735 case RELOAD_FOR_OPADDR_ADDR:
4737 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4738 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4740 case RELOAD_FOR_OPERAND_ADDRESS:
4741 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4743 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4745 case RELOAD_FOR_OUTADDR_ADDRESS:
4746 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4748 case RELOAD_FOR_OUTPUT_ADDRESS:
4749 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4752 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4755 for (i = 0; i < n_reloads; i++)
4757 rtx reg = rld[i].reg_rtx;
4758 if (reg && GET_CODE (reg) == REG
4759 && ((unsigned) regno - true_regnum (reg)
4760 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4763 if (! rld[i].in || ! rtx_equal_p (rld[i].in, value)
4764 || rld[i].out || out)
4767 switch (rld[i].when_needed)
4769 case RELOAD_FOR_OTHER_ADDRESS:
4772 case RELOAD_FOR_INPADDR_ADDRESS:
4773 /* find_reloads makes sure that a
4774 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4775 by at most one - the first -
4776 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4777 address reload is inherited, the address address reload
4778 goes away, so we can ignore this conflict. */
4779 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4780 && ignore_address_reloads
4781 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4782 Then the address address is still needed to store
4783 back the new address. */
4784 && ! rld[reloadnum].out)
4786 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4787 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4789 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4790 && ignore_address_reloads
4791 /* Unless we are reloading an auto_inc expression. */
4792 && ! rld[reloadnum].out)
4794 time2 = rld[i].opnum * 4 + 2;
4796 case RELOAD_FOR_INPUT_ADDRESS:
4797 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4798 && ignore_address_reloads
4799 && ! rld[reloadnum].out)
4801 time2 = rld[i].opnum * 4 + 3;
4803 case RELOAD_FOR_INPUT:
4804 time2 = rld[i].opnum * 4 + 4;
4805 check_earlyclobber = 1;
4807 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4808 == MAX_RECOG_OPERAND * 4 */
4809 case RELOAD_FOR_OPADDR_ADDR:
4810 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4811 && ignore_address_reloads
4812 && ! rld[reloadnum].out)
4814 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4816 case RELOAD_FOR_OPERAND_ADDRESS:
4817 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4818 check_earlyclobber = 1;
4820 case RELOAD_FOR_INSN:
4821 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4823 case RELOAD_FOR_OUTPUT:
4824 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4825 instruction is executed. */
4826 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4828 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4829 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4831 case RELOAD_FOR_OUTADDR_ADDRESS:
4832 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4833 && ignore_address_reloads
4834 && ! rld[reloadnum].out)
4836 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4838 case RELOAD_FOR_OUTPUT_ADDRESS:
4839 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4842 /* If there is no conflict in the input part, handle this
4843 like an output reload. */
4844 if (! rld[i].in || rtx_equal_p (rld[i].in, value))
4846 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4847 /* Earlyclobbered outputs must conflict with inputs. */
4848 if (earlyclobber_operand_p (rld[i].out))
4849 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4854 /* RELOAD_OTHER might be live beyond instruction execution,
4855 but this is not obvious when we set time2 = 1. So check
4856 here if there might be a problem with the new reload
4857 clobbering the register used by the RELOAD_OTHER. */
4865 && (! rld[i].in || rld[i].out
4866 || ! rtx_equal_p (rld[i].in, value)))
4867 || (out && rld[reloadnum].out_reg
4868 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4874 /* Earlyclobbered outputs must conflict with inputs. */
4875 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4881 /* Give an error message saying we failed to find a reload for INSN,
4882 and clear out reload R. */
4884 failed_reload (insn, r)
4888 if (asm_noperands (PATTERN (insn)) < 0)
4889 /* It's the compiler's fault. */
4890 fatal_insn ("Could not find a spill register", insn);
4892 /* It's the user's fault; the operand's mode and constraint
4893 don't match. Disable this reload so we don't crash in final. */
4894 error_for_asm (insn,
4895 "`asm' operand constraint incompatible with operand size");
4899 rld[r].optional = 1;
4900 rld[r].secondary_p = 1;
4903 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
4904 for reload R. If it's valid, get an rtx for it. Return nonzero if
4907 set_reload_reg (i, r)
4911 rtx reg = spill_reg_rtx[i];
4913 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
4914 spill_reg_rtx[i] = reg
4915 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
4917 regno = true_regnum (reg);
4919 /* Detect when the reload reg can't hold the reload mode.
4920 This used to be one `if', but Sequent compiler can't handle that. */
4921 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
4923 enum machine_mode test_mode = VOIDmode;
4925 test_mode = GET_MODE (rld[r].in);
4926 /* If rld[r].in has VOIDmode, it means we will load it
4927 in whatever mode the reload reg has: to wit, rld[r].mode.
4928 We have already tested that for validity. */
4929 /* Aside from that, we need to test that the expressions
4930 to reload from or into have modes which are valid for this
4931 reload register. Otherwise the reload insns would be invalid. */
4932 if (! (rld[r].in != 0 && test_mode != VOIDmode
4933 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
4934 if (! (rld[r].out != 0
4935 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
4937 /* The reg is OK. */
4940 /* Mark as in use for this insn the reload regs we use
4942 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
4943 rld[r].when_needed, rld[r].mode);
4945 rld[r].reg_rtx = reg;
4946 reload_spill_index[r] = spill_regs[i];
4953 /* Find a spill register to use as a reload register for reload R.
4954 LAST_RELOAD is non-zero if this is the last reload for the insn being
4957 Set rld[R].reg_rtx to the register allocated.
4959 We return 1 if successful, or 0 if we couldn't find a spill reg and
4960 we didn't change anything. */
4963 allocate_reload_reg (chain, r, last_reload)
4964 struct insn_chain *chain ATTRIBUTE_UNUSED;
4970 /* If we put this reload ahead, thinking it is a group,
4971 then insist on finding a group. Otherwise we can grab a
4972 reg that some other reload needs.
4973 (That can happen when we have a 68000 DATA_OR_FP_REG
4974 which is a group of data regs or one fp reg.)
4975 We need not be so restrictive if there are no more reloads
4978 ??? Really it would be nicer to have smarter handling
4979 for that kind of reg class, where a problem like this is normal.
4980 Perhaps those classes should be avoided for reloading
4981 by use of more alternatives. */
4983 int force_group = rld[r].nregs > 1 && ! last_reload;
4985 /* If we want a single register and haven't yet found one,
4986 take any reg in the right class and not in use.
4987 If we want a consecutive group, here is where we look for it.
4989 We use two passes so we can first look for reload regs to
4990 reuse, which are already in use for other reloads in this insn,
4991 and only then use additional registers.
4992 I think that maximizing reuse is needed to make sure we don't
4993 run out of reload regs. Suppose we have three reloads, and
4994 reloads A and B can share regs. These need two regs.
4995 Suppose A and B are given different regs.
4996 That leaves none for C. */
4997 for (pass = 0; pass < 2; pass++)
4999 /* I is the index in spill_regs.
5000 We advance it round-robin between insns to use all spill regs
5001 equally, so that inherited reloads have a chance
5002 of leapfrogging each other. */
5006 for (count = 0; count < n_spills; count++)
5008 int class = (int) rld[r].class;
5014 regnum = spill_regs[i];
5016 if ((reload_reg_free_p (regnum, rld[r].opnum,
5019 /* We check reload_reg_used to make sure we
5020 don't clobber the return register. */
5021 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5022 && reload_reg_free_for_value_p (regnum,
5027 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5028 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5029 /* Look first for regs to share, then for unshared. But
5030 don't share regs used for inherited reloads; they are
5031 the ones we want to preserve. */
5033 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5035 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5038 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5039 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5040 (on 68000) got us two FP regs. If NR is 1,
5041 we would reject both of them. */
5044 /* If we need only one reg, we have already won. */
5047 /* But reject a single reg if we demand a group. */
5052 /* Otherwise check that as many consecutive regs as we need
5053 are available here. */
5056 int regno = regnum + nr - 1;
5057 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5058 && spill_reg_order[regno] >= 0
5059 && reload_reg_free_p (regno, rld[r].opnum,
5060 rld[r].when_needed)))
5069 /* If we found something on pass 1, omit pass 2. */
5070 if (count < n_spills)
5074 /* We should have found a spill register by now. */
5075 if (count >= n_spills)
5078 /* I is the index in SPILL_REG_RTX of the reload register we are to
5079 allocate. Get an rtx for it and find its register number. */
5081 return set_reload_reg (i, r);
5084 /* Initialize all the tables needed to allocate reload registers.
5085 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5086 is the array we use to restore the reg_rtx field for every reload. */
5089 choose_reload_regs_init (chain, save_reload_reg_rtx)
5090 struct insn_chain *chain;
5091 rtx *save_reload_reg_rtx;
5095 for (i = 0; i < n_reloads; i++)
5096 rld[i].reg_rtx = save_reload_reg_rtx[i];
5098 bzero (reload_inherited, MAX_RELOADS);
5099 bzero ((char *) reload_inheritance_insn, MAX_RELOADS * sizeof (rtx));
5100 bzero ((char *) reload_override_in, MAX_RELOADS * sizeof (rtx));
5102 CLEAR_HARD_REG_SET (reload_reg_used);
5103 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5104 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5105 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5106 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5107 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5109 CLEAR_HARD_REG_SET (reg_used_in_insn);
5112 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5113 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5114 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5115 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5116 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5117 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5120 for (i = 0; i < reload_n_operands; i++)
5122 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5123 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5124 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5125 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5126 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5127 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5130 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5132 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5134 for (i = 0; i < n_reloads; i++)
5135 /* If we have already decided to use a certain register,
5136 don't use it in another way. */
5138 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5139 rld[i].when_needed, rld[i].mode);
5142 /* Assign hard reg targets for the pseudo-registers we must reload
5143 into hard regs for this insn.
5144 Also output the instructions to copy them in and out of the hard regs.
5146 For machines with register classes, we are responsible for
5147 finding a reload reg in the proper class. */
5150 choose_reload_regs (chain)
5151 struct insn_chain *chain;
5153 rtx insn = chain->insn;
5155 unsigned int max_group_size = 1;
5156 enum reg_class group_class = NO_REGS;
5157 int pass, win, inheritance;
5159 rtx save_reload_reg_rtx[MAX_RELOADS];
5161 /* In order to be certain of getting the registers we need,
5162 we must sort the reloads into order of increasing register class.
5163 Then our grabbing of reload registers will parallel the process
5164 that provided the reload registers.
5166 Also note whether any of the reloads wants a consecutive group of regs.
5167 If so, record the maximum size of the group desired and what
5168 register class contains all the groups needed by this insn. */
5170 for (j = 0; j < n_reloads; j++)
5172 reload_order[j] = j;
5173 reload_spill_index[j] = -1;
5175 if (rld[j].nregs > 1)
5177 max_group_size = MAX (rld[j].nregs, max_group_size);
5179 = reg_class_superunion[(int)rld[j].class][(int)group_class];
5182 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5186 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5188 /* If -O, try first with inheritance, then turning it off.
5189 If not -O, don't do inheritance.
5190 Using inheritance when not optimizing leads to paradoxes
5191 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5192 because one side of the comparison might be inherited. */
5194 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5196 choose_reload_regs_init (chain, save_reload_reg_rtx);
5198 /* Process the reloads in order of preference just found.
5199 Beyond this point, subregs can be found in reload_reg_rtx.
5201 This used to look for an existing reloaded home for all of the
5202 reloads, and only then perform any new reloads. But that could lose
5203 if the reloads were done out of reg-class order because a later
5204 reload with a looser constraint might have an old home in a register
5205 needed by an earlier reload with a tighter constraint.
5207 To solve this, we make two passes over the reloads, in the order
5208 described above. In the first pass we try to inherit a reload
5209 from a previous insn. If there is a later reload that needs a
5210 class that is a proper subset of the class being processed, we must
5211 also allocate a spill register during the first pass.
5213 Then make a second pass over the reloads to allocate any reloads
5214 that haven't been given registers yet. */
5216 for (j = 0; j < n_reloads; j++)
5218 register int r = reload_order[j];
5219 rtx search_equiv = NULL_RTX;
5221 /* Ignore reloads that got marked inoperative. */
5222 if (rld[r].out == 0 && rld[r].in == 0
5223 && ! rld[r].secondary_p)
5226 /* If find_reloads chose to use reload_in or reload_out as a reload
5227 register, we don't need to chose one. Otherwise, try even if it
5228 found one since we might save an insn if we find the value lying
5230 Try also when reload_in is a pseudo without a hard reg. */
5231 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5232 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5233 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5234 && GET_CODE (rld[r].in) != MEM
5235 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5238 #if 0 /* No longer needed for correct operation.
5239 It might give better code, or might not; worth an experiment? */
5240 /* If this is an optional reload, we can't inherit from earlier insns
5241 until we are sure that any non-optional reloads have been allocated.
5242 The following code takes advantage of the fact that optional reloads
5243 are at the end of reload_order. */
5244 if (rld[r].optional != 0)
5245 for (i = 0; i < j; i++)
5246 if ((rld[reload_order[i]].out != 0
5247 || rld[reload_order[i]].in != 0
5248 || rld[reload_order[i]].secondary_p)
5249 && ! rld[reload_order[i]].optional
5250 && rld[reload_order[i]].reg_rtx == 0)
5251 allocate_reload_reg (chain, reload_order[i], 0);
5254 /* First see if this pseudo is already available as reloaded
5255 for a previous insn. We cannot try to inherit for reloads
5256 that are smaller than the maximum number of registers needed
5257 for groups unless the register we would allocate cannot be used
5260 We could check here to see if this is a secondary reload for
5261 an object that is already in a register of the desired class.
5262 This would avoid the need for the secondary reload register.
5263 But this is complex because we can't easily determine what
5264 objects might want to be loaded via this reload. So let a
5265 register be allocated here. In `emit_reload_insns' we suppress
5266 one of the loads in the case described above. */
5271 register int regno = -1;
5272 enum machine_mode mode = VOIDmode;
5276 else if (GET_CODE (rld[r].in) == REG)
5278 regno = REGNO (rld[r].in);
5279 mode = GET_MODE (rld[r].in);
5281 else if (GET_CODE (rld[r].in_reg) == REG)
5283 regno = REGNO (rld[r].in_reg);
5284 mode = GET_MODE (rld[r].in_reg);
5286 else if (GET_CODE (rld[r].in_reg) == SUBREG
5287 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5289 word = SUBREG_WORD (rld[r].in_reg);
5290 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5291 if (regno < FIRST_PSEUDO_REGISTER)
5293 mode = GET_MODE (rld[r].in_reg);
5296 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5297 || GET_CODE (rld[r].in_reg) == PRE_DEC
5298 || GET_CODE (rld[r].in_reg) == POST_INC
5299 || GET_CODE (rld[r].in_reg) == POST_DEC)
5300 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5302 regno = REGNO (XEXP (rld[r].in_reg, 0));
5303 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5304 rld[r].out = rld[r].in;
5308 /* This won't work, since REGNO can be a pseudo reg number.
5309 Also, it takes much more hair to keep track of all the things
5310 that can invalidate an inherited reload of part of a pseudoreg. */
5311 else if (GET_CODE (rld[r].in) == SUBREG
5312 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5313 regno = REGNO (SUBREG_REG (rld[r].in)) + SUBREG_WORD (rld[r].in);
5316 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5318 enum reg_class class = rld[r].class, last_class;
5319 rtx last_reg = reg_last_reload_reg[regno];
5320 enum machine_mode need_mode;
5322 i = REGNO (last_reg) + word;
5323 last_class = REGNO_REG_CLASS (i);
5325 need_mode = smallest_mode_for_size ((word+1) * UNITS_PER_WORD,
5326 GET_MODE_CLASS (mode));
5329 #ifdef CLASS_CANNOT_CHANGE_MODE
5331 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5332 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5334 : (GET_MODE_SIZE (GET_MODE (last_reg))
5335 >= GET_MODE_SIZE (need_mode)))
5337 (GET_MODE_SIZE (GET_MODE (last_reg))
5338 >= GET_MODE_SIZE (need_mode))
5340 && reg_reloaded_contents[i] == regno
5341 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5342 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5343 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5344 /* Even if we can't use this register as a reload
5345 register, we might use it for reload_override_in,
5346 if copying it to the desired class is cheap
5348 || ((REGISTER_MOVE_COST (last_class, class)
5349 < MEMORY_MOVE_COST (mode, class, 1))
5350 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5351 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5355 #ifdef SECONDARY_MEMORY_NEEDED
5356 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5361 && (rld[r].nregs == max_group_size
5362 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5364 && reload_reg_free_for_value_p (i, rld[r].opnum,
5369 /* If a group is needed, verify that all the subsequent
5370 registers still have their values intact. */
5372 = HARD_REGNO_NREGS (i, rld[r].mode);
5375 for (k = 1; k < nr; k++)
5376 if (reg_reloaded_contents[i + k] != regno
5377 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5384 last_reg = (GET_MODE (last_reg) == mode
5385 ? last_reg : gen_rtx_REG (mode, i));
5387 /* We found a register that contains the
5388 value we need. If this register is the
5389 same as an `earlyclobber' operand of the
5390 current insn, just mark it as a place to
5391 reload from since we can't use it as the
5392 reload register itself. */
5394 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5395 if (reg_overlap_mentioned_for_reload_p
5396 (reg_last_reload_reg[regno],
5397 reload_earlyclobbers[i1]))
5400 if (i1 != n_earlyclobbers
5401 || ! (reload_reg_free_for_value_p
5402 (i, rld[r].opnum, rld[r].when_needed,
5403 rld[r].in, rld[r].out, r, 1))
5404 /* Don't use it if we'd clobber a pseudo reg. */
5405 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5407 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5408 /* Don't clobber the frame pointer. */
5409 || (i == HARD_FRAME_POINTER_REGNUM && rld[r].out)
5410 /* Don't really use the inherited spill reg
5411 if we need it wider than we've got it. */
5412 || (GET_MODE_SIZE (rld[r].mode)
5413 > GET_MODE_SIZE (mode))
5414 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5417 /* If find_reloads chose reload_out as reload
5418 register, stay with it - that leaves the
5419 inherited register for subsequent reloads. */
5420 || (rld[r].out && rld[r].reg_rtx
5421 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5423 reload_override_in[r] = last_reg;
5424 reload_inheritance_insn[r]
5425 = reg_reloaded_insn[i];
5430 /* We can use this as a reload reg. */
5431 /* Mark the register as in use for this part of
5433 mark_reload_reg_in_use (i,
5437 rld[r].reg_rtx = last_reg;
5438 reload_inherited[r] = 1;
5439 reload_inheritance_insn[r]
5440 = reg_reloaded_insn[i];
5441 reload_spill_index[r] = i;
5442 for (k = 0; k < nr; k++)
5443 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5451 /* Here's another way to see if the value is already lying around. */
5454 && ! reload_inherited[r]
5456 && (CONSTANT_P (rld[r].in)
5457 || GET_CODE (rld[r].in) == PLUS
5458 || GET_CODE (rld[r].in) == REG
5459 || GET_CODE (rld[r].in) == MEM)
5460 && (rld[r].nregs == max_group_size
5461 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5462 search_equiv = rld[r].in;
5463 /* If this is an output reload from a simple move insn, look
5464 if an equivalence for the input is available. */
5465 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5467 rtx set = single_set (insn);
5470 && rtx_equal_p (rld[r].out, SET_DEST (set))
5471 && CONSTANT_P (SET_SRC (set)))
5472 search_equiv = SET_SRC (set);
5478 = find_equiv_reg (search_equiv, insn, rld[r].class,
5479 -1, NULL_PTR, 0, rld[r].mode);
5484 if (GET_CODE (equiv) == REG)
5485 regno = REGNO (equiv);
5486 else if (GET_CODE (equiv) == SUBREG)
5488 /* This must be a SUBREG of a hard register.
5489 Make a new REG since this might be used in an
5490 address and not all machines support SUBREGs
5492 regno = REGNO (SUBREG_REG (equiv)) + SUBREG_WORD (equiv);
5493 equiv = gen_rtx_REG (rld[r].mode, regno);
5499 /* If we found a spill reg, reject it unless it is free
5500 and of the desired class. */
5502 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5503 && ! reload_reg_free_for_value_p (regno, rld[r].opnum,
5507 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5511 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5514 /* We found a register that contains the value we need.
5515 If this register is the same as an `earlyclobber' operand
5516 of the current insn, just mark it as a place to reload from
5517 since we can't use it as the reload register itself. */
5520 for (i = 0; i < n_earlyclobbers; i++)
5521 if (reg_overlap_mentioned_for_reload_p (equiv,
5522 reload_earlyclobbers[i]))
5524 reload_override_in[r] = equiv;
5529 /* If the equiv register we have found is explicitly clobbered
5530 in the current insn, it depends on the reload type if we
5531 can use it, use it for reload_override_in, or not at all.
5532 In particular, we then can't use EQUIV for a
5533 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5535 if (equiv != 0 && regno_clobbered_p (regno, insn))
5537 switch (rld[r].when_needed)
5539 case RELOAD_FOR_OTHER_ADDRESS:
5540 case RELOAD_FOR_INPADDR_ADDRESS:
5541 case RELOAD_FOR_INPUT_ADDRESS:
5542 case RELOAD_FOR_OPADDR_ADDR:
5545 case RELOAD_FOR_INPUT:
5546 case RELOAD_FOR_OPERAND_ADDRESS:
5547 reload_override_in[r] = equiv;
5555 /* If we found an equivalent reg, say no code need be generated
5556 to load it, and use it as our reload reg. */
5557 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5559 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5561 rld[r].reg_rtx = equiv;
5562 reload_inherited[r] = 1;
5564 /* If reg_reloaded_valid is not set for this register,
5565 there might be a stale spill_reg_store lying around.
5566 We must clear it, since otherwise emit_reload_insns
5567 might delete the store. */
5568 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5569 spill_reg_store[regno] = NULL_RTX;
5570 /* If any of the hard registers in EQUIV are spill
5571 registers, mark them as in use for this insn. */
5572 for (k = 0; k < nr; k++)
5574 i = spill_reg_order[regno + k];
5577 mark_reload_reg_in_use (regno, rld[r].opnum,
5580 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5587 /* If we found a register to use already, or if this is an optional
5588 reload, we are done. */
5589 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5592 #if 0 /* No longer needed for correct operation. Might or might not
5593 give better code on the average. Want to experiment? */
5595 /* See if there is a later reload that has a class different from our
5596 class that intersects our class or that requires less register
5597 than our reload. If so, we must allocate a register to this
5598 reload now, since that reload might inherit a previous reload
5599 and take the only available register in our class. Don't do this
5600 for optional reloads since they will force all previous reloads
5601 to be allocated. Also don't do this for reloads that have been
5604 for (i = j + 1; i < n_reloads; i++)
5606 int s = reload_order[i];
5608 if ((rld[s].in == 0 && rld[s].out == 0
5609 && ! rld[s].secondary_p)
5613 if ((rld[s].class != rld[r].class
5614 && reg_classes_intersect_p (rld[r].class,
5616 || rld[s].nregs < rld[r].nregs)
5623 allocate_reload_reg (chain, r, j == n_reloads - 1);
5627 /* Now allocate reload registers for anything non-optional that
5628 didn't get one yet. */
5629 for (j = 0; j < n_reloads; j++)
5631 register int r = reload_order[j];
5633 /* Ignore reloads that got marked inoperative. */
5634 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5637 /* Skip reloads that already have a register allocated or are
5639 if (rld[r].reg_rtx != 0 || rld[r].optional)
5642 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5646 /* If that loop got all the way, we have won. */
5653 /* Loop around and try without any inheritance. */
5658 /* First undo everything done by the failed attempt
5659 to allocate with inheritance. */
5660 choose_reload_regs_init (chain, save_reload_reg_rtx);
5662 /* Some sanity tests to verify that the reloads found in the first
5663 pass are identical to the ones we have now. */
5664 if (chain->n_reloads != n_reloads)
5667 for (i = 0; i < n_reloads; i++)
5669 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5671 if (chain->rld[i].when_needed != rld[i].when_needed)
5673 for (j = 0; j < n_spills; j++)
5674 if (spill_regs[j] == chain->rld[i].regno)
5675 if (! set_reload_reg (j, i))
5676 failed_reload (chain->insn, i);
5680 /* If we thought we could inherit a reload, because it seemed that
5681 nothing else wanted the same reload register earlier in the insn,
5682 verify that assumption, now that all reloads have been assigned.
5683 Likewise for reloads where reload_override_in has been set. */
5685 /* If doing expensive optimizations, do one preliminary pass that doesn't
5686 cancel any inheritance, but removes reloads that have been needed only
5687 for reloads that we know can be inherited. */
5688 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5690 for (j = 0; j < n_reloads; j++)
5692 register int r = reload_order[j];
5694 if (reload_inherited[r] && rld[r].reg_rtx)
5695 check_reg = rld[r].reg_rtx;
5696 else if (reload_override_in[r]
5697 && (GET_CODE (reload_override_in[r]) == REG
5698 || GET_CODE (reload_override_in[r]) == SUBREG))
5699 check_reg = reload_override_in[r];
5702 if (! reload_reg_free_for_value_p (true_regnum (check_reg),
5706 (reload_inherited[r]
5707 ? rld[r].out : const0_rtx),
5712 reload_inherited[r] = 0;
5713 reload_override_in[r] = 0;
5715 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5716 reload_override_in, then we do not need its related
5717 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5718 likewise for other reload types.
5719 We handle this by removing a reload when its only replacement
5720 is mentioned in reload_in of the reload we are going to inherit.
5721 A special case are auto_inc expressions; even if the input is
5722 inherited, we still need the address for the output. We can
5723 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5724 If we suceeded removing some reload and we are doing a preliminary
5725 pass just to remove such reloads, make another pass, since the
5726 removal of one reload might allow us to inherit another one. */
5728 && rld[r].out != rld[r].in
5729 && remove_address_replacements (rld[r].in) && pass)
5734 /* Now that reload_override_in is known valid,
5735 actually override reload_in. */
5736 for (j = 0; j < n_reloads; j++)
5737 if (reload_override_in[j])
5738 rld[j].in = reload_override_in[j];
5740 /* If this reload won't be done because it has been cancelled or is
5741 optional and not inherited, clear reload_reg_rtx so other
5742 routines (such as subst_reloads) don't get confused. */
5743 for (j = 0; j < n_reloads; j++)
5744 if (rld[j].reg_rtx != 0
5745 && ((rld[j].optional && ! reload_inherited[j])
5746 || (rld[j].in == 0 && rld[j].out == 0
5747 && ! rld[j].secondary_p)))
5749 int regno = true_regnum (rld[j].reg_rtx);
5751 if (spill_reg_order[regno] >= 0)
5752 clear_reload_reg_in_use (regno, rld[j].opnum,
5753 rld[j].when_needed, rld[j].mode);
5755 reload_spill_index[j] = -1;
5758 /* Record which pseudos and which spill regs have output reloads. */
5759 for (j = 0; j < n_reloads; j++)
5761 register int r = reload_order[j];
5763 i = reload_spill_index[r];
5765 /* I is nonneg if this reload uses a register.
5766 If rld[r].reg_rtx is 0, this is an optional reload
5767 that we opted to ignore. */
5768 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5769 && rld[r].reg_rtx != 0)
5771 register int nregno = REGNO (rld[r].out_reg);
5774 if (nregno < FIRST_PSEUDO_REGISTER)
5775 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5778 reg_has_output_reload[nregno + nr] = 1;
5782 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5784 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5787 if (rld[r].when_needed != RELOAD_OTHER
5788 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5789 && rld[r].when_needed != RELOAD_FOR_INSN)
5795 /* Deallocate the reload register for reload R. This is called from
5796 remove_address_replacements. */
5799 deallocate_reload_reg (r)
5804 if (! rld[r].reg_rtx)
5806 regno = true_regnum (rld[r].reg_rtx);
5808 if (spill_reg_order[regno] >= 0)
5809 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5811 reload_spill_index[r] = -1;
5814 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5815 reloads of the same item for fear that we might not have enough reload
5816 registers. However, normally they will get the same reload register
5817 and hence actually need not be loaded twice.
5819 Here we check for the most common case of this phenomenon: when we have
5820 a number of reloads for the same object, each of which were allocated
5821 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5822 reload, and is not modified in the insn itself. If we find such,
5823 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5824 This will not increase the number of spill registers needed and will
5825 prevent redundant code. */
5828 merge_assigned_reloads (insn)
5833 /* Scan all the reloads looking for ones that only load values and
5834 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5835 assigned and not modified by INSN. */
5837 for (i = 0; i < n_reloads; i++)
5839 int conflicting_input = 0;
5840 int max_input_address_opnum = -1;
5841 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5843 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5844 || rld[i].out != 0 || rld[i].reg_rtx == 0
5845 || reg_set_p (rld[i].reg_rtx, insn))
5848 /* Look at all other reloads. Ensure that the only use of this
5849 reload_reg_rtx is in a reload that just loads the same value
5850 as we do. Note that any secondary reloads must be of the identical
5851 class since the values, modes, and result registers are the
5852 same, so we need not do anything with any secondary reloads. */
5854 for (j = 0; j < n_reloads; j++)
5856 if (i == j || rld[j].reg_rtx == 0
5857 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5861 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5862 && rld[j].opnum > max_input_address_opnum)
5863 max_input_address_opnum = rld[j].opnum;
5865 /* If the reload regs aren't exactly the same (e.g, different modes)
5866 or if the values are different, we can't merge this reload.
5867 But if it is an input reload, we might still merge
5868 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
5870 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5871 || rld[j].out != 0 || rld[j].in == 0
5872 || ! rtx_equal_p (rld[i].in, rld[j].in))
5874 if (rld[j].when_needed != RELOAD_FOR_INPUT
5875 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
5876 || rld[i].opnum > rld[j].opnum)
5877 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
5879 conflicting_input = 1;
5880 if (min_conflicting_input_opnum > rld[j].opnum)
5881 min_conflicting_input_opnum = rld[j].opnum;
5885 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
5886 we, in fact, found any matching reloads. */
5889 && max_input_address_opnum <= min_conflicting_input_opnum)
5891 for (j = 0; j < n_reloads; j++)
5892 if (i != j && rld[j].reg_rtx != 0
5893 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
5894 && (! conflicting_input
5895 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5896 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
5898 rld[i].when_needed = RELOAD_OTHER;
5900 reload_spill_index[j] = -1;
5901 transfer_replacements (i, j);
5904 /* If this is now RELOAD_OTHER, look for any reloads that load
5905 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
5906 if they were for inputs, RELOAD_OTHER for outputs. Note that
5907 this test is equivalent to looking for reloads for this operand
5910 if (rld[i].when_needed == RELOAD_OTHER)
5911 for (j = 0; j < n_reloads; j++)
5913 && rld[i].when_needed != RELOAD_OTHER
5914 && reg_overlap_mentioned_for_reload_p (rld[j].in,
5917 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
5918 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
5919 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
5925 /* These arrays are filled by emit_reload_insns and its subroutines. */
5926 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
5927 static rtx other_input_address_reload_insns = 0;
5928 static rtx other_input_reload_insns = 0;
5929 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
5930 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5931 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
5932 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
5933 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
5934 static rtx operand_reload_insns = 0;
5935 static rtx other_operand_reload_insns = 0;
5936 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
5938 /* Values to be put in spill_reg_store are put here first. */
5939 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
5940 static HARD_REG_SET reg_reloaded_died;
5942 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
5943 has the number J. OLD contains the value to be used as input. */
5946 emit_input_reload_insns (chain, rl, old, j)
5947 struct insn_chain *chain;
5952 rtx insn = chain->insn;
5953 register rtx reloadreg = rl->reg_rtx;
5954 rtx oldequiv_reg = 0;
5957 enum machine_mode mode;
5960 /* Determine the mode to reload in.
5961 This is very tricky because we have three to choose from.
5962 There is the mode the insn operand wants (rl->inmode).
5963 There is the mode of the reload register RELOADREG.
5964 There is the intrinsic mode of the operand, which we could find
5965 by stripping some SUBREGs.
5966 It turns out that RELOADREG's mode is irrelevant:
5967 we can change that arbitrarily.
5969 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
5970 then the reload reg may not support QImode moves, so use SImode.
5971 If foo is in memory due to spilling a pseudo reg, this is safe,
5972 because the QImode value is in the least significant part of a
5973 slot big enough for a SImode. If foo is some other sort of
5974 memory reference, then it is impossible to reload this case,
5975 so previous passes had better make sure this never happens.
5977 Then consider a one-word union which has SImode and one of its
5978 members is a float, being fetched as (SUBREG:SF union:SI).
5979 We must fetch that as SFmode because we could be loading into
5980 a float-only register. In this case OLD's mode is correct.
5982 Consider an immediate integer: it has VOIDmode. Here we need
5983 to get a mode from something else.
5985 In some cases, there is a fourth mode, the operand's
5986 containing mode. If the insn specifies a containing mode for
5987 this operand, it overrides all others.
5989 I am not sure whether the algorithm here is always right,
5990 but it does the right things in those cases. */
5992 mode = GET_MODE (old);
5993 if (mode == VOIDmode)
5996 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5997 /* If we need a secondary register for this operation, see if
5998 the value is already in a register in that class. Don't
5999 do this if the secondary register will be used as a scratch
6002 if (rl->secondary_in_reload >= 0
6003 && rl->secondary_in_icode == CODE_FOR_nothing
6006 = find_equiv_reg (old, insn,
6007 rld[rl->secondary_in_reload].class,
6008 -1, NULL_PTR, 0, mode);
6011 /* If reloading from memory, see if there is a register
6012 that already holds the same value. If so, reload from there.
6013 We can pass 0 as the reload_reg_p argument because
6014 any other reload has either already been emitted,
6015 in which case find_equiv_reg will see the reload-insn,
6016 or has yet to be emitted, in which case it doesn't matter
6017 because we will use this equiv reg right away. */
6019 if (oldequiv == 0 && optimize
6020 && (GET_CODE (old) == MEM
6021 || (GET_CODE (old) == REG
6022 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6023 && reg_renumber[REGNO (old)] < 0)))
6024 oldequiv = find_equiv_reg (old, insn, ALL_REGS,
6025 -1, NULL_PTR, 0, mode);
6029 unsigned int regno = true_regnum (oldequiv);
6031 /* Don't use OLDEQUIV if any other reload changes it at an
6032 earlier stage of this insn or at this stage. */
6033 if (! reload_reg_free_for_value_p (regno, rl->opnum,
6035 rl->in, const0_rtx, j,
6039 /* If it is no cheaper to copy from OLDEQUIV into the
6040 reload register than it would be to move from memory,
6041 don't use it. Likewise, if we need a secondary register
6045 && ((REGNO_REG_CLASS (regno) != rl->class
6046 && (REGISTER_MOVE_COST (REGNO_REG_CLASS (regno),
6048 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6049 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6050 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6054 #ifdef SECONDARY_MEMORY_NEEDED
6055 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6063 /* delete_output_reload is only invoked properly if old contains
6064 the original pseudo register. Since this is replaced with a
6065 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6066 find the pseudo in RELOAD_IN_REG. */
6068 && reload_override_in[j]
6069 && GET_CODE (rl->in_reg) == REG)
6076 else if (GET_CODE (oldequiv) == REG)
6077 oldequiv_reg = oldequiv;
6078 else if (GET_CODE (oldequiv) == SUBREG)
6079 oldequiv_reg = SUBREG_REG (oldequiv);
6081 /* If we are reloading from a register that was recently stored in
6082 with an output-reload, see if we can prove there was
6083 actually no need to store the old value in it. */
6085 if (optimize && GET_CODE (oldequiv) == REG
6086 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6087 && spill_reg_store[REGNO (oldequiv)]
6088 && GET_CODE (old) == REG
6089 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6090 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6092 delete_output_reload (insn, j, REGNO (oldequiv));
6094 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6095 then load RELOADREG from OLDEQUIV. Note that we cannot use
6096 gen_lowpart_common since it can do the wrong thing when
6097 RELOADREG has a multi-word mode. Note that RELOADREG
6098 must always be a REG here. */
6100 if (GET_MODE (reloadreg) != mode)
6101 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6102 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6103 oldequiv = SUBREG_REG (oldequiv);
6104 if (GET_MODE (oldequiv) != VOIDmode
6105 && mode != GET_MODE (oldequiv))
6106 oldequiv = gen_rtx_SUBREG (mode, oldequiv, 0);
6108 /* Switch to the right place to emit the reload insns. */
6109 switch (rl->when_needed)
6112 where = &other_input_reload_insns;
6114 case RELOAD_FOR_INPUT:
6115 where = &input_reload_insns[rl->opnum];
6117 case RELOAD_FOR_INPUT_ADDRESS:
6118 where = &input_address_reload_insns[rl->opnum];
6120 case RELOAD_FOR_INPADDR_ADDRESS:
6121 where = &inpaddr_address_reload_insns[rl->opnum];
6123 case RELOAD_FOR_OUTPUT_ADDRESS:
6124 where = &output_address_reload_insns[rl->opnum];
6126 case RELOAD_FOR_OUTADDR_ADDRESS:
6127 where = &outaddr_address_reload_insns[rl->opnum];
6129 case RELOAD_FOR_OPERAND_ADDRESS:
6130 where = &operand_reload_insns;
6132 case RELOAD_FOR_OPADDR_ADDR:
6133 where = &other_operand_reload_insns;
6135 case RELOAD_FOR_OTHER_ADDRESS:
6136 where = &other_input_address_reload_insns;
6142 push_to_sequence (*where);
6144 /* Auto-increment addresses must be reloaded in a special way. */
6145 if (rl->out && ! rl->out_reg)
6147 /* We are not going to bother supporting the case where a
6148 incremented register can't be copied directly from
6149 OLDEQUIV since this seems highly unlikely. */
6150 if (rl->secondary_in_reload >= 0)
6153 if (reload_inherited[j])
6154 oldequiv = reloadreg;
6156 old = XEXP (rl->in_reg, 0);
6158 if (optimize && GET_CODE (oldequiv) == REG
6159 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6160 && spill_reg_store[REGNO (oldequiv)]
6161 && GET_CODE (old) == REG
6162 && (dead_or_set_p (insn,
6163 spill_reg_stored_to[REGNO (oldequiv)])
6164 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6166 delete_output_reload (insn, j, REGNO (oldequiv));
6168 /* Prevent normal processing of this reload. */
6170 /* Output a special code sequence for this case. */
6171 new_spill_reg_store[REGNO (reloadreg)]
6172 = inc_for_reload (reloadreg, oldequiv, rl->out,
6176 /* If we are reloading a pseudo-register that was set by the previous
6177 insn, see if we can get rid of that pseudo-register entirely
6178 by redirecting the previous insn into our reload register. */
6180 else if (optimize && GET_CODE (old) == REG
6181 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6182 && dead_or_set_p (insn, old)
6183 /* This is unsafe if some other reload
6184 uses the same reg first. */
6185 && reload_reg_free_for_value_p (REGNO (reloadreg),
6191 rtx temp = PREV_INSN (insn);
6192 while (temp && GET_CODE (temp) == NOTE)
6193 temp = PREV_INSN (temp);
6195 && GET_CODE (temp) == INSN
6196 && GET_CODE (PATTERN (temp)) == SET
6197 && SET_DEST (PATTERN (temp)) == old
6198 /* Make sure we can access insn_operand_constraint. */
6199 && asm_noperands (PATTERN (temp)) < 0
6200 /* This is unsafe if prev insn rejects our reload reg. */
6201 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6203 /* This is unsafe if operand occurs more than once in current
6204 insn. Perhaps some occurrences aren't reloaded. */
6205 && count_occurrences (PATTERN (insn), old, 0) == 1
6206 /* Don't risk splitting a matching pair of operands. */
6207 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6209 /* Store into the reload register instead of the pseudo. */
6210 SET_DEST (PATTERN (temp)) = reloadreg;
6212 /* If the previous insn is an output reload, the source is
6213 a reload register, and its spill_reg_store entry will
6214 contain the previous destination. This is now
6216 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6217 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6219 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6220 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6223 /* If these are the only uses of the pseudo reg,
6224 pretend for GDB it lives in the reload reg we used. */
6225 if (REG_N_DEATHS (REGNO (old)) == 1
6226 && REG_N_SETS (REGNO (old)) == 1)
6228 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6229 alter_reg (REGNO (old), -1);
6235 /* We can't do that, so output an insn to load RELOADREG. */
6237 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6238 /* If we have a secondary reload, pick up the secondary register
6239 and icode, if any. If OLDEQUIV and OLD are different or
6240 if this is an in-out reload, recompute whether or not we
6241 still need a secondary register and what the icode should
6242 be. If we still need a secondary register and the class or
6243 icode is different, go back to reloading from OLD if using
6244 OLDEQUIV means that we got the wrong type of register. We
6245 cannot have different class or icode due to an in-out reload
6246 because we don't make such reloads when both the input and
6247 output need secondary reload registers. */
6249 if (! special && rl->secondary_in_reload >= 0)
6251 rtx second_reload_reg = 0;
6252 int secondary_reload = rl->secondary_in_reload;
6253 rtx real_oldequiv = oldequiv;
6256 enum insn_code icode;
6258 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6259 and similarly for OLD.
6260 See comments in get_secondary_reload in reload.c. */
6261 /* If it is a pseudo that cannot be replaced with its
6262 equivalent MEM, we must fall back to reload_in, which
6263 will have all the necessary substitutions registered.
6264 Likewise for a pseudo that can't be replaced with its
6265 equivalent constant.
6267 Take extra care for subregs of such pseudos. Note that
6268 we cannot use reg_equiv_mem in this case because it is
6269 not in the right mode. */
6272 if (GET_CODE (tmp) == SUBREG)
6273 tmp = SUBREG_REG (tmp);
6274 if (GET_CODE (tmp) == REG
6275 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6276 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6277 || reg_equiv_constant[REGNO (tmp)] != 0))
6279 if (! reg_equiv_mem[REGNO (tmp)]
6280 || num_not_at_initial_offset
6281 || GET_CODE (oldequiv) == SUBREG)
6282 real_oldequiv = rl->in;
6284 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6288 if (GET_CODE (tmp) == SUBREG)
6289 tmp = SUBREG_REG (tmp);
6290 if (GET_CODE (tmp) == REG
6291 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6292 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6293 || reg_equiv_constant[REGNO (tmp)] != 0))
6295 if (! reg_equiv_mem[REGNO (tmp)]
6296 || num_not_at_initial_offset
6297 || GET_CODE (old) == SUBREG)
6300 real_old = reg_equiv_mem[REGNO (tmp)];
6303 second_reload_reg = rld[secondary_reload].reg_rtx;
6304 icode = rl->secondary_in_icode;
6306 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6307 || (rl->in != 0 && rl->out != 0))
6309 enum reg_class new_class
6310 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6311 mode, real_oldequiv);
6313 if (new_class == NO_REGS)
6314 second_reload_reg = 0;
6317 enum insn_code new_icode;
6318 enum machine_mode new_mode;
6320 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6321 REGNO (second_reload_reg)))
6322 oldequiv = old, real_oldequiv = real_old;
6325 new_icode = reload_in_optab[(int) mode];
6326 if (new_icode != CODE_FOR_nothing
6327 && ((insn_data[(int) new_icode].operand[0].predicate
6328 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6330 || (insn_data[(int) new_icode].operand[1].predicate
6331 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6332 (real_oldequiv, mode)))))
6333 new_icode = CODE_FOR_nothing;
6335 if (new_icode == CODE_FOR_nothing)
6338 new_mode = insn_data[(int) new_icode].operand[2].mode;
6340 if (GET_MODE (second_reload_reg) != new_mode)
6342 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6344 oldequiv = old, real_oldequiv = real_old;
6347 = gen_rtx_REG (new_mode,
6348 REGNO (second_reload_reg));
6354 /* If we still need a secondary reload register, check
6355 to see if it is being used as a scratch or intermediate
6356 register and generate code appropriately. If we need
6357 a scratch register, use REAL_OLDEQUIV since the form of
6358 the insn may depend on the actual address if it is
6361 if (second_reload_reg)
6363 if (icode != CODE_FOR_nothing)
6365 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6366 second_reload_reg));
6371 /* See if we need a scratch register to load the
6372 intermediate register (a tertiary reload). */
6373 enum insn_code tertiary_icode
6374 = rld[secondary_reload].secondary_in_icode;
6376 if (tertiary_icode != CODE_FOR_nothing)
6378 rtx third_reload_reg
6379 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6381 emit_insn ((GEN_FCN (tertiary_icode)
6382 (second_reload_reg, real_oldequiv,
6383 third_reload_reg)));
6386 gen_reload (second_reload_reg, real_oldequiv,
6390 oldequiv = second_reload_reg;
6396 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6398 rtx real_oldequiv = oldequiv;
6400 if ((GET_CODE (oldequiv) == REG
6401 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6402 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6403 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6404 || (GET_CODE (oldequiv) == SUBREG
6405 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6406 && (REGNO (SUBREG_REG (oldequiv))
6407 >= FIRST_PSEUDO_REGISTER)
6408 && ((reg_equiv_memory_loc
6409 [REGNO (SUBREG_REG (oldequiv))] != 0)
6410 || (reg_equiv_constant
6411 [REGNO (SUBREG_REG (oldequiv))] != 0))))
6412 real_oldequiv = rl->in;
6413 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6417 /* End this sequence. */
6418 *where = get_insns ();
6421 /* Update reload_override_in so that delete_address_reloads_1
6422 can see the actual register usage. */
6424 reload_override_in[j] = oldequiv;
6427 /* Generate insns to for the output reload RL, which is for the insn described
6428 by CHAIN and has the number J. */
6430 emit_output_reload_insns (chain, rl, j)
6431 struct insn_chain *chain;
6435 rtx reloadreg = rl->reg_rtx;
6436 rtx insn = chain->insn;
6439 enum machine_mode mode = GET_MODE (old);
6442 if (rl->when_needed == RELOAD_OTHER)
6445 push_to_sequence (output_reload_insns[rl->opnum]);
6447 /* Determine the mode to reload in.
6448 See comments above (for input reloading). */
6450 if (mode == VOIDmode)
6452 /* VOIDmode should never happen for an output. */
6453 if (asm_noperands (PATTERN (insn)) < 0)
6454 /* It's the compiler's fault. */
6455 fatal_insn ("VOIDmode on an output", insn);
6456 error_for_asm (insn, "output operand is constant in `asm'");
6457 /* Prevent crash--use something we know is valid. */
6459 old = gen_rtx_REG (mode, REGNO (reloadreg));
6462 if (GET_MODE (reloadreg) != mode)
6463 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6465 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6467 /* If we need two reload regs, set RELOADREG to the intermediate
6468 one, since it will be stored into OLD. We might need a secondary
6469 register only for an input reload, so check again here. */
6471 if (rl->secondary_out_reload >= 0)
6475 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6476 && reg_equiv_mem[REGNO (old)] != 0)
6477 real_old = reg_equiv_mem[REGNO (old)];
6479 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6483 rtx second_reloadreg = reloadreg;
6484 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6486 /* See if RELOADREG is to be used as a scratch register
6487 or as an intermediate register. */
6488 if (rl->secondary_out_icode != CODE_FOR_nothing)
6490 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6491 (real_old, second_reloadreg, reloadreg)));
6496 /* See if we need both a scratch and intermediate reload
6499 int secondary_reload = rl->secondary_out_reload;
6500 enum insn_code tertiary_icode
6501 = rld[secondary_reload].secondary_out_icode;
6503 if (GET_MODE (reloadreg) != mode)
6504 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6506 if (tertiary_icode != CODE_FOR_nothing)
6509 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6512 /* Copy primary reload reg to secondary reload reg.
6513 (Note that these have been swapped above, then
6514 secondary reload reg to OLD using our insn. */
6516 /* If REAL_OLD is a paradoxical SUBREG, remove it
6517 and try to put the opposite SUBREG on
6519 if (GET_CODE (real_old) == SUBREG
6520 && (GET_MODE_SIZE (GET_MODE (real_old))
6521 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6522 && 0 != (tem = gen_lowpart_common
6523 (GET_MODE (SUBREG_REG (real_old)),
6525 real_old = SUBREG_REG (real_old), reloadreg = tem;
6527 gen_reload (reloadreg, second_reloadreg,
6528 rl->opnum, rl->when_needed);
6529 emit_insn ((GEN_FCN (tertiary_icode)
6530 (real_old, reloadreg, third_reloadreg)));
6535 /* Copy between the reload regs here and then to
6538 gen_reload (reloadreg, second_reloadreg,
6539 rl->opnum, rl->when_needed);
6545 /* Output the last reload insn. */
6550 /* Don't output the last reload if OLD is not the dest of
6551 INSN and is in the src and is clobbered by INSN. */
6552 if (! flag_expensive_optimizations
6553 || GET_CODE (old) != REG
6554 || !(set = single_set (insn))
6555 || rtx_equal_p (old, SET_DEST (set))
6556 || !reg_mentioned_p (old, SET_SRC (set))
6557 || !regno_clobbered_p (REGNO (old), insn))
6558 gen_reload (old, reloadreg, rl->opnum,
6562 /* Look at all insns we emitted, just to be safe. */
6563 for (p = get_insns (); p; p = NEXT_INSN (p))
6566 rtx pat = PATTERN (p);
6568 /* If this output reload doesn't come from a spill reg,
6569 clear any memory of reloaded copies of the pseudo reg.
6570 If this output reload comes from a spill reg,
6571 reg_has_output_reload will make this do nothing. */
6572 note_stores (pat, forget_old_reloads_1, NULL);
6574 if (reg_mentioned_p (rl->reg_rtx, pat))
6576 rtx set = single_set (insn);
6577 if (reload_spill_index[j] < 0
6579 && SET_SRC (set) == rl->reg_rtx)
6581 int src = REGNO (SET_SRC (set));
6583 reload_spill_index[j] = src;
6584 SET_HARD_REG_BIT (reg_is_output_reload, src);
6585 if (find_regno_note (insn, REG_DEAD, src))
6586 SET_HARD_REG_BIT (reg_reloaded_died, src);
6588 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6590 int s = rl->secondary_out_reload;
6591 set = single_set (p);
6592 /* If this reload copies only to the secondary reload
6593 register, the secondary reload does the actual
6595 if (s >= 0 && set == NULL_RTX)
6596 ; /* We can't tell what function the secondary reload
6597 has and where the actual store to the pseudo is
6598 made; leave new_spill_reg_store alone. */
6600 && SET_SRC (set) == rl->reg_rtx
6601 && SET_DEST (set) == rld[s].reg_rtx)
6603 /* Usually the next instruction will be the
6604 secondary reload insn; if we can confirm
6605 that it is, setting new_spill_reg_store to
6606 that insn will allow an extra optimization. */
6607 rtx s_reg = rld[s].reg_rtx;
6608 rtx next = NEXT_INSN (p);
6609 rld[s].out = rl->out;
6610 rld[s].out_reg = rl->out_reg;
6611 set = single_set (next);
6612 if (set && SET_SRC (set) == s_reg
6613 && ! new_spill_reg_store[REGNO (s_reg)])
6615 SET_HARD_REG_BIT (reg_is_output_reload,
6617 new_spill_reg_store[REGNO (s_reg)] = next;
6621 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6626 if (rl->when_needed == RELOAD_OTHER)
6628 emit_insns (other_output_reload_insns[rl->opnum]);
6629 other_output_reload_insns[rl->opnum] = get_insns ();
6632 output_reload_insns[rl->opnum] = get_insns ();
6637 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6638 and has the number J. */
6640 do_input_reload (chain, rl, j)
6641 struct insn_chain *chain;
6645 int expect_occurrences = 1;
6646 rtx insn = chain->insn;
6647 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6648 ? rl->in_reg : rl->in);
6651 /* AUTO_INC reloads need to be handled even if inherited. We got an
6652 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6653 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6654 && ! rtx_equal_p (rl->reg_rtx, old)
6655 && rl->reg_rtx != 0)
6656 emit_input_reload_insns (chain, rld + j, old, j);
6658 /* When inheriting a wider reload, we have a MEM in rl->in,
6659 e.g. inheriting a SImode output reload for
6660 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6661 if (optimize && reload_inherited[j] && rl->in
6662 && GET_CODE (rl->in) == MEM
6663 && GET_CODE (rl->in_reg) == MEM
6664 && reload_spill_index[j] >= 0
6665 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6668 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6670 = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6673 /* If we are reloading a register that was recently stored in with an
6674 output-reload, see if we can prove there was
6675 actually no need to store the old value in it. */
6678 && (reload_inherited[j] || reload_override_in[j])
6680 && GET_CODE (rl->reg_rtx) == REG
6681 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6683 /* There doesn't seem to be any reason to restrict this to pseudos
6684 and doing so loses in the case where we are copying from a
6685 register of the wrong class. */
6686 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6687 >= FIRST_PSEUDO_REGISTER)
6689 /* The insn might have already some references to stackslots
6690 replaced by MEMs, while reload_out_reg still names the
6692 && (dead_or_set_p (insn,
6693 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6694 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6696 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6699 /* Do output reloading for reload RL, which is for the insn described by
6700 CHAIN and has the number J.
6701 ??? At some point we need to support handling output reloads of
6702 JUMP_INSNs or insns that set cc0. */
6704 do_output_reload (chain, rl, j)
6705 struct insn_chain *chain;
6710 rtx insn = chain->insn;
6711 /* If this is an output reload that stores something that is
6712 not loaded in this same reload, see if we can eliminate a previous
6714 rtx pseudo = rl->out_reg;
6717 && GET_CODE (pseudo) == REG
6718 && ! rtx_equal_p (rl->in_reg, pseudo)
6719 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6720 && reg_last_reload_reg[REGNO (pseudo)])
6722 int pseudo_no = REGNO (pseudo);
6723 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6725 /* We don't need to test full validity of last_regno for
6726 inherit here; we only want to know if the store actually
6727 matches the pseudo. */
6728 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6729 && reg_reloaded_contents[last_regno] == pseudo_no
6730 && spill_reg_store[last_regno]
6731 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6732 delete_output_reload (insn, j, last_regno);
6737 || rl->reg_rtx == old
6738 || rl->reg_rtx == 0)
6741 /* An output operand that dies right away does need a reload,
6742 but need not be copied from it. Show the new location in the
6744 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6745 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6747 XEXP (note, 0) = rl->reg_rtx;
6750 /* Likewise for a SUBREG of an operand that dies. */
6751 else if (GET_CODE (old) == SUBREG
6752 && GET_CODE (SUBREG_REG (old)) == REG
6753 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6756 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6760 else if (GET_CODE (old) == SCRATCH)
6761 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6762 but we don't want to make an output reload. */
6765 /* If is a JUMP_INSN, we can't support output reloads yet. */
6766 if (GET_CODE (insn) == JUMP_INSN)
6769 emit_output_reload_insns (chain, rld + j, j);
6772 /* Output insns to reload values in and out of the chosen reload regs. */
6775 emit_reload_insns (chain)
6776 struct insn_chain *chain;
6778 rtx insn = chain->insn;
6781 rtx following_insn = NEXT_INSN (insn);
6782 rtx before_insn = PREV_INSN (insn);
6784 CLEAR_HARD_REG_SET (reg_reloaded_died);
6786 for (j = 0; j < reload_n_operands; j++)
6787 input_reload_insns[j] = input_address_reload_insns[j]
6788 = inpaddr_address_reload_insns[j]
6789 = output_reload_insns[j] = output_address_reload_insns[j]
6790 = outaddr_address_reload_insns[j]
6791 = other_output_reload_insns[j] = 0;
6792 other_input_address_reload_insns = 0;
6793 other_input_reload_insns = 0;
6794 operand_reload_insns = 0;
6795 other_operand_reload_insns = 0;
6797 /* Now output the instructions to copy the data into and out of the
6798 reload registers. Do these in the order that the reloads were reported,
6799 since reloads of base and index registers precede reloads of operands
6800 and the operands may need the base and index registers reloaded. */
6802 for (j = 0; j < n_reloads; j++)
6805 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6806 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6808 do_input_reload (chain, rld + j, j);
6809 do_output_reload (chain, rld + j, j);
6812 /* Now write all the insns we made for reloads in the order expected by
6813 the allocation functions. Prior to the insn being reloaded, we write
6814 the following reloads:
6816 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6818 RELOAD_OTHER reloads.
6820 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6821 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6822 RELOAD_FOR_INPUT reload for the operand.
6824 RELOAD_FOR_OPADDR_ADDRS reloads.
6826 RELOAD_FOR_OPERAND_ADDRESS reloads.
6828 After the insn being reloaded, we write the following:
6830 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
6831 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
6832 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
6833 reloads for the operand. The RELOAD_OTHER output reloads are
6834 output in descending order by reload number. */
6836 emit_insns_before (other_input_address_reload_insns, insn);
6837 emit_insns_before (other_input_reload_insns, insn);
6839 for (j = 0; j < reload_n_operands; j++)
6841 emit_insns_before (inpaddr_address_reload_insns[j], insn);
6842 emit_insns_before (input_address_reload_insns[j], insn);
6843 emit_insns_before (input_reload_insns[j], insn);
6846 emit_insns_before (other_operand_reload_insns, insn);
6847 emit_insns_before (operand_reload_insns, insn);
6849 for (j = 0; j < reload_n_operands; j++)
6851 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
6852 emit_insns_before (output_address_reload_insns[j], following_insn);
6853 emit_insns_before (output_reload_insns[j], following_insn);
6854 emit_insns_before (other_output_reload_insns[j], following_insn);
6857 /* Keep basic block info up to date. */
6860 if (BLOCK_HEAD (chain->block) == insn)
6861 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
6862 if (BLOCK_END (chain->block) == insn)
6863 BLOCK_END (chain->block) = PREV_INSN (following_insn);
6866 /* For all the spill regs newly reloaded in this instruction,
6867 record what they were reloaded from, so subsequent instructions
6868 can inherit the reloads.
6870 Update spill_reg_store for the reloads of this insn.
6871 Copy the elements that were updated in the loop above. */
6873 for (j = 0; j < n_reloads; j++)
6875 register int r = reload_order[j];
6876 register int i = reload_spill_index[r];
6878 /* If this is a non-inherited input reload from a pseudo, we must
6879 clear any memory of a previous store to the same pseudo. Only do
6880 something if there will not be an output reload for the pseudo
6882 if (rld[r].in_reg != 0
6883 && ! (reload_inherited[r] || reload_override_in[r]))
6885 rtx reg = rld[r].in_reg;
6887 if (GET_CODE (reg) == SUBREG)
6888 reg = SUBREG_REG (reg);
6890 if (GET_CODE (reg) == REG
6891 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
6892 && ! reg_has_output_reload[REGNO (reg)])
6894 int nregno = REGNO (reg);
6896 if (reg_last_reload_reg[nregno])
6898 int last_regno = REGNO (reg_last_reload_reg[nregno]);
6900 if (reg_reloaded_contents[last_regno] == nregno)
6901 spill_reg_store[last_regno] = 0;
6906 /* I is nonneg if this reload used a register.
6907 If rld[r].reg_rtx is 0, this is an optional reload
6908 that we opted to ignore. */
6910 if (i >= 0 && rld[r].reg_rtx != 0)
6913 = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
6915 int part_reaches_end = 0;
6916 int all_reaches_end = 1;
6918 /* For a multi register reload, we need to check if all or part
6919 of the value lives to the end. */
6920 for (k = 0; k < nr; k++)
6922 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
6923 rld[r].when_needed))
6924 part_reaches_end = 1;
6926 all_reaches_end = 0;
6929 /* Ignore reloads that don't reach the end of the insn in
6931 if (all_reaches_end)
6933 /* First, clear out memory of what used to be in this spill reg.
6934 If consecutive registers are used, clear them all. */
6936 for (k = 0; k < nr; k++)
6937 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
6939 /* Maybe the spill reg contains a copy of reload_out. */
6941 && (GET_CODE (rld[r].out) == REG
6945 || GET_CODE (rld[r].out_reg) == REG))
6947 rtx out = (GET_CODE (rld[r].out) == REG
6951 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
6952 register int nregno = REGNO (out);
6953 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
6954 : HARD_REGNO_NREGS (nregno,
6955 GET_MODE (rld[r].reg_rtx)));
6957 spill_reg_store[i] = new_spill_reg_store[i];
6958 spill_reg_stored_to[i] = out;
6959 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
6961 /* If NREGNO is a hard register, it may occupy more than
6962 one register. If it does, say what is in the
6963 rest of the registers assuming that both registers
6964 agree on how many words the object takes. If not,
6965 invalidate the subsequent registers. */
6967 if (nregno < FIRST_PSEUDO_REGISTER)
6968 for (k = 1; k < nnr; k++)
6969 reg_last_reload_reg[nregno + k]
6971 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
6972 REGNO (rld[r].reg_rtx) + k)
6975 /* Now do the inverse operation. */
6976 for (k = 0; k < nr; k++)
6978 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
6979 reg_reloaded_contents[i + k]
6980 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
6983 reg_reloaded_insn[i + k] = insn;
6984 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
6988 /* Maybe the spill reg contains a copy of reload_in. Only do
6989 something if there will not be an output reload for
6990 the register being reloaded. */
6991 else if (rld[r].out_reg == 0
6993 && ((GET_CODE (rld[r].in) == REG
6994 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
6995 && ! reg_has_output_reload[REGNO (rld[r].in)])
6996 || (GET_CODE (rld[r].in_reg) == REG
6997 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
6998 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7000 register int nregno;
7003 if (GET_CODE (rld[r].in) == REG
7004 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7005 nregno = REGNO (rld[r].in);
7006 else if (GET_CODE (rld[r].in_reg) == REG)
7007 nregno = REGNO (rld[r].in_reg);
7009 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7011 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7012 : HARD_REGNO_NREGS (nregno,
7013 GET_MODE (rld[r].reg_rtx)));
7015 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7017 if (nregno < FIRST_PSEUDO_REGISTER)
7018 for (k = 1; k < nnr; k++)
7019 reg_last_reload_reg[nregno + k]
7021 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7022 REGNO (rld[r].reg_rtx) + k)
7025 /* Unless we inherited this reload, show we haven't
7026 recently done a store.
7027 Previous stores of inherited auto_inc expressions
7028 also have to be discarded. */
7029 if (! reload_inherited[r]
7030 || (rld[r].out && ! rld[r].out_reg))
7031 spill_reg_store[i] = 0;
7033 for (k = 0; k < nr; k++)
7035 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7036 reg_reloaded_contents[i + k]
7037 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7040 reg_reloaded_insn[i + k] = insn;
7041 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7046 /* However, if part of the reload reaches the end, then we must
7047 invalidate the old info for the part that survives to the end. */
7048 else if (part_reaches_end)
7050 for (k = 0; k < nr; k++)
7051 if (reload_reg_reaches_end_p (i + k,
7053 rld[r].when_needed))
7054 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7058 /* The following if-statement was #if 0'd in 1.34 (or before...).
7059 It's reenabled in 1.35 because supposedly nothing else
7060 deals with this problem. */
7062 /* If a register gets output-reloaded from a non-spill register,
7063 that invalidates any previous reloaded copy of it.
7064 But forget_old_reloads_1 won't get to see it, because
7065 it thinks only about the original insn. So invalidate it here. */
7066 if (i < 0 && rld[r].out != 0
7067 && (GET_CODE (rld[r].out) == REG
7068 || (GET_CODE (rld[r].out) == MEM
7069 && GET_CODE (rld[r].out_reg) == REG)))
7071 rtx out = (GET_CODE (rld[r].out) == REG
7072 ? rld[r].out : rld[r].out_reg);
7073 register int nregno = REGNO (out);
7074 if (nregno >= FIRST_PSEUDO_REGISTER)
7076 rtx src_reg, store_insn = NULL_RTX;
7078 reg_last_reload_reg[nregno] = 0;
7080 /* If we can find a hard register that is stored, record
7081 the storing insn so that we may delete this insn with
7082 delete_output_reload. */
7083 src_reg = rld[r].reg_rtx;
7085 /* If this is an optional reload, try to find the source reg
7086 from an input reload. */
7089 rtx set = single_set (insn);
7090 if (set && SET_DEST (set) == rld[r].out)
7094 src_reg = SET_SRC (set);
7096 for (k = 0; k < n_reloads; k++)
7098 if (rld[k].in == src_reg)
7100 src_reg = rld[k].reg_rtx;
7107 store_insn = new_spill_reg_store[REGNO (src_reg)];
7108 if (src_reg && GET_CODE (src_reg) == REG
7109 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7111 int src_regno = REGNO (src_reg);
7112 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7113 /* The place where to find a death note varies with
7114 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7115 necessarily checked exactly in the code that moves
7116 notes, so just check both locations. */
7117 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7119 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7122 spill_reg_store[src_regno + nr] = store_insn;
7123 spill_reg_stored_to[src_regno + nr] = out;
7124 reg_reloaded_contents[src_regno + nr] = nregno;
7125 reg_reloaded_insn[src_regno + nr] = store_insn;
7126 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7127 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7128 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7130 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7132 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7134 reg_last_reload_reg[nregno] = src_reg;
7139 int num_regs = HARD_REGNO_NREGS (nregno,GET_MODE (rld[r].out));
7141 while (num_regs-- > 0)
7142 reg_last_reload_reg[nregno + num_regs] = 0;
7146 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7149 /* Emit code to perform a reload from IN (which may be a reload register) to
7150 OUT (which may also be a reload register). IN or OUT is from operand
7151 OPNUM with reload type TYPE.
7153 Returns first insn emitted. */
7156 gen_reload (out, in, opnum, type)
7160 enum reload_type type;
7162 rtx last = get_last_insn ();
7165 /* If IN is a paradoxical SUBREG, remove it and try to put the
7166 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7167 if (GET_CODE (in) == SUBREG
7168 && (GET_MODE_SIZE (GET_MODE (in))
7169 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7170 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7171 in = SUBREG_REG (in), out = tem;
7172 else if (GET_CODE (out) == SUBREG
7173 && (GET_MODE_SIZE (GET_MODE (out))
7174 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7175 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7176 out = SUBREG_REG (out), in = tem;
7178 /* How to do this reload can get quite tricky. Normally, we are being
7179 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7180 register that didn't get a hard register. In that case we can just
7181 call emit_move_insn.
7183 We can also be asked to reload a PLUS that adds a register or a MEM to
7184 another register, constant or MEM. This can occur during frame pointer
7185 elimination and while reloading addresses. This case is handled by
7186 trying to emit a single insn to perform the add. If it is not valid,
7187 we use a two insn sequence.
7189 Finally, we could be called to handle an 'o' constraint by putting
7190 an address into a register. In that case, we first try to do this
7191 with a named pattern of "reload_load_address". If no such pattern
7192 exists, we just emit a SET insn and hope for the best (it will normally
7193 be valid on machines that use 'o').
7195 This entire process is made complex because reload will never
7196 process the insns we generate here and so we must ensure that
7197 they will fit their constraints and also by the fact that parts of
7198 IN might be being reloaded separately and replaced with spill registers.
7199 Because of this, we are, in some sense, just guessing the right approach
7200 here. The one listed above seems to work.
7202 ??? At some point, this whole thing needs to be rethought. */
7204 if (GET_CODE (in) == PLUS
7205 && (GET_CODE (XEXP (in, 0)) == REG
7206 || GET_CODE (XEXP (in, 0)) == SUBREG
7207 || GET_CODE (XEXP (in, 0)) == MEM)
7208 && (GET_CODE (XEXP (in, 1)) == REG
7209 || GET_CODE (XEXP (in, 1)) == SUBREG
7210 || CONSTANT_P (XEXP (in, 1))
7211 || GET_CODE (XEXP (in, 1)) == MEM))
7213 /* We need to compute the sum of a register or a MEM and another
7214 register, constant, or MEM, and put it into the reload
7215 register. The best possible way of doing this is if the machine
7216 has a three-operand ADD insn that accepts the required operands.
7218 The simplest approach is to try to generate such an insn and see if it
7219 is recognized and matches its constraints. If so, it can be used.
7221 It might be better not to actually emit the insn unless it is valid,
7222 but we need to pass the insn as an operand to `recog' and
7223 `extract_insn' and it is simpler to emit and then delete the insn if
7224 not valid than to dummy things up. */
7226 rtx op0, op1, tem, insn;
7229 op0 = find_replacement (&XEXP (in, 0));
7230 op1 = find_replacement (&XEXP (in, 1));
7232 /* Since constraint checking is strict, commutativity won't be
7233 checked, so we need to do that here to avoid spurious failure
7234 if the add instruction is two-address and the second operand
7235 of the add is the same as the reload reg, which is frequently
7236 the case. If the insn would be A = B + A, rearrange it so
7237 it will be A = A + B as constrain_operands expects. */
7239 if (GET_CODE (XEXP (in, 1)) == REG
7240 && REGNO (out) == REGNO (XEXP (in, 1)))
7241 tem = op0, op0 = op1, op1 = tem;
7243 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7244 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7246 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7247 code = recog_memoized (insn);
7251 extract_insn (insn);
7252 /* We want constrain operands to treat this insn strictly in
7253 its validity determination, i.e., the way it would after reload
7255 if (constrain_operands (1))
7259 delete_insns_since (last);
7261 /* If that failed, we must use a conservative two-insn sequence.
7263 Use a move to copy one operand into the reload register. Prefer
7264 to reload a constant, MEM or pseudo since the move patterns can
7265 handle an arbitrary operand. If OP1 is not a constant, MEM or
7266 pseudo and OP1 is not a valid operand for an add instruction, then
7269 After reloading one of the operands into the reload register, add
7270 the reload register to the output register.
7272 If there is another way to do this for a specific machine, a
7273 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7276 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7278 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7279 || (GET_CODE (op1) == REG
7280 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7281 || (code != CODE_FOR_nothing
7282 && ! ((*insn_data[code].operand[2].predicate)
7283 (op1, insn_data[code].operand[2].mode))))
7284 tem = op0, op0 = op1, op1 = tem;
7286 gen_reload (out, op0, opnum, type);
7288 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7289 This fixes a problem on the 32K where the stack pointer cannot
7290 be used as an operand of an add insn. */
7292 if (rtx_equal_p (op0, op1))
7295 insn = emit_insn (gen_add2_insn (out, op1));
7297 /* If that failed, copy the address register to the reload register.
7298 Then add the constant to the reload register. */
7300 code = recog_memoized (insn);
7304 extract_insn (insn);
7305 /* We want constrain operands to treat this insn strictly in
7306 its validity determination, i.e., the way it would after reload
7308 if (constrain_operands (1))
7310 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7312 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7317 delete_insns_since (last);
7319 gen_reload (out, op1, opnum, type);
7320 insn = emit_insn (gen_add2_insn (out, op0));
7321 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7324 #ifdef SECONDARY_MEMORY_NEEDED
7325 /* If we need a memory location to do the move, do it that way. */
7326 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7327 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7328 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7329 REGNO_REG_CLASS (REGNO (out)),
7332 /* Get the memory to use and rewrite both registers to its mode. */
7333 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7335 if (GET_MODE (loc) != GET_MODE (out))
7336 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7338 if (GET_MODE (loc) != GET_MODE (in))
7339 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7341 gen_reload (loc, in, opnum, type);
7342 gen_reload (out, loc, opnum, type);
7346 /* If IN is a simple operand, use gen_move_insn. */
7347 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7348 emit_insn (gen_move_insn (out, in));
7350 #ifdef HAVE_reload_load_address
7351 else if (HAVE_reload_load_address)
7352 emit_insn (gen_reload_load_address (out, in));
7355 /* Otherwise, just write (set OUT IN) and hope for the best. */
7357 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7359 /* Return the first insn emitted.
7360 We can not just return get_last_insn, because there may have
7361 been multiple instructions emitted. Also note that gen_move_insn may
7362 emit more than one insn itself, so we can not assume that there is one
7363 insn emitted per emit_insn_before call. */
7365 return last ? NEXT_INSN (last) : get_insns ();
7368 /* Delete a previously made output-reload
7369 whose result we now believe is not needed.
7370 First we double-check.
7372 INSN is the insn now being processed.
7373 LAST_RELOAD_REG is the hard register number for which we want to delete
7374 the last output reload.
7375 J is the reload-number that originally used REG. The caller has made
7376 certain that reload J doesn't use REG any longer for input. */
7379 delete_output_reload (insn, j, last_reload_reg)
7382 int last_reload_reg;
7384 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7385 rtx reg = spill_reg_stored_to[last_reload_reg];
7388 int n_inherited = 0;
7392 /* Get the raw pseudo-register referred to. */
7394 while (GET_CODE (reg) == SUBREG)
7395 reg = SUBREG_REG (reg);
7396 substed = reg_equiv_memory_loc[REGNO (reg)];
7398 /* This is unsafe if the operand occurs more often in the current
7399 insn than it is inherited. */
7400 for (k = n_reloads - 1; k >= 0; k--)
7402 rtx reg2 = rld[k].in;
7405 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7406 reg2 = rld[k].in_reg;
7408 if (rld[k].out && ! rld[k].out_reg)
7409 reg2 = XEXP (rld[k].in_reg, 0);
7411 while (GET_CODE (reg2) == SUBREG)
7412 reg2 = SUBREG_REG (reg2);
7413 if (rtx_equal_p (reg2, reg))
7415 if (reload_inherited[k] || reload_override_in[k] || k == j)
7418 reg2 = rld[k].out_reg;
7421 while (GET_CODE (reg2) == SUBREG)
7422 reg2 = XEXP (reg2, 0);
7423 if (rtx_equal_p (reg2, reg))
7430 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7432 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7433 if (n_occurrences > n_inherited)
7436 /* If the pseudo-reg we are reloading is no longer referenced
7437 anywhere between the store into it and here,
7438 and no jumps or labels intervene, then the value can get
7439 here through the reload reg alone.
7440 Otherwise, give up--return. */
7441 for (i1 = NEXT_INSN (output_reload_insn);
7442 i1 != insn; i1 = NEXT_INSN (i1))
7444 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7446 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7447 && reg_mentioned_p (reg, PATTERN (i1)))
7449 /* If this is USE in front of INSN, we only have to check that
7450 there are no more references than accounted for by inheritance. */
7451 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7453 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7454 i1 = NEXT_INSN (i1);
7456 if (n_occurrences <= n_inherited && i1 == insn)
7462 /* The caller has already checked that REG dies or is set in INSN.
7463 It has also checked that we are optimizing, and thus some inaccurancies
7464 in the debugging information are acceptable.
7465 So we could just delete output_reload_insn.
7466 But in some cases we can improve the debugging information without
7467 sacrificing optimization - maybe even improving the code:
7468 See if the pseudo reg has been completely replaced
7469 with reload regs. If so, delete the store insn
7470 and forget we had a stack slot for the pseudo. */
7471 if (rld[j].out != rld[j].in
7472 && REG_N_DEATHS (REGNO (reg)) == 1
7473 && REG_N_SETS (REGNO (reg)) == 1
7474 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7475 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7479 /* We know that it was used only between here
7480 and the beginning of the current basic block.
7481 (We also know that the last use before INSN was
7482 the output reload we are thinking of deleting, but never mind that.)
7483 Search that range; see if any ref remains. */
7484 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7486 rtx set = single_set (i2);
7488 /* Uses which just store in the pseudo don't count,
7489 since if they are the only uses, they are dead. */
7490 if (set != 0 && SET_DEST (set) == reg)
7492 if (GET_CODE (i2) == CODE_LABEL
7493 || GET_CODE (i2) == JUMP_INSN)
7495 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7496 && reg_mentioned_p (reg, PATTERN (i2)))
7498 /* Some other ref remains; just delete the output reload we
7500 delete_address_reloads (output_reload_insn, insn);
7501 PUT_CODE (output_reload_insn, NOTE);
7502 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7503 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7508 /* Delete the now-dead stores into this pseudo. */
7509 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7511 rtx set = single_set (i2);
7513 if (set != 0 && SET_DEST (set) == reg)
7515 delete_address_reloads (i2, insn);
7516 /* This might be a basic block head,
7517 thus don't use delete_insn. */
7518 PUT_CODE (i2, NOTE);
7519 NOTE_SOURCE_FILE (i2) = 0;
7520 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7522 if (GET_CODE (i2) == CODE_LABEL
7523 || GET_CODE (i2) == JUMP_INSN)
7527 /* For the debugging info,
7528 say the pseudo lives in this reload reg. */
7529 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7530 alter_reg (REGNO (reg), -1);
7532 delete_address_reloads (output_reload_insn, insn);
7533 PUT_CODE (output_reload_insn, NOTE);
7534 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7535 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7539 /* We are going to delete DEAD_INSN. Recursively delete loads of
7540 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7541 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7543 delete_address_reloads (dead_insn, current_insn)
7544 rtx dead_insn, current_insn;
7546 rtx set = single_set (dead_insn);
7547 rtx set2, dst, prev, next;
7550 rtx dst = SET_DEST (set);
7551 if (GET_CODE (dst) == MEM)
7552 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7554 /* If we deleted the store from a reloaded post_{in,de}c expression,
7555 we can delete the matching adds. */
7556 prev = PREV_INSN (dead_insn);
7557 next = NEXT_INSN (dead_insn);
7558 if (! prev || ! next)
7560 set = single_set (next);
7561 set2 = single_set (prev);
7563 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7564 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7565 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7567 dst = SET_DEST (set);
7568 if (! rtx_equal_p (dst, SET_DEST (set2))
7569 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7570 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7571 || (INTVAL (XEXP (SET_SRC (set), 1))
7572 != - INTVAL (XEXP (SET_SRC (set2), 1))))
7578 /* Subfunction of delete_address_reloads: process registers found in X. */
7580 delete_address_reloads_1 (dead_insn, x, current_insn)
7581 rtx dead_insn, x, current_insn;
7583 rtx prev, set, dst, i2;
7585 enum rtx_code code = GET_CODE (x);
7589 const char *fmt= GET_RTX_FORMAT (code);
7590 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7593 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7594 else if (fmt[i] == 'E')
7596 for (j = XVECLEN (x, i) - 1; j >=0; j--)
7597 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7604 if (spill_reg_order[REGNO (x)] < 0)
7607 /* Scan backwards for the insn that sets x. This might be a way back due
7609 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7611 code = GET_CODE (prev);
7612 if (code == CODE_LABEL || code == JUMP_INSN)
7614 if (GET_RTX_CLASS (code) != 'i')
7616 if (reg_set_p (x, PATTERN (prev)))
7618 if (reg_referenced_p (x, PATTERN (prev)))
7621 if (! prev || INSN_UID (prev) < reload_first_uid)
7623 /* Check that PREV only sets the reload register. */
7624 set = single_set (prev);
7627 dst = SET_DEST (set);
7628 if (GET_CODE (dst) != REG
7629 || ! rtx_equal_p (dst, x))
7631 if (! reg_set_p (dst, PATTERN (dead_insn)))
7633 /* Check if DST was used in a later insn -
7634 it might have been inherited. */
7635 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7637 if (GET_CODE (i2) == CODE_LABEL)
7641 if (reg_referenced_p (dst, PATTERN (i2)))
7643 /* If there is a reference to the register in the current insn,
7644 it might be loaded in a non-inherited reload. If no other
7645 reload uses it, that means the register is set before
7647 if (i2 == current_insn)
7649 for (j = n_reloads - 1; j >= 0; j--)
7650 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7651 || reload_override_in[j] == dst)
7653 for (j = n_reloads - 1; j >= 0; j--)
7654 if (rld[j].in && rld[j].reg_rtx == dst)
7661 if (GET_CODE (i2) == JUMP_INSN)
7663 /* If DST is still live at CURRENT_INSN, check if it is used for
7664 any reload. Note that even if CURRENT_INSN sets DST, we still
7665 have to check the reloads. */
7666 if (i2 == current_insn)
7668 for (j = n_reloads - 1; j >= 0; j--)
7669 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7670 || reload_override_in[j] == dst)
7672 /* ??? We can't finish the loop here, because dst might be
7673 allocated to a pseudo in this block if no reload in this
7674 block needs any of the clsses containing DST - see
7675 spill_hard_reg. There is no easy way to tell this, so we
7676 have to scan till the end of the basic block. */
7678 if (reg_set_p (dst, PATTERN (i2)))
7682 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7683 reg_reloaded_contents[REGNO (dst)] = -1;
7684 /* Can't use delete_insn here because PREV might be a basic block head. */
7685 PUT_CODE (prev, NOTE);
7686 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7687 NOTE_SOURCE_FILE (prev) = 0;
7690 /* Output reload-insns to reload VALUE into RELOADREG.
7691 VALUE is an autoincrement or autodecrement RTX whose operand
7692 is a register or memory location;
7693 so reloading involves incrementing that location.
7694 IN is either identical to VALUE, or some cheaper place to reload from.
7696 INC_AMOUNT is the number to increment or decrement by (always positive).
7697 This cannot be deduced from VALUE.
7699 Return the instruction that stores into RELOADREG. */
7702 inc_for_reload (reloadreg, in, value, inc_amount)
7707 /* REG or MEM to be copied and incremented. */
7708 rtx incloc = XEXP (value, 0);
7709 /* Nonzero if increment after copying. */
7710 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7716 rtx real_in = in == value ? XEXP (in, 0) : in;
7718 /* No hard register is equivalent to this register after
7719 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7720 we could inc/dec that register as well (maybe even using it for
7721 the source), but I'm not sure it's worth worrying about. */
7722 if (GET_CODE (incloc) == REG)
7723 reg_last_reload_reg[REGNO (incloc)] = 0;
7725 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7726 inc_amount = - inc_amount;
7728 inc = GEN_INT (inc_amount);
7730 /* If this is post-increment, first copy the location to the reload reg. */
7731 if (post && real_in != reloadreg)
7732 emit_insn (gen_move_insn (reloadreg, real_in));
7736 /* See if we can directly increment INCLOC. Use a method similar to
7737 that in gen_reload. */
7739 last = get_last_insn ();
7740 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7741 gen_rtx_PLUS (GET_MODE (incloc),
7744 code = recog_memoized (add_insn);
7747 extract_insn (add_insn);
7748 if (constrain_operands (1))
7750 /* If this is a pre-increment and we have incremented the value
7751 where it lives, copy the incremented value to RELOADREG to
7752 be used as an address. */
7755 emit_insn (gen_move_insn (reloadreg, incloc));
7760 delete_insns_since (last);
7763 /* If couldn't do the increment directly, must increment in RELOADREG.
7764 The way we do this depends on whether this is pre- or post-increment.
7765 For pre-increment, copy INCLOC to the reload register, increment it
7766 there, then save back. */
7770 if (in != reloadreg)
7771 emit_insn (gen_move_insn (reloadreg, real_in));
7772 emit_insn (gen_add2_insn (reloadreg, inc));
7773 store = emit_insn (gen_move_insn (incloc, reloadreg));
7778 Because this might be a jump insn or a compare, and because RELOADREG
7779 may not be available after the insn in an input reload, we must do
7780 the incrementation before the insn being reloaded for.
7782 We have already copied IN to RELOADREG. Increment the copy in
7783 RELOADREG, save that back, then decrement RELOADREG so it has
7784 the original value. */
7786 emit_insn (gen_add2_insn (reloadreg, inc));
7787 store = emit_insn (gen_move_insn (incloc, reloadreg));
7788 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7794 /* Return 1 if we are certain that the constraint-string STRING allows
7795 the hard register REG. Return 0 if we can't be sure of this. */
7798 constraint_accepts_reg_p (string, reg)
7803 int regno = true_regnum (reg);
7806 /* Initialize for first alternative. */
7808 /* Check that each alternative contains `g' or `r'. */
7810 switch (c = *string++)
7813 /* If an alternative lacks `g' or `r', we lose. */
7816 /* If an alternative lacks `g' or `r', we lose. */
7819 /* Initialize for next alternative. */
7824 /* Any general reg wins for this alternative. */
7825 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7829 /* Any reg in specified class wins for this alternative. */
7831 enum reg_class class = REG_CLASS_FROM_LETTER (c);
7833 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
7839 /* INSN is a no-op; delete it.
7840 If this sets the return value of the function, we must keep a USE around,
7841 in case this is in a different basic block than the final USE. Otherwise,
7842 we could loose important register lifeness information on
7843 SMALL_REGISTER_CLASSES machines, where return registers might be used as
7844 spills: subsequent passes assume that spill registers are dead at the end
7846 VALUE must be the return value in such a case, NULL otherwise. */
7848 reload_cse_delete_noop_set (insn, value)
7853 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
7854 INSN_CODE (insn) = -1;
7855 REG_NOTES (insn) = NULL_RTX;
7859 PUT_CODE (insn, NOTE);
7860 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
7861 NOTE_SOURCE_FILE (insn) = 0;
7865 /* See whether a single set SET is a noop. */
7867 reload_cse_noop_set_p (set)
7870 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
7873 /* Try to simplify INSN. */
7875 reload_cse_simplify (insn)
7878 rtx body = PATTERN (insn);
7880 if (GET_CODE (body) == SET)
7883 if (reload_cse_noop_set_p (body))
7885 rtx value = SET_DEST (body);
7886 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
7888 reload_cse_delete_noop_set (insn, value);
7892 /* It's not a no-op, but we can try to simplify it. */
7893 count += reload_cse_simplify_set (body, insn);
7896 apply_change_group ();
7898 reload_cse_simplify_operands (insn);
7900 else if (GET_CODE (body) == PARALLEL)
7904 rtx value = NULL_RTX;
7906 /* If every action in a PARALLEL is a noop, we can delete
7907 the entire PARALLEL. */
7908 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7910 rtx part = XVECEXP (body, 0, i);
7911 if (GET_CODE (part) == SET)
7913 if (! reload_cse_noop_set_p (part))
7915 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
7919 value = SET_DEST (part);
7922 else if (GET_CODE (part) != CLOBBER)
7928 reload_cse_delete_noop_set (insn, value);
7929 /* We're done with this insn. */
7933 /* It's not a no-op, but we can try to simplify it. */
7934 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
7935 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
7936 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
7939 apply_change_group ();
7941 reload_cse_simplify_operands (insn);
7945 /* Do a very simple CSE pass over the hard registers.
7947 This function detects no-op moves where we happened to assign two
7948 different pseudo-registers to the same hard register, and then
7949 copied one to the other. Reload will generate a useless
7950 instruction copying a register to itself.
7952 This function also detects cases where we load a value from memory
7953 into two different registers, and (if memory is more expensive than
7954 registers) changes it to simply copy the first register into the
7957 Another optimization is performed that scans the operands of each
7958 instruction to see whether the value is already available in a
7959 hard register. It then replaces the operand with the hard register
7960 if possible, much like an optional reload would. */
7963 reload_cse_regs_1 (first)
7969 init_alias_analysis ();
7971 for (insn = first; insn; insn = NEXT_INSN (insn))
7974 reload_cse_simplify (insn);
7976 cselib_process_insn (insn);
7980 end_alias_analysis ();
7984 /* Call cse / combine like post-reload optimization phases.
7985 FIRST is the first instruction. */
7987 reload_cse_regs (first)
7990 reload_cse_regs_1 (first);
7992 reload_cse_move2add (first);
7993 if (flag_expensive_optimizations)
7994 reload_cse_regs_1 (first);
7997 /* Try to simplify a single SET instruction. SET is the set pattern.
7998 INSN is the instruction it came from.
7999 This function only handles one case: if we set a register to a value
8000 which is not a register, we try to find that value in some other register
8001 and change the set into a register copy. */
8004 reload_cse_simplify_set (set, insn)
8011 enum reg_class dclass;
8014 struct elt_loc_list *l;
8016 dreg = true_regnum (SET_DEST (set));
8020 src = SET_SRC (set);
8021 if (side_effects_p (src) || true_regnum (src) >= 0)
8024 dclass = REGNO_REG_CLASS (dreg);
8026 /* If memory loads are cheaper than register copies, don't change them. */
8027 if (GET_CODE (src) == MEM)
8028 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8029 else if (CONSTANT_P (src))
8030 old_cost = rtx_cost (src, SET);
8031 else if (GET_CODE (src) == REG)
8032 old_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (src)), dclass);
8035 old_cost = rtx_cost (src, SET);
8037 val = cselib_lookup (src, VOIDmode, 0);
8040 for (l = val->locs; l; l = l->next)
8043 if (CONSTANT_P (l->loc) && ! references_value_p (l->loc, 0))
8044 this_cost = rtx_cost (l->loc, SET);
8045 else if (GET_CODE (l->loc) == REG)
8046 this_cost = REGISTER_MOVE_COST (REGNO_REG_CLASS (REGNO (l->loc)),
8050 /* If equal costs, prefer registers over anything else. That tends to
8051 lead to smaller instructions on some machines. */
8052 if ((this_cost < old_cost
8053 || (this_cost == old_cost
8054 && GET_CODE (l->loc) == REG
8055 && GET_CODE (SET_SRC (set)) != REG))
8056 && validate_change (insn, &SET_SRC (set), copy_rtx (l->loc), 1))
8057 old_cost = this_cost, did_change = 1;
8063 /* Try to replace operands in INSN with equivalent values that are already
8064 in registers. This can be viewed as optional reloading.
8066 For each non-register operand in the insn, see if any hard regs are
8067 known to be equivalent to that operand. Record the alternatives which
8068 can accept these hard registers. Among all alternatives, select the
8069 ones which are better or equal to the one currently matching, where
8070 "better" is in terms of '?' and '!' constraints. Among the remaining
8071 alternatives, select the one which replaces most operands with
8075 reload_cse_simplify_operands (insn)
8080 /* For each operand, all registers that are equivalent to it. */
8081 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8083 const char *constraints[MAX_RECOG_OPERANDS];
8085 /* Vector recording how bad an alternative is. */
8086 int *alternative_reject;
8087 /* Vector recording how many registers can be introduced by choosing
8088 this alternative. */
8089 int *alternative_nregs;
8090 /* Array of vectors recording, for each operand and each alternative,
8091 which hard register to substitute, or -1 if the operand should be
8093 int *op_alt_regno[MAX_RECOG_OPERANDS];
8094 /* Array of alternatives, sorted in order of decreasing desirability. */
8095 int *alternative_order;
8096 rtx reg = gen_rtx_REG (VOIDmode, -1);
8098 extract_insn (insn);
8100 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8103 /* Figure out which alternative currently matches. */
8104 if (! constrain_operands (1))
8105 fatal_insn_not_found (insn);
8107 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8108 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8109 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8110 bzero ((char *)alternative_reject, recog_data.n_alternatives * sizeof (int));
8111 bzero ((char *)alternative_nregs, recog_data.n_alternatives * sizeof (int));
8113 /* For each operand, find out which regs are equivalent. */
8114 for (i = 0; i < recog_data.n_operands; i++)
8117 struct elt_loc_list *l;
8119 CLEAR_HARD_REG_SET (equiv_regs[i]);
8121 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8122 right, so avoid the problem here. */
8123 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL)
8126 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8130 for (l = v->locs; l; l = l->next)
8131 if (GET_CODE (l->loc) == REG)
8132 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8135 for (i = 0; i < recog_data.n_operands; i++)
8137 enum machine_mode mode;
8141 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8142 for (j = 0; j < recog_data.n_alternatives; j++)
8143 op_alt_regno[i][j] = -1;
8145 p = constraints[i] = recog_data.constraints[i];
8146 mode = recog_data.operand_mode[i];
8148 /* Add the reject values for each alternative given by the constraints
8149 for this operand. */
8157 alternative_reject[j] += 3;
8159 alternative_reject[j] += 300;
8162 /* We won't change operands which are already registers. We
8163 also don't want to modify output operands. */
8164 regno = true_regnum (recog_data.operand[i]);
8166 || constraints[i][0] == '='
8167 || constraints[i][0] == '+')
8170 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8172 int class = (int) NO_REGS;
8174 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8177 REGNO (reg) = regno;
8178 PUT_MODE (reg, mode);
8180 /* We found a register equal to this operand. Now look for all
8181 alternatives that can accept this register and have not been
8182 assigned a register they can use yet. */
8191 case '=': case '+': case '?':
8192 case '#': case '&': case '!':
8194 case '0': case '1': case '2': case '3': case '4':
8195 case '5': case '6': case '7': case '8': case '9':
8196 case 'm': case '<': case '>': case 'V': case 'o':
8197 case 'E': case 'F': case 'G': case 'H':
8198 case 's': case 'i': case 'n':
8199 case 'I': case 'J': case 'K': case 'L':
8200 case 'M': case 'N': case 'O': case 'P':
8201 #ifdef EXTRA_CONSTRAINT
8202 case 'Q': case 'R': case 'S': case 'T': case 'U':
8205 /* These don't say anything we care about. */
8209 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8214 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8217 case ',': case '\0':
8218 /* See if REGNO fits this alternative, and set it up as the
8219 replacement register if we don't have one for this
8220 alternative yet and the operand being replaced is not
8221 a cheap CONST_INT. */
8222 if (op_alt_regno[i][j] == -1
8223 && reg_fits_class_p (reg, class, 0, mode)
8224 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8225 || (rtx_cost (recog_data.operand[i], SET)
8226 > rtx_cost (reg, SET))))
8228 alternative_nregs[j]++;
8229 op_alt_regno[i][j] = regno;
8241 /* Record all alternatives which are better or equal to the currently
8242 matching one in the alternative_order array. */
8243 for (i = j = 0; i < recog_data.n_alternatives; i++)
8244 if (alternative_reject[i] <= alternative_reject[which_alternative])
8245 alternative_order[j++] = i;
8246 recog_data.n_alternatives = j;
8248 /* Sort it. Given a small number of alternatives, a dumb algorithm
8249 won't hurt too much. */
8250 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8253 int best_reject = alternative_reject[alternative_order[i]];
8254 int best_nregs = alternative_nregs[alternative_order[i]];
8257 for (j = i + 1; j < recog_data.n_alternatives; j++)
8259 int this_reject = alternative_reject[alternative_order[j]];
8260 int this_nregs = alternative_nregs[alternative_order[j]];
8262 if (this_reject < best_reject
8263 || (this_reject == best_reject && this_nregs < best_nregs))
8266 best_reject = this_reject;
8267 best_nregs = this_nregs;
8271 tmp = alternative_order[best];
8272 alternative_order[best] = alternative_order[i];
8273 alternative_order[i] = tmp;
8276 /* Substitute the operands as determined by op_alt_regno for the best
8278 j = alternative_order[0];
8280 for (i = 0; i < recog_data.n_operands; i++)
8282 enum machine_mode mode = recog_data.operand_mode[i];
8283 if (op_alt_regno[i][j] == -1)
8286 validate_change (insn, recog_data.operand_loc[i],
8287 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8290 for (i = recog_data.n_dups - 1; i >= 0; i--)
8292 int op = recog_data.dup_num[i];
8293 enum machine_mode mode = recog_data.operand_mode[op];
8295 if (op_alt_regno[op][j] == -1)
8298 validate_change (insn, recog_data.dup_loc[i],
8299 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8302 return apply_change_group ();
8305 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8307 This code might also be useful when reload gave up on reg+reg addresssing
8308 because of clashes between the return register and INDEX_REG_CLASS. */
8310 /* The maximum number of uses of a register we can keep track of to
8311 replace them with reg+reg addressing. */
8312 #define RELOAD_COMBINE_MAX_USES 6
8314 /* INSN is the insn where a register has ben used, and USEP points to the
8315 location of the register within the rtl. */
8316 struct reg_use { rtx insn, *usep; };
8318 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8319 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8320 indicates where it becomes live again.
8321 Otherwise, USE_INDEX is the index of the last encountered use of the
8322 register (which is first among these we have seen since we scan backwards),
8323 OFFSET contains the constant offset that is added to the register in
8324 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8325 last, of these uses.
8326 STORE_RUID is always meaningful if we only want to use a value in a
8327 register in a different place: it denotes the next insn in the insn
8328 stream (i.e. the last ecountered) that sets or clobbers the register. */
8331 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8336 } reg_state[FIRST_PSEUDO_REGISTER];
8338 /* Reverse linear uid. This is increased in reload_combine while scanning
8339 the instructions from last to first. It is used to set last_label_ruid
8340 and the store_ruid / use_ruid fields in reg_state. */
8341 static int reload_combine_ruid;
8343 #define LABEL_LIVE(LABEL) \
8344 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8350 int first_index_reg = 1, last_index_reg = 0;
8353 int last_label_ruid;
8354 int min_labelno, n_labels;
8355 HARD_REG_SET ever_live_at_start, *label_live;
8357 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8358 reload has already used it where appropriate, so there is no use in
8359 trying to generate it now. */
8360 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8363 /* To avoid wasting too much time later searching for an index register,
8364 determine the minimum and maximum index register numbers. */
8365 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8366 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8368 if (! first_index_reg)
8369 first_index_reg = r;
8374 /* If no index register is available, we can quit now. */
8375 if (first_index_reg > last_index_reg)
8378 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8379 information is a bit fuzzy immediately after reload, but it's
8380 still good enough to determine which registers are live at a jump
8382 min_labelno = get_first_label_num ();
8383 n_labels = max_label_num () - min_labelno;
8384 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8385 CLEAR_HARD_REG_SET (ever_live_at_start);
8387 for (i = n_basic_blocks - 1; i >= 0; i--)
8389 insn = BLOCK_HEAD (i);
8390 if (GET_CODE (insn) == CODE_LABEL)
8394 REG_SET_TO_HARD_REG_SET (live,
8395 BASIC_BLOCK (i)->global_live_at_start);
8396 compute_use_by_pseudos (&live,
8397 BASIC_BLOCK (i)->global_live_at_start);
8398 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8399 IOR_HARD_REG_SET (ever_live_at_start, live);
8403 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8404 last_label_ruid = reload_combine_ruid = 0;
8405 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8407 reg_state[r].store_ruid = reload_combine_ruid;
8409 reg_state[r].use_index = -1;
8411 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8414 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8418 /* We cannot do our optimization across labels. Invalidating all the use
8419 information we have would be costly, so we just note where the label
8420 is and then later disable any optimization that would cross it. */
8421 if (GET_CODE (insn) == CODE_LABEL)
8422 last_label_ruid = reload_combine_ruid;
8423 else if (GET_CODE (insn) == BARRIER)
8424 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8425 if (! fixed_regs[r])
8426 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8428 if (! INSN_P (insn))
8431 reload_combine_ruid++;
8433 /* Look for (set (REGX) (CONST_INT))
8434 (set (REGX) (PLUS (REGX) (REGY)))
8436 ... (MEM (REGX)) ...
8438 (set (REGZ) (CONST_INT))
8440 ... (MEM (PLUS (REGZ) (REGY)))... .
8442 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8443 and that we know all uses of REGX before it dies. */
8444 set = single_set (insn);
8446 && GET_CODE (SET_DEST (set)) == REG
8447 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8448 GET_MODE (SET_DEST (set)))
8450 && GET_CODE (SET_SRC (set)) == PLUS
8451 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8452 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8453 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8455 rtx reg = SET_DEST (set);
8456 rtx plus = SET_SRC (set);
8457 rtx base = XEXP (plus, 1);
8458 rtx prev = prev_nonnote_insn (insn);
8459 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8460 unsigned int regno = REGNO (reg);
8461 rtx const_reg = NULL_RTX;
8462 rtx reg_sum = NULL_RTX;
8464 /* Now, we need an index register.
8465 We'll set index_reg to this index register, const_reg to the
8466 register that is to be loaded with the constant
8467 (denoted as REGZ in the substitution illustration above),
8468 and reg_sum to the register-register that we want to use to
8469 substitute uses of REG (typically in MEMs) with.
8470 First check REG and BASE for being index registers;
8471 we can use them even if they are not dead. */
8472 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8473 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8481 /* Otherwise, look for a free index register. Since we have
8482 checked above that neiter REG nor BASE are index registers,
8483 if we find anything at all, it will be different from these
8485 for (i = first_index_reg; i <= last_index_reg; i++)
8487 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8489 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8490 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8491 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8493 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8495 const_reg = index_reg;
8496 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8502 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8503 (REGY), i.e. BASE, is not clobbered before the last use we'll
8506 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8507 && rtx_equal_p (SET_DEST (prev_set), reg)
8508 && reg_state[regno].use_index >= 0
8509 && (reg_state[REGNO (base)].store_ruid
8510 <= reg_state[regno].use_ruid)
8515 /* Change destination register and, if necessary, the
8516 constant value in PREV, the constant loading instruction. */
8517 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8518 if (reg_state[regno].offset != const0_rtx)
8519 validate_change (prev,
8520 &SET_SRC (prev_set),
8521 GEN_INT (INTVAL (SET_SRC (prev_set))
8522 + INTVAL (reg_state[regno].offset)),
8525 /* Now for every use of REG that we have recorded, replace REG
8527 for (i = reg_state[regno].use_index;
8528 i < RELOAD_COMBINE_MAX_USES; i++)
8529 validate_change (reg_state[regno].reg_use[i].insn,
8530 reg_state[regno].reg_use[i].usep,
8533 if (apply_change_group ())
8537 /* Delete the reg-reg addition. */
8538 PUT_CODE (insn, NOTE);
8539 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8540 NOTE_SOURCE_FILE (insn) = 0;
8542 if (reg_state[regno].offset != const0_rtx)
8543 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8545 for (np = ®_NOTES (prev); *np; )
8547 if (REG_NOTE_KIND (*np) == REG_EQUAL
8548 || REG_NOTE_KIND (*np) == REG_EQUIV)
8549 *np = XEXP (*np, 1);
8551 np = &XEXP (*np, 1);
8554 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8555 reg_state[REGNO (const_reg)].store_ruid
8556 = reload_combine_ruid;
8562 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8564 if (GET_CODE (insn) == CALL_INSN)
8568 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8569 if (call_used_regs[r])
8571 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8572 reg_state[r].store_ruid = reload_combine_ruid;
8575 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8576 link = XEXP (link, 1))
8577 if (GET_CODE (XEXP (XEXP (link, 0), 0)) == REG)
8579 unsigned int regno = REGNO (XEXP (XEXP (link, 0), 0));
8581 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8583 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8584 reg_state[regno].store_ruid = reload_combine_ruid;
8587 reg_state[regno].use_index = -1;
8591 else if (GET_CODE (insn) == JUMP_INSN
8592 && GET_CODE (PATTERN (insn)) != RETURN)
8594 /* Non-spill registers might be used at the call destination in
8595 some unknown fashion, so we have to mark the unknown use. */
8598 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8599 && JUMP_LABEL (insn))
8600 live = &LABEL_LIVE (JUMP_LABEL (insn));
8602 live = &ever_live_at_start;
8604 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8605 if (TEST_HARD_REG_BIT (*live, i))
8606 reg_state[i].use_index = -1;
8609 reload_combine_note_use (&PATTERN (insn), insn);
8610 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8612 if (REG_NOTE_KIND (note) == REG_INC
8613 && GET_CODE (XEXP (note, 0)) == REG)
8615 int regno = REGNO (XEXP (note, 0));
8617 reg_state[regno].store_ruid = reload_combine_ruid;
8618 reg_state[regno].use_index = -1;
8626 /* Check if DST is a register or a subreg of a register; if it is,
8627 update reg_state[regno].store_ruid and reg_state[regno].use_index
8628 accordingly. Called via note_stores from reload_combine. */
8631 reload_combine_note_store (dst, set, data)
8633 void *data ATTRIBUTE_UNUSED;
8637 enum machine_mode mode = GET_MODE (dst);
8639 if (GET_CODE (dst) == SUBREG)
8641 regno = SUBREG_WORD (dst);
8642 dst = SUBREG_REG (dst);
8644 if (GET_CODE (dst) != REG)
8646 regno += REGNO (dst);
8648 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8649 careful with registers / register parts that are not full words.
8651 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8652 if (GET_CODE (set) != SET
8653 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8654 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8655 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8657 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8659 reg_state[i].use_index = -1;
8660 reg_state[i].store_ruid = reload_combine_ruid;
8665 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8667 reg_state[i].store_ruid = reload_combine_ruid;
8668 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8673 /* XP points to a piece of rtl that has to be checked for any uses of
8675 *XP is the pattern of INSN, or a part of it.
8676 Called from reload_combine, and recursively by itself. */
8678 reload_combine_note_use (xp, insn)
8682 enum rtx_code code = x->code;
8685 rtx offset = const0_rtx; /* For the REG case below. */
8690 if (GET_CODE (SET_DEST (x)) == REG)
8692 reload_combine_note_use (&SET_SRC (x), insn);
8698 /* If this is the USE of a return value, we can't change it. */
8699 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8701 /* Mark the return register as used in an unknown fashion. */
8702 rtx reg = XEXP (x, 0);
8703 int regno = REGNO (reg);
8704 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8706 while (--nregs >= 0)
8707 reg_state[regno + nregs].use_index = -1;
8713 if (GET_CODE (SET_DEST (x)) == REG)
8718 /* We are interested in (plus (reg) (const_int)) . */
8719 if (GET_CODE (XEXP (x, 0)) != REG || GET_CODE (XEXP (x, 1)) != CONST_INT)
8721 offset = XEXP (x, 1);
8726 int regno = REGNO (x);
8730 /* Some spurious USEs of pseudo registers might remain.
8731 Just ignore them. */
8732 if (regno >= FIRST_PSEUDO_REGISTER)
8735 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8737 /* We can't substitute into multi-hard-reg uses. */
8740 while (--nregs >= 0)
8741 reg_state[regno + nregs].use_index = -1;
8745 /* If this register is already used in some unknown fashion, we
8747 If we decrement the index from zero to -1, we can't store more
8748 uses, so this register becomes used in an unknown fashion. */
8749 use_index = --reg_state[regno].use_index;
8753 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
8755 /* We have found another use for a register that is already
8756 used later. Check if the offsets match; if not, mark the
8757 register as used in an unknown fashion. */
8758 if (! rtx_equal_p (offset, reg_state[regno].offset))
8760 reg_state[regno].use_index = -1;
8766 /* This is the first use of this register we have seen since we
8767 marked it as dead. */
8768 reg_state[regno].offset = offset;
8769 reg_state[regno].use_ruid = reload_combine_ruid;
8771 reg_state[regno].reg_use[use_index].insn = insn;
8772 reg_state[regno].reg_use[use_index].usep = xp;
8780 /* Recursively process the components of X. */
8781 fmt = GET_RTX_FORMAT (code);
8782 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8785 reload_combine_note_use (&XEXP (x, i), insn);
8786 else if (fmt[i] == 'E')
8788 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8789 reload_combine_note_use (&XVECEXP (x, i, j), insn);
8794 /* See if we can reduce the cost of a constant by replacing a move with
8796 /* We cannot do our optimization across labels. Invalidating all the
8797 information about register contents we have would be costly, so we
8798 use last_label_luid (local variable of reload_cse_move2add) to note
8799 where the label is and then later disable any optimization that would
8801 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
8802 reg_set_luid[n] is larger than last_label_luid[n] . */
8803 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
8805 /* reg_offset[n] has to be CONST_INT for it and reg_base_reg[n] /
8806 reg_mode[n] to be valid.
8807 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is negative, register n
8808 has been set to reg_offset[n] in mode reg_mode[n] .
8809 If reg_offset[n] is a CONST_INT and reg_base_reg[n] is non-negative,
8810 register n has been set to the sum of reg_offset[n] and register
8811 reg_base_reg[n], calculated in mode reg_mode[n] . */
8812 static rtx reg_offset[FIRST_PSEUDO_REGISTER];
8813 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
8814 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
8816 /* move2add_luid is linearily increased while scanning the instructions
8817 from first to last. It is used to set reg_set_luid in
8818 reload_cse_move2add and move2add_note_store. */
8819 static int move2add_luid;
8821 /* Generate a CONST_INT and force it in the range of MODE. */
8824 gen_mode_int (mode, value)
8825 enum machine_mode mode;
8826 HOST_WIDE_INT value;
8828 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
8829 int width = GET_MODE_BITSIZE (mode);
8831 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
8833 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
8834 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
8835 cval |= (HOST_WIDE_INT) -1 << width;
8837 return GEN_INT (cval);
8841 reload_cse_move2add (first)
8846 int last_label_luid;
8848 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
8849 reg_set_luid[i] = 0;
8851 last_label_luid = 0;
8853 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
8857 if (GET_CODE (insn) == CODE_LABEL)
8858 last_label_luid = move2add_luid;
8859 if (! INSN_P (insn))
8861 pat = PATTERN (insn);
8862 /* For simplicity, we only perform this optimization on
8863 straightforward SETs. */
8864 if (GET_CODE (pat) == SET
8865 && GET_CODE (SET_DEST (pat)) == REG)
8867 rtx reg = SET_DEST (pat);
8868 int regno = REGNO (reg);
8869 rtx src = SET_SRC (pat);
8871 /* Check if we have valid information on the contents of this
8872 register in the mode of REG. */
8873 /* ??? We don't know how zero / sign extension is handled, hence
8874 we can't go from a narrower to a wider mode. */
8875 if (reg_set_luid[regno] > last_label_luid
8876 && ((GET_MODE_SIZE (GET_MODE (reg))
8877 == GET_MODE_SIZE (reg_mode[regno]))
8878 || ((GET_MODE_SIZE (GET_MODE (reg))
8879 <= GET_MODE_SIZE (reg_mode[regno]))
8880 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (GET_MODE (reg)),
8881 GET_MODE_BITSIZE (reg_mode[regno]))))
8882 && GET_CODE (reg_offset[regno]) == CONST_INT)
8884 /* Try to transform (set (REGX) (CONST_INT A))
8886 (set (REGX) (CONST_INT B))
8888 (set (REGX) (CONST_INT A))
8890 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8892 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
8896 = gen_mode_int (GET_MODE (reg),
8897 INTVAL (src) - INTVAL (reg_offset[regno]));
8898 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
8899 use (set (reg) (reg)) instead.
8900 We don't delete this insn, nor do we convert it into a
8901 note, to avoid losing register notes or the return
8902 value flag. jump2 already knowns how to get rid of
8904 if (new_src == const0_rtx)
8905 success = validate_change (insn, &SET_SRC (pat), reg, 0);
8906 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
8907 && have_add2_insn (GET_MODE (reg)))
8908 success = validate_change (insn, &PATTERN (insn),
8909 gen_add2_insn (reg, new_src), 0);
8910 reg_set_luid[regno] = move2add_luid;
8911 reg_mode[regno] = GET_MODE (reg);
8912 reg_offset[regno] = src;
8916 /* Try to transform (set (REGX) (REGY))
8917 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8920 (set (REGX) (PLUS (REGX) (CONST_INT B)))
8923 (set (REGX) (PLUS (REGX) (CONST_INT A)))
8925 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
8926 else if (GET_CODE (src) == REG
8927 && reg_base_reg[regno] == (int) REGNO (src)
8928 && reg_set_luid[regno] > reg_set_luid[REGNO (src)])
8930 rtx next = next_nonnote_insn (insn);
8933 set = single_set (next);
8936 && SET_DEST (set) == reg
8937 && GET_CODE (SET_SRC (set)) == PLUS
8938 && XEXP (SET_SRC (set), 0) == reg
8939 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
8941 rtx src3 = XEXP (SET_SRC (set), 1);
8943 = gen_mode_int (GET_MODE (reg),
8945 - INTVAL (reg_offset[regno]));
8948 if (new_src == const0_rtx)
8949 /* See above why we create (set (reg) (reg)) here. */
8951 = validate_change (next, &SET_SRC (set), reg, 0);
8952 else if ((rtx_cost (new_src, PLUS)
8953 < 2 + rtx_cost (src3, SET))
8954 && have_add2_insn (GET_MODE (reg)))
8956 = validate_change (next, &PATTERN (next),
8957 gen_add2_insn (reg, new_src), 0);
8960 /* INSN might be the first insn in a basic block
8961 if the preceding insn is a conditional jump
8962 or a possible-throwing call. */
8963 PUT_CODE (insn, NOTE);
8964 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8965 NOTE_SOURCE_FILE (insn) = 0;
8968 reg_set_luid[regno] = move2add_luid;
8969 reg_mode[regno] = GET_MODE (reg);
8970 reg_offset[regno] = src3;
8977 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8979 if (REG_NOTE_KIND (note) == REG_INC
8980 && GET_CODE (XEXP (note, 0)) == REG)
8982 /* Indicate that this register has been recently written to,
8983 but the exact contents are not available. */
8984 int regno = REGNO (XEXP (note, 0));
8985 if (regno < FIRST_PSEUDO_REGISTER)
8987 reg_set_luid[regno] = move2add_luid;
8988 reg_offset[regno] = note;
8992 note_stores (PATTERN (insn), move2add_note_store, NULL);
8993 /* If this is a CALL_INSN, all call used registers are stored with
8995 if (GET_CODE (insn) == CALL_INSN)
8997 for (i = FIRST_PSEUDO_REGISTER-1; i >= 0; i--)
8999 if (call_used_regs[i])
9001 reg_set_luid[i] = move2add_luid;
9002 reg_offset[i] = insn; /* Invalidate contents. */
9009 /* SET is a SET or CLOBBER that sets DST.
9010 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9011 Called from reload_cse_move2add via note_stores. */
9014 move2add_note_store (dst, set, data)
9016 void *data ATTRIBUTE_UNUSED;
9018 unsigned int regno = 0;
9020 enum machine_mode mode = GET_MODE (dst);
9022 if (GET_CODE (dst) == SUBREG)
9024 regno = SUBREG_WORD (dst);
9025 dst = SUBREG_REG (dst);
9028 if (GET_CODE (dst) != REG)
9031 regno += REGNO (dst);
9033 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9034 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9035 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9036 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9038 rtx src = SET_SRC (set);
9040 reg_mode[regno] = mode;
9041 switch (GET_CODE (src))
9045 rtx src0 = XEXP (src, 0);
9047 if (GET_CODE (src0) == REG)
9049 if (REGNO (src0) != regno
9050 || reg_offset[regno] != const0_rtx)
9052 reg_base_reg[regno] = REGNO (src0);
9053 reg_set_luid[regno] = move2add_luid;
9056 reg_offset[regno] = XEXP (src, 1);
9060 reg_set_luid[regno] = move2add_luid;
9061 reg_offset[regno] = set; /* Invalidate contents. */
9066 reg_base_reg[regno] = REGNO (SET_SRC (set));
9067 reg_offset[regno] = const0_rtx;
9068 reg_set_luid[regno] = move2add_luid;
9072 reg_base_reg[regno] = -1;
9073 reg_offset[regno] = SET_SRC (set);
9074 reg_set_luid[regno] = move2add_luid;
9080 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9082 for (i = regno; i < endregno; i++)
9084 /* Indicate that this register has been recently written to,
9085 but the exact contents are not available. */
9086 reg_set_luid[i] = move2add_luid;
9087 reg_offset[i] = dst;
9094 add_auto_inc_notes (insn, x)
9098 enum rtx_code code = GET_CODE (x);
9102 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9105 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9109 /* Scan all the operand sub-expressions. */
9110 fmt = GET_RTX_FORMAT (code);
9111 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9114 add_auto_inc_notes (insn, XEXP (x, i));
9115 else if (fmt[i] == 'E')
9116 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9117 add_auto_inc_notes (insn, XVECEXP (x, i, j));
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