1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004 Free Software Foundation, Inc.
5 This file is part of GCC.
7 GCC is free software; you can redistribute it and/or modify it under
8 the terms of the GNU General Public License as published by the Free
9 Software Foundation; either version 2, or (at your option) any later
12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
13 WARRANTY; without even the implied warranty of MERCHANTABILITY or
14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17 You should have received a copy of the GNU General Public License
18 along with GCC; see the file COPYING. If not, write to the Free
19 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "basic-block.h"
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 /* During reload_as_needed, element N contains a REG rtx for the hard reg
82 into which reg N has been reloaded (perhaps for a previous insn). */
83 static rtx *reg_last_reload_reg;
85 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
86 for an output reload that stores into reg N. */
87 static char *reg_has_output_reload;
89 /* Indicates which hard regs are reload-registers for an output reload
90 in the current insn. */
91 static HARD_REG_SET reg_is_output_reload;
93 /* Element N is the constant value to which pseudo reg N is equivalent,
94 or zero if pseudo reg N is not equivalent to a constant.
95 find_reloads looks at this in order to replace pseudo reg N
96 with the constant it stands for. */
97 rtx *reg_equiv_constant;
99 /* Element N is a memory location to which pseudo reg N is equivalent,
100 prior to any register elimination (such as frame pointer to stack
101 pointer). Depending on whether or not it is a valid address, this value
102 is transferred to either reg_equiv_address or reg_equiv_mem. */
103 rtx *reg_equiv_memory_loc;
105 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
106 collector can keep track of what is inside. */
107 varray_type reg_equiv_memory_loc_varray;
109 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
110 This is used when the address is not valid as a memory address
111 (because its displacement is too big for the machine.) */
112 rtx *reg_equiv_address;
114 /* Element N is the memory slot to which pseudo reg N is equivalent,
115 or zero if pseudo reg N is not equivalent to a memory slot. */
118 /* Widest width in which each pseudo reg is referred to (via subreg). */
119 static unsigned int *reg_max_ref_width;
121 /* Element N is the list of insns that initialized reg N from its equivalent
122 constant or memory slot. */
123 static rtx *reg_equiv_init;
125 /* Vector to remember old contents of reg_renumber before spilling. */
126 static short *reg_old_renumber;
128 /* During reload_as_needed, element N contains the last pseudo regno reloaded
129 into hard register N. If that pseudo reg occupied more than one register,
130 reg_reloaded_contents points to that pseudo for each spill register in
131 use; all of these must remain set for an inheritance to occur. */
132 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
134 /* During reload_as_needed, element N contains the insn for which
135 hard register N was last used. Its contents are significant only
136 when reg_reloaded_valid is set for this register. */
137 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
139 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
140 static HARD_REG_SET reg_reloaded_valid;
141 /* Indicate if the register was dead at the end of the reload.
142 This is only valid if reg_reloaded_contents is set and valid. */
143 static HARD_REG_SET reg_reloaded_dead;
145 /* Indicate whether the register's current value is one that is not
146 safe to retain across a call, even for registers that are normally
148 static HARD_REG_SET reg_reloaded_call_part_clobbered;
150 /* Number of spill-regs so far; number of valid elements of spill_regs. */
153 /* In parallel with spill_regs, contains REG rtx's for those regs.
154 Holds the last rtx used for any given reg, or 0 if it has never
155 been used for spilling yet. This rtx is reused, provided it has
157 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
159 /* In parallel with spill_regs, contains nonzero for a spill reg
160 that was stored after the last time it was used.
161 The precise value is the insn generated to do the store. */
162 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
164 /* This is the register that was stored with spill_reg_store. This is a
165 copy of reload_out / reload_out_reg when the value was stored; if
166 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
167 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
169 /* This table is the inverse mapping of spill_regs:
170 indexed by hard reg number,
171 it contains the position of that reg in spill_regs,
172 or -1 for something that is not in spill_regs.
174 ?!? This is no longer accurate. */
175 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
177 /* This reg set indicates registers that can't be used as spill registers for
178 the currently processed insn. These are the hard registers which are live
179 during the insn, but not allocated to pseudos, as well as fixed
181 static HARD_REG_SET bad_spill_regs;
183 /* These are the hard registers that can't be used as spill register for any
184 insn. This includes registers used for user variables and registers that
185 we can't eliminate. A register that appears in this set also can't be used
186 to retry register allocation. */
187 static HARD_REG_SET bad_spill_regs_global;
189 /* Describes order of use of registers for reloading
190 of spilled pseudo-registers. `n_spills' is the number of
191 elements that are actually valid; new ones are added at the end.
193 Both spill_regs and spill_reg_order are used on two occasions:
194 once during find_reload_regs, where they keep track of the spill registers
195 for a single insn, but also during reload_as_needed where they show all
196 the registers ever used by reload. For the latter case, the information
197 is calculated during finish_spills. */
198 static short spill_regs[FIRST_PSEUDO_REGISTER];
200 /* This vector of reg sets indicates, for each pseudo, which hard registers
201 may not be used for retrying global allocation because the register was
202 formerly spilled from one of them. If we allowed reallocating a pseudo to
203 a register that it was already allocated to, reload might not
205 static HARD_REG_SET *pseudo_previous_regs;
207 /* This vector of reg sets indicates, for each pseudo, which hard
208 registers may not be used for retrying global allocation because they
209 are used as spill registers during one of the insns in which the
211 static HARD_REG_SET *pseudo_forbidden_regs;
213 /* All hard regs that have been used as spill registers for any insn are
214 marked in this set. */
215 static HARD_REG_SET used_spill_regs;
217 /* Index of last register assigned as a spill register. We allocate in
218 a round-robin fashion. */
219 static int last_spill_reg;
221 /* Nonzero if indirect addressing is supported on the machine; this means
222 that spilling (REG n) does not require reloading it into a register in
223 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
224 value indicates the level of indirect addressing supported, e.g., two
225 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
227 static char spill_indirect_levels;
229 /* Nonzero if indirect addressing is supported when the innermost MEM is
230 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
231 which these are valid is the same as spill_indirect_levels, above. */
232 char indirect_symref_ok;
234 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
235 char double_reg_address_ok;
237 /* Record the stack slot for each spilled hard register. */
238 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
240 /* Width allocated so far for that stack slot. */
241 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
243 /* Record which pseudos needed to be spilled. */
244 static regset_head spilled_pseudos;
246 /* Used for communication between order_regs_for_reload and count_pseudo.
247 Used to avoid counting one pseudo twice. */
248 static regset_head pseudos_counted;
250 /* First uid used by insns created by reload in this function.
251 Used in find_equiv_reg. */
252 int reload_first_uid;
254 /* Flag set by local-alloc or global-alloc if anything is live in
255 a call-clobbered reg across calls. */
256 int caller_save_needed;
258 /* Set to 1 while reload_as_needed is operating.
259 Required by some machines to handle any generated moves differently. */
260 int reload_in_progress = 0;
262 /* These arrays record the insn_code of insns that may be needed to
263 perform input and output reloads of special objects. They provide a
264 place to pass a scratch register. */
265 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
266 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
268 /* This obstack is used for allocation of rtl during register elimination.
269 The allocated storage can be freed once find_reloads has processed the
271 struct obstack reload_obstack;
273 /* Points to the beginning of the reload_obstack. All insn_chain structures
274 are allocated first. */
275 char *reload_startobj;
277 /* The point after all insn_chain structures. Used to quickly deallocate
278 memory allocated in copy_reloads during calculate_needs_all_insns. */
279 char *reload_firstobj;
281 /* This points before all local rtl generated by register elimination.
282 Used to quickly free all memory after processing one insn. */
283 static char *reload_insn_firstobj;
285 /* List of insn_chain instructions, one for every insn that reload needs to
287 struct insn_chain *reload_insn_chain;
289 /* List of all insns needing reloads. */
290 static struct insn_chain *insns_need_reload;
292 /* This structure is used to record information about register eliminations.
293 Each array entry describes one possible way of eliminating a register
294 in favor of another. If there is more than one way of eliminating a
295 particular register, the most preferred should be specified first. */
299 int from; /* Register number to be eliminated. */
300 int to; /* Register number used as replacement. */
301 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
302 int can_eliminate; /* Nonzero if this elimination can be done. */
303 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
304 insns made by reload. */
305 HOST_WIDE_INT offset; /* Current offset between the two regs. */
306 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
307 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
308 rtx from_rtx; /* REG rtx for the register to be eliminated.
309 We cannot simply compare the number since
310 we might then spuriously replace a hard
311 register corresponding to a pseudo
312 assigned to the reg to be eliminated. */
313 rtx to_rtx; /* REG rtx for the replacement. */
316 static struct elim_table *reg_eliminate = 0;
318 /* This is an intermediate structure to initialize the table. It has
319 exactly the members provided by ELIMINABLE_REGS. */
320 static const struct elim_table_1
324 } reg_eliminate_1[] =
326 /* If a set of eliminable registers was specified, define the table from it.
327 Otherwise, default to the normal case of the frame pointer being
328 replaced by the stack pointer. */
330 #ifdef ELIMINABLE_REGS
333 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
336 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
338 /* Record the number of pending eliminations that have an offset not equal
339 to their initial offset. If nonzero, we use a new copy of each
340 replacement result in any insns encountered. */
341 int num_not_at_initial_offset;
343 /* Count the number of registers that we may be able to eliminate. */
344 static int num_eliminable;
345 /* And the number of registers that are equivalent to a constant that
346 can be eliminated to frame_pointer / arg_pointer + constant. */
347 static int num_eliminable_invariants;
349 /* For each label, we record the offset of each elimination. If we reach
350 a label by more than one path and an offset differs, we cannot do the
351 elimination. This information is indexed by the difference of the
352 number of the label and the first label number. We can't offset the
353 pointer itself as this can cause problems on machines with segmented
354 memory. The first table is an array of flags that records whether we
355 have yet encountered a label and the second table is an array of arrays,
356 one entry in the latter array for each elimination. */
358 static int first_label_num;
359 static char *offsets_known_at;
360 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
362 /* Number of labels in the current function. */
364 static int num_labels;
366 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
367 static void maybe_fix_stack_asms (void);
368 static void copy_reloads (struct insn_chain *);
369 static void calculate_needs_all_insns (int);
370 static int find_reg (struct insn_chain *, int);
371 static void find_reload_regs (struct insn_chain *);
372 static void select_reload_regs (void);
373 static void delete_caller_save_insns (void);
375 static void spill_failure (rtx, enum reg_class);
376 static void count_spilled_pseudo (int, int, int);
377 static void delete_dead_insn (rtx);
378 static void alter_reg (int, int);
379 static void set_label_offsets (rtx, rtx, int);
380 static void check_eliminable_occurrences (rtx);
381 static void elimination_effects (rtx, enum machine_mode);
382 static int eliminate_regs_in_insn (rtx, int);
383 static void update_eliminable_offsets (void);
384 static void mark_not_eliminable (rtx, rtx, void *);
385 static void set_initial_elim_offsets (void);
386 static void verify_initial_elim_offsets (void);
387 static void set_initial_label_offsets (void);
388 static void set_offsets_for_label (rtx);
389 static void init_elim_table (void);
390 static void update_eliminables (HARD_REG_SET *);
391 static void spill_hard_reg (unsigned int, int);
392 static int finish_spills (int);
393 static void ior_hard_reg_set (HARD_REG_SET *, HARD_REG_SET *);
394 static void scan_paradoxical_subregs (rtx);
395 static void count_pseudo (int);
396 static void order_regs_for_reload (struct insn_chain *);
397 static void reload_as_needed (int);
398 static void forget_old_reloads_1 (rtx, rtx, void *);
399 static int reload_reg_class_lower (const void *, const void *);
400 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
402 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
404 static int reload_reg_free_p (unsigned int, int, enum reload_type);
405 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
407 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
409 static int function_invariant_p (rtx);
410 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
411 static int allocate_reload_reg (struct insn_chain *, int, int);
412 static int conflicts_with_override (rtx);
413 static void failed_reload (rtx, int);
414 static int set_reload_reg (int, int);
415 static void choose_reload_regs_init (struct insn_chain *, rtx *);
416 static void choose_reload_regs (struct insn_chain *);
417 static void merge_assigned_reloads (rtx);
418 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
420 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
422 static void do_input_reload (struct insn_chain *, struct reload *, int);
423 static void do_output_reload (struct insn_chain *, struct reload *, int);
424 static bool inherit_piecemeal_p (int, int);
425 static void emit_reload_insns (struct insn_chain *);
426 static void delete_output_reload (rtx, int, int);
427 static void delete_address_reloads (rtx, rtx);
428 static void delete_address_reloads_1 (rtx, rtx, rtx);
429 static rtx inc_for_reload (rtx, rtx, rtx, int);
431 static void add_auto_inc_notes (rtx, rtx);
433 static void copy_eh_notes (rtx, rtx);
435 /* Initialize the reload pass once per compilation. */
442 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
443 Set spill_indirect_levels to the number of levels such addressing is
444 permitted, zero if it is not permitted at all. */
447 = gen_rtx_MEM (Pmode,
450 LAST_VIRTUAL_REGISTER + 1),
452 spill_indirect_levels = 0;
454 while (memory_address_p (QImode, tem))
456 spill_indirect_levels++;
457 tem = gen_rtx_MEM (Pmode, tem);
460 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
462 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
463 indirect_symref_ok = memory_address_p (QImode, tem);
465 /* See if reg+reg is a valid (and offsettable) address. */
467 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
469 tem = gen_rtx_PLUS (Pmode,
470 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
471 gen_rtx_REG (Pmode, i));
473 /* This way, we make sure that reg+reg is an offsettable address. */
474 tem = plus_constant (tem, 4);
476 if (memory_address_p (QImode, tem))
478 double_reg_address_ok = 1;
483 /* Initialize obstack for our rtl allocation. */
484 gcc_obstack_init (&reload_obstack);
485 reload_startobj = obstack_alloc (&reload_obstack, 0);
487 INIT_REG_SET (&spilled_pseudos);
488 INIT_REG_SET (&pseudos_counted);
489 VARRAY_RTX_INIT (reg_equiv_memory_loc_varray, 0, "reg_equiv_memory_loc");
492 /* List of insn chains that are currently unused. */
493 static struct insn_chain *unused_insn_chains = 0;
495 /* Allocate an empty insn_chain structure. */
497 new_insn_chain (void)
499 struct insn_chain *c;
501 if (unused_insn_chains == 0)
503 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
504 INIT_REG_SET (&c->live_throughout);
505 INIT_REG_SET (&c->dead_or_set);
509 c = unused_insn_chains;
510 unused_insn_chains = c->next;
512 c->is_caller_save_insn = 0;
513 c->need_operand_change = 0;
519 /* Small utility function to set all regs in hard reg set TO which are
520 allocated to pseudos in regset FROM. */
523 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
527 EXECUTE_IF_SET_IN_REG_SET
528 (from, FIRST_PSEUDO_REGISTER, regno,
530 int r = reg_renumber[regno];
535 /* reload_combine uses the information from
536 BASIC_BLOCK->global_live_at_start, which might still
537 contain registers that have not actually been allocated
538 since they have an equivalence. */
539 gcc_assert (reload_completed);
543 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
545 SET_HARD_REG_BIT (*to, r + nregs);
550 /* Replace all pseudos found in LOC with their corresponding
554 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
567 unsigned int regno = REGNO (x);
569 if (regno < FIRST_PSEUDO_REGISTER)
572 x = eliminate_regs (x, mem_mode, usage);
576 replace_pseudos_in (loc, mem_mode, usage);
580 if (reg_equiv_constant[regno])
581 *loc = reg_equiv_constant[regno];
582 else if (reg_equiv_mem[regno])
583 *loc = reg_equiv_mem[regno];
584 else if (reg_equiv_address[regno])
585 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
588 gcc_assert (!REG_P (regno_reg_rtx[regno])
589 || REGNO (regno_reg_rtx[regno]) != regno);
590 *loc = regno_reg_rtx[regno];
595 else if (code == MEM)
597 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
601 /* Process each of our operands recursively. */
602 fmt = GET_RTX_FORMAT (code);
603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
605 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
606 else if (*fmt == 'E')
607 for (j = 0; j < XVECLEN (x, i); j++)
608 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
612 /* Global variables used by reload and its subroutines. */
614 /* Set during calculate_needs if an insn needs register elimination. */
615 static int something_needs_elimination;
616 /* Set during calculate_needs if an insn needs an operand changed. */
617 int something_needs_operands_changed;
619 /* Nonzero means we couldn't get enough spill regs. */
622 /* Main entry point for the reload pass.
624 FIRST is the first insn of the function being compiled.
626 GLOBAL nonzero means we were called from global_alloc
627 and should attempt to reallocate any pseudoregs that we
628 displace from hard regs we will use for reloads.
629 If GLOBAL is zero, we do not have enough information to do that,
630 so any pseudo reg that is spilled must go to the stack.
632 Return value is nonzero if reload failed
633 and we must not do any more for this function. */
636 reload (rtx first, int global)
640 struct elim_table *ep;
643 /* Make sure even insns with volatile mem refs are recognizable. */
648 reload_firstobj = obstack_alloc (&reload_obstack, 0);
650 /* Make sure that the last insn in the chain
651 is not something that needs reloading. */
652 emit_note (NOTE_INSN_DELETED);
654 /* Enable find_equiv_reg to distinguish insns made by reload. */
655 reload_first_uid = get_max_uid ();
657 #ifdef SECONDARY_MEMORY_NEEDED
658 /* Initialize the secondary memory table. */
659 clear_secondary_mem ();
662 /* We don't have a stack slot for any spill reg yet. */
663 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
664 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
666 /* Initialize the save area information for caller-save, in case some
670 /* Compute which hard registers are now in use
671 as homes for pseudo registers.
672 This is done here rather than (eg) in global_alloc
673 because this point is reached even if not optimizing. */
674 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
677 /* A function that receives a nonlocal goto must save all call-saved
679 if (current_function_has_nonlocal_label)
680 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
681 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
682 regs_ever_live[i] = 1;
684 #ifdef NON_SAVING_SETJMP
685 /* A function that calls setjmp should save and restore all the
686 call-saved registers on a system where longjmp clobbers them. */
687 if (NON_SAVING_SETJMP && current_function_calls_setjmp)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i])
691 regs_ever_live[i] = 1;
695 /* Find all the pseudo registers that didn't get hard regs
696 but do have known equivalent constants or memory slots.
697 These include parameters (known equivalent to parameter slots)
698 and cse'd or loop-moved constant memory addresses.
700 Record constant equivalents in reg_equiv_constant
701 so they will be substituted by find_reloads.
702 Record memory equivalents in reg_mem_equiv so they can
703 be substituted eventually by altering the REG-rtx's. */
705 reg_equiv_constant = xcalloc (max_regno, sizeof (rtx));
706 reg_equiv_mem = xcalloc (max_regno, sizeof (rtx));
707 reg_equiv_init = xcalloc (max_regno, sizeof (rtx));
708 reg_equiv_address = xcalloc (max_regno, sizeof (rtx));
709 reg_max_ref_width = xcalloc (max_regno, sizeof (int));
710 reg_old_renumber = xcalloc (max_regno, sizeof (short));
711 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
712 pseudo_forbidden_regs = xmalloc (max_regno * sizeof (HARD_REG_SET));
713 pseudo_previous_regs = xcalloc (max_regno, sizeof (HARD_REG_SET));
715 CLEAR_HARD_REG_SET (bad_spill_regs_global);
717 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
718 to. Also find all paradoxical subregs and find largest such for
721 num_eliminable_invariants = 0;
722 for (insn = first; insn; insn = NEXT_INSN (insn))
724 rtx set = single_set (insn);
726 /* We may introduce USEs that we want to remove at the end, so
727 we'll mark them with QImode. Make sure there are no
728 previously-marked insns left by say regmove. */
729 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
730 && GET_MODE (insn) != VOIDmode)
731 PUT_MODE (insn, VOIDmode);
733 if (set != 0 && REG_P (SET_DEST (set)))
735 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
737 && (! function_invariant_p (XEXP (note, 0))
739 /* A function invariant is often CONSTANT_P but may
740 include a register. We promise to only pass
741 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
742 || (CONSTANT_P (XEXP (note, 0))
743 && LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))))
745 rtx x = XEXP (note, 0);
746 i = REGNO (SET_DEST (set));
747 if (i > LAST_VIRTUAL_REGISTER)
749 /* It can happen that a REG_EQUIV note contains a MEM
750 that is not a legitimate memory operand. As later
751 stages of reload assume that all addresses found
752 in the reg_equiv_* arrays were originally legitimate,
753 we ignore such REG_EQUIV notes. */
754 if (memory_operand (x, VOIDmode))
756 /* Always unshare the equivalence, so we can
757 substitute into this insn without touching the
759 reg_equiv_memory_loc[i] = copy_rtx (x);
761 else if (function_invariant_p (x))
763 if (GET_CODE (x) == PLUS)
765 /* This is PLUS of frame pointer and a constant,
766 and might be shared. Unshare it. */
767 reg_equiv_constant[i] = copy_rtx (x);
768 num_eliminable_invariants++;
770 else if (x == frame_pointer_rtx
771 || x == arg_pointer_rtx)
773 reg_equiv_constant[i] = x;
774 num_eliminable_invariants++;
776 else if (LEGITIMATE_CONSTANT_P (x))
777 reg_equiv_constant[i] = x;
780 reg_equiv_memory_loc[i]
781 = force_const_mem (GET_MODE (SET_DEST (set)), x);
782 if (!reg_equiv_memory_loc[i])
789 /* If this register is being made equivalent to a MEM
790 and the MEM is not SET_SRC, the equivalencing insn
791 is one with the MEM as a SET_DEST and it occurs later.
792 So don't mark this insn now. */
794 || rtx_equal_p (SET_SRC (set), x))
796 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
801 /* If this insn is setting a MEM from a register equivalent to it,
802 this is the equivalencing insn. */
803 else if (set && MEM_P (SET_DEST (set))
804 && REG_P (SET_SRC (set))
805 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
806 && rtx_equal_p (SET_DEST (set),
807 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
808 reg_equiv_init[REGNO (SET_SRC (set))]
809 = gen_rtx_INSN_LIST (VOIDmode, insn,
810 reg_equiv_init[REGNO (SET_SRC (set))]);
813 scan_paradoxical_subregs (PATTERN (insn));
818 first_label_num = get_first_label_num ();
819 num_labels = max_label_num () - first_label_num;
821 /* Allocate the tables used to store offset information at labels. */
822 /* We used to use alloca here, but the size of what it would try to
823 allocate would occasionally cause it to exceed the stack limit and
824 cause a core dump. */
825 offsets_known_at = xmalloc (num_labels);
826 offsets_at = xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
828 /* Alter each pseudo-reg rtx to contain its hard reg number.
829 Assign stack slots to the pseudos that lack hard regs or equivalents.
830 Do not touch virtual registers. */
832 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
835 /* If we have some registers we think can be eliminated, scan all insns to
836 see if there is an insn that sets one of these registers to something
837 other than itself plus a constant. If so, the register cannot be
838 eliminated. Doing this scan here eliminates an extra pass through the
839 main reload loop in the most common case where register elimination
841 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
843 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
845 maybe_fix_stack_asms ();
847 insns_need_reload = 0;
848 something_needs_elimination = 0;
850 /* Initialize to -1, which means take the first spill register. */
853 /* Spill any hard regs that we know we can't eliminate. */
854 CLEAR_HARD_REG_SET (used_spill_regs);
855 /* There can be multiple ways to eliminate a register;
856 they should be listed adjacently.
857 Elimination for any register fails only if all possible ways fail. */
858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
861 int can_eliminate = 0;
864 can_eliminate |= ep->can_eliminate;
867 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
869 spill_hard_reg (from, 1);
872 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
873 if (frame_pointer_needed)
874 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
876 finish_spills (global);
878 /* From now on, we may need to generate moves differently. We may also
879 allow modifications of insns which cause them to not be recognized.
880 Any such modifications will be cleaned up during reload itself. */
881 reload_in_progress = 1;
883 /* This loop scans the entire function each go-round
884 and repeats until one repetition spills no additional hard regs. */
887 int something_changed;
890 HOST_WIDE_INT starting_frame_size;
892 /* Round size of stack frame to stack_alignment_needed. This must be done
893 here because the stack size may be a part of the offset computation
894 for register elimination, and there might have been new stack slots
895 created in the last iteration of this loop. */
896 if (cfun->stack_alignment_needed)
897 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
899 starting_frame_size = get_frame_size ();
901 set_initial_elim_offsets ();
902 set_initial_label_offsets ();
904 /* For each pseudo register that has an equivalent location defined,
905 try to eliminate any eliminable registers (such as the frame pointer)
906 assuming initial offsets for the replacement register, which
909 If the resulting location is directly addressable, substitute
910 the MEM we just got directly for the old REG.
912 If it is not addressable but is a constant or the sum of a hard reg
913 and constant, it is probably not addressable because the constant is
914 out of range, in that case record the address; we will generate
915 hairy code to compute the address in a register each time it is
916 needed. Similarly if it is a hard register, but one that is not
917 valid as an address register.
919 If the location is not addressable, but does not have one of the
920 above forms, assign a stack slot. We have to do this to avoid the
921 potential of producing lots of reloads if, e.g., a location involves
922 a pseudo that didn't get a hard register and has an equivalent memory
923 location that also involves a pseudo that didn't get a hard register.
925 Perhaps at some point we will improve reload_when_needed handling
926 so this problem goes away. But that's very hairy. */
928 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
929 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
931 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
933 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
935 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
936 else if (CONSTANT_P (XEXP (x, 0))
937 || (REG_P (XEXP (x, 0))
938 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
939 || (GET_CODE (XEXP (x, 0)) == PLUS
940 && REG_P (XEXP (XEXP (x, 0), 0))
941 && (REGNO (XEXP (XEXP (x, 0), 0))
942 < FIRST_PSEUDO_REGISTER)
943 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
944 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
947 /* Make a new stack slot. Then indicate that something
948 changed so we go back and recompute offsets for
949 eliminable registers because the allocation of memory
950 below might change some offset. reg_equiv_{mem,address}
951 will be set up for this pseudo on the next pass around
953 reg_equiv_memory_loc[i] = 0;
954 reg_equiv_init[i] = 0;
959 if (caller_save_needed)
962 /* If we allocated another stack slot, redo elimination bookkeeping. */
963 if (starting_frame_size != get_frame_size ())
966 if (caller_save_needed)
968 save_call_clobbered_regs ();
969 /* That might have allocated new insn_chain structures. */
970 reload_firstobj = obstack_alloc (&reload_obstack, 0);
973 calculate_needs_all_insns (global);
975 CLEAR_REG_SET (&spilled_pseudos);
978 something_changed = 0;
980 /* If we allocated any new memory locations, make another pass
981 since it might have changed elimination offsets. */
982 if (starting_frame_size != get_frame_size ())
983 something_changed = 1;
986 HARD_REG_SET to_spill;
987 CLEAR_HARD_REG_SET (to_spill);
988 update_eliminables (&to_spill);
989 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
990 if (TEST_HARD_REG_BIT (to_spill, i))
992 spill_hard_reg (i, 1);
995 /* Regardless of the state of spills, if we previously had
996 a register that we thought we could eliminate, but now can
997 not eliminate, we must run another pass.
999 Consider pseudos which have an entry in reg_equiv_* which
1000 reference an eliminable register. We must make another pass
1001 to update reg_equiv_* so that we do not substitute in the
1002 old value from when we thought the elimination could be
1004 something_changed = 1;
1008 select_reload_regs ();
1012 if (insns_need_reload != 0 || did_spill)
1013 something_changed |= finish_spills (global);
1015 if (! something_changed)
1018 if (caller_save_needed)
1019 delete_caller_save_insns ();
1021 obstack_free (&reload_obstack, reload_firstobj);
1024 /* If global-alloc was run, notify it of any register eliminations we have
1027 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1028 if (ep->can_eliminate)
1029 mark_elimination (ep->from, ep->to);
1031 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1032 If that insn didn't set the register (i.e., it copied the register to
1033 memory), just delete that insn instead of the equivalencing insn plus
1034 anything now dead. If we call delete_dead_insn on that insn, we may
1035 delete the insn that actually sets the register if the register dies
1036 there and that is incorrect. */
1038 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1040 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1043 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1045 rtx equiv_insn = XEXP (list, 0);
1047 /* If we already deleted the insn or if it may trap, we can't
1048 delete it. The latter case shouldn't happen, but can
1049 if an insn has a variable address, gets a REG_EH_REGION
1050 note added to it, and then gets converted into an load
1051 from a constant address. */
1052 if (NOTE_P (equiv_insn)
1053 || can_throw_internal (equiv_insn))
1055 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1056 delete_dead_insn (equiv_insn);
1058 SET_INSN_DELETED (equiv_insn);
1063 /* Use the reload registers where necessary
1064 by generating move instructions to move the must-be-register
1065 values into or out of the reload registers. */
1067 if (insns_need_reload != 0 || something_needs_elimination
1068 || something_needs_operands_changed)
1070 HOST_WIDE_INT old_frame_size = get_frame_size ();
1072 reload_as_needed (global);
1074 gcc_assert (old_frame_size == get_frame_size ());
1077 verify_initial_elim_offsets ();
1080 /* If we were able to eliminate the frame pointer, show that it is no
1081 longer live at the start of any basic block. If it ls live by
1082 virtue of being in a pseudo, that pseudo will be marked live
1083 and hence the frame pointer will be known to be live via that
1086 if (! frame_pointer_needed)
1088 CLEAR_REGNO_REG_SET (bb->global_live_at_start,
1089 HARD_FRAME_POINTER_REGNUM);
1091 /* Come here (with failure set nonzero) if we can't get enough spill regs
1092 and we decide not to abort about it. */
1095 CLEAR_REG_SET (&spilled_pseudos);
1096 reload_in_progress = 0;
1098 /* Now eliminate all pseudo regs by modifying them into
1099 their equivalent memory references.
1100 The REG-rtx's for the pseudos are modified in place,
1101 so all insns that used to refer to them now refer to memory.
1103 For a reg that has a reg_equiv_address, all those insns
1104 were changed by reloading so that no insns refer to it any longer;
1105 but the DECL_RTL of a variable decl may refer to it,
1106 and if so this causes the debugging info to mention the variable. */
1108 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1112 if (reg_equiv_mem[i])
1113 addr = XEXP (reg_equiv_mem[i], 0);
1115 if (reg_equiv_address[i])
1116 addr = reg_equiv_address[i];
1120 if (reg_renumber[i] < 0)
1122 rtx reg = regno_reg_rtx[i];
1124 REG_USERVAR_P (reg) = 0;
1125 PUT_CODE (reg, MEM);
1126 XEXP (reg, 0) = addr;
1127 if (reg_equiv_memory_loc[i])
1128 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1131 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1132 MEM_ATTRS (reg) = 0;
1135 else if (reg_equiv_mem[i])
1136 XEXP (reg_equiv_mem[i], 0) = addr;
1140 /* We must set reload_completed now since the cleanup_subreg_operands call
1141 below will re-recognize each insn and reload may have generated insns
1142 which are only valid during and after reload. */
1143 reload_completed = 1;
1145 /* Make a pass over all the insns and delete all USEs which we inserted
1146 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1147 notes. Delete all CLOBBER insns, except those that refer to the return
1148 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1149 from misarranging variable-array code, and simplify (subreg (reg))
1150 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1151 are no longer useful or accurate. Strip and regenerate REG_INC notes
1152 that may have been moved around. */
1154 for (insn = first; insn; insn = NEXT_INSN (insn))
1160 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1161 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1163 if ((GET_CODE (PATTERN (insn)) == USE
1164 /* We mark with QImode USEs introduced by reload itself. */
1165 && (GET_MODE (insn) == QImode
1166 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1167 || (GET_CODE (PATTERN (insn)) == CLOBBER
1168 && (!MEM_P (XEXP (PATTERN (insn), 0))
1169 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1170 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1171 && XEXP (XEXP (PATTERN (insn), 0), 0)
1172 != stack_pointer_rtx))
1173 && (!REG_P (XEXP (PATTERN (insn), 0))
1174 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1180 /* Some CLOBBERs may survive until here and still reference unassigned
1181 pseudos with const equivalent, which may in turn cause ICE in later
1182 passes if the reference remains in place. */
1183 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1184 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1185 VOIDmode, PATTERN (insn));
1187 pnote = ®_NOTES (insn);
1190 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1191 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1192 || REG_NOTE_KIND (*pnote) == REG_INC
1193 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1194 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1195 *pnote = XEXP (*pnote, 1);
1197 pnote = &XEXP (*pnote, 1);
1201 add_auto_inc_notes (insn, PATTERN (insn));
1204 /* And simplify (subreg (reg)) if it appears as an operand. */
1205 cleanup_subreg_operands (insn);
1208 /* If we are doing stack checking, give a warning if this function's
1209 frame size is larger than we expect. */
1210 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1212 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1213 static int verbose_warned = 0;
1215 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1216 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1217 size += UNITS_PER_WORD;
1219 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1221 warning ("frame size too large for reliable stack checking");
1222 if (! verbose_warned)
1224 warning ("try reducing the number of local variables");
1230 /* Indicate that we no longer have known memory locations or constants. */
1231 if (reg_equiv_constant)
1232 free (reg_equiv_constant);
1233 reg_equiv_constant = 0;
1234 VARRAY_GROW (reg_equiv_memory_loc_varray, 0);
1235 reg_equiv_memory_loc = 0;
1237 if (offsets_known_at)
1238 free (offsets_known_at);
1242 free (reg_equiv_mem);
1243 free (reg_equiv_init);
1244 free (reg_equiv_address);
1245 free (reg_max_ref_width);
1246 free (reg_old_renumber);
1247 free (pseudo_previous_regs);
1248 free (pseudo_forbidden_regs);
1250 CLEAR_HARD_REG_SET (used_spill_regs);
1251 for (i = 0; i < n_spills; i++)
1252 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1254 /* Free all the insn_chain structures at once. */
1255 obstack_free (&reload_obstack, reload_startobj);
1256 unused_insn_chains = 0;
1257 fixup_abnormal_edges ();
1259 /* Replacing pseudos with their memory equivalents might have
1260 created shared rtx. Subsequent passes would get confused
1261 by this, so unshare everything here. */
1262 unshare_all_rtl_again (first);
1264 #ifdef STACK_BOUNDARY
1265 /* init_emit has set the alignment of the hard frame pointer
1266 to STACK_BOUNDARY. It is very likely no longer valid if
1267 the hard frame pointer was used for register allocation. */
1268 if (!frame_pointer_needed)
1269 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1275 /* Yet another special case. Unfortunately, reg-stack forces people to
1276 write incorrect clobbers in asm statements. These clobbers must not
1277 cause the register to appear in bad_spill_regs, otherwise we'll call
1278 fatal_insn later. We clear the corresponding regnos in the live
1279 register sets to avoid this.
1280 The whole thing is rather sick, I'm afraid. */
1283 maybe_fix_stack_asms (void)
1286 const char *constraints[MAX_RECOG_OPERANDS];
1287 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1288 struct insn_chain *chain;
1290 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1293 HARD_REG_SET clobbered, allowed;
1296 if (! INSN_P (chain->insn)
1297 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1299 pat = PATTERN (chain->insn);
1300 if (GET_CODE (pat) != PARALLEL)
1303 CLEAR_HARD_REG_SET (clobbered);
1304 CLEAR_HARD_REG_SET (allowed);
1306 /* First, make a mask of all stack regs that are clobbered. */
1307 for (i = 0; i < XVECLEN (pat, 0); i++)
1309 rtx t = XVECEXP (pat, 0, i);
1310 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1311 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1314 /* Get the operand values and constraints out of the insn. */
1315 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1316 constraints, operand_mode);
1318 /* For every operand, see what registers are allowed. */
1319 for (i = 0; i < noperands; i++)
1321 const char *p = constraints[i];
1322 /* For every alternative, we compute the class of registers allowed
1323 for reloading in CLS, and merge its contents into the reg set
1325 int cls = (int) NO_REGS;
1331 if (c == '\0' || c == ',' || c == '#')
1333 /* End of one alternative - mark the regs in the current
1334 class, and reset the class. */
1335 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1341 } while (c != '\0' && c != ',');
1349 case '=': case '+': case '*': case '%': case '?': case '!':
1350 case '0': case '1': case '2': case '3': case '4': case 'm':
1351 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1352 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1353 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1358 cls = (int) reg_class_subunion[cls]
1359 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1364 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1368 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1369 cls = (int) reg_class_subunion[cls]
1370 [(int) MODE_BASE_REG_CLASS (VOIDmode)];
1372 cls = (int) reg_class_subunion[cls]
1373 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1375 p += CONSTRAINT_LEN (c, p);
1378 /* Those of the registers which are clobbered, but allowed by the
1379 constraints, must be usable as reload registers. So clear them
1380 out of the life information. */
1381 AND_HARD_REG_SET (allowed, clobbered);
1382 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1383 if (TEST_HARD_REG_BIT (allowed, i))
1385 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1386 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1393 /* Copy the global variables n_reloads and rld into the corresponding elts
1396 copy_reloads (struct insn_chain *chain)
1398 chain->n_reloads = n_reloads;
1399 chain->rld = obstack_alloc (&reload_obstack,
1400 n_reloads * sizeof (struct reload));
1401 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1402 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1405 /* Walk the chain of insns, and determine for each whether it needs reloads
1406 and/or eliminations. Build the corresponding insns_need_reload list, and
1407 set something_needs_elimination as appropriate. */
1409 calculate_needs_all_insns (int global)
1411 struct insn_chain **pprev_reload = &insns_need_reload;
1412 struct insn_chain *chain, *next = 0;
1414 something_needs_elimination = 0;
1416 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1417 for (chain = reload_insn_chain; chain != 0; chain = next)
1419 rtx insn = chain->insn;
1423 /* Clear out the shortcuts. */
1424 chain->n_reloads = 0;
1425 chain->need_elim = 0;
1426 chain->need_reload = 0;
1427 chain->need_operand_change = 0;
1429 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1430 include REG_LABEL), we need to see what effects this has on the
1431 known offsets at labels. */
1433 if (LABEL_P (insn) || JUMP_P (insn)
1434 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1435 set_label_offsets (insn, insn, 0);
1439 rtx old_body = PATTERN (insn);
1440 int old_code = INSN_CODE (insn);
1441 rtx old_notes = REG_NOTES (insn);
1442 int did_elimination = 0;
1443 int operands_changed = 0;
1444 rtx set = single_set (insn);
1446 /* Skip insns that only set an equivalence. */
1447 if (set && REG_P (SET_DEST (set))
1448 && reg_renumber[REGNO (SET_DEST (set))] < 0
1449 && reg_equiv_constant[REGNO (SET_DEST (set))])
1452 /* If needed, eliminate any eliminable registers. */
1453 if (num_eliminable || num_eliminable_invariants)
1454 did_elimination = eliminate_regs_in_insn (insn, 0);
1456 /* Analyze the instruction. */
1457 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1458 global, spill_reg_order);
1460 /* If a no-op set needs more than one reload, this is likely
1461 to be something that needs input address reloads. We
1462 can't get rid of this cleanly later, and it is of no use
1463 anyway, so discard it now.
1464 We only do this when expensive_optimizations is enabled,
1465 since this complements reload inheritance / output
1466 reload deletion, and it can make debugging harder. */
1467 if (flag_expensive_optimizations && n_reloads > 1)
1469 rtx set = single_set (insn);
1471 && SET_SRC (set) == SET_DEST (set)
1472 && REG_P (SET_SRC (set))
1473 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1476 /* Delete it from the reload chain. */
1478 chain->prev->next = next;
1480 reload_insn_chain = next;
1482 next->prev = chain->prev;
1483 chain->next = unused_insn_chains;
1484 unused_insn_chains = chain;
1489 update_eliminable_offsets ();
1491 /* Remember for later shortcuts which insns had any reloads or
1492 register eliminations. */
1493 chain->need_elim = did_elimination;
1494 chain->need_reload = n_reloads > 0;
1495 chain->need_operand_change = operands_changed;
1497 /* Discard any register replacements done. */
1498 if (did_elimination)
1500 obstack_free (&reload_obstack, reload_insn_firstobj);
1501 PATTERN (insn) = old_body;
1502 INSN_CODE (insn) = old_code;
1503 REG_NOTES (insn) = old_notes;
1504 something_needs_elimination = 1;
1507 something_needs_operands_changed |= operands_changed;
1511 copy_reloads (chain);
1512 *pprev_reload = chain;
1513 pprev_reload = &chain->next_need_reload;
1520 /* Comparison function for qsort to decide which of two reloads
1521 should be handled first. *P1 and *P2 are the reload numbers. */
1524 reload_reg_class_lower (const void *r1p, const void *r2p)
1526 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1529 /* Consider required reloads before optional ones. */
1530 t = rld[r1].optional - rld[r2].optional;
1534 /* Count all solitary classes before non-solitary ones. */
1535 t = ((reg_class_size[(int) rld[r2].class] == 1)
1536 - (reg_class_size[(int) rld[r1].class] == 1));
1540 /* Aside from solitaires, consider all multi-reg groups first. */
1541 t = rld[r2].nregs - rld[r1].nregs;
1545 /* Consider reloads in order of increasing reg-class number. */
1546 t = (int) rld[r1].class - (int) rld[r2].class;
1550 /* If reloads are equally urgent, sort by reload number,
1551 so that the results of qsort leave nothing to chance. */
1555 /* The cost of spilling each hard reg. */
1556 static int spill_cost[FIRST_PSEUDO_REGISTER];
1558 /* When spilling multiple hard registers, we use SPILL_COST for the first
1559 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1560 only the first hard reg for a multi-reg pseudo. */
1561 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1563 /* Update the spill cost arrays, considering that pseudo REG is live. */
1566 count_pseudo (int reg)
1568 int freq = REG_FREQ (reg);
1569 int r = reg_renumber[reg];
1572 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1573 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1576 SET_REGNO_REG_SET (&pseudos_counted, reg);
1578 gcc_assert (r >= 0);
1580 spill_add_cost[r] += freq;
1582 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1584 spill_cost[r + nregs] += freq;
1587 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1588 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1591 order_regs_for_reload (struct insn_chain *chain)
1594 HARD_REG_SET used_by_pseudos;
1595 HARD_REG_SET used_by_pseudos2;
1597 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1599 memset (spill_cost, 0, sizeof spill_cost);
1600 memset (spill_add_cost, 0, sizeof spill_add_cost);
1602 /* Count number of uses of each hard reg by pseudo regs allocated to it
1603 and then order them by decreasing use. First exclude hard registers
1604 that are live in or across this insn. */
1606 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1607 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1608 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1609 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1611 /* Now find out which pseudos are allocated to it, and update
1613 CLEAR_REG_SET (&pseudos_counted);
1615 EXECUTE_IF_SET_IN_REG_SET
1616 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1620 EXECUTE_IF_SET_IN_REG_SET
1621 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1625 CLEAR_REG_SET (&pseudos_counted);
1628 /* Vector of reload-numbers showing the order in which the reloads should
1630 static short reload_order[MAX_RELOADS];
1632 /* This is used to keep track of the spill regs used in one insn. */
1633 static HARD_REG_SET used_spill_regs_local;
1635 /* We decided to spill hard register SPILLED, which has a size of
1636 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1637 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1638 update SPILL_COST/SPILL_ADD_COST. */
1641 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1643 int r = reg_renumber[reg];
1644 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1646 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1647 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1650 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1652 spill_add_cost[r] -= REG_FREQ (reg);
1654 spill_cost[r + nregs] -= REG_FREQ (reg);
1657 /* Find reload register to use for reload number ORDER. */
1660 find_reg (struct insn_chain *chain, int order)
1662 int rnum = reload_order[order];
1663 struct reload *rl = rld + rnum;
1664 int best_cost = INT_MAX;
1668 HARD_REG_SET not_usable;
1669 HARD_REG_SET used_by_other_reload;
1671 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1672 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1673 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1675 CLEAR_HARD_REG_SET (used_by_other_reload);
1676 for (k = 0; k < order; k++)
1678 int other = reload_order[k];
1680 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1681 for (j = 0; j < rld[other].nregs; j++)
1682 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1685 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1687 unsigned int regno = i;
1689 if (! TEST_HARD_REG_BIT (not_usable, regno)
1690 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1691 && HARD_REGNO_MODE_OK (regno, rl->mode))
1693 int this_cost = spill_cost[regno];
1695 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1697 for (j = 1; j < this_nregs; j++)
1699 this_cost += spill_add_cost[regno + j];
1700 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1701 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1706 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1708 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1710 if (this_cost < best_cost
1711 /* Among registers with equal cost, prefer caller-saved ones, or
1712 use REG_ALLOC_ORDER if it is defined. */
1713 || (this_cost == best_cost
1714 #ifdef REG_ALLOC_ORDER
1715 && (inv_reg_alloc_order[regno]
1716 < inv_reg_alloc_order[best_reg])
1718 && call_used_regs[regno]
1719 && ! call_used_regs[best_reg]
1724 best_cost = this_cost;
1732 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1734 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1735 rl->regno = best_reg;
1737 EXECUTE_IF_SET_IN_REG_SET
1738 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1740 count_spilled_pseudo (best_reg, rl->nregs, j);
1743 EXECUTE_IF_SET_IN_REG_SET
1744 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1746 count_spilled_pseudo (best_reg, rl->nregs, j);
1749 for (i = 0; i < rl->nregs; i++)
1751 gcc_assert (spill_cost[best_reg + i] == 0);
1752 gcc_assert (spill_add_cost[best_reg + i] == 0);
1753 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1758 /* Find more reload regs to satisfy the remaining need of an insn, which
1760 Do it by ascending class number, since otherwise a reg
1761 might be spilled for a big class and might fail to count
1762 for a smaller class even though it belongs to that class. */
1765 find_reload_regs (struct insn_chain *chain)
1769 /* In order to be certain of getting the registers we need,
1770 we must sort the reloads into order of increasing register class.
1771 Then our grabbing of reload registers will parallel the process
1772 that provided the reload registers. */
1773 for (i = 0; i < chain->n_reloads; i++)
1775 /* Show whether this reload already has a hard reg. */
1776 if (chain->rld[i].reg_rtx)
1778 int regno = REGNO (chain->rld[i].reg_rtx);
1779 chain->rld[i].regno = regno;
1781 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1784 chain->rld[i].regno = -1;
1785 reload_order[i] = i;
1788 n_reloads = chain->n_reloads;
1789 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1791 CLEAR_HARD_REG_SET (used_spill_regs_local);
1794 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1796 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1798 /* Compute the order of preference for hard registers to spill. */
1800 order_regs_for_reload (chain);
1802 for (i = 0; i < n_reloads; i++)
1804 int r = reload_order[i];
1806 /* Ignore reloads that got marked inoperative. */
1807 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1808 && ! rld[r].optional
1809 && rld[r].regno == -1)
1810 if (! find_reg (chain, i))
1812 spill_failure (chain->insn, rld[r].class);
1818 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1819 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1821 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1825 select_reload_regs (void)
1827 struct insn_chain *chain;
1829 /* Try to satisfy the needs for each insn. */
1830 for (chain = insns_need_reload; chain != 0;
1831 chain = chain->next_need_reload)
1832 find_reload_regs (chain);
1835 /* Delete all insns that were inserted by emit_caller_save_insns during
1838 delete_caller_save_insns (void)
1840 struct insn_chain *c = reload_insn_chain;
1844 while (c != 0 && c->is_caller_save_insn)
1846 struct insn_chain *next = c->next;
1849 if (c == reload_insn_chain)
1850 reload_insn_chain = next;
1854 next->prev = c->prev;
1856 c->prev->next = next;
1857 c->next = unused_insn_chains;
1858 unused_insn_chains = c;
1866 /* Handle the failure to find a register to spill.
1867 INSN should be one of the insns which needed this particular spill reg. */
1870 spill_failure (rtx insn, enum reg_class class)
1872 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1873 if (asm_noperands (PATTERN (insn)) >= 0)
1874 error_for_asm (insn, "can't find a register in class `%s' while reloading `asm'",
1875 reg_class_names[class]);
1878 error ("unable to find a register to spill in class `%s'",
1879 reg_class_names[class]);
1880 fatal_insn ("this is the insn:", insn);
1884 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1885 data that is dead in INSN. */
1888 delete_dead_insn (rtx insn)
1890 rtx prev = prev_real_insn (insn);
1893 /* If the previous insn sets a register that dies in our insn, delete it
1895 if (prev && GET_CODE (PATTERN (prev)) == SET
1896 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1897 && reg_mentioned_p (prev_dest, PATTERN (insn))
1898 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1899 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1900 delete_dead_insn (prev);
1902 SET_INSN_DELETED (insn);
1905 /* Modify the home of pseudo-reg I.
1906 The new home is present in reg_renumber[I].
1908 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1909 or it may be -1, meaning there is none or it is not relevant.
1910 This is used so that all pseudos spilled from a given hard reg
1911 can share one stack slot. */
1914 alter_reg (int i, int from_reg)
1916 /* When outputting an inline function, this can happen
1917 for a reg that isn't actually used. */
1918 if (regno_reg_rtx[i] == 0)
1921 /* If the reg got changed to a MEM at rtl-generation time,
1923 if (!REG_P (regno_reg_rtx[i]))
1926 /* Modify the reg-rtx to contain the new hard reg
1927 number or else to contain its pseudo reg number. */
1928 REGNO (regno_reg_rtx[i])
1929 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1931 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1932 allocate a stack slot for it. */
1934 if (reg_renumber[i] < 0
1935 && REG_N_REFS (i) > 0
1936 && reg_equiv_constant[i] == 0
1937 && reg_equiv_memory_loc[i] == 0)
1940 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1941 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1944 /* Each pseudo reg has an inherent size which comes from its own mode,
1945 and a total size which provides room for paradoxical subregs
1946 which refer to the pseudo reg in wider modes.
1948 We can use a slot already allocated if it provides both
1949 enough inherent space and enough total space.
1950 Otherwise, we allocate a new slot, making sure that it has no less
1951 inherent space, and no less total space, then the previous slot. */
1954 /* No known place to spill from => no slot to reuse. */
1955 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1956 inherent_size == total_size ? 0 : -1);
1957 if (BYTES_BIG_ENDIAN)
1958 /* Cancel the big-endian correction done in assign_stack_local.
1959 Get the address of the beginning of the slot.
1960 This is so we can do a big-endian correction unconditionally
1962 adjust = inherent_size - total_size;
1964 /* Nothing can alias this slot except this pseudo. */
1965 set_mem_alias_set (x, new_alias_set ());
1968 /* Reuse a stack slot if possible. */
1969 else if (spill_stack_slot[from_reg] != 0
1970 && spill_stack_slot_width[from_reg] >= total_size
1971 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1973 x = spill_stack_slot[from_reg];
1975 /* Allocate a bigger slot. */
1978 /* Compute maximum size needed, both for inherent size
1979 and for total size. */
1980 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
1983 if (spill_stack_slot[from_reg])
1985 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1987 mode = GET_MODE (spill_stack_slot[from_reg]);
1988 if (spill_stack_slot_width[from_reg] > total_size)
1989 total_size = spill_stack_slot_width[from_reg];
1992 /* Make a slot with that size. */
1993 x = assign_stack_local (mode, total_size,
1994 inherent_size == total_size ? 0 : -1);
1997 /* All pseudos mapped to this slot can alias each other. */
1998 if (spill_stack_slot[from_reg])
1999 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2001 set_mem_alias_set (x, new_alias_set ());
2003 if (BYTES_BIG_ENDIAN)
2005 /* Cancel the big-endian correction done in assign_stack_local.
2006 Get the address of the beginning of the slot.
2007 This is so we can do a big-endian correction unconditionally
2009 adjust = GET_MODE_SIZE (mode) - total_size;
2012 = adjust_address_nv (x, mode_for_size (total_size
2018 spill_stack_slot[from_reg] = stack_slot;
2019 spill_stack_slot_width[from_reg] = total_size;
2022 /* On a big endian machine, the "address" of the slot
2023 is the address of the low part that fits its inherent mode. */
2024 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2025 adjust += (total_size - inherent_size);
2027 /* If we have any adjustment to make, or if the stack slot is the
2028 wrong mode, make a new stack slot. */
2029 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2031 /* If we have a decl for the original register, set it for the
2032 memory. If this is a shared MEM, make a copy. */
2033 if (REG_EXPR (regno_reg_rtx[i])
2034 && TREE_CODE_CLASS (TREE_CODE (REG_EXPR (regno_reg_rtx[i]))) == 'd')
2036 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2038 /* We can do this only for the DECLs home pseudo, not for
2039 any copies of it, since otherwise when the stack slot
2040 is reused, nonoverlapping_memrefs_p might think they
2042 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2044 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2047 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2051 /* Save the stack slot for later. */
2052 reg_equiv_memory_loc[i] = x;
2056 /* Mark the slots in regs_ever_live for the hard regs
2057 used by pseudo-reg number REGNO. */
2060 mark_home_live (int regno)
2064 i = reg_renumber[regno];
2067 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2069 regs_ever_live[i++] = 1;
2072 /* This function handles the tracking of elimination offsets around branches.
2074 X is a piece of RTL being scanned.
2076 INSN is the insn that it came from, if any.
2078 INITIAL_P is nonzero if we are to set the offset to be the initial
2079 offset and zero if we are setting the offset of the label to be the
2083 set_label_offsets (rtx x, rtx insn, int initial_p)
2085 enum rtx_code code = GET_CODE (x);
2088 struct elim_table *p;
2093 if (LABEL_REF_NONLOCAL_P (x))
2098 /* ... fall through ... */
2101 /* If we know nothing about this label, set the desired offsets. Note
2102 that this sets the offset at a label to be the offset before a label
2103 if we don't know anything about the label. This is not correct for
2104 the label after a BARRIER, but is the best guess we can make. If
2105 we guessed wrong, we will suppress an elimination that might have
2106 been possible had we been able to guess correctly. */
2108 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2110 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2111 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2112 = (initial_p ? reg_eliminate[i].initial_offset
2113 : reg_eliminate[i].offset);
2114 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2117 /* Otherwise, if this is the definition of a label and it is
2118 preceded by a BARRIER, set our offsets to the known offset of
2122 && (tem = prev_nonnote_insn (insn)) != 0
2124 set_offsets_for_label (insn);
2126 /* If neither of the above cases is true, compare each offset
2127 with those previously recorded and suppress any eliminations
2128 where the offsets disagree. */
2130 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2131 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2132 != (initial_p ? reg_eliminate[i].initial_offset
2133 : reg_eliminate[i].offset))
2134 reg_eliminate[i].can_eliminate = 0;
2139 set_label_offsets (PATTERN (insn), insn, initial_p);
2141 /* ... fall through ... */
2145 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2146 and hence must have all eliminations at their initial offsets. */
2147 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2148 if (REG_NOTE_KIND (tem) == REG_LABEL)
2149 set_label_offsets (XEXP (tem, 0), insn, 1);
2155 /* Each of the labels in the parallel or address vector must be
2156 at their initial offsets. We want the first field for PARALLEL
2157 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2159 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2160 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2165 /* We only care about setting PC. If the source is not RETURN,
2166 IF_THEN_ELSE, or a label, disable any eliminations not at
2167 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2168 isn't one of those possibilities. For branches to a label,
2169 call ourselves recursively.
2171 Note that this can disable elimination unnecessarily when we have
2172 a non-local goto since it will look like a non-constant jump to
2173 someplace in the current function. This isn't a significant
2174 problem since such jumps will normally be when all elimination
2175 pairs are back to their initial offsets. */
2177 if (SET_DEST (x) != pc_rtx)
2180 switch (GET_CODE (SET_SRC (x)))
2187 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2191 tem = XEXP (SET_SRC (x), 1);
2192 if (GET_CODE (tem) == LABEL_REF)
2193 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2194 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2197 tem = XEXP (SET_SRC (x), 2);
2198 if (GET_CODE (tem) == LABEL_REF)
2199 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2200 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2208 /* If we reach here, all eliminations must be at their initial
2209 offset because we are doing a jump to a variable address. */
2210 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2211 if (p->offset != p->initial_offset)
2212 p->can_eliminate = 0;
2220 /* Scan X and replace any eliminable registers (such as fp) with a
2221 replacement (such as sp), plus an offset.
2223 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2224 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2225 MEM, we are allowed to replace a sum of a register and the constant zero
2226 with the register, which we cannot do outside a MEM. In addition, we need
2227 to record the fact that a register is referenced outside a MEM.
2229 If INSN is an insn, it is the insn containing X. If we replace a REG
2230 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2231 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2232 the REG is being modified.
2234 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2235 That's used when we eliminate in expressions stored in notes.
2236 This means, do not set ref_outside_mem even if the reference
2239 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2240 replacements done assuming all offsets are at their initial values. If
2241 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2242 encounter, return the actual location so that find_reloads will do
2243 the proper thing. */
2246 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2248 enum rtx_code code = GET_CODE (x);
2249 struct elim_table *ep;
2256 if (! current_function_decl)
2278 /* First handle the case where we encounter a bare register that
2279 is eliminable. Replace it with a PLUS. */
2280 if (regno < FIRST_PSEUDO_REGISTER)
2282 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2284 if (ep->from_rtx == x && ep->can_eliminate)
2285 return plus_constant (ep->to_rtx, ep->previous_offset);
2288 else if (reg_renumber && reg_renumber[regno] < 0
2289 && reg_equiv_constant && reg_equiv_constant[regno]
2290 && ! CONSTANT_P (reg_equiv_constant[regno]))
2291 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2295 /* You might think handling MINUS in a manner similar to PLUS is a
2296 good idea. It is not. It has been tried multiple times and every
2297 time the change has had to have been reverted.
2299 Other parts of reload know a PLUS is special (gen_reload for example)
2300 and require special code to handle code a reloaded PLUS operand.
2302 Also consider backends where the flags register is clobbered by a
2303 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2304 lea instruction comes to mind). If we try to reload a MINUS, we
2305 may kill the flags register that was holding a useful value.
2307 So, please before trying to handle MINUS, consider reload as a
2308 whole instead of this little section as well as the backend issues. */
2310 /* If this is the sum of an eliminable register and a constant, rework
2312 if (REG_P (XEXP (x, 0))
2313 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2314 && CONSTANT_P (XEXP (x, 1)))
2316 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2318 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2320 /* The only time we want to replace a PLUS with a REG (this
2321 occurs when the constant operand of the PLUS is the negative
2322 of the offset) is when we are inside a MEM. We won't want
2323 to do so at other times because that would change the
2324 structure of the insn in a way that reload can't handle.
2325 We special-case the commonest situation in
2326 eliminate_regs_in_insn, so just replace a PLUS with a
2327 PLUS here, unless inside a MEM. */
2328 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2329 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2332 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2333 plus_constant (XEXP (x, 1),
2334 ep->previous_offset));
2337 /* If the register is not eliminable, we are done since the other
2338 operand is a constant. */
2342 /* If this is part of an address, we want to bring any constant to the
2343 outermost PLUS. We will do this by doing register replacement in
2344 our operands and seeing if a constant shows up in one of them.
2346 Note that there is no risk of modifying the structure of the insn,
2347 since we only get called for its operands, thus we are either
2348 modifying the address inside a MEM, or something like an address
2349 operand of a load-address insn. */
2352 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2353 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2355 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2357 /* If one side is a PLUS and the other side is a pseudo that
2358 didn't get a hard register but has a reg_equiv_constant,
2359 we must replace the constant here since it may no longer
2360 be in the position of any operand. */
2361 if (GET_CODE (new0) == PLUS && REG_P (new1)
2362 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2363 && reg_renumber[REGNO (new1)] < 0
2364 && reg_equiv_constant != 0
2365 && reg_equiv_constant[REGNO (new1)] != 0)
2366 new1 = reg_equiv_constant[REGNO (new1)];
2367 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2368 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2369 && reg_renumber[REGNO (new0)] < 0
2370 && reg_equiv_constant[REGNO (new0)] != 0)
2371 new0 = reg_equiv_constant[REGNO (new0)];
2373 new = form_sum (new0, new1);
2375 /* As above, if we are not inside a MEM we do not want to
2376 turn a PLUS into something else. We might try to do so here
2377 for an addition of 0 if we aren't optimizing. */
2378 if (! mem_mode && GET_CODE (new) != PLUS)
2379 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2387 /* If this is the product of an eliminable register and a
2388 constant, apply the distribute law and move the constant out
2389 so that we have (plus (mult ..) ..). This is needed in order
2390 to keep load-address insns valid. This case is pathological.
2391 We ignore the possibility of overflow here. */
2392 if (REG_P (XEXP (x, 0))
2393 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2394 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2395 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2397 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2400 /* Refs inside notes don't count for this purpose. */
2401 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2402 || GET_CODE (insn) == INSN_LIST)))
2403 ep->ref_outside_mem = 1;
2406 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2407 ep->previous_offset * INTVAL (XEXP (x, 1)));
2410 /* ... fall through ... */
2414 /* See comments before PLUS about handling MINUS. */
2416 case DIV: case UDIV:
2417 case MOD: case UMOD:
2418 case AND: case IOR: case XOR:
2419 case ROTATERT: case ROTATE:
2420 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2422 case GE: case GT: case GEU: case GTU:
2423 case LE: case LT: case LEU: case LTU:
2425 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2427 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2429 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2430 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2435 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2438 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2439 if (new != XEXP (x, 0))
2441 /* If this is a REG_DEAD note, it is not valid anymore.
2442 Using the eliminated version could result in creating a
2443 REG_DEAD note for the stack or frame pointer. */
2444 if (GET_MODE (x) == REG_DEAD)
2446 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2449 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2453 /* ... fall through ... */
2456 /* Now do eliminations in the rest of the chain. If this was
2457 an EXPR_LIST, this might result in allocating more memory than is
2458 strictly needed, but it simplifies the code. */
2461 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2462 if (new != XEXP (x, 1))
2464 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2472 case STRICT_LOW_PART:
2474 case SIGN_EXTEND: case ZERO_EXTEND:
2475 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2476 case FLOAT: case FIX:
2477 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2485 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2486 if (new != XEXP (x, 0))
2487 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2491 /* Similar to above processing, but preserve SUBREG_BYTE.
2492 Convert (subreg (mem)) to (mem) if not paradoxical.
2493 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2494 pseudo didn't get a hard reg, we must replace this with the
2495 eliminated version of the memory location because push_reload
2496 may do the replacement in certain circumstances. */
2497 if (REG_P (SUBREG_REG (x))
2498 && (GET_MODE_SIZE (GET_MODE (x))
2499 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2500 && reg_equiv_memory_loc != 0
2501 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2503 new = SUBREG_REG (x);
2506 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2508 if (new != SUBREG_REG (x))
2510 int x_size = GET_MODE_SIZE (GET_MODE (x));
2511 int new_size = GET_MODE_SIZE (GET_MODE (new));
2514 && ((x_size < new_size
2515 #ifdef WORD_REGISTER_OPERATIONS
2516 /* On these machines, combine can create rtl of the form
2517 (set (subreg:m1 (reg:m2 R) 0) ...)
2518 where m1 < m2, and expects something interesting to
2519 happen to the entire word. Moreover, it will use the
2520 (reg:m2 R) later, expecting all bits to be preserved.
2521 So if the number of words is the same, preserve the
2522 subreg so that push_reload can see it. */
2523 && ! ((x_size - 1) / UNITS_PER_WORD
2524 == (new_size -1 ) / UNITS_PER_WORD)
2527 || x_size == new_size)
2529 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2531 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2537 /* Our only special processing is to pass the mode of the MEM to our
2538 recursive call and copy the flags. While we are here, handle this
2539 case more efficiently. */
2541 replace_equiv_address_nv (x,
2542 eliminate_regs (XEXP (x, 0),
2543 GET_MODE (x), insn));
2546 /* Handle insn_list USE that a call to a pure function may generate. */
2547 new = eliminate_regs (XEXP (x, 0), 0, insn);
2548 if (new != XEXP (x, 0))
2549 return gen_rtx_USE (GET_MODE (x), new);
2561 /* Process each of our operands recursively. If any have changed, make a
2563 fmt = GET_RTX_FORMAT (code);
2564 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2568 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2569 if (new != XEXP (x, i) && ! copied)
2571 rtx new_x = rtx_alloc (code);
2572 memcpy (new_x, x, RTX_SIZE (code));
2578 else if (*fmt == 'E')
2581 for (j = 0; j < XVECLEN (x, i); j++)
2583 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2584 if (new != XVECEXP (x, i, j) && ! copied_vec)
2586 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2590 rtx new_x = rtx_alloc (code);
2591 memcpy (new_x, x, RTX_SIZE (code));
2595 XVEC (x, i) = new_v;
2598 XVECEXP (x, i, j) = new;
2606 /* Scan rtx X for modifications of elimination target registers. Update
2607 the table of eliminables to reflect the changed state. MEM_MODE is
2608 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2611 elimination_effects (rtx x, enum machine_mode mem_mode)
2613 enum rtx_code code = GET_CODE (x);
2614 struct elim_table *ep;
2638 /* First handle the case where we encounter a bare register that
2639 is eliminable. Replace it with a PLUS. */
2640 if (regno < FIRST_PSEUDO_REGISTER)
2642 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2644 if (ep->from_rtx == x && ep->can_eliminate)
2647 ep->ref_outside_mem = 1;
2652 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2653 && reg_equiv_constant[regno]
2654 && ! function_invariant_p (reg_equiv_constant[regno]))
2655 elimination_effects (reg_equiv_constant[regno], mem_mode);
2664 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2665 if (ep->to_rtx == XEXP (x, 0))
2667 int size = GET_MODE_SIZE (mem_mode);
2669 /* If more bytes than MEM_MODE are pushed, account for them. */
2670 #ifdef PUSH_ROUNDING
2671 if (ep->to_rtx == stack_pointer_rtx)
2672 size = PUSH_ROUNDING (size);
2674 if (code == PRE_DEC || code == POST_DEC)
2676 else if (code == PRE_INC || code == POST_INC)
2678 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2679 && GET_CODE (XEXP (x, 1)) == PLUS
2680 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2681 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2682 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2685 /* These two aren't unary operators. */
2686 if (code == POST_MODIFY || code == PRE_MODIFY)
2689 /* Fall through to generic unary operation case. */
2690 case STRICT_LOW_PART:
2692 case SIGN_EXTEND: case ZERO_EXTEND:
2693 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2694 case FLOAT: case FIX:
2695 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2703 elimination_effects (XEXP (x, 0), mem_mode);
2707 if (REG_P (SUBREG_REG (x))
2708 && (GET_MODE_SIZE (GET_MODE (x))
2709 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2710 && reg_equiv_memory_loc != 0
2711 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2714 elimination_effects (SUBREG_REG (x), mem_mode);
2718 /* If using a register that is the source of an eliminate we still
2719 think can be performed, note it cannot be performed since we don't
2720 know how this register is used. */
2721 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2722 if (ep->from_rtx == XEXP (x, 0))
2723 ep->can_eliminate = 0;
2725 elimination_effects (XEXP (x, 0), mem_mode);
2729 /* If clobbering a register that is the replacement register for an
2730 elimination we still think can be performed, note that it cannot
2731 be performed. Otherwise, we need not be concerned about it. */
2732 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2733 if (ep->to_rtx == XEXP (x, 0))
2734 ep->can_eliminate = 0;
2736 elimination_effects (XEXP (x, 0), mem_mode);
2740 /* Check for setting a register that we know about. */
2741 if (REG_P (SET_DEST (x)))
2743 /* See if this is setting the replacement register for an
2746 If DEST is the hard frame pointer, we do nothing because we
2747 assume that all assignments to the frame pointer are for
2748 non-local gotos and are being done at a time when they are valid
2749 and do not disturb anything else. Some machines want to
2750 eliminate a fake argument pointer (or even a fake frame pointer)
2751 with either the real frame or the stack pointer. Assignments to
2752 the hard frame pointer must not prevent this elimination. */
2754 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2756 if (ep->to_rtx == SET_DEST (x)
2757 && SET_DEST (x) != hard_frame_pointer_rtx)
2759 /* If it is being incremented, adjust the offset. Otherwise,
2760 this elimination can't be done. */
2761 rtx src = SET_SRC (x);
2763 if (GET_CODE (src) == PLUS
2764 && XEXP (src, 0) == SET_DEST (x)
2765 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2766 ep->offset -= INTVAL (XEXP (src, 1));
2768 ep->can_eliminate = 0;
2772 elimination_effects (SET_DEST (x), 0);
2773 elimination_effects (SET_SRC (x), 0);
2777 /* Our only special processing is to pass the mode of the MEM to our
2779 elimination_effects (XEXP (x, 0), GET_MODE (x));
2786 fmt = GET_RTX_FORMAT (code);
2787 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2790 elimination_effects (XEXP (x, i), mem_mode);
2791 else if (*fmt == 'E')
2792 for (j = 0; j < XVECLEN (x, i); j++)
2793 elimination_effects (XVECEXP (x, i, j), mem_mode);
2797 /* Descend through rtx X and verify that no references to eliminable registers
2798 remain. If any do remain, mark the involved register as not
2802 check_eliminable_occurrences (rtx x)
2811 code = GET_CODE (x);
2813 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2815 struct elim_table *ep;
2817 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2818 if (ep->from_rtx == x)
2819 ep->can_eliminate = 0;
2823 fmt = GET_RTX_FORMAT (code);
2824 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2827 check_eliminable_occurrences (XEXP (x, i));
2828 else if (*fmt == 'E')
2831 for (j = 0; j < XVECLEN (x, i); j++)
2832 check_eliminable_occurrences (XVECEXP (x, i, j));
2837 /* Scan INSN and eliminate all eliminable registers in it.
2839 If REPLACE is nonzero, do the replacement destructively. Also
2840 delete the insn as dead it if it is setting an eliminable register.
2842 If REPLACE is zero, do all our allocations in reload_obstack.
2844 If no eliminations were done and this insn doesn't require any elimination
2845 processing (these are not identical conditions: it might be updating sp,
2846 but not referencing fp; this needs to be seen during reload_as_needed so
2847 that the offset between fp and sp can be taken into consideration), zero
2848 is returned. Otherwise, 1 is returned. */
2851 eliminate_regs_in_insn (rtx insn, int replace)
2853 int icode = recog_memoized (insn);
2854 rtx old_body = PATTERN (insn);
2855 int insn_is_asm = asm_noperands (old_body) >= 0;
2856 rtx old_set = single_set (insn);
2860 rtx substed_operand[MAX_RECOG_OPERANDS];
2861 rtx orig_operand[MAX_RECOG_OPERANDS];
2862 struct elim_table *ep;
2865 if (! insn_is_asm && icode < 0)
2867 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2868 || GET_CODE (PATTERN (insn)) == CLOBBER
2869 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2870 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2871 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2875 if (old_set != 0 && REG_P (SET_DEST (old_set))
2876 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2878 /* Check for setting an eliminable register. */
2879 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2880 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2882 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2883 /* If this is setting the frame pointer register to the
2884 hardware frame pointer register and this is an elimination
2885 that will be done (tested above), this insn is really
2886 adjusting the frame pointer downward to compensate for
2887 the adjustment done before a nonlocal goto. */
2888 if (ep->from == FRAME_POINTER_REGNUM
2889 && ep->to == HARD_FRAME_POINTER_REGNUM)
2891 rtx base = SET_SRC (old_set);
2892 rtx base_insn = insn;
2893 HOST_WIDE_INT offset = 0;
2895 while (base != ep->to_rtx)
2897 rtx prev_insn, prev_set;
2899 if (GET_CODE (base) == PLUS
2900 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2902 offset += INTVAL (XEXP (base, 1));
2903 base = XEXP (base, 0);
2905 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2906 && (prev_set = single_set (prev_insn)) != 0
2907 && rtx_equal_p (SET_DEST (prev_set), base))
2909 base = SET_SRC (prev_set);
2910 base_insn = prev_insn;
2916 if (base == ep->to_rtx)
2919 = plus_constant (ep->to_rtx, offset - ep->offset);
2921 new_body = old_body;
2924 new_body = copy_insn (old_body);
2925 if (REG_NOTES (insn))
2926 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2928 PATTERN (insn) = new_body;
2929 old_set = single_set (insn);
2931 /* First see if this insn remains valid when we
2932 make the change. If not, keep the INSN_CODE
2933 the same and let reload fit it up. */
2934 validate_change (insn, &SET_SRC (old_set), src, 1);
2935 validate_change (insn, &SET_DEST (old_set),
2937 if (! apply_change_group ())
2939 SET_SRC (old_set) = src;
2940 SET_DEST (old_set) = ep->to_rtx;
2949 /* In this case this insn isn't serving a useful purpose. We
2950 will delete it in reload_as_needed once we know that this
2951 elimination is, in fact, being done.
2953 If REPLACE isn't set, we can't delete this insn, but needn't
2954 process it since it won't be used unless something changes. */
2957 delete_dead_insn (insn);
2965 /* We allow one special case which happens to work on all machines we
2966 currently support: a single set with the source or a REG_EQUAL
2967 note being a PLUS of an eliminable register and a constant. */
2969 if (old_set && REG_P (SET_DEST (old_set)))
2971 /* First see if the source is of the form (plus (reg) CST). */
2972 if (GET_CODE (SET_SRC (old_set)) == PLUS
2973 && REG_P (XEXP (SET_SRC (old_set), 0))
2974 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
2975 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
2976 plus_src = SET_SRC (old_set);
2977 else if (REG_P (SET_SRC (old_set)))
2979 /* Otherwise, see if we have a REG_EQUAL note of the form
2980 (plus (reg) CST). */
2982 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
2984 if (REG_NOTE_KIND (links) == REG_EQUAL
2985 && GET_CODE (XEXP (links, 0)) == PLUS
2986 && REG_P (XEXP (XEXP (links, 0), 0))
2987 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT
2988 && REGNO (XEXP (XEXP (links, 0), 0)) < FIRST_PSEUDO_REGISTER)
2990 plus_src = XEXP (links, 0);
2998 rtx reg = XEXP (plus_src, 0);
2999 HOST_WIDE_INT offset = INTVAL (XEXP (plus_src, 1));
3001 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3002 if (ep->from_rtx == reg && ep->can_eliminate)
3004 offset += ep->offset;
3009 /* We assume here that if we need a PARALLEL with
3010 CLOBBERs for this assignment, we can do with the
3011 MATCH_SCRATCHes that add_clobbers allocates.
3012 There's not much we can do if that doesn't work. */
3013 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3017 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3020 rtvec vec = rtvec_alloc (num_clobbers + 1);
3022 vec->elem[0] = PATTERN (insn);
3023 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3024 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3026 gcc_assert (INSN_CODE (insn) >= 0);
3028 /* If we have a nonzero offset, and the source is already
3029 a simple REG, the following transformation would
3030 increase the cost of the insn by replacing a simple REG
3031 with (plus (reg sp) CST). So try only when plus_src
3032 comes from old_set proper, not REG_NOTES. */
3033 else if (SET_SRC (old_set) == plus_src)
3035 new_body = old_body;
3038 new_body = copy_insn (old_body);
3039 if (REG_NOTES (insn))
3040 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3042 PATTERN (insn) = new_body;
3043 old_set = single_set (insn);
3045 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3046 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3052 /* This can't have an effect on elimination offsets, so skip right
3058 /* Determine the effects of this insn on elimination offsets. */
3059 elimination_effects (old_body, 0);
3061 /* Eliminate all eliminable registers occurring in operands that
3062 can be handled by reload. */
3063 extract_insn (insn);
3064 for (i = 0; i < recog_data.n_operands; i++)
3066 orig_operand[i] = recog_data.operand[i];
3067 substed_operand[i] = recog_data.operand[i];
3069 /* For an asm statement, every operand is eliminable. */
3070 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3072 /* Check for setting a register that we know about. */
3073 if (recog_data.operand_type[i] != OP_IN
3074 && REG_P (orig_operand[i]))
3076 /* If we are assigning to a register that can be eliminated, it
3077 must be as part of a PARALLEL, since the code above handles
3078 single SETs. We must indicate that we can no longer
3079 eliminate this reg. */
3080 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3082 if (ep->from_rtx == orig_operand[i])
3083 ep->can_eliminate = 0;
3086 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3087 replace ? insn : NULL_RTX);
3088 if (substed_operand[i] != orig_operand[i])
3090 /* Terminate the search in check_eliminable_occurrences at
3092 *recog_data.operand_loc[i] = 0;
3094 /* If an output operand changed from a REG to a MEM and INSN is an
3095 insn, write a CLOBBER insn. */
3096 if (recog_data.operand_type[i] != OP_IN
3097 && REG_P (orig_operand[i])
3098 && MEM_P (substed_operand[i])
3100 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3105 for (i = 0; i < recog_data.n_dups; i++)
3106 *recog_data.dup_loc[i]
3107 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3109 /* If any eliminable remain, they aren't eliminable anymore. */
3110 check_eliminable_occurrences (old_body);
3112 /* Substitute the operands; the new values are in the substed_operand
3114 for (i = 0; i < recog_data.n_operands; i++)
3115 *recog_data.operand_loc[i] = substed_operand[i];
3116 for (i = 0; i < recog_data.n_dups; i++)
3117 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3119 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3120 re-recognize the insn. We do this in case we had a simple addition
3121 but now can do this as a load-address. This saves an insn in this
3123 If re-recognition fails, the old insn code number will still be used,
3124 and some register operands may have changed into PLUS expressions.
3125 These will be handled by find_reloads by loading them into a register
3130 /* If we aren't replacing things permanently and we changed something,
3131 make another copy to ensure that all the RTL is new. Otherwise
3132 things can go wrong if find_reload swaps commutative operands
3133 and one is inside RTL that has been copied while the other is not. */
3134 new_body = old_body;
3137 new_body = copy_insn (old_body);
3138 if (REG_NOTES (insn))
3139 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3141 PATTERN (insn) = new_body;
3143 /* If we had a move insn but now we don't, rerecognize it. This will
3144 cause spurious re-recognition if the old move had a PARALLEL since
3145 the new one still will, but we can't call single_set without
3146 having put NEW_BODY into the insn and the re-recognition won't
3147 hurt in this rare case. */
3148 /* ??? Why this huge if statement - why don't we just rerecognize the
3152 && ((REG_P (SET_SRC (old_set))
3153 && (GET_CODE (new_body) != SET
3154 || !REG_P (SET_SRC (new_body))))
3155 /* If this was a load from or store to memory, compare
3156 the MEM in recog_data.operand to the one in the insn.
3157 If they are not equal, then rerecognize the insn. */
3159 && ((MEM_P (SET_SRC (old_set))
3160 && SET_SRC (old_set) != recog_data.operand[1])
3161 || (MEM_P (SET_DEST (old_set))
3162 && SET_DEST (old_set) != recog_data.operand[0])))
3163 /* If this was an add insn before, rerecognize. */
3164 || GET_CODE (SET_SRC (old_set)) == PLUS))
3166 int new_icode = recog (PATTERN (insn), insn, 0);
3168 INSN_CODE (insn) = icode;
3172 /* Restore the old body. If there were any changes to it, we made a copy
3173 of it while the changes were still in place, so we'll correctly return
3174 a modified insn below. */
3177 /* Restore the old body. */
3178 for (i = 0; i < recog_data.n_operands; i++)
3179 *recog_data.operand_loc[i] = orig_operand[i];
3180 for (i = 0; i < recog_data.n_dups; i++)
3181 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3184 /* Update all elimination pairs to reflect the status after the current
3185 insn. The changes we make were determined by the earlier call to
3186 elimination_effects.
3188 We also detect cases where register elimination cannot be done,
3189 namely, if a register would be both changed and referenced outside a MEM
3190 in the resulting insn since such an insn is often undefined and, even if
3191 not, we cannot know what meaning will be given to it. Note that it is
3192 valid to have a register used in an address in an insn that changes it
3193 (presumably with a pre- or post-increment or decrement).
3195 If anything changes, return nonzero. */
3197 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3199 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3200 ep->can_eliminate = 0;
3202 ep->ref_outside_mem = 0;
3204 if (ep->previous_offset != ep->offset)
3209 /* If we changed something, perform elimination in REG_NOTES. This is
3210 needed even when REPLACE is zero because a REG_DEAD note might refer
3211 to a register that we eliminate and could cause a different number
3212 of spill registers to be needed in the final reload pass than in
3214 if (val && REG_NOTES (insn) != 0)
3215 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3220 /* Loop through all elimination pairs.
3221 Recalculate the number not at initial offset.
3223 Compute the maximum offset (minimum offset if the stack does not
3224 grow downward) for each elimination pair. */
3227 update_eliminable_offsets (void)
3229 struct elim_table *ep;
3231 num_not_at_initial_offset = 0;
3232 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3234 ep->previous_offset = ep->offset;
3235 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3236 num_not_at_initial_offset++;
3240 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3241 replacement we currently believe is valid, mark it as not eliminable if X
3242 modifies DEST in any way other than by adding a constant integer to it.
3244 If DEST is the frame pointer, we do nothing because we assume that
3245 all assignments to the hard frame pointer are nonlocal gotos and are being
3246 done at a time when they are valid and do not disturb anything else.
3247 Some machines want to eliminate a fake argument pointer with either the
3248 frame or stack pointer. Assignments to the hard frame pointer must not
3249 prevent this elimination.
3251 Called via note_stores from reload before starting its passes to scan
3252 the insns of the function. */
3255 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3259 /* A SUBREG of a hard register here is just changing its mode. We should
3260 not see a SUBREG of an eliminable hard register, but check just in
3262 if (GET_CODE (dest) == SUBREG)
3263 dest = SUBREG_REG (dest);
3265 if (dest == hard_frame_pointer_rtx)
3268 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3269 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3270 && (GET_CODE (x) != SET
3271 || GET_CODE (SET_SRC (x)) != PLUS
3272 || XEXP (SET_SRC (x), 0) != dest
3273 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3275 reg_eliminate[i].can_eliminate_previous
3276 = reg_eliminate[i].can_eliminate = 0;
3281 /* Verify that the initial elimination offsets did not change since the
3282 last call to set_initial_elim_offsets. This is used to catch cases
3283 where something illegal happened during reload_as_needed that could
3284 cause incorrect code to be generated if we did not check for it. */
3287 verify_initial_elim_offsets (void)
3291 #ifdef ELIMINABLE_REGS
3292 struct elim_table *ep;
3294 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3296 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3297 gcc_assert (t == ep->initial_offset);
3300 INITIAL_FRAME_POINTER_OFFSET (t);
3301 gcc_assert (t == reg_eliminate[0].initial_offset);
3305 /* Reset all offsets on eliminable registers to their initial values. */
3308 set_initial_elim_offsets (void)
3310 struct elim_table *ep = reg_eliminate;
3312 #ifdef ELIMINABLE_REGS
3313 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3315 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3316 ep->previous_offset = ep->offset = ep->initial_offset;
3319 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3320 ep->previous_offset = ep->offset = ep->initial_offset;
3323 num_not_at_initial_offset = 0;
3326 /* Initialize the known label offsets.
3327 Set a known offset for each forced label to be at the initial offset
3328 of each elimination. We do this because we assume that all
3329 computed jumps occur from a location where each elimination is
3330 at its initial offset.
3331 For all other labels, show that we don't know the offsets. */
3334 set_initial_label_offsets (void)
3337 memset (offsets_known_at, 0, num_labels);
3339 for (x = forced_labels; x; x = XEXP (x, 1))
3341 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3344 /* Set all elimination offsets to the known values for the code label given
3348 set_offsets_for_label (rtx insn)
3351 int label_nr = CODE_LABEL_NUMBER (insn);
3352 struct elim_table *ep;
3354 num_not_at_initial_offset = 0;
3355 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3357 ep->offset = ep->previous_offset
3358 = offsets_at[label_nr - first_label_num][i];
3359 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3360 num_not_at_initial_offset++;
3364 /* See if anything that happened changes which eliminations are valid.
3365 For example, on the SPARC, whether or not the frame pointer can
3366 be eliminated can depend on what registers have been used. We need
3367 not check some conditions again (such as flag_omit_frame_pointer)
3368 since they can't have changed. */
3371 update_eliminables (HARD_REG_SET *pset)
3373 int previous_frame_pointer_needed = frame_pointer_needed;
3374 struct elim_table *ep;
3376 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3377 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3378 #ifdef ELIMINABLE_REGS
3379 || ! CAN_ELIMINATE (ep->from, ep->to)
3382 ep->can_eliminate = 0;
3384 /* Look for the case where we have discovered that we can't replace
3385 register A with register B and that means that we will now be
3386 trying to replace register A with register C. This means we can
3387 no longer replace register C with register B and we need to disable
3388 such an elimination, if it exists. This occurs often with A == ap,
3389 B == sp, and C == fp. */
3391 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3393 struct elim_table *op;
3396 if (! ep->can_eliminate && ep->can_eliminate_previous)
3398 /* Find the current elimination for ep->from, if there is a
3400 for (op = reg_eliminate;
3401 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3402 if (op->from == ep->from && op->can_eliminate)
3408 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3410 for (op = reg_eliminate;
3411 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3412 if (op->from == new_to && op->to == ep->to)
3413 op->can_eliminate = 0;
3417 /* See if any registers that we thought we could eliminate the previous
3418 time are no longer eliminable. If so, something has changed and we
3419 must spill the register. Also, recompute the number of eliminable
3420 registers and see if the frame pointer is needed; it is if there is
3421 no elimination of the frame pointer that we can perform. */
3423 frame_pointer_needed = 1;
3424 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3426 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3427 && ep->to != HARD_FRAME_POINTER_REGNUM)
3428 frame_pointer_needed = 0;
3430 if (! ep->can_eliminate && ep->can_eliminate_previous)
3432 ep->can_eliminate_previous = 0;
3433 SET_HARD_REG_BIT (*pset, ep->from);
3438 /* If we didn't need a frame pointer last time, but we do now, spill
3439 the hard frame pointer. */
3440 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3441 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3444 /* Initialize the table of registers to eliminate. */
3447 init_elim_table (void)
3449 struct elim_table *ep;
3450 #ifdef ELIMINABLE_REGS
3451 const struct elim_table_1 *ep1;
3455 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3457 /* Does this function require a frame pointer? */
3459 frame_pointer_needed = (! flag_omit_frame_pointer
3460 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3461 and restore sp for alloca. So we can't eliminate
3462 the frame pointer in that case. At some point,
3463 we should improve this by emitting the
3464 sp-adjusting insns for this case. */
3465 || (current_function_calls_alloca
3466 && EXIT_IGNORE_STACK)
3467 || FRAME_POINTER_REQUIRED);
3471 #ifdef ELIMINABLE_REGS
3472 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3473 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3475 ep->from = ep1->from;
3477 ep->can_eliminate = ep->can_eliminate_previous
3478 = (CAN_ELIMINATE (ep->from, ep->to)
3479 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3482 reg_eliminate[0].from = reg_eliminate_1[0].from;
3483 reg_eliminate[0].to = reg_eliminate_1[0].to;
3484 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3485 = ! frame_pointer_needed;
3488 /* Count the number of eliminable registers and build the FROM and TO
3489 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3490 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3491 We depend on this. */
3492 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3494 num_eliminable += ep->can_eliminate;
3495 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3496 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3500 /* Kick all pseudos out of hard register REGNO.
3502 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3503 because we found we can't eliminate some register. In the case, no pseudos
3504 are allowed to be in the register, even if they are only in a block that
3505 doesn't require spill registers, unlike the case when we are spilling this
3506 hard reg to produce another spill register.
3508 Return nonzero if any pseudos needed to be kicked out. */
3511 spill_hard_reg (unsigned int regno, int cant_eliminate)
3517 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3518 regs_ever_live[regno] = 1;
3521 /* Spill every pseudo reg that was allocated to this reg
3522 or to something that overlaps this reg. */
3524 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3525 if (reg_renumber[i] >= 0
3526 && (unsigned int) reg_renumber[i] <= regno
3527 && ((unsigned int) reg_renumber[i]
3528 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3529 [PSEUDO_REGNO_MODE (i)]
3531 SET_REGNO_REG_SET (&spilled_pseudos, i);
3534 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3535 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3538 ior_hard_reg_set (HARD_REG_SET *set1, HARD_REG_SET *set2)
3540 IOR_HARD_REG_SET (*set1, *set2);
3543 /* After find_reload_regs has been run for all insn that need reloads,
3544 and/or spill_hard_regs was called, this function is used to actually
3545 spill pseudo registers and try to reallocate them. It also sets up the
3546 spill_regs array for use by choose_reload_regs. */
3549 finish_spills (int global)
3551 struct insn_chain *chain;
3552 int something_changed = 0;
3555 /* Build the spill_regs array for the function. */
3556 /* If there are some registers still to eliminate and one of the spill regs
3557 wasn't ever used before, additional stack space may have to be
3558 allocated to store this register. Thus, we may have changed the offset
3559 between the stack and frame pointers, so mark that something has changed.
3561 One might think that we need only set VAL to 1 if this is a call-used
3562 register. However, the set of registers that must be saved by the
3563 prologue is not identical to the call-used set. For example, the
3564 register used by the call insn for the return PC is a call-used register,
3565 but must be saved by the prologue. */
3568 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3569 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3571 spill_reg_order[i] = n_spills;
3572 spill_regs[n_spills++] = i;
3573 if (num_eliminable && ! regs_ever_live[i])
3574 something_changed = 1;
3575 regs_ever_live[i] = 1;
3578 spill_reg_order[i] = -1;
3580 EXECUTE_IF_SET_IN_REG_SET
3581 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3583 /* Record the current hard register the pseudo is allocated to in
3584 pseudo_previous_regs so we avoid reallocating it to the same
3585 hard reg in a later pass. */
3586 gcc_assert (reg_renumber[i] >= 0);
3588 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3589 /* Mark it as no longer having a hard register home. */
3590 reg_renumber[i] = -1;
3591 /* We will need to scan everything again. */
3592 something_changed = 1;
3595 /* Retry global register allocation if possible. */
3598 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3599 /* For every insn that needs reloads, set the registers used as spill
3600 regs in pseudo_forbidden_regs for every pseudo live across the
3602 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3604 EXECUTE_IF_SET_IN_REG_SET
3605 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3607 ior_hard_reg_set (pseudo_forbidden_regs + i,
3608 &chain->used_spill_regs);
3610 EXECUTE_IF_SET_IN_REG_SET
3611 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3613 ior_hard_reg_set (pseudo_forbidden_regs + i,
3614 &chain->used_spill_regs);
3618 /* Retry allocating the spilled pseudos. For each reg, merge the
3619 various reg sets that indicate which hard regs can't be used,
3620 and call retry_global_alloc.
3621 We change spill_pseudos here to only contain pseudos that did not
3622 get a new hard register. */
3623 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3624 if (reg_old_renumber[i] != reg_renumber[i])
3626 HARD_REG_SET forbidden;
3627 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3628 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3629 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3630 retry_global_alloc (i, forbidden);
3631 if (reg_renumber[i] >= 0)
3632 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3636 /* Fix up the register information in the insn chain.
3637 This involves deleting those of the spilled pseudos which did not get
3638 a new hard register home from the live_{before,after} sets. */
3639 for (chain = reload_insn_chain; chain; chain = chain->next)
3641 HARD_REG_SET used_by_pseudos;
3642 HARD_REG_SET used_by_pseudos2;
3644 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3645 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3647 /* Mark any unallocated hard regs as available for spills. That
3648 makes inheritance work somewhat better. */
3649 if (chain->need_reload)
3651 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3652 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3653 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3655 /* Save the old value for the sanity test below. */
3656 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3658 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3659 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3660 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3661 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3663 /* Make sure we only enlarge the set. */
3664 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3670 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3671 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3673 int regno = reg_renumber[i];
3674 if (reg_old_renumber[i] == regno)
3677 alter_reg (i, reg_old_renumber[i]);
3678 reg_old_renumber[i] = regno;
3682 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3684 fprintf (dump_file, " Register %d now in %d.\n\n",
3685 i, reg_renumber[i]);
3689 return something_changed;
3692 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3695 scan_paradoxical_subregs (rtx x)
3699 enum rtx_code code = GET_CODE (x);
3709 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3717 if (REG_P (SUBREG_REG (x))
3718 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3719 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3720 = GET_MODE_SIZE (GET_MODE (x));
3727 fmt = GET_RTX_FORMAT (code);
3728 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3731 scan_paradoxical_subregs (XEXP (x, i));
3732 else if (fmt[i] == 'E')
3735 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3736 scan_paradoxical_subregs (XVECEXP (x, i, j));
3741 /* Reload pseudo-registers into hard regs around each insn as needed.
3742 Additional register load insns are output before the insn that needs it
3743 and perhaps store insns after insns that modify the reloaded pseudo reg.
3745 reg_last_reload_reg and reg_reloaded_contents keep track of
3746 which registers are already available in reload registers.
3747 We update these for the reloads that we perform,
3748 as the insns are scanned. */
3751 reload_as_needed (int live_known)
3753 struct insn_chain *chain;
3754 #if defined (AUTO_INC_DEC)
3759 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3760 memset (spill_reg_store, 0, sizeof spill_reg_store);
3761 reg_last_reload_reg = xcalloc (max_regno, sizeof (rtx));
3762 reg_has_output_reload = xmalloc (max_regno);
3763 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3764 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3766 set_initial_elim_offsets ();
3768 for (chain = reload_insn_chain; chain; chain = chain->next)
3771 rtx insn = chain->insn;
3772 rtx old_next = NEXT_INSN (insn);
3774 /* If we pass a label, copy the offsets from the label information
3775 into the current offsets of each elimination. */
3777 set_offsets_for_label (insn);
3779 else if (INSN_P (insn))
3781 rtx oldpat = copy_rtx (PATTERN (insn));
3783 /* If this is a USE and CLOBBER of a MEM, ensure that any
3784 references to eliminable registers have been removed. */
3786 if ((GET_CODE (PATTERN (insn)) == USE
3787 || GET_CODE (PATTERN (insn)) == CLOBBER)
3788 && MEM_P (XEXP (PATTERN (insn), 0)))
3789 XEXP (XEXP (PATTERN (insn), 0), 0)
3790 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3791 GET_MODE (XEXP (PATTERN (insn), 0)),
3794 /* If we need to do register elimination processing, do so.
3795 This might delete the insn, in which case we are done. */
3796 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3798 eliminate_regs_in_insn (insn, 1);
3801 update_eliminable_offsets ();
3806 /* If need_elim is nonzero but need_reload is zero, one might think
3807 that we could simply set n_reloads to 0. However, find_reloads
3808 could have done some manipulation of the insn (such as swapping
3809 commutative operands), and these manipulations are lost during
3810 the first pass for every insn that needs register elimination.
3811 So the actions of find_reloads must be redone here. */
3813 if (! chain->need_elim && ! chain->need_reload
3814 && ! chain->need_operand_change)
3816 /* First find the pseudo regs that must be reloaded for this insn.
3817 This info is returned in the tables reload_... (see reload.h).
3818 Also modify the body of INSN by substituting RELOAD
3819 rtx's for those pseudo regs. */
3822 memset (reg_has_output_reload, 0, max_regno);
3823 CLEAR_HARD_REG_SET (reg_is_output_reload);
3825 find_reloads (insn, 1, spill_indirect_levels, live_known,
3831 rtx next = NEXT_INSN (insn);
3834 prev = PREV_INSN (insn);
3836 /* Now compute which reload regs to reload them into. Perhaps
3837 reusing reload regs from previous insns, or else output
3838 load insns to reload them. Maybe output store insns too.
3839 Record the choices of reload reg in reload_reg_rtx. */
3840 choose_reload_regs (chain);
3842 /* Merge any reloads that we didn't combine for fear of
3843 increasing the number of spill registers needed but now
3844 discover can be safely merged. */
3845 if (SMALL_REGISTER_CLASSES)
3846 merge_assigned_reloads (insn);
3848 /* Generate the insns to reload operands into or out of
3849 their reload regs. */
3850 emit_reload_insns (chain);
3852 /* Substitute the chosen reload regs from reload_reg_rtx
3853 into the insn's body (or perhaps into the bodies of other
3854 load and store insn that we just made for reloading
3855 and that we moved the structure into). */
3856 subst_reloads (insn);
3858 /* If this was an ASM, make sure that all the reload insns
3859 we have generated are valid. If not, give an error
3862 if (asm_noperands (PATTERN (insn)) >= 0)
3863 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3864 if (p != insn && INSN_P (p)
3865 && GET_CODE (PATTERN (p)) != USE
3866 && (recog_memoized (p) < 0
3867 || (extract_insn (p), ! constrain_operands (1))))
3869 error_for_asm (insn,
3870 "`asm' operand requires impossible reload");
3875 if (num_eliminable && chain->need_elim)
3876 update_eliminable_offsets ();
3878 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3879 is no longer validly lying around to save a future reload.
3880 Note that this does not detect pseudos that were reloaded
3881 for this insn in order to be stored in
3882 (obeying register constraints). That is correct; such reload
3883 registers ARE still valid. */
3884 note_stores (oldpat, forget_old_reloads_1, NULL);
3886 /* There may have been CLOBBER insns placed after INSN. So scan
3887 between INSN and NEXT and use them to forget old reloads. */
3888 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3889 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
3890 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3893 /* Likewise for regs altered by auto-increment in this insn.
3894 REG_INC notes have been changed by reloading:
3895 find_reloads_address_1 records substitutions for them,
3896 which have been performed by subst_reloads above. */
3897 for (i = n_reloads - 1; i >= 0; i--)
3899 rtx in_reg = rld[i].in_reg;
3902 enum rtx_code code = GET_CODE (in_reg);
3903 /* PRE_INC / PRE_DEC will have the reload register ending up
3904 with the same value as the stack slot, but that doesn't
3905 hold true for POST_INC / POST_DEC. Either we have to
3906 convert the memory access to a true POST_INC / POST_DEC,
3907 or we can't use the reload register for inheritance. */
3908 if ((code == POST_INC || code == POST_DEC)
3909 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3910 REGNO (rld[i].reg_rtx))
3911 /* Make sure it is the inc/dec pseudo, and not
3912 some other (e.g. output operand) pseudo. */
3913 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3914 == REGNO (XEXP (in_reg, 0))))
3917 rtx reload_reg = rld[i].reg_rtx;
3918 enum machine_mode mode = GET_MODE (reload_reg);
3922 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3924 /* We really want to ignore REG_INC notes here, so
3925 use PATTERN (p) as argument to reg_set_p . */
3926 if (reg_set_p (reload_reg, PATTERN (p)))
3928 n = count_occurrences (PATTERN (p), reload_reg, 0);
3933 n = validate_replace_rtx (reload_reg,
3934 gen_rtx_fmt_e (code,
3939 /* We must also verify that the constraints
3940 are met after the replacement. */
3943 n = constrain_operands (1);
3947 /* If the constraints were not met, then
3948 undo the replacement. */
3951 validate_replace_rtx (gen_rtx_fmt_e (code,
3964 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
3966 /* Mark this as having an output reload so that the
3967 REG_INC processing code below won't invalidate
3968 the reload for inheritance. */
3969 SET_HARD_REG_BIT (reg_is_output_reload,
3970 REGNO (reload_reg));
3971 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3974 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
3977 else if ((code == PRE_INC || code == PRE_DEC)
3978 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3979 REGNO (rld[i].reg_rtx))
3980 /* Make sure it is the inc/dec pseudo, and not
3981 some other (e.g. output operand) pseudo. */
3982 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3983 == REGNO (XEXP (in_reg, 0))))
3985 SET_HARD_REG_BIT (reg_is_output_reload,
3986 REGNO (rld[i].reg_rtx));
3987 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
3991 /* If a pseudo that got a hard register is auto-incremented,
3992 we must purge records of copying it into pseudos without
3994 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
3995 if (REG_NOTE_KIND (x) == REG_INC)
3997 /* See if this pseudo reg was reloaded in this insn.
3998 If so, its last-reload info is still valid
3999 because it is based on this insn's reload. */
4000 for (i = 0; i < n_reloads; i++)
4001 if (rld[i].out == XEXP (x, 0))
4005 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4009 /* A reload reg's contents are unknown after a label. */
4011 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4013 /* Don't assume a reload reg is still good after a call insn
4014 if it is a call-used reg, or if it contains a value that will
4015 be partially clobbered by the call. */
4016 else if (CALL_P (insn))
4018 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4019 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4024 free (reg_last_reload_reg);
4025 free (reg_has_output_reload);
4028 /* Discard all record of any value reloaded from X,
4029 or reloaded in X from someplace else;
4030 unless X is an output reload reg of the current insn.
4032 X may be a hard reg (the reload reg)
4033 or it may be a pseudo reg that was reloaded from. */
4036 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4037 void *data ATTRIBUTE_UNUSED)
4042 /* note_stores does give us subregs of hard regs,
4043 subreg_regno_offset will abort if it is not a hard reg. */
4044 while (GET_CODE (x) == SUBREG)
4046 /* We ignore the subreg offset when calculating the regno,
4047 because we are using the entire underlying hard register
4057 if (regno >= FIRST_PSEUDO_REGISTER)
4063 nr = hard_regno_nregs[regno][GET_MODE (x)];
4064 /* Storing into a spilled-reg invalidates its contents.
4065 This can happen if a block-local pseudo is allocated to that reg
4066 and it wasn't spilled because this block's total need is 0.
4067 Then some insn might have an optional reload and use this reg. */
4068 for (i = 0; i < nr; i++)
4069 /* But don't do this if the reg actually serves as an output
4070 reload reg in the current instruction. */
4072 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4074 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4075 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4076 spill_reg_store[regno + i] = 0;
4080 /* Since value of X has changed,
4081 forget any value previously copied from it. */
4084 /* But don't forget a copy if this is the output reload
4085 that establishes the copy's validity. */
4086 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4087 reg_last_reload_reg[regno + nr] = 0;
4090 /* The following HARD_REG_SETs indicate when each hard register is
4091 used for a reload of various parts of the current insn. */
4093 /* If reg is unavailable for all reloads. */
4094 static HARD_REG_SET reload_reg_unavailable;
4095 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4096 static HARD_REG_SET reload_reg_used;
4097 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4098 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4099 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4100 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4101 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4102 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4103 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4104 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4105 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4106 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4107 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4108 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4109 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4110 static HARD_REG_SET reload_reg_used_in_op_addr;
4111 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4112 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4113 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4114 static HARD_REG_SET reload_reg_used_in_insn;
4115 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4116 static HARD_REG_SET reload_reg_used_in_other_addr;
4118 /* If reg is in use as a reload reg for any sort of reload. */
4119 static HARD_REG_SET reload_reg_used_at_all;
4121 /* If reg is use as an inherited reload. We just mark the first register
4123 static HARD_REG_SET reload_reg_used_for_inherit;
4125 /* Records which hard regs are used in any way, either as explicit use or
4126 by being allocated to a pseudo during any point of the current insn. */
4127 static HARD_REG_SET reg_used_in_insn;
4129 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4130 TYPE. MODE is used to indicate how many consecutive regs are
4134 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4135 enum machine_mode mode)
4137 unsigned int nregs = hard_regno_nregs[regno][mode];
4140 for (i = regno; i < nregs + regno; i++)
4145 SET_HARD_REG_BIT (reload_reg_used, i);
4148 case RELOAD_FOR_INPUT_ADDRESS:
4149 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4152 case RELOAD_FOR_INPADDR_ADDRESS:
4153 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4156 case RELOAD_FOR_OUTPUT_ADDRESS:
4157 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4160 case RELOAD_FOR_OUTADDR_ADDRESS:
4161 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4164 case RELOAD_FOR_OPERAND_ADDRESS:
4165 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4168 case RELOAD_FOR_OPADDR_ADDR:
4169 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4172 case RELOAD_FOR_OTHER_ADDRESS:
4173 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4176 case RELOAD_FOR_INPUT:
4177 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4180 case RELOAD_FOR_OUTPUT:
4181 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4184 case RELOAD_FOR_INSN:
4185 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4189 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4193 /* Similarly, but show REGNO is no longer in use for a reload. */
4196 clear_reload_reg_in_use (unsigned int regno, int opnum,
4197 enum reload_type type, enum machine_mode mode)
4199 unsigned int nregs = hard_regno_nregs[regno][mode];
4200 unsigned int start_regno, end_regno, r;
4202 /* A complication is that for some reload types, inheritance might
4203 allow multiple reloads of the same types to share a reload register.
4204 We set check_opnum if we have to check only reloads with the same
4205 operand number, and check_any if we have to check all reloads. */
4206 int check_opnum = 0;
4208 HARD_REG_SET *used_in_set;
4213 used_in_set = &reload_reg_used;
4216 case RELOAD_FOR_INPUT_ADDRESS:
4217 used_in_set = &reload_reg_used_in_input_addr[opnum];
4220 case RELOAD_FOR_INPADDR_ADDRESS:
4222 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4225 case RELOAD_FOR_OUTPUT_ADDRESS:
4226 used_in_set = &reload_reg_used_in_output_addr[opnum];
4229 case RELOAD_FOR_OUTADDR_ADDRESS:
4231 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4234 case RELOAD_FOR_OPERAND_ADDRESS:
4235 used_in_set = &reload_reg_used_in_op_addr;
4238 case RELOAD_FOR_OPADDR_ADDR:
4240 used_in_set = &reload_reg_used_in_op_addr_reload;
4243 case RELOAD_FOR_OTHER_ADDRESS:
4244 used_in_set = &reload_reg_used_in_other_addr;
4248 case RELOAD_FOR_INPUT:
4249 used_in_set = &reload_reg_used_in_input[opnum];
4252 case RELOAD_FOR_OUTPUT:
4253 used_in_set = &reload_reg_used_in_output[opnum];
4256 case RELOAD_FOR_INSN:
4257 used_in_set = &reload_reg_used_in_insn;
4262 /* We resolve conflicts with remaining reloads of the same type by
4263 excluding the intervals of reload registers by them from the
4264 interval of freed reload registers. Since we only keep track of
4265 one set of interval bounds, we might have to exclude somewhat
4266 more than what would be necessary if we used a HARD_REG_SET here.
4267 But this should only happen very infrequently, so there should
4268 be no reason to worry about it. */
4270 start_regno = regno;
4271 end_regno = regno + nregs;
4272 if (check_opnum || check_any)
4274 for (i = n_reloads - 1; i >= 0; i--)
4276 if (rld[i].when_needed == type
4277 && (check_any || rld[i].opnum == opnum)
4280 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4281 unsigned int conflict_end
4283 + hard_regno_nregs[conflict_start][rld[i].mode]);
4285 /* If there is an overlap with the first to-be-freed register,
4286 adjust the interval start. */
4287 if (conflict_start <= start_regno && conflict_end > start_regno)
4288 start_regno = conflict_end;
4289 /* Otherwise, if there is a conflict with one of the other
4290 to-be-freed registers, adjust the interval end. */
4291 if (conflict_start > start_regno && conflict_start < end_regno)
4292 end_regno = conflict_start;
4297 for (r = start_regno; r < end_regno; r++)
4298 CLEAR_HARD_REG_BIT (*used_in_set, r);
4301 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4302 specified by OPNUM and TYPE. */
4305 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4309 /* In use for a RELOAD_OTHER means it's not available for anything. */
4310 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4311 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4317 /* In use for anything means we can't use it for RELOAD_OTHER. */
4318 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4319 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4320 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4321 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4324 for (i = 0; i < reload_n_operands; i++)
4325 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4326 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4327 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4328 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4329 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4330 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4335 case RELOAD_FOR_INPUT:
4336 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4337 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4340 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4343 /* If it is used for some other input, can't use it. */
4344 for (i = 0; i < reload_n_operands; i++)
4345 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4348 /* If it is used in a later operand's address, can't use it. */
4349 for (i = opnum + 1; i < reload_n_operands; i++)
4350 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4351 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4356 case RELOAD_FOR_INPUT_ADDRESS:
4357 /* Can't use a register if it is used for an input address for this
4358 operand or used as an input in an earlier one. */
4359 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4360 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4363 for (i = 0; i < opnum; i++)
4364 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4369 case RELOAD_FOR_INPADDR_ADDRESS:
4370 /* Can't use a register if it is used for an input address
4371 for this operand or used as an input in an earlier
4373 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4376 for (i = 0; i < opnum; i++)
4377 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4382 case RELOAD_FOR_OUTPUT_ADDRESS:
4383 /* Can't use a register if it is used for an output address for this
4384 operand or used as an output in this or a later operand. Note
4385 that multiple output operands are emitted in reverse order, so
4386 the conflicting ones are those with lower indices. */
4387 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4390 for (i = 0; i <= opnum; i++)
4391 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4396 case RELOAD_FOR_OUTADDR_ADDRESS:
4397 /* Can't use a register if it is used for an output address
4398 for this operand or used as an output in this or a
4399 later operand. Note that multiple output operands are
4400 emitted in reverse order, so the conflicting ones are
4401 those with lower indices. */
4402 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4405 for (i = 0; i <= opnum; i++)
4406 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4411 case RELOAD_FOR_OPERAND_ADDRESS:
4412 for (i = 0; i < reload_n_operands; i++)
4413 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4416 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4417 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4419 case RELOAD_FOR_OPADDR_ADDR:
4420 for (i = 0; i < reload_n_operands; i++)
4421 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4424 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4426 case RELOAD_FOR_OUTPUT:
4427 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4428 outputs, or an operand address for this or an earlier output.
4429 Note that multiple output operands are emitted in reverse order,
4430 so the conflicting ones are those with higher indices. */
4431 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4434 for (i = 0; i < reload_n_operands; i++)
4435 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4438 for (i = opnum; i < reload_n_operands; i++)
4439 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4440 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4445 case RELOAD_FOR_INSN:
4446 for (i = 0; i < reload_n_operands; i++)
4447 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4448 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4451 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4452 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4454 case RELOAD_FOR_OTHER_ADDRESS:
4455 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4462 /* Return 1 if the value in reload reg REGNO, as used by a reload
4463 needed for the part of the insn specified by OPNUM and TYPE,
4464 is still available in REGNO at the end of the insn.
4466 We can assume that the reload reg was already tested for availability
4467 at the time it is needed, and we should not check this again,
4468 in case the reg has already been marked in use. */
4471 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4478 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4479 its value must reach the end. */
4482 /* If this use is for part of the insn,
4483 its value reaches if no subsequent part uses the same register.
4484 Just like the above function, don't try to do this with lots
4487 case RELOAD_FOR_OTHER_ADDRESS:
4488 /* Here we check for everything else, since these don't conflict
4489 with anything else and everything comes later. */
4491 for (i = 0; i < reload_n_operands; i++)
4492 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4493 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4494 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4496 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4497 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4500 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4501 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4502 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4503 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4505 case RELOAD_FOR_INPUT_ADDRESS:
4506 case RELOAD_FOR_INPADDR_ADDRESS:
4507 /* Similar, except that we check only for this and subsequent inputs
4508 and the address of only subsequent inputs and we do not need
4509 to check for RELOAD_OTHER objects since they are known not to
4512 for (i = opnum; i < reload_n_operands; i++)
4513 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4516 for (i = opnum + 1; i < reload_n_operands; i++)
4517 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4518 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4521 for (i = 0; i < reload_n_operands; i++)
4522 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4523 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4524 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4527 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4530 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4531 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4532 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4534 case RELOAD_FOR_INPUT:
4535 /* Similar to input address, except we start at the next operand for
4536 both input and input address and we do not check for
4537 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4540 for (i = opnum + 1; i < reload_n_operands; i++)
4541 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4546 /* ... fall through ... */
4548 case RELOAD_FOR_OPERAND_ADDRESS:
4549 /* Check outputs and their addresses. */
4551 for (i = 0; i < reload_n_operands; i++)
4552 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4553 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4554 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4557 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4559 case RELOAD_FOR_OPADDR_ADDR:
4560 for (i = 0; i < reload_n_operands; i++)
4561 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4562 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4566 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4567 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4568 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4570 case RELOAD_FOR_INSN:
4571 /* These conflict with other outputs with RELOAD_OTHER. So
4572 we need only check for output addresses. */
4574 opnum = reload_n_operands;
4576 /* ... fall through ... */
4578 case RELOAD_FOR_OUTPUT:
4579 case RELOAD_FOR_OUTPUT_ADDRESS:
4580 case RELOAD_FOR_OUTADDR_ADDRESS:
4581 /* We already know these can't conflict with a later output. So the
4582 only thing to check are later output addresses.
4583 Note that multiple output operands are emitted in reverse order,
4584 so the conflicting ones are those with lower indices. */
4585 for (i = 0; i < opnum; i++)
4586 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4587 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4597 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4600 This function uses the same algorithm as reload_reg_free_p above. */
4603 reloads_conflict (int r1, int r2)
4605 enum reload_type r1_type = rld[r1].when_needed;
4606 enum reload_type r2_type = rld[r2].when_needed;
4607 int r1_opnum = rld[r1].opnum;
4608 int r2_opnum = rld[r2].opnum;
4610 /* RELOAD_OTHER conflicts with everything. */
4611 if (r2_type == RELOAD_OTHER)
4614 /* Otherwise, check conflicts differently for each type. */
4618 case RELOAD_FOR_INPUT:
4619 return (r2_type == RELOAD_FOR_INSN
4620 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4621 || r2_type == RELOAD_FOR_OPADDR_ADDR
4622 || r2_type == RELOAD_FOR_INPUT
4623 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4624 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4625 && r2_opnum > r1_opnum));
4627 case RELOAD_FOR_INPUT_ADDRESS:
4628 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4629 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4631 case RELOAD_FOR_INPADDR_ADDRESS:
4632 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4633 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4635 case RELOAD_FOR_OUTPUT_ADDRESS:
4636 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4637 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4639 case RELOAD_FOR_OUTADDR_ADDRESS:
4640 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4641 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4643 case RELOAD_FOR_OPERAND_ADDRESS:
4644 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4645 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4647 case RELOAD_FOR_OPADDR_ADDR:
4648 return (r2_type == RELOAD_FOR_INPUT
4649 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4651 case RELOAD_FOR_OUTPUT:
4652 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4653 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4654 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4655 && r2_opnum >= r1_opnum));
4657 case RELOAD_FOR_INSN:
4658 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4659 || r2_type == RELOAD_FOR_INSN
4660 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4662 case RELOAD_FOR_OTHER_ADDRESS:
4663 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4673 /* Indexed by reload number, 1 if incoming value
4674 inherited from previous insns. */
4675 char reload_inherited[MAX_RELOADS];
4677 /* For an inherited reload, this is the insn the reload was inherited from,
4678 if we know it. Otherwise, this is 0. */
4679 rtx reload_inheritance_insn[MAX_RELOADS];
4681 /* If nonzero, this is a place to get the value of the reload,
4682 rather than using reload_in. */
4683 rtx reload_override_in[MAX_RELOADS];
4685 /* For each reload, the hard register number of the register used,
4686 or -1 if we did not need a register for this reload. */
4687 int reload_spill_index[MAX_RELOADS];
4689 /* Subroutine of free_for_value_p, used to check a single register.
4690 START_REGNO is the starting regno of the full reload register
4691 (possibly comprising multiple hard registers) that we are considering. */
4694 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4695 enum reload_type type, rtx value, rtx out,
4696 int reloadnum, int ignore_address_reloads)
4699 /* Set if we see an input reload that must not share its reload register
4700 with any new earlyclobber, but might otherwise share the reload
4701 register with an output or input-output reload. */
4702 int check_earlyclobber = 0;
4706 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4709 if (out == const0_rtx)
4715 /* We use some pseudo 'time' value to check if the lifetimes of the
4716 new register use would overlap with the one of a previous reload
4717 that is not read-only or uses a different value.
4718 The 'time' used doesn't have to be linear in any shape or form, just
4720 Some reload types use different 'buckets' for each operand.
4721 So there are MAX_RECOG_OPERANDS different time values for each
4723 We compute TIME1 as the time when the register for the prospective
4724 new reload ceases to be live, and TIME2 for each existing
4725 reload as the time when that the reload register of that reload
4727 Where there is little to be gained by exact lifetime calculations,
4728 we just make conservative assumptions, i.e. a longer lifetime;
4729 this is done in the 'default:' cases. */
4732 case RELOAD_FOR_OTHER_ADDRESS:
4733 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4734 time1 = copy ? 0 : 1;
4737 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4739 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4740 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4741 respectively, to the time values for these, we get distinct time
4742 values. To get distinct time values for each operand, we have to
4743 multiply opnum by at least three. We round that up to four because
4744 multiply by four is often cheaper. */
4745 case RELOAD_FOR_INPADDR_ADDRESS:
4746 time1 = opnum * 4 + 2;
4748 case RELOAD_FOR_INPUT_ADDRESS:
4749 time1 = opnum * 4 + 3;
4751 case RELOAD_FOR_INPUT:
4752 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4753 executes (inclusive). */
4754 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4756 case RELOAD_FOR_OPADDR_ADDR:
4758 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4759 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4761 case RELOAD_FOR_OPERAND_ADDRESS:
4762 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4764 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4766 case RELOAD_FOR_OUTADDR_ADDRESS:
4767 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4769 case RELOAD_FOR_OUTPUT_ADDRESS:
4770 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4773 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4776 for (i = 0; i < n_reloads; i++)
4778 rtx reg = rld[i].reg_rtx;
4779 if (reg && REG_P (reg)
4780 && ((unsigned) regno - true_regnum (reg)
4781 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4784 rtx other_input = rld[i].in;
4786 /* If the other reload loads the same input value, that
4787 will not cause a conflict only if it's loading it into
4788 the same register. */
4789 if (true_regnum (reg) != start_regno)
4790 other_input = NULL_RTX;
4791 if (! other_input || ! rtx_equal_p (other_input, value)
4792 || rld[i].out || out)
4795 switch (rld[i].when_needed)
4797 case RELOAD_FOR_OTHER_ADDRESS:
4800 case RELOAD_FOR_INPADDR_ADDRESS:
4801 /* find_reloads makes sure that a
4802 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4803 by at most one - the first -
4804 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4805 address reload is inherited, the address address reload
4806 goes away, so we can ignore this conflict. */
4807 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4808 && ignore_address_reloads
4809 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4810 Then the address address is still needed to store
4811 back the new address. */
4812 && ! rld[reloadnum].out)
4814 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4815 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4817 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4818 && ignore_address_reloads
4819 /* Unless we are reloading an auto_inc expression. */
4820 && ! rld[reloadnum].out)
4822 time2 = rld[i].opnum * 4 + 2;
4824 case RELOAD_FOR_INPUT_ADDRESS:
4825 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4826 && ignore_address_reloads
4827 && ! rld[reloadnum].out)
4829 time2 = rld[i].opnum * 4 + 3;
4831 case RELOAD_FOR_INPUT:
4832 time2 = rld[i].opnum * 4 + 4;
4833 check_earlyclobber = 1;
4835 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4836 == MAX_RECOG_OPERAND * 4 */
4837 case RELOAD_FOR_OPADDR_ADDR:
4838 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4839 && ignore_address_reloads
4840 && ! rld[reloadnum].out)
4842 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4844 case RELOAD_FOR_OPERAND_ADDRESS:
4845 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4846 check_earlyclobber = 1;
4848 case RELOAD_FOR_INSN:
4849 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4851 case RELOAD_FOR_OUTPUT:
4852 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4853 instruction is executed. */
4854 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4856 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4857 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4859 case RELOAD_FOR_OUTADDR_ADDRESS:
4860 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4861 && ignore_address_reloads
4862 && ! rld[reloadnum].out)
4864 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4866 case RELOAD_FOR_OUTPUT_ADDRESS:
4867 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4870 /* If there is no conflict in the input part, handle this
4871 like an output reload. */
4872 if (! rld[i].in || rtx_equal_p (other_input, value))
4874 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4875 /* Earlyclobbered outputs must conflict with inputs. */
4876 if (earlyclobber_operand_p (rld[i].out))
4877 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4882 /* RELOAD_OTHER might be live beyond instruction execution,
4883 but this is not obvious when we set time2 = 1. So check
4884 here if there might be a problem with the new reload
4885 clobbering the register used by the RELOAD_OTHER. */
4893 && (! rld[i].in || rld[i].out
4894 || ! rtx_equal_p (other_input, value)))
4895 || (out && rld[reloadnum].out_reg
4896 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4902 /* Earlyclobbered outputs must conflict with inputs. */
4903 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4909 /* Return 1 if the value in reload reg REGNO, as used by a reload
4910 needed for the part of the insn specified by OPNUM and TYPE,
4911 may be used to load VALUE into it.
4913 MODE is the mode in which the register is used, this is needed to
4914 determine how many hard regs to test.
4916 Other read-only reloads with the same value do not conflict
4917 unless OUT is nonzero and these other reloads have to live while
4918 output reloads live.
4919 If OUT is CONST0_RTX, this is a special case: it means that the
4920 test should not be for using register REGNO as reload register, but
4921 for copying from register REGNO into the reload register.
4923 RELOADNUM is the number of the reload we want to load this value for;
4924 a reload does not conflict with itself.
4926 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4927 reloads that load an address for the very reload we are considering.
4929 The caller has to make sure that there is no conflict with the return
4933 free_for_value_p (int regno, enum machine_mode mode, int opnum,
4934 enum reload_type type, rtx value, rtx out, int reloadnum,
4935 int ignore_address_reloads)
4937 int nregs = hard_regno_nregs[regno][mode];
4939 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4940 value, out, reloadnum,
4941 ignore_address_reloads))
4946 /* Return nonzero if the rtx X is invariant over the current function. */
4947 /* ??? Actually, the places where we use this expect exactly what
4948 * is tested here, and not everything that is function invariant. In
4949 * particular, the frame pointer and arg pointer are special cased;
4950 * pic_offset_table_rtx is not, and this will cause aborts when we
4951 * go to spill these things to memory. */
4954 function_invariant_p (rtx x)
4958 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
4960 if (GET_CODE (x) == PLUS
4961 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
4962 && CONSTANT_P (XEXP (x, 1)))
4967 /* Determine whether the reload reg X overlaps any rtx'es used for
4968 overriding inheritance. Return nonzero if so. */
4971 conflicts_with_override (rtx x)
4974 for (i = 0; i < n_reloads; i++)
4975 if (reload_override_in[i]
4976 && reg_overlap_mentioned_p (x, reload_override_in[i]))
4981 /* Give an error message saying we failed to find a reload for INSN,
4982 and clear out reload R. */
4984 failed_reload (rtx insn, int r)
4986 if (asm_noperands (PATTERN (insn)) < 0)
4987 /* It's the compiler's fault. */
4988 fatal_insn ("could not find a spill register", insn);
4990 /* It's the user's fault; the operand's mode and constraint
4991 don't match. Disable this reload so we don't crash in final. */
4992 error_for_asm (insn,
4993 "`asm' operand constraint incompatible with operand size");
4997 rld[r].optional = 1;
4998 rld[r].secondary_p = 1;
5001 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5002 for reload R. If it's valid, get an rtx for it. Return nonzero if
5005 set_reload_reg (int i, int r)
5008 rtx reg = spill_reg_rtx[i];
5010 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5011 spill_reg_rtx[i] = reg
5012 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5014 regno = true_regnum (reg);
5016 /* Detect when the reload reg can't hold the reload mode.
5017 This used to be one `if', but Sequent compiler can't handle that. */
5018 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5020 enum machine_mode test_mode = VOIDmode;
5022 test_mode = GET_MODE (rld[r].in);
5023 /* If rld[r].in has VOIDmode, it means we will load it
5024 in whatever mode the reload reg has: to wit, rld[r].mode.
5025 We have already tested that for validity. */
5026 /* Aside from that, we need to test that the expressions
5027 to reload from or into have modes which are valid for this
5028 reload register. Otherwise the reload insns would be invalid. */
5029 if (! (rld[r].in != 0 && test_mode != VOIDmode
5030 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5031 if (! (rld[r].out != 0
5032 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5034 /* The reg is OK. */
5037 /* Mark as in use for this insn the reload regs we use
5039 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5040 rld[r].when_needed, rld[r].mode);
5042 rld[r].reg_rtx = reg;
5043 reload_spill_index[r] = spill_regs[i];
5050 /* Find a spill register to use as a reload register for reload R.
5051 LAST_RELOAD is nonzero if this is the last reload for the insn being
5054 Set rld[R].reg_rtx to the register allocated.
5056 We return 1 if successful, or 0 if we couldn't find a spill reg and
5057 we didn't change anything. */
5060 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5065 /* If we put this reload ahead, thinking it is a group,
5066 then insist on finding a group. Otherwise we can grab a
5067 reg that some other reload needs.
5068 (That can happen when we have a 68000 DATA_OR_FP_REG
5069 which is a group of data regs or one fp reg.)
5070 We need not be so restrictive if there are no more reloads
5073 ??? Really it would be nicer to have smarter handling
5074 for that kind of reg class, where a problem like this is normal.
5075 Perhaps those classes should be avoided for reloading
5076 by use of more alternatives. */
5078 int force_group = rld[r].nregs > 1 && ! last_reload;
5080 /* If we want a single register and haven't yet found one,
5081 take any reg in the right class and not in use.
5082 If we want a consecutive group, here is where we look for it.
5084 We use two passes so we can first look for reload regs to
5085 reuse, which are already in use for other reloads in this insn,
5086 and only then use additional registers.
5087 I think that maximizing reuse is needed to make sure we don't
5088 run out of reload regs. Suppose we have three reloads, and
5089 reloads A and B can share regs. These need two regs.
5090 Suppose A and B are given different regs.
5091 That leaves none for C. */
5092 for (pass = 0; pass < 2; pass++)
5094 /* I is the index in spill_regs.
5095 We advance it round-robin between insns to use all spill regs
5096 equally, so that inherited reloads have a chance
5097 of leapfrogging each other. */
5101 for (count = 0; count < n_spills; count++)
5103 int class = (int) rld[r].class;
5109 regnum = spill_regs[i];
5111 if ((reload_reg_free_p (regnum, rld[r].opnum,
5114 /* We check reload_reg_used to make sure we
5115 don't clobber the return register. */
5116 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5117 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5118 rld[r].when_needed, rld[r].in,
5120 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5121 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5122 /* Look first for regs to share, then for unshared. But
5123 don't share regs used for inherited reloads; they are
5124 the ones we want to preserve. */
5126 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5128 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5131 int nr = hard_regno_nregs[regnum][rld[r].mode];
5132 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5133 (on 68000) got us two FP regs. If NR is 1,
5134 we would reject both of them. */
5137 /* If we need only one reg, we have already won. */
5140 /* But reject a single reg if we demand a group. */
5145 /* Otherwise check that as many consecutive regs as we need
5146 are available here. */
5149 int regno = regnum + nr - 1;
5150 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5151 && spill_reg_order[regno] >= 0
5152 && reload_reg_free_p (regno, rld[r].opnum,
5153 rld[r].when_needed)))
5162 /* If we found something on pass 1, omit pass 2. */
5163 if (count < n_spills)
5167 /* We should have found a spill register by now. */
5168 if (count >= n_spills)
5171 /* I is the index in SPILL_REG_RTX of the reload register we are to
5172 allocate. Get an rtx for it and find its register number. */
5174 return set_reload_reg (i, r);
5177 /* Initialize all the tables needed to allocate reload registers.
5178 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5179 is the array we use to restore the reg_rtx field for every reload. */
5182 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5186 for (i = 0; i < n_reloads; i++)
5187 rld[i].reg_rtx = save_reload_reg_rtx[i];
5189 memset (reload_inherited, 0, MAX_RELOADS);
5190 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5191 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5193 CLEAR_HARD_REG_SET (reload_reg_used);
5194 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5195 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5196 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5197 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5198 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5200 CLEAR_HARD_REG_SET (reg_used_in_insn);
5203 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5204 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5205 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5206 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5207 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5208 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5211 for (i = 0; i < reload_n_operands; i++)
5213 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5214 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5215 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5216 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5217 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5218 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5221 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5223 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5225 for (i = 0; i < n_reloads; i++)
5226 /* If we have already decided to use a certain register,
5227 don't use it in another way. */
5229 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5230 rld[i].when_needed, rld[i].mode);
5233 /* Assign hard reg targets for the pseudo-registers we must reload
5234 into hard regs for this insn.
5235 Also output the instructions to copy them in and out of the hard regs.
5237 For machines with register classes, we are responsible for
5238 finding a reload reg in the proper class. */
5241 choose_reload_regs (struct insn_chain *chain)
5243 rtx insn = chain->insn;
5245 unsigned int max_group_size = 1;
5246 enum reg_class group_class = NO_REGS;
5247 int pass, win, inheritance;
5249 rtx save_reload_reg_rtx[MAX_RELOADS];
5251 /* In order to be certain of getting the registers we need,
5252 we must sort the reloads into order of increasing register class.
5253 Then our grabbing of reload registers will parallel the process
5254 that provided the reload registers.
5256 Also note whether any of the reloads wants a consecutive group of regs.
5257 If so, record the maximum size of the group desired and what
5258 register class contains all the groups needed by this insn. */
5260 for (j = 0; j < n_reloads; j++)
5262 reload_order[j] = j;
5263 reload_spill_index[j] = -1;
5265 if (rld[j].nregs > 1)
5267 max_group_size = MAX (rld[j].nregs, max_group_size);
5269 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5272 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5276 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5278 /* If -O, try first with inheritance, then turning it off.
5279 If not -O, don't do inheritance.
5280 Using inheritance when not optimizing leads to paradoxes
5281 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5282 because one side of the comparison might be inherited. */
5284 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5286 choose_reload_regs_init (chain, save_reload_reg_rtx);
5288 /* Process the reloads in order of preference just found.
5289 Beyond this point, subregs can be found in reload_reg_rtx.
5291 This used to look for an existing reloaded home for all of the
5292 reloads, and only then perform any new reloads. But that could lose
5293 if the reloads were done out of reg-class order because a later
5294 reload with a looser constraint might have an old home in a register
5295 needed by an earlier reload with a tighter constraint.
5297 To solve this, we make two passes over the reloads, in the order
5298 described above. In the first pass we try to inherit a reload
5299 from a previous insn. If there is a later reload that needs a
5300 class that is a proper subset of the class being processed, we must
5301 also allocate a spill register during the first pass.
5303 Then make a second pass over the reloads to allocate any reloads
5304 that haven't been given registers yet. */
5306 for (j = 0; j < n_reloads; j++)
5308 int r = reload_order[j];
5309 rtx search_equiv = NULL_RTX;
5311 /* Ignore reloads that got marked inoperative. */
5312 if (rld[r].out == 0 && rld[r].in == 0
5313 && ! rld[r].secondary_p)
5316 /* If find_reloads chose to use reload_in or reload_out as a reload
5317 register, we don't need to chose one. Otherwise, try even if it
5318 found one since we might save an insn if we find the value lying
5320 Try also when reload_in is a pseudo without a hard reg. */
5321 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5322 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5323 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5324 && !MEM_P (rld[r].in)
5325 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5328 #if 0 /* No longer needed for correct operation.
5329 It might give better code, or might not; worth an experiment? */
5330 /* If this is an optional reload, we can't inherit from earlier insns
5331 until we are sure that any non-optional reloads have been allocated.
5332 The following code takes advantage of the fact that optional reloads
5333 are at the end of reload_order. */
5334 if (rld[r].optional != 0)
5335 for (i = 0; i < j; i++)
5336 if ((rld[reload_order[i]].out != 0
5337 || rld[reload_order[i]].in != 0
5338 || rld[reload_order[i]].secondary_p)
5339 && ! rld[reload_order[i]].optional
5340 && rld[reload_order[i]].reg_rtx == 0)
5341 allocate_reload_reg (chain, reload_order[i], 0);
5344 /* First see if this pseudo is already available as reloaded
5345 for a previous insn. We cannot try to inherit for reloads
5346 that are smaller than the maximum number of registers needed
5347 for groups unless the register we would allocate cannot be used
5350 We could check here to see if this is a secondary reload for
5351 an object that is already in a register of the desired class.
5352 This would avoid the need for the secondary reload register.
5353 But this is complex because we can't easily determine what
5354 objects might want to be loaded via this reload. So let a
5355 register be allocated here. In `emit_reload_insns' we suppress
5356 one of the loads in the case described above. */
5362 enum machine_mode mode = VOIDmode;
5366 else if (REG_P (rld[r].in))
5368 regno = REGNO (rld[r].in);
5369 mode = GET_MODE (rld[r].in);
5371 else if (REG_P (rld[r].in_reg))
5373 regno = REGNO (rld[r].in_reg);
5374 mode = GET_MODE (rld[r].in_reg);
5376 else if (GET_CODE (rld[r].in_reg) == SUBREG
5377 && REG_P (SUBREG_REG (rld[r].in_reg)))
5379 byte = SUBREG_BYTE (rld[r].in_reg);
5380 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5381 if (regno < FIRST_PSEUDO_REGISTER)
5382 regno = subreg_regno (rld[r].in_reg);
5383 mode = GET_MODE (rld[r].in_reg);
5386 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5387 || GET_CODE (rld[r].in_reg) == PRE_DEC
5388 || GET_CODE (rld[r].in_reg) == POST_INC
5389 || GET_CODE (rld[r].in_reg) == POST_DEC)
5390 && REG_P (XEXP (rld[r].in_reg, 0)))
5392 regno = REGNO (XEXP (rld[r].in_reg, 0));
5393 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5394 rld[r].out = rld[r].in;
5398 /* This won't work, since REGNO can be a pseudo reg number.
5399 Also, it takes much more hair to keep track of all the things
5400 that can invalidate an inherited reload of part of a pseudoreg. */
5401 else if (GET_CODE (rld[r].in) == SUBREG
5402 && REG_P (SUBREG_REG (rld[r].in)))
5403 regno = subreg_regno (rld[r].in);
5406 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5408 enum reg_class class = rld[r].class, last_class;
5409 rtx last_reg = reg_last_reload_reg[regno];
5410 enum machine_mode need_mode;
5412 i = REGNO (last_reg);
5413 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5414 last_class = REGNO_REG_CLASS (i);
5420 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5421 GET_MODE_CLASS (mode));
5424 #ifdef CANNOT_CHANGE_MODE_CLASS
5425 (!REG_CANNOT_CHANGE_MODE_P (i, GET_MODE (last_reg),
5429 (GET_MODE_SIZE (GET_MODE (last_reg))
5430 >= GET_MODE_SIZE (need_mode))
5431 #ifdef CANNOT_CHANGE_MODE_CLASS
5434 && reg_reloaded_contents[i] == regno
5435 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5436 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5437 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5438 /* Even if we can't use this register as a reload
5439 register, we might use it for reload_override_in,
5440 if copying it to the desired class is cheap
5442 || ((REGISTER_MOVE_COST (mode, last_class, class)
5443 < MEMORY_MOVE_COST (mode, class, 1))
5444 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5445 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5449 #ifdef SECONDARY_MEMORY_NEEDED
5450 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5455 && (rld[r].nregs == max_group_size
5456 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5458 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5459 rld[r].when_needed, rld[r].in,
5462 /* If a group is needed, verify that all the subsequent
5463 registers still have their values intact. */
5464 int nr = hard_regno_nregs[i][rld[r].mode];
5467 for (k = 1; k < nr; k++)
5468 if (reg_reloaded_contents[i + k] != regno
5469 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5477 last_reg = (GET_MODE (last_reg) == mode
5478 ? last_reg : gen_rtx_REG (mode, i));
5481 for (k = 0; k < nr; k++)
5482 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5485 /* We found a register that contains the
5486 value we need. If this register is the
5487 same as an `earlyclobber' operand of the
5488 current insn, just mark it as a place to
5489 reload from since we can't use it as the
5490 reload register itself. */
5492 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5493 if (reg_overlap_mentioned_for_reload_p
5494 (reg_last_reload_reg[regno],
5495 reload_earlyclobbers[i1]))
5498 if (i1 != n_earlyclobbers
5499 || ! (free_for_value_p (i, rld[r].mode,
5501 rld[r].when_needed, rld[r].in,
5503 /* Don't use it if we'd clobber a pseudo reg. */
5504 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5506 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5507 /* Don't clobber the frame pointer. */
5508 || (i == HARD_FRAME_POINTER_REGNUM
5509 && frame_pointer_needed
5511 /* Don't really use the inherited spill reg
5512 if we need it wider than we've got it. */
5513 || (GET_MODE_SIZE (rld[r].mode)
5514 > GET_MODE_SIZE (mode))
5517 /* If find_reloads chose reload_out as reload
5518 register, stay with it - that leaves the
5519 inherited register for subsequent reloads. */
5520 || (rld[r].out && rld[r].reg_rtx
5521 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5523 if (! rld[r].optional)
5525 reload_override_in[r] = last_reg;
5526 reload_inheritance_insn[r]
5527 = reg_reloaded_insn[i];
5533 /* We can use this as a reload reg. */
5534 /* Mark the register as in use for this part of
5536 mark_reload_reg_in_use (i,
5540 rld[r].reg_rtx = last_reg;
5541 reload_inherited[r] = 1;
5542 reload_inheritance_insn[r]
5543 = reg_reloaded_insn[i];
5544 reload_spill_index[r] = i;
5545 for (k = 0; k < nr; k++)
5546 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5554 /* Here's another way to see if the value is already lying around. */
5557 && ! reload_inherited[r]
5559 && (CONSTANT_P (rld[r].in)
5560 || GET_CODE (rld[r].in) == PLUS
5561 || REG_P (rld[r].in)
5562 || MEM_P (rld[r].in))
5563 && (rld[r].nregs == max_group_size
5564 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5565 search_equiv = rld[r].in;
5566 /* If this is an output reload from a simple move insn, look
5567 if an equivalence for the input is available. */
5568 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5570 rtx set = single_set (insn);
5573 && rtx_equal_p (rld[r].out, SET_DEST (set))
5574 && CONSTANT_P (SET_SRC (set)))
5575 search_equiv = SET_SRC (set);
5581 = find_equiv_reg (search_equiv, insn, rld[r].class,
5582 -1, NULL, 0, rld[r].mode);
5588 regno = REGNO (equiv);
5591 /* This must be a SUBREG of a hard register.
5592 Make a new REG since this might be used in an
5593 address and not all machines support SUBREGs
5595 gcc_assert (GET_CODE (equiv) == SUBREG);
5596 regno = subreg_regno (equiv);
5597 equiv = gen_rtx_REG (rld[r].mode, regno);
5601 /* If we found a spill reg, reject it unless it is free
5602 and of the desired class. */
5606 int bad_for_class = 0;
5607 int max_regno = regno + rld[r].nregs;
5609 for (i = regno; i < max_regno; i++)
5611 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5613 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5618 && ! free_for_value_p (regno, rld[r].mode,
5619 rld[r].opnum, rld[r].when_needed,
5620 rld[r].in, rld[r].out, r, 1))
5625 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5628 /* We found a register that contains the value we need.
5629 If this register is the same as an `earlyclobber' operand
5630 of the current insn, just mark it as a place to reload from
5631 since we can't use it as the reload register itself. */
5634 for (i = 0; i < n_earlyclobbers; i++)
5635 if (reg_overlap_mentioned_for_reload_p (equiv,
5636 reload_earlyclobbers[i]))
5638 if (! rld[r].optional)
5639 reload_override_in[r] = equiv;
5644 /* If the equiv register we have found is explicitly clobbered
5645 in the current insn, it depends on the reload type if we
5646 can use it, use it for reload_override_in, or not at all.
5647 In particular, we then can't use EQUIV for a
5648 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5652 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5653 switch (rld[r].when_needed)
5655 case RELOAD_FOR_OTHER_ADDRESS:
5656 case RELOAD_FOR_INPADDR_ADDRESS:
5657 case RELOAD_FOR_INPUT_ADDRESS:
5658 case RELOAD_FOR_OPADDR_ADDR:
5661 case RELOAD_FOR_INPUT:
5662 case RELOAD_FOR_OPERAND_ADDRESS:
5663 if (! rld[r].optional)
5664 reload_override_in[r] = equiv;
5670 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5671 switch (rld[r].when_needed)
5673 case RELOAD_FOR_OTHER_ADDRESS:
5674 case RELOAD_FOR_INPADDR_ADDRESS:
5675 case RELOAD_FOR_INPUT_ADDRESS:
5676 case RELOAD_FOR_OPADDR_ADDR:
5677 case RELOAD_FOR_OPERAND_ADDRESS:
5678 case RELOAD_FOR_INPUT:
5681 if (! rld[r].optional)
5682 reload_override_in[r] = equiv;
5690 /* If we found an equivalent reg, say no code need be generated
5691 to load it, and use it as our reload reg. */
5693 && (regno != HARD_FRAME_POINTER_REGNUM
5694 || !frame_pointer_needed))
5696 int nr = hard_regno_nregs[regno][rld[r].mode];
5698 rld[r].reg_rtx = equiv;
5699 reload_inherited[r] = 1;
5701 /* If reg_reloaded_valid is not set for this register,
5702 there might be a stale spill_reg_store lying around.
5703 We must clear it, since otherwise emit_reload_insns
5704 might delete the store. */
5705 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5706 spill_reg_store[regno] = NULL_RTX;
5707 /* If any of the hard registers in EQUIV are spill
5708 registers, mark them as in use for this insn. */
5709 for (k = 0; k < nr; k++)
5711 i = spill_reg_order[regno + k];
5714 mark_reload_reg_in_use (regno, rld[r].opnum,
5717 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5724 /* If we found a register to use already, or if this is an optional
5725 reload, we are done. */
5726 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5730 /* No longer needed for correct operation. Might or might
5731 not give better code on the average. Want to experiment? */
5733 /* See if there is a later reload that has a class different from our
5734 class that intersects our class or that requires less register
5735 than our reload. If so, we must allocate a register to this
5736 reload now, since that reload might inherit a previous reload
5737 and take the only available register in our class. Don't do this
5738 for optional reloads since they will force all previous reloads
5739 to be allocated. Also don't do this for reloads that have been
5742 for (i = j + 1; i < n_reloads; i++)
5744 int s = reload_order[i];
5746 if ((rld[s].in == 0 && rld[s].out == 0
5747 && ! rld[s].secondary_p)
5751 if ((rld[s].class != rld[r].class
5752 && reg_classes_intersect_p (rld[r].class,
5754 || rld[s].nregs < rld[r].nregs)
5761 allocate_reload_reg (chain, r, j == n_reloads - 1);
5765 /* Now allocate reload registers for anything non-optional that
5766 didn't get one yet. */
5767 for (j = 0; j < n_reloads; j++)
5769 int r = reload_order[j];
5771 /* Ignore reloads that got marked inoperative. */
5772 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5775 /* Skip reloads that already have a register allocated or are
5777 if (rld[r].reg_rtx != 0 || rld[r].optional)
5780 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5784 /* If that loop got all the way, we have won. */
5791 /* Loop around and try without any inheritance. */
5796 /* First undo everything done by the failed attempt
5797 to allocate with inheritance. */
5798 choose_reload_regs_init (chain, save_reload_reg_rtx);
5800 /* Some sanity tests to verify that the reloads found in the first
5801 pass are identical to the ones we have now. */
5802 gcc_assert (chain->n_reloads == n_reloads);
5804 for (i = 0; i < n_reloads; i++)
5806 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5808 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5809 for (j = 0; j < n_spills; j++)
5810 if (spill_regs[j] == chain->rld[i].regno)
5811 if (! set_reload_reg (j, i))
5812 failed_reload (chain->insn, i);
5816 /* If we thought we could inherit a reload, because it seemed that
5817 nothing else wanted the same reload register earlier in the insn,
5818 verify that assumption, now that all reloads have been assigned.
5819 Likewise for reloads where reload_override_in has been set. */
5821 /* If doing expensive optimizations, do one preliminary pass that doesn't
5822 cancel any inheritance, but removes reloads that have been needed only
5823 for reloads that we know can be inherited. */
5824 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5826 for (j = 0; j < n_reloads; j++)
5828 int r = reload_order[j];
5830 if (reload_inherited[r] && rld[r].reg_rtx)
5831 check_reg = rld[r].reg_rtx;
5832 else if (reload_override_in[r]
5833 && (REG_P (reload_override_in[r])
5834 || GET_CODE (reload_override_in[r]) == SUBREG))
5835 check_reg = reload_override_in[r];
5838 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5839 rld[r].opnum, rld[r].when_needed, rld[r].in,
5840 (reload_inherited[r]
5841 ? rld[r].out : const0_rtx),
5846 reload_inherited[r] = 0;
5847 reload_override_in[r] = 0;
5849 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5850 reload_override_in, then we do not need its related
5851 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5852 likewise for other reload types.
5853 We handle this by removing a reload when its only replacement
5854 is mentioned in reload_in of the reload we are going to inherit.
5855 A special case are auto_inc expressions; even if the input is
5856 inherited, we still need the address for the output. We can
5857 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5858 If we succeeded removing some reload and we are doing a preliminary
5859 pass just to remove such reloads, make another pass, since the
5860 removal of one reload might allow us to inherit another one. */
5862 && rld[r].out != rld[r].in
5863 && remove_address_replacements (rld[r].in) && pass)
5868 /* Now that reload_override_in is known valid,
5869 actually override reload_in. */
5870 for (j = 0; j < n_reloads; j++)
5871 if (reload_override_in[j])
5872 rld[j].in = reload_override_in[j];
5874 /* If this reload won't be done because it has been canceled or is
5875 optional and not inherited, clear reload_reg_rtx so other
5876 routines (such as subst_reloads) don't get confused. */
5877 for (j = 0; j < n_reloads; j++)
5878 if (rld[j].reg_rtx != 0
5879 && ((rld[j].optional && ! reload_inherited[j])
5880 || (rld[j].in == 0 && rld[j].out == 0
5881 && ! rld[j].secondary_p)))
5883 int regno = true_regnum (rld[j].reg_rtx);
5885 if (spill_reg_order[regno] >= 0)
5886 clear_reload_reg_in_use (regno, rld[j].opnum,
5887 rld[j].when_needed, rld[j].mode);
5889 reload_spill_index[j] = -1;
5892 /* Record which pseudos and which spill regs have output reloads. */
5893 for (j = 0; j < n_reloads; j++)
5895 int r = reload_order[j];
5897 i = reload_spill_index[r];
5899 /* I is nonneg if this reload uses a register.
5900 If rld[r].reg_rtx is 0, this is an optional reload
5901 that we opted to ignore. */
5902 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
5903 && rld[r].reg_rtx != 0)
5905 int nregno = REGNO (rld[r].out_reg);
5908 if (nregno < FIRST_PSEUDO_REGISTER)
5909 nr = hard_regno_nregs[nregno][rld[r].mode];
5912 reg_has_output_reload[nregno + nr] = 1;
5916 nr = hard_regno_nregs[i][rld[r].mode];
5918 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5921 gcc_assert (rld[r].when_needed == RELOAD_OTHER
5922 || rld[r].when_needed == RELOAD_FOR_OUTPUT
5923 || rld[r].when_needed == RELOAD_FOR_INSN);
5928 /* Deallocate the reload register for reload R. This is called from
5929 remove_address_replacements. */
5932 deallocate_reload_reg (int r)
5936 if (! rld[r].reg_rtx)
5938 regno = true_regnum (rld[r].reg_rtx);
5940 if (spill_reg_order[regno] >= 0)
5941 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5943 reload_spill_index[r] = -1;
5946 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
5947 reloads of the same item for fear that we might not have enough reload
5948 registers. However, normally they will get the same reload register
5949 and hence actually need not be loaded twice.
5951 Here we check for the most common case of this phenomenon: when we have
5952 a number of reloads for the same object, each of which were allocated
5953 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5954 reload, and is not modified in the insn itself. If we find such,
5955 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5956 This will not increase the number of spill registers needed and will
5957 prevent redundant code. */
5960 merge_assigned_reloads (rtx insn)
5964 /* Scan all the reloads looking for ones that only load values and
5965 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5966 assigned and not modified by INSN. */
5968 for (i = 0; i < n_reloads; i++)
5970 int conflicting_input = 0;
5971 int max_input_address_opnum = -1;
5972 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
5974 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
5975 || rld[i].out != 0 || rld[i].reg_rtx == 0
5976 || reg_set_p (rld[i].reg_rtx, insn))
5979 /* Look at all other reloads. Ensure that the only use of this
5980 reload_reg_rtx is in a reload that just loads the same value
5981 as we do. Note that any secondary reloads must be of the identical
5982 class since the values, modes, and result registers are the
5983 same, so we need not do anything with any secondary reloads. */
5985 for (j = 0; j < n_reloads; j++)
5987 if (i == j || rld[j].reg_rtx == 0
5988 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
5992 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
5993 && rld[j].opnum > max_input_address_opnum)
5994 max_input_address_opnum = rld[j].opnum;
5996 /* If the reload regs aren't exactly the same (e.g, different modes)
5997 or if the values are different, we can't merge this reload.
5998 But if it is an input reload, we might still merge
5999 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6001 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6002 || rld[j].out != 0 || rld[j].in == 0
6003 || ! rtx_equal_p (rld[i].in, rld[j].in))
6005 if (rld[j].when_needed != RELOAD_FOR_INPUT
6006 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6007 || rld[i].opnum > rld[j].opnum)
6008 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6010 conflicting_input = 1;
6011 if (min_conflicting_input_opnum > rld[j].opnum)
6012 min_conflicting_input_opnum = rld[j].opnum;
6016 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6017 we, in fact, found any matching reloads. */
6020 && max_input_address_opnum <= min_conflicting_input_opnum)
6022 for (j = 0; j < n_reloads; j++)
6023 if (i != j && rld[j].reg_rtx != 0
6024 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6025 && (! conflicting_input
6026 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6027 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6029 rld[i].when_needed = RELOAD_OTHER;
6031 reload_spill_index[j] = -1;
6032 transfer_replacements (i, j);
6035 /* If this is now RELOAD_OTHER, look for any reloads that load
6036 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6037 if they were for inputs, RELOAD_OTHER for outputs. Note that
6038 this test is equivalent to looking for reloads for this operand
6040 /* We must take special care when there are two or more reloads to
6041 be merged and a RELOAD_FOR_OUTPUT_ADDRESS reload that loads the
6042 same value or a part of it; we must not change its type if there
6043 is a conflicting input. */
6045 if (rld[i].when_needed == RELOAD_OTHER)
6046 for (j = 0; j < n_reloads; j++)
6048 && rld[j].when_needed != RELOAD_OTHER
6049 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6050 && (! conflicting_input
6051 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6052 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6053 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6059 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6060 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6061 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6063 /* Check to see if we accidentally converted two reloads
6064 that use the same reload register with different inputs
6065 to the same type. If so, the resulting code won't work,
6068 for (k = 0; k < j; k++)
6069 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6070 || rld[k].when_needed != rld[j].when_needed
6071 || !rtx_equal_p (rld[k].reg_rtx,
6073 || rtx_equal_p (rld[k].in,
6080 /* These arrays are filled by emit_reload_insns and its subroutines. */
6081 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6082 static rtx other_input_address_reload_insns = 0;
6083 static rtx other_input_reload_insns = 0;
6084 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6085 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6086 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6087 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6088 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6089 static rtx operand_reload_insns = 0;
6090 static rtx other_operand_reload_insns = 0;
6091 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6093 /* Values to be put in spill_reg_store are put here first. */
6094 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6095 static HARD_REG_SET reg_reloaded_died;
6097 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6098 has the number J. OLD contains the value to be used as input. */
6101 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6104 rtx insn = chain->insn;
6105 rtx reloadreg = rl->reg_rtx;
6106 rtx oldequiv_reg = 0;
6109 enum machine_mode mode;
6112 /* Determine the mode to reload in.
6113 This is very tricky because we have three to choose from.
6114 There is the mode the insn operand wants (rl->inmode).
6115 There is the mode of the reload register RELOADREG.
6116 There is the intrinsic mode of the operand, which we could find
6117 by stripping some SUBREGs.
6118 It turns out that RELOADREG's mode is irrelevant:
6119 we can change that arbitrarily.
6121 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6122 then the reload reg may not support QImode moves, so use SImode.
6123 If foo is in memory due to spilling a pseudo reg, this is safe,
6124 because the QImode value is in the least significant part of a
6125 slot big enough for a SImode. If foo is some other sort of
6126 memory reference, then it is impossible to reload this case,
6127 so previous passes had better make sure this never happens.
6129 Then consider a one-word union which has SImode and one of its
6130 members is a float, being fetched as (SUBREG:SF union:SI).
6131 We must fetch that as SFmode because we could be loading into
6132 a float-only register. In this case OLD's mode is correct.
6134 Consider an immediate integer: it has VOIDmode. Here we need
6135 to get a mode from something else.
6137 In some cases, there is a fourth mode, the operand's
6138 containing mode. If the insn specifies a containing mode for
6139 this operand, it overrides all others.
6141 I am not sure whether the algorithm here is always right,
6142 but it does the right things in those cases. */
6144 mode = GET_MODE (old);
6145 if (mode == VOIDmode)
6148 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6149 /* If we need a secondary register for this operation, see if
6150 the value is already in a register in that class. Don't
6151 do this if the secondary register will be used as a scratch
6154 if (rl->secondary_in_reload >= 0
6155 && rl->secondary_in_icode == CODE_FOR_nothing
6158 = find_equiv_reg (old, insn,
6159 rld[rl->secondary_in_reload].class,
6163 /* If reloading from memory, see if there is a register
6164 that already holds the same value. If so, reload from there.
6165 We can pass 0 as the reload_reg_p argument because
6166 any other reload has either already been emitted,
6167 in which case find_equiv_reg will see the reload-insn,
6168 or has yet to be emitted, in which case it doesn't matter
6169 because we will use this equiv reg right away. */
6171 if (oldequiv == 0 && optimize
6174 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6175 && reg_renumber[REGNO (old)] < 0)))
6176 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6180 unsigned int regno = true_regnum (oldequiv);
6182 /* Don't use OLDEQUIV if any other reload changes it at an
6183 earlier stage of this insn or at this stage. */
6184 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6185 rl->in, const0_rtx, j, 0))
6188 /* If it is no cheaper to copy from OLDEQUIV into the
6189 reload register than it would be to move from memory,
6190 don't use it. Likewise, if we need a secondary register
6194 && (((enum reg_class) REGNO_REG_CLASS (regno) != rl->class
6195 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6197 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6198 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6199 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6203 #ifdef SECONDARY_MEMORY_NEEDED
6204 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6212 /* delete_output_reload is only invoked properly if old contains
6213 the original pseudo register. Since this is replaced with a
6214 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6215 find the pseudo in RELOAD_IN_REG. */
6217 && reload_override_in[j]
6218 && REG_P (rl->in_reg))
6225 else if (REG_P (oldequiv))
6226 oldequiv_reg = oldequiv;
6227 else if (GET_CODE (oldequiv) == SUBREG)
6228 oldequiv_reg = SUBREG_REG (oldequiv);
6230 /* If we are reloading from a register that was recently stored in
6231 with an output-reload, see if we can prove there was
6232 actually no need to store the old value in it. */
6234 if (optimize && REG_P (oldequiv)
6235 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6236 && spill_reg_store[REGNO (oldequiv)]
6238 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6239 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6241 delete_output_reload (insn, j, REGNO (oldequiv));
6243 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6244 then load RELOADREG from OLDEQUIV. Note that we cannot use
6245 gen_lowpart_common since it can do the wrong thing when
6246 RELOADREG has a multi-word mode. Note that RELOADREG
6247 must always be a REG here. */
6249 if (GET_MODE (reloadreg) != mode)
6250 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6251 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6252 oldequiv = SUBREG_REG (oldequiv);
6253 if (GET_MODE (oldequiv) != VOIDmode
6254 && mode != GET_MODE (oldequiv))
6255 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6257 /* Switch to the right place to emit the reload insns. */
6258 switch (rl->when_needed)
6261 where = &other_input_reload_insns;
6263 case RELOAD_FOR_INPUT:
6264 where = &input_reload_insns[rl->opnum];
6266 case RELOAD_FOR_INPUT_ADDRESS:
6267 where = &input_address_reload_insns[rl->opnum];
6269 case RELOAD_FOR_INPADDR_ADDRESS:
6270 where = &inpaddr_address_reload_insns[rl->opnum];
6272 case RELOAD_FOR_OUTPUT_ADDRESS:
6273 where = &output_address_reload_insns[rl->opnum];
6275 case RELOAD_FOR_OUTADDR_ADDRESS:
6276 where = &outaddr_address_reload_insns[rl->opnum];
6278 case RELOAD_FOR_OPERAND_ADDRESS:
6279 where = &operand_reload_insns;
6281 case RELOAD_FOR_OPADDR_ADDR:
6282 where = &other_operand_reload_insns;
6284 case RELOAD_FOR_OTHER_ADDRESS:
6285 where = &other_input_address_reload_insns;
6291 push_to_sequence (*where);
6293 /* Auto-increment addresses must be reloaded in a special way. */
6294 if (rl->out && ! rl->out_reg)
6296 /* We are not going to bother supporting the case where a
6297 incremented register can't be copied directly from
6298 OLDEQUIV since this seems highly unlikely. */
6299 gcc_assert (rl->secondary_in_reload < 0);
6301 if (reload_inherited[j])
6302 oldequiv = reloadreg;
6304 old = XEXP (rl->in_reg, 0);
6306 if (optimize && REG_P (oldequiv)
6307 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6308 && spill_reg_store[REGNO (oldequiv)]
6310 && (dead_or_set_p (insn,
6311 spill_reg_stored_to[REGNO (oldequiv)])
6312 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6314 delete_output_reload (insn, j, REGNO (oldequiv));
6316 /* Prevent normal processing of this reload. */
6318 /* Output a special code sequence for this case. */
6319 new_spill_reg_store[REGNO (reloadreg)]
6320 = inc_for_reload (reloadreg, oldequiv, rl->out,
6324 /* If we are reloading a pseudo-register that was set by the previous
6325 insn, see if we can get rid of that pseudo-register entirely
6326 by redirecting the previous insn into our reload register. */
6328 else if (optimize && REG_P (old)
6329 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6330 && dead_or_set_p (insn, old)
6331 /* This is unsafe if some other reload
6332 uses the same reg first. */
6333 && ! conflicts_with_override (reloadreg)
6334 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6335 rl->when_needed, old, rl->out, j, 0))
6337 rtx temp = PREV_INSN (insn);
6338 while (temp && NOTE_P (temp))
6339 temp = PREV_INSN (temp);
6341 && NONJUMP_INSN_P (temp)
6342 && GET_CODE (PATTERN (temp)) == SET
6343 && SET_DEST (PATTERN (temp)) == old
6344 /* Make sure we can access insn_operand_constraint. */
6345 && asm_noperands (PATTERN (temp)) < 0
6346 /* This is unsafe if operand occurs more than once in current
6347 insn. Perhaps some occurrences aren't reloaded. */
6348 && count_occurrences (PATTERN (insn), old, 0) == 1)
6350 rtx old = SET_DEST (PATTERN (temp));
6351 /* Store into the reload register instead of the pseudo. */
6352 SET_DEST (PATTERN (temp)) = reloadreg;
6354 /* Verify that resulting insn is valid. */
6355 extract_insn (temp);
6356 if (constrain_operands (1))
6358 /* If the previous insn is an output reload, the source is
6359 a reload register, and its spill_reg_store entry will
6360 contain the previous destination. This is now
6362 if (REG_P (SET_SRC (PATTERN (temp)))
6363 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6365 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6366 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6369 /* If these are the only uses of the pseudo reg,
6370 pretend for GDB it lives in the reload reg we used. */
6371 if (REG_N_DEATHS (REGNO (old)) == 1
6372 && REG_N_SETS (REGNO (old)) == 1)
6374 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6375 alter_reg (REGNO (old), -1);
6381 SET_DEST (PATTERN (temp)) = old;
6386 /* We can't do that, so output an insn to load RELOADREG. */
6388 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6389 /* If we have a secondary reload, pick up the secondary register
6390 and icode, if any. If OLDEQUIV and OLD are different or
6391 if this is an in-out reload, recompute whether or not we
6392 still need a secondary register and what the icode should
6393 be. If we still need a secondary register and the class or
6394 icode is different, go back to reloading from OLD if using
6395 OLDEQUIV means that we got the wrong type of register. We
6396 cannot have different class or icode due to an in-out reload
6397 because we don't make such reloads when both the input and
6398 output need secondary reload registers. */
6400 if (! special && rl->secondary_in_reload >= 0)
6402 rtx second_reload_reg = 0;
6403 int secondary_reload = rl->secondary_in_reload;
6404 rtx real_oldequiv = oldequiv;
6407 enum insn_code icode;
6409 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6410 and similarly for OLD.
6411 See comments in get_secondary_reload in reload.c. */
6412 /* If it is a pseudo that cannot be replaced with its
6413 equivalent MEM, we must fall back to reload_in, which
6414 will have all the necessary substitutions registered.
6415 Likewise for a pseudo that can't be replaced with its
6416 equivalent constant.
6418 Take extra care for subregs of such pseudos. Note that
6419 we cannot use reg_equiv_mem in this case because it is
6420 not in the right mode. */
6423 if (GET_CODE (tmp) == SUBREG)
6424 tmp = SUBREG_REG (tmp);
6426 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6427 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6428 || reg_equiv_constant[REGNO (tmp)] != 0))
6430 if (! reg_equiv_mem[REGNO (tmp)]
6431 || num_not_at_initial_offset
6432 || GET_CODE (oldequiv) == SUBREG)
6433 real_oldequiv = rl->in;
6435 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6439 if (GET_CODE (tmp) == SUBREG)
6440 tmp = SUBREG_REG (tmp);
6442 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6443 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6444 || reg_equiv_constant[REGNO (tmp)] != 0))
6446 if (! reg_equiv_mem[REGNO (tmp)]
6447 || num_not_at_initial_offset
6448 || GET_CODE (old) == SUBREG)
6451 real_old = reg_equiv_mem[REGNO (tmp)];
6454 second_reload_reg = rld[secondary_reload].reg_rtx;
6455 icode = rl->secondary_in_icode;
6457 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6458 || (rl->in != 0 && rl->out != 0))
6460 enum reg_class new_class
6461 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6462 mode, real_oldequiv);
6464 if (new_class == NO_REGS)
6465 second_reload_reg = 0;
6468 enum insn_code new_icode;
6469 enum machine_mode new_mode;
6471 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6472 REGNO (second_reload_reg)))
6473 oldequiv = old, real_oldequiv = real_old;
6476 new_icode = reload_in_optab[(int) mode];
6477 if (new_icode != CODE_FOR_nothing
6478 && ((insn_data[(int) new_icode].operand[0].predicate
6479 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6481 || (insn_data[(int) new_icode].operand[1].predicate
6482 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6483 (real_oldequiv, mode)))))
6484 new_icode = CODE_FOR_nothing;
6486 if (new_icode == CODE_FOR_nothing)
6489 new_mode = insn_data[(int) new_icode].operand[2].mode;
6491 if (GET_MODE (second_reload_reg) != new_mode)
6493 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6495 oldequiv = old, real_oldequiv = real_old;
6498 = reload_adjust_reg_for_mode (second_reload_reg,
6505 /* If we still need a secondary reload register, check
6506 to see if it is being used as a scratch or intermediate
6507 register and generate code appropriately. If we need
6508 a scratch register, use REAL_OLDEQUIV since the form of
6509 the insn may depend on the actual address if it is
6512 if (second_reload_reg)
6514 if (icode != CODE_FOR_nothing)
6516 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6517 second_reload_reg));
6522 /* See if we need a scratch register to load the
6523 intermediate register (a tertiary reload). */
6524 enum insn_code tertiary_icode
6525 = rld[secondary_reload].secondary_in_icode;
6527 if (tertiary_icode != CODE_FOR_nothing)
6529 rtx third_reload_reg
6530 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6532 emit_insn ((GEN_FCN (tertiary_icode)
6533 (second_reload_reg, real_oldequiv,
6534 third_reload_reg)));
6537 gen_reload (second_reload_reg, real_oldequiv,
6541 oldequiv = second_reload_reg;
6547 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6549 rtx real_oldequiv = oldequiv;
6551 if ((REG_P (oldequiv)
6552 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6553 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6554 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6555 || (GET_CODE (oldequiv) == SUBREG
6556 && REG_P (SUBREG_REG (oldequiv))
6557 && (REGNO (SUBREG_REG (oldequiv))
6558 >= FIRST_PSEUDO_REGISTER)
6559 && ((reg_equiv_memory_loc
6560 [REGNO (SUBREG_REG (oldequiv))] != 0)
6561 || (reg_equiv_constant
6562 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6563 || (CONSTANT_P (oldequiv)
6564 && (PREFERRED_RELOAD_CLASS (oldequiv,
6565 REGNO_REG_CLASS (REGNO (reloadreg)))
6567 real_oldequiv = rl->in;
6568 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6572 if (flag_non_call_exceptions)
6573 copy_eh_notes (insn, get_insns ());
6575 /* End this sequence. */
6576 *where = get_insns ();
6579 /* Update reload_override_in so that delete_address_reloads_1
6580 can see the actual register usage. */
6582 reload_override_in[j] = oldequiv;
6585 /* Generate insns to for the output reload RL, which is for the insn described
6586 by CHAIN and has the number J. */
6588 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6591 rtx reloadreg = rl->reg_rtx;
6592 rtx insn = chain->insn;
6595 enum machine_mode mode = GET_MODE (old);
6598 if (rl->when_needed == RELOAD_OTHER)
6601 push_to_sequence (output_reload_insns[rl->opnum]);
6603 /* Determine the mode to reload in.
6604 See comments above (for input reloading). */
6606 if (mode == VOIDmode)
6608 /* VOIDmode should never happen for an output. */
6609 if (asm_noperands (PATTERN (insn)) < 0)
6610 /* It's the compiler's fault. */
6611 fatal_insn ("VOIDmode on an output", insn);
6612 error_for_asm (insn, "output operand is constant in `asm'");
6613 /* Prevent crash--use something we know is valid. */
6615 old = gen_rtx_REG (mode, REGNO (reloadreg));
6618 if (GET_MODE (reloadreg) != mode)
6619 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6621 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6623 /* If we need two reload regs, set RELOADREG to the intermediate
6624 one, since it will be stored into OLD. We might need a secondary
6625 register only for an input reload, so check again here. */
6627 if (rl->secondary_out_reload >= 0)
6631 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6632 && reg_equiv_mem[REGNO (old)] != 0)
6633 real_old = reg_equiv_mem[REGNO (old)];
6635 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6639 rtx second_reloadreg = reloadreg;
6640 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6642 /* See if RELOADREG is to be used as a scratch register
6643 or as an intermediate register. */
6644 if (rl->secondary_out_icode != CODE_FOR_nothing)
6646 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6647 (real_old, second_reloadreg, reloadreg)));
6652 /* See if we need both a scratch and intermediate reload
6655 int secondary_reload = rl->secondary_out_reload;
6656 enum insn_code tertiary_icode
6657 = rld[secondary_reload].secondary_out_icode;
6659 if (GET_MODE (reloadreg) != mode)
6660 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6662 if (tertiary_icode != CODE_FOR_nothing)
6665 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6668 /* Copy primary reload reg to secondary reload reg.
6669 (Note that these have been swapped above, then
6670 secondary reload reg to OLD using our insn.) */
6672 /* If REAL_OLD is a paradoxical SUBREG, remove it
6673 and try to put the opposite SUBREG on
6675 if (GET_CODE (real_old) == SUBREG
6676 && (GET_MODE_SIZE (GET_MODE (real_old))
6677 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6678 && 0 != (tem = gen_lowpart_common
6679 (GET_MODE (SUBREG_REG (real_old)),
6681 real_old = SUBREG_REG (real_old), reloadreg = tem;
6683 gen_reload (reloadreg, second_reloadreg,
6684 rl->opnum, rl->when_needed);
6685 emit_insn ((GEN_FCN (tertiary_icode)
6686 (real_old, reloadreg, third_reloadreg)));
6691 /* Copy between the reload regs here and then to
6694 gen_reload (reloadreg, second_reloadreg,
6695 rl->opnum, rl->when_needed);
6701 /* Output the last reload insn. */
6706 /* Don't output the last reload if OLD is not the dest of
6707 INSN and is in the src and is clobbered by INSN. */
6708 if (! flag_expensive_optimizations
6710 || !(set = single_set (insn))
6711 || rtx_equal_p (old, SET_DEST (set))
6712 || !reg_mentioned_p (old, SET_SRC (set))
6713 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6714 gen_reload (old, reloadreg, rl->opnum,
6718 /* Look at all insns we emitted, just to be safe. */
6719 for (p = get_insns (); p; p = NEXT_INSN (p))
6722 rtx pat = PATTERN (p);
6724 /* If this output reload doesn't come from a spill reg,
6725 clear any memory of reloaded copies of the pseudo reg.
6726 If this output reload comes from a spill reg,
6727 reg_has_output_reload will make this do nothing. */
6728 note_stores (pat, forget_old_reloads_1, NULL);
6730 if (reg_mentioned_p (rl->reg_rtx, pat))
6732 rtx set = single_set (insn);
6733 if (reload_spill_index[j] < 0
6735 && SET_SRC (set) == rl->reg_rtx)
6737 int src = REGNO (SET_SRC (set));
6739 reload_spill_index[j] = src;
6740 SET_HARD_REG_BIT (reg_is_output_reload, src);
6741 if (find_regno_note (insn, REG_DEAD, src))
6742 SET_HARD_REG_BIT (reg_reloaded_died, src);
6744 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6746 int s = rl->secondary_out_reload;
6747 set = single_set (p);
6748 /* If this reload copies only to the secondary reload
6749 register, the secondary reload does the actual
6751 if (s >= 0 && set == NULL_RTX)
6752 /* We can't tell what function the secondary reload
6753 has and where the actual store to the pseudo is
6754 made; leave new_spill_reg_store alone. */
6757 && SET_SRC (set) == rl->reg_rtx
6758 && SET_DEST (set) == rld[s].reg_rtx)
6760 /* Usually the next instruction will be the
6761 secondary reload insn; if we can confirm
6762 that it is, setting new_spill_reg_store to
6763 that insn will allow an extra optimization. */
6764 rtx s_reg = rld[s].reg_rtx;
6765 rtx next = NEXT_INSN (p);
6766 rld[s].out = rl->out;
6767 rld[s].out_reg = rl->out_reg;
6768 set = single_set (next);
6769 if (set && SET_SRC (set) == s_reg
6770 && ! new_spill_reg_store[REGNO (s_reg)])
6772 SET_HARD_REG_BIT (reg_is_output_reload,
6774 new_spill_reg_store[REGNO (s_reg)] = next;
6778 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6783 if (rl->when_needed == RELOAD_OTHER)
6785 emit_insn (other_output_reload_insns[rl->opnum]);
6786 other_output_reload_insns[rl->opnum] = get_insns ();
6789 output_reload_insns[rl->opnum] = get_insns ();
6791 if (flag_non_call_exceptions)
6792 copy_eh_notes (insn, get_insns ());
6797 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6798 and has the number J. */
6800 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6802 rtx insn = chain->insn;
6803 rtx old = (rl->in && MEM_P (rl->in)
6804 ? rl->in_reg : rl->in);
6807 /* AUTO_INC reloads need to be handled even if inherited. We got an
6808 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6809 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6810 && ! rtx_equal_p (rl->reg_rtx, old)
6811 && rl->reg_rtx != 0)
6812 emit_input_reload_insns (chain, rld + j, old, j);
6814 /* When inheriting a wider reload, we have a MEM in rl->in,
6815 e.g. inheriting a SImode output reload for
6816 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6817 if (optimize && reload_inherited[j] && rl->in
6819 && MEM_P (rl->in_reg)
6820 && reload_spill_index[j] >= 0
6821 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6822 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6824 /* If we are reloading a register that was recently stored in with an
6825 output-reload, see if we can prove there was
6826 actually no need to store the old value in it. */
6829 && (reload_inherited[j] || reload_override_in[j])
6831 && REG_P (rl->reg_rtx)
6832 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6834 /* There doesn't seem to be any reason to restrict this to pseudos
6835 and doing so loses in the case where we are copying from a
6836 register of the wrong class. */
6837 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6838 >= FIRST_PSEUDO_REGISTER)
6840 /* The insn might have already some references to stackslots
6841 replaced by MEMs, while reload_out_reg still names the
6843 && (dead_or_set_p (insn,
6844 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6845 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6847 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6850 /* Do output reloading for reload RL, which is for the insn described by
6851 CHAIN and has the number J.
6852 ??? At some point we need to support handling output reloads of
6853 JUMP_INSNs or insns that set cc0. */
6855 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
6858 rtx insn = chain->insn;
6859 /* If this is an output reload that stores something that is
6860 not loaded in this same reload, see if we can eliminate a previous
6862 rtx pseudo = rl->out_reg;
6867 && ! rtx_equal_p (rl->in_reg, pseudo)
6868 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6869 && reg_last_reload_reg[REGNO (pseudo)])
6871 int pseudo_no = REGNO (pseudo);
6872 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6874 /* We don't need to test full validity of last_regno for
6875 inherit here; we only want to know if the store actually
6876 matches the pseudo. */
6877 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6878 && reg_reloaded_contents[last_regno] == pseudo_no
6879 && spill_reg_store[last_regno]
6880 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6881 delete_output_reload (insn, j, last_regno);
6886 || rl->reg_rtx == old
6887 || rl->reg_rtx == 0)
6890 /* An output operand that dies right away does need a reload,
6891 but need not be copied from it. Show the new location in the
6893 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
6894 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6896 XEXP (note, 0) = rl->reg_rtx;
6899 /* Likewise for a SUBREG of an operand that dies. */
6900 else if (GET_CODE (old) == SUBREG
6901 && REG_P (SUBREG_REG (old))
6902 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6905 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6909 else if (GET_CODE (old) == SCRATCH)
6910 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6911 but we don't want to make an output reload. */
6914 /* If is a JUMP_INSN, we can't support output reloads yet. */
6915 gcc_assert (!JUMP_P (insn));
6917 emit_output_reload_insns (chain, rld + j, j);
6920 /* Reload number R reloads from or to a group of hard registers starting at
6921 register REGNO. Return true if it can be treated for inheritance purposes
6922 like a group of reloads, each one reloading a single hard register.
6923 The caller has already checked that the spill register and REGNO use
6924 the same number of registers to store the reload value. */
6927 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
6929 #ifdef CANNOT_CHANGE_MODE_CLASS
6930 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
6931 GET_MODE (rld[r].reg_rtx),
6932 reg_raw_mode[reload_spill_index[r]])
6933 && !REG_CANNOT_CHANGE_MODE_P (regno,
6934 GET_MODE (rld[r].reg_rtx),
6935 reg_raw_mode[regno]));
6941 /* Output insns to reload values in and out of the chosen reload regs. */
6944 emit_reload_insns (struct insn_chain *chain)
6946 rtx insn = chain->insn;
6950 CLEAR_HARD_REG_SET (reg_reloaded_died);
6952 for (j = 0; j < reload_n_operands; j++)
6953 input_reload_insns[j] = input_address_reload_insns[j]
6954 = inpaddr_address_reload_insns[j]
6955 = output_reload_insns[j] = output_address_reload_insns[j]
6956 = outaddr_address_reload_insns[j]
6957 = other_output_reload_insns[j] = 0;
6958 other_input_address_reload_insns = 0;
6959 other_input_reload_insns = 0;
6960 operand_reload_insns = 0;
6961 other_operand_reload_insns = 0;
6963 /* Dump reloads into the dump file. */
6966 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6967 debug_reload_to_stream (dump_file);
6970 /* Now output the instructions to copy the data into and out of the
6971 reload registers. Do these in the order that the reloads were reported,
6972 since reloads of base and index registers precede reloads of operands
6973 and the operands may need the base and index registers reloaded. */
6975 for (j = 0; j < n_reloads; j++)
6978 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6979 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6981 do_input_reload (chain, rld + j, j);
6982 do_output_reload (chain, rld + j, j);
6985 /* Now write all the insns we made for reloads in the order expected by
6986 the allocation functions. Prior to the insn being reloaded, we write
6987 the following reloads:
6989 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6991 RELOAD_OTHER reloads.
6993 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6994 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6995 RELOAD_FOR_INPUT reload for the operand.
6997 RELOAD_FOR_OPADDR_ADDRS reloads.
6999 RELOAD_FOR_OPERAND_ADDRESS reloads.
7001 After the insn being reloaded, we write the following:
7003 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7004 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7005 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7006 reloads for the operand. The RELOAD_OTHER output reloads are
7007 output in descending order by reload number. */
7009 emit_insn_before_sameloc (other_input_address_reload_insns, insn);
7010 emit_insn_before_sameloc (other_input_reload_insns, insn);
7012 for (j = 0; j < reload_n_operands; j++)
7014 emit_insn_before_sameloc (inpaddr_address_reload_insns[j], insn);
7015 emit_insn_before_sameloc (input_address_reload_insns[j], insn);
7016 emit_insn_before_sameloc (input_reload_insns[j], insn);
7019 emit_insn_before_sameloc (other_operand_reload_insns, insn);
7020 emit_insn_before_sameloc (operand_reload_insns, insn);
7022 for (j = 0; j < reload_n_operands; j++)
7024 rtx x = emit_insn_after_sameloc (outaddr_address_reload_insns[j], insn);
7025 x = emit_insn_after_sameloc (output_address_reload_insns[j], x);
7026 x = emit_insn_after_sameloc (output_reload_insns[j], x);
7027 emit_insn_after_sameloc (other_output_reload_insns[j], x);
7030 /* For all the spill regs newly reloaded in this instruction,
7031 record what they were reloaded from, so subsequent instructions
7032 can inherit the reloads.
7034 Update spill_reg_store for the reloads of this insn.
7035 Copy the elements that were updated in the loop above. */
7037 for (j = 0; j < n_reloads; j++)
7039 int r = reload_order[j];
7040 int i = reload_spill_index[r];
7042 /* If this is a non-inherited input reload from a pseudo, we must
7043 clear any memory of a previous store to the same pseudo. Only do
7044 something if there will not be an output reload for the pseudo
7046 if (rld[r].in_reg != 0
7047 && ! (reload_inherited[r] || reload_override_in[r]))
7049 rtx reg = rld[r].in_reg;
7051 if (GET_CODE (reg) == SUBREG)
7052 reg = SUBREG_REG (reg);
7055 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7056 && ! reg_has_output_reload[REGNO (reg)])
7058 int nregno = REGNO (reg);
7060 if (reg_last_reload_reg[nregno])
7062 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7064 if (reg_reloaded_contents[last_regno] == nregno)
7065 spill_reg_store[last_regno] = 0;
7070 /* I is nonneg if this reload used a register.
7071 If rld[r].reg_rtx is 0, this is an optional reload
7072 that we opted to ignore. */
7074 if (i >= 0 && rld[r].reg_rtx != 0)
7076 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7078 int part_reaches_end = 0;
7079 int all_reaches_end = 1;
7081 /* For a multi register reload, we need to check if all or part
7082 of the value lives to the end. */
7083 for (k = 0; k < nr; k++)
7085 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7086 rld[r].when_needed))
7087 part_reaches_end = 1;
7089 all_reaches_end = 0;
7092 /* Ignore reloads that don't reach the end of the insn in
7094 if (all_reaches_end)
7096 /* First, clear out memory of what used to be in this spill reg.
7097 If consecutive registers are used, clear them all. */
7099 for (k = 0; k < nr; k++)
7101 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7102 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7105 /* Maybe the spill reg contains a copy of reload_out. */
7107 && (REG_P (rld[r].out)
7111 || REG_P (rld[r].out_reg)))
7113 rtx out = (REG_P (rld[r].out)
7117 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7118 int nregno = REGNO (out);
7119 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7120 : hard_regno_nregs[nregno]
7121 [GET_MODE (rld[r].reg_rtx)]);
7124 spill_reg_store[i] = new_spill_reg_store[i];
7125 spill_reg_stored_to[i] = out;
7126 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7128 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7130 && inherit_piecemeal_p (r, nregno));
7132 /* If NREGNO is a hard register, it may occupy more than
7133 one register. If it does, say what is in the
7134 rest of the registers assuming that both registers
7135 agree on how many words the object takes. If not,
7136 invalidate the subsequent registers. */
7138 if (nregno < FIRST_PSEUDO_REGISTER)
7139 for (k = 1; k < nnr; k++)
7140 reg_last_reload_reg[nregno + k]
7142 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7145 /* Now do the inverse operation. */
7146 for (k = 0; k < nr; k++)
7148 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7149 reg_reloaded_contents[i + k]
7150 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7153 reg_reloaded_insn[i + k] = insn;
7154 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7155 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7156 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7160 /* Maybe the spill reg contains a copy of reload_in. Only do
7161 something if there will not be an output reload for
7162 the register being reloaded. */
7163 else if (rld[r].out_reg == 0
7165 && ((REG_P (rld[r].in)
7166 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7167 && ! reg_has_output_reload[REGNO (rld[r].in)])
7168 || (REG_P (rld[r].in_reg)
7169 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7170 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7177 if (REG_P (rld[r].in)
7178 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7180 else if (REG_P (rld[r].in_reg))
7183 in = XEXP (rld[r].in_reg, 0);
7184 nregno = REGNO (in);
7186 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7187 : hard_regno_nregs[nregno]
7188 [GET_MODE (rld[r].reg_rtx)]);
7190 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7192 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7194 && inherit_piecemeal_p (r, nregno));
7196 if (nregno < FIRST_PSEUDO_REGISTER)
7197 for (k = 1; k < nnr; k++)
7198 reg_last_reload_reg[nregno + k]
7200 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7203 /* Unless we inherited this reload, show we haven't
7204 recently done a store.
7205 Previous stores of inherited auto_inc expressions
7206 also have to be discarded. */
7207 if (! reload_inherited[r]
7208 || (rld[r].out && ! rld[r].out_reg))
7209 spill_reg_store[i] = 0;
7211 for (k = 0; k < nr; k++)
7213 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7214 reg_reloaded_contents[i + k]
7215 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7218 reg_reloaded_insn[i + k] = insn;
7219 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7220 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7221 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7226 /* However, if part of the reload reaches the end, then we must
7227 invalidate the old info for the part that survives to the end. */
7228 else if (part_reaches_end)
7230 for (k = 0; k < nr; k++)
7231 if (reload_reg_reaches_end_p (i + k,
7233 rld[r].when_needed))
7234 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7238 /* The following if-statement was #if 0'd in 1.34 (or before...).
7239 It's reenabled in 1.35 because supposedly nothing else
7240 deals with this problem. */
7242 /* If a register gets output-reloaded from a non-spill register,
7243 that invalidates any previous reloaded copy of it.
7244 But forget_old_reloads_1 won't get to see it, because
7245 it thinks only about the original insn. So invalidate it here. */
7246 if (i < 0 && rld[r].out != 0
7247 && (REG_P (rld[r].out)
7248 || (MEM_P (rld[r].out)
7249 && REG_P (rld[r].out_reg))))
7251 rtx out = (REG_P (rld[r].out)
7252 ? rld[r].out : rld[r].out_reg);
7253 int nregno = REGNO (out);
7254 if (nregno >= FIRST_PSEUDO_REGISTER)
7256 rtx src_reg, store_insn = NULL_RTX;
7258 reg_last_reload_reg[nregno] = 0;
7260 /* If we can find a hard register that is stored, record
7261 the storing insn so that we may delete this insn with
7262 delete_output_reload. */
7263 src_reg = rld[r].reg_rtx;
7265 /* If this is an optional reload, try to find the source reg
7266 from an input reload. */
7269 rtx set = single_set (insn);
7270 if (set && SET_DEST (set) == rld[r].out)
7274 src_reg = SET_SRC (set);
7276 for (k = 0; k < n_reloads; k++)
7278 if (rld[k].in == src_reg)
7280 src_reg = rld[k].reg_rtx;
7287 store_insn = new_spill_reg_store[REGNO (src_reg)];
7288 if (src_reg && REG_P (src_reg)
7289 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7291 int src_regno = REGNO (src_reg);
7292 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7293 /* The place where to find a death note varies with
7294 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7295 necessarily checked exactly in the code that moves
7296 notes, so just check both locations. */
7297 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7298 if (! note && store_insn)
7299 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7302 spill_reg_store[src_regno + nr] = store_insn;
7303 spill_reg_stored_to[src_regno + nr] = out;
7304 reg_reloaded_contents[src_regno + nr] = nregno;
7305 reg_reloaded_insn[src_regno + nr] = store_insn;
7306 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7307 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7308 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7309 GET_MODE (src_reg)))
7310 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7312 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7314 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7316 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7318 reg_last_reload_reg[nregno] = src_reg;
7319 /* We have to set reg_has_output_reload here, or else
7320 forget_old_reloads_1 will clear reg_last_reload_reg
7322 reg_has_output_reload[nregno] = 1;
7327 int num_regs = hard_regno_nregs[nregno][GET_MODE (rld[r].out)];
7329 while (num_regs-- > 0)
7330 reg_last_reload_reg[nregno + num_regs] = 0;
7334 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7337 /* Emit code to perform a reload from IN (which may be a reload register) to
7338 OUT (which may also be a reload register). IN or OUT is from operand
7339 OPNUM with reload type TYPE.
7341 Returns first insn emitted. */
7344 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7346 rtx last = get_last_insn ();
7349 /* If IN is a paradoxical SUBREG, remove it and try to put the
7350 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7351 if (GET_CODE (in) == SUBREG
7352 && (GET_MODE_SIZE (GET_MODE (in))
7353 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7354 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7355 in = SUBREG_REG (in), out = tem;
7356 else if (GET_CODE (out) == SUBREG
7357 && (GET_MODE_SIZE (GET_MODE (out))
7358 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7359 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7360 out = SUBREG_REG (out), in = tem;
7362 /* How to do this reload can get quite tricky. Normally, we are being
7363 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7364 register that didn't get a hard register. In that case we can just
7365 call emit_move_insn.
7367 We can also be asked to reload a PLUS that adds a register or a MEM to
7368 another register, constant or MEM. This can occur during frame pointer
7369 elimination and while reloading addresses. This case is handled by
7370 trying to emit a single insn to perform the add. If it is not valid,
7371 we use a two insn sequence.
7373 Finally, we could be called to handle an 'o' constraint by putting
7374 an address into a register. In that case, we first try to do this
7375 with a named pattern of "reload_load_address". If no such pattern
7376 exists, we just emit a SET insn and hope for the best (it will normally
7377 be valid on machines that use 'o').
7379 This entire process is made complex because reload will never
7380 process the insns we generate here and so we must ensure that
7381 they will fit their constraints and also by the fact that parts of
7382 IN might be being reloaded separately and replaced with spill registers.
7383 Because of this, we are, in some sense, just guessing the right approach
7384 here. The one listed above seems to work.
7386 ??? At some point, this whole thing needs to be rethought. */
7388 if (GET_CODE (in) == PLUS
7389 && (REG_P (XEXP (in, 0))
7390 || GET_CODE (XEXP (in, 0)) == SUBREG
7391 || MEM_P (XEXP (in, 0)))
7392 && (REG_P (XEXP (in, 1))
7393 || GET_CODE (XEXP (in, 1)) == SUBREG
7394 || CONSTANT_P (XEXP (in, 1))
7395 || MEM_P (XEXP (in, 1))))
7397 /* We need to compute the sum of a register or a MEM and another
7398 register, constant, or MEM, and put it into the reload
7399 register. The best possible way of doing this is if the machine
7400 has a three-operand ADD insn that accepts the required operands.
7402 The simplest approach is to try to generate such an insn and see if it
7403 is recognized and matches its constraints. If so, it can be used.
7405 It might be better not to actually emit the insn unless it is valid,
7406 but we need to pass the insn as an operand to `recog' and
7407 `extract_insn' and it is simpler to emit and then delete the insn if
7408 not valid than to dummy things up. */
7410 rtx op0, op1, tem, insn;
7413 op0 = find_replacement (&XEXP (in, 0));
7414 op1 = find_replacement (&XEXP (in, 1));
7416 /* Since constraint checking is strict, commutativity won't be
7417 checked, so we need to do that here to avoid spurious failure
7418 if the add instruction is two-address and the second operand
7419 of the add is the same as the reload reg, which is frequently
7420 the case. If the insn would be A = B + A, rearrange it so
7421 it will be A = A + B as constrain_operands expects. */
7423 if (REG_P (XEXP (in, 1))
7424 && REGNO (out) == REGNO (XEXP (in, 1)))
7425 tem = op0, op0 = op1, op1 = tem;
7427 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7428 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7430 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7431 code = recog_memoized (insn);
7435 extract_insn (insn);
7436 /* We want constrain operands to treat this insn strictly in
7437 its validity determination, i.e., the way it would after reload
7439 if (constrain_operands (1))
7443 delete_insns_since (last);
7445 /* If that failed, we must use a conservative two-insn sequence.
7447 Use a move to copy one operand into the reload register. Prefer
7448 to reload a constant, MEM or pseudo since the move patterns can
7449 handle an arbitrary operand. If OP1 is not a constant, MEM or
7450 pseudo and OP1 is not a valid operand for an add instruction, then
7453 After reloading one of the operands into the reload register, add
7454 the reload register to the output register.
7456 If there is another way to do this for a specific machine, a
7457 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7460 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7462 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7464 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7465 || (code != CODE_FOR_nothing
7466 && ! ((*insn_data[code].operand[2].predicate)
7467 (op1, insn_data[code].operand[2].mode))))
7468 tem = op0, op0 = op1, op1 = tem;
7470 gen_reload (out, op0, opnum, type);
7472 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7473 This fixes a problem on the 32K where the stack pointer cannot
7474 be used as an operand of an add insn. */
7476 if (rtx_equal_p (op0, op1))
7479 insn = emit_insn (gen_add2_insn (out, op1));
7481 /* If that failed, copy the address register to the reload register.
7482 Then add the constant to the reload register. */
7484 code = recog_memoized (insn);
7488 extract_insn (insn);
7489 /* We want constrain operands to treat this insn strictly in
7490 its validity determination, i.e., the way it would after reload
7492 if (constrain_operands (1))
7494 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7496 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7501 delete_insns_since (last);
7503 gen_reload (out, op1, opnum, type);
7504 insn = emit_insn (gen_add2_insn (out, op0));
7505 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7508 #ifdef SECONDARY_MEMORY_NEEDED
7509 /* If we need a memory location to do the move, do it that way. */
7510 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7511 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7512 && (REG_P (out) || GET_CODE (out) == SUBREG)
7513 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7514 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7515 REGNO_REG_CLASS (reg_or_subregno (out)),
7518 /* Get the memory to use and rewrite both registers to its mode. */
7519 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7521 if (GET_MODE (loc) != GET_MODE (out))
7522 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7524 if (GET_MODE (loc) != GET_MODE (in))
7525 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7527 gen_reload (loc, in, opnum, type);
7528 gen_reload (out, loc, opnum, type);
7532 /* If IN is a simple operand, use gen_move_insn. */
7533 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7534 emit_insn (gen_move_insn (out, in));
7536 #ifdef HAVE_reload_load_address
7537 else if (HAVE_reload_load_address)
7538 emit_insn (gen_reload_load_address (out, in));
7541 /* Otherwise, just write (set OUT IN) and hope for the best. */
7543 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7545 /* Return the first insn emitted.
7546 We can not just return get_last_insn, because there may have
7547 been multiple instructions emitted. Also note that gen_move_insn may
7548 emit more than one insn itself, so we can not assume that there is one
7549 insn emitted per emit_insn_before call. */
7551 return last ? NEXT_INSN (last) : get_insns ();
7554 /* Delete a previously made output-reload whose result we now believe
7555 is not needed. First we double-check.
7557 INSN is the insn now being processed.
7558 LAST_RELOAD_REG is the hard register number for which we want to delete
7559 the last output reload.
7560 J is the reload-number that originally used REG. The caller has made
7561 certain that reload J doesn't use REG any longer for input. */
7564 delete_output_reload (rtx insn, int j, int last_reload_reg)
7566 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7567 rtx reg = spill_reg_stored_to[last_reload_reg];
7570 int n_inherited = 0;
7574 /* It is possible that this reload has been only used to set another reload
7575 we eliminated earlier and thus deleted this instruction too. */
7576 if (INSN_DELETED_P (output_reload_insn))
7579 /* Get the raw pseudo-register referred to. */
7581 while (GET_CODE (reg) == SUBREG)
7582 reg = SUBREG_REG (reg);
7583 substed = reg_equiv_memory_loc[REGNO (reg)];
7585 /* This is unsafe if the operand occurs more often in the current
7586 insn than it is inherited. */
7587 for (k = n_reloads - 1; k >= 0; k--)
7589 rtx reg2 = rld[k].in;
7592 if (MEM_P (reg2) || reload_override_in[k])
7593 reg2 = rld[k].in_reg;
7595 if (rld[k].out && ! rld[k].out_reg)
7596 reg2 = XEXP (rld[k].in_reg, 0);
7598 while (GET_CODE (reg2) == SUBREG)
7599 reg2 = SUBREG_REG (reg2);
7600 if (rtx_equal_p (reg2, reg))
7602 if (reload_inherited[k] || reload_override_in[k] || k == j)
7605 reg2 = rld[k].out_reg;
7608 while (GET_CODE (reg2) == SUBREG)
7609 reg2 = XEXP (reg2, 0);
7610 if (rtx_equal_p (reg2, reg))
7617 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7619 n_occurrences += count_occurrences (PATTERN (insn),
7620 eliminate_regs (substed, 0,
7622 if (n_occurrences > n_inherited)
7625 /* If the pseudo-reg we are reloading is no longer referenced
7626 anywhere between the store into it and here,
7627 and no jumps or labels intervene, then the value can get
7628 here through the reload reg alone.
7629 Otherwise, give up--return. */
7630 for (i1 = NEXT_INSN (output_reload_insn);
7631 i1 != insn; i1 = NEXT_INSN (i1))
7633 if (LABEL_P (i1) || JUMP_P (i1))
7635 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7636 && reg_mentioned_p (reg, PATTERN (i1)))
7638 /* If this is USE in front of INSN, we only have to check that
7639 there are no more references than accounted for by inheritance. */
7640 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7642 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7643 i1 = NEXT_INSN (i1);
7645 if (n_occurrences <= n_inherited && i1 == insn)
7651 /* We will be deleting the insn. Remove the spill reg information. */
7652 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7654 spill_reg_store[last_reload_reg + k] = 0;
7655 spill_reg_stored_to[last_reload_reg + k] = 0;
7658 /* The caller has already checked that REG dies or is set in INSN.
7659 It has also checked that we are optimizing, and thus some
7660 inaccuracies in the debugging information are acceptable.
7661 So we could just delete output_reload_insn. But in some cases
7662 we can improve the debugging information without sacrificing
7663 optimization - maybe even improving the code: See if the pseudo
7664 reg has been completely replaced with reload regs. If so, delete
7665 the store insn and forget we had a stack slot for the pseudo. */
7666 if (rld[j].out != rld[j].in
7667 && REG_N_DEATHS (REGNO (reg)) == 1
7668 && REG_N_SETS (REGNO (reg)) == 1
7669 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7670 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7674 /* We know that it was used only between here and the beginning of
7675 the current basic block. (We also know that the last use before
7676 INSN was the output reload we are thinking of deleting, but never
7677 mind that.) Search that range; see if any ref remains. */
7678 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7680 rtx set = single_set (i2);
7682 /* Uses which just store in the pseudo don't count,
7683 since if they are the only uses, they are dead. */
7684 if (set != 0 && SET_DEST (set) == reg)
7689 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7690 && reg_mentioned_p (reg, PATTERN (i2)))
7692 /* Some other ref remains; just delete the output reload we
7694 delete_address_reloads (output_reload_insn, insn);
7695 delete_insn (output_reload_insn);
7700 /* Delete the now-dead stores into this pseudo. Note that this
7701 loop also takes care of deleting output_reload_insn. */
7702 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7704 rtx set = single_set (i2);
7706 if (set != 0 && SET_DEST (set) == reg)
7708 delete_address_reloads (i2, insn);
7716 /* For the debugging info, say the pseudo lives in this reload reg. */
7717 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7718 alter_reg (REGNO (reg), -1);
7722 delete_address_reloads (output_reload_insn, insn);
7723 delete_insn (output_reload_insn);
7727 /* We are going to delete DEAD_INSN. Recursively delete loads of
7728 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7729 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7731 delete_address_reloads (rtx dead_insn, rtx current_insn)
7733 rtx set = single_set (dead_insn);
7734 rtx set2, dst, prev, next;
7737 rtx dst = SET_DEST (set);
7739 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7741 /* If we deleted the store from a reloaded post_{in,de}c expression,
7742 we can delete the matching adds. */
7743 prev = PREV_INSN (dead_insn);
7744 next = NEXT_INSN (dead_insn);
7745 if (! prev || ! next)
7747 set = single_set (next);
7748 set2 = single_set (prev);
7750 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7751 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7752 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7754 dst = SET_DEST (set);
7755 if (! rtx_equal_p (dst, SET_DEST (set2))
7756 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7757 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7758 || (INTVAL (XEXP (SET_SRC (set), 1))
7759 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7761 delete_related_insns (prev);
7762 delete_related_insns (next);
7765 /* Subfunction of delete_address_reloads: process registers found in X. */
7767 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7769 rtx prev, set, dst, i2;
7771 enum rtx_code code = GET_CODE (x);
7775 const char *fmt = GET_RTX_FORMAT (code);
7776 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7779 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7780 else if (fmt[i] == 'E')
7782 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7783 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7790 if (spill_reg_order[REGNO (x)] < 0)
7793 /* Scan backwards for the insn that sets x. This might be a way back due
7795 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7797 code = GET_CODE (prev);
7798 if (code == CODE_LABEL || code == JUMP_INSN)
7802 if (reg_set_p (x, PATTERN (prev)))
7804 if (reg_referenced_p (x, PATTERN (prev)))
7807 if (! prev || INSN_UID (prev) < reload_first_uid)
7809 /* Check that PREV only sets the reload register. */
7810 set = single_set (prev);
7813 dst = SET_DEST (set);
7815 || ! rtx_equal_p (dst, x))
7817 if (! reg_set_p (dst, PATTERN (dead_insn)))
7819 /* Check if DST was used in a later insn -
7820 it might have been inherited. */
7821 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7827 if (reg_referenced_p (dst, PATTERN (i2)))
7829 /* If there is a reference to the register in the current insn,
7830 it might be loaded in a non-inherited reload. If no other
7831 reload uses it, that means the register is set before
7833 if (i2 == current_insn)
7835 for (j = n_reloads - 1; j >= 0; j--)
7836 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7837 || reload_override_in[j] == dst)
7839 for (j = n_reloads - 1; j >= 0; j--)
7840 if (rld[j].in && rld[j].reg_rtx == dst)
7849 /* If DST is still live at CURRENT_INSN, check if it is used for
7850 any reload. Note that even if CURRENT_INSN sets DST, we still
7851 have to check the reloads. */
7852 if (i2 == current_insn)
7854 for (j = n_reloads - 1; j >= 0; j--)
7855 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7856 || reload_override_in[j] == dst)
7858 /* ??? We can't finish the loop here, because dst might be
7859 allocated to a pseudo in this block if no reload in this
7860 block needs any of the classes containing DST - see
7861 spill_hard_reg. There is no easy way to tell this, so we
7862 have to scan till the end of the basic block. */
7864 if (reg_set_p (dst, PATTERN (i2)))
7868 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7869 reg_reloaded_contents[REGNO (dst)] = -1;
7873 /* Output reload-insns to reload VALUE into RELOADREG.
7874 VALUE is an autoincrement or autodecrement RTX whose operand
7875 is a register or memory location;
7876 so reloading involves incrementing that location.
7877 IN is either identical to VALUE, or some cheaper place to reload from.
7879 INC_AMOUNT is the number to increment or decrement by (always positive).
7880 This cannot be deduced from VALUE.
7882 Return the instruction that stores into RELOADREG. */
7885 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
7887 /* REG or MEM to be copied and incremented. */
7888 rtx incloc = XEXP (value, 0);
7889 /* Nonzero if increment after copying. */
7890 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7896 rtx real_in = in == value ? XEXP (in, 0) : in;
7898 /* No hard register is equivalent to this register after
7899 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
7900 we could inc/dec that register as well (maybe even using it for
7901 the source), but I'm not sure it's worth worrying about. */
7903 reg_last_reload_reg[REGNO (incloc)] = 0;
7905 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7906 inc_amount = -inc_amount;
7908 inc = GEN_INT (inc_amount);
7910 /* If this is post-increment, first copy the location to the reload reg. */
7911 if (post && real_in != reloadreg)
7912 emit_insn (gen_move_insn (reloadreg, real_in));
7916 /* See if we can directly increment INCLOC. Use a method similar to
7917 that in gen_reload. */
7919 last = get_last_insn ();
7920 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7921 gen_rtx_PLUS (GET_MODE (incloc),
7924 code = recog_memoized (add_insn);
7927 extract_insn (add_insn);
7928 if (constrain_operands (1))
7930 /* If this is a pre-increment and we have incremented the value
7931 where it lives, copy the incremented value to RELOADREG to
7932 be used as an address. */
7935 emit_insn (gen_move_insn (reloadreg, incloc));
7940 delete_insns_since (last);
7943 /* If couldn't do the increment directly, must increment in RELOADREG.
7944 The way we do this depends on whether this is pre- or post-increment.
7945 For pre-increment, copy INCLOC to the reload register, increment it
7946 there, then save back. */
7950 if (in != reloadreg)
7951 emit_insn (gen_move_insn (reloadreg, real_in));
7952 emit_insn (gen_add2_insn (reloadreg, inc));
7953 store = emit_insn (gen_move_insn (incloc, reloadreg));
7958 Because this might be a jump insn or a compare, and because RELOADREG
7959 may not be available after the insn in an input reload, we must do
7960 the incrementation before the insn being reloaded for.
7962 We have already copied IN to RELOADREG. Increment the copy in
7963 RELOADREG, save that back, then decrement RELOADREG so it has
7964 the original value. */
7966 emit_insn (gen_add2_insn (reloadreg, inc));
7967 store = emit_insn (gen_move_insn (incloc, reloadreg));
7968 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7976 add_auto_inc_notes (rtx insn, rtx x)
7978 enum rtx_code code = GET_CODE (x);
7982 if (code == MEM && auto_inc_p (XEXP (x, 0)))
7985 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
7989 /* Scan all the operand sub-expressions. */
7990 fmt = GET_RTX_FORMAT (code);
7991 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7994 add_auto_inc_notes (insn, XEXP (x, i));
7995 else if (fmt[i] == 'E')
7996 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7997 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8002 /* Copy EH notes from an insn to its reloads. */
8004 copy_eh_notes (rtx insn, rtx x)
8006 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8009 for (; x != 0; x = NEXT_INSN (x))
8011 if (may_trap_p (PATTERN (x)))
8013 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8019 /* This is used by reload pass, that does emit some instructions after
8020 abnormal calls moving basic block end, but in fact it wants to emit
8021 them on the edge. Looks for abnormal call edges, find backward the
8022 proper call and fix the damage.
8024 Similar handle instructions throwing exceptions internally. */
8026 fixup_abnormal_edges (void)
8028 bool inserted = false;
8035 /* Look for cases we are interested in - calls or instructions causing
8037 for (e = bb->succ; e; e = e->succ_next)
8039 if (e->flags & EDGE_ABNORMAL_CALL)
8041 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8042 == (EDGE_ABNORMAL | EDGE_EH))
8045 if (e && !CALL_P (BB_END (bb))
8046 && !can_throw_internal (BB_END (bb)))
8048 rtx insn = BB_END (bb), stop = NEXT_INSN (BB_END (bb));
8050 for (e = bb->succ; e; e = e->succ_next)
8051 if (e->flags & EDGE_FALLTHRU)
8053 /* Get past the new insns generated. Allow notes, as the insns may
8054 be already deleted. */
8055 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8056 && !can_throw_internal (insn)
8057 && insn != BB_HEAD (bb))
8058 insn = PREV_INSN (insn);
8059 gcc_assert (CALL_P (insn) || can_throw_internal (insn));
8062 insn = NEXT_INSN (insn);
8063 while (insn && insn != stop)
8065 next = NEXT_INSN (insn);
8070 /* Sometimes there's still the return value USE.
8071 If it's placed after a trapping call (i.e. that
8072 call is the last insn anyway), we have no fallthru
8073 edge. Simply delete this use and don't try to insert
8074 on the non-existent edge. */
8075 if (GET_CODE (PATTERN (insn)) != USE)
8077 /* We're not deleting it, we're moving it. */
8078 INSN_DELETED_P (insn) = 0;
8079 PREV_INSN (insn) = NULL_RTX;
8080 NEXT_INSN (insn) = NULL_RTX;
8082 insert_insn_on_edge (insn, e);
8089 /* We've possibly turned single trapping insn into multiple ones. */
8090 if (flag_non_call_exceptions)
8093 blocks = sbitmap_alloc (last_basic_block);
8094 sbitmap_ones (blocks);
8095 find_many_sub_basic_blocks (blocks);
8098 commit_edge_insertions ();
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