1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE
322 target hook in previous scan over insns
324 HOST_WIDE_INT offset; /* Current offset between the two regs. */
325 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
326 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
327 rtx from_rtx; /* REG rtx for the register to be eliminated.
328 We cannot simply compare the number since
329 we might then spuriously replace a hard
330 register corresponding to a pseudo
331 assigned to the reg to be eliminated. */
332 rtx to_rtx; /* REG rtx for the replacement. */
335 static struct elim_table *reg_eliminate = 0;
337 /* This is an intermediate structure to initialize the table. It has
338 exactly the members provided by ELIMINABLE_REGS. */
339 static const struct elim_table_1
343 } reg_eliminate_1[] =
345 /* If a set of eliminable registers was specified, define the table from it.
346 Otherwise, default to the normal case of the frame pointer being
347 replaced by the stack pointer. */
349 #ifdef ELIMINABLE_REGS
352 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
355 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
357 /* Record the number of pending eliminations that have an offset not equal
358 to their initial offset. If nonzero, we use a new copy of each
359 replacement result in any insns encountered. */
360 int num_not_at_initial_offset;
362 /* Count the number of registers that we may be able to eliminate. */
363 static int num_eliminable;
364 /* And the number of registers that are equivalent to a constant that
365 can be eliminated to frame_pointer / arg_pointer + constant. */
366 static int num_eliminable_invariants;
368 /* For each label, we record the offset of each elimination. If we reach
369 a label by more than one path and an offset differs, we cannot do the
370 elimination. This information is indexed by the difference of the
371 number of the label and the first label number. We can't offset the
372 pointer itself as this can cause problems on machines with segmented
373 memory. The first table is an array of flags that records whether we
374 have yet encountered a label and the second table is an array of arrays,
375 one entry in the latter array for each elimination. */
377 static int first_label_num;
378 static char *offsets_known_at;
379 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
381 /* Number of labels in the current function. */
383 static int num_labels;
385 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
386 static void maybe_fix_stack_asms (void);
387 static void copy_reloads (struct insn_chain *);
388 static void calculate_needs_all_insns (int);
389 static int find_reg (struct insn_chain *, int);
390 static void find_reload_regs (struct insn_chain *);
391 static void select_reload_regs (void);
392 static void delete_caller_save_insns (void);
394 static void spill_failure (rtx, enum reg_class);
395 static void count_spilled_pseudo (int, int, int);
396 static void delete_dead_insn (rtx);
397 static void alter_reg (int, int, bool);
398 static void set_label_offsets (rtx, rtx, int);
399 static void check_eliminable_occurrences (rtx);
400 static void elimination_effects (rtx, enum machine_mode);
401 static int eliminate_regs_in_insn (rtx, int);
402 static void update_eliminable_offsets (void);
403 static void mark_not_eliminable (rtx, const_rtx, void *);
404 static void set_initial_elim_offsets (void);
405 static bool verify_initial_elim_offsets (void);
406 static void set_initial_label_offsets (void);
407 static void set_offsets_for_label (rtx);
408 static void init_elim_table (void);
409 static void update_eliminables (HARD_REG_SET *);
410 static void spill_hard_reg (unsigned int, int);
411 static int finish_spills (int);
412 static void scan_paradoxical_subregs (rtx);
413 static void count_pseudo (int);
414 static void order_regs_for_reload (struct insn_chain *);
415 static void reload_as_needed (int);
416 static void forget_old_reloads_1 (rtx, const_rtx, void *);
417 static void forget_marked_reloads (regset);
418 static int reload_reg_class_lower (const void *, const void *);
419 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
421 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
423 static int reload_reg_free_p (unsigned int, int, enum reload_type);
424 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
426 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
428 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
429 static int allocate_reload_reg (struct insn_chain *, int, int);
430 static int conflicts_with_override (rtx);
431 static void failed_reload (rtx, int);
432 static int set_reload_reg (int, int);
433 static void choose_reload_regs_init (struct insn_chain *, rtx *);
434 static void choose_reload_regs (struct insn_chain *);
435 static void merge_assigned_reloads (rtx);
436 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
438 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
440 static void do_input_reload (struct insn_chain *, struct reload *, int);
441 static void do_output_reload (struct insn_chain *, struct reload *, int);
442 static void emit_reload_insns (struct insn_chain *);
443 static void delete_output_reload (rtx, int, int, rtx);
444 static void delete_address_reloads (rtx, rtx);
445 static void delete_address_reloads_1 (rtx, rtx, rtx);
446 static rtx inc_for_reload (rtx, rtx, rtx, int);
448 static void add_auto_inc_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert (ira_conflicts_p || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
803 if (NONDEBUG_INSN_P (insn))
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1003 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1005 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1006 else if (CONSTANT_P (XEXP (x, 0))
1007 || (REG_P (XEXP (x, 0))
1008 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1009 || (GET_CODE (XEXP (x, 0)) == PLUS
1010 && REG_P (XEXP (XEXP (x, 0), 0))
1011 && (REGNO (XEXP (XEXP (x, 0), 0))
1012 < FIRST_PSEUDO_REGISTER)
1013 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1014 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1017 /* Make a new stack slot. Then indicate that something
1018 changed so we go back and recompute offsets for
1019 eliminable registers because the allocation of memory
1020 below might change some offset. reg_equiv_{mem,address}
1021 will be set up for this pseudo on the next pass around
1023 reg_equiv_memory_loc[i] = 0;
1024 reg_equiv_init[i] = 0;
1025 alter_reg (i, -1, true);
1029 if (caller_save_needed)
1030 setup_save_areas ();
1032 /* If we allocated another stack slot, redo elimination bookkeeping. */
1033 if (starting_frame_size != get_frame_size ())
1035 if (starting_frame_size && crtl->stack_alignment_needed)
1037 /* If we have a stack frame, we must align it now. The
1038 stack size may be a part of the offset computation for
1039 register elimination. So if this changes the stack size,
1040 then repeat the elimination bookkeeping. We don't
1041 realign when there is no stack, as that will cause a
1042 stack frame when none is needed should
1043 STARTING_FRAME_OFFSET not be already aligned to
1045 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1046 if (starting_frame_size != get_frame_size ())
1050 if (caller_save_needed)
1052 save_call_clobbered_regs ();
1053 /* That might have allocated new insn_chain structures. */
1054 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1057 calculate_needs_all_insns (global);
1059 if (! ira_conflicts_p)
1060 /* Don't do it for IRA. We need this info because we don't
1061 change live_throughout and dead_or_set for chains when IRA
1063 CLEAR_REG_SET (&spilled_pseudos);
1067 something_changed = 0;
1069 /* If we allocated any new memory locations, make another pass
1070 since it might have changed elimination offsets. */
1071 if (starting_frame_size != get_frame_size ())
1072 something_changed = 1;
1074 /* Even if the frame size remained the same, we might still have
1075 changed elimination offsets, e.g. if find_reloads called
1076 force_const_mem requiring the back end to allocate a constant
1077 pool base register that needs to be saved on the stack. */
1078 else if (!verify_initial_elim_offsets ())
1079 something_changed = 1;
1082 HARD_REG_SET to_spill;
1083 CLEAR_HARD_REG_SET (to_spill);
1084 update_eliminables (&to_spill);
1085 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1087 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1088 if (TEST_HARD_REG_BIT (to_spill, i))
1090 spill_hard_reg (i, 1);
1093 /* Regardless of the state of spills, if we previously had
1094 a register that we thought we could eliminate, but now can
1095 not eliminate, we must run another pass.
1097 Consider pseudos which have an entry in reg_equiv_* which
1098 reference an eliminable register. We must make another pass
1099 to update reg_equiv_* so that we do not substitute in the
1100 old value from when we thought the elimination could be
1102 something_changed = 1;
1106 select_reload_regs ();
1110 if (insns_need_reload != 0 || did_spill)
1111 something_changed |= finish_spills (global);
1113 if (! something_changed)
1116 if (caller_save_needed)
1117 delete_caller_save_insns ();
1119 obstack_free (&reload_obstack, reload_firstobj);
1122 /* If global-alloc was run, notify it of any register eliminations we have
1125 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1126 if (ep->can_eliminate)
1127 mark_elimination (ep->from, ep->to);
1129 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1130 If that insn didn't set the register (i.e., it copied the register to
1131 memory), just delete that insn instead of the equivalencing insn plus
1132 anything now dead. If we call delete_dead_insn on that insn, we may
1133 delete the insn that actually sets the register if the register dies
1134 there and that is incorrect. */
1136 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1138 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1141 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1143 rtx equiv_insn = XEXP (list, 0);
1145 /* If we already deleted the insn or if it may trap, we can't
1146 delete it. The latter case shouldn't happen, but can
1147 if an insn has a variable address, gets a REG_EH_REGION
1148 note added to it, and then gets converted into a load
1149 from a constant address. */
1150 if (NOTE_P (equiv_insn)
1151 || can_throw_internal (equiv_insn))
1153 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1154 delete_dead_insn (equiv_insn);
1156 SET_INSN_DELETED (equiv_insn);
1161 /* Use the reload registers where necessary
1162 by generating move instructions to move the must-be-register
1163 values into or out of the reload registers. */
1165 if (insns_need_reload != 0 || something_needs_elimination
1166 || something_needs_operands_changed)
1168 HOST_WIDE_INT old_frame_size = get_frame_size ();
1170 reload_as_needed (global);
1172 gcc_assert (old_frame_size == get_frame_size ());
1174 gcc_assert (verify_initial_elim_offsets ());
1177 /* If we were able to eliminate the frame pointer, show that it is no
1178 longer live at the start of any basic block. If it ls live by
1179 virtue of being in a pseudo, that pseudo will be marked live
1180 and hence the frame pointer will be known to be live via that
1183 if (! frame_pointer_needed)
1185 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1187 /* Come here (with failure set nonzero) if we can't get enough spill
1191 CLEAR_REG_SET (&changed_allocation_pseudos);
1192 CLEAR_REG_SET (&spilled_pseudos);
1193 reload_in_progress = 0;
1195 /* Now eliminate all pseudo regs by modifying them into
1196 their equivalent memory references.
1197 The REG-rtx's for the pseudos are modified in place,
1198 so all insns that used to refer to them now refer to memory.
1200 For a reg that has a reg_equiv_address, all those insns
1201 were changed by reloading so that no insns refer to it any longer;
1202 but the DECL_RTL of a variable decl may refer to it,
1203 and if so this causes the debugging info to mention the variable. */
1205 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1209 if (reg_equiv_mem[i])
1210 addr = XEXP (reg_equiv_mem[i], 0);
1212 if (reg_equiv_address[i])
1213 addr = reg_equiv_address[i];
1217 if (reg_renumber[i] < 0)
1219 rtx reg = regno_reg_rtx[i];
1221 REG_USERVAR_P (reg) = 0;
1222 PUT_CODE (reg, MEM);
1223 XEXP (reg, 0) = addr;
1224 if (reg_equiv_memory_loc[i])
1225 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1228 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1229 MEM_ATTRS (reg) = 0;
1231 MEM_NOTRAP_P (reg) = 1;
1233 else if (reg_equiv_mem[i])
1234 XEXP (reg_equiv_mem[i], 0) = addr;
1237 /* We don't want complex addressing modes in debug insns
1238 if simpler ones will do, so delegitimize equivalences
1240 if (MAY_HAVE_DEBUG_INSNS && reg_renumber[i] < 0)
1242 rtx reg = regno_reg_rtx[i];
1246 if (reg_equiv_constant[i])
1247 equiv = reg_equiv_constant[i];
1248 else if (reg_equiv_invariant[i])
1249 equiv = reg_equiv_invariant[i];
1250 else if (reg && MEM_P (reg))
1252 equiv = targetm.delegitimize_address (reg);
1256 else if (reg && REG_P (reg) && (int)REGNO (reg) != i)
1260 for (use = DF_REG_USE_CHAIN (i); use;
1261 use = DF_REF_NEXT_REG (use))
1262 if (DEBUG_INSN_P (DF_REF_INSN (use)))
1264 rtx *loc = DF_REF_LOC (use);
1268 *loc = copy_rtx (equiv);
1269 else if (GET_CODE (x) == SUBREG
1270 && SUBREG_REG (x) == reg)
1271 *loc = simplify_gen_subreg (GET_MODE (x), equiv,
1276 *loc = wrap_constant (GET_MODE (x), *loc);
1281 /* We must set reload_completed now since the cleanup_subreg_operands call
1282 below will re-recognize each insn and reload may have generated insns
1283 which are only valid during and after reload. */
1284 reload_completed = 1;
1286 /* Make a pass over all the insns and delete all USEs which we inserted
1287 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1288 notes. Delete all CLOBBER insns, except those that refer to the return
1289 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1290 from misarranging variable-array code, and simplify (subreg (reg))
1291 operands. Strip and regenerate REG_INC notes that may have been moved
1294 for (insn = first; insn; insn = NEXT_INSN (insn))
1300 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1301 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1303 if ((GET_CODE (PATTERN (insn)) == USE
1304 /* We mark with QImode USEs introduced by reload itself. */
1305 && (GET_MODE (insn) == QImode
1306 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1307 || (GET_CODE (PATTERN (insn)) == CLOBBER
1308 && (!MEM_P (XEXP (PATTERN (insn), 0))
1309 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1310 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1311 && XEXP (XEXP (PATTERN (insn), 0), 0)
1312 != stack_pointer_rtx))
1313 && (!REG_P (XEXP (PATTERN (insn), 0))
1314 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1320 /* Some CLOBBERs may survive until here and still reference unassigned
1321 pseudos with const equivalent, which may in turn cause ICE in later
1322 passes if the reference remains in place. */
1323 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1324 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1325 VOIDmode, PATTERN (insn));
1327 /* Discard obvious no-ops, even without -O. This optimization
1328 is fast and doesn't interfere with debugging. */
1329 if (NONJUMP_INSN_P (insn)
1330 && GET_CODE (PATTERN (insn)) == SET
1331 && REG_P (SET_SRC (PATTERN (insn)))
1332 && REG_P (SET_DEST (PATTERN (insn)))
1333 && (REGNO (SET_SRC (PATTERN (insn)))
1334 == REGNO (SET_DEST (PATTERN (insn)))))
1340 pnote = ®_NOTES (insn);
1343 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1344 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1345 || REG_NOTE_KIND (*pnote) == REG_INC)
1346 *pnote = XEXP (*pnote, 1);
1348 pnote = &XEXP (*pnote, 1);
1352 add_auto_inc_notes (insn, PATTERN (insn));
1355 /* Simplify (subreg (reg)) if it appears as an operand. */
1356 cleanup_subreg_operands (insn);
1358 /* Clean up invalid ASMs so that they don't confuse later passes.
1360 if (asm_noperands (PATTERN (insn)) >= 0)
1362 extract_insn (insn);
1363 if (!constrain_operands (1))
1365 error_for_asm (insn,
1366 "%<asm%> operand has impossible constraints");
1373 /* If we are doing generic stack checking, give a warning if this
1374 function's frame size is larger than we expect. */
1375 if (flag_stack_check == GENERIC_STACK_CHECK)
1377 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1378 static int verbose_warned = 0;
1380 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1381 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1382 size += UNITS_PER_WORD;
1384 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1386 warning (0, "frame size too large for reliable stack checking");
1387 if (! verbose_warned)
1389 warning (0, "try reducing the number of local variables");
1395 /* Indicate that we no longer have known memory locations or constants. */
1396 if (reg_equiv_constant)
1397 free (reg_equiv_constant);
1398 if (reg_equiv_invariant)
1399 free (reg_equiv_invariant);
1400 reg_equiv_constant = 0;
1401 reg_equiv_invariant = 0;
1402 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1403 reg_equiv_memory_loc = 0;
1405 free (temp_pseudo_reg_arr);
1407 if (offsets_known_at)
1408 free (offsets_known_at);
1412 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1413 if (reg_equiv_alt_mem_list[i])
1414 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1415 free (reg_equiv_alt_mem_list);
1417 free (reg_equiv_mem);
1419 free (reg_equiv_address);
1420 free (reg_max_ref_width);
1421 free (reg_old_renumber);
1422 free (pseudo_previous_regs);
1423 free (pseudo_forbidden_regs);
1425 CLEAR_HARD_REG_SET (used_spill_regs);
1426 for (i = 0; i < n_spills; i++)
1427 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1429 /* Free all the insn_chain structures at once. */
1430 obstack_free (&reload_obstack, reload_startobj);
1431 unused_insn_chains = 0;
1432 fixup_abnormal_edges ();
1434 /* Replacing pseudos with their memory equivalents might have
1435 created shared rtx. Subsequent passes would get confused
1436 by this, so unshare everything here. */
1437 unshare_all_rtl_again (first);
1439 #ifdef STACK_BOUNDARY
1440 /* init_emit has set the alignment of the hard frame pointer
1441 to STACK_BOUNDARY. It is very likely no longer valid if
1442 the hard frame pointer was used for register allocation. */
1443 if (!frame_pointer_needed)
1444 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1450 /* Yet another special case. Unfortunately, reg-stack forces people to
1451 write incorrect clobbers in asm statements. These clobbers must not
1452 cause the register to appear in bad_spill_regs, otherwise we'll call
1453 fatal_insn later. We clear the corresponding regnos in the live
1454 register sets to avoid this.
1455 The whole thing is rather sick, I'm afraid. */
1458 maybe_fix_stack_asms (void)
1461 const char *constraints[MAX_RECOG_OPERANDS];
1462 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1463 struct insn_chain *chain;
1465 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1468 HARD_REG_SET clobbered, allowed;
1471 if (! INSN_P (chain->insn)
1472 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1474 pat = PATTERN (chain->insn);
1475 if (GET_CODE (pat) != PARALLEL)
1478 CLEAR_HARD_REG_SET (clobbered);
1479 CLEAR_HARD_REG_SET (allowed);
1481 /* First, make a mask of all stack regs that are clobbered. */
1482 for (i = 0; i < XVECLEN (pat, 0); i++)
1484 rtx t = XVECEXP (pat, 0, i);
1485 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1486 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1489 /* Get the operand values and constraints out of the insn. */
1490 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1491 constraints, operand_mode, NULL);
1493 /* For every operand, see what registers are allowed. */
1494 for (i = 0; i < noperands; i++)
1496 const char *p = constraints[i];
1497 /* For every alternative, we compute the class of registers allowed
1498 for reloading in CLS, and merge its contents into the reg set
1500 int cls = (int) NO_REGS;
1506 if (c == '\0' || c == ',' || c == '#')
1508 /* End of one alternative - mark the regs in the current
1509 class, and reset the class. */
1510 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1516 } while (c != '\0' && c != ',');
1524 case '=': case '+': case '*': case '%': case '?': case '!':
1525 case '0': case '1': case '2': case '3': case '4': case '<':
1526 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1527 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1528 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1529 case TARGET_MEM_CONSTRAINT:
1533 cls = (int) reg_class_subunion[cls]
1534 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1539 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1543 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1544 cls = (int) reg_class_subunion[cls]
1545 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1547 cls = (int) reg_class_subunion[cls]
1548 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1550 p += CONSTRAINT_LEN (c, p);
1553 /* Those of the registers which are clobbered, but allowed by the
1554 constraints, must be usable as reload registers. So clear them
1555 out of the life information. */
1556 AND_HARD_REG_SET (allowed, clobbered);
1557 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1558 if (TEST_HARD_REG_BIT (allowed, i))
1560 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1561 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1568 /* Copy the global variables n_reloads and rld into the corresponding elts
1571 copy_reloads (struct insn_chain *chain)
1573 chain->n_reloads = n_reloads;
1574 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1575 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1576 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1579 /* Walk the chain of insns, and determine for each whether it needs reloads
1580 and/or eliminations. Build the corresponding insns_need_reload list, and
1581 set something_needs_elimination as appropriate. */
1583 calculate_needs_all_insns (int global)
1585 struct insn_chain **pprev_reload = &insns_need_reload;
1586 struct insn_chain *chain, *next = 0;
1588 something_needs_elimination = 0;
1590 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1591 for (chain = reload_insn_chain; chain != 0; chain = next)
1593 rtx insn = chain->insn;
1597 /* Clear out the shortcuts. */
1598 chain->n_reloads = 0;
1599 chain->need_elim = 0;
1600 chain->need_reload = 0;
1601 chain->need_operand_change = 0;
1603 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1604 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1605 what effects this has on the known offsets at labels. */
1607 if (LABEL_P (insn) || JUMP_P (insn)
1608 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1609 set_label_offsets (insn, insn, 0);
1613 rtx old_body = PATTERN (insn);
1614 int old_code = INSN_CODE (insn);
1615 rtx old_notes = REG_NOTES (insn);
1616 int did_elimination = 0;
1617 int operands_changed = 0;
1618 rtx set = single_set (insn);
1620 /* Skip insns that only set an equivalence. */
1621 if (set && REG_P (SET_DEST (set))
1622 && reg_renumber[REGNO (SET_DEST (set))] < 0
1623 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1624 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1625 && reg_equiv_init[REGNO (SET_DEST (set))])
1628 /* If needed, eliminate any eliminable registers. */
1629 if (num_eliminable || num_eliminable_invariants)
1630 did_elimination = eliminate_regs_in_insn (insn, 0);
1632 /* Analyze the instruction. */
1633 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1634 global, spill_reg_order);
1636 /* If a no-op set needs more than one reload, this is likely
1637 to be something that needs input address reloads. We
1638 can't get rid of this cleanly later, and it is of no use
1639 anyway, so discard it now.
1640 We only do this when expensive_optimizations is enabled,
1641 since this complements reload inheritance / output
1642 reload deletion, and it can make debugging harder. */
1643 if (flag_expensive_optimizations && n_reloads > 1)
1645 rtx set = single_set (insn);
1648 ((SET_SRC (set) == SET_DEST (set)
1649 && REG_P (SET_SRC (set))
1650 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1651 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1652 && reg_renumber[REGNO (SET_SRC (set))] < 0
1653 && reg_renumber[REGNO (SET_DEST (set))] < 0
1654 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1655 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1656 && rtx_equal_p (reg_equiv_memory_loc
1657 [REGNO (SET_SRC (set))],
1658 reg_equiv_memory_loc
1659 [REGNO (SET_DEST (set))]))))
1661 if (ira_conflicts_p)
1662 /* Inform IRA about the insn deletion. */
1663 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1664 REGNO (SET_SRC (set)));
1666 /* Delete it from the reload chain. */
1668 chain->prev->next = next;
1670 reload_insn_chain = next;
1672 next->prev = chain->prev;
1673 chain->next = unused_insn_chains;
1674 unused_insn_chains = chain;
1679 update_eliminable_offsets ();
1681 /* Remember for later shortcuts which insns had any reloads or
1682 register eliminations. */
1683 chain->need_elim = did_elimination;
1684 chain->need_reload = n_reloads > 0;
1685 chain->need_operand_change = operands_changed;
1687 /* Discard any register replacements done. */
1688 if (did_elimination)
1690 obstack_free (&reload_obstack, reload_insn_firstobj);
1691 PATTERN (insn) = old_body;
1692 INSN_CODE (insn) = old_code;
1693 REG_NOTES (insn) = old_notes;
1694 something_needs_elimination = 1;
1697 something_needs_operands_changed |= operands_changed;
1701 copy_reloads (chain);
1702 *pprev_reload = chain;
1703 pprev_reload = &chain->next_need_reload;
1710 /* Comparison function for qsort to decide which of two reloads
1711 should be handled first. *P1 and *P2 are the reload numbers. */
1714 reload_reg_class_lower (const void *r1p, const void *r2p)
1716 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1719 /* Consider required reloads before optional ones. */
1720 t = rld[r1].optional - rld[r2].optional;
1724 /* Count all solitary classes before non-solitary ones. */
1725 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1726 - (reg_class_size[(int) rld[r1].rclass] == 1));
1730 /* Aside from solitaires, consider all multi-reg groups first. */
1731 t = rld[r2].nregs - rld[r1].nregs;
1735 /* Consider reloads in order of increasing reg-class number. */
1736 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1740 /* If reloads are equally urgent, sort by reload number,
1741 so that the results of qsort leave nothing to chance. */
1745 /* The cost of spilling each hard reg. */
1746 static int spill_cost[FIRST_PSEUDO_REGISTER];
1748 /* When spilling multiple hard registers, we use SPILL_COST for the first
1749 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1750 only the first hard reg for a multi-reg pseudo. */
1751 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1753 /* Map of hard regno to pseudo regno currently occupying the hard
1755 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1757 /* Update the spill cost arrays, considering that pseudo REG is live. */
1760 count_pseudo (int reg)
1762 int freq = REG_FREQ (reg);
1763 int r = reg_renumber[reg];
1766 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1767 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1768 /* Ignore spilled pseudo-registers which can be here only if IRA
1770 || (ira_conflicts_p && r < 0))
1773 SET_REGNO_REG_SET (&pseudos_counted, reg);
1775 gcc_assert (r >= 0);
1777 spill_add_cost[r] += freq;
1778 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1781 hard_regno_to_pseudo_regno[r + nregs] = reg;
1782 spill_cost[r + nregs] += freq;
1786 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1787 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1790 order_regs_for_reload (struct insn_chain *chain)
1793 HARD_REG_SET used_by_pseudos;
1794 HARD_REG_SET used_by_pseudos2;
1795 reg_set_iterator rsi;
1797 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1799 memset (spill_cost, 0, sizeof spill_cost);
1800 memset (spill_add_cost, 0, sizeof spill_add_cost);
1801 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1802 hard_regno_to_pseudo_regno[i] = -1;
1804 /* Count number of uses of each hard reg by pseudo regs allocated to it
1805 and then order them by decreasing use. First exclude hard registers
1806 that are live in or across this insn. */
1808 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1809 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1810 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1811 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1813 /* Now find out which pseudos are allocated to it, and update
1815 CLEAR_REG_SET (&pseudos_counted);
1817 EXECUTE_IF_SET_IN_REG_SET
1818 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1822 EXECUTE_IF_SET_IN_REG_SET
1823 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1827 CLEAR_REG_SET (&pseudos_counted);
1830 /* Vector of reload-numbers showing the order in which the reloads should
1832 static short reload_order[MAX_RELOADS];
1834 /* This is used to keep track of the spill regs used in one insn. */
1835 static HARD_REG_SET used_spill_regs_local;
1837 /* We decided to spill hard register SPILLED, which has a size of
1838 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1839 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1840 update SPILL_COST/SPILL_ADD_COST. */
1843 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1845 int freq = REG_FREQ (reg);
1846 int r = reg_renumber[reg];
1847 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1849 /* Ignore spilled pseudo-registers which can be here only if IRA is
1851 if ((ira_conflicts_p && r < 0)
1852 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1853 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1856 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1858 spill_add_cost[r] -= freq;
1861 hard_regno_to_pseudo_regno[r + nregs] = -1;
1862 spill_cost[r + nregs] -= freq;
1866 /* Find reload register to use for reload number ORDER. */
1869 find_reg (struct insn_chain *chain, int order)
1871 int rnum = reload_order[order];
1872 struct reload *rl = rld + rnum;
1873 int best_cost = INT_MAX;
1875 unsigned int i, j, n;
1877 HARD_REG_SET not_usable;
1878 HARD_REG_SET used_by_other_reload;
1879 reg_set_iterator rsi;
1880 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1881 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1883 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1884 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1885 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1887 CLEAR_HARD_REG_SET (used_by_other_reload);
1888 for (k = 0; k < order; k++)
1890 int other = reload_order[k];
1892 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1893 for (j = 0; j < rld[other].nregs; j++)
1894 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1897 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1899 #ifdef REG_ALLOC_ORDER
1900 unsigned int regno = reg_alloc_order[i];
1902 unsigned int regno = i;
1905 if (! TEST_HARD_REG_BIT (not_usable, regno)
1906 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1907 && HARD_REGNO_MODE_OK (regno, rl->mode))
1909 int this_cost = spill_cost[regno];
1911 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1913 for (j = 1; j < this_nregs; j++)
1915 this_cost += spill_add_cost[regno + j];
1916 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1917 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1923 if (ira_conflicts_p)
1925 /* Ask IRA to find a better pseudo-register for
1927 for (n = j = 0; j < this_nregs; j++)
1929 int r = hard_regno_to_pseudo_regno[regno + j];
1933 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1934 regno_pseudo_regs[n++] = r;
1936 regno_pseudo_regs[n++] = -1;
1938 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1939 best_regno_pseudo_regs,
1946 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1947 if (regno_pseudo_regs[j] < 0)
1954 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1956 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1958 if (this_cost < best_cost
1959 /* Among registers with equal cost, prefer caller-saved ones, or
1960 use REG_ALLOC_ORDER if it is defined. */
1961 || (this_cost == best_cost
1962 #ifdef REG_ALLOC_ORDER
1963 && (inv_reg_alloc_order[regno]
1964 < inv_reg_alloc_order[best_reg])
1966 && call_used_regs[regno]
1967 && ! call_used_regs[best_reg]
1972 best_cost = this_cost;
1980 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1982 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1983 rl->regno = best_reg;
1985 EXECUTE_IF_SET_IN_REG_SET
1986 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1988 count_spilled_pseudo (best_reg, rl->nregs, j);
1991 EXECUTE_IF_SET_IN_REG_SET
1992 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1994 count_spilled_pseudo (best_reg, rl->nregs, j);
1997 for (i = 0; i < rl->nregs; i++)
1999 gcc_assert (spill_cost[best_reg + i] == 0);
2000 gcc_assert (spill_add_cost[best_reg + i] == 0);
2001 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
2002 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
2007 /* Find more reload regs to satisfy the remaining need of an insn, which
2009 Do it by ascending class number, since otherwise a reg
2010 might be spilled for a big class and might fail to count
2011 for a smaller class even though it belongs to that class. */
2014 find_reload_regs (struct insn_chain *chain)
2018 /* In order to be certain of getting the registers we need,
2019 we must sort the reloads into order of increasing register class.
2020 Then our grabbing of reload registers will parallel the process
2021 that provided the reload registers. */
2022 for (i = 0; i < chain->n_reloads; i++)
2024 /* Show whether this reload already has a hard reg. */
2025 if (chain->rld[i].reg_rtx)
2027 int regno = REGNO (chain->rld[i].reg_rtx);
2028 chain->rld[i].regno = regno;
2030 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
2033 chain->rld[i].regno = -1;
2034 reload_order[i] = i;
2037 n_reloads = chain->n_reloads;
2038 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
2040 CLEAR_HARD_REG_SET (used_spill_regs_local);
2043 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2045 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2047 /* Compute the order of preference for hard registers to spill. */
2049 order_regs_for_reload (chain);
2051 for (i = 0; i < n_reloads; i++)
2053 int r = reload_order[i];
2055 /* Ignore reloads that got marked inoperative. */
2056 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2057 && ! rld[r].optional
2058 && rld[r].regno == -1)
2059 if (! find_reg (chain, i))
2062 fprintf (dump_file, "reload failure for reload %d\n", r);
2063 spill_failure (chain->insn, rld[r].rclass);
2069 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2070 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2072 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2076 select_reload_regs (void)
2078 struct insn_chain *chain;
2080 /* Try to satisfy the needs for each insn. */
2081 for (chain = insns_need_reload; chain != 0;
2082 chain = chain->next_need_reload)
2083 find_reload_regs (chain);
2086 /* Delete all insns that were inserted by emit_caller_save_insns during
2089 delete_caller_save_insns (void)
2091 struct insn_chain *c = reload_insn_chain;
2095 while (c != 0 && c->is_caller_save_insn)
2097 struct insn_chain *next = c->next;
2100 if (c == reload_insn_chain)
2101 reload_insn_chain = next;
2105 next->prev = c->prev;
2107 c->prev->next = next;
2108 c->next = unused_insn_chains;
2109 unused_insn_chains = c;
2117 /* Handle the failure to find a register to spill.
2118 INSN should be one of the insns which needed this particular spill reg. */
2121 spill_failure (rtx insn, enum reg_class rclass)
2123 if (asm_noperands (PATTERN (insn)) >= 0)
2124 error_for_asm (insn, "can't find a register in class %qs while "
2125 "reloading %<asm%>",
2126 reg_class_names[rclass]);
2129 error ("unable to find a register to spill in class %qs",
2130 reg_class_names[rclass]);
2134 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2135 debug_reload_to_stream (dump_file);
2137 fatal_insn ("this is the insn:", insn);
2141 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2142 data that is dead in INSN. */
2145 delete_dead_insn (rtx insn)
2147 rtx prev = prev_real_insn (insn);
2150 /* If the previous insn sets a register that dies in our insn, delete it
2152 if (prev && GET_CODE (PATTERN (prev)) == SET
2153 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2154 && reg_mentioned_p (prev_dest, PATTERN (insn))
2155 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2156 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2157 delete_dead_insn (prev);
2159 SET_INSN_DELETED (insn);
2162 /* Modify the home of pseudo-reg I.
2163 The new home is present in reg_renumber[I].
2165 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2166 or it may be -1, meaning there is none or it is not relevant.
2167 This is used so that all pseudos spilled from a given hard reg
2168 can share one stack slot. */
2171 alter_reg (int i, int from_reg, bool dont_share_p)
2173 /* When outputting an inline function, this can happen
2174 for a reg that isn't actually used. */
2175 if (regno_reg_rtx[i] == 0)
2178 /* If the reg got changed to a MEM at rtl-generation time,
2180 if (!REG_P (regno_reg_rtx[i]))
2183 /* Modify the reg-rtx to contain the new hard reg
2184 number or else to contain its pseudo reg number. */
2185 SET_REGNO (regno_reg_rtx[i],
2186 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2188 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2189 allocate a stack slot for it. */
2191 if (reg_renumber[i] < 0
2192 && REG_N_REFS (i) > 0
2193 && reg_equiv_constant[i] == 0
2194 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2195 && reg_equiv_memory_loc[i] == 0)
2198 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2199 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2200 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2201 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2202 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2205 if (ira_conflicts_p)
2207 /* Mark the spill for IRA. */
2208 SET_REGNO_REG_SET (&spilled_pseudos, i);
2210 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2216 /* Each pseudo reg has an inherent size which comes from its own mode,
2217 and a total size which provides room for paradoxical subregs
2218 which refer to the pseudo reg in wider modes.
2220 We can use a slot already allocated if it provides both
2221 enough inherent space and enough total space.
2222 Otherwise, we allocate a new slot, making sure that it has no less
2223 inherent space, and no less total space, then the previous slot. */
2224 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2228 /* No known place to spill from => no slot to reuse. */
2229 x = assign_stack_local (mode, total_size,
2230 min_align > inherent_align
2231 || total_size > inherent_size ? -1 : 0);
2235 /* Cancel the big-endian correction done in assign_stack_local.
2236 Get the address of the beginning of the slot. This is so we
2237 can do a big-endian correction unconditionally below. */
2238 if (BYTES_BIG_ENDIAN)
2240 adjust = inherent_size - total_size;
2243 = adjust_address_nv (x, mode_for_size (total_size
2249 if (! dont_share_p && ira_conflicts_p)
2250 /* Inform IRA about allocation a new stack slot. */
2251 ira_mark_new_stack_slot (stack_slot, i, total_size);
2254 /* Reuse a stack slot if possible. */
2255 else if (spill_stack_slot[from_reg] != 0
2256 && spill_stack_slot_width[from_reg] >= total_size
2257 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2259 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2260 x = spill_stack_slot[from_reg];
2262 /* Allocate a bigger slot. */
2265 /* Compute maximum size needed, both for inherent size
2266 and for total size. */
2269 if (spill_stack_slot[from_reg])
2271 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2273 mode = GET_MODE (spill_stack_slot[from_reg]);
2274 if (spill_stack_slot_width[from_reg] > total_size)
2275 total_size = spill_stack_slot_width[from_reg];
2276 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2277 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2280 /* Make a slot with that size. */
2281 x = assign_stack_local (mode, total_size,
2282 min_align > inherent_align
2283 || total_size > inherent_size ? -1 : 0);
2286 /* Cancel the big-endian correction done in assign_stack_local.
2287 Get the address of the beginning of the slot. This is so we
2288 can do a big-endian correction unconditionally below. */
2289 if (BYTES_BIG_ENDIAN)
2291 adjust = GET_MODE_SIZE (mode) - total_size;
2294 = adjust_address_nv (x, mode_for_size (total_size
2300 spill_stack_slot[from_reg] = stack_slot;
2301 spill_stack_slot_width[from_reg] = total_size;
2304 /* On a big endian machine, the "address" of the slot
2305 is the address of the low part that fits its inherent mode. */
2306 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2307 adjust += (total_size - inherent_size);
2309 /* If we have any adjustment to make, or if the stack slot is the
2310 wrong mode, make a new stack slot. */
2311 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2313 /* Set all of the memory attributes as appropriate for a spill. */
2314 set_mem_attrs_for_spill (x);
2316 /* Save the stack slot for later. */
2317 reg_equiv_memory_loc[i] = x;
2321 /* Mark the slots in regs_ever_live for the hard regs used by
2322 pseudo-reg number REGNO, accessed in MODE. */
2325 mark_home_live_1 (int regno, enum machine_mode mode)
2329 i = reg_renumber[regno];
2332 lim = end_hard_regno (mode, i);
2334 df_set_regs_ever_live(i++, true);
2337 /* Mark the slots in regs_ever_live for the hard regs
2338 used by pseudo-reg number REGNO. */
2341 mark_home_live (int regno)
2343 if (reg_renumber[regno] >= 0)
2344 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2347 /* This function handles the tracking of elimination offsets around branches.
2349 X is a piece of RTL being scanned.
2351 INSN is the insn that it came from, if any.
2353 INITIAL_P is nonzero if we are to set the offset to be the initial
2354 offset and zero if we are setting the offset of the label to be the
2358 set_label_offsets (rtx x, rtx insn, int initial_p)
2360 enum rtx_code code = GET_CODE (x);
2363 struct elim_table *p;
2368 if (LABEL_REF_NONLOCAL_P (x))
2373 /* ... fall through ... */
2376 /* If we know nothing about this label, set the desired offsets. Note
2377 that this sets the offset at a label to be the offset before a label
2378 if we don't know anything about the label. This is not correct for
2379 the label after a BARRIER, but is the best guess we can make. If
2380 we guessed wrong, we will suppress an elimination that might have
2381 been possible had we been able to guess correctly. */
2383 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2385 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2386 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2387 = (initial_p ? reg_eliminate[i].initial_offset
2388 : reg_eliminate[i].offset);
2389 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2392 /* Otherwise, if this is the definition of a label and it is
2393 preceded by a BARRIER, set our offsets to the known offset of
2397 && (tem = prev_nonnote_insn (insn)) != 0
2399 set_offsets_for_label (insn);
2401 /* If neither of the above cases is true, compare each offset
2402 with those previously recorded and suppress any eliminations
2403 where the offsets disagree. */
2405 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2406 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2407 != (initial_p ? reg_eliminate[i].initial_offset
2408 : reg_eliminate[i].offset))
2409 reg_eliminate[i].can_eliminate = 0;
2414 set_label_offsets (PATTERN (insn), insn, initial_p);
2416 /* ... fall through ... */
2420 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2421 to indirectly and hence must have all eliminations at their
2423 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2424 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2425 set_label_offsets (XEXP (tem, 0), insn, 1);
2431 /* Each of the labels in the parallel or address vector must be
2432 at their initial offsets. We want the first field for PARALLEL
2433 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2435 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2436 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2441 /* We only care about setting PC. If the source is not RETURN,
2442 IF_THEN_ELSE, or a label, disable any eliminations not at
2443 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2444 isn't one of those possibilities. For branches to a label,
2445 call ourselves recursively.
2447 Note that this can disable elimination unnecessarily when we have
2448 a non-local goto since it will look like a non-constant jump to
2449 someplace in the current function. This isn't a significant
2450 problem since such jumps will normally be when all elimination
2451 pairs are back to their initial offsets. */
2453 if (SET_DEST (x) != pc_rtx)
2456 switch (GET_CODE (SET_SRC (x)))
2463 set_label_offsets (SET_SRC (x), insn, initial_p);
2467 tem = XEXP (SET_SRC (x), 1);
2468 if (GET_CODE (tem) == LABEL_REF)
2469 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2470 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2473 tem = XEXP (SET_SRC (x), 2);
2474 if (GET_CODE (tem) == LABEL_REF)
2475 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2476 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2484 /* If we reach here, all eliminations must be at their initial
2485 offset because we are doing a jump to a variable address. */
2486 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2487 if (p->offset != p->initial_offset)
2488 p->can_eliminate = 0;
2496 /* Scan X and replace any eliminable registers (such as fp) with a
2497 replacement (such as sp), plus an offset.
2499 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2500 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2501 MEM, we are allowed to replace a sum of a register and the constant zero
2502 with the register, which we cannot do outside a MEM. In addition, we need
2503 to record the fact that a register is referenced outside a MEM.
2505 If INSN is an insn, it is the insn containing X. If we replace a REG
2506 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2507 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2508 the REG is being modified.
2510 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2511 That's used when we eliminate in expressions stored in notes.
2512 This means, do not set ref_outside_mem even if the reference
2515 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2516 replacements done assuming all offsets are at their initial values. If
2517 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2518 encounter, return the actual location so that find_reloads will do
2519 the proper thing. */
2522 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2523 bool may_use_invariant)
2525 enum rtx_code code = GET_CODE (x);
2526 struct elim_table *ep;
2533 if (! current_function_decl)
2556 /* First handle the case where we encounter a bare register that
2557 is eliminable. Replace it with a PLUS. */
2558 if (regno < FIRST_PSEUDO_REGISTER)
2560 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2562 if (ep->from_rtx == x && ep->can_eliminate)
2563 return plus_constant (ep->to_rtx, ep->previous_offset);
2566 else if (reg_renumber && reg_renumber[regno] < 0
2567 && reg_equiv_invariant && reg_equiv_invariant[regno])
2569 if (may_use_invariant)
2570 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2571 mem_mode, insn, true);
2572 /* There exists at least one use of REGNO that cannot be
2573 eliminated. Prevent the defining insn from being deleted. */
2574 reg_equiv_init[regno] = NULL_RTX;
2575 alter_reg (regno, -1, true);
2579 /* You might think handling MINUS in a manner similar to PLUS is a
2580 good idea. It is not. It has been tried multiple times and every
2581 time the change has had to have been reverted.
2583 Other parts of reload know a PLUS is special (gen_reload for example)
2584 and require special code to handle code a reloaded PLUS operand.
2586 Also consider backends where the flags register is clobbered by a
2587 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2588 lea instruction comes to mind). If we try to reload a MINUS, we
2589 may kill the flags register that was holding a useful value.
2591 So, please before trying to handle MINUS, consider reload as a
2592 whole instead of this little section as well as the backend issues. */
2594 /* If this is the sum of an eliminable register and a constant, rework
2596 if (REG_P (XEXP (x, 0))
2597 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2598 && CONSTANT_P (XEXP (x, 1)))
2600 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2602 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2604 /* The only time we want to replace a PLUS with a REG (this
2605 occurs when the constant operand of the PLUS is the negative
2606 of the offset) is when we are inside a MEM. We won't want
2607 to do so at other times because that would change the
2608 structure of the insn in a way that reload can't handle.
2609 We special-case the commonest situation in
2610 eliminate_regs_in_insn, so just replace a PLUS with a
2611 PLUS here, unless inside a MEM. */
2612 if (mem_mode != 0 && CONST_INT_P (XEXP (x, 1))
2613 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2616 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2617 plus_constant (XEXP (x, 1),
2618 ep->previous_offset));
2621 /* If the register is not eliminable, we are done since the other
2622 operand is a constant. */
2626 /* If this is part of an address, we want to bring any constant to the
2627 outermost PLUS. We will do this by doing register replacement in
2628 our operands and seeing if a constant shows up in one of them.
2630 Note that there is no risk of modifying the structure of the insn,
2631 since we only get called for its operands, thus we are either
2632 modifying the address inside a MEM, or something like an address
2633 operand of a load-address insn. */
2636 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2637 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2639 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2641 /* If one side is a PLUS and the other side is a pseudo that
2642 didn't get a hard register but has a reg_equiv_constant,
2643 we must replace the constant here since it may no longer
2644 be in the position of any operand. */
2645 if (GET_CODE (new0) == PLUS && REG_P (new1)
2646 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2647 && reg_renumber[REGNO (new1)] < 0
2648 && reg_equiv_constant != 0
2649 && reg_equiv_constant[REGNO (new1)] != 0)
2650 new1 = reg_equiv_constant[REGNO (new1)];
2651 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2652 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2653 && reg_renumber[REGNO (new0)] < 0
2654 && reg_equiv_constant[REGNO (new0)] != 0)
2655 new0 = reg_equiv_constant[REGNO (new0)];
2657 new_rtx = form_sum (new0, new1);
2659 /* As above, if we are not inside a MEM we do not want to
2660 turn a PLUS into something else. We might try to do so here
2661 for an addition of 0 if we aren't optimizing. */
2662 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2663 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2671 /* If this is the product of an eliminable register and a
2672 constant, apply the distribute law and move the constant out
2673 so that we have (plus (mult ..) ..). This is needed in order
2674 to keep load-address insns valid. This case is pathological.
2675 We ignore the possibility of overflow here. */
2676 if (REG_P (XEXP (x, 0))
2677 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2678 && CONST_INT_P (XEXP (x, 1)))
2679 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2681 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2684 /* Refs inside notes don't count for this purpose. */
2685 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2686 || GET_CODE (insn) == INSN_LIST)))
2687 ep->ref_outside_mem = 1;
2690 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2691 ep->previous_offset * INTVAL (XEXP (x, 1)));
2694 /* ... fall through ... */
2698 /* See comments before PLUS about handling MINUS. */
2700 case DIV: case UDIV:
2701 case MOD: case UMOD:
2702 case AND: case IOR: case XOR:
2703 case ROTATERT: case ROTATE:
2704 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2706 case GE: case GT: case GEU: case GTU:
2707 case LE: case LT: case LEU: case LTU:
2709 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2710 rtx new1 = XEXP (x, 1)
2711 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2713 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2714 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2719 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2722 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2723 if (new_rtx != XEXP (x, 0))
2725 /* If this is a REG_DEAD note, it is not valid anymore.
2726 Using the eliminated version could result in creating a
2727 REG_DEAD note for the stack or frame pointer. */
2728 if (REG_NOTE_KIND (x) == REG_DEAD)
2730 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2733 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2737 /* ... fall through ... */
2740 /* Now do eliminations in the rest of the chain. If this was
2741 an EXPR_LIST, this might result in allocating more memory than is
2742 strictly needed, but it simplifies the code. */
2745 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2746 if (new_rtx != XEXP (x, 1))
2748 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2756 /* We do not support elimination of a register that is modified.
2757 elimination_effects has already make sure that this does not
2763 /* We do not support elimination of a register that is modified.
2764 elimination_effects has already make sure that this does not
2765 happen. The only remaining case we need to consider here is
2766 that the increment value may be an eliminable register. */
2767 if (GET_CODE (XEXP (x, 1)) == PLUS
2768 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2770 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2773 if (new_rtx != XEXP (XEXP (x, 1), 1))
2774 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2775 gen_rtx_PLUS (GET_MODE (x),
2776 XEXP (x, 0), new_rtx));
2780 case STRICT_LOW_PART:
2782 case SIGN_EXTEND: case ZERO_EXTEND:
2783 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2784 case FLOAT: case FIX:
2785 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2794 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2795 if (new_rtx != XEXP (x, 0))
2796 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2800 /* Similar to above processing, but preserve SUBREG_BYTE.
2801 Convert (subreg (mem)) to (mem) if not paradoxical.
2802 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2803 pseudo didn't get a hard reg, we must replace this with the
2804 eliminated version of the memory location because push_reload
2805 may do the replacement in certain circumstances. */
2806 if (REG_P (SUBREG_REG (x))
2807 && (GET_MODE_SIZE (GET_MODE (x))
2808 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2809 && reg_equiv_memory_loc != 0
2810 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2812 new_rtx = SUBREG_REG (x);
2815 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2817 if (new_rtx != SUBREG_REG (x))
2819 int x_size = GET_MODE_SIZE (GET_MODE (x));
2820 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2823 && ((x_size < new_size
2824 #ifdef WORD_REGISTER_OPERATIONS
2825 /* On these machines, combine can create rtl of the form
2826 (set (subreg:m1 (reg:m2 R) 0) ...)
2827 where m1 < m2, and expects something interesting to
2828 happen to the entire word. Moreover, it will use the
2829 (reg:m2 R) later, expecting all bits to be preserved.
2830 So if the number of words is the same, preserve the
2831 subreg so that push_reload can see it. */
2832 && ! ((x_size - 1) / UNITS_PER_WORD
2833 == (new_size -1 ) / UNITS_PER_WORD)
2836 || x_size == new_size)
2838 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2840 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2846 /* Our only special processing is to pass the mode of the MEM to our
2847 recursive call and copy the flags. While we are here, handle this
2848 case more efficiently. */
2850 replace_equiv_address_nv (x,
2851 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2855 /* Handle insn_list USE that a call to a pure function may generate. */
2856 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2857 if (new_rtx != XEXP (x, 0))
2858 return gen_rtx_USE (GET_MODE (x), new_rtx);
2870 /* Process each of our operands recursively. If any have changed, make a
2872 fmt = GET_RTX_FORMAT (code);
2873 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2877 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2878 if (new_rtx != XEXP (x, i) && ! copied)
2880 x = shallow_copy_rtx (x);
2883 XEXP (x, i) = new_rtx;
2885 else if (*fmt == 'E')
2888 for (j = 0; j < XVECLEN (x, i); j++)
2890 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2891 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2893 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2897 x = shallow_copy_rtx (x);
2900 XVEC (x, i) = new_v;
2903 XVECEXP (x, i, j) = new_rtx;
2912 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2914 return eliminate_regs_1 (x, mem_mode, insn, false);
2917 /* Scan rtx X for modifications of elimination target registers. Update
2918 the table of eliminables to reflect the changed state. MEM_MODE is
2919 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2922 elimination_effects (rtx x, enum machine_mode mem_mode)
2924 enum rtx_code code = GET_CODE (x);
2925 struct elim_table *ep;
2950 /* First handle the case where we encounter a bare register that
2951 is eliminable. Replace it with a PLUS. */
2952 if (regno < FIRST_PSEUDO_REGISTER)
2954 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2956 if (ep->from_rtx == x && ep->can_eliminate)
2959 ep->ref_outside_mem = 1;
2964 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2965 && reg_equiv_constant[regno]
2966 && ! function_invariant_p (reg_equiv_constant[regno]))
2967 elimination_effects (reg_equiv_constant[regno], mem_mode);
2976 /* If we modify the source of an elimination rule, disable it. */
2977 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2978 if (ep->from_rtx == XEXP (x, 0))
2979 ep->can_eliminate = 0;
2981 /* If we modify the target of an elimination rule by adding a constant,
2982 update its offset. If we modify the target in any other way, we'll
2983 have to disable the rule as well. */
2984 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2985 if (ep->to_rtx == XEXP (x, 0))
2987 int size = GET_MODE_SIZE (mem_mode);
2989 /* If more bytes than MEM_MODE are pushed, account for them. */
2990 #ifdef PUSH_ROUNDING
2991 if (ep->to_rtx == stack_pointer_rtx)
2992 size = PUSH_ROUNDING (size);
2994 if (code == PRE_DEC || code == POST_DEC)
2996 else if (code == PRE_INC || code == POST_INC)
2998 else if (code == PRE_MODIFY || code == POST_MODIFY)
3000 if (GET_CODE (XEXP (x, 1)) == PLUS
3001 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
3002 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
3003 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
3005 ep->can_eliminate = 0;
3009 /* These two aren't unary operators. */
3010 if (code == POST_MODIFY || code == PRE_MODIFY)
3013 /* Fall through to generic unary operation case. */
3014 case STRICT_LOW_PART:
3016 case SIGN_EXTEND: case ZERO_EXTEND:
3017 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
3018 case FLOAT: case FIX:
3019 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
3028 elimination_effects (XEXP (x, 0), mem_mode);
3032 if (REG_P (SUBREG_REG (x))
3033 && (GET_MODE_SIZE (GET_MODE (x))
3034 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3035 && reg_equiv_memory_loc != 0
3036 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
3039 elimination_effects (SUBREG_REG (x), mem_mode);
3043 /* If using a register that is the source of an eliminate we still
3044 think can be performed, note it cannot be performed since we don't
3045 know how this register is used. */
3046 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3047 if (ep->from_rtx == XEXP (x, 0))
3048 ep->can_eliminate = 0;
3050 elimination_effects (XEXP (x, 0), mem_mode);
3054 /* If clobbering a register that is the replacement register for an
3055 elimination we still think can be performed, note that it cannot
3056 be performed. Otherwise, we need not be concerned about it. */
3057 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3058 if (ep->to_rtx == XEXP (x, 0))
3059 ep->can_eliminate = 0;
3061 elimination_effects (XEXP (x, 0), mem_mode);
3065 /* Check for setting a register that we know about. */
3066 if (REG_P (SET_DEST (x)))
3068 /* See if this is setting the replacement register for an
3071 If DEST is the hard frame pointer, we do nothing because we
3072 assume that all assignments to the frame pointer are for
3073 non-local gotos and are being done at a time when they are valid
3074 and do not disturb anything else. Some machines want to
3075 eliminate a fake argument pointer (or even a fake frame pointer)
3076 with either the real frame or the stack pointer. Assignments to
3077 the hard frame pointer must not prevent this elimination. */
3079 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3081 if (ep->to_rtx == SET_DEST (x)
3082 && SET_DEST (x) != hard_frame_pointer_rtx)
3084 /* If it is being incremented, adjust the offset. Otherwise,
3085 this elimination can't be done. */
3086 rtx src = SET_SRC (x);
3088 if (GET_CODE (src) == PLUS
3089 && XEXP (src, 0) == SET_DEST (x)
3090 && CONST_INT_P (XEXP (src, 1)))
3091 ep->offset -= INTVAL (XEXP (src, 1));
3093 ep->can_eliminate = 0;
3097 elimination_effects (SET_DEST (x), VOIDmode);
3098 elimination_effects (SET_SRC (x), VOIDmode);
3102 /* Our only special processing is to pass the mode of the MEM to our
3104 elimination_effects (XEXP (x, 0), GET_MODE (x));
3111 fmt = GET_RTX_FORMAT (code);
3112 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3115 elimination_effects (XEXP (x, i), mem_mode);
3116 else if (*fmt == 'E')
3117 for (j = 0; j < XVECLEN (x, i); j++)
3118 elimination_effects (XVECEXP (x, i, j), mem_mode);
3122 /* Descend through rtx X and verify that no references to eliminable registers
3123 remain. If any do remain, mark the involved register as not
3127 check_eliminable_occurrences (rtx x)
3136 code = GET_CODE (x);
3138 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3140 struct elim_table *ep;
3142 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3143 if (ep->from_rtx == x)
3144 ep->can_eliminate = 0;
3148 fmt = GET_RTX_FORMAT (code);
3149 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3152 check_eliminable_occurrences (XEXP (x, i));
3153 else if (*fmt == 'E')
3156 for (j = 0; j < XVECLEN (x, i); j++)
3157 check_eliminable_occurrences (XVECEXP (x, i, j));
3162 /* Scan INSN and eliminate all eliminable registers in it.
3164 If REPLACE is nonzero, do the replacement destructively. Also
3165 delete the insn as dead it if it is setting an eliminable register.
3167 If REPLACE is zero, do all our allocations in reload_obstack.
3169 If no eliminations were done and this insn doesn't require any elimination
3170 processing (these are not identical conditions: it might be updating sp,
3171 but not referencing fp; this needs to be seen during reload_as_needed so
3172 that the offset between fp and sp can be taken into consideration), zero
3173 is returned. Otherwise, 1 is returned. */
3176 eliminate_regs_in_insn (rtx insn, int replace)
3178 int icode = recog_memoized (insn);
3179 rtx old_body = PATTERN (insn);
3180 int insn_is_asm = asm_noperands (old_body) >= 0;
3181 rtx old_set = single_set (insn);
3185 rtx substed_operand[MAX_RECOG_OPERANDS];
3186 rtx orig_operand[MAX_RECOG_OPERANDS];
3187 struct elim_table *ep;
3188 rtx plus_src, plus_cst_src;
3190 if (! insn_is_asm && icode < 0)
3192 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3193 || GET_CODE (PATTERN (insn)) == CLOBBER
3194 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3195 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3196 || GET_CODE (PATTERN (insn)) == ASM_INPUT
3197 || DEBUG_INSN_P (insn));
3201 if (old_set != 0 && REG_P (SET_DEST (old_set))
3202 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3204 /* Check for setting an eliminable register. */
3205 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3206 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3208 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3209 /* If this is setting the frame pointer register to the
3210 hardware frame pointer register and this is an elimination
3211 that will be done (tested above), this insn is really
3212 adjusting the frame pointer downward to compensate for
3213 the adjustment done before a nonlocal goto. */
3214 if (ep->from == FRAME_POINTER_REGNUM
3215 && ep->to == HARD_FRAME_POINTER_REGNUM)
3217 rtx base = SET_SRC (old_set);
3218 rtx base_insn = insn;
3219 HOST_WIDE_INT offset = 0;
3221 while (base != ep->to_rtx)
3223 rtx prev_insn, prev_set;
3225 if (GET_CODE (base) == PLUS
3226 && CONST_INT_P (XEXP (base, 1)))
3228 offset += INTVAL (XEXP (base, 1));
3229 base = XEXP (base, 0);
3231 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3232 && (prev_set = single_set (prev_insn)) != 0
3233 && rtx_equal_p (SET_DEST (prev_set), base))
3235 base = SET_SRC (prev_set);
3236 base_insn = prev_insn;
3242 if (base == ep->to_rtx)
3245 = plus_constant (ep->to_rtx, offset - ep->offset);
3247 new_body = old_body;
3250 new_body = copy_insn (old_body);
3251 if (REG_NOTES (insn))
3252 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3254 PATTERN (insn) = new_body;
3255 old_set = single_set (insn);
3257 /* First see if this insn remains valid when we
3258 make the change. If not, keep the INSN_CODE
3259 the same and let reload fit it up. */
3260 validate_change (insn, &SET_SRC (old_set), src, 1);
3261 validate_change (insn, &SET_DEST (old_set),
3263 if (! apply_change_group ())
3265 SET_SRC (old_set) = src;
3266 SET_DEST (old_set) = ep->to_rtx;
3275 /* In this case this insn isn't serving a useful purpose. We
3276 will delete it in reload_as_needed once we know that this
3277 elimination is, in fact, being done.
3279 If REPLACE isn't set, we can't delete this insn, but needn't
3280 process it since it won't be used unless something changes. */
3283 delete_dead_insn (insn);
3291 /* We allow one special case which happens to work on all machines we
3292 currently support: a single set with the source or a REG_EQUAL
3293 note being a PLUS of an eliminable register and a constant. */
3294 plus_src = plus_cst_src = 0;
3295 if (old_set && REG_P (SET_DEST (old_set)))
3297 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3298 plus_src = SET_SRC (old_set);
3299 /* First see if the source is of the form (plus (...) CST). */
3301 && CONST_INT_P (XEXP (plus_src, 1)))
3302 plus_cst_src = plus_src;
3303 else if (REG_P (SET_SRC (old_set))
3306 /* Otherwise, see if we have a REG_EQUAL note of the form
3307 (plus (...) CST). */
3309 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3311 if ((REG_NOTE_KIND (links) == REG_EQUAL
3312 || REG_NOTE_KIND (links) == REG_EQUIV)
3313 && GET_CODE (XEXP (links, 0)) == PLUS
3314 && CONST_INT_P (XEXP (XEXP (links, 0), 1)))
3316 plus_cst_src = XEXP (links, 0);
3322 /* Check that the first operand of the PLUS is a hard reg or
3323 the lowpart subreg of one. */
3326 rtx reg = XEXP (plus_cst_src, 0);
3327 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3328 reg = SUBREG_REG (reg);
3330 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3336 rtx reg = XEXP (plus_cst_src, 0);
3337 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3339 if (GET_CODE (reg) == SUBREG)
3340 reg = SUBREG_REG (reg);
3342 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3343 if (ep->from_rtx == reg && ep->can_eliminate)
3345 rtx to_rtx = ep->to_rtx;
3346 offset += ep->offset;
3347 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3349 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3350 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3352 /* If we have a nonzero offset, and the source is already
3353 a simple REG, the following transformation would
3354 increase the cost of the insn by replacing a simple REG
3355 with (plus (reg sp) CST). So try only when we already
3356 had a PLUS before. */
3357 if (offset == 0 || plus_src)
3359 rtx new_src = plus_constant (to_rtx, offset);
3361 new_body = old_body;
3364 new_body = copy_insn (old_body);
3365 if (REG_NOTES (insn))
3366 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3368 PATTERN (insn) = new_body;
3369 old_set = single_set (insn);
3371 /* First see if this insn remains valid when we make the
3372 change. If not, try to replace the whole pattern with
3373 a simple set (this may help if the original insn was a
3374 PARALLEL that was only recognized as single_set due to
3375 REG_UNUSED notes). If this isn't valid either, keep
3376 the INSN_CODE the same and let reload fix it up. */
3377 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3379 rtx new_pat = gen_rtx_SET (VOIDmode,
3380 SET_DEST (old_set), new_src);
3382 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3383 SET_SRC (old_set) = new_src;
3390 /* This can't have an effect on elimination offsets, so skip right
3396 /* Determine the effects of this insn on elimination offsets. */
3397 elimination_effects (old_body, VOIDmode);
3399 /* Eliminate all eliminable registers occurring in operands that
3400 can be handled by reload. */
3401 extract_insn (insn);
3402 for (i = 0; i < recog_data.n_operands; i++)
3404 orig_operand[i] = recog_data.operand[i];
3405 substed_operand[i] = recog_data.operand[i];
3407 /* For an asm statement, every operand is eliminable. */
3408 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3410 bool is_set_src, in_plus;
3412 /* Check for setting a register that we know about. */
3413 if (recog_data.operand_type[i] != OP_IN
3414 && REG_P (orig_operand[i]))
3416 /* If we are assigning to a register that can be eliminated, it
3417 must be as part of a PARALLEL, since the code above handles
3418 single SETs. We must indicate that we can no longer
3419 eliminate this reg. */
3420 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3422 if (ep->from_rtx == orig_operand[i])
3423 ep->can_eliminate = 0;
3426 /* Companion to the above plus substitution, we can allow
3427 invariants as the source of a plain move. */
3429 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3433 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3434 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3438 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3439 replace ? insn : NULL_RTX,
3440 is_set_src || in_plus);
3441 if (substed_operand[i] != orig_operand[i])
3443 /* Terminate the search in check_eliminable_occurrences at
3445 *recog_data.operand_loc[i] = 0;
3447 /* If an output operand changed from a REG to a MEM and INSN is an
3448 insn, write a CLOBBER insn. */
3449 if (recog_data.operand_type[i] != OP_IN
3450 && REG_P (orig_operand[i])
3451 && MEM_P (substed_operand[i])
3453 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3457 for (i = 0; i < recog_data.n_dups; i++)
3458 *recog_data.dup_loc[i]
3459 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3461 /* If any eliminable remain, they aren't eliminable anymore. */
3462 check_eliminable_occurrences (old_body);
3464 /* Substitute the operands; the new values are in the substed_operand
3466 for (i = 0; i < recog_data.n_operands; i++)
3467 *recog_data.operand_loc[i] = substed_operand[i];
3468 for (i = 0; i < recog_data.n_dups; i++)
3469 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3471 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3472 re-recognize the insn. We do this in case we had a simple addition
3473 but now can do this as a load-address. This saves an insn in this
3475 If re-recognition fails, the old insn code number will still be used,
3476 and some register operands may have changed into PLUS expressions.
3477 These will be handled by find_reloads by loading them into a register
3482 /* If we aren't replacing things permanently and we changed something,
3483 make another copy to ensure that all the RTL is new. Otherwise
3484 things can go wrong if find_reload swaps commutative operands
3485 and one is inside RTL that has been copied while the other is not. */
3486 new_body = old_body;
3489 new_body = copy_insn (old_body);
3490 if (REG_NOTES (insn))
3491 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3493 PATTERN (insn) = new_body;
3495 /* If we had a move insn but now we don't, rerecognize it. This will
3496 cause spurious re-recognition if the old move had a PARALLEL since
3497 the new one still will, but we can't call single_set without
3498 having put NEW_BODY into the insn and the re-recognition won't
3499 hurt in this rare case. */
3500 /* ??? Why this huge if statement - why don't we just rerecognize the
3504 && ((REG_P (SET_SRC (old_set))
3505 && (GET_CODE (new_body) != SET
3506 || !REG_P (SET_SRC (new_body))))
3507 /* If this was a load from or store to memory, compare
3508 the MEM in recog_data.operand to the one in the insn.
3509 If they are not equal, then rerecognize the insn. */
3511 && ((MEM_P (SET_SRC (old_set))
3512 && SET_SRC (old_set) != recog_data.operand[1])
3513 || (MEM_P (SET_DEST (old_set))
3514 && SET_DEST (old_set) != recog_data.operand[0])))
3515 /* If this was an add insn before, rerecognize. */
3516 || GET_CODE (SET_SRC (old_set)) == PLUS))
3518 int new_icode = recog (PATTERN (insn), insn, 0);
3520 INSN_CODE (insn) = new_icode;
3524 /* Restore the old body. If there were any changes to it, we made a copy
3525 of it while the changes were still in place, so we'll correctly return
3526 a modified insn below. */
3529 /* Restore the old body. */
3530 for (i = 0; i < recog_data.n_operands; i++)
3531 *recog_data.operand_loc[i] = orig_operand[i];
3532 for (i = 0; i < recog_data.n_dups; i++)
3533 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3536 /* Update all elimination pairs to reflect the status after the current
3537 insn. The changes we make were determined by the earlier call to
3538 elimination_effects.
3540 We also detect cases where register elimination cannot be done,
3541 namely, if a register would be both changed and referenced outside a MEM
3542 in the resulting insn since such an insn is often undefined and, even if
3543 not, we cannot know what meaning will be given to it. Note that it is
3544 valid to have a register used in an address in an insn that changes it
3545 (presumably with a pre- or post-increment or decrement).
3547 If anything changes, return nonzero. */
3549 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3551 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3552 ep->can_eliminate = 0;
3554 ep->ref_outside_mem = 0;
3556 if (ep->previous_offset != ep->offset)
3561 /* If we changed something, perform elimination in REG_NOTES. This is
3562 needed even when REPLACE is zero because a REG_DEAD note might refer
3563 to a register that we eliminate and could cause a different number
3564 of spill registers to be needed in the final reload pass than in
3566 if (val && REG_NOTES (insn) != 0)
3568 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3573 /* Loop through all elimination pairs.
3574 Recalculate the number not at initial offset.
3576 Compute the maximum offset (minimum offset if the stack does not
3577 grow downward) for each elimination pair. */
3580 update_eliminable_offsets (void)
3582 struct elim_table *ep;
3584 num_not_at_initial_offset = 0;
3585 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3587 ep->previous_offset = ep->offset;
3588 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3589 num_not_at_initial_offset++;
3593 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3594 replacement we currently believe is valid, mark it as not eliminable if X
3595 modifies DEST in any way other than by adding a constant integer to it.
3597 If DEST is the frame pointer, we do nothing because we assume that
3598 all assignments to the hard frame pointer are nonlocal gotos and are being
3599 done at a time when they are valid and do not disturb anything else.
3600 Some machines want to eliminate a fake argument pointer with either the
3601 frame or stack pointer. Assignments to the hard frame pointer must not
3602 prevent this elimination.
3604 Called via note_stores from reload before starting its passes to scan
3605 the insns of the function. */
3608 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3612 /* A SUBREG of a hard register here is just changing its mode. We should
3613 not see a SUBREG of an eliminable hard register, but check just in
3615 if (GET_CODE (dest) == SUBREG)
3616 dest = SUBREG_REG (dest);
3618 if (dest == hard_frame_pointer_rtx)
3621 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3622 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3623 && (GET_CODE (x) != SET
3624 || GET_CODE (SET_SRC (x)) != PLUS
3625 || XEXP (SET_SRC (x), 0) != dest
3626 || !CONST_INT_P (XEXP (SET_SRC (x), 1))))
3628 reg_eliminate[i].can_eliminate_previous
3629 = reg_eliminate[i].can_eliminate = 0;
3634 /* Verify that the initial elimination offsets did not change since the
3635 last call to set_initial_elim_offsets. This is used to catch cases
3636 where something illegal happened during reload_as_needed that could
3637 cause incorrect code to be generated if we did not check for it. */
3640 verify_initial_elim_offsets (void)
3644 if (!num_eliminable)
3647 #ifdef ELIMINABLE_REGS
3649 struct elim_table *ep;
3651 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3653 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3654 if (t != ep->initial_offset)
3659 INITIAL_FRAME_POINTER_OFFSET (t);
3660 if (t != reg_eliminate[0].initial_offset)
3667 /* Reset all offsets on eliminable registers to their initial values. */
3670 set_initial_elim_offsets (void)
3672 struct elim_table *ep = reg_eliminate;
3674 #ifdef ELIMINABLE_REGS
3675 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3677 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3678 ep->previous_offset = ep->offset = ep->initial_offset;
3681 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3682 ep->previous_offset = ep->offset = ep->initial_offset;
3685 num_not_at_initial_offset = 0;
3688 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3691 set_initial_eh_label_offset (rtx label)
3693 set_label_offsets (label, NULL_RTX, 1);
3696 /* Initialize the known label offsets.
3697 Set a known offset for each forced label to be at the initial offset
3698 of each elimination. We do this because we assume that all
3699 computed jumps occur from a location where each elimination is
3700 at its initial offset.
3701 For all other labels, show that we don't know the offsets. */
3704 set_initial_label_offsets (void)
3707 memset (offsets_known_at, 0, num_labels);
3709 for (x = forced_labels; x; x = XEXP (x, 1))
3711 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3713 for_each_eh_label (set_initial_eh_label_offset);
3716 /* Set all elimination offsets to the known values for the code label given
3720 set_offsets_for_label (rtx insn)
3723 int label_nr = CODE_LABEL_NUMBER (insn);
3724 struct elim_table *ep;
3726 num_not_at_initial_offset = 0;
3727 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3729 ep->offset = ep->previous_offset
3730 = offsets_at[label_nr - first_label_num][i];
3731 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3732 num_not_at_initial_offset++;
3736 /* See if anything that happened changes which eliminations are valid.
3737 For example, on the SPARC, whether or not the frame pointer can
3738 be eliminated can depend on what registers have been used. We need
3739 not check some conditions again (such as flag_omit_frame_pointer)
3740 since they can't have changed. */
3743 update_eliminables (HARD_REG_SET *pset)
3745 int previous_frame_pointer_needed = frame_pointer_needed;
3746 struct elim_table *ep;
3748 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3749 if ((ep->from == HARD_FRAME_POINTER_REGNUM
3750 && targetm.frame_pointer_required ())
3751 #ifdef ELIMINABLE_REGS
3752 || ! targetm.can_eliminate (ep->from, ep->to)
3755 ep->can_eliminate = 0;
3757 /* Look for the case where we have discovered that we can't replace
3758 register A with register B and that means that we will now be
3759 trying to replace register A with register C. This means we can
3760 no longer replace register C with register B and we need to disable
3761 such an elimination, if it exists. This occurs often with A == ap,
3762 B == sp, and C == fp. */
3764 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3766 struct elim_table *op;
3769 if (! ep->can_eliminate && ep->can_eliminate_previous)
3771 /* Find the current elimination for ep->from, if there is a
3773 for (op = reg_eliminate;
3774 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3775 if (op->from == ep->from && op->can_eliminate)
3781 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3783 for (op = reg_eliminate;
3784 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3785 if (op->from == new_to && op->to == ep->to)
3786 op->can_eliminate = 0;
3790 /* See if any registers that we thought we could eliminate the previous
3791 time are no longer eliminable. If so, something has changed and we
3792 must spill the register. Also, recompute the number of eliminable
3793 registers and see if the frame pointer is needed; it is if there is
3794 no elimination of the frame pointer that we can perform. */
3796 frame_pointer_needed = 1;
3797 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3799 if (ep->can_eliminate
3800 && ep->from == FRAME_POINTER_REGNUM
3801 && ep->to != HARD_FRAME_POINTER_REGNUM
3802 && (! SUPPORTS_STACK_ALIGNMENT
3803 || ! crtl->stack_realign_needed))
3804 frame_pointer_needed = 0;
3806 if (! ep->can_eliminate && ep->can_eliminate_previous)
3808 ep->can_eliminate_previous = 0;
3809 SET_HARD_REG_BIT (*pset, ep->from);
3814 /* If we didn't need a frame pointer last time, but we do now, spill
3815 the hard frame pointer. */
3816 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3817 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3820 /* Return true if X is used as the target register of an elimination. */
3823 elimination_target_reg_p (rtx x)
3825 struct elim_table *ep;
3827 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3828 if (ep->to_rtx == x && ep->can_eliminate)
3834 /* Initialize the table of registers to eliminate.
3835 Pre-condition: global flag frame_pointer_needed has been set before
3836 calling this function. */
3839 init_elim_table (void)
3841 struct elim_table *ep;
3842 #ifdef ELIMINABLE_REGS
3843 const struct elim_table_1 *ep1;
3847 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3851 #ifdef ELIMINABLE_REGS
3852 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3853 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3855 ep->from = ep1->from;
3857 ep->can_eliminate = ep->can_eliminate_previous
3858 = (targetm.can_eliminate (ep->from, ep->to)
3859 && ! (ep->to == STACK_POINTER_REGNUM
3860 && frame_pointer_needed
3861 && (! SUPPORTS_STACK_ALIGNMENT
3862 || ! stack_realign_fp)));
3865 reg_eliminate[0].from = reg_eliminate_1[0].from;
3866 reg_eliminate[0].to = reg_eliminate_1[0].to;
3867 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3868 = ! frame_pointer_needed;
3871 /* Count the number of eliminable registers and build the FROM and TO
3872 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3873 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3874 We depend on this. */
3875 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3877 num_eliminable += ep->can_eliminate;
3878 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3879 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3883 /* Kick all pseudos out of hard register REGNO.
3885 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3886 because we found we can't eliminate some register. In the case, no pseudos
3887 are allowed to be in the register, even if they are only in a block that
3888 doesn't require spill registers, unlike the case when we are spilling this
3889 hard reg to produce another spill register.
3891 Return nonzero if any pseudos needed to be kicked out. */
3894 spill_hard_reg (unsigned int regno, int cant_eliminate)
3900 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3901 df_set_regs_ever_live (regno, true);
3904 /* Spill every pseudo reg that was allocated to this reg
3905 or to something that overlaps this reg. */
3907 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3908 if (reg_renumber[i] >= 0
3909 && (unsigned int) reg_renumber[i] <= regno
3910 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3911 SET_REGNO_REG_SET (&spilled_pseudos, i);
3914 /* After find_reload_regs has been run for all insn that need reloads,
3915 and/or spill_hard_regs was called, this function is used to actually
3916 spill pseudo registers and try to reallocate them. It also sets up the
3917 spill_regs array for use by choose_reload_regs. */
3920 finish_spills (int global)
3922 struct insn_chain *chain;
3923 int something_changed = 0;
3925 reg_set_iterator rsi;
3927 /* Build the spill_regs array for the function. */
3928 /* If there are some registers still to eliminate and one of the spill regs
3929 wasn't ever used before, additional stack space may have to be
3930 allocated to store this register. Thus, we may have changed the offset
3931 between the stack and frame pointers, so mark that something has changed.
3933 One might think that we need only set VAL to 1 if this is a call-used
3934 register. However, the set of registers that must be saved by the
3935 prologue is not identical to the call-used set. For example, the
3936 register used by the call insn for the return PC is a call-used register,
3937 but must be saved by the prologue. */
3940 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3941 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3943 spill_reg_order[i] = n_spills;
3944 spill_regs[n_spills++] = i;
3945 if (num_eliminable && ! df_regs_ever_live_p (i))
3946 something_changed = 1;
3947 df_set_regs_ever_live (i, true);
3950 spill_reg_order[i] = -1;
3952 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3953 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3955 /* Record the current hard register the pseudo is allocated to
3956 in pseudo_previous_regs so we avoid reallocating it to the
3957 same hard reg in a later pass. */
3958 gcc_assert (reg_renumber[i] >= 0);
3960 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3961 /* Mark it as no longer having a hard register home. */
3962 reg_renumber[i] = -1;
3963 if (ira_conflicts_p)
3964 /* Inform IRA about the change. */
3965 ira_mark_allocation_change (i);
3966 /* We will need to scan everything again. */
3967 something_changed = 1;
3970 /* Retry global register allocation if possible. */
3971 if (global && ira_conflicts_p)
3975 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3976 /* For every insn that needs reloads, set the registers used as spill
3977 regs in pseudo_forbidden_regs for every pseudo live across the
3979 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3981 EXECUTE_IF_SET_IN_REG_SET
3982 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3984 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3985 chain->used_spill_regs);
3987 EXECUTE_IF_SET_IN_REG_SET
3988 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3990 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3991 chain->used_spill_regs);
3995 /* Retry allocating the pseudos spilled in IRA and the
3996 reload. For each reg, merge the various reg sets that
3997 indicate which hard regs can't be used, and call
3998 ira_reassign_pseudos. */
3999 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
4000 if (reg_old_renumber[i] != reg_renumber[i])
4002 if (reg_renumber[i] < 0)
4003 temp_pseudo_reg_arr[n++] = i;
4005 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
4007 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
4008 bad_spill_regs_global,
4009 pseudo_forbidden_regs, pseudo_previous_regs,
4011 something_changed = 1;
4013 /* Fix up the register information in the insn chain.
4014 This involves deleting those of the spilled pseudos which did not get
4015 a new hard register home from the live_{before,after} sets. */
4016 for (chain = reload_insn_chain; chain; chain = chain->next)
4018 HARD_REG_SET used_by_pseudos;
4019 HARD_REG_SET used_by_pseudos2;
4021 if (! ira_conflicts_p)
4023 /* Don't do it for IRA because IRA and the reload still can
4024 assign hard registers to the spilled pseudos on next
4025 reload iterations. */
4026 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
4027 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
4029 /* Mark any unallocated hard regs as available for spills. That
4030 makes inheritance work somewhat better. */
4031 if (chain->need_reload)
4033 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
4034 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
4035 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
4037 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
4038 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
4039 /* Value of chain->used_spill_regs from previous iteration
4040 may be not included in the value calculated here because
4041 of possible removing caller-saves insns (see function
4042 delete_caller_save_insns. */
4043 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
4044 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4048 CLEAR_REG_SET (&changed_allocation_pseudos);
4049 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4050 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4052 int regno = reg_renumber[i];
4053 if (reg_old_renumber[i] == regno)
4056 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4058 alter_reg (i, reg_old_renumber[i], false);
4059 reg_old_renumber[i] = regno;
4063 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4065 fprintf (dump_file, " Register %d now in %d.\n\n",
4066 i, reg_renumber[i]);
4070 return something_changed;
4073 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4076 scan_paradoxical_subregs (rtx x)
4080 enum rtx_code code = GET_CODE (x);
4091 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4099 if (REG_P (SUBREG_REG (x))
4100 && (GET_MODE_SIZE (GET_MODE (x))
4101 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4103 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4104 = GET_MODE_SIZE (GET_MODE (x));
4105 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4113 fmt = GET_RTX_FORMAT (code);
4114 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4117 scan_paradoxical_subregs (XEXP (x, i));
4118 else if (fmt[i] == 'E')
4121 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4122 scan_paradoxical_subregs (XVECEXP (x, i, j));
4127 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4128 examine all of the reload insns between PREV and NEXT exclusive, and
4129 annotate all that may trap. */
4132 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4134 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4137 if (!insn_could_throw_p (insn))
4138 remove_note (insn, note);
4139 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next);
4142 /* Reload pseudo-registers into hard regs around each insn as needed.
4143 Additional register load insns are output before the insn that needs it
4144 and perhaps store insns after insns that modify the reloaded pseudo reg.
4146 reg_last_reload_reg and reg_reloaded_contents keep track of
4147 which registers are already available in reload registers.
4148 We update these for the reloads that we perform,
4149 as the insns are scanned. */
4152 reload_as_needed (int live_known)
4154 struct insn_chain *chain;
4155 #if defined (AUTO_INC_DEC)
4160 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4161 memset (spill_reg_store, 0, sizeof spill_reg_store);
4162 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4163 INIT_REG_SET (®_has_output_reload);
4164 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4165 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4167 set_initial_elim_offsets ();
4169 for (chain = reload_insn_chain; chain; chain = chain->next)
4172 rtx insn = chain->insn;
4173 rtx old_next = NEXT_INSN (insn);
4175 rtx old_prev = PREV_INSN (insn);
4178 /* If we pass a label, copy the offsets from the label information
4179 into the current offsets of each elimination. */
4181 set_offsets_for_label (insn);
4183 else if (INSN_P (insn))
4185 regset_head regs_to_forget;
4186 INIT_REG_SET (®s_to_forget);
4187 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4189 /* If this is a USE and CLOBBER of a MEM, ensure that any
4190 references to eliminable registers have been removed. */
4192 if ((GET_CODE (PATTERN (insn)) == USE
4193 || GET_CODE (PATTERN (insn)) == CLOBBER)
4194 && MEM_P (XEXP (PATTERN (insn), 0)))
4195 XEXP (XEXP (PATTERN (insn), 0), 0)
4196 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4197 GET_MODE (XEXP (PATTERN (insn), 0)),
4200 /* If we need to do register elimination processing, do so.
4201 This might delete the insn, in which case we are done. */
4202 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4204 eliminate_regs_in_insn (insn, 1);
4207 update_eliminable_offsets ();
4208 CLEAR_REG_SET (®s_to_forget);
4213 /* If need_elim is nonzero but need_reload is zero, one might think
4214 that we could simply set n_reloads to 0. However, find_reloads
4215 could have done some manipulation of the insn (such as swapping
4216 commutative operands), and these manipulations are lost during
4217 the first pass for every insn that needs register elimination.
4218 So the actions of find_reloads must be redone here. */
4220 if (! chain->need_elim && ! chain->need_reload
4221 && ! chain->need_operand_change)
4223 /* First find the pseudo regs that must be reloaded for this insn.
4224 This info is returned in the tables reload_... (see reload.h).
4225 Also modify the body of INSN by substituting RELOAD
4226 rtx's for those pseudo regs. */
4229 CLEAR_REG_SET (®_has_output_reload);
4230 CLEAR_HARD_REG_SET (reg_is_output_reload);
4232 find_reloads (insn, 1, spill_indirect_levels, live_known,
4238 rtx next = NEXT_INSN (insn);
4241 prev = PREV_INSN (insn);
4243 /* Now compute which reload regs to reload them into. Perhaps
4244 reusing reload regs from previous insns, or else output
4245 load insns to reload them. Maybe output store insns too.
4246 Record the choices of reload reg in reload_reg_rtx. */
4247 choose_reload_regs (chain);
4249 /* Merge any reloads that we didn't combine for fear of
4250 increasing the number of spill registers needed but now
4251 discover can be safely merged. */
4252 if (SMALL_REGISTER_CLASSES)
4253 merge_assigned_reloads (insn);
4255 /* Generate the insns to reload operands into or out of
4256 their reload regs. */
4257 emit_reload_insns (chain);
4259 /* Substitute the chosen reload regs from reload_reg_rtx
4260 into the insn's body (or perhaps into the bodies of other
4261 load and store insn that we just made for reloading
4262 and that we moved the structure into). */
4263 subst_reloads (insn);
4265 /* Adjust the exception region notes for loads and stores. */
4266 if (flag_non_call_exceptions && !CALL_P (insn))
4267 fixup_eh_region_note (insn, prev, next);
4269 /* If this was an ASM, make sure that all the reload insns
4270 we have generated are valid. If not, give an error
4272 if (asm_noperands (PATTERN (insn)) >= 0)
4273 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4274 if (p != insn && INSN_P (p)
4275 && GET_CODE (PATTERN (p)) != USE
4276 && (recog_memoized (p) < 0
4277 || (extract_insn (p), ! constrain_operands (1))))
4279 error_for_asm (insn,
4280 "%<asm%> operand requires "
4281 "impossible reload");
4286 if (num_eliminable && chain->need_elim)
4287 update_eliminable_offsets ();
4289 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4290 is no longer validly lying around to save a future reload.
4291 Note that this does not detect pseudos that were reloaded
4292 for this insn in order to be stored in
4293 (obeying register constraints). That is correct; such reload
4294 registers ARE still valid. */
4295 forget_marked_reloads (®s_to_forget);
4296 CLEAR_REG_SET (®s_to_forget);
4298 /* There may have been CLOBBER insns placed after INSN. So scan
4299 between INSN and NEXT and use them to forget old reloads. */
4300 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4301 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4302 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4305 /* Likewise for regs altered by auto-increment in this insn.
4306 REG_INC notes have been changed by reloading:
4307 find_reloads_address_1 records substitutions for them,
4308 which have been performed by subst_reloads above. */
4309 for (i = n_reloads - 1; i >= 0; i--)
4311 rtx in_reg = rld[i].in_reg;
4314 enum rtx_code code = GET_CODE (in_reg);
4315 /* PRE_INC / PRE_DEC will have the reload register ending up
4316 with the same value as the stack slot, but that doesn't
4317 hold true for POST_INC / POST_DEC. Either we have to
4318 convert the memory access to a true POST_INC / POST_DEC,
4319 or we can't use the reload register for inheritance. */
4320 if ((code == POST_INC || code == POST_DEC)
4321 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4322 REGNO (rld[i].reg_rtx))
4323 /* Make sure it is the inc/dec pseudo, and not
4324 some other (e.g. output operand) pseudo. */
4325 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4326 == REGNO (XEXP (in_reg, 0))))
4329 rtx reload_reg = rld[i].reg_rtx;
4330 enum machine_mode mode = GET_MODE (reload_reg);
4334 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4336 /* We really want to ignore REG_INC notes here, so
4337 use PATTERN (p) as argument to reg_set_p . */
4338 if (reg_set_p (reload_reg, PATTERN (p)))
4340 n = count_occurrences (PATTERN (p), reload_reg, 0);
4346 = gen_rtx_fmt_e (code, mode, reload_reg);
4348 validate_replace_rtx_group (reload_reg,
4350 n = verify_changes (0);
4352 /* We must also verify that the constraints
4353 are met after the replacement. Make sure
4354 extract_insn is only called for an insn
4355 where the replacements were found to be
4360 n = constrain_operands (1);
4363 /* If the constraints were not met, then
4364 undo the replacement, else confirm it. */
4368 confirm_change_group ();
4374 add_reg_note (p, REG_INC, reload_reg);
4375 /* Mark this as having an output reload so that the
4376 REG_INC processing code below won't invalidate
4377 the reload for inheritance. */
4378 SET_HARD_REG_BIT (reg_is_output_reload,
4379 REGNO (reload_reg));
4380 SET_REGNO_REG_SET (®_has_output_reload,
4381 REGNO (XEXP (in_reg, 0)));
4384 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4387 else if ((code == PRE_INC || code == PRE_DEC)
4388 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4389 REGNO (rld[i].reg_rtx))
4390 /* Make sure it is the inc/dec pseudo, and not
4391 some other (e.g. output operand) pseudo. */
4392 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4393 == REGNO (XEXP (in_reg, 0))))
4395 SET_HARD_REG_BIT (reg_is_output_reload,
4396 REGNO (rld[i].reg_rtx));
4397 SET_REGNO_REG_SET (®_has_output_reload,
4398 REGNO (XEXP (in_reg, 0)));
4400 else if (code == PRE_INC || code == PRE_DEC
4401 || code == POST_INC || code == POST_DEC)
4403 int in_regno = REGNO (XEXP (in_reg, 0));
4405 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4408 bool forget_p = true;
4410 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4411 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4414 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4417 if (x == reg_reloaded_insn[in_hard_regno])
4423 /* If for some reasons, we didn't set up
4424 reg_last_reload_reg in this insn,
4425 invalidate inheritance from previous
4426 insns for the incremented/decremented
4427 register. Such registers will be not in
4428 reg_has_output_reload. Invalidate it
4429 also if the corresponding element in
4430 reg_reloaded_insn is also
4433 forget_old_reloads_1 (XEXP (in_reg, 0),
4439 /* If a pseudo that got a hard register is auto-incremented,
4440 we must purge records of copying it into pseudos without
4442 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4443 if (REG_NOTE_KIND (x) == REG_INC)
4445 /* See if this pseudo reg was reloaded in this insn.
4446 If so, its last-reload info is still valid
4447 because it is based on this insn's reload. */
4448 for (i = 0; i < n_reloads; i++)
4449 if (rld[i].out == XEXP (x, 0))
4453 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4457 /* A reload reg's contents are unknown after a label. */
4459 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4461 /* Don't assume a reload reg is still good after a call insn
4462 if it is a call-used reg, or if it contains a value that will
4463 be partially clobbered by the call. */
4464 else if (CALL_P (insn))
4466 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4467 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4472 free (reg_last_reload_reg);
4473 CLEAR_REG_SET (®_has_output_reload);
4476 /* Discard all record of any value reloaded from X,
4477 or reloaded in X from someplace else;
4478 unless X is an output reload reg of the current insn.
4480 X may be a hard reg (the reload reg)
4481 or it may be a pseudo reg that was reloaded from.
4483 When DATA is non-NULL just mark the registers in regset
4484 to be forgotten later. */
4487 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4492 regset regs = (regset) data;
4494 /* note_stores does give us subregs of hard regs,
4495 subreg_regno_offset requires a hard reg. */
4496 while (GET_CODE (x) == SUBREG)
4498 /* We ignore the subreg offset when calculating the regno,
4499 because we are using the entire underlying hard register
4509 if (regno >= FIRST_PSEUDO_REGISTER)
4515 nr = hard_regno_nregs[regno][GET_MODE (x)];
4516 /* Storing into a spilled-reg invalidates its contents.
4517 This can happen if a block-local pseudo is allocated to that reg
4518 and it wasn't spilled because this block's total need is 0.
4519 Then some insn might have an optional reload and use this reg. */
4521 for (i = 0; i < nr; i++)
4522 /* But don't do this if the reg actually serves as an output
4523 reload reg in the current instruction. */
4525 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4527 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4528 spill_reg_store[regno + i] = 0;
4534 SET_REGNO_REG_SET (regs, regno + nr);
4537 /* Since value of X has changed,
4538 forget any value previously copied from it. */
4541 /* But don't forget a copy if this is the output reload
4542 that establishes the copy's validity. */
4544 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4545 reg_last_reload_reg[regno + nr] = 0;
4549 /* Forget the reloads marked in regset by previous function. */
4551 forget_marked_reloads (regset regs)
4554 reg_set_iterator rsi;
4555 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4557 if (reg < FIRST_PSEUDO_REGISTER
4558 /* But don't do this if the reg actually serves as an output
4559 reload reg in the current instruction. */
4561 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4563 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4564 spill_reg_store[reg] = 0;
4567 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4568 reg_last_reload_reg[reg] = 0;
4572 /* The following HARD_REG_SETs indicate when each hard register is
4573 used for a reload of various parts of the current insn. */
4575 /* If reg is unavailable for all reloads. */
4576 static HARD_REG_SET reload_reg_unavailable;
4577 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4578 static HARD_REG_SET reload_reg_used;
4579 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4580 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4581 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4582 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4583 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4584 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4585 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4586 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4587 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4588 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4589 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4590 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4591 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4592 static HARD_REG_SET reload_reg_used_in_op_addr;
4593 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4594 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4595 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4596 static HARD_REG_SET reload_reg_used_in_insn;
4597 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4598 static HARD_REG_SET reload_reg_used_in_other_addr;
4600 /* If reg is in use as a reload reg for any sort of reload. */
4601 static HARD_REG_SET reload_reg_used_at_all;
4603 /* If reg is use as an inherited reload. We just mark the first register
4605 static HARD_REG_SET reload_reg_used_for_inherit;
4607 /* Records which hard regs are used in any way, either as explicit use or
4608 by being allocated to a pseudo during any point of the current insn. */
4609 static HARD_REG_SET reg_used_in_insn;
4611 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4612 TYPE. MODE is used to indicate how many consecutive regs are
4616 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4617 enum machine_mode mode)
4619 unsigned int nregs = hard_regno_nregs[regno][mode];
4622 for (i = regno; i < nregs + regno; i++)
4627 SET_HARD_REG_BIT (reload_reg_used, i);
4630 case RELOAD_FOR_INPUT_ADDRESS:
4631 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4634 case RELOAD_FOR_INPADDR_ADDRESS:
4635 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4638 case RELOAD_FOR_OUTPUT_ADDRESS:
4639 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4642 case RELOAD_FOR_OUTADDR_ADDRESS:
4643 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4646 case RELOAD_FOR_OPERAND_ADDRESS:
4647 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4650 case RELOAD_FOR_OPADDR_ADDR:
4651 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4654 case RELOAD_FOR_OTHER_ADDRESS:
4655 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4658 case RELOAD_FOR_INPUT:
4659 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4662 case RELOAD_FOR_OUTPUT:
4663 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4666 case RELOAD_FOR_INSN:
4667 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4671 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4675 /* Similarly, but show REGNO is no longer in use for a reload. */
4678 clear_reload_reg_in_use (unsigned int regno, int opnum,
4679 enum reload_type type, enum machine_mode mode)
4681 unsigned int nregs = hard_regno_nregs[regno][mode];
4682 unsigned int start_regno, end_regno, r;
4684 /* A complication is that for some reload types, inheritance might
4685 allow multiple reloads of the same types to share a reload register.
4686 We set check_opnum if we have to check only reloads with the same
4687 operand number, and check_any if we have to check all reloads. */
4688 int check_opnum = 0;
4690 HARD_REG_SET *used_in_set;
4695 used_in_set = &reload_reg_used;
4698 case RELOAD_FOR_INPUT_ADDRESS:
4699 used_in_set = &reload_reg_used_in_input_addr[opnum];
4702 case RELOAD_FOR_INPADDR_ADDRESS:
4704 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4707 case RELOAD_FOR_OUTPUT_ADDRESS:
4708 used_in_set = &reload_reg_used_in_output_addr[opnum];
4711 case RELOAD_FOR_OUTADDR_ADDRESS:
4713 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4716 case RELOAD_FOR_OPERAND_ADDRESS:
4717 used_in_set = &reload_reg_used_in_op_addr;
4720 case RELOAD_FOR_OPADDR_ADDR:
4722 used_in_set = &reload_reg_used_in_op_addr_reload;
4725 case RELOAD_FOR_OTHER_ADDRESS:
4726 used_in_set = &reload_reg_used_in_other_addr;
4730 case RELOAD_FOR_INPUT:
4731 used_in_set = &reload_reg_used_in_input[opnum];
4734 case RELOAD_FOR_OUTPUT:
4735 used_in_set = &reload_reg_used_in_output[opnum];
4738 case RELOAD_FOR_INSN:
4739 used_in_set = &reload_reg_used_in_insn;
4744 /* We resolve conflicts with remaining reloads of the same type by
4745 excluding the intervals of reload registers by them from the
4746 interval of freed reload registers. Since we only keep track of
4747 one set of interval bounds, we might have to exclude somewhat
4748 more than what would be necessary if we used a HARD_REG_SET here.
4749 But this should only happen very infrequently, so there should
4750 be no reason to worry about it. */
4752 start_regno = regno;
4753 end_regno = regno + nregs;
4754 if (check_opnum || check_any)
4756 for (i = n_reloads - 1; i >= 0; i--)
4758 if (rld[i].when_needed == type
4759 && (check_any || rld[i].opnum == opnum)
4762 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4763 unsigned int conflict_end
4764 = end_hard_regno (rld[i].mode, conflict_start);
4766 /* If there is an overlap with the first to-be-freed register,
4767 adjust the interval start. */
4768 if (conflict_start <= start_regno && conflict_end > start_regno)
4769 start_regno = conflict_end;
4770 /* Otherwise, if there is a conflict with one of the other
4771 to-be-freed registers, adjust the interval end. */
4772 if (conflict_start > start_regno && conflict_start < end_regno)
4773 end_regno = conflict_start;
4778 for (r = start_regno; r < end_regno; r++)
4779 CLEAR_HARD_REG_BIT (*used_in_set, r);
4782 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4783 specified by OPNUM and TYPE. */
4786 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4790 /* In use for a RELOAD_OTHER means it's not available for anything. */
4791 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4792 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4798 /* In use for anything means we can't use it for RELOAD_OTHER. */
4799 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4800 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4801 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4802 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4805 for (i = 0; i < reload_n_operands; i++)
4806 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4807 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4808 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4809 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4810 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4811 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4816 case RELOAD_FOR_INPUT:
4817 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4818 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4824 /* If it is used for some other input, can't use it. */
4825 for (i = 0; i < reload_n_operands; i++)
4826 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4829 /* If it is used in a later operand's address, can't use it. */
4830 for (i = opnum + 1; i < reload_n_operands; i++)
4831 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4832 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4837 case RELOAD_FOR_INPUT_ADDRESS:
4838 /* Can't use a register if it is used for an input address for this
4839 operand or used as an input in an earlier one. */
4840 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4841 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4844 for (i = 0; i < opnum; i++)
4845 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4850 case RELOAD_FOR_INPADDR_ADDRESS:
4851 /* Can't use a register if it is used for an input address
4852 for this operand or used as an input in an earlier
4854 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4857 for (i = 0; i < opnum; i++)
4858 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4863 case RELOAD_FOR_OUTPUT_ADDRESS:
4864 /* Can't use a register if it is used for an output address for this
4865 operand or used as an output in this or a later operand. Note
4866 that multiple output operands are emitted in reverse order, so
4867 the conflicting ones are those with lower indices. */
4868 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4871 for (i = 0; i <= opnum; i++)
4872 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4877 case RELOAD_FOR_OUTADDR_ADDRESS:
4878 /* Can't use a register if it is used for an output address
4879 for this operand or used as an output in this or a
4880 later operand. Note that multiple output operands are
4881 emitted in reverse order, so the conflicting ones are
4882 those with lower indices. */
4883 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4886 for (i = 0; i <= opnum; i++)
4887 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4892 case RELOAD_FOR_OPERAND_ADDRESS:
4893 for (i = 0; i < reload_n_operands; i++)
4894 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4897 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4898 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4900 case RELOAD_FOR_OPADDR_ADDR:
4901 for (i = 0; i < reload_n_operands; i++)
4902 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4905 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4907 case RELOAD_FOR_OUTPUT:
4908 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4909 outputs, or an operand address for this or an earlier output.
4910 Note that multiple output operands are emitted in reverse order,
4911 so the conflicting ones are those with higher indices. */
4912 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4915 for (i = 0; i < reload_n_operands; i++)
4916 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4919 for (i = opnum; i < reload_n_operands; i++)
4920 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4921 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4926 case RELOAD_FOR_INSN:
4927 for (i = 0; i < reload_n_operands; i++)
4928 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4929 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4932 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4933 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4935 case RELOAD_FOR_OTHER_ADDRESS:
4936 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4943 /* Return 1 if the value in reload reg REGNO, as used by a reload
4944 needed for the part of the insn specified by OPNUM and TYPE,
4945 is still available in REGNO at the end of the insn.
4947 We can assume that the reload reg was already tested for availability
4948 at the time it is needed, and we should not check this again,
4949 in case the reg has already been marked in use. */
4952 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4959 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4960 its value must reach the end. */
4963 /* If this use is for part of the insn,
4964 its value reaches if no subsequent part uses the same register.
4965 Just like the above function, don't try to do this with lots
4968 case RELOAD_FOR_OTHER_ADDRESS:
4969 /* Here we check for everything else, since these don't conflict
4970 with anything else and everything comes later. */
4972 for (i = 0; i < reload_n_operands; i++)
4973 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4974 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4975 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4976 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4977 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4978 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4981 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4982 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4983 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4984 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4986 case RELOAD_FOR_INPUT_ADDRESS:
4987 case RELOAD_FOR_INPADDR_ADDRESS:
4988 /* Similar, except that we check only for this and subsequent inputs
4989 and the address of only subsequent inputs and we do not need
4990 to check for RELOAD_OTHER objects since they are known not to
4993 for (i = opnum; i < reload_n_operands; i++)
4994 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4997 for (i = opnum + 1; i < reload_n_operands; i++)
4998 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4999 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
5002 for (i = 0; i < reload_n_operands; i++)
5003 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5004 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5005 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5008 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
5011 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5012 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5013 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5015 case RELOAD_FOR_INPUT:
5016 /* Similar to input address, except we start at the next operand for
5017 both input and input address and we do not check for
5018 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
5021 for (i = opnum + 1; i < reload_n_operands; i++)
5022 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
5023 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
5024 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
5027 /* ... fall through ... */
5029 case RELOAD_FOR_OPERAND_ADDRESS:
5030 /* Check outputs and their addresses. */
5032 for (i = 0; i < reload_n_operands; i++)
5033 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5034 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5035 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5038 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5040 case RELOAD_FOR_OPADDR_ADDR:
5041 for (i = 0; i < reload_n_operands; i++)
5042 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5043 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5044 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5047 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5048 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5049 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5051 case RELOAD_FOR_INSN:
5052 /* These conflict with other outputs with RELOAD_OTHER. So
5053 we need only check for output addresses. */
5055 opnum = reload_n_operands;
5057 /* ... fall through ... */
5059 case RELOAD_FOR_OUTPUT:
5060 case RELOAD_FOR_OUTPUT_ADDRESS:
5061 case RELOAD_FOR_OUTADDR_ADDRESS:
5062 /* We already know these can't conflict with a later output. So the
5063 only thing to check are later output addresses.
5064 Note that multiple output operands are emitted in reverse order,
5065 so the conflicting ones are those with lower indices. */
5066 for (i = 0; i < opnum; i++)
5067 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5068 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5078 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5079 every register in the range [REGNO, REGNO + NREGS). */
5082 reload_regs_reach_end_p (unsigned int regno, int nregs,
5083 int opnum, enum reload_type type)
5087 for (i = 0; i < nregs; i++)
5088 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5094 /* Returns whether R1 and R2 are uniquely chained: the value of one
5095 is used by the other, and that value is not used by any other
5096 reload for this insn. This is used to partially undo the decision
5097 made in find_reloads when in the case of multiple
5098 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5099 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5100 reloads. This code tries to avoid the conflict created by that
5101 change. It might be cleaner to explicitly keep track of which
5102 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5103 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5104 this after the fact. */
5106 reloads_unique_chain_p (int r1, int r2)
5110 /* We only check input reloads. */
5111 if (! rld[r1].in || ! rld[r2].in)
5114 /* Avoid anything with output reloads. */
5115 if (rld[r1].out || rld[r2].out)
5118 /* "chained" means one reload is a component of the other reload,
5119 not the same as the other reload. */
5120 if (rld[r1].opnum != rld[r2].opnum
5121 || rtx_equal_p (rld[r1].in, rld[r2].in)
5122 || rld[r1].optional || rld[r2].optional
5123 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5124 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5127 for (i = 0; i < n_reloads; i ++)
5128 /* Look for input reloads that aren't our two */
5129 if (i != r1 && i != r2 && rld[i].in)
5131 /* If our reload is mentioned at all, it isn't a simple chain. */
5132 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5139 /* The recursive function change all occurrences of WHAT in *WHERE
5142 substitute (rtx *where, const_rtx what, rtx repl)
5151 if (*where == what || rtx_equal_p (*where, what))
5157 code = GET_CODE (*where);
5158 fmt = GET_RTX_FORMAT (code);
5159 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5165 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5166 substitute (&XVECEXP (*where, i, j), what, repl);
5168 else if (fmt[i] == 'e')
5169 substitute (&XEXP (*where, i), what, repl);
5173 /* The function returns TRUE if chain of reload R1 and R2 (in any
5174 order) can be evaluated without usage of intermediate register for
5175 the reload containing another reload. It is important to see
5176 gen_reload to understand what the function is trying to do. As an
5177 example, let us have reload chain
5180 r1: <something> + const
5182 and reload R2 got reload reg HR. The function returns true if
5183 there is a correct insn HR = HR + <something>. Otherwise,
5184 gen_reload will use intermediate register (and this is the reload
5185 reg for R1) to reload <something>.
5187 We need this function to find a conflict for chain reloads. In our
5188 example, if HR = HR + <something> is incorrect insn, then we cannot
5189 use HR as a reload register for R2. If we do use it then we get a
5198 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5202 rtx out, in, tem, insn;
5203 rtx last = get_last_insn ();
5205 /* Make r2 a component of r1. */
5206 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5212 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5213 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5214 gcc_assert (regno >= 0);
5215 out = gen_rtx_REG (rld[r1].mode, regno);
5216 in = copy_rtx (rld[r1].in);
5217 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5219 /* If IN is a paradoxical SUBREG, remove it and try to put the
5220 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5221 if (GET_CODE (in) == SUBREG
5222 && (GET_MODE_SIZE (GET_MODE (in))
5223 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5224 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5225 in = SUBREG_REG (in), out = tem;
5227 if (GET_CODE (in) == PLUS
5228 && (REG_P (XEXP (in, 0))
5229 || GET_CODE (XEXP (in, 0)) == SUBREG
5230 || MEM_P (XEXP (in, 0)))
5231 && (REG_P (XEXP (in, 1))
5232 || GET_CODE (XEXP (in, 1)) == SUBREG
5233 || CONSTANT_P (XEXP (in, 1))
5234 || MEM_P (XEXP (in, 1))))
5236 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5237 code = recog_memoized (insn);
5242 extract_insn (insn);
5243 /* We want constrain operands to treat this insn strictly in
5244 its validity determination, i.e., the way it would after
5245 reload has completed. */
5246 result = constrain_operands (1);
5249 delete_insns_since (last);
5253 /* It looks like other cases in gen_reload are not possible for
5254 chain reloads or do need an intermediate hard registers. */
5258 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5261 This function uses the same algorithm as reload_reg_free_p above. */
5264 reloads_conflict (int r1, int r2)
5266 enum reload_type r1_type = rld[r1].when_needed;
5267 enum reload_type r2_type = rld[r2].when_needed;
5268 int r1_opnum = rld[r1].opnum;
5269 int r2_opnum = rld[r2].opnum;
5271 /* RELOAD_OTHER conflicts with everything. */
5272 if (r2_type == RELOAD_OTHER)
5275 /* Otherwise, check conflicts differently for each type. */
5279 case RELOAD_FOR_INPUT:
5280 return (r2_type == RELOAD_FOR_INSN
5281 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5282 || r2_type == RELOAD_FOR_OPADDR_ADDR
5283 || r2_type == RELOAD_FOR_INPUT
5284 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5285 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5286 && r2_opnum > r1_opnum));
5288 case RELOAD_FOR_INPUT_ADDRESS:
5289 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5290 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5292 case RELOAD_FOR_INPADDR_ADDRESS:
5293 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5294 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5296 case RELOAD_FOR_OUTPUT_ADDRESS:
5297 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5298 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5300 case RELOAD_FOR_OUTADDR_ADDRESS:
5301 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5302 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5304 case RELOAD_FOR_OPERAND_ADDRESS:
5305 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5306 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5307 && (!reloads_unique_chain_p (r1, r2)
5308 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5310 case RELOAD_FOR_OPADDR_ADDR:
5311 return (r2_type == RELOAD_FOR_INPUT
5312 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5314 case RELOAD_FOR_OUTPUT:
5315 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5316 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5317 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5318 && r2_opnum >= r1_opnum));
5320 case RELOAD_FOR_INSN:
5321 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5322 || r2_type == RELOAD_FOR_INSN
5323 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5325 case RELOAD_FOR_OTHER_ADDRESS:
5326 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5336 /* Indexed by reload number, 1 if incoming value
5337 inherited from previous insns. */
5338 static char reload_inherited[MAX_RELOADS];
5340 /* For an inherited reload, this is the insn the reload was inherited from,
5341 if we know it. Otherwise, this is 0. */
5342 static rtx reload_inheritance_insn[MAX_RELOADS];
5344 /* If nonzero, this is a place to get the value of the reload,
5345 rather than using reload_in. */
5346 static rtx reload_override_in[MAX_RELOADS];
5348 /* For each reload, the hard register number of the register used,
5349 or -1 if we did not need a register for this reload. */
5350 static int reload_spill_index[MAX_RELOADS];
5352 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5353 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5355 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5356 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5358 /* Subroutine of free_for_value_p, used to check a single register.
5359 START_REGNO is the starting regno of the full reload register
5360 (possibly comprising multiple hard registers) that we are considering. */
5363 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5364 enum reload_type type, rtx value, rtx out,
5365 int reloadnum, int ignore_address_reloads)
5368 /* Set if we see an input reload that must not share its reload register
5369 with any new earlyclobber, but might otherwise share the reload
5370 register with an output or input-output reload. */
5371 int check_earlyclobber = 0;
5375 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5378 if (out == const0_rtx)
5384 /* We use some pseudo 'time' value to check if the lifetimes of the
5385 new register use would overlap with the one of a previous reload
5386 that is not read-only or uses a different value.
5387 The 'time' used doesn't have to be linear in any shape or form, just
5389 Some reload types use different 'buckets' for each operand.
5390 So there are MAX_RECOG_OPERANDS different time values for each
5392 We compute TIME1 as the time when the register for the prospective
5393 new reload ceases to be live, and TIME2 for each existing
5394 reload as the time when that the reload register of that reload
5396 Where there is little to be gained by exact lifetime calculations,
5397 we just make conservative assumptions, i.e. a longer lifetime;
5398 this is done in the 'default:' cases. */
5401 case RELOAD_FOR_OTHER_ADDRESS:
5402 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5403 time1 = copy ? 0 : 1;
5406 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5408 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5409 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5410 respectively, to the time values for these, we get distinct time
5411 values. To get distinct time values for each operand, we have to
5412 multiply opnum by at least three. We round that up to four because
5413 multiply by four is often cheaper. */
5414 case RELOAD_FOR_INPADDR_ADDRESS:
5415 time1 = opnum * 4 + 2;
5417 case RELOAD_FOR_INPUT_ADDRESS:
5418 time1 = opnum * 4 + 3;
5420 case RELOAD_FOR_INPUT:
5421 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5422 executes (inclusive). */
5423 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5425 case RELOAD_FOR_OPADDR_ADDR:
5427 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5428 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5430 case RELOAD_FOR_OPERAND_ADDRESS:
5431 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5433 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5435 case RELOAD_FOR_OUTADDR_ADDRESS:
5436 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5438 case RELOAD_FOR_OUTPUT_ADDRESS:
5439 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5442 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5445 for (i = 0; i < n_reloads; i++)
5447 rtx reg = rld[i].reg_rtx;
5448 if (reg && REG_P (reg)
5449 && ((unsigned) regno - true_regnum (reg)
5450 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5453 rtx other_input = rld[i].in;
5455 /* If the other reload loads the same input value, that
5456 will not cause a conflict only if it's loading it into
5457 the same register. */
5458 if (true_regnum (reg) != start_regno)
5459 other_input = NULL_RTX;
5460 if (! other_input || ! rtx_equal_p (other_input, value)
5461 || rld[i].out || out)
5464 switch (rld[i].when_needed)
5466 case RELOAD_FOR_OTHER_ADDRESS:
5469 case RELOAD_FOR_INPADDR_ADDRESS:
5470 /* find_reloads makes sure that a
5471 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5472 by at most one - the first -
5473 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5474 address reload is inherited, the address address reload
5475 goes away, so we can ignore this conflict. */
5476 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5477 && ignore_address_reloads
5478 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5479 Then the address address is still needed to store
5480 back the new address. */
5481 && ! rld[reloadnum].out)
5483 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5484 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5486 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5487 && ignore_address_reloads
5488 /* Unless we are reloading an auto_inc expression. */
5489 && ! rld[reloadnum].out)
5491 time2 = rld[i].opnum * 4 + 2;
5493 case RELOAD_FOR_INPUT_ADDRESS:
5494 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5495 && ignore_address_reloads
5496 && ! rld[reloadnum].out)
5498 time2 = rld[i].opnum * 4 + 3;
5500 case RELOAD_FOR_INPUT:
5501 time2 = rld[i].opnum * 4 + 4;
5502 check_earlyclobber = 1;
5504 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5505 == MAX_RECOG_OPERAND * 4 */
5506 case RELOAD_FOR_OPADDR_ADDR:
5507 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5508 && ignore_address_reloads
5509 && ! rld[reloadnum].out)
5511 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5513 case RELOAD_FOR_OPERAND_ADDRESS:
5514 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5515 check_earlyclobber = 1;
5517 case RELOAD_FOR_INSN:
5518 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5520 case RELOAD_FOR_OUTPUT:
5521 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5522 instruction is executed. */
5523 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5525 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5526 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5528 case RELOAD_FOR_OUTADDR_ADDRESS:
5529 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5530 && ignore_address_reloads
5531 && ! rld[reloadnum].out)
5533 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5535 case RELOAD_FOR_OUTPUT_ADDRESS:
5536 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5539 /* If there is no conflict in the input part, handle this
5540 like an output reload. */
5541 if (! rld[i].in || rtx_equal_p (other_input, value))
5543 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5544 /* Earlyclobbered outputs must conflict with inputs. */
5545 if (earlyclobber_operand_p (rld[i].out))
5546 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5551 /* RELOAD_OTHER might be live beyond instruction execution,
5552 but this is not obvious when we set time2 = 1. So check
5553 here if there might be a problem with the new reload
5554 clobbering the register used by the RELOAD_OTHER. */
5562 && (! rld[i].in || rld[i].out
5563 || ! rtx_equal_p (other_input, value)))
5564 || (out && rld[reloadnum].out_reg
5565 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5571 /* Earlyclobbered outputs must conflict with inputs. */
5572 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5578 /* Return 1 if the value in reload reg REGNO, as used by a reload
5579 needed for the part of the insn specified by OPNUM and TYPE,
5580 may be used to load VALUE into it.
5582 MODE is the mode in which the register is used, this is needed to
5583 determine how many hard regs to test.
5585 Other read-only reloads with the same value do not conflict
5586 unless OUT is nonzero and these other reloads have to live while
5587 output reloads live.
5588 If OUT is CONST0_RTX, this is a special case: it means that the
5589 test should not be for using register REGNO as reload register, but
5590 for copying from register REGNO into the reload register.
5592 RELOADNUM is the number of the reload we want to load this value for;
5593 a reload does not conflict with itself.
5595 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5596 reloads that load an address for the very reload we are considering.
5598 The caller has to make sure that there is no conflict with the return
5602 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5603 enum reload_type type, rtx value, rtx out, int reloadnum,
5604 int ignore_address_reloads)
5606 int nregs = hard_regno_nregs[regno][mode];
5608 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5609 value, out, reloadnum,
5610 ignore_address_reloads))
5615 /* Return nonzero if the rtx X is invariant over the current function. */
5616 /* ??? Actually, the places where we use this expect exactly what is
5617 tested here, and not everything that is function invariant. In
5618 particular, the frame pointer and arg pointer are special cased;
5619 pic_offset_table_rtx is not, and we must not spill these things to
5623 function_invariant_p (const_rtx x)
5627 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5629 if (GET_CODE (x) == PLUS
5630 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5631 && CONSTANT_P (XEXP (x, 1)))
5636 /* Determine whether the reload reg X overlaps any rtx'es used for
5637 overriding inheritance. Return nonzero if so. */
5640 conflicts_with_override (rtx x)
5643 for (i = 0; i < n_reloads; i++)
5644 if (reload_override_in[i]
5645 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5650 /* Give an error message saying we failed to find a reload for INSN,
5651 and clear out reload R. */
5653 failed_reload (rtx insn, int r)
5655 if (asm_noperands (PATTERN (insn)) < 0)
5656 /* It's the compiler's fault. */
5657 fatal_insn ("could not find a spill register", insn);
5659 /* It's the user's fault; the operand's mode and constraint
5660 don't match. Disable this reload so we don't crash in final. */
5661 error_for_asm (insn,
5662 "%<asm%> operand constraint incompatible with operand size");
5666 rld[r].optional = 1;
5667 rld[r].secondary_p = 1;
5670 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5671 for reload R. If it's valid, get an rtx for it. Return nonzero if
5674 set_reload_reg (int i, int r)
5677 rtx reg = spill_reg_rtx[i];
5679 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5680 spill_reg_rtx[i] = reg
5681 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5683 regno = true_regnum (reg);
5685 /* Detect when the reload reg can't hold the reload mode.
5686 This used to be one `if', but Sequent compiler can't handle that. */
5687 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5689 enum machine_mode test_mode = VOIDmode;
5691 test_mode = GET_MODE (rld[r].in);
5692 /* If rld[r].in has VOIDmode, it means we will load it
5693 in whatever mode the reload reg has: to wit, rld[r].mode.
5694 We have already tested that for validity. */
5695 /* Aside from that, we need to test that the expressions
5696 to reload from or into have modes which are valid for this
5697 reload register. Otherwise the reload insns would be invalid. */
5698 if (! (rld[r].in != 0 && test_mode != VOIDmode
5699 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5700 if (! (rld[r].out != 0
5701 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5703 /* The reg is OK. */
5706 /* Mark as in use for this insn the reload regs we use
5708 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5709 rld[r].when_needed, rld[r].mode);
5711 rld[r].reg_rtx = reg;
5712 reload_spill_index[r] = spill_regs[i];
5719 /* Find a spill register to use as a reload register for reload R.
5720 LAST_RELOAD is nonzero if this is the last reload for the insn being
5723 Set rld[R].reg_rtx to the register allocated.
5725 We return 1 if successful, or 0 if we couldn't find a spill reg and
5726 we didn't change anything. */
5729 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5734 /* If we put this reload ahead, thinking it is a group,
5735 then insist on finding a group. Otherwise we can grab a
5736 reg that some other reload needs.
5737 (That can happen when we have a 68000 DATA_OR_FP_REG
5738 which is a group of data regs or one fp reg.)
5739 We need not be so restrictive if there are no more reloads
5742 ??? Really it would be nicer to have smarter handling
5743 for that kind of reg class, where a problem like this is normal.
5744 Perhaps those classes should be avoided for reloading
5745 by use of more alternatives. */
5747 int force_group = rld[r].nregs > 1 && ! last_reload;
5749 /* If we want a single register and haven't yet found one,
5750 take any reg in the right class and not in use.
5751 If we want a consecutive group, here is where we look for it.
5753 We use two passes so we can first look for reload regs to
5754 reuse, which are already in use for other reloads in this insn,
5755 and only then use additional registers.
5756 I think that maximizing reuse is needed to make sure we don't
5757 run out of reload regs. Suppose we have three reloads, and
5758 reloads A and B can share regs. These need two regs.
5759 Suppose A and B are given different regs.
5760 That leaves none for C. */
5761 for (pass = 0; pass < 2; pass++)
5763 /* I is the index in spill_regs.
5764 We advance it round-robin between insns to use all spill regs
5765 equally, so that inherited reloads have a chance
5766 of leapfrogging each other. */
5770 for (count = 0; count < n_spills; count++)
5772 int rclass = (int) rld[r].rclass;
5778 regnum = spill_regs[i];
5780 if ((reload_reg_free_p (regnum, rld[r].opnum,
5783 /* We check reload_reg_used to make sure we
5784 don't clobber the return register. */
5785 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5786 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5787 rld[r].when_needed, rld[r].in,
5789 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5790 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5791 /* Look first for regs to share, then for unshared. But
5792 don't share regs used for inherited reloads; they are
5793 the ones we want to preserve. */
5795 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5797 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5800 int nr = hard_regno_nregs[regnum][rld[r].mode];
5801 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5802 (on 68000) got us two FP regs. If NR is 1,
5803 we would reject both of them. */
5806 /* If we need only one reg, we have already won. */
5809 /* But reject a single reg if we demand a group. */
5814 /* Otherwise check that as many consecutive regs as we need
5815 are available here. */
5818 int regno = regnum + nr - 1;
5819 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5820 && spill_reg_order[regno] >= 0
5821 && reload_reg_free_p (regno, rld[r].opnum,
5822 rld[r].when_needed)))
5831 /* If we found something on pass 1, omit pass 2. */
5832 if (count < n_spills)
5836 /* We should have found a spill register by now. */
5837 if (count >= n_spills)
5840 /* I is the index in SPILL_REG_RTX of the reload register we are to
5841 allocate. Get an rtx for it and find its register number. */
5843 return set_reload_reg (i, r);
5846 /* Initialize all the tables needed to allocate reload registers.
5847 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5848 is the array we use to restore the reg_rtx field for every reload. */
5851 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5855 for (i = 0; i < n_reloads; i++)
5856 rld[i].reg_rtx = save_reload_reg_rtx[i];
5858 memset (reload_inherited, 0, MAX_RELOADS);
5859 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5860 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5862 CLEAR_HARD_REG_SET (reload_reg_used);
5863 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5864 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5865 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5866 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5867 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5869 CLEAR_HARD_REG_SET (reg_used_in_insn);
5872 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5873 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5874 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5875 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5876 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5877 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5880 for (i = 0; i < reload_n_operands; i++)
5882 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5883 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5884 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5885 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5886 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5887 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5890 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5892 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5894 for (i = 0; i < n_reloads; i++)
5895 /* If we have already decided to use a certain register,
5896 don't use it in another way. */
5898 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5899 rld[i].when_needed, rld[i].mode);
5902 /* Assign hard reg targets for the pseudo-registers we must reload
5903 into hard regs for this insn.
5904 Also output the instructions to copy them in and out of the hard regs.
5906 For machines with register classes, we are responsible for
5907 finding a reload reg in the proper class. */
5910 choose_reload_regs (struct insn_chain *chain)
5912 rtx insn = chain->insn;
5914 unsigned int max_group_size = 1;
5915 enum reg_class group_class = NO_REGS;
5916 int pass, win, inheritance;
5918 rtx save_reload_reg_rtx[MAX_RELOADS];
5920 /* In order to be certain of getting the registers we need,
5921 we must sort the reloads into order of increasing register class.
5922 Then our grabbing of reload registers will parallel the process
5923 that provided the reload registers.
5925 Also note whether any of the reloads wants a consecutive group of regs.
5926 If so, record the maximum size of the group desired and what
5927 register class contains all the groups needed by this insn. */
5929 for (j = 0; j < n_reloads; j++)
5931 reload_order[j] = j;
5932 if (rld[j].reg_rtx != NULL_RTX)
5934 gcc_assert (REG_P (rld[j].reg_rtx)
5935 && HARD_REGISTER_P (rld[j].reg_rtx));
5936 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5939 reload_spill_index[j] = -1;
5941 if (rld[j].nregs > 1)
5943 max_group_size = MAX (rld[j].nregs, max_group_size);
5945 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5948 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5952 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5954 /* If -O, try first with inheritance, then turning it off.
5955 If not -O, don't do inheritance.
5956 Using inheritance when not optimizing leads to paradoxes
5957 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5958 because one side of the comparison might be inherited. */
5960 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5962 choose_reload_regs_init (chain, save_reload_reg_rtx);
5964 /* Process the reloads in order of preference just found.
5965 Beyond this point, subregs can be found in reload_reg_rtx.
5967 This used to look for an existing reloaded home for all of the
5968 reloads, and only then perform any new reloads. But that could lose
5969 if the reloads were done out of reg-class order because a later
5970 reload with a looser constraint might have an old home in a register
5971 needed by an earlier reload with a tighter constraint.
5973 To solve this, we make two passes over the reloads, in the order
5974 described above. In the first pass we try to inherit a reload
5975 from a previous insn. If there is a later reload that needs a
5976 class that is a proper subset of the class being processed, we must
5977 also allocate a spill register during the first pass.
5979 Then make a second pass over the reloads to allocate any reloads
5980 that haven't been given registers yet. */
5982 for (j = 0; j < n_reloads; j++)
5984 int r = reload_order[j];
5985 rtx search_equiv = NULL_RTX;
5987 /* Ignore reloads that got marked inoperative. */
5988 if (rld[r].out == 0 && rld[r].in == 0
5989 && ! rld[r].secondary_p)
5992 /* If find_reloads chose to use reload_in or reload_out as a reload
5993 register, we don't need to chose one. Otherwise, try even if it
5994 found one since we might save an insn if we find the value lying
5996 Try also when reload_in is a pseudo without a hard reg. */
5997 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5998 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5999 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
6000 && !MEM_P (rld[r].in)
6001 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
6004 #if 0 /* No longer needed for correct operation.
6005 It might give better code, or might not; worth an experiment? */
6006 /* If this is an optional reload, we can't inherit from earlier insns
6007 until we are sure that any non-optional reloads have been allocated.
6008 The following code takes advantage of the fact that optional reloads
6009 are at the end of reload_order. */
6010 if (rld[r].optional != 0)
6011 for (i = 0; i < j; i++)
6012 if ((rld[reload_order[i]].out != 0
6013 || rld[reload_order[i]].in != 0
6014 || rld[reload_order[i]].secondary_p)
6015 && ! rld[reload_order[i]].optional
6016 && rld[reload_order[i]].reg_rtx == 0)
6017 allocate_reload_reg (chain, reload_order[i], 0);
6020 /* First see if this pseudo is already available as reloaded
6021 for a previous insn. We cannot try to inherit for reloads
6022 that are smaller than the maximum number of registers needed
6023 for groups unless the register we would allocate cannot be used
6026 We could check here to see if this is a secondary reload for
6027 an object that is already in a register of the desired class.
6028 This would avoid the need for the secondary reload register.
6029 But this is complex because we can't easily determine what
6030 objects might want to be loaded via this reload. So let a
6031 register be allocated here. In `emit_reload_insns' we suppress
6032 one of the loads in the case described above. */
6038 enum machine_mode mode = VOIDmode;
6042 else if (REG_P (rld[r].in))
6044 regno = REGNO (rld[r].in);
6045 mode = GET_MODE (rld[r].in);
6047 else if (REG_P (rld[r].in_reg))
6049 regno = REGNO (rld[r].in_reg);
6050 mode = GET_MODE (rld[r].in_reg);
6052 else if (GET_CODE (rld[r].in_reg) == SUBREG
6053 && REG_P (SUBREG_REG (rld[r].in_reg)))
6055 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6056 if (regno < FIRST_PSEUDO_REGISTER)
6057 regno = subreg_regno (rld[r].in_reg);
6059 byte = SUBREG_BYTE (rld[r].in_reg);
6060 mode = GET_MODE (rld[r].in_reg);
6063 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6064 && REG_P (XEXP (rld[r].in_reg, 0)))
6066 regno = REGNO (XEXP (rld[r].in_reg, 0));
6067 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6068 rld[r].out = rld[r].in;
6072 /* This won't work, since REGNO can be a pseudo reg number.
6073 Also, it takes much more hair to keep track of all the things
6074 that can invalidate an inherited reload of part of a pseudoreg. */
6075 else if (GET_CODE (rld[r].in) == SUBREG
6076 && REG_P (SUBREG_REG (rld[r].in)))
6077 regno = subreg_regno (rld[r].in);
6081 && reg_last_reload_reg[regno] != 0
6082 #ifdef CANNOT_CHANGE_MODE_CLASS
6083 /* Verify that the register it's in can be used in
6085 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6086 GET_MODE (reg_last_reload_reg[regno]),
6091 enum reg_class rclass = rld[r].rclass, last_class;
6092 rtx last_reg = reg_last_reload_reg[regno];
6093 enum machine_mode need_mode;
6095 i = REGNO (last_reg);
6096 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6097 last_class = REGNO_REG_CLASS (i);
6103 = smallest_mode_for_size
6104 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6105 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6106 ? MODE_INT : GET_MODE_CLASS (mode));
6108 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6109 >= GET_MODE_SIZE (need_mode))
6110 && reg_reloaded_contents[i] == regno
6111 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6112 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6113 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6114 /* Even if we can't use this register as a reload
6115 register, we might use it for reload_override_in,
6116 if copying it to the desired class is cheap
6118 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6119 < MEMORY_MOVE_COST (mode, rclass, 1))
6120 && (secondary_reload_class (1, rclass, mode,
6123 #ifdef SECONDARY_MEMORY_NEEDED
6124 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6129 && (rld[r].nregs == max_group_size
6130 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6132 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6133 rld[r].when_needed, rld[r].in,
6136 /* If a group is needed, verify that all the subsequent
6137 registers still have their values intact. */
6138 int nr = hard_regno_nregs[i][rld[r].mode];
6141 for (k = 1; k < nr; k++)
6142 if (reg_reloaded_contents[i + k] != regno
6143 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6151 last_reg = (GET_MODE (last_reg) == mode
6152 ? last_reg : gen_rtx_REG (mode, i));
6155 for (k = 0; k < nr; k++)
6156 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6159 /* We found a register that contains the
6160 value we need. If this register is the
6161 same as an `earlyclobber' operand of the
6162 current insn, just mark it as a place to
6163 reload from since we can't use it as the
6164 reload register itself. */
6166 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6167 if (reg_overlap_mentioned_for_reload_p
6168 (reg_last_reload_reg[regno],
6169 reload_earlyclobbers[i1]))
6172 if (i1 != n_earlyclobbers
6173 || ! (free_for_value_p (i, rld[r].mode,
6175 rld[r].when_needed, rld[r].in,
6177 /* Don't use it if we'd clobber a pseudo reg. */
6178 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6180 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6181 /* Don't clobber the frame pointer. */
6182 || (i == HARD_FRAME_POINTER_REGNUM
6183 && frame_pointer_needed
6185 /* Don't really use the inherited spill reg
6186 if we need it wider than we've got it. */
6187 || (GET_MODE_SIZE (rld[r].mode)
6188 > GET_MODE_SIZE (mode))
6191 /* If find_reloads chose reload_out as reload
6192 register, stay with it - that leaves the
6193 inherited register for subsequent reloads. */
6194 || (rld[r].out && rld[r].reg_rtx
6195 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6197 if (! rld[r].optional)
6199 reload_override_in[r] = last_reg;
6200 reload_inheritance_insn[r]
6201 = reg_reloaded_insn[i];
6207 /* We can use this as a reload reg. */
6208 /* Mark the register as in use for this part of
6210 mark_reload_reg_in_use (i,
6214 rld[r].reg_rtx = last_reg;
6215 reload_inherited[r] = 1;
6216 reload_inheritance_insn[r]
6217 = reg_reloaded_insn[i];
6218 reload_spill_index[r] = i;
6219 for (k = 0; k < nr; k++)
6220 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6228 /* Here's another way to see if the value is already lying around. */
6231 && ! reload_inherited[r]
6233 && (CONSTANT_P (rld[r].in)
6234 || GET_CODE (rld[r].in) == PLUS
6235 || REG_P (rld[r].in)
6236 || MEM_P (rld[r].in))
6237 && (rld[r].nregs == max_group_size
6238 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6239 search_equiv = rld[r].in;
6240 /* If this is an output reload from a simple move insn, look
6241 if an equivalence for the input is available. */
6242 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6244 rtx set = single_set (insn);
6247 && rtx_equal_p (rld[r].out, SET_DEST (set))
6248 && CONSTANT_P (SET_SRC (set)))
6249 search_equiv = SET_SRC (set);
6255 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6256 -1, NULL, 0, rld[r].mode);
6262 regno = REGNO (equiv);
6265 /* This must be a SUBREG of a hard register.
6266 Make a new REG since this might be used in an
6267 address and not all machines support SUBREGs
6269 gcc_assert (GET_CODE (equiv) == SUBREG);
6270 regno = subreg_regno (equiv);
6271 equiv = gen_rtx_REG (rld[r].mode, regno);
6272 /* If we choose EQUIV as the reload register, but the
6273 loop below decides to cancel the inheritance, we'll
6274 end up reloading EQUIV in rld[r].mode, not the mode
6275 it had originally. That isn't safe when EQUIV isn't
6276 available as a spill register since its value might
6277 still be live at this point. */
6278 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6279 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6284 /* If we found a spill reg, reject it unless it is free
6285 and of the desired class. */
6289 int bad_for_class = 0;
6290 int max_regno = regno + rld[r].nregs;
6292 for (i = regno; i < max_regno; i++)
6294 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6296 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6301 && ! free_for_value_p (regno, rld[r].mode,
6302 rld[r].opnum, rld[r].when_needed,
6303 rld[r].in, rld[r].out, r, 1))
6308 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6311 /* We found a register that contains the value we need.
6312 If this register is the same as an `earlyclobber' operand
6313 of the current insn, just mark it as a place to reload from
6314 since we can't use it as the reload register itself. */
6317 for (i = 0; i < n_earlyclobbers; i++)
6318 if (reg_overlap_mentioned_for_reload_p (equiv,
6319 reload_earlyclobbers[i]))
6321 if (! rld[r].optional)
6322 reload_override_in[r] = equiv;
6327 /* If the equiv register we have found is explicitly clobbered
6328 in the current insn, it depends on the reload type if we
6329 can use it, use it for reload_override_in, or not at all.
6330 In particular, we then can't use EQUIV for a
6331 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6335 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6336 switch (rld[r].when_needed)
6338 case RELOAD_FOR_OTHER_ADDRESS:
6339 case RELOAD_FOR_INPADDR_ADDRESS:
6340 case RELOAD_FOR_INPUT_ADDRESS:
6341 case RELOAD_FOR_OPADDR_ADDR:
6344 case RELOAD_FOR_INPUT:
6345 case RELOAD_FOR_OPERAND_ADDRESS:
6346 if (! rld[r].optional)
6347 reload_override_in[r] = equiv;
6353 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6354 switch (rld[r].when_needed)
6356 case RELOAD_FOR_OTHER_ADDRESS:
6357 case RELOAD_FOR_INPADDR_ADDRESS:
6358 case RELOAD_FOR_INPUT_ADDRESS:
6359 case RELOAD_FOR_OPADDR_ADDR:
6360 case RELOAD_FOR_OPERAND_ADDRESS:
6361 case RELOAD_FOR_INPUT:
6364 if (! rld[r].optional)
6365 reload_override_in[r] = equiv;
6373 /* If we found an equivalent reg, say no code need be generated
6374 to load it, and use it as our reload reg. */
6376 && (regno != HARD_FRAME_POINTER_REGNUM
6377 || !frame_pointer_needed))
6379 int nr = hard_regno_nregs[regno][rld[r].mode];
6381 rld[r].reg_rtx = equiv;
6382 reload_spill_index[r] = regno;
6383 reload_inherited[r] = 1;
6385 /* If reg_reloaded_valid is not set for this register,
6386 there might be a stale spill_reg_store lying around.
6387 We must clear it, since otherwise emit_reload_insns
6388 might delete the store. */
6389 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6390 spill_reg_store[regno] = NULL_RTX;
6391 /* If any of the hard registers in EQUIV are spill
6392 registers, mark them as in use for this insn. */
6393 for (k = 0; k < nr; k++)
6395 i = spill_reg_order[regno + k];
6398 mark_reload_reg_in_use (regno, rld[r].opnum,
6401 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6408 /* If we found a register to use already, or if this is an optional
6409 reload, we are done. */
6410 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6414 /* No longer needed for correct operation. Might or might
6415 not give better code on the average. Want to experiment? */
6417 /* See if there is a later reload that has a class different from our
6418 class that intersects our class or that requires less register
6419 than our reload. If so, we must allocate a register to this
6420 reload now, since that reload might inherit a previous reload
6421 and take the only available register in our class. Don't do this
6422 for optional reloads since they will force all previous reloads
6423 to be allocated. Also don't do this for reloads that have been
6426 for (i = j + 1; i < n_reloads; i++)
6428 int s = reload_order[i];
6430 if ((rld[s].in == 0 && rld[s].out == 0
6431 && ! rld[s].secondary_p)
6435 if ((rld[s].rclass != rld[r].rclass
6436 && reg_classes_intersect_p (rld[r].rclass,
6438 || rld[s].nregs < rld[r].nregs)
6445 allocate_reload_reg (chain, r, j == n_reloads - 1);
6449 /* Now allocate reload registers for anything non-optional that
6450 didn't get one yet. */
6451 for (j = 0; j < n_reloads; j++)
6453 int r = reload_order[j];
6455 /* Ignore reloads that got marked inoperative. */
6456 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6459 /* Skip reloads that already have a register allocated or are
6461 if (rld[r].reg_rtx != 0 || rld[r].optional)
6464 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6468 /* If that loop got all the way, we have won. */
6475 /* Loop around and try without any inheritance. */
6480 /* First undo everything done by the failed attempt
6481 to allocate with inheritance. */
6482 choose_reload_regs_init (chain, save_reload_reg_rtx);
6484 /* Some sanity tests to verify that the reloads found in the first
6485 pass are identical to the ones we have now. */
6486 gcc_assert (chain->n_reloads == n_reloads);
6488 for (i = 0; i < n_reloads; i++)
6490 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6492 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6493 for (j = 0; j < n_spills; j++)
6494 if (spill_regs[j] == chain->rld[i].regno)
6495 if (! set_reload_reg (j, i))
6496 failed_reload (chain->insn, i);
6500 /* If we thought we could inherit a reload, because it seemed that
6501 nothing else wanted the same reload register earlier in the insn,
6502 verify that assumption, now that all reloads have been assigned.
6503 Likewise for reloads where reload_override_in has been set. */
6505 /* If doing expensive optimizations, do one preliminary pass that doesn't
6506 cancel any inheritance, but removes reloads that have been needed only
6507 for reloads that we know can be inherited. */
6508 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6510 for (j = 0; j < n_reloads; j++)
6512 int r = reload_order[j];
6514 if (reload_inherited[r] && rld[r].reg_rtx)
6515 check_reg = rld[r].reg_rtx;
6516 else if (reload_override_in[r]
6517 && (REG_P (reload_override_in[r])
6518 || GET_CODE (reload_override_in[r]) == SUBREG))
6519 check_reg = reload_override_in[r];
6522 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6523 rld[r].opnum, rld[r].when_needed, rld[r].in,
6524 (reload_inherited[r]
6525 ? rld[r].out : const0_rtx),
6530 reload_inherited[r] = 0;
6531 reload_override_in[r] = 0;
6533 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6534 reload_override_in, then we do not need its related
6535 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6536 likewise for other reload types.
6537 We handle this by removing a reload when its only replacement
6538 is mentioned in reload_in of the reload we are going to inherit.
6539 A special case are auto_inc expressions; even if the input is
6540 inherited, we still need the address for the output. We can
6541 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6542 If we succeeded removing some reload and we are doing a preliminary
6543 pass just to remove such reloads, make another pass, since the
6544 removal of one reload might allow us to inherit another one. */
6546 && rld[r].out != rld[r].in
6547 && remove_address_replacements (rld[r].in) && pass)
6552 /* Now that reload_override_in is known valid,
6553 actually override reload_in. */
6554 for (j = 0; j < n_reloads; j++)
6555 if (reload_override_in[j])
6556 rld[j].in = reload_override_in[j];
6558 /* If this reload won't be done because it has been canceled or is
6559 optional and not inherited, clear reload_reg_rtx so other
6560 routines (such as subst_reloads) don't get confused. */
6561 for (j = 0; j < n_reloads; j++)
6562 if (rld[j].reg_rtx != 0
6563 && ((rld[j].optional && ! reload_inherited[j])
6564 || (rld[j].in == 0 && rld[j].out == 0
6565 && ! rld[j].secondary_p)))
6567 int regno = true_regnum (rld[j].reg_rtx);
6569 if (spill_reg_order[regno] >= 0)
6570 clear_reload_reg_in_use (regno, rld[j].opnum,
6571 rld[j].when_needed, rld[j].mode);
6573 reload_spill_index[j] = -1;
6576 /* Record which pseudos and which spill regs have output reloads. */
6577 for (j = 0; j < n_reloads; j++)
6579 int r = reload_order[j];
6581 i = reload_spill_index[r];
6583 /* I is nonneg if this reload uses a register.
6584 If rld[r].reg_rtx is 0, this is an optional reload
6585 that we opted to ignore. */
6586 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6587 && rld[r].reg_rtx != 0)
6589 int nregno = REGNO (rld[r].out_reg);
6592 if (nregno < FIRST_PSEUDO_REGISTER)
6593 nr = hard_regno_nregs[nregno][rld[r].mode];
6596 SET_REGNO_REG_SET (®_has_output_reload,
6601 nr = hard_regno_nregs[i][rld[r].mode];
6603 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6606 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6607 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6608 || rld[r].when_needed == RELOAD_FOR_INSN);
6613 /* Deallocate the reload register for reload R. This is called from
6614 remove_address_replacements. */
6617 deallocate_reload_reg (int r)
6621 if (! rld[r].reg_rtx)
6623 regno = true_regnum (rld[r].reg_rtx);
6625 if (spill_reg_order[regno] >= 0)
6626 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6628 reload_spill_index[r] = -1;
6631 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6632 reloads of the same item for fear that we might not have enough reload
6633 registers. However, normally they will get the same reload register
6634 and hence actually need not be loaded twice.
6636 Here we check for the most common case of this phenomenon: when we have
6637 a number of reloads for the same object, each of which were allocated
6638 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6639 reload, and is not modified in the insn itself. If we find such,
6640 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6641 This will not increase the number of spill registers needed and will
6642 prevent redundant code. */
6645 merge_assigned_reloads (rtx insn)
6649 /* Scan all the reloads looking for ones that only load values and
6650 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6651 assigned and not modified by INSN. */
6653 for (i = 0; i < n_reloads; i++)
6655 int conflicting_input = 0;
6656 int max_input_address_opnum = -1;
6657 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6659 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6660 || rld[i].out != 0 || rld[i].reg_rtx == 0
6661 || reg_set_p (rld[i].reg_rtx, insn))
6664 /* Look at all other reloads. Ensure that the only use of this
6665 reload_reg_rtx is in a reload that just loads the same value
6666 as we do. Note that any secondary reloads must be of the identical
6667 class since the values, modes, and result registers are the
6668 same, so we need not do anything with any secondary reloads. */
6670 for (j = 0; j < n_reloads; j++)
6672 if (i == j || rld[j].reg_rtx == 0
6673 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6677 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6678 && rld[j].opnum > max_input_address_opnum)
6679 max_input_address_opnum = rld[j].opnum;
6681 /* If the reload regs aren't exactly the same (e.g, different modes)
6682 or if the values are different, we can't merge this reload.
6683 But if it is an input reload, we might still merge
6684 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6686 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6687 || rld[j].out != 0 || rld[j].in == 0
6688 || ! rtx_equal_p (rld[i].in, rld[j].in))
6690 if (rld[j].when_needed != RELOAD_FOR_INPUT
6691 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6692 || rld[i].opnum > rld[j].opnum)
6693 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6695 conflicting_input = 1;
6696 if (min_conflicting_input_opnum > rld[j].opnum)
6697 min_conflicting_input_opnum = rld[j].opnum;
6701 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6702 we, in fact, found any matching reloads. */
6705 && max_input_address_opnum <= min_conflicting_input_opnum)
6707 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6709 for (j = 0; j < n_reloads; j++)
6710 if (i != j && rld[j].reg_rtx != 0
6711 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6712 && (! conflicting_input
6713 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6714 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6716 rld[i].when_needed = RELOAD_OTHER;
6718 reload_spill_index[j] = -1;
6719 transfer_replacements (i, j);
6722 /* If this is now RELOAD_OTHER, look for any reloads that
6723 load parts of this operand and set them to
6724 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6725 RELOAD_OTHER for outputs. Note that this test is
6726 equivalent to looking for reloads for this operand
6729 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6730 it may share registers with a RELOAD_FOR_INPUT, so we can
6731 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6732 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6734 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6735 instruction is assigned the same register as the earlier
6736 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6737 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6738 instruction to be deleted later on. */
6740 if (rld[i].when_needed == RELOAD_OTHER)
6741 for (j = 0; j < n_reloads; j++)
6743 && rld[j].when_needed != RELOAD_OTHER
6744 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6745 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6746 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6747 && (! conflicting_input
6748 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6749 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6750 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6756 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6757 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6758 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6760 /* Check to see if we accidentally converted two
6761 reloads that use the same reload register with
6762 different inputs to the same type. If so, the
6763 resulting code won't work. */
6765 for (k = 0; k < j; k++)
6766 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6767 || rld[k].when_needed != rld[j].when_needed
6768 || !rtx_equal_p (rld[k].reg_rtx,
6770 || rtx_equal_p (rld[k].in,
6777 /* These arrays are filled by emit_reload_insns and its subroutines. */
6778 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6779 static rtx other_input_address_reload_insns = 0;
6780 static rtx other_input_reload_insns = 0;
6781 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6782 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6783 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6784 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6785 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6786 static rtx operand_reload_insns = 0;
6787 static rtx other_operand_reload_insns = 0;
6788 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6790 /* Values to be put in spill_reg_store are put here first. */
6791 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6792 static HARD_REG_SET reg_reloaded_died;
6794 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6795 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6796 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6797 adjusted register, and return true. Otherwise, return false. */
6799 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6800 enum reg_class new_class,
6801 enum machine_mode new_mode)
6806 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6808 unsigned regno = REGNO (reg);
6810 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6812 if (GET_MODE (reg) != new_mode)
6814 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6816 if (hard_regno_nregs[regno][new_mode]
6817 > hard_regno_nregs[regno][GET_MODE (reg)])
6819 reg = reload_adjust_reg_for_mode (reg, new_mode);
6827 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6828 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6829 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6830 adjusted register, and return true. Otherwise, return false. */
6832 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6833 enum insn_code icode)
6836 enum reg_class new_class = scratch_reload_class (icode);
6837 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6839 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6840 new_class, new_mode);
6843 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6844 has the number J. OLD contains the value to be used as input. */
6847 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6850 rtx insn = chain->insn;
6852 rtx oldequiv_reg = 0;
6855 enum machine_mode mode;
6858 /* delete_output_reload is only invoked properly if old contains
6859 the original pseudo register. Since this is replaced with a
6860 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6861 find the pseudo in RELOAD_IN_REG. */
6862 if (reload_override_in[j]
6863 && REG_P (rl->in_reg))
6870 else if (REG_P (oldequiv))
6871 oldequiv_reg = oldequiv;
6872 else if (GET_CODE (oldequiv) == SUBREG)
6873 oldequiv_reg = SUBREG_REG (oldequiv);
6875 reloadreg = reload_reg_rtx_for_input[j];
6876 mode = GET_MODE (reloadreg);
6878 /* If we are reloading from a register that was recently stored in
6879 with an output-reload, see if we can prove there was
6880 actually no need to store the old value in it. */
6882 if (optimize && REG_P (oldequiv)
6883 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6884 && spill_reg_store[REGNO (oldequiv)]
6886 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6887 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6889 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6891 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6894 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6895 oldequiv = SUBREG_REG (oldequiv);
6896 if (GET_MODE (oldequiv) != VOIDmode
6897 && mode != GET_MODE (oldequiv))
6898 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6900 /* Switch to the right place to emit the reload insns. */
6901 switch (rl->when_needed)
6904 where = &other_input_reload_insns;
6906 case RELOAD_FOR_INPUT:
6907 where = &input_reload_insns[rl->opnum];
6909 case RELOAD_FOR_INPUT_ADDRESS:
6910 where = &input_address_reload_insns[rl->opnum];
6912 case RELOAD_FOR_INPADDR_ADDRESS:
6913 where = &inpaddr_address_reload_insns[rl->opnum];
6915 case RELOAD_FOR_OUTPUT_ADDRESS:
6916 where = &output_address_reload_insns[rl->opnum];
6918 case RELOAD_FOR_OUTADDR_ADDRESS:
6919 where = &outaddr_address_reload_insns[rl->opnum];
6921 case RELOAD_FOR_OPERAND_ADDRESS:
6922 where = &operand_reload_insns;
6924 case RELOAD_FOR_OPADDR_ADDR:
6925 where = &other_operand_reload_insns;
6927 case RELOAD_FOR_OTHER_ADDRESS:
6928 where = &other_input_address_reload_insns;
6934 push_to_sequence (*where);
6936 /* Auto-increment addresses must be reloaded in a special way. */
6937 if (rl->out && ! rl->out_reg)
6939 /* We are not going to bother supporting the case where a
6940 incremented register can't be copied directly from
6941 OLDEQUIV since this seems highly unlikely. */
6942 gcc_assert (rl->secondary_in_reload < 0);
6944 if (reload_inherited[j])
6945 oldequiv = reloadreg;
6947 old = XEXP (rl->in_reg, 0);
6949 if (optimize && REG_P (oldequiv)
6950 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6951 && spill_reg_store[REGNO (oldequiv)]
6953 && (dead_or_set_p (insn,
6954 spill_reg_stored_to[REGNO (oldequiv)])
6955 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6957 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6959 /* Prevent normal processing of this reload. */
6961 /* Output a special code sequence for this case. */
6962 new_spill_reg_store[REGNO (reloadreg)]
6963 = inc_for_reload (reloadreg, oldequiv, rl->out,
6967 /* If we are reloading a pseudo-register that was set by the previous
6968 insn, see if we can get rid of that pseudo-register entirely
6969 by redirecting the previous insn into our reload register. */
6971 else if (optimize && REG_P (old)
6972 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6973 && dead_or_set_p (insn, old)
6974 /* This is unsafe if some other reload
6975 uses the same reg first. */
6976 && ! conflicts_with_override (reloadreg)
6977 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6978 rl->when_needed, old, rl->out, j, 0))
6980 rtx temp = PREV_INSN (insn);
6981 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp)))
6982 temp = PREV_INSN (temp);
6984 && NONJUMP_INSN_P (temp)
6985 && GET_CODE (PATTERN (temp)) == SET
6986 && SET_DEST (PATTERN (temp)) == old
6987 /* Make sure we can access insn_operand_constraint. */
6988 && asm_noperands (PATTERN (temp)) < 0
6989 /* This is unsafe if operand occurs more than once in current
6990 insn. Perhaps some occurrences aren't reloaded. */
6991 && count_occurrences (PATTERN (insn), old, 0) == 1)
6993 rtx old = SET_DEST (PATTERN (temp));
6994 /* Store into the reload register instead of the pseudo. */
6995 SET_DEST (PATTERN (temp)) = reloadreg;
6997 /* Verify that resulting insn is valid. */
6998 extract_insn (temp);
6999 if (constrain_operands (1))
7001 /* If the previous insn is an output reload, the source is
7002 a reload register, and its spill_reg_store entry will
7003 contain the previous destination. This is now
7005 if (REG_P (SET_SRC (PATTERN (temp)))
7006 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
7008 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7009 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
7012 /* If these are the only uses of the pseudo reg,
7013 pretend for GDB it lives in the reload reg we used. */
7014 if (REG_N_DEATHS (REGNO (old)) == 1
7015 && REG_N_SETS (REGNO (old)) == 1)
7017 reg_renumber[REGNO (old)] = REGNO (reloadreg);
7018 if (ira_conflicts_p)
7019 /* Inform IRA about the change. */
7020 ira_mark_allocation_change (REGNO (old));
7021 alter_reg (REGNO (old), -1, false);
7025 /* Adjust any debug insns between temp and insn. */
7026 while ((temp = NEXT_INSN (temp)) != insn)
7027 if (DEBUG_INSN_P (temp))
7028 replace_rtx (PATTERN (temp), old, reloadreg);
7030 gcc_assert (NOTE_P (temp));
7034 SET_DEST (PATTERN (temp)) = old;
7039 /* We can't do that, so output an insn to load RELOADREG. */
7041 /* If we have a secondary reload, pick up the secondary register
7042 and icode, if any. If OLDEQUIV and OLD are different or
7043 if this is an in-out reload, recompute whether or not we
7044 still need a secondary register and what the icode should
7045 be. If we still need a secondary register and the class or
7046 icode is different, go back to reloading from OLD if using
7047 OLDEQUIV means that we got the wrong type of register. We
7048 cannot have different class or icode due to an in-out reload
7049 because we don't make such reloads when both the input and
7050 output need secondary reload registers. */
7052 if (! special && rl->secondary_in_reload >= 0)
7054 rtx second_reload_reg = 0;
7055 rtx third_reload_reg = 0;
7056 int secondary_reload = rl->secondary_in_reload;
7057 rtx real_oldequiv = oldequiv;
7060 enum insn_code icode;
7061 enum insn_code tertiary_icode = CODE_FOR_nothing;
7063 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7064 and similarly for OLD.
7065 See comments in get_secondary_reload in reload.c. */
7066 /* If it is a pseudo that cannot be replaced with its
7067 equivalent MEM, we must fall back to reload_in, which
7068 will have all the necessary substitutions registered.
7069 Likewise for a pseudo that can't be replaced with its
7070 equivalent constant.
7072 Take extra care for subregs of such pseudos. Note that
7073 we cannot use reg_equiv_mem in this case because it is
7074 not in the right mode. */
7077 if (GET_CODE (tmp) == SUBREG)
7078 tmp = SUBREG_REG (tmp);
7080 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7081 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7082 || reg_equiv_constant[REGNO (tmp)] != 0))
7084 if (! reg_equiv_mem[REGNO (tmp)]
7085 || num_not_at_initial_offset
7086 || GET_CODE (oldequiv) == SUBREG)
7087 real_oldequiv = rl->in;
7089 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7093 if (GET_CODE (tmp) == SUBREG)
7094 tmp = SUBREG_REG (tmp);
7096 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7097 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7098 || reg_equiv_constant[REGNO (tmp)] != 0))
7100 if (! reg_equiv_mem[REGNO (tmp)]
7101 || num_not_at_initial_offset
7102 || GET_CODE (old) == SUBREG)
7105 real_old = reg_equiv_mem[REGNO (tmp)];
7108 second_reload_reg = rld[secondary_reload].reg_rtx;
7109 if (rld[secondary_reload].secondary_in_reload >= 0)
7111 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7113 third_reload_reg = rld[tertiary_reload].reg_rtx;
7114 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7115 /* We'd have to add more code for quartary reloads. */
7116 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7118 icode = rl->secondary_in_icode;
7120 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7121 || (rl->in != 0 && rl->out != 0))
7123 secondary_reload_info sri, sri2;
7124 enum reg_class new_class, new_t_class;
7126 sri.icode = CODE_FOR_nothing;
7127 sri.prev_sri = NULL;
7128 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7131 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7132 second_reload_reg = 0;
7133 else if (new_class == NO_REGS)
7135 if (reload_adjust_reg_for_icode (&second_reload_reg,
7137 (enum insn_code) sri.icode))
7139 icode = (enum insn_code) sri.icode;
7140 third_reload_reg = 0;
7145 real_oldequiv = real_old;
7148 else if (sri.icode != CODE_FOR_nothing)
7149 /* We currently lack a way to express this in reloads. */
7153 sri2.icode = CODE_FOR_nothing;
7154 sri2.prev_sri = &sri;
7155 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7156 new_class, mode, &sri);
7157 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7159 if (reload_adjust_reg_for_temp (&second_reload_reg,
7163 third_reload_reg = 0;
7164 tertiary_icode = (enum insn_code) sri2.icode;
7169 real_oldequiv = real_old;
7172 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7174 rtx intermediate = second_reload_reg;
7176 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7178 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7182 second_reload_reg = intermediate;
7183 tertiary_icode = (enum insn_code) sri2.icode;
7188 real_oldequiv = real_old;
7191 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7193 rtx intermediate = second_reload_reg;
7195 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7197 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7200 second_reload_reg = intermediate;
7201 tertiary_icode = (enum insn_code) sri2.icode;
7206 real_oldequiv = real_old;
7211 /* This could be handled more intelligently too. */
7213 real_oldequiv = real_old;
7218 /* If we still need a secondary reload register, check
7219 to see if it is being used as a scratch or intermediate
7220 register and generate code appropriately. If we need
7221 a scratch register, use REAL_OLDEQUIV since the form of
7222 the insn may depend on the actual address if it is
7225 if (second_reload_reg)
7227 if (icode != CODE_FOR_nothing)
7229 /* We'd have to add extra code to handle this case. */
7230 gcc_assert (!third_reload_reg);
7232 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7233 second_reload_reg));
7238 /* See if we need a scratch register to load the
7239 intermediate register (a tertiary reload). */
7240 if (tertiary_icode != CODE_FOR_nothing)
7242 emit_insn ((GEN_FCN (tertiary_icode)
7243 (second_reload_reg, real_oldequiv,
7244 third_reload_reg)));
7246 else if (third_reload_reg)
7248 gen_reload (third_reload_reg, real_oldequiv,
7251 gen_reload (second_reload_reg, third_reload_reg,
7256 gen_reload (second_reload_reg, real_oldequiv,
7260 oldequiv = second_reload_reg;
7265 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7267 rtx real_oldequiv = oldequiv;
7269 if ((REG_P (oldequiv)
7270 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7271 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7272 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7273 || (GET_CODE (oldequiv) == SUBREG
7274 && REG_P (SUBREG_REG (oldequiv))
7275 && (REGNO (SUBREG_REG (oldequiv))
7276 >= FIRST_PSEUDO_REGISTER)
7277 && ((reg_equiv_memory_loc
7278 [REGNO (SUBREG_REG (oldequiv))] != 0)
7279 || (reg_equiv_constant
7280 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7281 || (CONSTANT_P (oldequiv)
7282 && (PREFERRED_RELOAD_CLASS (oldequiv,
7283 REGNO_REG_CLASS (REGNO (reloadreg)))
7285 real_oldequiv = rl->in;
7286 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7290 if (flag_non_call_exceptions)
7291 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7293 /* End this sequence. */
7294 *where = get_insns ();
7297 /* Update reload_override_in so that delete_address_reloads_1
7298 can see the actual register usage. */
7300 reload_override_in[j] = oldequiv;
7303 /* Generate insns to for the output reload RL, which is for the insn described
7304 by CHAIN and has the number J. */
7306 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7310 rtx insn = chain->insn;
7313 enum machine_mode mode;
7317 if (rl->when_needed == RELOAD_OTHER)
7320 push_to_sequence (output_reload_insns[rl->opnum]);
7322 rl_reg_rtx = reload_reg_rtx_for_output[j];
7323 mode = GET_MODE (rl_reg_rtx);
7325 reloadreg = rl_reg_rtx;
7327 /* If we need two reload regs, set RELOADREG to the intermediate
7328 one, since it will be stored into OLD. We might need a secondary
7329 register only for an input reload, so check again here. */
7331 if (rl->secondary_out_reload >= 0)
7334 int secondary_reload = rl->secondary_out_reload;
7335 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7337 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7338 && reg_equiv_mem[REGNO (old)] != 0)
7339 real_old = reg_equiv_mem[REGNO (old)];
7341 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7343 rtx second_reloadreg = reloadreg;
7344 reloadreg = rld[secondary_reload].reg_rtx;
7346 /* See if RELOADREG is to be used as a scratch register
7347 or as an intermediate register. */
7348 if (rl->secondary_out_icode != CODE_FOR_nothing)
7350 /* We'd have to add extra code to handle this case. */
7351 gcc_assert (tertiary_reload < 0);
7353 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7354 (real_old, second_reloadreg, reloadreg)));
7359 /* See if we need both a scratch and intermediate reload
7362 enum insn_code tertiary_icode
7363 = rld[secondary_reload].secondary_out_icode;
7365 /* We'd have to add more code for quartary reloads. */
7366 gcc_assert (tertiary_reload < 0
7367 || rld[tertiary_reload].secondary_out_reload < 0);
7369 if (GET_MODE (reloadreg) != mode)
7370 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7372 if (tertiary_icode != CODE_FOR_nothing)
7374 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7377 /* Copy primary reload reg to secondary reload reg.
7378 (Note that these have been swapped above, then
7379 secondary reload reg to OLD using our insn.) */
7381 /* If REAL_OLD is a paradoxical SUBREG, remove it
7382 and try to put the opposite SUBREG on
7384 if (GET_CODE (real_old) == SUBREG
7385 && (GET_MODE_SIZE (GET_MODE (real_old))
7386 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7387 && 0 != (tem = gen_lowpart_common
7388 (GET_MODE (SUBREG_REG (real_old)),
7390 real_old = SUBREG_REG (real_old), reloadreg = tem;
7392 gen_reload (reloadreg, second_reloadreg,
7393 rl->opnum, rl->when_needed);
7394 emit_insn ((GEN_FCN (tertiary_icode)
7395 (real_old, reloadreg, third_reloadreg)));
7401 /* Copy between the reload regs here and then to
7404 gen_reload (reloadreg, second_reloadreg,
7405 rl->opnum, rl->when_needed);
7406 if (tertiary_reload >= 0)
7408 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7410 gen_reload (third_reloadreg, reloadreg,
7411 rl->opnum, rl->when_needed);
7412 reloadreg = third_reloadreg;
7419 /* Output the last reload insn. */
7424 /* Don't output the last reload if OLD is not the dest of
7425 INSN and is in the src and is clobbered by INSN. */
7426 if (! flag_expensive_optimizations
7428 || !(set = single_set (insn))
7429 || rtx_equal_p (old, SET_DEST (set))
7430 || !reg_mentioned_p (old, SET_SRC (set))
7431 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7432 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7433 gen_reload (old, reloadreg, rl->opnum,
7437 /* Look at all insns we emitted, just to be safe. */
7438 for (p = get_insns (); p; p = NEXT_INSN (p))
7441 rtx pat = PATTERN (p);
7443 /* If this output reload doesn't come from a spill reg,
7444 clear any memory of reloaded copies of the pseudo reg.
7445 If this output reload comes from a spill reg,
7446 reg_has_output_reload will make this do nothing. */
7447 note_stores (pat, forget_old_reloads_1, NULL);
7449 if (reg_mentioned_p (rl_reg_rtx, pat))
7451 rtx set = single_set (insn);
7452 if (reload_spill_index[j] < 0
7454 && SET_SRC (set) == rl_reg_rtx)
7456 int src = REGNO (SET_SRC (set));
7458 reload_spill_index[j] = src;
7459 SET_HARD_REG_BIT (reg_is_output_reload, src);
7460 if (find_regno_note (insn, REG_DEAD, src))
7461 SET_HARD_REG_BIT (reg_reloaded_died, src);
7463 if (HARD_REGISTER_P (rl_reg_rtx))
7465 int s = rl->secondary_out_reload;
7466 set = single_set (p);
7467 /* If this reload copies only to the secondary reload
7468 register, the secondary reload does the actual
7470 if (s >= 0 && set == NULL_RTX)
7471 /* We can't tell what function the secondary reload
7472 has and where the actual store to the pseudo is
7473 made; leave new_spill_reg_store alone. */
7476 && SET_SRC (set) == rl_reg_rtx
7477 && SET_DEST (set) == rld[s].reg_rtx)
7479 /* Usually the next instruction will be the
7480 secondary reload insn; if we can confirm
7481 that it is, setting new_spill_reg_store to
7482 that insn will allow an extra optimization. */
7483 rtx s_reg = rld[s].reg_rtx;
7484 rtx next = NEXT_INSN (p);
7485 rld[s].out = rl->out;
7486 rld[s].out_reg = rl->out_reg;
7487 set = single_set (next);
7488 if (set && SET_SRC (set) == s_reg
7489 && ! new_spill_reg_store[REGNO (s_reg)])
7491 SET_HARD_REG_BIT (reg_is_output_reload,
7493 new_spill_reg_store[REGNO (s_reg)] = next;
7497 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7502 if (rl->when_needed == RELOAD_OTHER)
7504 emit_insn (other_output_reload_insns[rl->opnum]);
7505 other_output_reload_insns[rl->opnum] = get_insns ();
7508 output_reload_insns[rl->opnum] = get_insns ();
7510 if (flag_non_call_exceptions)
7511 copy_reg_eh_region_note_forward (insn, get_insns (), NULL);
7516 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7517 and has the number J. */
7519 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7521 rtx insn = chain->insn;
7522 rtx old = (rl->in && MEM_P (rl->in)
7523 ? rl->in_reg : rl->in);
7524 rtx reg_rtx = rl->reg_rtx;
7528 enum machine_mode mode;
7530 /* Determine the mode to reload in.
7531 This is very tricky because we have three to choose from.
7532 There is the mode the insn operand wants (rl->inmode).
7533 There is the mode of the reload register RELOADREG.
7534 There is the intrinsic mode of the operand, which we could find
7535 by stripping some SUBREGs.
7536 It turns out that RELOADREG's mode is irrelevant:
7537 we can change that arbitrarily.
7539 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7540 then the reload reg may not support QImode moves, so use SImode.
7541 If foo is in memory due to spilling a pseudo reg, this is safe,
7542 because the QImode value is in the least significant part of a
7543 slot big enough for a SImode. If foo is some other sort of
7544 memory reference, then it is impossible to reload this case,
7545 so previous passes had better make sure this never happens.
7547 Then consider a one-word union which has SImode and one of its
7548 members is a float, being fetched as (SUBREG:SF union:SI).
7549 We must fetch that as SFmode because we could be loading into
7550 a float-only register. In this case OLD's mode is correct.
7552 Consider an immediate integer: it has VOIDmode. Here we need
7553 to get a mode from something else.
7555 In some cases, there is a fourth mode, the operand's
7556 containing mode. If the insn specifies a containing mode for
7557 this operand, it overrides all others.
7559 I am not sure whether the algorithm here is always right,
7560 but it does the right things in those cases. */
7562 mode = GET_MODE (old);
7563 if (mode == VOIDmode)
7566 /* We cannot use gen_lowpart_common since it can do the wrong thing
7567 when REG_RTX has a multi-word mode. Note that REG_RTX must
7568 always be a REG here. */
7569 if (GET_MODE (reg_rtx) != mode)
7570 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7572 reload_reg_rtx_for_input[j] = reg_rtx;
7575 /* AUTO_INC reloads need to be handled even if inherited. We got an
7576 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7577 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7578 && ! rtx_equal_p (reg_rtx, old)
7580 emit_input_reload_insns (chain, rld + j, old, j);
7582 /* When inheriting a wider reload, we have a MEM in rl->in,
7583 e.g. inheriting a SImode output reload for
7584 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7585 if (optimize && reload_inherited[j] && rl->in
7587 && MEM_P (rl->in_reg)
7588 && reload_spill_index[j] >= 0
7589 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7590 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7592 /* If we are reloading a register that was recently stored in with an
7593 output-reload, see if we can prove there was
7594 actually no need to store the old value in it. */
7597 && (reload_inherited[j] || reload_override_in[j])
7600 && spill_reg_store[REGNO (reg_rtx)] != 0
7602 /* There doesn't seem to be any reason to restrict this to pseudos
7603 and doing so loses in the case where we are copying from a
7604 register of the wrong class. */
7605 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7607 /* The insn might have already some references to stackslots
7608 replaced by MEMs, while reload_out_reg still names the
7610 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7611 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7612 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7615 /* Do output reloading for reload RL, which is for the insn described by
7616 CHAIN and has the number J.
7617 ??? At some point we need to support handling output reloads of
7618 JUMP_INSNs or insns that set cc0. */
7620 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7623 rtx insn = chain->insn;
7624 /* If this is an output reload that stores something that is
7625 not loaded in this same reload, see if we can eliminate a previous
7627 rtx pseudo = rl->out_reg;
7628 rtx reg_rtx = rl->reg_rtx;
7630 if (rl->out && reg_rtx)
7632 enum machine_mode mode;
7634 /* Determine the mode to reload in.
7635 See comments above (for input reloading). */
7636 mode = GET_MODE (rl->out);
7637 if (mode == VOIDmode)
7639 /* VOIDmode should never happen for an output. */
7640 if (asm_noperands (PATTERN (insn)) < 0)
7641 /* It's the compiler's fault. */
7642 fatal_insn ("VOIDmode on an output", insn);
7643 error_for_asm (insn, "output operand is constant in %<asm%>");
7644 /* Prevent crash--use something we know is valid. */
7646 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7648 if (GET_MODE (reg_rtx) != mode)
7649 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7651 reload_reg_rtx_for_output[j] = reg_rtx;
7656 && ! rtx_equal_p (rl->in_reg, pseudo)
7657 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7658 && reg_last_reload_reg[REGNO (pseudo)])
7660 int pseudo_no = REGNO (pseudo);
7661 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7663 /* We don't need to test full validity of last_regno for
7664 inherit here; we only want to know if the store actually
7665 matches the pseudo. */
7666 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7667 && reg_reloaded_contents[last_regno] == pseudo_no
7668 && spill_reg_store[last_regno]
7669 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7670 delete_output_reload (insn, j, last_regno, reg_rtx);
7676 || rtx_equal_p (old, reg_rtx))
7679 /* An output operand that dies right away does need a reload,
7680 but need not be copied from it. Show the new location in the
7682 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7683 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7685 XEXP (note, 0) = reg_rtx;
7688 /* Likewise for a SUBREG of an operand that dies. */
7689 else if (GET_CODE (old) == SUBREG
7690 && REG_P (SUBREG_REG (old))
7691 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7694 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7697 else if (GET_CODE (old) == SCRATCH)
7698 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7699 but we don't want to make an output reload. */
7702 /* If is a JUMP_INSN, we can't support output reloads yet. */
7703 gcc_assert (NONJUMP_INSN_P (insn));
7705 emit_output_reload_insns (chain, rld + j, j);
7708 /* A reload copies values of MODE from register SRC to register DEST.
7709 Return true if it can be treated for inheritance purposes like a
7710 group of reloads, each one reloading a single hard register. The
7711 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7712 occupy the same number of hard registers. */
7715 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7716 int src ATTRIBUTE_UNUSED,
7717 enum machine_mode mode ATTRIBUTE_UNUSED)
7719 #ifdef CANNOT_CHANGE_MODE_CLASS
7720 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7721 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7727 /* Output insns to reload values in and out of the chosen reload regs. */
7730 emit_reload_insns (struct insn_chain *chain)
7732 rtx insn = chain->insn;
7736 CLEAR_HARD_REG_SET (reg_reloaded_died);
7738 for (j = 0; j < reload_n_operands; j++)
7739 input_reload_insns[j] = input_address_reload_insns[j]
7740 = inpaddr_address_reload_insns[j]
7741 = output_reload_insns[j] = output_address_reload_insns[j]
7742 = outaddr_address_reload_insns[j]
7743 = other_output_reload_insns[j] = 0;
7744 other_input_address_reload_insns = 0;
7745 other_input_reload_insns = 0;
7746 operand_reload_insns = 0;
7747 other_operand_reload_insns = 0;
7749 /* Dump reloads into the dump file. */
7752 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7753 debug_reload_to_stream (dump_file);
7756 /* Now output the instructions to copy the data into and out of the
7757 reload registers. Do these in the order that the reloads were reported,
7758 since reloads of base and index registers precede reloads of operands
7759 and the operands may need the base and index registers reloaded. */
7761 for (j = 0; j < n_reloads; j++)
7763 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7767 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7768 new_spill_reg_store[i] = 0;
7771 do_input_reload (chain, rld + j, j);
7772 do_output_reload (chain, rld + j, j);
7775 /* Now write all the insns we made for reloads in the order expected by
7776 the allocation functions. Prior to the insn being reloaded, we write
7777 the following reloads:
7779 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7781 RELOAD_OTHER reloads.
7783 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7784 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7785 RELOAD_FOR_INPUT reload for the operand.
7787 RELOAD_FOR_OPADDR_ADDRS reloads.
7789 RELOAD_FOR_OPERAND_ADDRESS reloads.
7791 After the insn being reloaded, we write the following:
7793 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7794 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7795 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7796 reloads for the operand. The RELOAD_OTHER output reloads are
7797 output in descending order by reload number. */
7799 emit_insn_before (other_input_address_reload_insns, insn);
7800 emit_insn_before (other_input_reload_insns, insn);
7802 for (j = 0; j < reload_n_operands; j++)
7804 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7805 emit_insn_before (input_address_reload_insns[j], insn);
7806 emit_insn_before (input_reload_insns[j], insn);
7809 emit_insn_before (other_operand_reload_insns, insn);
7810 emit_insn_before (operand_reload_insns, insn);
7812 for (j = 0; j < reload_n_operands; j++)
7814 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7815 x = emit_insn_after (output_address_reload_insns[j], x);
7816 x = emit_insn_after (output_reload_insns[j], x);
7817 emit_insn_after (other_output_reload_insns[j], x);
7820 /* For all the spill regs newly reloaded in this instruction,
7821 record what they were reloaded from, so subsequent instructions
7822 can inherit the reloads.
7824 Update spill_reg_store for the reloads of this insn.
7825 Copy the elements that were updated in the loop above. */
7827 for (j = 0; j < n_reloads; j++)
7829 int r = reload_order[j];
7830 int i = reload_spill_index[r];
7832 /* If this is a non-inherited input reload from a pseudo, we must
7833 clear any memory of a previous store to the same pseudo. Only do
7834 something if there will not be an output reload for the pseudo
7836 if (rld[r].in_reg != 0
7837 && ! (reload_inherited[r] || reload_override_in[r]))
7839 rtx reg = rld[r].in_reg;
7841 if (GET_CODE (reg) == SUBREG)
7842 reg = SUBREG_REG (reg);
7845 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7846 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7848 int nregno = REGNO (reg);
7850 if (reg_last_reload_reg[nregno])
7852 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7854 if (reg_reloaded_contents[last_regno] == nregno)
7855 spill_reg_store[last_regno] = 0;
7860 /* I is nonneg if this reload used a register.
7861 If rld[r].reg_rtx is 0, this is an optional reload
7862 that we opted to ignore. */
7864 if (i >= 0 && rld[r].reg_rtx != 0)
7866 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7869 /* For a multi register reload, we need to check if all or part
7870 of the value lives to the end. */
7871 for (k = 0; k < nr; k++)
7872 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7873 rld[r].when_needed))
7874 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7876 /* Maybe the spill reg contains a copy of reload_out. */
7878 && (REG_P (rld[r].out)
7882 || REG_P (rld[r].out_reg)))
7885 enum machine_mode mode;
7888 reg = reload_reg_rtx_for_output[r];
7889 mode = GET_MODE (reg);
7890 regno = REGNO (reg);
7891 nregs = hard_regno_nregs[regno][mode];
7892 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7893 rld[r].when_needed))
7895 rtx out = (REG_P (rld[r].out)
7899 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7900 int out_regno = REGNO (out);
7901 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7902 : hard_regno_nregs[out_regno][mode]);
7905 spill_reg_store[regno] = new_spill_reg_store[regno];
7906 spill_reg_stored_to[regno] = out;
7907 reg_last_reload_reg[out_regno] = reg;
7909 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7910 && nregs == out_nregs
7911 && inherit_piecemeal_p (out_regno, regno, mode));
7913 /* If OUT_REGNO is a hard register, it may occupy more than
7914 one register. If it does, say what is in the
7915 rest of the registers assuming that both registers
7916 agree on how many words the object takes. If not,
7917 invalidate the subsequent registers. */
7919 if (HARD_REGISTER_NUM_P (out_regno))
7920 for (k = 1; k < out_nregs; k++)
7921 reg_last_reload_reg[out_regno + k]
7922 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7924 /* Now do the inverse operation. */
7925 for (k = 0; k < nregs; k++)
7927 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7928 reg_reloaded_contents[regno + k]
7929 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7932 reg_reloaded_insn[regno + k] = insn;
7933 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7934 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7935 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7938 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7943 /* Maybe the spill reg contains a copy of reload_in. Only do
7944 something if there will not be an output reload for
7945 the register being reloaded. */
7946 else if (rld[r].out_reg == 0
7948 && ((REG_P (rld[r].in)
7949 && !HARD_REGISTER_P (rld[r].in)
7950 && !REGNO_REG_SET_P (®_has_output_reload,
7952 || (REG_P (rld[r].in_reg)
7953 && !REGNO_REG_SET_P (®_has_output_reload,
7954 REGNO (rld[r].in_reg))))
7955 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7958 enum machine_mode mode;
7961 reg = reload_reg_rtx_for_input[r];
7962 mode = GET_MODE (reg);
7963 regno = REGNO (reg);
7964 nregs = hard_regno_nregs[regno][mode];
7965 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7966 rld[r].when_needed))
7973 if (REG_P (rld[r].in)
7974 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7976 else if (REG_P (rld[r].in_reg))
7979 in = XEXP (rld[r].in_reg, 0);
7980 in_regno = REGNO (in);
7982 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7983 : hard_regno_nregs[in_regno][mode]);
7985 reg_last_reload_reg[in_regno] = reg;
7987 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7988 && nregs == in_nregs
7989 && inherit_piecemeal_p (regno, in_regno, mode));
7991 if (HARD_REGISTER_NUM_P (in_regno))
7992 for (k = 1; k < in_nregs; k++)
7993 reg_last_reload_reg[in_regno + k]
7994 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7996 /* Unless we inherited this reload, show we haven't
7997 recently done a store.
7998 Previous stores of inherited auto_inc expressions
7999 also have to be discarded. */
8000 if (! reload_inherited[r]
8001 || (rld[r].out && ! rld[r].out_reg))
8002 spill_reg_store[regno] = 0;
8004 for (k = 0; k < nregs; k++)
8006 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
8007 reg_reloaded_contents[regno + k]
8008 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
8011 reg_reloaded_insn[regno + k] = insn;
8012 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
8013 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
8014 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8017 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8024 /* The following if-statement was #if 0'd in 1.34 (or before...).
8025 It's reenabled in 1.35 because supposedly nothing else
8026 deals with this problem. */
8028 /* If a register gets output-reloaded from a non-spill register,
8029 that invalidates any previous reloaded copy of it.
8030 But forget_old_reloads_1 won't get to see it, because
8031 it thinks only about the original insn. So invalidate it here.
8032 Also do the same thing for RELOAD_OTHER constraints where the
8033 output is discarded. */
8035 && ((rld[r].out != 0
8036 && (REG_P (rld[r].out)
8037 || (MEM_P (rld[r].out)
8038 && REG_P (rld[r].out_reg))))
8039 || (rld[r].out == 0 && rld[r].out_reg
8040 && REG_P (rld[r].out_reg))))
8042 rtx out = ((rld[r].out && REG_P (rld[r].out))
8043 ? rld[r].out : rld[r].out_reg);
8044 int out_regno = REGNO (out);
8045 enum machine_mode mode = GET_MODE (out);
8047 /* REG_RTX is now set or clobbered by the main instruction.
8048 As the comment above explains, forget_old_reloads_1 only
8049 sees the original instruction, and there is no guarantee
8050 that the original instruction also clobbered REG_RTX.
8051 For example, if find_reloads sees that the input side of
8052 a matched operand pair dies in this instruction, it may
8053 use the input register as the reload register.
8055 Calling forget_old_reloads_1 is a waste of effort if
8056 REG_RTX is also the output register.
8058 If we know that REG_RTX holds the value of a pseudo
8059 register, the code after the call will record that fact. */
8060 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8061 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8063 if (!HARD_REGISTER_NUM_P (out_regno))
8065 rtx src_reg, store_insn = NULL_RTX;
8067 reg_last_reload_reg[out_regno] = 0;
8069 /* If we can find a hard register that is stored, record
8070 the storing insn so that we may delete this insn with
8071 delete_output_reload. */
8072 src_reg = reload_reg_rtx_for_output[r];
8074 /* If this is an optional reload, try to find the source reg
8075 from an input reload. */
8078 rtx set = single_set (insn);
8079 if (set && SET_DEST (set) == rld[r].out)
8083 src_reg = SET_SRC (set);
8085 for (k = 0; k < n_reloads; k++)
8087 if (rld[k].in == src_reg)
8089 src_reg = reload_reg_rtx_for_input[k];
8096 store_insn = new_spill_reg_store[REGNO (src_reg)];
8097 if (src_reg && REG_P (src_reg)
8098 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8100 int src_regno, src_nregs, k;
8103 gcc_assert (GET_MODE (src_reg) == mode);
8104 src_regno = REGNO (src_reg);
8105 src_nregs = hard_regno_nregs[src_regno][mode];
8106 /* The place where to find a death note varies with
8107 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8108 necessarily checked exactly in the code that moves
8109 notes, so just check both locations. */
8110 note = find_regno_note (insn, REG_DEAD, src_regno);
8111 if (! note && store_insn)
8112 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8113 for (k = 0; k < src_nregs; k++)
8115 spill_reg_store[src_regno + k] = store_insn;
8116 spill_reg_stored_to[src_regno + k] = out;
8117 reg_reloaded_contents[src_regno + k] = out_regno;
8118 reg_reloaded_insn[src_regno + k] = store_insn;
8119 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8120 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8121 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8123 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8126 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8128 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8130 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8132 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8134 reg_last_reload_reg[out_regno] = src_reg;
8135 /* We have to set reg_has_output_reload here, or else
8136 forget_old_reloads_1 will clear reg_last_reload_reg
8138 SET_REGNO_REG_SET (®_has_output_reload,
8144 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8146 for (k = 0; k < out_nregs; k++)
8147 reg_last_reload_reg[out_regno + k] = 0;
8151 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8154 /* Go through the motions to emit INSN and test if it is strictly valid.
8155 Return the emitted insn if valid, else return NULL. */
8158 emit_insn_if_valid_for_reload (rtx insn)
8160 rtx last = get_last_insn ();
8163 insn = emit_insn (insn);
8164 code = recog_memoized (insn);
8168 extract_insn (insn);
8169 /* We want constrain operands to treat this insn strictly in its
8170 validity determination, i.e., the way it would after reload has
8172 if (constrain_operands (1))
8176 delete_insns_since (last);
8180 /* Emit code to perform a reload from IN (which may be a reload register) to
8181 OUT (which may also be a reload register). IN or OUT is from operand
8182 OPNUM with reload type TYPE.
8184 Returns first insn emitted. */
8187 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8189 rtx last = get_last_insn ();
8192 /* If IN is a paradoxical SUBREG, remove it and try to put the
8193 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8194 if (GET_CODE (in) == SUBREG
8195 && (GET_MODE_SIZE (GET_MODE (in))
8196 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8197 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8198 in = SUBREG_REG (in), out = tem;
8199 else if (GET_CODE (out) == SUBREG
8200 && (GET_MODE_SIZE (GET_MODE (out))
8201 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8202 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8203 out = SUBREG_REG (out), in = tem;
8205 /* How to do this reload can get quite tricky. Normally, we are being
8206 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8207 register that didn't get a hard register. In that case we can just
8208 call emit_move_insn.
8210 We can also be asked to reload a PLUS that adds a register or a MEM to
8211 another register, constant or MEM. This can occur during frame pointer
8212 elimination and while reloading addresses. This case is handled by
8213 trying to emit a single insn to perform the add. If it is not valid,
8214 we use a two insn sequence.
8216 Or we can be asked to reload an unary operand that was a fragment of
8217 an addressing mode, into a register. If it isn't recognized as-is,
8218 we try making the unop operand and the reload-register the same:
8219 (set reg:X (unop:X expr:Y))
8220 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8222 Finally, we could be called to handle an 'o' constraint by putting
8223 an address into a register. In that case, we first try to do this
8224 with a named pattern of "reload_load_address". If no such pattern
8225 exists, we just emit a SET insn and hope for the best (it will normally
8226 be valid on machines that use 'o').
8228 This entire process is made complex because reload will never
8229 process the insns we generate here and so we must ensure that
8230 they will fit their constraints and also by the fact that parts of
8231 IN might be being reloaded separately and replaced with spill registers.
8232 Because of this, we are, in some sense, just guessing the right approach
8233 here. The one listed above seems to work.
8235 ??? At some point, this whole thing needs to be rethought. */
8237 if (GET_CODE (in) == PLUS
8238 && (REG_P (XEXP (in, 0))
8239 || GET_CODE (XEXP (in, 0)) == SUBREG
8240 || MEM_P (XEXP (in, 0)))
8241 && (REG_P (XEXP (in, 1))
8242 || GET_CODE (XEXP (in, 1)) == SUBREG
8243 || CONSTANT_P (XEXP (in, 1))
8244 || MEM_P (XEXP (in, 1))))
8246 /* We need to compute the sum of a register or a MEM and another
8247 register, constant, or MEM, and put it into the reload
8248 register. The best possible way of doing this is if the machine
8249 has a three-operand ADD insn that accepts the required operands.
8251 The simplest approach is to try to generate such an insn and see if it
8252 is recognized and matches its constraints. If so, it can be used.
8254 It might be better not to actually emit the insn unless it is valid,
8255 but we need to pass the insn as an operand to `recog' and
8256 `extract_insn' and it is simpler to emit and then delete the insn if
8257 not valid than to dummy things up. */
8259 rtx op0, op1, tem, insn;
8262 op0 = find_replacement (&XEXP (in, 0));
8263 op1 = find_replacement (&XEXP (in, 1));
8265 /* Since constraint checking is strict, commutativity won't be
8266 checked, so we need to do that here to avoid spurious failure
8267 if the add instruction is two-address and the second operand
8268 of the add is the same as the reload reg, which is frequently
8269 the case. If the insn would be A = B + A, rearrange it so
8270 it will be A = A + B as constrain_operands expects. */
8272 if (REG_P (XEXP (in, 1))
8273 && REGNO (out) == REGNO (XEXP (in, 1)))
8274 tem = op0, op0 = op1, op1 = tem;
8276 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8277 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8279 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8283 /* If that failed, we must use a conservative two-insn sequence.
8285 Use a move to copy one operand into the reload register. Prefer
8286 to reload a constant, MEM or pseudo since the move patterns can
8287 handle an arbitrary operand. If OP1 is not a constant, MEM or
8288 pseudo and OP1 is not a valid operand for an add instruction, then
8291 After reloading one of the operands into the reload register, add
8292 the reload register to the output register.
8294 If there is another way to do this for a specific machine, a
8295 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8298 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8300 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8302 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8303 || (code != CODE_FOR_nothing
8304 && ! ((*insn_data[code].operand[2].predicate)
8305 (op1, insn_data[code].operand[2].mode))))
8306 tem = op0, op0 = op1, op1 = tem;
8308 gen_reload (out, op0, opnum, type);
8310 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8311 This fixes a problem on the 32K where the stack pointer cannot
8312 be used as an operand of an add insn. */
8314 if (rtx_equal_p (op0, op1))
8317 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8320 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8321 set_unique_reg_note (insn, REG_EQUIV, in);
8325 /* If that failed, copy the address register to the reload register.
8326 Then add the constant to the reload register. */
8328 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8329 gen_reload (out, op1, opnum, type);
8330 insn = emit_insn (gen_add2_insn (out, op0));
8331 set_unique_reg_note (insn, REG_EQUIV, in);
8334 #ifdef SECONDARY_MEMORY_NEEDED
8335 /* If we need a memory location to do the move, do it that way. */
8336 else if ((REG_P (in)
8337 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8338 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8340 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8341 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8342 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8343 REGNO_REG_CLASS (reg_or_subregno (out)),
8346 /* Get the memory to use and rewrite both registers to its mode. */
8347 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8349 if (GET_MODE (loc) != GET_MODE (out))
8350 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8352 if (GET_MODE (loc) != GET_MODE (in))
8353 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8355 gen_reload (loc, in, opnum, type);
8356 gen_reload (out, loc, opnum, type);
8359 else if (REG_P (out) && UNARY_P (in))
8366 op1 = find_replacement (&XEXP (in, 0));
8367 if (op1 != XEXP (in, 0))
8368 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8370 /* First, try a plain SET. */
8371 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8375 /* If that failed, move the inner operand to the reload
8376 register, and try the same unop with the inner expression
8377 replaced with the reload register. */
8379 if (GET_MODE (op1) != GET_MODE (out))
8380 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8384 gen_reload (out_moded, op1, opnum, type);
8387 = gen_rtx_SET (VOIDmode, out,
8388 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8390 insn = emit_insn_if_valid_for_reload (insn);
8393 set_unique_reg_note (insn, REG_EQUIV, in);
8397 fatal_insn ("Failure trying to reload:", set);
8399 /* If IN is a simple operand, use gen_move_insn. */
8400 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8402 tem = emit_insn (gen_move_insn (out, in));
8403 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8404 mark_jump_label (in, tem, 0);
8407 #ifdef HAVE_reload_load_address
8408 else if (HAVE_reload_load_address)
8409 emit_insn (gen_reload_load_address (out, in));
8412 /* Otherwise, just write (set OUT IN) and hope for the best. */
8414 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8416 /* Return the first insn emitted.
8417 We can not just return get_last_insn, because there may have
8418 been multiple instructions emitted. Also note that gen_move_insn may
8419 emit more than one insn itself, so we can not assume that there is one
8420 insn emitted per emit_insn_before call. */
8422 return last ? NEXT_INSN (last) : get_insns ();
8425 /* Delete a previously made output-reload whose result we now believe
8426 is not needed. First we double-check.
8428 INSN is the insn now being processed.
8429 LAST_RELOAD_REG is the hard register number for which we want to delete
8430 the last output reload.
8431 J is the reload-number that originally used REG. The caller has made
8432 certain that reload J doesn't use REG any longer for input.
8433 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8436 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8438 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8439 rtx reg = spill_reg_stored_to[last_reload_reg];
8442 int n_inherited = 0;
8446 /* It is possible that this reload has been only used to set another reload
8447 we eliminated earlier and thus deleted this instruction too. */
8448 if (INSN_DELETED_P (output_reload_insn))
8451 /* Get the raw pseudo-register referred to. */
8453 while (GET_CODE (reg) == SUBREG)
8454 reg = SUBREG_REG (reg);
8455 substed = reg_equiv_memory_loc[REGNO (reg)];
8457 /* This is unsafe if the operand occurs more often in the current
8458 insn than it is inherited. */
8459 for (k = n_reloads - 1; k >= 0; k--)
8461 rtx reg2 = rld[k].in;
8464 if (MEM_P (reg2) || reload_override_in[k])
8465 reg2 = rld[k].in_reg;
8467 if (rld[k].out && ! rld[k].out_reg)
8468 reg2 = XEXP (rld[k].in_reg, 0);
8470 while (GET_CODE (reg2) == SUBREG)
8471 reg2 = SUBREG_REG (reg2);
8472 if (rtx_equal_p (reg2, reg))
8474 if (reload_inherited[k] || reload_override_in[k] || k == j)
8480 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8481 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8482 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8485 n_occurrences += count_occurrences (PATTERN (insn),
8486 eliminate_regs (substed, VOIDmode,
8488 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8490 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8491 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8493 if (n_occurrences > n_inherited)
8496 /* If the pseudo-reg we are reloading is no longer referenced
8497 anywhere between the store into it and here,
8498 and we're within the same basic block, then the value can only
8499 pass through the reload reg and end up here.
8500 Otherwise, give up--return. */
8501 for (i1 = NEXT_INSN (output_reload_insn);
8502 i1 != insn; i1 = NEXT_INSN (i1))
8504 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8506 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8507 && reg_mentioned_p (reg, PATTERN (i1)))
8509 /* If this is USE in front of INSN, we only have to check that
8510 there are no more references than accounted for by inheritance. */
8511 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8513 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8514 i1 = NEXT_INSN (i1);
8516 if (n_occurrences <= n_inherited && i1 == insn)
8522 /* We will be deleting the insn. Remove the spill reg information. */
8523 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8525 spill_reg_store[last_reload_reg + k] = 0;
8526 spill_reg_stored_to[last_reload_reg + k] = 0;
8529 /* The caller has already checked that REG dies or is set in INSN.
8530 It has also checked that we are optimizing, and thus some
8531 inaccuracies in the debugging information are acceptable.
8532 So we could just delete output_reload_insn. But in some cases
8533 we can improve the debugging information without sacrificing
8534 optimization - maybe even improving the code: See if the pseudo
8535 reg has been completely replaced with reload regs. If so, delete
8536 the store insn and forget we had a stack slot for the pseudo. */
8537 if (rld[j].out != rld[j].in
8538 && REG_N_DEATHS (REGNO (reg)) == 1
8539 && REG_N_SETS (REGNO (reg)) == 1
8540 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8541 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8545 /* We know that it was used only between here and the beginning of
8546 the current basic block. (We also know that the last use before
8547 INSN was the output reload we are thinking of deleting, but never
8548 mind that.) Search that range; see if any ref remains. */
8549 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8551 rtx set = single_set (i2);
8553 /* Uses which just store in the pseudo don't count,
8554 since if they are the only uses, they are dead. */
8555 if (set != 0 && SET_DEST (set) == reg)
8560 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8561 && reg_mentioned_p (reg, PATTERN (i2)))
8563 /* Some other ref remains; just delete the output reload we
8565 delete_address_reloads (output_reload_insn, insn);
8566 delete_insn (output_reload_insn);
8571 /* Delete the now-dead stores into this pseudo. Note that this
8572 loop also takes care of deleting output_reload_insn. */
8573 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8575 rtx set = single_set (i2);
8577 if (set != 0 && SET_DEST (set) == reg)
8579 delete_address_reloads (i2, insn);
8587 /* For the debugging info, say the pseudo lives in this reload reg. */
8588 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8589 if (ira_conflicts_p)
8590 /* Inform IRA about the change. */
8591 ira_mark_allocation_change (REGNO (reg));
8592 alter_reg (REGNO (reg), -1, false);
8596 delete_address_reloads (output_reload_insn, insn);
8597 delete_insn (output_reload_insn);
8601 /* We are going to delete DEAD_INSN. Recursively delete loads of
8602 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8603 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8605 delete_address_reloads (rtx dead_insn, rtx current_insn)
8607 rtx set = single_set (dead_insn);
8608 rtx set2, dst, prev, next;
8611 rtx dst = SET_DEST (set);
8613 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8615 /* If we deleted the store from a reloaded post_{in,de}c expression,
8616 we can delete the matching adds. */
8617 prev = PREV_INSN (dead_insn);
8618 next = NEXT_INSN (dead_insn);
8619 if (! prev || ! next)
8621 set = single_set (next);
8622 set2 = single_set (prev);
8624 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8625 || !CONST_INT_P (XEXP (SET_SRC (set), 1))
8626 || !CONST_INT_P (XEXP (SET_SRC (set2), 1)))
8628 dst = SET_DEST (set);
8629 if (! rtx_equal_p (dst, SET_DEST (set2))
8630 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8631 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8632 || (INTVAL (XEXP (SET_SRC (set), 1))
8633 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8635 delete_related_insns (prev);
8636 delete_related_insns (next);
8639 /* Subfunction of delete_address_reloads: process registers found in X. */
8641 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8643 rtx prev, set, dst, i2;
8645 enum rtx_code code = GET_CODE (x);
8649 const char *fmt = GET_RTX_FORMAT (code);
8650 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8653 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8654 else if (fmt[i] == 'E')
8656 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8657 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8664 if (spill_reg_order[REGNO (x)] < 0)
8667 /* Scan backwards for the insn that sets x. This might be a way back due
8669 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8671 code = GET_CODE (prev);
8672 if (code == CODE_LABEL || code == JUMP_INSN)
8676 if (reg_set_p (x, PATTERN (prev)))
8678 if (reg_referenced_p (x, PATTERN (prev)))
8681 if (! prev || INSN_UID (prev) < reload_first_uid)
8683 /* Check that PREV only sets the reload register. */
8684 set = single_set (prev);
8687 dst = SET_DEST (set);
8689 || ! rtx_equal_p (dst, x))
8691 if (! reg_set_p (dst, PATTERN (dead_insn)))
8693 /* Check if DST was used in a later insn -
8694 it might have been inherited. */
8695 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8701 if (reg_referenced_p (dst, PATTERN (i2)))
8703 /* If there is a reference to the register in the current insn,
8704 it might be loaded in a non-inherited reload. If no other
8705 reload uses it, that means the register is set before
8707 if (i2 == current_insn)
8709 for (j = n_reloads - 1; j >= 0; j--)
8710 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8711 || reload_override_in[j] == dst)
8713 for (j = n_reloads - 1; j >= 0; j--)
8714 if (rld[j].in && rld[j].reg_rtx == dst)
8723 /* If DST is still live at CURRENT_INSN, check if it is used for
8724 any reload. Note that even if CURRENT_INSN sets DST, we still
8725 have to check the reloads. */
8726 if (i2 == current_insn)
8728 for (j = n_reloads - 1; j >= 0; j--)
8729 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8730 || reload_override_in[j] == dst)
8732 /* ??? We can't finish the loop here, because dst might be
8733 allocated to a pseudo in this block if no reload in this
8734 block needs any of the classes containing DST - see
8735 spill_hard_reg. There is no easy way to tell this, so we
8736 have to scan till the end of the basic block. */
8738 if (reg_set_p (dst, PATTERN (i2)))
8742 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8743 reg_reloaded_contents[REGNO (dst)] = -1;
8747 /* Output reload-insns to reload VALUE into RELOADREG.
8748 VALUE is an autoincrement or autodecrement RTX whose operand
8749 is a register or memory location;
8750 so reloading involves incrementing that location.
8751 IN is either identical to VALUE, or some cheaper place to reload from.
8753 INC_AMOUNT is the number to increment or decrement by (always positive).
8754 This cannot be deduced from VALUE.
8756 Return the instruction that stores into RELOADREG. */
8759 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8761 /* REG or MEM to be copied and incremented. */
8762 rtx incloc = find_replacement (&XEXP (value, 0));
8763 /* Nonzero if increment after copying. */
8764 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8765 || GET_CODE (value) == POST_MODIFY);
8771 rtx real_in = in == value ? incloc : in;
8773 /* No hard register is equivalent to this register after
8774 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8775 we could inc/dec that register as well (maybe even using it for
8776 the source), but I'm not sure it's worth worrying about. */
8778 reg_last_reload_reg[REGNO (incloc)] = 0;
8780 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8782 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8783 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8787 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8788 inc_amount = -inc_amount;
8790 inc = GEN_INT (inc_amount);
8793 /* If this is post-increment, first copy the location to the reload reg. */
8794 if (post && real_in != reloadreg)
8795 emit_insn (gen_move_insn (reloadreg, real_in));
8799 /* See if we can directly increment INCLOC. Use a method similar to
8800 that in gen_reload. */
8802 last = get_last_insn ();
8803 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8804 gen_rtx_PLUS (GET_MODE (incloc),
8807 code = recog_memoized (add_insn);
8810 extract_insn (add_insn);
8811 if (constrain_operands (1))
8813 /* If this is a pre-increment and we have incremented the value
8814 where it lives, copy the incremented value to RELOADREG to
8815 be used as an address. */
8818 emit_insn (gen_move_insn (reloadreg, incloc));
8823 delete_insns_since (last);
8826 /* If couldn't do the increment directly, must increment in RELOADREG.
8827 The way we do this depends on whether this is pre- or post-increment.
8828 For pre-increment, copy INCLOC to the reload register, increment it
8829 there, then save back. */
8833 if (in != reloadreg)
8834 emit_insn (gen_move_insn (reloadreg, real_in));
8835 emit_insn (gen_add2_insn (reloadreg, inc));
8836 store = emit_insn (gen_move_insn (incloc, reloadreg));
8841 Because this might be a jump insn or a compare, and because RELOADREG
8842 may not be available after the insn in an input reload, we must do
8843 the incrementation before the insn being reloaded for.
8845 We have already copied IN to RELOADREG. Increment the copy in
8846 RELOADREG, save that back, then decrement RELOADREG so it has
8847 the original value. */
8849 emit_insn (gen_add2_insn (reloadreg, inc));
8850 store = emit_insn (gen_move_insn (incloc, reloadreg));
8851 if (CONST_INT_P (inc))
8852 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8854 emit_insn (gen_sub2_insn (reloadreg, inc));
8862 add_auto_inc_notes (rtx insn, rtx x)
8864 enum rtx_code code = GET_CODE (x);
8868 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8870 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8874 /* Scan all the operand sub-expressions. */
8875 fmt = GET_RTX_FORMAT (code);
8876 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8879 add_auto_inc_notes (insn, XEXP (x, i));
8880 else if (fmt[i] == 'E')
8881 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8882 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8887 /* This is used by reload pass, that does emit some instructions after
8888 abnormal calls moving basic block end, but in fact it wants to emit
8889 them on the edge. Looks for abnormal call edges, find backward the
8890 proper call and fix the damage.
8892 Similar handle instructions throwing exceptions internally. */
8894 fixup_abnormal_edges (void)
8896 bool inserted = false;
8904 /* Look for cases we are interested in - calls or instructions causing
8906 FOR_EACH_EDGE (e, ei, bb->succs)
8908 if (e->flags & EDGE_ABNORMAL_CALL)
8910 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8911 == (EDGE_ABNORMAL | EDGE_EH))
8914 if (e && !CALL_P (BB_END (bb))
8915 && !can_throw_internal (BB_END (bb)))
8919 /* Get past the new insns generated. Allow notes, as the insns
8920 may be already deleted. */
8922 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8923 && !can_throw_internal (insn)
8924 && insn != BB_HEAD (bb))
8925 insn = PREV_INSN (insn);
8927 if (CALL_P (insn) || can_throw_internal (insn))
8931 stop = NEXT_INSN (BB_END (bb));
8933 insn = NEXT_INSN (insn);
8935 FOR_EACH_EDGE (e, ei, bb->succs)
8936 if (e->flags & EDGE_FALLTHRU)
8939 while (insn && insn != stop)
8941 next = NEXT_INSN (insn);
8946 /* Sometimes there's still the return value USE.
8947 If it's placed after a trapping call (i.e. that
8948 call is the last insn anyway), we have no fallthru
8949 edge. Simply delete this use and don't try to insert
8950 on the non-existent edge. */
8951 if (GET_CODE (PATTERN (insn)) != USE)
8953 /* We're not deleting it, we're moving it. */
8954 INSN_DELETED_P (insn) = 0;
8955 PREV_INSN (insn) = NULL_RTX;
8956 NEXT_INSN (insn) = NULL_RTX;
8958 insert_insn_on_edge (insn, e);
8962 else if (!BARRIER_P (insn))
8963 set_block_for_insn (insn, NULL);
8968 /* It may be that we don't find any such trapping insn. In this
8969 case we discovered quite late that the insn that had been
8970 marked as can_throw_internal in fact couldn't trap at all.
8971 So we should in fact delete the EH edges out of the block. */
8973 purge_dead_edges (bb);
8977 /* We've possibly turned single trapping insn into multiple ones. */
8978 if (flag_non_call_exceptions)
8981 blocks = sbitmap_alloc (last_basic_block);
8982 sbitmap_ones (blocks);
8983 find_many_sub_basic_blocks (blocks);
8984 sbitmap_free (blocks);
8988 commit_edge_insertions ();
8990 #ifdef ENABLE_CHECKING
8991 /* Verify that we didn't turn one trapping insn into many, and that
8992 we found and corrected all of the problems wrt fixups on the
8994 verify_flow_info ();
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