1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation,
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 2, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING. If not, write to the Free
20 Software Foundation, 51 Franklin Street, Fifth Floor, Boston, MA
25 #include "coretypes.h"
29 #include "hard-reg-set.h"
33 #include "insn-config.h"
39 #include "addresses.h"
40 #include "basic-block.h"
50 /* This file contains the reload pass of the compiler, which is
51 run after register allocation has been done. It checks that
52 each insn is valid (operands required to be in registers really
53 are in registers of the proper class) and fixes up invalid ones
54 by copying values temporarily into registers for the insns
57 The results of register allocation are described by the vector
58 reg_renumber; the insns still contain pseudo regs, but reg_renumber
59 can be used to find which hard reg, if any, a pseudo reg is in.
61 The technique we always use is to free up a few hard regs that are
62 called ``reload regs'', and for each place where a pseudo reg
63 must be in a hard reg, copy it temporarily into one of the reload regs.
65 Reload regs are allocated locally for every instruction that needs
66 reloads. When there are pseudos which are allocated to a register that
67 has been chosen as a reload reg, such pseudos must be ``spilled''.
68 This means that they go to other hard regs, or to stack slots if no other
69 available hard regs can be found. Spilling can invalidate more
70 insns, requiring additional need for reloads, so we must keep checking
71 until the process stabilizes.
73 For machines with different classes of registers, we must keep track
74 of the register class needed for each reload, and make sure that
75 we allocate enough reload registers of each class.
77 The file reload.c contains the code that checks one insn for
78 validity and reports the reloads that it needs. This file
79 is in charge of scanning the entire rtl code, accumulating the
80 reload needs, spilling, assigning reload registers to use for
81 fixing up each insn, and generating the new insns to copy values
82 into the reload registers. */
84 /* During reload_as_needed, element N contains a REG rtx for the hard reg
85 into which reg N has been reloaded (perhaps for a previous insn). */
86 static rtx *reg_last_reload_reg;
88 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
89 for an output reload that stores into reg N. */
90 static char *reg_has_output_reload;
92 /* Indicates which hard regs are reload-registers for an output reload
93 in the current insn. */
94 static HARD_REG_SET reg_is_output_reload;
96 /* Element N is the constant value to which pseudo reg N is equivalent,
97 or zero if pseudo reg N is not equivalent to a constant.
98 find_reloads looks at this in order to replace pseudo reg N
99 with the constant it stands for. */
100 rtx *reg_equiv_constant;
102 /* Element N is an invariant value to which pseudo reg N is equivalent.
103 eliminate_regs_in_insn uses this to replace pseudos in particular
105 rtx *reg_equiv_invariant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
114 collector can keep track of what is inside. */
115 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
117 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
118 This is used when the address is not valid as a memory address
119 (because its displacement is too big for the machine.) */
120 rtx *reg_equiv_address;
122 /* Element N is the memory slot to which pseudo reg N is equivalent,
123 or zero if pseudo reg N is not equivalent to a memory slot. */
126 /* Widest width in which each pseudo reg is referred to (via subreg). */
127 static unsigned int *reg_max_ref_width;
129 /* Element N is the list of insns that initialized reg N from its equivalent
130 constant or memory slot. */
132 int reg_equiv_init_size;
134 /* Vector to remember old contents of reg_renumber before spilling. */
135 static short *reg_old_renumber;
137 /* During reload_as_needed, element N contains the last pseudo regno reloaded
138 into hard register N. If that pseudo reg occupied more than one register,
139 reg_reloaded_contents points to that pseudo for each spill register in
140 use; all of these must remain set for an inheritance to occur. */
141 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
143 /* During reload_as_needed, element N contains the insn for which
144 hard register N was last used. Its contents are significant only
145 when reg_reloaded_valid is set for this register. */
146 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
148 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
149 static HARD_REG_SET reg_reloaded_valid;
150 /* Indicate if the register was dead at the end of the reload.
151 This is only valid if reg_reloaded_contents is set and valid. */
152 static HARD_REG_SET reg_reloaded_dead;
154 /* Indicate whether the register's current value is one that is not
155 safe to retain across a call, even for registers that are normally
157 static HARD_REG_SET reg_reloaded_call_part_clobbered;
159 /* Number of spill-regs so far; number of valid elements of spill_regs. */
162 /* In parallel with spill_regs, contains REG rtx's for those regs.
163 Holds the last rtx used for any given reg, or 0 if it has never
164 been used for spilling yet. This rtx is reused, provided it has
166 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
168 /* In parallel with spill_regs, contains nonzero for a spill reg
169 that was stored after the last time it was used.
170 The precise value is the insn generated to do the store. */
171 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
173 /* This is the register that was stored with spill_reg_store. This is a
174 copy of reload_out / reload_out_reg when the value was stored; if
175 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
176 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
178 /* This table is the inverse mapping of spill_regs:
179 indexed by hard reg number,
180 it contains the position of that reg in spill_regs,
181 or -1 for something that is not in spill_regs.
183 ?!? This is no longer accurate. */
184 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
186 /* This reg set indicates registers that can't be used as spill registers for
187 the currently processed insn. These are the hard registers which are live
188 during the insn, but not allocated to pseudos, as well as fixed
190 static HARD_REG_SET bad_spill_regs;
192 /* These are the hard registers that can't be used as spill register for any
193 insn. This includes registers used for user variables and registers that
194 we can't eliminate. A register that appears in this set also can't be used
195 to retry register allocation. */
196 static HARD_REG_SET bad_spill_regs_global;
198 /* Describes order of use of registers for reloading
199 of spilled pseudo-registers. `n_spills' is the number of
200 elements that are actually valid; new ones are added at the end.
202 Both spill_regs and spill_reg_order are used on two occasions:
203 once during find_reload_regs, where they keep track of the spill registers
204 for a single insn, but also during reload_as_needed where they show all
205 the registers ever used by reload. For the latter case, the information
206 is calculated during finish_spills. */
207 static short spill_regs[FIRST_PSEUDO_REGISTER];
209 /* This vector of reg sets indicates, for each pseudo, which hard registers
210 may not be used for retrying global allocation because the register was
211 formerly spilled from one of them. If we allowed reallocating a pseudo to
212 a register that it was already allocated to, reload might not
214 static HARD_REG_SET *pseudo_previous_regs;
216 /* This vector of reg sets indicates, for each pseudo, which hard
217 registers may not be used for retrying global allocation because they
218 are used as spill registers during one of the insns in which the
220 static HARD_REG_SET *pseudo_forbidden_regs;
222 /* All hard regs that have been used as spill registers for any insn are
223 marked in this set. */
224 static HARD_REG_SET used_spill_regs;
226 /* Index of last register assigned as a spill register. We allocate in
227 a round-robin fashion. */
228 static int last_spill_reg;
230 /* Nonzero if indirect addressing is supported on the machine; this means
231 that spilling (REG n) does not require reloading it into a register in
232 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
233 value indicates the level of indirect addressing supported, e.g., two
234 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
236 static char spill_indirect_levels;
238 /* Nonzero if indirect addressing is supported when the innermost MEM is
239 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
240 which these are valid is the same as spill_indirect_levels, above. */
241 char indirect_symref_ok;
243 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
244 char double_reg_address_ok;
246 /* Record the stack slot for each spilled hard register. */
247 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
249 /* Width allocated so far for that stack slot. */
250 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
252 /* Record which pseudos needed to be spilled. */
253 static regset_head spilled_pseudos;
255 /* Used for communication between order_regs_for_reload and count_pseudo.
256 Used to avoid counting one pseudo twice. */
257 static regset_head pseudos_counted;
259 /* First uid used by insns created by reload in this function.
260 Used in find_equiv_reg. */
261 int reload_first_uid;
263 /* Flag set by local-alloc or global-alloc if anything is live in
264 a call-clobbered reg across calls. */
265 int caller_save_needed;
267 /* Set to 1 while reload_as_needed is operating.
268 Required by some machines to handle any generated moves differently. */
269 int reload_in_progress = 0;
271 /* These arrays record the insn_code of insns that may be needed to
272 perform input and output reloads of special objects. They provide a
273 place to pass a scratch register. */
274 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
275 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
277 /* This obstack is used for allocation of rtl during register elimination.
278 The allocated storage can be freed once find_reloads has processed the
280 static struct obstack reload_obstack;
282 /* Points to the beginning of the reload_obstack. All insn_chain structures
283 are allocated first. */
284 static char *reload_startobj;
286 /* The point after all insn_chain structures. Used to quickly deallocate
287 memory allocated in copy_reloads during calculate_needs_all_insns. */
288 static char *reload_firstobj;
290 /* This points before all local rtl generated by register elimination.
291 Used to quickly free all memory after processing one insn. */
292 static char *reload_insn_firstobj;
294 /* List of insn_chain instructions, one for every insn that reload needs to
296 struct insn_chain *reload_insn_chain;
298 /* List of all insns needing reloads. */
299 static struct insn_chain *insns_need_reload;
301 /* This structure is used to record information about register eliminations.
302 Each array entry describes one possible way of eliminating a register
303 in favor of another. If there is more than one way of eliminating a
304 particular register, the most preferred should be specified first. */
308 int from; /* Register number to be eliminated. */
309 int to; /* Register number used as replacement. */
310 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
311 int can_eliminate; /* Nonzero if this elimination can be done. */
312 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
313 insns made by reload. */
314 HOST_WIDE_INT offset; /* Current offset between the two regs. */
315 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
316 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
317 rtx from_rtx; /* REG rtx for the register to be eliminated.
318 We cannot simply compare the number since
319 we might then spuriously replace a hard
320 register corresponding to a pseudo
321 assigned to the reg to be eliminated. */
322 rtx to_rtx; /* REG rtx for the replacement. */
325 static struct elim_table *reg_eliminate = 0;
327 /* This is an intermediate structure to initialize the table. It has
328 exactly the members provided by ELIMINABLE_REGS. */
329 static const struct elim_table_1
333 } reg_eliminate_1[] =
335 /* If a set of eliminable registers was specified, define the table from it.
336 Otherwise, default to the normal case of the frame pointer being
337 replaced by the stack pointer. */
339 #ifdef ELIMINABLE_REGS
342 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
345 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
347 /* Record the number of pending eliminations that have an offset not equal
348 to their initial offset. If nonzero, we use a new copy of each
349 replacement result in any insns encountered. */
350 int num_not_at_initial_offset;
352 /* Count the number of registers that we may be able to eliminate. */
353 static int num_eliminable;
354 /* And the number of registers that are equivalent to a constant that
355 can be eliminated to frame_pointer / arg_pointer + constant. */
356 static int num_eliminable_invariants;
358 /* For each label, we record the offset of each elimination. If we reach
359 a label by more than one path and an offset differs, we cannot do the
360 elimination. This information is indexed by the difference of the
361 number of the label and the first label number. We can't offset the
362 pointer itself as this can cause problems on machines with segmented
363 memory. The first table is an array of flags that records whether we
364 have yet encountered a label and the second table is an array of arrays,
365 one entry in the latter array for each elimination. */
367 static int first_label_num;
368 static char *offsets_known_at;
369 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
371 /* Number of labels in the current function. */
373 static int num_labels;
375 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
376 static void maybe_fix_stack_asms (void);
377 static void copy_reloads (struct insn_chain *);
378 static void calculate_needs_all_insns (int);
379 static int find_reg (struct insn_chain *, int);
380 static void find_reload_regs (struct insn_chain *);
381 static void select_reload_regs (void);
382 static void delete_caller_save_insns (void);
384 static void spill_failure (rtx, enum reg_class);
385 static void count_spilled_pseudo (int, int, int);
386 static void delete_dead_insn (rtx);
387 static void alter_reg (int, int);
388 static void set_label_offsets (rtx, rtx, int);
389 static void check_eliminable_occurrences (rtx);
390 static void elimination_effects (rtx, enum machine_mode);
391 static int eliminate_regs_in_insn (rtx, int);
392 static void update_eliminable_offsets (void);
393 static void mark_not_eliminable (rtx, rtx, void *);
394 static void set_initial_elim_offsets (void);
395 static bool verify_initial_elim_offsets (void);
396 static void set_initial_label_offsets (void);
397 static void set_offsets_for_label (rtx);
398 static void init_elim_table (void);
399 static void update_eliminables (HARD_REG_SET *);
400 static void spill_hard_reg (unsigned int, int);
401 static int finish_spills (int);
402 static void scan_paradoxical_subregs (rtx);
403 static void count_pseudo (int);
404 static void order_regs_for_reload (struct insn_chain *);
405 static void reload_as_needed (int);
406 static void forget_old_reloads_1 (rtx, rtx, void *);
407 static int reload_reg_class_lower (const void *, const void *);
408 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
410 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
412 static int reload_reg_free_p (unsigned int, int, enum reload_type);
413 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
415 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
417 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
418 static int allocate_reload_reg (struct insn_chain *, int, int);
419 static int conflicts_with_override (rtx);
420 static void failed_reload (rtx, int);
421 static int set_reload_reg (int, int);
422 static void choose_reload_regs_init (struct insn_chain *, rtx *);
423 static void choose_reload_regs (struct insn_chain *);
424 static void merge_assigned_reloads (rtx);
425 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
427 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
429 static void do_input_reload (struct insn_chain *, struct reload *, int);
430 static void do_output_reload (struct insn_chain *, struct reload *, int);
431 static bool inherit_piecemeal_p (int, int);
432 static void emit_reload_insns (struct insn_chain *);
433 static void delete_output_reload (rtx, int, int);
434 static void delete_address_reloads (rtx, rtx);
435 static void delete_address_reloads_1 (rtx, rtx, rtx);
436 static rtx inc_for_reload (rtx, rtx, rtx, int);
438 static void add_auto_inc_notes (rtx, rtx);
440 static void copy_eh_notes (rtx, rtx);
441 static int reloads_conflict (int, int);
442 static rtx gen_reload (rtx, rtx, int, enum reload_type);
443 static rtx emit_insn_if_valid_for_reload (rtx);
445 /* Initialize the reload pass once per compilation. */
452 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
453 Set spill_indirect_levels to the number of levels such addressing is
454 permitted, zero if it is not permitted at all. */
457 = gen_rtx_MEM (Pmode,
460 LAST_VIRTUAL_REGISTER + 1),
462 spill_indirect_levels = 0;
464 while (memory_address_p (QImode, tem))
466 spill_indirect_levels++;
467 tem = gen_rtx_MEM (Pmode, tem);
470 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
472 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
473 indirect_symref_ok = memory_address_p (QImode, tem);
475 /* See if reg+reg is a valid (and offsettable) address. */
477 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
479 tem = gen_rtx_PLUS (Pmode,
480 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
481 gen_rtx_REG (Pmode, i));
483 /* This way, we make sure that reg+reg is an offsettable address. */
484 tem = plus_constant (tem, 4);
486 if (memory_address_p (QImode, tem))
488 double_reg_address_ok = 1;
493 /* Initialize obstack for our rtl allocation. */
494 gcc_obstack_init (&reload_obstack);
495 reload_startobj = obstack_alloc (&reload_obstack, 0);
497 INIT_REG_SET (&spilled_pseudos);
498 INIT_REG_SET (&pseudos_counted);
501 /* List of insn chains that are currently unused. */
502 static struct insn_chain *unused_insn_chains = 0;
504 /* Allocate an empty insn_chain structure. */
506 new_insn_chain (void)
508 struct insn_chain *c;
510 if (unused_insn_chains == 0)
512 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
513 INIT_REG_SET (&c->live_throughout);
514 INIT_REG_SET (&c->dead_or_set);
518 c = unused_insn_chains;
519 unused_insn_chains = c->next;
521 c->is_caller_save_insn = 0;
522 c->need_operand_change = 0;
528 /* Small utility function to set all regs in hard reg set TO which are
529 allocated to pseudos in regset FROM. */
532 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
535 reg_set_iterator rsi;
537 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
539 int r = reg_renumber[regno];
544 /* reload_combine uses the information from
545 BASIC_BLOCK->global_live_at_start, which might still
546 contain registers that have not actually been allocated
547 since they have an equivalence. */
548 gcc_assert (reload_completed);
552 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (regno)];
554 SET_HARD_REG_BIT (*to, r + nregs);
559 /* Replace all pseudos found in LOC with their corresponding
563 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
576 unsigned int regno = REGNO (x);
578 if (regno < FIRST_PSEUDO_REGISTER)
581 x = eliminate_regs (x, mem_mode, usage);
585 replace_pseudos_in (loc, mem_mode, usage);
589 if (reg_equiv_constant[regno])
590 *loc = reg_equiv_constant[regno];
591 else if (reg_equiv_mem[regno])
592 *loc = reg_equiv_mem[regno];
593 else if (reg_equiv_address[regno])
594 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
597 gcc_assert (!REG_P (regno_reg_rtx[regno])
598 || REGNO (regno_reg_rtx[regno]) != regno);
599 *loc = regno_reg_rtx[regno];
604 else if (code == MEM)
606 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
610 /* Process each of our operands recursively. */
611 fmt = GET_RTX_FORMAT (code);
612 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
614 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
615 else if (*fmt == 'E')
616 for (j = 0; j < XVECLEN (x, i); j++)
617 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
621 /* Global variables used by reload and its subroutines. */
623 /* Set during calculate_needs if an insn needs register elimination. */
624 static int something_needs_elimination;
625 /* Set during calculate_needs if an insn needs an operand changed. */
626 static int something_needs_operands_changed;
628 /* Nonzero means we couldn't get enough spill regs. */
631 /* Main entry point for the reload pass.
633 FIRST is the first insn of the function being compiled.
635 GLOBAL nonzero means we were called from global_alloc
636 and should attempt to reallocate any pseudoregs that we
637 displace from hard regs we will use for reloads.
638 If GLOBAL is zero, we do not have enough information to do that,
639 so any pseudo reg that is spilled must go to the stack.
641 Return value is nonzero if reload failed
642 and we must not do any more for this function. */
645 reload (rtx first, int global)
649 struct elim_table *ep;
652 /* Make sure even insns with volatile mem refs are recognizable. */
657 reload_firstobj = obstack_alloc (&reload_obstack, 0);
659 /* Make sure that the last insn in the chain
660 is not something that needs reloading. */
661 emit_note (NOTE_INSN_DELETED);
663 /* Enable find_equiv_reg to distinguish insns made by reload. */
664 reload_first_uid = get_max_uid ();
666 #ifdef SECONDARY_MEMORY_NEEDED
667 /* Initialize the secondary memory table. */
668 clear_secondary_mem ();
671 /* We don't have a stack slot for any spill reg yet. */
672 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
673 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
675 /* Initialize the save area information for caller-save, in case some
679 /* Compute which hard registers are now in use
680 as homes for pseudo registers.
681 This is done here rather than (eg) in global_alloc
682 because this point is reached even if not optimizing. */
683 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
686 /* A function that receives a nonlocal goto must save all call-saved
688 if (current_function_has_nonlocal_label)
689 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
690 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
691 regs_ever_live[i] = 1;
693 /* Find all the pseudo registers that didn't get hard regs
694 but do have known equivalent constants or memory slots.
695 These include parameters (known equivalent to parameter slots)
696 and cse'd or loop-moved constant memory addresses.
698 Record constant equivalents in reg_equiv_constant
699 so they will be substituted by find_reloads.
700 Record memory equivalents in reg_mem_equiv so they can
701 be substituted eventually by altering the REG-rtx's. */
703 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
704 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
705 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
706 reg_equiv_address = XCNEWVEC (rtx, max_regno);
707 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
708 reg_old_renumber = XCNEWVEC (short, max_regno);
709 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
710 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
711 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
713 CLEAR_HARD_REG_SET (bad_spill_regs_global);
715 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
716 to. Also find all paradoxical subregs and find largest such for
719 num_eliminable_invariants = 0;
720 for (insn = first; insn; insn = NEXT_INSN (insn))
722 rtx set = single_set (insn);
724 /* We may introduce USEs that we want to remove at the end, so
725 we'll mark them with QImode. Make sure there are no
726 previously-marked insns left by say regmove. */
727 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
728 && GET_MODE (insn) != VOIDmode)
729 PUT_MODE (insn, VOIDmode);
732 scan_paradoxical_subregs (PATTERN (insn));
734 if (set != 0 && REG_P (SET_DEST (set)))
736 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
742 i = REGNO (SET_DEST (set));
745 if (i <= LAST_VIRTUAL_REGISTER)
748 if (! function_invariant_p (x)
750 /* A function invariant is often CONSTANT_P but may
751 include a register. We promise to only pass
752 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
754 && LEGITIMATE_PIC_OPERAND_P (x)))
756 /* It can happen that a REG_EQUIV note contains a MEM
757 that is not a legitimate memory operand. As later
758 stages of reload assume that all addresses found
759 in the reg_equiv_* arrays were originally legitimate,
760 we ignore such REG_EQUIV notes. */
761 if (memory_operand (x, VOIDmode))
763 /* Always unshare the equivalence, so we can
764 substitute into this insn without touching the
766 reg_equiv_memory_loc[i] = copy_rtx (x);
768 else if (function_invariant_p (x))
770 if (GET_CODE (x) == PLUS)
772 /* This is PLUS of frame pointer and a constant,
773 and might be shared. Unshare it. */
774 reg_equiv_invariant[i] = copy_rtx (x);
775 num_eliminable_invariants++;
777 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
779 reg_equiv_invariant[i] = x;
780 num_eliminable_invariants++;
782 else if (LEGITIMATE_CONSTANT_P (x))
783 reg_equiv_constant[i] = x;
786 reg_equiv_memory_loc[i]
787 = force_const_mem (GET_MODE (SET_DEST (set)), x);
788 if (! reg_equiv_memory_loc[i])
789 reg_equiv_init[i] = NULL_RTX;
794 reg_equiv_init[i] = NULL_RTX;
799 reg_equiv_init[i] = NULL_RTX;
804 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
805 if (reg_equiv_init[i])
807 fprintf (dump_file, "init_insns for %u: ", i);
808 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
809 fprintf (dump_file, "\n");
814 first_label_num = get_first_label_num ();
815 num_labels = max_label_num () - first_label_num;
817 /* Allocate the tables used to store offset information at labels. */
818 /* We used to use alloca here, but the size of what it would try to
819 allocate would occasionally cause it to exceed the stack limit and
820 cause a core dump. */
821 offsets_known_at = XNEWVEC (char, num_labels);
822 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
824 /* Alter each pseudo-reg rtx to contain its hard reg number.
825 Assign stack slots to the pseudos that lack hard regs or equivalents.
826 Do not touch virtual registers. */
828 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
831 /* If we have some registers we think can be eliminated, scan all insns to
832 see if there is an insn that sets one of these registers to something
833 other than itself plus a constant. If so, the register cannot be
834 eliminated. Doing this scan here eliminates an extra pass through the
835 main reload loop in the most common case where register elimination
837 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
839 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
841 maybe_fix_stack_asms ();
843 insns_need_reload = 0;
844 something_needs_elimination = 0;
846 /* Initialize to -1, which means take the first spill register. */
849 /* Spill any hard regs that we know we can't eliminate. */
850 CLEAR_HARD_REG_SET (used_spill_regs);
851 /* There can be multiple ways to eliminate a register;
852 they should be listed adjacently.
853 Elimination for any register fails only if all possible ways fail. */
854 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
857 int can_eliminate = 0;
860 can_eliminate |= ep->can_eliminate;
863 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
865 spill_hard_reg (from, 1);
868 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
869 if (frame_pointer_needed)
870 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
872 finish_spills (global);
874 /* From now on, we may need to generate moves differently. We may also
875 allow modifications of insns which cause them to not be recognized.
876 Any such modifications will be cleaned up during reload itself. */
877 reload_in_progress = 1;
879 /* This loop scans the entire function each go-round
880 and repeats until one repetition spills no additional hard regs. */
883 int something_changed;
886 HOST_WIDE_INT starting_frame_size;
888 /* Round size of stack frame to stack_alignment_needed. This must be done
889 here because the stack size may be a part of the offset computation
890 for register elimination, and there might have been new stack slots
891 created in the last iteration of this loop. */
892 if (cfun->stack_alignment_needed)
893 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
895 starting_frame_size = get_frame_size ();
897 set_initial_elim_offsets ();
898 set_initial_label_offsets ();
900 /* For each pseudo register that has an equivalent location defined,
901 try to eliminate any eliminable registers (such as the frame pointer)
902 assuming initial offsets for the replacement register, which
905 If the resulting location is directly addressable, substitute
906 the MEM we just got directly for the old REG.
908 If it is not addressable but is a constant or the sum of a hard reg
909 and constant, it is probably not addressable because the constant is
910 out of range, in that case record the address; we will generate
911 hairy code to compute the address in a register each time it is
912 needed. Similarly if it is a hard register, but one that is not
913 valid as an address register.
915 If the location is not addressable, but does not have one of the
916 above forms, assign a stack slot. We have to do this to avoid the
917 potential of producing lots of reloads if, e.g., a location involves
918 a pseudo that didn't get a hard register and has an equivalent memory
919 location that also involves a pseudo that didn't get a hard register.
921 Perhaps at some point we will improve reload_when_needed handling
922 so this problem goes away. But that's very hairy. */
924 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
925 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
927 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
929 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
931 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
932 else if (CONSTANT_P (XEXP (x, 0))
933 || (REG_P (XEXP (x, 0))
934 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
935 || (GET_CODE (XEXP (x, 0)) == PLUS
936 && REG_P (XEXP (XEXP (x, 0), 0))
937 && (REGNO (XEXP (XEXP (x, 0), 0))
938 < FIRST_PSEUDO_REGISTER)
939 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
940 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
943 /* Make a new stack slot. Then indicate that something
944 changed so we go back and recompute offsets for
945 eliminable registers because the allocation of memory
946 below might change some offset. reg_equiv_{mem,address}
947 will be set up for this pseudo on the next pass around
949 reg_equiv_memory_loc[i] = 0;
950 reg_equiv_init[i] = 0;
955 if (caller_save_needed)
958 /* If we allocated another stack slot, redo elimination bookkeeping. */
959 if (starting_frame_size != get_frame_size ())
962 if (caller_save_needed)
964 save_call_clobbered_regs ();
965 /* That might have allocated new insn_chain structures. */
966 reload_firstobj = obstack_alloc (&reload_obstack, 0);
969 calculate_needs_all_insns (global);
971 CLEAR_REG_SET (&spilled_pseudos);
974 something_changed = 0;
976 /* If we allocated any new memory locations, make another pass
977 since it might have changed elimination offsets. */
978 if (starting_frame_size != get_frame_size ())
979 something_changed = 1;
981 /* Even if the frame size remained the same, we might still have
982 changed elimination offsets, e.g. if find_reloads called
983 force_const_mem requiring the back end to allocate a constant
984 pool base register that needs to be saved on the stack. */
985 else if (!verify_initial_elim_offsets ())
986 something_changed = 1;
989 HARD_REG_SET to_spill;
990 CLEAR_HARD_REG_SET (to_spill);
991 update_eliminables (&to_spill);
992 AND_COMPL_HARD_REG_SET(used_spill_regs, to_spill);
994 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
995 if (TEST_HARD_REG_BIT (to_spill, i))
997 spill_hard_reg (i, 1);
1000 /* Regardless of the state of spills, if we previously had
1001 a register that we thought we could eliminate, but now can
1002 not eliminate, we must run another pass.
1004 Consider pseudos which have an entry in reg_equiv_* which
1005 reference an eliminable register. We must make another pass
1006 to update reg_equiv_* so that we do not substitute in the
1007 old value from when we thought the elimination could be
1009 something_changed = 1;
1013 select_reload_regs ();
1017 if (insns_need_reload != 0 || did_spill)
1018 something_changed |= finish_spills (global);
1020 if (! something_changed)
1023 if (caller_save_needed)
1024 delete_caller_save_insns ();
1026 obstack_free (&reload_obstack, reload_firstobj);
1029 /* If global-alloc was run, notify it of any register eliminations we have
1032 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1033 if (ep->can_eliminate)
1034 mark_elimination (ep->from, ep->to);
1036 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1037 If that insn didn't set the register (i.e., it copied the register to
1038 memory), just delete that insn instead of the equivalencing insn plus
1039 anything now dead. If we call delete_dead_insn on that insn, we may
1040 delete the insn that actually sets the register if the register dies
1041 there and that is incorrect. */
1043 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1045 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1048 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1050 rtx equiv_insn = XEXP (list, 0);
1052 /* If we already deleted the insn or if it may trap, we can't
1053 delete it. The latter case shouldn't happen, but can
1054 if an insn has a variable address, gets a REG_EH_REGION
1055 note added to it, and then gets converted into a load
1056 from a constant address. */
1057 if (NOTE_P (equiv_insn)
1058 || can_throw_internal (equiv_insn))
1060 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1061 delete_dead_insn (equiv_insn);
1063 SET_INSN_DELETED (equiv_insn);
1068 /* Use the reload registers where necessary
1069 by generating move instructions to move the must-be-register
1070 values into or out of the reload registers. */
1072 if (insns_need_reload != 0 || something_needs_elimination
1073 || something_needs_operands_changed)
1075 HOST_WIDE_INT old_frame_size = get_frame_size ();
1077 reload_as_needed (global);
1079 gcc_assert (old_frame_size == get_frame_size ());
1081 gcc_assert (verify_initial_elim_offsets ());
1084 /* If we were able to eliminate the frame pointer, show that it is no
1085 longer live at the start of any basic block. If it ls live by
1086 virtue of being in a pseudo, that pseudo will be marked live
1087 and hence the frame pointer will be known to be live via that
1090 if (! frame_pointer_needed)
1092 CLEAR_REGNO_REG_SET (bb->il.rtl->global_live_at_start,
1093 HARD_FRAME_POINTER_REGNUM);
1095 /* Come here (with failure set nonzero) if we can't get enough spill
1099 CLEAR_REG_SET (&spilled_pseudos);
1100 reload_in_progress = 0;
1102 /* Now eliminate all pseudo regs by modifying them into
1103 their equivalent memory references.
1104 The REG-rtx's for the pseudos are modified in place,
1105 so all insns that used to refer to them now refer to memory.
1107 For a reg that has a reg_equiv_address, all those insns
1108 were changed by reloading so that no insns refer to it any longer;
1109 but the DECL_RTL of a variable decl may refer to it,
1110 and if so this causes the debugging info to mention the variable. */
1112 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1116 if (reg_equiv_mem[i])
1117 addr = XEXP (reg_equiv_mem[i], 0);
1119 if (reg_equiv_address[i])
1120 addr = reg_equiv_address[i];
1124 if (reg_renumber[i] < 0)
1126 rtx reg = regno_reg_rtx[i];
1128 REG_USERVAR_P (reg) = 0;
1129 PUT_CODE (reg, MEM);
1130 XEXP (reg, 0) = addr;
1131 if (reg_equiv_memory_loc[i])
1132 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1135 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1136 MEM_ATTRS (reg) = 0;
1138 MEM_NOTRAP_P (reg) = 1;
1140 else if (reg_equiv_mem[i])
1141 XEXP (reg_equiv_mem[i], 0) = addr;
1145 /* We must set reload_completed now since the cleanup_subreg_operands call
1146 below will re-recognize each insn and reload may have generated insns
1147 which are only valid during and after reload. */
1148 reload_completed = 1;
1150 /* Make a pass over all the insns and delete all USEs which we inserted
1151 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1152 notes. Delete all CLOBBER insns, except those that refer to the return
1153 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1154 from misarranging variable-array code, and simplify (subreg (reg))
1155 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1156 are no longer useful or accurate. Strip and regenerate REG_INC notes
1157 that may have been moved around. */
1159 for (insn = first; insn; insn = NEXT_INSN (insn))
1165 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1166 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1168 if ((GET_CODE (PATTERN (insn)) == USE
1169 /* We mark with QImode USEs introduced by reload itself. */
1170 && (GET_MODE (insn) == QImode
1171 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1172 || (GET_CODE (PATTERN (insn)) == CLOBBER
1173 && (!MEM_P (XEXP (PATTERN (insn), 0))
1174 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1175 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1176 && XEXP (XEXP (PATTERN (insn), 0), 0)
1177 != stack_pointer_rtx))
1178 && (!REG_P (XEXP (PATTERN (insn), 0))
1179 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1185 /* Some CLOBBERs may survive until here and still reference unassigned
1186 pseudos with const equivalent, which may in turn cause ICE in later
1187 passes if the reference remains in place. */
1188 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1189 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1190 VOIDmode, PATTERN (insn));
1192 /* Discard obvious no-ops, even without -O. This optimization
1193 is fast and doesn't interfere with debugging. */
1194 if (NONJUMP_INSN_P (insn)
1195 && GET_CODE (PATTERN (insn)) == SET
1196 && REG_P (SET_SRC (PATTERN (insn)))
1197 && REG_P (SET_DEST (PATTERN (insn)))
1198 && (REGNO (SET_SRC (PATTERN (insn)))
1199 == REGNO (SET_DEST (PATTERN (insn)))))
1205 pnote = ®_NOTES (insn);
1208 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1209 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1210 || REG_NOTE_KIND (*pnote) == REG_INC
1211 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1212 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1213 *pnote = XEXP (*pnote, 1);
1215 pnote = &XEXP (*pnote, 1);
1219 add_auto_inc_notes (insn, PATTERN (insn));
1222 /* And simplify (subreg (reg)) if it appears as an operand. */
1223 cleanup_subreg_operands (insn);
1226 /* If we are doing stack checking, give a warning if this function's
1227 frame size is larger than we expect. */
1228 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1230 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1231 static int verbose_warned = 0;
1233 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1234 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1235 size += UNITS_PER_WORD;
1237 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1239 warning (0, "frame size too large for reliable stack checking");
1240 if (! verbose_warned)
1242 warning (0, "try reducing the number of local variables");
1248 /* Indicate that we no longer have known memory locations or constants. */
1249 if (reg_equiv_constant)
1250 free (reg_equiv_constant);
1251 if (reg_equiv_invariant)
1252 free (reg_equiv_invariant);
1253 reg_equiv_constant = 0;
1254 reg_equiv_invariant = 0;
1255 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1256 reg_equiv_memory_loc = 0;
1258 if (offsets_known_at)
1259 free (offsets_known_at);
1263 free (reg_equiv_mem);
1265 free (reg_equiv_address);
1266 free (reg_max_ref_width);
1267 free (reg_old_renumber);
1268 free (pseudo_previous_regs);
1269 free (pseudo_forbidden_regs);
1271 CLEAR_HARD_REG_SET (used_spill_regs);
1272 for (i = 0; i < n_spills; i++)
1273 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1275 /* Free all the insn_chain structures at once. */
1276 obstack_free (&reload_obstack, reload_startobj);
1277 unused_insn_chains = 0;
1278 fixup_abnormal_edges ();
1280 /* Replacing pseudos with their memory equivalents might have
1281 created shared rtx. Subsequent passes would get confused
1282 by this, so unshare everything here. */
1283 unshare_all_rtl_again (first);
1285 #ifdef STACK_BOUNDARY
1286 /* init_emit has set the alignment of the hard frame pointer
1287 to STACK_BOUNDARY. It is very likely no longer valid if
1288 the hard frame pointer was used for register allocation. */
1289 if (!frame_pointer_needed)
1290 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1296 /* Yet another special case. Unfortunately, reg-stack forces people to
1297 write incorrect clobbers in asm statements. These clobbers must not
1298 cause the register to appear in bad_spill_regs, otherwise we'll call
1299 fatal_insn later. We clear the corresponding regnos in the live
1300 register sets to avoid this.
1301 The whole thing is rather sick, I'm afraid. */
1304 maybe_fix_stack_asms (void)
1307 const char *constraints[MAX_RECOG_OPERANDS];
1308 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1309 struct insn_chain *chain;
1311 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1314 HARD_REG_SET clobbered, allowed;
1317 if (! INSN_P (chain->insn)
1318 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1320 pat = PATTERN (chain->insn);
1321 if (GET_CODE (pat) != PARALLEL)
1324 CLEAR_HARD_REG_SET (clobbered);
1325 CLEAR_HARD_REG_SET (allowed);
1327 /* First, make a mask of all stack regs that are clobbered. */
1328 for (i = 0; i < XVECLEN (pat, 0); i++)
1330 rtx t = XVECEXP (pat, 0, i);
1331 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1332 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1335 /* Get the operand values and constraints out of the insn. */
1336 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1337 constraints, operand_mode);
1339 /* For every operand, see what registers are allowed. */
1340 for (i = 0; i < noperands; i++)
1342 const char *p = constraints[i];
1343 /* For every alternative, we compute the class of registers allowed
1344 for reloading in CLS, and merge its contents into the reg set
1346 int cls = (int) NO_REGS;
1352 if (c == '\0' || c == ',' || c == '#')
1354 /* End of one alternative - mark the regs in the current
1355 class, and reset the class. */
1356 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1362 } while (c != '\0' && c != ',');
1370 case '=': case '+': case '*': case '%': case '?': case '!':
1371 case '0': case '1': case '2': case '3': case '4': case 'm':
1372 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1373 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1374 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1379 cls = (int) reg_class_subunion[cls]
1380 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1385 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1389 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1390 cls = (int) reg_class_subunion[cls]
1391 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1393 cls = (int) reg_class_subunion[cls]
1394 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1396 p += CONSTRAINT_LEN (c, p);
1399 /* Those of the registers which are clobbered, but allowed by the
1400 constraints, must be usable as reload registers. So clear them
1401 out of the life information. */
1402 AND_HARD_REG_SET (allowed, clobbered);
1403 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1404 if (TEST_HARD_REG_BIT (allowed, i))
1406 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1407 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1414 /* Copy the global variables n_reloads and rld into the corresponding elts
1417 copy_reloads (struct insn_chain *chain)
1419 chain->n_reloads = n_reloads;
1420 chain->rld = obstack_alloc (&reload_obstack,
1421 n_reloads * sizeof (struct reload));
1422 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1423 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1426 /* Walk the chain of insns, and determine for each whether it needs reloads
1427 and/or eliminations. Build the corresponding insns_need_reload list, and
1428 set something_needs_elimination as appropriate. */
1430 calculate_needs_all_insns (int global)
1432 struct insn_chain **pprev_reload = &insns_need_reload;
1433 struct insn_chain *chain, *next = 0;
1435 something_needs_elimination = 0;
1437 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1438 for (chain = reload_insn_chain; chain != 0; chain = next)
1440 rtx insn = chain->insn;
1444 /* Clear out the shortcuts. */
1445 chain->n_reloads = 0;
1446 chain->need_elim = 0;
1447 chain->need_reload = 0;
1448 chain->need_operand_change = 0;
1450 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1451 include REG_LABEL), we need to see what effects this has on the
1452 known offsets at labels. */
1454 if (LABEL_P (insn) || JUMP_P (insn)
1455 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1456 set_label_offsets (insn, insn, 0);
1460 rtx old_body = PATTERN (insn);
1461 int old_code = INSN_CODE (insn);
1462 rtx old_notes = REG_NOTES (insn);
1463 int did_elimination = 0;
1464 int operands_changed = 0;
1465 rtx set = single_set (insn);
1467 /* Skip insns that only set an equivalence. */
1468 if (set && REG_P (SET_DEST (set))
1469 && reg_renumber[REGNO (SET_DEST (set))] < 0
1470 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1471 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1472 && reg_equiv_init[REGNO (SET_DEST (set))])
1475 /* If needed, eliminate any eliminable registers. */
1476 if (num_eliminable || num_eliminable_invariants)
1477 did_elimination = eliminate_regs_in_insn (insn, 0);
1479 /* Analyze the instruction. */
1480 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1481 global, spill_reg_order);
1483 /* If a no-op set needs more than one reload, this is likely
1484 to be something that needs input address reloads. We
1485 can't get rid of this cleanly later, and it is of no use
1486 anyway, so discard it now.
1487 We only do this when expensive_optimizations is enabled,
1488 since this complements reload inheritance / output
1489 reload deletion, and it can make debugging harder. */
1490 if (flag_expensive_optimizations && n_reloads > 1)
1492 rtx set = single_set (insn);
1494 && SET_SRC (set) == SET_DEST (set)
1495 && REG_P (SET_SRC (set))
1496 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1499 /* Delete it from the reload chain. */
1501 chain->prev->next = next;
1503 reload_insn_chain = next;
1505 next->prev = chain->prev;
1506 chain->next = unused_insn_chains;
1507 unused_insn_chains = chain;
1512 update_eliminable_offsets ();
1514 /* Remember for later shortcuts which insns had any reloads or
1515 register eliminations. */
1516 chain->need_elim = did_elimination;
1517 chain->need_reload = n_reloads > 0;
1518 chain->need_operand_change = operands_changed;
1520 /* Discard any register replacements done. */
1521 if (did_elimination)
1523 obstack_free (&reload_obstack, reload_insn_firstobj);
1524 PATTERN (insn) = old_body;
1525 INSN_CODE (insn) = old_code;
1526 REG_NOTES (insn) = old_notes;
1527 something_needs_elimination = 1;
1530 something_needs_operands_changed |= operands_changed;
1534 copy_reloads (chain);
1535 *pprev_reload = chain;
1536 pprev_reload = &chain->next_need_reload;
1543 /* Comparison function for qsort to decide which of two reloads
1544 should be handled first. *P1 and *P2 are the reload numbers. */
1547 reload_reg_class_lower (const void *r1p, const void *r2p)
1549 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1552 /* Consider required reloads before optional ones. */
1553 t = rld[r1].optional - rld[r2].optional;
1557 /* Count all solitary classes before non-solitary ones. */
1558 t = ((reg_class_size[(int) rld[r2].class] == 1)
1559 - (reg_class_size[(int) rld[r1].class] == 1));
1563 /* Aside from solitaires, consider all multi-reg groups first. */
1564 t = rld[r2].nregs - rld[r1].nregs;
1568 /* Consider reloads in order of increasing reg-class number. */
1569 t = (int) rld[r1].class - (int) rld[r2].class;
1573 /* If reloads are equally urgent, sort by reload number,
1574 so that the results of qsort leave nothing to chance. */
1578 /* The cost of spilling each hard reg. */
1579 static int spill_cost[FIRST_PSEUDO_REGISTER];
1581 /* When spilling multiple hard registers, we use SPILL_COST for the first
1582 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1583 only the first hard reg for a multi-reg pseudo. */
1584 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1586 /* Update the spill cost arrays, considering that pseudo REG is live. */
1589 count_pseudo (int reg)
1591 int freq = REG_FREQ (reg);
1592 int r = reg_renumber[reg];
1595 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1596 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1599 SET_REGNO_REG_SET (&pseudos_counted, reg);
1601 gcc_assert (r >= 0);
1603 spill_add_cost[r] += freq;
1605 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1607 spill_cost[r + nregs] += freq;
1610 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1611 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1614 order_regs_for_reload (struct insn_chain *chain)
1617 HARD_REG_SET used_by_pseudos;
1618 HARD_REG_SET used_by_pseudos2;
1619 reg_set_iterator rsi;
1621 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1623 memset (spill_cost, 0, sizeof spill_cost);
1624 memset (spill_add_cost, 0, sizeof spill_add_cost);
1626 /* Count number of uses of each hard reg by pseudo regs allocated to it
1627 and then order them by decreasing use. First exclude hard registers
1628 that are live in or across this insn. */
1630 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1631 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1632 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1633 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1635 /* Now find out which pseudos are allocated to it, and update
1637 CLEAR_REG_SET (&pseudos_counted);
1639 EXECUTE_IF_SET_IN_REG_SET
1640 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1644 EXECUTE_IF_SET_IN_REG_SET
1645 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1649 CLEAR_REG_SET (&pseudos_counted);
1652 /* Vector of reload-numbers showing the order in which the reloads should
1654 static short reload_order[MAX_RELOADS];
1656 /* This is used to keep track of the spill regs used in one insn. */
1657 static HARD_REG_SET used_spill_regs_local;
1659 /* We decided to spill hard register SPILLED, which has a size of
1660 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1661 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1662 update SPILL_COST/SPILL_ADD_COST. */
1665 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1667 int r = reg_renumber[reg];
1668 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1670 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1671 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1674 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1676 spill_add_cost[r] -= REG_FREQ (reg);
1678 spill_cost[r + nregs] -= REG_FREQ (reg);
1681 /* Find reload register to use for reload number ORDER. */
1684 find_reg (struct insn_chain *chain, int order)
1686 int rnum = reload_order[order];
1687 struct reload *rl = rld + rnum;
1688 int best_cost = INT_MAX;
1692 HARD_REG_SET not_usable;
1693 HARD_REG_SET used_by_other_reload;
1694 reg_set_iterator rsi;
1696 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1697 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1698 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1700 CLEAR_HARD_REG_SET (used_by_other_reload);
1701 for (k = 0; k < order; k++)
1703 int other = reload_order[k];
1705 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1706 for (j = 0; j < rld[other].nregs; j++)
1707 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1710 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1712 unsigned int regno = i;
1714 if (! TEST_HARD_REG_BIT (not_usable, regno)
1715 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1716 && HARD_REGNO_MODE_OK (regno, rl->mode))
1718 int this_cost = spill_cost[regno];
1720 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1722 for (j = 1; j < this_nregs; j++)
1724 this_cost += spill_add_cost[regno + j];
1725 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1726 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1731 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1733 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1735 if (this_cost < best_cost
1736 /* Among registers with equal cost, prefer caller-saved ones, or
1737 use REG_ALLOC_ORDER if it is defined. */
1738 || (this_cost == best_cost
1739 #ifdef REG_ALLOC_ORDER
1740 && (inv_reg_alloc_order[regno]
1741 < inv_reg_alloc_order[best_reg])
1743 && call_used_regs[regno]
1744 && ! call_used_regs[best_reg]
1749 best_cost = this_cost;
1757 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1759 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1760 rl->regno = best_reg;
1762 EXECUTE_IF_SET_IN_REG_SET
1763 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1765 count_spilled_pseudo (best_reg, rl->nregs, j);
1768 EXECUTE_IF_SET_IN_REG_SET
1769 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1771 count_spilled_pseudo (best_reg, rl->nregs, j);
1774 for (i = 0; i < rl->nregs; i++)
1776 gcc_assert (spill_cost[best_reg + i] == 0);
1777 gcc_assert (spill_add_cost[best_reg + i] == 0);
1778 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1783 /* Find more reload regs to satisfy the remaining need of an insn, which
1785 Do it by ascending class number, since otherwise a reg
1786 might be spilled for a big class and might fail to count
1787 for a smaller class even though it belongs to that class. */
1790 find_reload_regs (struct insn_chain *chain)
1794 /* In order to be certain of getting the registers we need,
1795 we must sort the reloads into order of increasing register class.
1796 Then our grabbing of reload registers will parallel the process
1797 that provided the reload registers. */
1798 for (i = 0; i < chain->n_reloads; i++)
1800 /* Show whether this reload already has a hard reg. */
1801 if (chain->rld[i].reg_rtx)
1803 int regno = REGNO (chain->rld[i].reg_rtx);
1804 chain->rld[i].regno = regno;
1806 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1809 chain->rld[i].regno = -1;
1810 reload_order[i] = i;
1813 n_reloads = chain->n_reloads;
1814 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1816 CLEAR_HARD_REG_SET (used_spill_regs_local);
1819 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1821 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1823 /* Compute the order of preference for hard registers to spill. */
1825 order_regs_for_reload (chain);
1827 for (i = 0; i < n_reloads; i++)
1829 int r = reload_order[i];
1831 /* Ignore reloads that got marked inoperative. */
1832 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1833 && ! rld[r].optional
1834 && rld[r].regno == -1)
1835 if (! find_reg (chain, i))
1838 fprintf(dump_file, "reload failure for reload %d\n", r);
1839 spill_failure (chain->insn, rld[r].class);
1845 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1846 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1848 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1852 select_reload_regs (void)
1854 struct insn_chain *chain;
1856 /* Try to satisfy the needs for each insn. */
1857 for (chain = insns_need_reload; chain != 0;
1858 chain = chain->next_need_reload)
1859 find_reload_regs (chain);
1862 /* Delete all insns that were inserted by emit_caller_save_insns during
1865 delete_caller_save_insns (void)
1867 struct insn_chain *c = reload_insn_chain;
1871 while (c != 0 && c->is_caller_save_insn)
1873 struct insn_chain *next = c->next;
1876 if (c == reload_insn_chain)
1877 reload_insn_chain = next;
1881 next->prev = c->prev;
1883 c->prev->next = next;
1884 c->next = unused_insn_chains;
1885 unused_insn_chains = c;
1893 /* Handle the failure to find a register to spill.
1894 INSN should be one of the insns which needed this particular spill reg. */
1897 spill_failure (rtx insn, enum reg_class class)
1899 if (asm_noperands (PATTERN (insn)) >= 0)
1900 error_for_asm (insn, "can't find a register in class %qs while "
1901 "reloading %<asm%>",
1902 reg_class_names[class]);
1905 error ("unable to find a register to spill in class %qs",
1906 reg_class_names[class]);
1910 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1911 debug_reload_to_stream (dump_file);
1913 fatal_insn ("this is the insn:", insn);
1917 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1918 data that is dead in INSN. */
1921 delete_dead_insn (rtx insn)
1923 rtx prev = prev_real_insn (insn);
1926 /* If the previous insn sets a register that dies in our insn, delete it
1928 if (prev && GET_CODE (PATTERN (prev)) == SET
1929 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
1930 && reg_mentioned_p (prev_dest, PATTERN (insn))
1931 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1932 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1933 delete_dead_insn (prev);
1935 SET_INSN_DELETED (insn);
1938 /* Modify the home of pseudo-reg I.
1939 The new home is present in reg_renumber[I].
1941 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1942 or it may be -1, meaning there is none or it is not relevant.
1943 This is used so that all pseudos spilled from a given hard reg
1944 can share one stack slot. */
1947 alter_reg (int i, int from_reg)
1949 /* When outputting an inline function, this can happen
1950 for a reg that isn't actually used. */
1951 if (regno_reg_rtx[i] == 0)
1954 /* If the reg got changed to a MEM at rtl-generation time,
1956 if (!REG_P (regno_reg_rtx[i]))
1959 /* Modify the reg-rtx to contain the new hard reg
1960 number or else to contain its pseudo reg number. */
1961 REGNO (regno_reg_rtx[i])
1962 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1964 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1965 allocate a stack slot for it. */
1967 if (reg_renumber[i] < 0
1968 && REG_N_REFS (i) > 0
1969 && reg_equiv_constant[i] == 0
1970 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
1971 && reg_equiv_memory_loc[i] == 0)
1974 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1975 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1978 /* Each pseudo reg has an inherent size which comes from its own mode,
1979 and a total size which provides room for paradoxical subregs
1980 which refer to the pseudo reg in wider modes.
1982 We can use a slot already allocated if it provides both
1983 enough inherent space and enough total space.
1984 Otherwise, we allocate a new slot, making sure that it has no less
1985 inherent space, and no less total space, then the previous slot. */
1988 /* No known place to spill from => no slot to reuse. */
1989 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1990 inherent_size == total_size ? 0 : -1);
1991 if (BYTES_BIG_ENDIAN)
1992 /* Cancel the big-endian correction done in assign_stack_local.
1993 Get the address of the beginning of the slot.
1994 This is so we can do a big-endian correction unconditionally
1996 adjust = inherent_size - total_size;
1998 /* Nothing can alias this slot except this pseudo. */
1999 set_mem_alias_set (x, new_alias_set ());
2002 /* Reuse a stack slot if possible. */
2003 else if (spill_stack_slot[from_reg] != 0
2004 && spill_stack_slot_width[from_reg] >= total_size
2005 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2007 x = spill_stack_slot[from_reg];
2009 /* Allocate a bigger slot. */
2012 /* Compute maximum size needed, both for inherent size
2013 and for total size. */
2014 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2017 if (spill_stack_slot[from_reg])
2019 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2021 mode = GET_MODE (spill_stack_slot[from_reg]);
2022 if (spill_stack_slot_width[from_reg] > total_size)
2023 total_size = spill_stack_slot_width[from_reg];
2026 /* Make a slot with that size. */
2027 x = assign_stack_local (mode, total_size,
2028 inherent_size == total_size ? 0 : -1);
2031 /* All pseudos mapped to this slot can alias each other. */
2032 if (spill_stack_slot[from_reg])
2033 set_mem_alias_set (x, MEM_ALIAS_SET (spill_stack_slot[from_reg]));
2035 set_mem_alias_set (x, new_alias_set ());
2037 if (BYTES_BIG_ENDIAN)
2039 /* Cancel the big-endian correction done in assign_stack_local.
2040 Get the address of the beginning of the slot.
2041 This is so we can do a big-endian correction unconditionally
2043 adjust = GET_MODE_SIZE (mode) - total_size;
2046 = adjust_address_nv (x, mode_for_size (total_size
2052 spill_stack_slot[from_reg] = stack_slot;
2053 spill_stack_slot_width[from_reg] = total_size;
2056 /* On a big endian machine, the "address" of the slot
2057 is the address of the low part that fits its inherent mode. */
2058 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2059 adjust += (total_size - inherent_size);
2061 /* If we have any adjustment to make, or if the stack slot is the
2062 wrong mode, make a new stack slot. */
2063 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2065 /* If we have a decl for the original register, set it for the
2066 memory. If this is a shared MEM, make a copy. */
2067 if (REG_EXPR (regno_reg_rtx[i])
2068 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2070 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2072 /* We can do this only for the DECLs home pseudo, not for
2073 any copies of it, since otherwise when the stack slot
2074 is reused, nonoverlapping_memrefs_p might think they
2076 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2078 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2081 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2085 /* Save the stack slot for later. */
2086 reg_equiv_memory_loc[i] = x;
2090 /* Mark the slots in regs_ever_live for the hard regs
2091 used by pseudo-reg number REGNO. */
2094 mark_home_live (int regno)
2098 i = reg_renumber[regno];
2101 lim = i + hard_regno_nregs[i][PSEUDO_REGNO_MODE (regno)];
2103 regs_ever_live[i++] = 1;
2106 /* This function handles the tracking of elimination offsets around branches.
2108 X is a piece of RTL being scanned.
2110 INSN is the insn that it came from, if any.
2112 INITIAL_P is nonzero if we are to set the offset to be the initial
2113 offset and zero if we are setting the offset of the label to be the
2117 set_label_offsets (rtx x, rtx insn, int initial_p)
2119 enum rtx_code code = GET_CODE (x);
2122 struct elim_table *p;
2127 if (LABEL_REF_NONLOCAL_P (x))
2132 /* ... fall through ... */
2135 /* If we know nothing about this label, set the desired offsets. Note
2136 that this sets the offset at a label to be the offset before a label
2137 if we don't know anything about the label. This is not correct for
2138 the label after a BARRIER, but is the best guess we can make. If
2139 we guessed wrong, we will suppress an elimination that might have
2140 been possible had we been able to guess correctly. */
2142 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2144 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2145 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2146 = (initial_p ? reg_eliminate[i].initial_offset
2147 : reg_eliminate[i].offset);
2148 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2151 /* Otherwise, if this is the definition of a label and it is
2152 preceded by a BARRIER, set our offsets to the known offset of
2156 && (tem = prev_nonnote_insn (insn)) != 0
2158 set_offsets_for_label (insn);
2160 /* If neither of the above cases is true, compare each offset
2161 with those previously recorded and suppress any eliminations
2162 where the offsets disagree. */
2164 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2165 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2166 != (initial_p ? reg_eliminate[i].initial_offset
2167 : reg_eliminate[i].offset))
2168 reg_eliminate[i].can_eliminate = 0;
2173 set_label_offsets (PATTERN (insn), insn, initial_p);
2175 /* ... fall through ... */
2179 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2180 and hence must have all eliminations at their initial offsets. */
2181 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2182 if (REG_NOTE_KIND (tem) == REG_LABEL)
2183 set_label_offsets (XEXP (tem, 0), insn, 1);
2189 /* Each of the labels in the parallel or address vector must be
2190 at their initial offsets. We want the first field for PARALLEL
2191 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2193 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2194 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2199 /* We only care about setting PC. If the source is not RETURN,
2200 IF_THEN_ELSE, or a label, disable any eliminations not at
2201 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2202 isn't one of those possibilities. For branches to a label,
2203 call ourselves recursively.
2205 Note that this can disable elimination unnecessarily when we have
2206 a non-local goto since it will look like a non-constant jump to
2207 someplace in the current function. This isn't a significant
2208 problem since such jumps will normally be when all elimination
2209 pairs are back to their initial offsets. */
2211 if (SET_DEST (x) != pc_rtx)
2214 switch (GET_CODE (SET_SRC (x)))
2221 set_label_offsets (SET_SRC (x), insn, initial_p);
2225 tem = XEXP (SET_SRC (x), 1);
2226 if (GET_CODE (tem) == LABEL_REF)
2227 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2228 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2231 tem = XEXP (SET_SRC (x), 2);
2232 if (GET_CODE (tem) == LABEL_REF)
2233 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2234 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2242 /* If we reach here, all eliminations must be at their initial
2243 offset because we are doing a jump to a variable address. */
2244 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2245 if (p->offset != p->initial_offset)
2246 p->can_eliminate = 0;
2254 /* Scan X and replace any eliminable registers (such as fp) with a
2255 replacement (such as sp), plus an offset.
2257 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2258 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2259 MEM, we are allowed to replace a sum of a register and the constant zero
2260 with the register, which we cannot do outside a MEM. In addition, we need
2261 to record the fact that a register is referenced outside a MEM.
2263 If INSN is an insn, it is the insn containing X. If we replace a REG
2264 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2265 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2266 the REG is being modified.
2268 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2269 That's used when we eliminate in expressions stored in notes.
2270 This means, do not set ref_outside_mem even if the reference
2273 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2274 replacements done assuming all offsets are at their initial values. If
2275 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2276 encounter, return the actual location so that find_reloads will do
2277 the proper thing. */
2280 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2281 bool may_use_invariant)
2283 enum rtx_code code = GET_CODE (x);
2284 struct elim_table *ep;
2291 if (! current_function_decl)
2313 /* First handle the case where we encounter a bare register that
2314 is eliminable. Replace it with a PLUS. */
2315 if (regno < FIRST_PSEUDO_REGISTER)
2317 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2319 if (ep->from_rtx == x && ep->can_eliminate)
2320 return plus_constant (ep->to_rtx, ep->previous_offset);
2323 else if (reg_renumber && reg_renumber[regno] < 0
2324 && reg_equiv_invariant && reg_equiv_invariant[regno])
2326 if (may_use_invariant)
2327 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2328 mem_mode, insn, true);
2329 /* There exists at least one use of REGNO that cannot be
2330 eliminated. Prevent the defining insn from being deleted. */
2331 reg_equiv_init[regno] = NULL_RTX;
2332 alter_reg (regno, -1);
2336 /* You might think handling MINUS in a manner similar to PLUS is a
2337 good idea. It is not. It has been tried multiple times and every
2338 time the change has had to have been reverted.
2340 Other parts of reload know a PLUS is special (gen_reload for example)
2341 and require special code to handle code a reloaded PLUS operand.
2343 Also consider backends where the flags register is clobbered by a
2344 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2345 lea instruction comes to mind). If we try to reload a MINUS, we
2346 may kill the flags register that was holding a useful value.
2348 So, please before trying to handle MINUS, consider reload as a
2349 whole instead of this little section as well as the backend issues. */
2351 /* If this is the sum of an eliminable register and a constant, rework
2353 if (REG_P (XEXP (x, 0))
2354 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2355 && CONSTANT_P (XEXP (x, 1)))
2357 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2359 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2361 /* The only time we want to replace a PLUS with a REG (this
2362 occurs when the constant operand of the PLUS is the negative
2363 of the offset) is when we are inside a MEM. We won't want
2364 to do so at other times because that would change the
2365 structure of the insn in a way that reload can't handle.
2366 We special-case the commonest situation in
2367 eliminate_regs_in_insn, so just replace a PLUS with a
2368 PLUS here, unless inside a MEM. */
2369 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2370 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2373 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2374 plus_constant (XEXP (x, 1),
2375 ep->previous_offset));
2378 /* If the register is not eliminable, we are done since the other
2379 operand is a constant. */
2383 /* If this is part of an address, we want to bring any constant to the
2384 outermost PLUS. We will do this by doing register replacement in
2385 our operands and seeing if a constant shows up in one of them.
2387 Note that there is no risk of modifying the structure of the insn,
2388 since we only get called for its operands, thus we are either
2389 modifying the address inside a MEM, or something like an address
2390 operand of a load-address insn. */
2393 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2394 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2396 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2398 /* If one side is a PLUS and the other side is a pseudo that
2399 didn't get a hard register but has a reg_equiv_constant,
2400 we must replace the constant here since it may no longer
2401 be in the position of any operand. */
2402 if (GET_CODE (new0) == PLUS && REG_P (new1)
2403 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2404 && reg_renumber[REGNO (new1)] < 0
2405 && reg_equiv_constant != 0
2406 && reg_equiv_constant[REGNO (new1)] != 0)
2407 new1 = reg_equiv_constant[REGNO (new1)];
2408 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2409 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2410 && reg_renumber[REGNO (new0)] < 0
2411 && reg_equiv_constant[REGNO (new0)] != 0)
2412 new0 = reg_equiv_constant[REGNO (new0)];
2414 new = form_sum (new0, new1);
2416 /* As above, if we are not inside a MEM we do not want to
2417 turn a PLUS into something else. We might try to do so here
2418 for an addition of 0 if we aren't optimizing. */
2419 if (! mem_mode && GET_CODE (new) != PLUS)
2420 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2428 /* If this is the product of an eliminable register and a
2429 constant, apply the distribute law and move the constant out
2430 so that we have (plus (mult ..) ..). This is needed in order
2431 to keep load-address insns valid. This case is pathological.
2432 We ignore the possibility of overflow here. */
2433 if (REG_P (XEXP (x, 0))
2434 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2435 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2436 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2438 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2441 /* Refs inside notes don't count for this purpose. */
2442 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2443 || GET_CODE (insn) == INSN_LIST)))
2444 ep->ref_outside_mem = 1;
2447 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2448 ep->previous_offset * INTVAL (XEXP (x, 1)));
2451 /* ... fall through ... */
2455 /* See comments before PLUS about handling MINUS. */
2457 case DIV: case UDIV:
2458 case MOD: case UMOD:
2459 case AND: case IOR: case XOR:
2460 case ROTATERT: case ROTATE:
2461 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2463 case GE: case GT: case GEU: case GTU:
2464 case LE: case LT: case LEU: case LTU:
2466 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2467 rtx new1 = XEXP (x, 1)
2468 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2470 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2471 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2476 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2479 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2480 if (new != XEXP (x, 0))
2482 /* If this is a REG_DEAD note, it is not valid anymore.
2483 Using the eliminated version could result in creating a
2484 REG_DEAD note for the stack or frame pointer. */
2485 if (GET_MODE (x) == REG_DEAD)
2487 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2490 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2494 /* ... fall through ... */
2497 /* Now do eliminations in the rest of the chain. If this was
2498 an EXPR_LIST, this might result in allocating more memory than is
2499 strictly needed, but it simplifies the code. */
2502 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2503 if (new != XEXP (x, 1))
2505 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2513 case STRICT_LOW_PART:
2515 case SIGN_EXTEND: case ZERO_EXTEND:
2516 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2517 case FLOAT: case FIX:
2518 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2526 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2527 if (new != XEXP (x, 0))
2528 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2532 /* Similar to above processing, but preserve SUBREG_BYTE.
2533 Convert (subreg (mem)) to (mem) if not paradoxical.
2534 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2535 pseudo didn't get a hard reg, we must replace this with the
2536 eliminated version of the memory location because push_reload
2537 may do the replacement in certain circumstances. */
2538 if (REG_P (SUBREG_REG (x))
2539 && (GET_MODE_SIZE (GET_MODE (x))
2540 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2541 && reg_equiv_memory_loc != 0
2542 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2544 new = SUBREG_REG (x);
2547 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2549 if (new != SUBREG_REG (x))
2551 int x_size = GET_MODE_SIZE (GET_MODE (x));
2552 int new_size = GET_MODE_SIZE (GET_MODE (new));
2555 && ((x_size < new_size
2556 #ifdef WORD_REGISTER_OPERATIONS
2557 /* On these machines, combine can create rtl of the form
2558 (set (subreg:m1 (reg:m2 R) 0) ...)
2559 where m1 < m2, and expects something interesting to
2560 happen to the entire word. Moreover, it will use the
2561 (reg:m2 R) later, expecting all bits to be preserved.
2562 So if the number of words is the same, preserve the
2563 subreg so that push_reload can see it. */
2564 && ! ((x_size - 1) / UNITS_PER_WORD
2565 == (new_size -1 ) / UNITS_PER_WORD)
2568 || x_size == new_size)
2570 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2572 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2578 /* Our only special processing is to pass the mode of the MEM to our
2579 recursive call and copy the flags. While we are here, handle this
2580 case more efficiently. */
2582 replace_equiv_address_nv (x,
2583 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2587 /* Handle insn_list USE that a call to a pure function may generate. */
2588 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2589 if (new != XEXP (x, 0))
2590 return gen_rtx_USE (GET_MODE (x), new);
2602 /* Process each of our operands recursively. If any have changed, make a
2604 fmt = GET_RTX_FORMAT (code);
2605 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2609 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2610 if (new != XEXP (x, i) && ! copied)
2612 x = shallow_copy_rtx (x);
2617 else if (*fmt == 'E')
2620 for (j = 0; j < XVECLEN (x, i); j++)
2622 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2623 if (new != XVECEXP (x, i, j) && ! copied_vec)
2625 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2629 x = shallow_copy_rtx (x);
2632 XVEC (x, i) = new_v;
2635 XVECEXP (x, i, j) = new;
2644 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2646 return eliminate_regs_1 (x, mem_mode, insn, false);
2649 /* Scan rtx X for modifications of elimination target registers. Update
2650 the table of eliminables to reflect the changed state. MEM_MODE is
2651 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2654 elimination_effects (rtx x, enum machine_mode mem_mode)
2656 enum rtx_code code = GET_CODE (x);
2657 struct elim_table *ep;
2681 /* First handle the case where we encounter a bare register that
2682 is eliminable. Replace it with a PLUS. */
2683 if (regno < FIRST_PSEUDO_REGISTER)
2685 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2687 if (ep->from_rtx == x && ep->can_eliminate)
2690 ep->ref_outside_mem = 1;
2695 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2696 && reg_equiv_constant[regno]
2697 && ! function_invariant_p (reg_equiv_constant[regno]))
2698 elimination_effects (reg_equiv_constant[regno], mem_mode);
2707 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2708 if (ep->to_rtx == XEXP (x, 0))
2710 int size = GET_MODE_SIZE (mem_mode);
2712 /* If more bytes than MEM_MODE are pushed, account for them. */
2713 #ifdef PUSH_ROUNDING
2714 if (ep->to_rtx == stack_pointer_rtx)
2715 size = PUSH_ROUNDING (size);
2717 if (code == PRE_DEC || code == POST_DEC)
2719 else if (code == PRE_INC || code == POST_INC)
2721 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2722 && GET_CODE (XEXP (x, 1)) == PLUS
2723 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2724 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2725 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2728 /* These two aren't unary operators. */
2729 if (code == POST_MODIFY || code == PRE_MODIFY)
2732 /* Fall through to generic unary operation case. */
2733 case STRICT_LOW_PART:
2735 case SIGN_EXTEND: case ZERO_EXTEND:
2736 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2737 case FLOAT: case FIX:
2738 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2746 elimination_effects (XEXP (x, 0), mem_mode);
2750 if (REG_P (SUBREG_REG (x))
2751 && (GET_MODE_SIZE (GET_MODE (x))
2752 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2753 && reg_equiv_memory_loc != 0
2754 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2757 elimination_effects (SUBREG_REG (x), mem_mode);
2761 /* If using a register that is the source of an eliminate we still
2762 think can be performed, note it cannot be performed since we don't
2763 know how this register is used. */
2764 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2765 if (ep->from_rtx == XEXP (x, 0))
2766 ep->can_eliminate = 0;
2768 elimination_effects (XEXP (x, 0), mem_mode);
2772 /* If clobbering a register that is the replacement register for an
2773 elimination we still think can be performed, note that it cannot
2774 be performed. Otherwise, we need not be concerned about it. */
2775 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2776 if (ep->to_rtx == XEXP (x, 0))
2777 ep->can_eliminate = 0;
2779 elimination_effects (XEXP (x, 0), mem_mode);
2783 /* Check for setting a register that we know about. */
2784 if (REG_P (SET_DEST (x)))
2786 /* See if this is setting the replacement register for an
2789 If DEST is the hard frame pointer, we do nothing because we
2790 assume that all assignments to the frame pointer are for
2791 non-local gotos and are being done at a time when they are valid
2792 and do not disturb anything else. Some machines want to
2793 eliminate a fake argument pointer (or even a fake frame pointer)
2794 with either the real frame or the stack pointer. Assignments to
2795 the hard frame pointer must not prevent this elimination. */
2797 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2799 if (ep->to_rtx == SET_DEST (x)
2800 && SET_DEST (x) != hard_frame_pointer_rtx)
2802 /* If it is being incremented, adjust the offset. Otherwise,
2803 this elimination can't be done. */
2804 rtx src = SET_SRC (x);
2806 if (GET_CODE (src) == PLUS
2807 && XEXP (src, 0) == SET_DEST (x)
2808 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2809 ep->offset -= INTVAL (XEXP (src, 1));
2811 ep->can_eliminate = 0;
2815 elimination_effects (SET_DEST (x), 0);
2816 elimination_effects (SET_SRC (x), 0);
2820 /* Our only special processing is to pass the mode of the MEM to our
2822 elimination_effects (XEXP (x, 0), GET_MODE (x));
2829 fmt = GET_RTX_FORMAT (code);
2830 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2833 elimination_effects (XEXP (x, i), mem_mode);
2834 else if (*fmt == 'E')
2835 for (j = 0; j < XVECLEN (x, i); j++)
2836 elimination_effects (XVECEXP (x, i, j), mem_mode);
2840 /* Descend through rtx X and verify that no references to eliminable registers
2841 remain. If any do remain, mark the involved register as not
2845 check_eliminable_occurrences (rtx x)
2854 code = GET_CODE (x);
2856 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2858 struct elim_table *ep;
2860 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2861 if (ep->from_rtx == x)
2862 ep->can_eliminate = 0;
2866 fmt = GET_RTX_FORMAT (code);
2867 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2870 check_eliminable_occurrences (XEXP (x, i));
2871 else if (*fmt == 'E')
2874 for (j = 0; j < XVECLEN (x, i); j++)
2875 check_eliminable_occurrences (XVECEXP (x, i, j));
2880 /* Scan INSN and eliminate all eliminable registers in it.
2882 If REPLACE is nonzero, do the replacement destructively. Also
2883 delete the insn as dead it if it is setting an eliminable register.
2885 If REPLACE is zero, do all our allocations in reload_obstack.
2887 If no eliminations were done and this insn doesn't require any elimination
2888 processing (these are not identical conditions: it might be updating sp,
2889 but not referencing fp; this needs to be seen during reload_as_needed so
2890 that the offset between fp and sp can be taken into consideration), zero
2891 is returned. Otherwise, 1 is returned. */
2894 eliminate_regs_in_insn (rtx insn, int replace)
2896 int icode = recog_memoized (insn);
2897 rtx old_body = PATTERN (insn);
2898 int insn_is_asm = asm_noperands (old_body) >= 0;
2899 rtx old_set = single_set (insn);
2903 rtx substed_operand[MAX_RECOG_OPERANDS];
2904 rtx orig_operand[MAX_RECOG_OPERANDS];
2905 struct elim_table *ep;
2906 rtx plus_src, plus_cst_src;
2908 if (! insn_is_asm && icode < 0)
2910 gcc_assert (GET_CODE (PATTERN (insn)) == USE
2911 || GET_CODE (PATTERN (insn)) == CLOBBER
2912 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2913 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2914 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
2918 if (old_set != 0 && REG_P (SET_DEST (old_set))
2919 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2921 /* Check for setting an eliminable register. */
2922 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2923 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2925 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2926 /* If this is setting the frame pointer register to the
2927 hardware frame pointer register and this is an elimination
2928 that will be done (tested above), this insn is really
2929 adjusting the frame pointer downward to compensate for
2930 the adjustment done before a nonlocal goto. */
2931 if (ep->from == FRAME_POINTER_REGNUM
2932 && ep->to == HARD_FRAME_POINTER_REGNUM)
2934 rtx base = SET_SRC (old_set);
2935 rtx base_insn = insn;
2936 HOST_WIDE_INT offset = 0;
2938 while (base != ep->to_rtx)
2940 rtx prev_insn, prev_set;
2942 if (GET_CODE (base) == PLUS
2943 && GET_CODE (XEXP (base, 1)) == CONST_INT)
2945 offset += INTVAL (XEXP (base, 1));
2946 base = XEXP (base, 0);
2948 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
2949 && (prev_set = single_set (prev_insn)) != 0
2950 && rtx_equal_p (SET_DEST (prev_set), base))
2952 base = SET_SRC (prev_set);
2953 base_insn = prev_insn;
2959 if (base == ep->to_rtx)
2962 = plus_constant (ep->to_rtx, offset - ep->offset);
2964 new_body = old_body;
2967 new_body = copy_insn (old_body);
2968 if (REG_NOTES (insn))
2969 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
2971 PATTERN (insn) = new_body;
2972 old_set = single_set (insn);
2974 /* First see if this insn remains valid when we
2975 make the change. If not, keep the INSN_CODE
2976 the same and let reload fit it up. */
2977 validate_change (insn, &SET_SRC (old_set), src, 1);
2978 validate_change (insn, &SET_DEST (old_set),
2980 if (! apply_change_group ())
2982 SET_SRC (old_set) = src;
2983 SET_DEST (old_set) = ep->to_rtx;
2992 /* In this case this insn isn't serving a useful purpose. We
2993 will delete it in reload_as_needed once we know that this
2994 elimination is, in fact, being done.
2996 If REPLACE isn't set, we can't delete this insn, but needn't
2997 process it since it won't be used unless something changes. */
3000 delete_dead_insn (insn);
3008 /* We allow one special case which happens to work on all machines we
3009 currently support: a single set with the source or a REG_EQUAL
3010 note being a PLUS of an eliminable register and a constant. */
3011 plus_src = plus_cst_src = 0;
3012 if (old_set && REG_P (SET_DEST (old_set)))
3014 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3015 plus_src = SET_SRC (old_set);
3016 /* First see if the source is of the form (plus (...) CST). */
3018 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3019 plus_cst_src = plus_src;
3020 else if (REG_P (SET_SRC (old_set))
3023 /* Otherwise, see if we have a REG_EQUAL note of the form
3024 (plus (...) CST). */
3026 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3028 if (REG_NOTE_KIND (links) == REG_EQUAL
3029 && GET_CODE (XEXP (links, 0)) == PLUS
3030 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3032 plus_cst_src = XEXP (links, 0);
3038 /* Check that the first operand of the PLUS is a hard reg or
3039 the lowpart subreg of one. */
3042 rtx reg = XEXP (plus_cst_src, 0);
3043 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3044 reg = SUBREG_REG (reg);
3046 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3052 rtx reg = XEXP (plus_cst_src, 0);
3053 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3055 if (GET_CODE (reg) == SUBREG)
3056 reg = SUBREG_REG (reg);
3058 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3059 if (ep->from_rtx == reg && ep->can_eliminate)
3061 rtx to_rtx = ep->to_rtx;
3062 offset += ep->offset;
3064 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3065 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3070 /* We assume here that if we need a PARALLEL with
3071 CLOBBERs for this assignment, we can do with the
3072 MATCH_SCRATCHes that add_clobbers allocates.
3073 There's not much we can do if that doesn't work. */
3074 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3078 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3081 rtvec vec = rtvec_alloc (num_clobbers + 1);
3083 vec->elem[0] = PATTERN (insn);
3084 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3085 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3087 gcc_assert (INSN_CODE (insn) >= 0);
3089 /* If we have a nonzero offset, and the source is already
3090 a simple REG, the following transformation would
3091 increase the cost of the insn by replacing a simple REG
3092 with (plus (reg sp) CST). So try only when we already
3093 had a PLUS before. */
3096 new_body = old_body;
3099 new_body = copy_insn (old_body);
3100 if (REG_NOTES (insn))
3101 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3103 PATTERN (insn) = new_body;
3104 old_set = single_set (insn);
3106 XEXP (SET_SRC (old_set), 0) = to_rtx;
3107 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3113 /* This can't have an effect on elimination offsets, so skip right
3119 /* Determine the effects of this insn on elimination offsets. */
3120 elimination_effects (old_body, 0);
3122 /* Eliminate all eliminable registers occurring in operands that
3123 can be handled by reload. */
3124 extract_insn (insn);
3125 for (i = 0; i < recog_data.n_operands; i++)
3127 orig_operand[i] = recog_data.operand[i];
3128 substed_operand[i] = recog_data.operand[i];
3130 /* For an asm statement, every operand is eliminable. */
3131 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3133 bool is_set_src, in_plus;
3135 /* Check for setting a register that we know about. */
3136 if (recog_data.operand_type[i] != OP_IN
3137 && REG_P (orig_operand[i]))
3139 /* If we are assigning to a register that can be eliminated, it
3140 must be as part of a PARALLEL, since the code above handles
3141 single SETs. We must indicate that we can no longer
3142 eliminate this reg. */
3143 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3145 if (ep->from_rtx == orig_operand[i])
3146 ep->can_eliminate = 0;
3149 /* Companion to the above plus substitution, we can allow
3150 invariants as the source of a plain move. */
3152 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3156 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3157 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3161 = eliminate_regs_1 (recog_data.operand[i], 0,
3162 replace ? insn : NULL_RTX,
3163 is_set_src || in_plus);
3164 if (substed_operand[i] != orig_operand[i])
3166 /* Terminate the search in check_eliminable_occurrences at
3168 *recog_data.operand_loc[i] = 0;
3170 /* If an output operand changed from a REG to a MEM and INSN is an
3171 insn, write a CLOBBER insn. */
3172 if (recog_data.operand_type[i] != OP_IN
3173 && REG_P (orig_operand[i])
3174 && MEM_P (substed_operand[i])
3176 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3181 for (i = 0; i < recog_data.n_dups; i++)
3182 *recog_data.dup_loc[i]
3183 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3185 /* If any eliminable remain, they aren't eliminable anymore. */
3186 check_eliminable_occurrences (old_body);
3188 /* Substitute the operands; the new values are in the substed_operand
3190 for (i = 0; i < recog_data.n_operands; i++)
3191 *recog_data.operand_loc[i] = substed_operand[i];
3192 for (i = 0; i < recog_data.n_dups; i++)
3193 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3195 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3196 re-recognize the insn. We do this in case we had a simple addition
3197 but now can do this as a load-address. This saves an insn in this
3199 If re-recognition fails, the old insn code number will still be used,
3200 and some register operands may have changed into PLUS expressions.
3201 These will be handled by find_reloads by loading them into a register
3206 /* If we aren't replacing things permanently and we changed something,
3207 make another copy to ensure that all the RTL is new. Otherwise
3208 things can go wrong if find_reload swaps commutative operands
3209 and one is inside RTL that has been copied while the other is not. */
3210 new_body = old_body;
3213 new_body = copy_insn (old_body);
3214 if (REG_NOTES (insn))
3215 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3217 PATTERN (insn) = new_body;
3219 /* If we had a move insn but now we don't, rerecognize it. This will
3220 cause spurious re-recognition if the old move had a PARALLEL since
3221 the new one still will, but we can't call single_set without
3222 having put NEW_BODY into the insn and the re-recognition won't
3223 hurt in this rare case. */
3224 /* ??? Why this huge if statement - why don't we just rerecognize the
3228 && ((REG_P (SET_SRC (old_set))
3229 && (GET_CODE (new_body) != SET
3230 || !REG_P (SET_SRC (new_body))))
3231 /* If this was a load from or store to memory, compare
3232 the MEM in recog_data.operand to the one in the insn.
3233 If they are not equal, then rerecognize the insn. */
3235 && ((MEM_P (SET_SRC (old_set))
3236 && SET_SRC (old_set) != recog_data.operand[1])
3237 || (MEM_P (SET_DEST (old_set))
3238 && SET_DEST (old_set) != recog_data.operand[0])))
3239 /* If this was an add insn before, rerecognize. */
3240 || GET_CODE (SET_SRC (old_set)) == PLUS))
3242 int new_icode = recog (PATTERN (insn), insn, 0);
3244 INSN_CODE (insn) = new_icode;
3248 /* Restore the old body. If there were any changes to it, we made a copy
3249 of it while the changes were still in place, so we'll correctly return
3250 a modified insn below. */
3253 /* Restore the old body. */
3254 for (i = 0; i < recog_data.n_operands; i++)
3255 *recog_data.operand_loc[i] = orig_operand[i];
3256 for (i = 0; i < recog_data.n_dups; i++)
3257 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3260 /* Update all elimination pairs to reflect the status after the current
3261 insn. The changes we make were determined by the earlier call to
3262 elimination_effects.
3264 We also detect cases where register elimination cannot be done,
3265 namely, if a register would be both changed and referenced outside a MEM
3266 in the resulting insn since such an insn is often undefined and, even if
3267 not, we cannot know what meaning will be given to it. Note that it is
3268 valid to have a register used in an address in an insn that changes it
3269 (presumably with a pre- or post-increment or decrement).
3271 If anything changes, return nonzero. */
3273 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3275 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3276 ep->can_eliminate = 0;
3278 ep->ref_outside_mem = 0;
3280 if (ep->previous_offset != ep->offset)
3285 /* If we changed something, perform elimination in REG_NOTES. This is
3286 needed even when REPLACE is zero because a REG_DEAD note might refer
3287 to a register that we eliminate and could cause a different number
3288 of spill registers to be needed in the final reload pass than in
3290 if (val && REG_NOTES (insn) != 0)
3292 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3297 /* Loop through all elimination pairs.
3298 Recalculate the number not at initial offset.
3300 Compute the maximum offset (minimum offset if the stack does not
3301 grow downward) for each elimination pair. */
3304 update_eliminable_offsets (void)
3306 struct elim_table *ep;
3308 num_not_at_initial_offset = 0;
3309 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3311 ep->previous_offset = ep->offset;
3312 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3313 num_not_at_initial_offset++;
3317 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3318 replacement we currently believe is valid, mark it as not eliminable if X
3319 modifies DEST in any way other than by adding a constant integer to it.
3321 If DEST is the frame pointer, we do nothing because we assume that
3322 all assignments to the hard frame pointer are nonlocal gotos and are being
3323 done at a time when they are valid and do not disturb anything else.
3324 Some machines want to eliminate a fake argument pointer with either the
3325 frame or stack pointer. Assignments to the hard frame pointer must not
3326 prevent this elimination.
3328 Called via note_stores from reload before starting its passes to scan
3329 the insns of the function. */
3332 mark_not_eliminable (rtx dest, rtx x, void *data ATTRIBUTE_UNUSED)
3336 /* A SUBREG of a hard register here is just changing its mode. We should
3337 not see a SUBREG of an eliminable hard register, but check just in
3339 if (GET_CODE (dest) == SUBREG)
3340 dest = SUBREG_REG (dest);
3342 if (dest == hard_frame_pointer_rtx)
3345 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3346 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3347 && (GET_CODE (x) != SET
3348 || GET_CODE (SET_SRC (x)) != PLUS
3349 || XEXP (SET_SRC (x), 0) != dest
3350 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3352 reg_eliminate[i].can_eliminate_previous
3353 = reg_eliminate[i].can_eliminate = 0;
3358 /* Verify that the initial elimination offsets did not change since the
3359 last call to set_initial_elim_offsets. This is used to catch cases
3360 where something illegal happened during reload_as_needed that could
3361 cause incorrect code to be generated if we did not check for it. */
3364 verify_initial_elim_offsets (void)
3368 if (!num_eliminable)
3371 #ifdef ELIMINABLE_REGS
3373 struct elim_table *ep;
3375 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3377 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3378 if (t != ep->initial_offset)
3383 INITIAL_FRAME_POINTER_OFFSET (t);
3384 if (t != reg_eliminate[0].initial_offset)
3391 /* Reset all offsets on eliminable registers to their initial values. */
3394 set_initial_elim_offsets (void)
3396 struct elim_table *ep = reg_eliminate;
3398 #ifdef ELIMINABLE_REGS
3399 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3401 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3402 ep->previous_offset = ep->offset = ep->initial_offset;
3405 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3406 ep->previous_offset = ep->offset = ep->initial_offset;
3409 num_not_at_initial_offset = 0;
3412 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3415 set_initial_eh_label_offset (rtx label)
3417 set_label_offsets (label, NULL_RTX, 1);
3420 /* Initialize the known label offsets.
3421 Set a known offset for each forced label to be at the initial offset
3422 of each elimination. We do this because we assume that all
3423 computed jumps occur from a location where each elimination is
3424 at its initial offset.
3425 For all other labels, show that we don't know the offsets. */
3428 set_initial_label_offsets (void)
3431 memset (offsets_known_at, 0, num_labels);
3433 for (x = forced_labels; x; x = XEXP (x, 1))
3435 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3437 for_each_eh_label (set_initial_eh_label_offset);
3440 /* Set all elimination offsets to the known values for the code label given
3444 set_offsets_for_label (rtx insn)
3447 int label_nr = CODE_LABEL_NUMBER (insn);
3448 struct elim_table *ep;
3450 num_not_at_initial_offset = 0;
3451 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3453 ep->offset = ep->previous_offset
3454 = offsets_at[label_nr - first_label_num][i];
3455 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3456 num_not_at_initial_offset++;
3460 /* See if anything that happened changes which eliminations are valid.
3461 For example, on the SPARC, whether or not the frame pointer can
3462 be eliminated can depend on what registers have been used. We need
3463 not check some conditions again (such as flag_omit_frame_pointer)
3464 since they can't have changed. */
3467 update_eliminables (HARD_REG_SET *pset)
3469 int previous_frame_pointer_needed = frame_pointer_needed;
3470 struct elim_table *ep;
3472 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3473 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3474 #ifdef ELIMINABLE_REGS
3475 || ! CAN_ELIMINATE (ep->from, ep->to)
3478 ep->can_eliminate = 0;
3480 /* Look for the case where we have discovered that we can't replace
3481 register A with register B and that means that we will now be
3482 trying to replace register A with register C. This means we can
3483 no longer replace register C with register B and we need to disable
3484 such an elimination, if it exists. This occurs often with A == ap,
3485 B == sp, and C == fp. */
3487 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3489 struct elim_table *op;
3492 if (! ep->can_eliminate && ep->can_eliminate_previous)
3494 /* Find the current elimination for ep->from, if there is a
3496 for (op = reg_eliminate;
3497 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3498 if (op->from == ep->from && op->can_eliminate)
3504 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3506 for (op = reg_eliminate;
3507 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3508 if (op->from == new_to && op->to == ep->to)
3509 op->can_eliminate = 0;
3513 /* See if any registers that we thought we could eliminate the previous
3514 time are no longer eliminable. If so, something has changed and we
3515 must spill the register. Also, recompute the number of eliminable
3516 registers and see if the frame pointer is needed; it is if there is
3517 no elimination of the frame pointer that we can perform. */
3519 frame_pointer_needed = 1;
3520 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3522 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3523 && ep->to != HARD_FRAME_POINTER_REGNUM)
3524 frame_pointer_needed = 0;
3526 if (! ep->can_eliminate && ep->can_eliminate_previous)
3528 ep->can_eliminate_previous = 0;
3529 SET_HARD_REG_BIT (*pset, ep->from);
3534 /* If we didn't need a frame pointer last time, but we do now, spill
3535 the hard frame pointer. */
3536 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3537 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3540 /* Initialize the table of registers to eliminate. */
3543 init_elim_table (void)
3545 struct elim_table *ep;
3546 #ifdef ELIMINABLE_REGS
3547 const struct elim_table_1 *ep1;
3551 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3553 /* Does this function require a frame pointer? */
3555 frame_pointer_needed = (! flag_omit_frame_pointer
3556 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3557 and restore sp for alloca. So we can't eliminate
3558 the frame pointer in that case. At some point,
3559 we should improve this by emitting the
3560 sp-adjusting insns for this case. */
3561 || (current_function_calls_alloca
3562 && EXIT_IGNORE_STACK)
3563 || current_function_accesses_prior_frames
3564 || FRAME_POINTER_REQUIRED);
3568 #ifdef ELIMINABLE_REGS
3569 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3570 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3572 ep->from = ep1->from;
3574 ep->can_eliminate = ep->can_eliminate_previous
3575 = (CAN_ELIMINATE (ep->from, ep->to)
3576 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3579 reg_eliminate[0].from = reg_eliminate_1[0].from;
3580 reg_eliminate[0].to = reg_eliminate_1[0].to;
3581 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3582 = ! frame_pointer_needed;
3585 /* Count the number of eliminable registers and build the FROM and TO
3586 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3587 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3588 We depend on this. */
3589 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3591 num_eliminable += ep->can_eliminate;
3592 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3593 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3597 /* Kick all pseudos out of hard register REGNO.
3599 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3600 because we found we can't eliminate some register. In the case, no pseudos
3601 are allowed to be in the register, even if they are only in a block that
3602 doesn't require spill registers, unlike the case when we are spilling this
3603 hard reg to produce another spill register.
3605 Return nonzero if any pseudos needed to be kicked out. */
3608 spill_hard_reg (unsigned int regno, int cant_eliminate)
3614 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3615 regs_ever_live[regno] = 1;
3618 /* Spill every pseudo reg that was allocated to this reg
3619 or to something that overlaps this reg. */
3621 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3622 if (reg_renumber[i] >= 0
3623 && (unsigned int) reg_renumber[i] <= regno
3624 && ((unsigned int) reg_renumber[i]
3625 + hard_regno_nregs[(unsigned int) reg_renumber[i]]
3626 [PSEUDO_REGNO_MODE (i)]
3628 SET_REGNO_REG_SET (&spilled_pseudos, i);
3631 /* After find_reload_regs has been run for all insn that need reloads,
3632 and/or spill_hard_regs was called, this function is used to actually
3633 spill pseudo registers and try to reallocate them. It also sets up the
3634 spill_regs array for use by choose_reload_regs. */
3637 finish_spills (int global)
3639 struct insn_chain *chain;
3640 int something_changed = 0;
3642 reg_set_iterator rsi;
3644 /* Build the spill_regs array for the function. */
3645 /* If there are some registers still to eliminate and one of the spill regs
3646 wasn't ever used before, additional stack space may have to be
3647 allocated to store this register. Thus, we may have changed the offset
3648 between the stack and frame pointers, so mark that something has changed.
3650 One might think that we need only set VAL to 1 if this is a call-used
3651 register. However, the set of registers that must be saved by the
3652 prologue is not identical to the call-used set. For example, the
3653 register used by the call insn for the return PC is a call-used register,
3654 but must be saved by the prologue. */
3657 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3658 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3660 spill_reg_order[i] = n_spills;
3661 spill_regs[n_spills++] = i;
3662 if (num_eliminable && ! regs_ever_live[i])
3663 something_changed = 1;
3664 regs_ever_live[i] = 1;
3667 spill_reg_order[i] = -1;
3669 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3671 /* Record the current hard register the pseudo is allocated to in
3672 pseudo_previous_regs so we avoid reallocating it to the same
3673 hard reg in a later pass. */
3674 gcc_assert (reg_renumber[i] >= 0);
3676 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3677 /* Mark it as no longer having a hard register home. */
3678 reg_renumber[i] = -1;
3679 /* We will need to scan everything again. */
3680 something_changed = 1;
3683 /* Retry global register allocation if possible. */
3686 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3687 /* For every insn that needs reloads, set the registers used as spill
3688 regs in pseudo_forbidden_regs for every pseudo live across the
3690 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3692 EXECUTE_IF_SET_IN_REG_SET
3693 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3695 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3696 chain->used_spill_regs);
3698 EXECUTE_IF_SET_IN_REG_SET
3699 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3701 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3702 chain->used_spill_regs);
3706 /* Retry allocating the spilled pseudos. For each reg, merge the
3707 various reg sets that indicate which hard regs can't be used,
3708 and call retry_global_alloc.
3709 We change spill_pseudos here to only contain pseudos that did not
3710 get a new hard register. */
3711 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3712 if (reg_old_renumber[i] != reg_renumber[i])
3714 HARD_REG_SET forbidden;
3715 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3716 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3717 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3718 retry_global_alloc (i, forbidden);
3719 if (reg_renumber[i] >= 0)
3720 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3724 /* Fix up the register information in the insn chain.
3725 This involves deleting those of the spilled pseudos which did not get
3726 a new hard register home from the live_{before,after} sets. */
3727 for (chain = reload_insn_chain; chain; chain = chain->next)
3729 HARD_REG_SET used_by_pseudos;
3730 HARD_REG_SET used_by_pseudos2;
3732 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3733 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3735 /* Mark any unallocated hard regs as available for spills. That
3736 makes inheritance work somewhat better. */
3737 if (chain->need_reload)
3739 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3740 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3741 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3743 /* Save the old value for the sanity test below. */
3744 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3746 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3747 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3748 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3749 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3751 /* Make sure we only enlarge the set. */
3752 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3758 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3759 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3761 int regno = reg_renumber[i];
3762 if (reg_old_renumber[i] == regno)
3765 alter_reg (i, reg_old_renumber[i]);
3766 reg_old_renumber[i] = regno;
3770 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3772 fprintf (dump_file, " Register %d now in %d.\n\n",
3773 i, reg_renumber[i]);
3777 return something_changed;
3780 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3783 scan_paradoxical_subregs (rtx x)
3787 enum rtx_code code = GET_CODE (x);
3797 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3805 if (REG_P (SUBREG_REG (x))
3806 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3807 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3808 = GET_MODE_SIZE (GET_MODE (x));
3815 fmt = GET_RTX_FORMAT (code);
3816 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3819 scan_paradoxical_subregs (XEXP (x, i));
3820 else if (fmt[i] == 'E')
3823 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3824 scan_paradoxical_subregs (XVECEXP (x, i, j));
3829 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3830 examine all of the reload insns between PREV and NEXT exclusive, and
3831 annotate all that may trap. */
3834 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
3836 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
3837 unsigned int trap_count;
3843 if (may_trap_p (PATTERN (insn)))
3847 remove_note (insn, note);
3851 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
3852 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
3856 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
3860 /* Reload pseudo-registers into hard regs around each insn as needed.
3861 Additional register load insns are output before the insn that needs it
3862 and perhaps store insns after insns that modify the reloaded pseudo reg.
3864 reg_last_reload_reg and reg_reloaded_contents keep track of
3865 which registers are already available in reload registers.
3866 We update these for the reloads that we perform,
3867 as the insns are scanned. */
3870 reload_as_needed (int live_known)
3872 struct insn_chain *chain;
3873 #if defined (AUTO_INC_DEC)
3878 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
3879 memset (spill_reg_store, 0, sizeof spill_reg_store);
3880 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
3881 reg_has_output_reload = XNEWVEC (char, max_regno);
3882 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3883 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
3885 set_initial_elim_offsets ();
3887 for (chain = reload_insn_chain; chain; chain = chain->next)
3890 rtx insn = chain->insn;
3891 rtx old_next = NEXT_INSN (insn);
3893 /* If we pass a label, copy the offsets from the label information
3894 into the current offsets of each elimination. */
3896 set_offsets_for_label (insn);
3898 else if (INSN_P (insn))
3900 rtx oldpat = copy_rtx (PATTERN (insn));
3902 /* If this is a USE and CLOBBER of a MEM, ensure that any
3903 references to eliminable registers have been removed. */
3905 if ((GET_CODE (PATTERN (insn)) == USE
3906 || GET_CODE (PATTERN (insn)) == CLOBBER)
3907 && MEM_P (XEXP (PATTERN (insn), 0)))
3908 XEXP (XEXP (PATTERN (insn), 0), 0)
3909 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3910 GET_MODE (XEXP (PATTERN (insn), 0)),
3913 /* If we need to do register elimination processing, do so.
3914 This might delete the insn, in which case we are done. */
3915 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3917 eliminate_regs_in_insn (insn, 1);
3920 update_eliminable_offsets ();
3925 /* If need_elim is nonzero but need_reload is zero, one might think
3926 that we could simply set n_reloads to 0. However, find_reloads
3927 could have done some manipulation of the insn (such as swapping
3928 commutative operands), and these manipulations are lost during
3929 the first pass for every insn that needs register elimination.
3930 So the actions of find_reloads must be redone here. */
3932 if (! chain->need_elim && ! chain->need_reload
3933 && ! chain->need_operand_change)
3935 /* First find the pseudo regs that must be reloaded for this insn.
3936 This info is returned in the tables reload_... (see reload.h).
3937 Also modify the body of INSN by substituting RELOAD
3938 rtx's for those pseudo regs. */
3941 memset (reg_has_output_reload, 0, max_regno);
3942 CLEAR_HARD_REG_SET (reg_is_output_reload);
3944 find_reloads (insn, 1, spill_indirect_levels, live_known,
3950 rtx next = NEXT_INSN (insn);
3953 prev = PREV_INSN (insn);
3955 /* Now compute which reload regs to reload them into. Perhaps
3956 reusing reload regs from previous insns, or else output
3957 load insns to reload them. Maybe output store insns too.
3958 Record the choices of reload reg in reload_reg_rtx. */
3959 choose_reload_regs (chain);
3961 /* Merge any reloads that we didn't combine for fear of
3962 increasing the number of spill registers needed but now
3963 discover can be safely merged. */
3964 if (SMALL_REGISTER_CLASSES)
3965 merge_assigned_reloads (insn);
3967 /* Generate the insns to reload operands into or out of
3968 their reload regs. */
3969 emit_reload_insns (chain);
3971 /* Substitute the chosen reload regs from reload_reg_rtx
3972 into the insn's body (or perhaps into the bodies of other
3973 load and store insn that we just made for reloading
3974 and that we moved the structure into). */
3975 subst_reloads (insn);
3977 /* Adjust the exception region notes for loads and stores. */
3978 if (flag_non_call_exceptions && !CALL_P (insn))
3979 fixup_eh_region_note (insn, prev, next);
3981 /* If this was an ASM, make sure that all the reload insns
3982 we have generated are valid. If not, give an error
3984 if (asm_noperands (PATTERN (insn)) >= 0)
3985 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3986 if (p != insn && INSN_P (p)
3987 && GET_CODE (PATTERN (p)) != USE
3988 && (recog_memoized (p) < 0
3989 || (extract_insn (p), ! constrain_operands (1))))
3991 error_for_asm (insn,
3992 "%<asm%> operand requires "
3993 "impossible reload");
3998 if (num_eliminable && chain->need_elim)
3999 update_eliminable_offsets ();
4001 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4002 is no longer validly lying around to save a future reload.
4003 Note that this does not detect pseudos that were reloaded
4004 for this insn in order to be stored in
4005 (obeying register constraints). That is correct; such reload
4006 registers ARE still valid. */
4007 note_stores (oldpat, forget_old_reloads_1, NULL);
4009 /* There may have been CLOBBER insns placed after INSN. So scan
4010 between INSN and NEXT and use them to forget old reloads. */
4011 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4012 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4013 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4016 /* Likewise for regs altered by auto-increment in this insn.
4017 REG_INC notes have been changed by reloading:
4018 find_reloads_address_1 records substitutions for them,
4019 which have been performed by subst_reloads above. */
4020 for (i = n_reloads - 1; i >= 0; i--)
4022 rtx in_reg = rld[i].in_reg;
4025 enum rtx_code code = GET_CODE (in_reg);
4026 /* PRE_INC / PRE_DEC will have the reload register ending up
4027 with the same value as the stack slot, but that doesn't
4028 hold true for POST_INC / POST_DEC. Either we have to
4029 convert the memory access to a true POST_INC / POST_DEC,
4030 or we can't use the reload register for inheritance. */
4031 if ((code == POST_INC || code == POST_DEC)
4032 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4033 REGNO (rld[i].reg_rtx))
4034 /* Make sure it is the inc/dec pseudo, and not
4035 some other (e.g. output operand) pseudo. */
4036 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4037 == REGNO (XEXP (in_reg, 0))))
4040 rtx reload_reg = rld[i].reg_rtx;
4041 enum machine_mode mode = GET_MODE (reload_reg);
4045 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4047 /* We really want to ignore REG_INC notes here, so
4048 use PATTERN (p) as argument to reg_set_p . */
4049 if (reg_set_p (reload_reg, PATTERN (p)))
4051 n = count_occurrences (PATTERN (p), reload_reg, 0);
4056 n = validate_replace_rtx (reload_reg,
4057 gen_rtx_fmt_e (code,
4062 /* We must also verify that the constraints
4063 are met after the replacement. */
4066 n = constrain_operands (1);
4070 /* If the constraints were not met, then
4071 undo the replacement. */
4074 validate_replace_rtx (gen_rtx_fmt_e (code,
4087 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4089 /* Mark this as having an output reload so that the
4090 REG_INC processing code below won't invalidate
4091 the reload for inheritance. */
4092 SET_HARD_REG_BIT (reg_is_output_reload,
4093 REGNO (reload_reg));
4094 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4097 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4100 else if ((code == PRE_INC || code == PRE_DEC)
4101 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4102 REGNO (rld[i].reg_rtx))
4103 /* Make sure it is the inc/dec pseudo, and not
4104 some other (e.g. output operand) pseudo. */
4105 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4106 == REGNO (XEXP (in_reg, 0))))
4108 SET_HARD_REG_BIT (reg_is_output_reload,
4109 REGNO (rld[i].reg_rtx));
4110 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4114 /* If a pseudo that got a hard register is auto-incremented,
4115 we must purge records of copying it into pseudos without
4117 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4118 if (REG_NOTE_KIND (x) == REG_INC)
4120 /* See if this pseudo reg was reloaded in this insn.
4121 If so, its last-reload info is still valid
4122 because it is based on this insn's reload. */
4123 for (i = 0; i < n_reloads; i++)
4124 if (rld[i].out == XEXP (x, 0))
4128 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4132 /* A reload reg's contents are unknown after a label. */
4134 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4136 /* Don't assume a reload reg is still good after a call insn
4137 if it is a call-used reg, or if it contains a value that will
4138 be partially clobbered by the call. */
4139 else if (CALL_P (insn))
4141 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4142 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4147 free (reg_last_reload_reg);
4148 free (reg_has_output_reload);
4151 /* Discard all record of any value reloaded from X,
4152 or reloaded in X from someplace else;
4153 unless X is an output reload reg of the current insn.
4155 X may be a hard reg (the reload reg)
4156 or it may be a pseudo reg that was reloaded from. */
4159 forget_old_reloads_1 (rtx x, rtx ignored ATTRIBUTE_UNUSED,
4160 void *data ATTRIBUTE_UNUSED)
4165 /* note_stores does give us subregs of hard regs,
4166 subreg_regno_offset requires a hard reg. */
4167 while (GET_CODE (x) == SUBREG)
4169 /* We ignore the subreg offset when calculating the regno,
4170 because we are using the entire underlying hard register
4180 if (regno >= FIRST_PSEUDO_REGISTER)
4186 nr = hard_regno_nregs[regno][GET_MODE (x)];
4187 /* Storing into a spilled-reg invalidates its contents.
4188 This can happen if a block-local pseudo is allocated to that reg
4189 and it wasn't spilled because this block's total need is 0.
4190 Then some insn might have an optional reload and use this reg. */
4191 for (i = 0; i < nr; i++)
4192 /* But don't do this if the reg actually serves as an output
4193 reload reg in the current instruction. */
4195 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4197 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4198 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4199 spill_reg_store[regno + i] = 0;
4203 /* Since value of X has changed,
4204 forget any value previously copied from it. */
4207 /* But don't forget a copy if this is the output reload
4208 that establishes the copy's validity. */
4209 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4210 reg_last_reload_reg[regno + nr] = 0;
4213 /* The following HARD_REG_SETs indicate when each hard register is
4214 used for a reload of various parts of the current insn. */
4216 /* If reg is unavailable for all reloads. */
4217 static HARD_REG_SET reload_reg_unavailable;
4218 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4219 static HARD_REG_SET reload_reg_used;
4220 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4221 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4222 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4223 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4224 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4225 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4226 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4227 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4228 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4229 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4230 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4231 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4232 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4233 static HARD_REG_SET reload_reg_used_in_op_addr;
4234 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4235 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4236 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4237 static HARD_REG_SET reload_reg_used_in_insn;
4238 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4239 static HARD_REG_SET reload_reg_used_in_other_addr;
4241 /* If reg is in use as a reload reg for any sort of reload. */
4242 static HARD_REG_SET reload_reg_used_at_all;
4244 /* If reg is use as an inherited reload. We just mark the first register
4246 static HARD_REG_SET reload_reg_used_for_inherit;
4248 /* Records which hard regs are used in any way, either as explicit use or
4249 by being allocated to a pseudo during any point of the current insn. */
4250 static HARD_REG_SET reg_used_in_insn;
4252 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4253 TYPE. MODE is used to indicate how many consecutive regs are
4257 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4258 enum machine_mode mode)
4260 unsigned int nregs = hard_regno_nregs[regno][mode];
4263 for (i = regno; i < nregs + regno; i++)
4268 SET_HARD_REG_BIT (reload_reg_used, i);
4271 case RELOAD_FOR_INPUT_ADDRESS:
4272 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4275 case RELOAD_FOR_INPADDR_ADDRESS:
4276 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4279 case RELOAD_FOR_OUTPUT_ADDRESS:
4280 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4283 case RELOAD_FOR_OUTADDR_ADDRESS:
4284 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4287 case RELOAD_FOR_OPERAND_ADDRESS:
4288 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4291 case RELOAD_FOR_OPADDR_ADDR:
4292 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4295 case RELOAD_FOR_OTHER_ADDRESS:
4296 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4299 case RELOAD_FOR_INPUT:
4300 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4303 case RELOAD_FOR_OUTPUT:
4304 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4307 case RELOAD_FOR_INSN:
4308 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4312 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4316 /* Similarly, but show REGNO is no longer in use for a reload. */
4319 clear_reload_reg_in_use (unsigned int regno, int opnum,
4320 enum reload_type type, enum machine_mode mode)
4322 unsigned int nregs = hard_regno_nregs[regno][mode];
4323 unsigned int start_regno, end_regno, r;
4325 /* A complication is that for some reload types, inheritance might
4326 allow multiple reloads of the same types to share a reload register.
4327 We set check_opnum if we have to check only reloads with the same
4328 operand number, and check_any if we have to check all reloads. */
4329 int check_opnum = 0;
4331 HARD_REG_SET *used_in_set;
4336 used_in_set = &reload_reg_used;
4339 case RELOAD_FOR_INPUT_ADDRESS:
4340 used_in_set = &reload_reg_used_in_input_addr[opnum];
4343 case RELOAD_FOR_INPADDR_ADDRESS:
4345 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4348 case RELOAD_FOR_OUTPUT_ADDRESS:
4349 used_in_set = &reload_reg_used_in_output_addr[opnum];
4352 case RELOAD_FOR_OUTADDR_ADDRESS:
4354 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4357 case RELOAD_FOR_OPERAND_ADDRESS:
4358 used_in_set = &reload_reg_used_in_op_addr;
4361 case RELOAD_FOR_OPADDR_ADDR:
4363 used_in_set = &reload_reg_used_in_op_addr_reload;
4366 case RELOAD_FOR_OTHER_ADDRESS:
4367 used_in_set = &reload_reg_used_in_other_addr;
4371 case RELOAD_FOR_INPUT:
4372 used_in_set = &reload_reg_used_in_input[opnum];
4375 case RELOAD_FOR_OUTPUT:
4376 used_in_set = &reload_reg_used_in_output[opnum];
4379 case RELOAD_FOR_INSN:
4380 used_in_set = &reload_reg_used_in_insn;
4385 /* We resolve conflicts with remaining reloads of the same type by
4386 excluding the intervals of reload registers by them from the
4387 interval of freed reload registers. Since we only keep track of
4388 one set of interval bounds, we might have to exclude somewhat
4389 more than what would be necessary if we used a HARD_REG_SET here.
4390 But this should only happen very infrequently, so there should
4391 be no reason to worry about it. */
4393 start_regno = regno;
4394 end_regno = regno + nregs;
4395 if (check_opnum || check_any)
4397 for (i = n_reloads - 1; i >= 0; i--)
4399 if (rld[i].when_needed == type
4400 && (check_any || rld[i].opnum == opnum)
4403 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4404 unsigned int conflict_end
4406 + hard_regno_nregs[conflict_start][rld[i].mode]);
4408 /* If there is an overlap with the first to-be-freed register,
4409 adjust the interval start. */
4410 if (conflict_start <= start_regno && conflict_end > start_regno)
4411 start_regno = conflict_end;
4412 /* Otherwise, if there is a conflict with one of the other
4413 to-be-freed registers, adjust the interval end. */
4414 if (conflict_start > start_regno && conflict_start < end_regno)
4415 end_regno = conflict_start;
4420 for (r = start_regno; r < end_regno; r++)
4421 CLEAR_HARD_REG_BIT (*used_in_set, r);
4424 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4425 specified by OPNUM and TYPE. */
4428 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4432 /* In use for a RELOAD_OTHER means it's not available for anything. */
4433 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4434 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4440 /* In use for anything means we can't use it for RELOAD_OTHER. */
4441 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4442 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4443 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4444 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4447 for (i = 0; i < reload_n_operands; i++)
4448 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4449 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4450 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4451 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4452 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4453 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4458 case RELOAD_FOR_INPUT:
4459 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4460 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4463 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4466 /* If it is used for some other input, can't use it. */
4467 for (i = 0; i < reload_n_operands; i++)
4468 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4471 /* If it is used in a later operand's address, can't use it. */
4472 for (i = opnum + 1; i < reload_n_operands; i++)
4473 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4474 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4479 case RELOAD_FOR_INPUT_ADDRESS:
4480 /* Can't use a register if it is used for an input address for this
4481 operand or used as an input in an earlier one. */
4482 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4483 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4486 for (i = 0; i < opnum; i++)
4487 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4492 case RELOAD_FOR_INPADDR_ADDRESS:
4493 /* Can't use a register if it is used for an input address
4494 for this operand or used as an input in an earlier
4496 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4499 for (i = 0; i < opnum; i++)
4500 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4505 case RELOAD_FOR_OUTPUT_ADDRESS:
4506 /* Can't use a register if it is used for an output address for this
4507 operand or used as an output in this or a later operand. Note
4508 that multiple output operands are emitted in reverse order, so
4509 the conflicting ones are those with lower indices. */
4510 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4513 for (i = 0; i <= opnum; i++)
4514 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4519 case RELOAD_FOR_OUTADDR_ADDRESS:
4520 /* Can't use a register if it is used for an output address
4521 for this operand or used as an output in this or a
4522 later operand. Note that multiple output operands are
4523 emitted in reverse order, so the conflicting ones are
4524 those with lower indices. */
4525 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4528 for (i = 0; i <= opnum; i++)
4529 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4534 case RELOAD_FOR_OPERAND_ADDRESS:
4535 for (i = 0; i < reload_n_operands; i++)
4536 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4539 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4540 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4542 case RELOAD_FOR_OPADDR_ADDR:
4543 for (i = 0; i < reload_n_operands; i++)
4544 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4547 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4549 case RELOAD_FOR_OUTPUT:
4550 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4551 outputs, or an operand address for this or an earlier output.
4552 Note that multiple output operands are emitted in reverse order,
4553 so the conflicting ones are those with higher indices. */
4554 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4557 for (i = 0; i < reload_n_operands; i++)
4558 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4561 for (i = opnum; i < reload_n_operands; i++)
4562 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4563 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4568 case RELOAD_FOR_INSN:
4569 for (i = 0; i < reload_n_operands; i++)
4570 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4574 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4575 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4577 case RELOAD_FOR_OTHER_ADDRESS:
4578 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4585 /* Return 1 if the value in reload reg REGNO, as used by a reload
4586 needed for the part of the insn specified by OPNUM and TYPE,
4587 is still available in REGNO at the end of the insn.
4589 We can assume that the reload reg was already tested for availability
4590 at the time it is needed, and we should not check this again,
4591 in case the reg has already been marked in use. */
4594 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4601 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4602 its value must reach the end. */
4605 /* If this use is for part of the insn,
4606 its value reaches if no subsequent part uses the same register.
4607 Just like the above function, don't try to do this with lots
4610 case RELOAD_FOR_OTHER_ADDRESS:
4611 /* Here we check for everything else, since these don't conflict
4612 with anything else and everything comes later. */
4614 for (i = 0; i < reload_n_operands; i++)
4615 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4616 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4617 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4618 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4619 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4620 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4623 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4624 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4625 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4626 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4628 case RELOAD_FOR_INPUT_ADDRESS:
4629 case RELOAD_FOR_INPADDR_ADDRESS:
4630 /* Similar, except that we check only for this and subsequent inputs
4631 and the address of only subsequent inputs and we do not need
4632 to check for RELOAD_OTHER objects since they are known not to
4635 for (i = opnum; i < reload_n_operands; i++)
4636 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4639 for (i = opnum + 1; i < reload_n_operands; i++)
4640 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4641 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4644 for (i = 0; i < reload_n_operands; i++)
4645 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4646 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4647 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4650 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4653 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4654 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4655 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4657 case RELOAD_FOR_INPUT:
4658 /* Similar to input address, except we start at the next operand for
4659 both input and input address and we do not check for
4660 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4663 for (i = opnum + 1; i < reload_n_operands; i++)
4664 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4665 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4666 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4669 /* ... fall through ... */
4671 case RELOAD_FOR_OPERAND_ADDRESS:
4672 /* Check outputs and their addresses. */
4674 for (i = 0; i < reload_n_operands; i++)
4675 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4676 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4677 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4680 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4682 case RELOAD_FOR_OPADDR_ADDR:
4683 for (i = 0; i < reload_n_operands; i++)
4684 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4685 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4686 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4689 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4690 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4691 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4693 case RELOAD_FOR_INSN:
4694 /* These conflict with other outputs with RELOAD_OTHER. So
4695 we need only check for output addresses. */
4697 opnum = reload_n_operands;
4699 /* ... fall through ... */
4701 case RELOAD_FOR_OUTPUT:
4702 case RELOAD_FOR_OUTPUT_ADDRESS:
4703 case RELOAD_FOR_OUTADDR_ADDRESS:
4704 /* We already know these can't conflict with a later output. So the
4705 only thing to check are later output addresses.
4706 Note that multiple output operands are emitted in reverse order,
4707 so the conflicting ones are those with lower indices. */
4708 for (i = 0; i < opnum; i++)
4709 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4710 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4720 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4723 This function uses the same algorithm as reload_reg_free_p above. */
4726 reloads_conflict (int r1, int r2)
4728 enum reload_type r1_type = rld[r1].when_needed;
4729 enum reload_type r2_type = rld[r2].when_needed;
4730 int r1_opnum = rld[r1].opnum;
4731 int r2_opnum = rld[r2].opnum;
4733 /* RELOAD_OTHER conflicts with everything. */
4734 if (r2_type == RELOAD_OTHER)
4737 /* Otherwise, check conflicts differently for each type. */
4741 case RELOAD_FOR_INPUT:
4742 return (r2_type == RELOAD_FOR_INSN
4743 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4744 || r2_type == RELOAD_FOR_OPADDR_ADDR
4745 || r2_type == RELOAD_FOR_INPUT
4746 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4747 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4748 && r2_opnum > r1_opnum));
4750 case RELOAD_FOR_INPUT_ADDRESS:
4751 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4752 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4754 case RELOAD_FOR_INPADDR_ADDRESS:
4755 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4756 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4758 case RELOAD_FOR_OUTPUT_ADDRESS:
4759 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4760 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4762 case RELOAD_FOR_OUTADDR_ADDRESS:
4763 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4764 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
4766 case RELOAD_FOR_OPERAND_ADDRESS:
4767 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4768 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4770 case RELOAD_FOR_OPADDR_ADDR:
4771 return (r2_type == RELOAD_FOR_INPUT
4772 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4774 case RELOAD_FOR_OUTPUT:
4775 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4776 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4777 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4778 && r2_opnum >= r1_opnum));
4780 case RELOAD_FOR_INSN:
4781 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4782 || r2_type == RELOAD_FOR_INSN
4783 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4785 case RELOAD_FOR_OTHER_ADDRESS:
4786 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4796 /* Indexed by reload number, 1 if incoming value
4797 inherited from previous insns. */
4798 static char reload_inherited[MAX_RELOADS];
4800 /* For an inherited reload, this is the insn the reload was inherited from,
4801 if we know it. Otherwise, this is 0. */
4802 static rtx reload_inheritance_insn[MAX_RELOADS];
4804 /* If nonzero, this is a place to get the value of the reload,
4805 rather than using reload_in. */
4806 static rtx reload_override_in[MAX_RELOADS];
4808 /* For each reload, the hard register number of the register used,
4809 or -1 if we did not need a register for this reload. */
4810 static int reload_spill_index[MAX_RELOADS];
4812 /* Subroutine of free_for_value_p, used to check a single register.
4813 START_REGNO is the starting regno of the full reload register
4814 (possibly comprising multiple hard registers) that we are considering. */
4817 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
4818 enum reload_type type, rtx value, rtx out,
4819 int reloadnum, int ignore_address_reloads)
4822 /* Set if we see an input reload that must not share its reload register
4823 with any new earlyclobber, but might otherwise share the reload
4824 register with an output or input-output reload. */
4825 int check_earlyclobber = 0;
4829 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4832 if (out == const0_rtx)
4838 /* We use some pseudo 'time' value to check if the lifetimes of the
4839 new register use would overlap with the one of a previous reload
4840 that is not read-only or uses a different value.
4841 The 'time' used doesn't have to be linear in any shape or form, just
4843 Some reload types use different 'buckets' for each operand.
4844 So there are MAX_RECOG_OPERANDS different time values for each
4846 We compute TIME1 as the time when the register for the prospective
4847 new reload ceases to be live, and TIME2 for each existing
4848 reload as the time when that the reload register of that reload
4850 Where there is little to be gained by exact lifetime calculations,
4851 we just make conservative assumptions, i.e. a longer lifetime;
4852 this is done in the 'default:' cases. */
4855 case RELOAD_FOR_OTHER_ADDRESS:
4856 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4857 time1 = copy ? 0 : 1;
4860 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4862 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4863 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4864 respectively, to the time values for these, we get distinct time
4865 values. To get distinct time values for each operand, we have to
4866 multiply opnum by at least three. We round that up to four because
4867 multiply by four is often cheaper. */
4868 case RELOAD_FOR_INPADDR_ADDRESS:
4869 time1 = opnum * 4 + 2;
4871 case RELOAD_FOR_INPUT_ADDRESS:
4872 time1 = opnum * 4 + 3;
4874 case RELOAD_FOR_INPUT:
4875 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4876 executes (inclusive). */
4877 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4879 case RELOAD_FOR_OPADDR_ADDR:
4881 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4882 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4884 case RELOAD_FOR_OPERAND_ADDRESS:
4885 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4887 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4889 case RELOAD_FOR_OUTADDR_ADDRESS:
4890 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4892 case RELOAD_FOR_OUTPUT_ADDRESS:
4893 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4896 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4899 for (i = 0; i < n_reloads; i++)
4901 rtx reg = rld[i].reg_rtx;
4902 if (reg && REG_P (reg)
4903 && ((unsigned) regno - true_regnum (reg)
4904 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
4907 rtx other_input = rld[i].in;
4909 /* If the other reload loads the same input value, that
4910 will not cause a conflict only if it's loading it into
4911 the same register. */
4912 if (true_regnum (reg) != start_regno)
4913 other_input = NULL_RTX;
4914 if (! other_input || ! rtx_equal_p (other_input, value)
4915 || rld[i].out || out)
4918 switch (rld[i].when_needed)
4920 case RELOAD_FOR_OTHER_ADDRESS:
4923 case RELOAD_FOR_INPADDR_ADDRESS:
4924 /* find_reloads makes sure that a
4925 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4926 by at most one - the first -
4927 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4928 address reload is inherited, the address address reload
4929 goes away, so we can ignore this conflict. */
4930 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4931 && ignore_address_reloads
4932 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4933 Then the address address is still needed to store
4934 back the new address. */
4935 && ! rld[reloadnum].out)
4937 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4938 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4940 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4941 && ignore_address_reloads
4942 /* Unless we are reloading an auto_inc expression. */
4943 && ! rld[reloadnum].out)
4945 time2 = rld[i].opnum * 4 + 2;
4947 case RELOAD_FOR_INPUT_ADDRESS:
4948 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4949 && ignore_address_reloads
4950 && ! rld[reloadnum].out)
4952 time2 = rld[i].opnum * 4 + 3;
4954 case RELOAD_FOR_INPUT:
4955 time2 = rld[i].opnum * 4 + 4;
4956 check_earlyclobber = 1;
4958 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4959 == MAX_RECOG_OPERAND * 4 */
4960 case RELOAD_FOR_OPADDR_ADDR:
4961 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4962 && ignore_address_reloads
4963 && ! rld[reloadnum].out)
4965 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4967 case RELOAD_FOR_OPERAND_ADDRESS:
4968 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4969 check_earlyclobber = 1;
4971 case RELOAD_FOR_INSN:
4972 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4974 case RELOAD_FOR_OUTPUT:
4975 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4976 instruction is executed. */
4977 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4979 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4980 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4982 case RELOAD_FOR_OUTADDR_ADDRESS:
4983 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4984 && ignore_address_reloads
4985 && ! rld[reloadnum].out)
4987 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4989 case RELOAD_FOR_OUTPUT_ADDRESS:
4990 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4993 /* If there is no conflict in the input part, handle this
4994 like an output reload. */
4995 if (! rld[i].in || rtx_equal_p (other_input, value))
4997 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4998 /* Earlyclobbered outputs must conflict with inputs. */
4999 if (earlyclobber_operand_p (rld[i].out))
5000 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5005 /* RELOAD_OTHER might be live beyond instruction execution,
5006 but this is not obvious when we set time2 = 1. So check
5007 here if there might be a problem with the new reload
5008 clobbering the register used by the RELOAD_OTHER. */
5016 && (! rld[i].in || rld[i].out
5017 || ! rtx_equal_p (other_input, value)))
5018 || (out && rld[reloadnum].out_reg
5019 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5025 /* Earlyclobbered outputs must conflict with inputs. */
5026 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5032 /* Return 1 if the value in reload reg REGNO, as used by a reload
5033 needed for the part of the insn specified by OPNUM and TYPE,
5034 may be used to load VALUE into it.
5036 MODE is the mode in which the register is used, this is needed to
5037 determine how many hard regs to test.
5039 Other read-only reloads with the same value do not conflict
5040 unless OUT is nonzero and these other reloads have to live while
5041 output reloads live.
5042 If OUT is CONST0_RTX, this is a special case: it means that the
5043 test should not be for using register REGNO as reload register, but
5044 for copying from register REGNO into the reload register.
5046 RELOADNUM is the number of the reload we want to load this value for;
5047 a reload does not conflict with itself.
5049 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5050 reloads that load an address for the very reload we are considering.
5052 The caller has to make sure that there is no conflict with the return
5056 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5057 enum reload_type type, rtx value, rtx out, int reloadnum,
5058 int ignore_address_reloads)
5060 int nregs = hard_regno_nregs[regno][mode];
5062 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5063 value, out, reloadnum,
5064 ignore_address_reloads))
5069 /* Return nonzero if the rtx X is invariant over the current function. */
5070 /* ??? Actually, the places where we use this expect exactly what is
5071 tested here, and not everything that is function invariant. In
5072 particular, the frame pointer and arg pointer are special cased;
5073 pic_offset_table_rtx is not, and we must not spill these things to
5077 function_invariant_p (rtx x)
5081 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5083 if (GET_CODE (x) == PLUS
5084 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5085 && CONSTANT_P (XEXP (x, 1)))
5090 /* Determine whether the reload reg X overlaps any rtx'es used for
5091 overriding inheritance. Return nonzero if so. */
5094 conflicts_with_override (rtx x)
5097 for (i = 0; i < n_reloads; i++)
5098 if (reload_override_in[i]
5099 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5104 /* Give an error message saying we failed to find a reload for INSN,
5105 and clear out reload R. */
5107 failed_reload (rtx insn, int r)
5109 if (asm_noperands (PATTERN (insn)) < 0)
5110 /* It's the compiler's fault. */
5111 fatal_insn ("could not find a spill register", insn);
5113 /* It's the user's fault; the operand's mode and constraint
5114 don't match. Disable this reload so we don't crash in final. */
5115 error_for_asm (insn,
5116 "%<asm%> operand constraint incompatible with operand size");
5120 rld[r].optional = 1;
5121 rld[r].secondary_p = 1;
5124 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5125 for reload R. If it's valid, get an rtx for it. Return nonzero if
5128 set_reload_reg (int i, int r)
5131 rtx reg = spill_reg_rtx[i];
5133 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5134 spill_reg_rtx[i] = reg
5135 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5137 regno = true_regnum (reg);
5139 /* Detect when the reload reg can't hold the reload mode.
5140 This used to be one `if', but Sequent compiler can't handle that. */
5141 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5143 enum machine_mode test_mode = VOIDmode;
5145 test_mode = GET_MODE (rld[r].in);
5146 /* If rld[r].in has VOIDmode, it means we will load it
5147 in whatever mode the reload reg has: to wit, rld[r].mode.
5148 We have already tested that for validity. */
5149 /* Aside from that, we need to test that the expressions
5150 to reload from or into have modes which are valid for this
5151 reload register. Otherwise the reload insns would be invalid. */
5152 if (! (rld[r].in != 0 && test_mode != VOIDmode
5153 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5154 if (! (rld[r].out != 0
5155 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5157 /* The reg is OK. */
5160 /* Mark as in use for this insn the reload regs we use
5162 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5163 rld[r].when_needed, rld[r].mode);
5165 rld[r].reg_rtx = reg;
5166 reload_spill_index[r] = spill_regs[i];
5173 /* Find a spill register to use as a reload register for reload R.
5174 LAST_RELOAD is nonzero if this is the last reload for the insn being
5177 Set rld[R].reg_rtx to the register allocated.
5179 We return 1 if successful, or 0 if we couldn't find a spill reg and
5180 we didn't change anything. */
5183 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5188 /* If we put this reload ahead, thinking it is a group,
5189 then insist on finding a group. Otherwise we can grab a
5190 reg that some other reload needs.
5191 (That can happen when we have a 68000 DATA_OR_FP_REG
5192 which is a group of data regs or one fp reg.)
5193 We need not be so restrictive if there are no more reloads
5196 ??? Really it would be nicer to have smarter handling
5197 for that kind of reg class, where a problem like this is normal.
5198 Perhaps those classes should be avoided for reloading
5199 by use of more alternatives. */
5201 int force_group = rld[r].nregs > 1 && ! last_reload;
5203 /* If we want a single register and haven't yet found one,
5204 take any reg in the right class and not in use.
5205 If we want a consecutive group, here is where we look for it.
5207 We use two passes so we can first look for reload regs to
5208 reuse, which are already in use for other reloads in this insn,
5209 and only then use additional registers.
5210 I think that maximizing reuse is needed to make sure we don't
5211 run out of reload regs. Suppose we have three reloads, and
5212 reloads A and B can share regs. These need two regs.
5213 Suppose A and B are given different regs.
5214 That leaves none for C. */
5215 for (pass = 0; pass < 2; pass++)
5217 /* I is the index in spill_regs.
5218 We advance it round-robin between insns to use all spill regs
5219 equally, so that inherited reloads have a chance
5220 of leapfrogging each other. */
5224 for (count = 0; count < n_spills; count++)
5226 int class = (int) rld[r].class;
5232 regnum = spill_regs[i];
5234 if ((reload_reg_free_p (regnum, rld[r].opnum,
5237 /* We check reload_reg_used to make sure we
5238 don't clobber the return register. */
5239 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5240 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5241 rld[r].when_needed, rld[r].in,
5243 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5244 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5245 /* Look first for regs to share, then for unshared. But
5246 don't share regs used for inherited reloads; they are
5247 the ones we want to preserve. */
5249 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5251 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5254 int nr = hard_regno_nregs[regnum][rld[r].mode];
5255 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5256 (on 68000) got us two FP regs. If NR is 1,
5257 we would reject both of them. */
5260 /* If we need only one reg, we have already won. */
5263 /* But reject a single reg if we demand a group. */
5268 /* Otherwise check that as many consecutive regs as we need
5269 are available here. */
5272 int regno = regnum + nr - 1;
5273 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5274 && spill_reg_order[regno] >= 0
5275 && reload_reg_free_p (regno, rld[r].opnum,
5276 rld[r].when_needed)))
5285 /* If we found something on pass 1, omit pass 2. */
5286 if (count < n_spills)
5290 /* We should have found a spill register by now. */
5291 if (count >= n_spills)
5294 /* I is the index in SPILL_REG_RTX of the reload register we are to
5295 allocate. Get an rtx for it and find its register number. */
5297 return set_reload_reg (i, r);
5300 /* Initialize all the tables needed to allocate reload registers.
5301 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5302 is the array we use to restore the reg_rtx field for every reload. */
5305 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5309 for (i = 0; i < n_reloads; i++)
5310 rld[i].reg_rtx = save_reload_reg_rtx[i];
5312 memset (reload_inherited, 0, MAX_RELOADS);
5313 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5314 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5316 CLEAR_HARD_REG_SET (reload_reg_used);
5317 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5318 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5319 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5320 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5321 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5323 CLEAR_HARD_REG_SET (reg_used_in_insn);
5326 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5327 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5328 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5329 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5330 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5331 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5334 for (i = 0; i < reload_n_operands; i++)
5336 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5337 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5338 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5339 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5340 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5341 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5344 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5346 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5348 for (i = 0; i < n_reloads; i++)
5349 /* If we have already decided to use a certain register,
5350 don't use it in another way. */
5352 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5353 rld[i].when_needed, rld[i].mode);
5356 /* Assign hard reg targets for the pseudo-registers we must reload
5357 into hard regs for this insn.
5358 Also output the instructions to copy them in and out of the hard regs.
5360 For machines with register classes, we are responsible for
5361 finding a reload reg in the proper class. */
5364 choose_reload_regs (struct insn_chain *chain)
5366 rtx insn = chain->insn;
5368 unsigned int max_group_size = 1;
5369 enum reg_class group_class = NO_REGS;
5370 int pass, win, inheritance;
5372 rtx save_reload_reg_rtx[MAX_RELOADS];
5374 /* In order to be certain of getting the registers we need,
5375 we must sort the reloads into order of increasing register class.
5376 Then our grabbing of reload registers will parallel the process
5377 that provided the reload registers.
5379 Also note whether any of the reloads wants a consecutive group of regs.
5380 If so, record the maximum size of the group desired and what
5381 register class contains all the groups needed by this insn. */
5383 for (j = 0; j < n_reloads; j++)
5385 reload_order[j] = j;
5386 reload_spill_index[j] = -1;
5388 if (rld[j].nregs > 1)
5390 max_group_size = MAX (rld[j].nregs, max_group_size);
5392 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5395 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5399 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5401 /* If -O, try first with inheritance, then turning it off.
5402 If not -O, don't do inheritance.
5403 Using inheritance when not optimizing leads to paradoxes
5404 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5405 because one side of the comparison might be inherited. */
5407 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5409 choose_reload_regs_init (chain, save_reload_reg_rtx);
5411 /* Process the reloads in order of preference just found.
5412 Beyond this point, subregs can be found in reload_reg_rtx.
5414 This used to look for an existing reloaded home for all of the
5415 reloads, and only then perform any new reloads. But that could lose
5416 if the reloads were done out of reg-class order because a later
5417 reload with a looser constraint might have an old home in a register
5418 needed by an earlier reload with a tighter constraint.
5420 To solve this, we make two passes over the reloads, in the order
5421 described above. In the first pass we try to inherit a reload
5422 from a previous insn. If there is a later reload that needs a
5423 class that is a proper subset of the class being processed, we must
5424 also allocate a spill register during the first pass.
5426 Then make a second pass over the reloads to allocate any reloads
5427 that haven't been given registers yet. */
5429 for (j = 0; j < n_reloads; j++)
5431 int r = reload_order[j];
5432 rtx search_equiv = NULL_RTX;
5434 /* Ignore reloads that got marked inoperative. */
5435 if (rld[r].out == 0 && rld[r].in == 0
5436 && ! rld[r].secondary_p)
5439 /* If find_reloads chose to use reload_in or reload_out as a reload
5440 register, we don't need to chose one. Otherwise, try even if it
5441 found one since we might save an insn if we find the value lying
5443 Try also when reload_in is a pseudo without a hard reg. */
5444 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5445 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5446 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5447 && !MEM_P (rld[r].in)
5448 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5451 #if 0 /* No longer needed for correct operation.
5452 It might give better code, or might not; worth an experiment? */
5453 /* If this is an optional reload, we can't inherit from earlier insns
5454 until we are sure that any non-optional reloads have been allocated.
5455 The following code takes advantage of the fact that optional reloads
5456 are at the end of reload_order. */
5457 if (rld[r].optional != 0)
5458 for (i = 0; i < j; i++)
5459 if ((rld[reload_order[i]].out != 0
5460 || rld[reload_order[i]].in != 0
5461 || rld[reload_order[i]].secondary_p)
5462 && ! rld[reload_order[i]].optional
5463 && rld[reload_order[i]].reg_rtx == 0)
5464 allocate_reload_reg (chain, reload_order[i], 0);
5467 /* First see if this pseudo is already available as reloaded
5468 for a previous insn. We cannot try to inherit for reloads
5469 that are smaller than the maximum number of registers needed
5470 for groups unless the register we would allocate cannot be used
5473 We could check here to see if this is a secondary reload for
5474 an object that is already in a register of the desired class.
5475 This would avoid the need for the secondary reload register.
5476 But this is complex because we can't easily determine what
5477 objects might want to be loaded via this reload. So let a
5478 register be allocated here. In `emit_reload_insns' we suppress
5479 one of the loads in the case described above. */
5485 enum machine_mode mode = VOIDmode;
5489 else if (REG_P (rld[r].in))
5491 regno = REGNO (rld[r].in);
5492 mode = GET_MODE (rld[r].in);
5494 else if (REG_P (rld[r].in_reg))
5496 regno = REGNO (rld[r].in_reg);
5497 mode = GET_MODE (rld[r].in_reg);
5499 else if (GET_CODE (rld[r].in_reg) == SUBREG
5500 && REG_P (SUBREG_REG (rld[r].in_reg)))
5502 byte = SUBREG_BYTE (rld[r].in_reg);
5503 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5504 if (regno < FIRST_PSEUDO_REGISTER)
5505 regno = subreg_regno (rld[r].in_reg);
5506 mode = GET_MODE (rld[r].in_reg);
5509 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5510 && REG_P (XEXP (rld[r].in_reg, 0)))
5512 regno = REGNO (XEXP (rld[r].in_reg, 0));
5513 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5514 rld[r].out = rld[r].in;
5518 /* This won't work, since REGNO can be a pseudo reg number.
5519 Also, it takes much more hair to keep track of all the things
5520 that can invalidate an inherited reload of part of a pseudoreg. */
5521 else if (GET_CODE (rld[r].in) == SUBREG
5522 && REG_P (SUBREG_REG (rld[r].in)))
5523 regno = subreg_regno (rld[r].in);
5526 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5528 enum reg_class class = rld[r].class, last_class;
5529 rtx last_reg = reg_last_reload_reg[regno];
5530 enum machine_mode need_mode;
5532 i = REGNO (last_reg);
5533 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5534 last_class = REGNO_REG_CLASS (i);
5540 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5541 + byte * BITS_PER_UNIT,
5542 GET_MODE_CLASS (mode));
5544 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5545 >= GET_MODE_SIZE (need_mode))
5546 #ifdef CANNOT_CHANGE_MODE_CLASS
5547 /* Verify that the register in "i" can be obtained
5549 && !REG_CANNOT_CHANGE_MODE_P (REGNO (last_reg),
5550 GET_MODE (last_reg),
5553 && reg_reloaded_contents[i] == regno
5554 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5555 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5556 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5557 /* Even if we can't use this register as a reload
5558 register, we might use it for reload_override_in,
5559 if copying it to the desired class is cheap
5561 || ((REGISTER_MOVE_COST (mode, last_class, class)
5562 < MEMORY_MOVE_COST (mode, class, 1))
5563 && (secondary_reload_class (1, class, mode,
5566 #ifdef SECONDARY_MEMORY_NEEDED
5567 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5572 && (rld[r].nregs == max_group_size
5573 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5575 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5576 rld[r].when_needed, rld[r].in,
5579 /* If a group is needed, verify that all the subsequent
5580 registers still have their values intact. */
5581 int nr = hard_regno_nregs[i][rld[r].mode];
5584 for (k = 1; k < nr; k++)
5585 if (reg_reloaded_contents[i + k] != regno
5586 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5594 last_reg = (GET_MODE (last_reg) == mode
5595 ? last_reg : gen_rtx_REG (mode, i));
5598 for (k = 0; k < nr; k++)
5599 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5602 /* We found a register that contains the
5603 value we need. If this register is the
5604 same as an `earlyclobber' operand of the
5605 current insn, just mark it as a place to
5606 reload from since we can't use it as the
5607 reload register itself. */
5609 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5610 if (reg_overlap_mentioned_for_reload_p
5611 (reg_last_reload_reg[regno],
5612 reload_earlyclobbers[i1]))
5615 if (i1 != n_earlyclobbers
5616 || ! (free_for_value_p (i, rld[r].mode,
5618 rld[r].when_needed, rld[r].in,
5620 /* Don't use it if we'd clobber a pseudo reg. */
5621 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5623 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5624 /* Don't clobber the frame pointer. */
5625 || (i == HARD_FRAME_POINTER_REGNUM
5626 && frame_pointer_needed
5628 /* Don't really use the inherited spill reg
5629 if we need it wider than we've got it. */
5630 || (GET_MODE_SIZE (rld[r].mode)
5631 > GET_MODE_SIZE (mode))
5634 /* If find_reloads chose reload_out as reload
5635 register, stay with it - that leaves the
5636 inherited register for subsequent reloads. */
5637 || (rld[r].out && rld[r].reg_rtx
5638 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5640 if (! rld[r].optional)
5642 reload_override_in[r] = last_reg;
5643 reload_inheritance_insn[r]
5644 = reg_reloaded_insn[i];
5650 /* We can use this as a reload reg. */
5651 /* Mark the register as in use for this part of
5653 mark_reload_reg_in_use (i,
5657 rld[r].reg_rtx = last_reg;
5658 reload_inherited[r] = 1;
5659 reload_inheritance_insn[r]
5660 = reg_reloaded_insn[i];
5661 reload_spill_index[r] = i;
5662 for (k = 0; k < nr; k++)
5663 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5671 /* Here's another way to see if the value is already lying around. */
5674 && ! reload_inherited[r]
5676 && (CONSTANT_P (rld[r].in)
5677 || GET_CODE (rld[r].in) == PLUS
5678 || REG_P (rld[r].in)
5679 || MEM_P (rld[r].in))
5680 && (rld[r].nregs == max_group_size
5681 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5682 search_equiv = rld[r].in;
5683 /* If this is an output reload from a simple move insn, look
5684 if an equivalence for the input is available. */
5685 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5687 rtx set = single_set (insn);
5690 && rtx_equal_p (rld[r].out, SET_DEST (set))
5691 && CONSTANT_P (SET_SRC (set)))
5692 search_equiv = SET_SRC (set);
5698 = find_equiv_reg (search_equiv, insn, rld[r].class,
5699 -1, NULL, 0, rld[r].mode);
5705 regno = REGNO (equiv);
5708 /* This must be a SUBREG of a hard register.
5709 Make a new REG since this might be used in an
5710 address and not all machines support SUBREGs
5712 gcc_assert (GET_CODE (equiv) == SUBREG);
5713 regno = subreg_regno (equiv);
5714 equiv = gen_rtx_REG (rld[r].mode, regno);
5715 /* If we choose EQUIV as the reload register, but the
5716 loop below decides to cancel the inheritance, we'll
5717 end up reloading EQUIV in rld[r].mode, not the mode
5718 it had originally. That isn't safe when EQUIV isn't
5719 available as a spill register since its value might
5720 still be live at this point. */
5721 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5722 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5727 /* If we found a spill reg, reject it unless it is free
5728 and of the desired class. */
5732 int bad_for_class = 0;
5733 int max_regno = regno + rld[r].nregs;
5735 for (i = regno; i < max_regno; i++)
5737 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
5739 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5744 && ! free_for_value_p (regno, rld[r].mode,
5745 rld[r].opnum, rld[r].when_needed,
5746 rld[r].in, rld[r].out, r, 1))
5751 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5754 /* We found a register that contains the value we need.
5755 If this register is the same as an `earlyclobber' operand
5756 of the current insn, just mark it as a place to reload from
5757 since we can't use it as the reload register itself. */
5760 for (i = 0; i < n_earlyclobbers; i++)
5761 if (reg_overlap_mentioned_for_reload_p (equiv,
5762 reload_earlyclobbers[i]))
5764 if (! rld[r].optional)
5765 reload_override_in[r] = equiv;
5770 /* If the equiv register we have found is explicitly clobbered
5771 in the current insn, it depends on the reload type if we
5772 can use it, use it for reload_override_in, or not at all.
5773 In particular, we then can't use EQUIV for a
5774 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5778 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
5779 switch (rld[r].when_needed)
5781 case RELOAD_FOR_OTHER_ADDRESS:
5782 case RELOAD_FOR_INPADDR_ADDRESS:
5783 case RELOAD_FOR_INPUT_ADDRESS:
5784 case RELOAD_FOR_OPADDR_ADDR:
5787 case RELOAD_FOR_INPUT:
5788 case RELOAD_FOR_OPERAND_ADDRESS:
5789 if (! rld[r].optional)
5790 reload_override_in[r] = equiv;
5796 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5797 switch (rld[r].when_needed)
5799 case RELOAD_FOR_OTHER_ADDRESS:
5800 case RELOAD_FOR_INPADDR_ADDRESS:
5801 case RELOAD_FOR_INPUT_ADDRESS:
5802 case RELOAD_FOR_OPADDR_ADDR:
5803 case RELOAD_FOR_OPERAND_ADDRESS:
5804 case RELOAD_FOR_INPUT:
5807 if (! rld[r].optional)
5808 reload_override_in[r] = equiv;
5816 /* If we found an equivalent reg, say no code need be generated
5817 to load it, and use it as our reload reg. */
5819 && (regno != HARD_FRAME_POINTER_REGNUM
5820 || !frame_pointer_needed))
5822 int nr = hard_regno_nregs[regno][rld[r].mode];
5824 rld[r].reg_rtx = equiv;
5825 reload_inherited[r] = 1;
5827 /* If reg_reloaded_valid is not set for this register,
5828 there might be a stale spill_reg_store lying around.
5829 We must clear it, since otherwise emit_reload_insns
5830 might delete the store. */
5831 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5832 spill_reg_store[regno] = NULL_RTX;
5833 /* If any of the hard registers in EQUIV are spill
5834 registers, mark them as in use for this insn. */
5835 for (k = 0; k < nr; k++)
5837 i = spill_reg_order[regno + k];
5840 mark_reload_reg_in_use (regno, rld[r].opnum,
5843 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5850 /* If we found a register to use already, or if this is an optional
5851 reload, we are done. */
5852 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5856 /* No longer needed for correct operation. Might or might
5857 not give better code on the average. Want to experiment? */
5859 /* See if there is a later reload that has a class different from our
5860 class that intersects our class or that requires less register
5861 than our reload. If so, we must allocate a register to this
5862 reload now, since that reload might inherit a previous reload
5863 and take the only available register in our class. Don't do this
5864 for optional reloads since they will force all previous reloads
5865 to be allocated. Also don't do this for reloads that have been
5868 for (i = j + 1; i < n_reloads; i++)
5870 int s = reload_order[i];
5872 if ((rld[s].in == 0 && rld[s].out == 0
5873 && ! rld[s].secondary_p)
5877 if ((rld[s].class != rld[r].class
5878 && reg_classes_intersect_p (rld[r].class,
5880 || rld[s].nregs < rld[r].nregs)
5887 allocate_reload_reg (chain, r, j == n_reloads - 1);
5891 /* Now allocate reload registers for anything non-optional that
5892 didn't get one yet. */
5893 for (j = 0; j < n_reloads; j++)
5895 int r = reload_order[j];
5897 /* Ignore reloads that got marked inoperative. */
5898 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5901 /* Skip reloads that already have a register allocated or are
5903 if (rld[r].reg_rtx != 0 || rld[r].optional)
5906 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5910 /* If that loop got all the way, we have won. */
5917 /* Loop around and try without any inheritance. */
5922 /* First undo everything done by the failed attempt
5923 to allocate with inheritance. */
5924 choose_reload_regs_init (chain, save_reload_reg_rtx);
5926 /* Some sanity tests to verify that the reloads found in the first
5927 pass are identical to the ones we have now. */
5928 gcc_assert (chain->n_reloads == n_reloads);
5930 for (i = 0; i < n_reloads; i++)
5932 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5934 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
5935 for (j = 0; j < n_spills; j++)
5936 if (spill_regs[j] == chain->rld[i].regno)
5937 if (! set_reload_reg (j, i))
5938 failed_reload (chain->insn, i);
5942 /* If we thought we could inherit a reload, because it seemed that
5943 nothing else wanted the same reload register earlier in the insn,
5944 verify that assumption, now that all reloads have been assigned.
5945 Likewise for reloads where reload_override_in has been set. */
5947 /* If doing expensive optimizations, do one preliminary pass that doesn't
5948 cancel any inheritance, but removes reloads that have been needed only
5949 for reloads that we know can be inherited. */
5950 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5952 for (j = 0; j < n_reloads; j++)
5954 int r = reload_order[j];
5956 if (reload_inherited[r] && rld[r].reg_rtx)
5957 check_reg = rld[r].reg_rtx;
5958 else if (reload_override_in[r]
5959 && (REG_P (reload_override_in[r])
5960 || GET_CODE (reload_override_in[r]) == SUBREG))
5961 check_reg = reload_override_in[r];
5964 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5965 rld[r].opnum, rld[r].when_needed, rld[r].in,
5966 (reload_inherited[r]
5967 ? rld[r].out : const0_rtx),
5972 reload_inherited[r] = 0;
5973 reload_override_in[r] = 0;
5975 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5976 reload_override_in, then we do not need its related
5977 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5978 likewise for other reload types.
5979 We handle this by removing a reload when its only replacement
5980 is mentioned in reload_in of the reload we are going to inherit.
5981 A special case are auto_inc expressions; even if the input is
5982 inherited, we still need the address for the output. We can
5983 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5984 If we succeeded removing some reload and we are doing a preliminary
5985 pass just to remove such reloads, make another pass, since the
5986 removal of one reload might allow us to inherit another one. */
5988 && rld[r].out != rld[r].in
5989 && remove_address_replacements (rld[r].in) && pass)
5994 /* Now that reload_override_in is known valid,
5995 actually override reload_in. */
5996 for (j = 0; j < n_reloads; j++)
5997 if (reload_override_in[j])
5998 rld[j].in = reload_override_in[j];
6000 /* If this reload won't be done because it has been canceled or is
6001 optional and not inherited, clear reload_reg_rtx so other
6002 routines (such as subst_reloads) don't get confused. */
6003 for (j = 0; j < n_reloads; j++)
6004 if (rld[j].reg_rtx != 0
6005 && ((rld[j].optional && ! reload_inherited[j])
6006 || (rld[j].in == 0 && rld[j].out == 0
6007 && ! rld[j].secondary_p)))
6009 int regno = true_regnum (rld[j].reg_rtx);
6011 if (spill_reg_order[regno] >= 0)
6012 clear_reload_reg_in_use (regno, rld[j].opnum,
6013 rld[j].when_needed, rld[j].mode);
6015 reload_spill_index[j] = -1;
6018 /* Record which pseudos and which spill regs have output reloads. */
6019 for (j = 0; j < n_reloads; j++)
6021 int r = reload_order[j];
6023 i = reload_spill_index[r];
6025 /* I is nonneg if this reload uses a register.
6026 If rld[r].reg_rtx is 0, this is an optional reload
6027 that we opted to ignore. */
6028 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6029 && rld[r].reg_rtx != 0)
6031 int nregno = REGNO (rld[r].out_reg);
6034 if (nregno < FIRST_PSEUDO_REGISTER)
6035 nr = hard_regno_nregs[nregno][rld[r].mode];
6038 reg_has_output_reload[nregno + nr] = 1;
6042 nr = hard_regno_nregs[i][rld[r].mode];
6044 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6047 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6048 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6049 || rld[r].when_needed == RELOAD_FOR_INSN);
6054 /* Deallocate the reload register for reload R. This is called from
6055 remove_address_replacements. */
6058 deallocate_reload_reg (int r)
6062 if (! rld[r].reg_rtx)
6064 regno = true_regnum (rld[r].reg_rtx);
6066 if (spill_reg_order[regno] >= 0)
6067 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6069 reload_spill_index[r] = -1;
6072 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6073 reloads of the same item for fear that we might not have enough reload
6074 registers. However, normally they will get the same reload register
6075 and hence actually need not be loaded twice.
6077 Here we check for the most common case of this phenomenon: when we have
6078 a number of reloads for the same object, each of which were allocated
6079 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6080 reload, and is not modified in the insn itself. If we find such,
6081 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6082 This will not increase the number of spill registers needed and will
6083 prevent redundant code. */
6086 merge_assigned_reloads (rtx insn)
6090 /* Scan all the reloads looking for ones that only load values and
6091 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6092 assigned and not modified by INSN. */
6094 for (i = 0; i < n_reloads; i++)
6096 int conflicting_input = 0;
6097 int max_input_address_opnum = -1;
6098 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6100 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6101 || rld[i].out != 0 || rld[i].reg_rtx == 0
6102 || reg_set_p (rld[i].reg_rtx, insn))
6105 /* Look at all other reloads. Ensure that the only use of this
6106 reload_reg_rtx is in a reload that just loads the same value
6107 as we do. Note that any secondary reloads must be of the identical
6108 class since the values, modes, and result registers are the
6109 same, so we need not do anything with any secondary reloads. */
6111 for (j = 0; j < n_reloads; j++)
6113 if (i == j || rld[j].reg_rtx == 0
6114 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6118 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6119 && rld[j].opnum > max_input_address_opnum)
6120 max_input_address_opnum = rld[j].opnum;
6122 /* If the reload regs aren't exactly the same (e.g, different modes)
6123 or if the values are different, we can't merge this reload.
6124 But if it is an input reload, we might still merge
6125 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6127 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6128 || rld[j].out != 0 || rld[j].in == 0
6129 || ! rtx_equal_p (rld[i].in, rld[j].in))
6131 if (rld[j].when_needed != RELOAD_FOR_INPUT
6132 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6133 || rld[i].opnum > rld[j].opnum)
6134 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6136 conflicting_input = 1;
6137 if (min_conflicting_input_opnum > rld[j].opnum)
6138 min_conflicting_input_opnum = rld[j].opnum;
6142 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6143 we, in fact, found any matching reloads. */
6146 && max_input_address_opnum <= min_conflicting_input_opnum)
6148 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6150 for (j = 0; j < n_reloads; j++)
6151 if (i != j && rld[j].reg_rtx != 0
6152 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6153 && (! conflicting_input
6154 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6155 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6157 rld[i].when_needed = RELOAD_OTHER;
6159 reload_spill_index[j] = -1;
6160 transfer_replacements (i, j);
6163 /* If this is now RELOAD_OTHER, look for any reloads that load
6164 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6165 if they were for inputs, RELOAD_OTHER for outputs. Note that
6166 this test is equivalent to looking for reloads for this operand
6168 /* We must take special care with RELOAD_FOR_OUTPUT_ADDRESS; it may
6169 share registers with a RELOAD_FOR_INPUT, so we can not change it
6170 to RELOAD_FOR_OTHER_ADDRESS. We should never need to, since we
6171 do not modify RELOAD_FOR_OUTPUT. */
6173 if (rld[i].when_needed == RELOAD_OTHER)
6174 for (j = 0; j < n_reloads; j++)
6176 && rld[j].when_needed != RELOAD_OTHER
6177 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6178 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6179 && (! conflicting_input
6180 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6181 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6182 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6188 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6189 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6190 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6192 /* Check to see if we accidentally converted two
6193 reloads that use the same reload register with
6194 different inputs to the same type. If so, the
6195 resulting code won't work. */
6197 for (k = 0; k < j; k++)
6198 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6199 || rld[k].when_needed != rld[j].when_needed
6200 || !rtx_equal_p (rld[k].reg_rtx,
6202 || rtx_equal_p (rld[k].in,
6209 /* These arrays are filled by emit_reload_insns and its subroutines. */
6210 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6211 static rtx other_input_address_reload_insns = 0;
6212 static rtx other_input_reload_insns = 0;
6213 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6214 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6215 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6216 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6217 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6218 static rtx operand_reload_insns = 0;
6219 static rtx other_operand_reload_insns = 0;
6220 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6222 /* Values to be put in spill_reg_store are put here first. */
6223 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6224 static HARD_REG_SET reg_reloaded_died;
6226 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6227 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6228 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6229 adjusted register, and return true. Otherwise, return false. */
6231 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6232 enum reg_class new_class,
6233 enum machine_mode new_mode)
6238 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6240 unsigned regno = REGNO (reg);
6242 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6244 if (GET_MODE (reg) != new_mode)
6246 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6248 if (hard_regno_nregs[regno][new_mode]
6249 > hard_regno_nregs[regno][GET_MODE (reg)])
6251 reg = reload_adjust_reg_for_mode (reg, new_mode);
6259 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6260 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6261 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6262 adjusted register, and return true. Otherwise, return false. */
6264 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6265 enum insn_code icode)
6268 enum reg_class new_class = scratch_reload_class (icode);
6269 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6271 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6272 new_class, new_mode);
6275 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6276 has the number J. OLD contains the value to be used as input. */
6279 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6282 rtx insn = chain->insn;
6283 rtx reloadreg = rl->reg_rtx;
6284 rtx oldequiv_reg = 0;
6287 enum machine_mode mode;
6290 /* Determine the mode to reload in.
6291 This is very tricky because we have three to choose from.
6292 There is the mode the insn operand wants (rl->inmode).
6293 There is the mode of the reload register RELOADREG.
6294 There is the intrinsic mode of the operand, which we could find
6295 by stripping some SUBREGs.
6296 It turns out that RELOADREG's mode is irrelevant:
6297 we can change that arbitrarily.
6299 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6300 then the reload reg may not support QImode moves, so use SImode.
6301 If foo is in memory due to spilling a pseudo reg, this is safe,
6302 because the QImode value is in the least significant part of a
6303 slot big enough for a SImode. If foo is some other sort of
6304 memory reference, then it is impossible to reload this case,
6305 so previous passes had better make sure this never happens.
6307 Then consider a one-word union which has SImode and one of its
6308 members is a float, being fetched as (SUBREG:SF union:SI).
6309 We must fetch that as SFmode because we could be loading into
6310 a float-only register. In this case OLD's mode is correct.
6312 Consider an immediate integer: it has VOIDmode. Here we need
6313 to get a mode from something else.
6315 In some cases, there is a fourth mode, the operand's
6316 containing mode. If the insn specifies a containing mode for
6317 this operand, it overrides all others.
6319 I am not sure whether the algorithm here is always right,
6320 but it does the right things in those cases. */
6322 mode = GET_MODE (old);
6323 if (mode == VOIDmode)
6326 /* delete_output_reload is only invoked properly if old contains
6327 the original pseudo register. Since this is replaced with a
6328 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6329 find the pseudo in RELOAD_IN_REG. */
6330 if (reload_override_in[j]
6331 && REG_P (rl->in_reg))
6338 else if (REG_P (oldequiv))
6339 oldequiv_reg = oldequiv;
6340 else if (GET_CODE (oldequiv) == SUBREG)
6341 oldequiv_reg = SUBREG_REG (oldequiv);
6343 /* If we are reloading from a register that was recently stored in
6344 with an output-reload, see if we can prove there was
6345 actually no need to store the old value in it. */
6347 if (optimize && REG_P (oldequiv)
6348 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6349 && spill_reg_store[REGNO (oldequiv)]
6351 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6352 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6354 delete_output_reload (insn, j, REGNO (oldequiv));
6356 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6357 then load RELOADREG from OLDEQUIV. Note that we cannot use
6358 gen_lowpart_common since it can do the wrong thing when
6359 RELOADREG has a multi-word mode. Note that RELOADREG
6360 must always be a REG here. */
6362 if (GET_MODE (reloadreg) != mode)
6363 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6364 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6365 oldequiv = SUBREG_REG (oldequiv);
6366 if (GET_MODE (oldequiv) != VOIDmode
6367 && mode != GET_MODE (oldequiv))
6368 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6370 /* Switch to the right place to emit the reload insns. */
6371 switch (rl->when_needed)
6374 where = &other_input_reload_insns;
6376 case RELOAD_FOR_INPUT:
6377 where = &input_reload_insns[rl->opnum];
6379 case RELOAD_FOR_INPUT_ADDRESS:
6380 where = &input_address_reload_insns[rl->opnum];
6382 case RELOAD_FOR_INPADDR_ADDRESS:
6383 where = &inpaddr_address_reload_insns[rl->opnum];
6385 case RELOAD_FOR_OUTPUT_ADDRESS:
6386 where = &output_address_reload_insns[rl->opnum];
6388 case RELOAD_FOR_OUTADDR_ADDRESS:
6389 where = &outaddr_address_reload_insns[rl->opnum];
6391 case RELOAD_FOR_OPERAND_ADDRESS:
6392 where = &operand_reload_insns;
6394 case RELOAD_FOR_OPADDR_ADDR:
6395 where = &other_operand_reload_insns;
6397 case RELOAD_FOR_OTHER_ADDRESS:
6398 where = &other_input_address_reload_insns;
6404 push_to_sequence (*where);
6406 /* Auto-increment addresses must be reloaded in a special way. */
6407 if (rl->out && ! rl->out_reg)
6409 /* We are not going to bother supporting the case where a
6410 incremented register can't be copied directly from
6411 OLDEQUIV since this seems highly unlikely. */
6412 gcc_assert (rl->secondary_in_reload < 0);
6414 if (reload_inherited[j])
6415 oldequiv = reloadreg;
6417 old = XEXP (rl->in_reg, 0);
6419 if (optimize && REG_P (oldequiv)
6420 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6421 && spill_reg_store[REGNO (oldequiv)]
6423 && (dead_or_set_p (insn,
6424 spill_reg_stored_to[REGNO (oldequiv)])
6425 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6427 delete_output_reload (insn, j, REGNO (oldequiv));
6429 /* Prevent normal processing of this reload. */
6431 /* Output a special code sequence for this case. */
6432 new_spill_reg_store[REGNO (reloadreg)]
6433 = inc_for_reload (reloadreg, oldequiv, rl->out,
6437 /* If we are reloading a pseudo-register that was set by the previous
6438 insn, see if we can get rid of that pseudo-register entirely
6439 by redirecting the previous insn into our reload register. */
6441 else if (optimize && REG_P (old)
6442 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6443 && dead_or_set_p (insn, old)
6444 /* This is unsafe if some other reload
6445 uses the same reg first. */
6446 && ! conflicts_with_override (reloadreg)
6447 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6448 rl->when_needed, old, rl->out, j, 0))
6450 rtx temp = PREV_INSN (insn);
6451 while (temp && NOTE_P (temp))
6452 temp = PREV_INSN (temp);
6454 && NONJUMP_INSN_P (temp)
6455 && GET_CODE (PATTERN (temp)) == SET
6456 && SET_DEST (PATTERN (temp)) == old
6457 /* Make sure we can access insn_operand_constraint. */
6458 && asm_noperands (PATTERN (temp)) < 0
6459 /* This is unsafe if operand occurs more than once in current
6460 insn. Perhaps some occurrences aren't reloaded. */
6461 && count_occurrences (PATTERN (insn), old, 0) == 1)
6463 rtx old = SET_DEST (PATTERN (temp));
6464 /* Store into the reload register instead of the pseudo. */
6465 SET_DEST (PATTERN (temp)) = reloadreg;
6467 /* Verify that resulting insn is valid. */
6468 extract_insn (temp);
6469 if (constrain_operands (1))
6471 /* If the previous insn is an output reload, the source is
6472 a reload register, and its spill_reg_store entry will
6473 contain the previous destination. This is now
6475 if (REG_P (SET_SRC (PATTERN (temp)))
6476 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6478 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6479 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6482 /* If these are the only uses of the pseudo reg,
6483 pretend for GDB it lives in the reload reg we used. */
6484 if (REG_N_DEATHS (REGNO (old)) == 1
6485 && REG_N_SETS (REGNO (old)) == 1)
6487 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6488 alter_reg (REGNO (old), -1);
6494 SET_DEST (PATTERN (temp)) = old;
6499 /* We can't do that, so output an insn to load RELOADREG. */
6501 /* If we have a secondary reload, pick up the secondary register
6502 and icode, if any. If OLDEQUIV and OLD are different or
6503 if this is an in-out reload, recompute whether or not we
6504 still need a secondary register and what the icode should
6505 be. If we still need a secondary register and the class or
6506 icode is different, go back to reloading from OLD if using
6507 OLDEQUIV means that we got the wrong type of register. We
6508 cannot have different class or icode due to an in-out reload
6509 because we don't make such reloads when both the input and
6510 output need secondary reload registers. */
6512 if (! special && rl->secondary_in_reload >= 0)
6514 rtx second_reload_reg = 0;
6515 rtx third_reload_reg = 0;
6516 int secondary_reload = rl->secondary_in_reload;
6517 rtx real_oldequiv = oldequiv;
6520 enum insn_code icode;
6521 enum insn_code tertiary_icode = CODE_FOR_nothing;
6523 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6524 and similarly for OLD.
6525 See comments in get_secondary_reload in reload.c. */
6526 /* If it is a pseudo that cannot be replaced with its
6527 equivalent MEM, we must fall back to reload_in, which
6528 will have all the necessary substitutions registered.
6529 Likewise for a pseudo that can't be replaced with its
6530 equivalent constant.
6532 Take extra care for subregs of such pseudos. Note that
6533 we cannot use reg_equiv_mem in this case because it is
6534 not in the right mode. */
6537 if (GET_CODE (tmp) == SUBREG)
6538 tmp = SUBREG_REG (tmp);
6540 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6541 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6542 || reg_equiv_constant[REGNO (tmp)] != 0))
6544 if (! reg_equiv_mem[REGNO (tmp)]
6545 || num_not_at_initial_offset
6546 || GET_CODE (oldequiv) == SUBREG)
6547 real_oldequiv = rl->in;
6549 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6553 if (GET_CODE (tmp) == SUBREG)
6554 tmp = SUBREG_REG (tmp);
6556 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6557 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6558 || reg_equiv_constant[REGNO (tmp)] != 0))
6560 if (! reg_equiv_mem[REGNO (tmp)]
6561 || num_not_at_initial_offset
6562 || GET_CODE (old) == SUBREG)
6565 real_old = reg_equiv_mem[REGNO (tmp)];
6568 second_reload_reg = rld[secondary_reload].reg_rtx;
6569 if (rld[secondary_reload].secondary_in_reload >= 0)
6571 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6573 third_reload_reg = rld[tertiary_reload].reg_rtx;
6574 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6575 /* We'd have to add more code for quartary reloads. */
6576 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6578 icode = rl->secondary_in_icode;
6580 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6581 || (rl->in != 0 && rl->out != 0))
6583 secondary_reload_info sri, sri2;
6584 enum reg_class new_class, new_t_class;
6586 sri.icode = CODE_FOR_nothing;
6587 sri.prev_sri = NULL;
6588 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6591 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6592 second_reload_reg = 0;
6593 else if (new_class == NO_REGS)
6595 if (reload_adjust_reg_for_icode (&second_reload_reg,
6596 third_reload_reg, sri.icode))
6597 icode = sri.icode, third_reload_reg = 0;
6599 oldequiv = old, real_oldequiv = real_old;
6601 else if (sri.icode != CODE_FOR_nothing)
6602 /* We currently lack a way to express this in reloads. */
6606 sri2.icode = CODE_FOR_nothing;
6607 sri2.prev_sri = &sri;
6608 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6609 new_class, mode, &sri);
6610 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6612 if (reload_adjust_reg_for_temp (&second_reload_reg,
6615 third_reload_reg = 0, tertiary_icode = sri2.icode;
6617 oldequiv = old, real_oldequiv = real_old;
6619 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6621 rtx intermediate = second_reload_reg;
6623 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6625 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6628 second_reload_reg = intermediate;
6629 tertiary_icode = sri2.icode;
6632 oldequiv = old, real_oldequiv = real_old;
6634 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6636 rtx intermediate = second_reload_reg;
6638 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6640 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6643 second_reload_reg = intermediate;
6644 tertiary_icode = sri2.icode;
6647 oldequiv = old, real_oldequiv = real_old;
6650 /* This could be handled more intelligently too. */
6651 oldequiv = old, real_oldequiv = real_old;
6655 /* If we still need a secondary reload register, check
6656 to see if it is being used as a scratch or intermediate
6657 register and generate code appropriately. If we need
6658 a scratch register, use REAL_OLDEQUIV since the form of
6659 the insn may depend on the actual address if it is
6662 if (second_reload_reg)
6664 if (icode != CODE_FOR_nothing)
6666 /* We'd have to add extra code to handle this case. */
6667 gcc_assert (!third_reload_reg);
6669 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6670 second_reload_reg));
6675 /* See if we need a scratch register to load the
6676 intermediate register (a tertiary reload). */
6677 if (tertiary_icode != CODE_FOR_nothing)
6679 emit_insn ((GEN_FCN (tertiary_icode)
6680 (second_reload_reg, real_oldequiv,
6681 third_reload_reg)));
6683 else if (third_reload_reg)
6685 gen_reload (third_reload_reg, real_oldequiv,
6688 gen_reload (second_reload_reg, third_reload_reg,
6693 gen_reload (second_reload_reg, real_oldequiv,
6697 oldequiv = second_reload_reg;
6702 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6704 rtx real_oldequiv = oldequiv;
6706 if ((REG_P (oldequiv)
6707 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6708 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6709 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6710 || (GET_CODE (oldequiv) == SUBREG
6711 && REG_P (SUBREG_REG (oldequiv))
6712 && (REGNO (SUBREG_REG (oldequiv))
6713 >= FIRST_PSEUDO_REGISTER)
6714 && ((reg_equiv_memory_loc
6715 [REGNO (SUBREG_REG (oldequiv))] != 0)
6716 || (reg_equiv_constant
6717 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6718 || (CONSTANT_P (oldequiv)
6719 && (PREFERRED_RELOAD_CLASS (oldequiv,
6720 REGNO_REG_CLASS (REGNO (reloadreg)))
6722 real_oldequiv = rl->in;
6723 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6727 if (flag_non_call_exceptions)
6728 copy_eh_notes (insn, get_insns ());
6730 /* End this sequence. */
6731 *where = get_insns ();
6734 /* Update reload_override_in so that delete_address_reloads_1
6735 can see the actual register usage. */
6737 reload_override_in[j] = oldequiv;
6740 /* Generate insns to for the output reload RL, which is for the insn described
6741 by CHAIN and has the number J. */
6743 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
6746 rtx reloadreg = rl->reg_rtx;
6747 rtx insn = chain->insn;
6750 enum machine_mode mode = GET_MODE (old);
6753 if (rl->when_needed == RELOAD_OTHER)
6756 push_to_sequence (output_reload_insns[rl->opnum]);
6758 /* Determine the mode to reload in.
6759 See comments above (for input reloading). */
6761 if (mode == VOIDmode)
6763 /* VOIDmode should never happen for an output. */
6764 if (asm_noperands (PATTERN (insn)) < 0)
6765 /* It's the compiler's fault. */
6766 fatal_insn ("VOIDmode on an output", insn);
6767 error_for_asm (insn, "output operand is constant in %<asm%>");
6768 /* Prevent crash--use something we know is valid. */
6770 old = gen_rtx_REG (mode, REGNO (reloadreg));
6773 if (GET_MODE (reloadreg) != mode)
6774 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6776 /* If we need two reload regs, set RELOADREG to the intermediate
6777 one, since it will be stored into OLD. We might need a secondary
6778 register only for an input reload, so check again here. */
6780 if (rl->secondary_out_reload >= 0)
6783 int secondary_reload = rl->secondary_out_reload;
6784 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
6786 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
6787 && reg_equiv_mem[REGNO (old)] != 0)
6788 real_old = reg_equiv_mem[REGNO (old)];
6790 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
6792 rtx second_reloadreg = reloadreg;
6793 reloadreg = rld[secondary_reload].reg_rtx;
6795 /* See if RELOADREG is to be used as a scratch register
6796 or as an intermediate register. */
6797 if (rl->secondary_out_icode != CODE_FOR_nothing)
6799 /* We'd have to add extra code to handle this case. */
6800 gcc_assert (tertiary_reload < 0);
6802 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6803 (real_old, second_reloadreg, reloadreg)));
6808 /* See if we need both a scratch and intermediate reload
6811 enum insn_code tertiary_icode
6812 = rld[secondary_reload].secondary_out_icode;
6814 /* We'd have to add more code for quartary reloads. */
6815 gcc_assert (tertiary_reload < 0
6816 || rld[tertiary_reload].secondary_out_reload < 0);
6818 if (GET_MODE (reloadreg) != mode)
6819 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6821 if (tertiary_icode != CODE_FOR_nothing)
6823 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6826 /* Copy primary reload reg to secondary reload reg.
6827 (Note that these have been swapped above, then
6828 secondary reload reg to OLD using our insn.) */
6830 /* If REAL_OLD is a paradoxical SUBREG, remove it
6831 and try to put the opposite SUBREG on
6833 if (GET_CODE (real_old) == SUBREG
6834 && (GET_MODE_SIZE (GET_MODE (real_old))
6835 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6836 && 0 != (tem = gen_lowpart_common
6837 (GET_MODE (SUBREG_REG (real_old)),
6839 real_old = SUBREG_REG (real_old), reloadreg = tem;
6841 gen_reload (reloadreg, second_reloadreg,
6842 rl->opnum, rl->when_needed);
6843 emit_insn ((GEN_FCN (tertiary_icode)
6844 (real_old, reloadreg, third_reloadreg)));
6850 /* Copy between the reload regs here and then to
6853 gen_reload (reloadreg, second_reloadreg,
6854 rl->opnum, rl->when_needed);
6855 if (tertiary_reload >= 0)
6857 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
6859 gen_reload (third_reloadreg, reloadreg,
6860 rl->opnum, rl->when_needed);
6861 reloadreg = third_reloadreg;
6868 /* Output the last reload insn. */
6873 /* Don't output the last reload if OLD is not the dest of
6874 INSN and is in the src and is clobbered by INSN. */
6875 if (! flag_expensive_optimizations
6877 || !(set = single_set (insn))
6878 || rtx_equal_p (old, SET_DEST (set))
6879 || !reg_mentioned_p (old, SET_SRC (set))
6880 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
6881 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
6882 gen_reload (old, reloadreg, rl->opnum,
6886 /* Look at all insns we emitted, just to be safe. */
6887 for (p = get_insns (); p; p = NEXT_INSN (p))
6890 rtx pat = PATTERN (p);
6892 /* If this output reload doesn't come from a spill reg,
6893 clear any memory of reloaded copies of the pseudo reg.
6894 If this output reload comes from a spill reg,
6895 reg_has_output_reload will make this do nothing. */
6896 note_stores (pat, forget_old_reloads_1, NULL);
6898 if (reg_mentioned_p (rl->reg_rtx, pat))
6900 rtx set = single_set (insn);
6901 if (reload_spill_index[j] < 0
6903 && SET_SRC (set) == rl->reg_rtx)
6905 int src = REGNO (SET_SRC (set));
6907 reload_spill_index[j] = src;
6908 SET_HARD_REG_BIT (reg_is_output_reload, src);
6909 if (find_regno_note (insn, REG_DEAD, src))
6910 SET_HARD_REG_BIT (reg_reloaded_died, src);
6912 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6914 int s = rl->secondary_out_reload;
6915 set = single_set (p);
6916 /* If this reload copies only to the secondary reload
6917 register, the secondary reload does the actual
6919 if (s >= 0 && set == NULL_RTX)
6920 /* We can't tell what function the secondary reload
6921 has and where the actual store to the pseudo is
6922 made; leave new_spill_reg_store alone. */
6925 && SET_SRC (set) == rl->reg_rtx
6926 && SET_DEST (set) == rld[s].reg_rtx)
6928 /* Usually the next instruction will be the
6929 secondary reload insn; if we can confirm
6930 that it is, setting new_spill_reg_store to
6931 that insn will allow an extra optimization. */
6932 rtx s_reg = rld[s].reg_rtx;
6933 rtx next = NEXT_INSN (p);
6934 rld[s].out = rl->out;
6935 rld[s].out_reg = rl->out_reg;
6936 set = single_set (next);
6937 if (set && SET_SRC (set) == s_reg
6938 && ! new_spill_reg_store[REGNO (s_reg)])
6940 SET_HARD_REG_BIT (reg_is_output_reload,
6942 new_spill_reg_store[REGNO (s_reg)] = next;
6946 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6951 if (rl->when_needed == RELOAD_OTHER)
6953 emit_insn (other_output_reload_insns[rl->opnum]);
6954 other_output_reload_insns[rl->opnum] = get_insns ();
6957 output_reload_insns[rl->opnum] = get_insns ();
6959 if (flag_non_call_exceptions)
6960 copy_eh_notes (insn, get_insns ());
6965 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6966 and has the number J. */
6968 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
6970 rtx insn = chain->insn;
6971 rtx old = (rl->in && MEM_P (rl->in)
6972 ? rl->in_reg : rl->in);
6975 /* AUTO_INC reloads need to be handled even if inherited. We got an
6976 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6977 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6978 && ! rtx_equal_p (rl->reg_rtx, old)
6979 && rl->reg_rtx != 0)
6980 emit_input_reload_insns (chain, rld + j, old, j);
6982 /* When inheriting a wider reload, we have a MEM in rl->in,
6983 e.g. inheriting a SImode output reload for
6984 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6985 if (optimize && reload_inherited[j] && rl->in
6987 && MEM_P (rl->in_reg)
6988 && reload_spill_index[j] >= 0
6989 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6990 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6992 /* If we are reloading a register that was recently stored in with an
6993 output-reload, see if we can prove there was
6994 actually no need to store the old value in it. */
6997 /* Only attempt this for input reloads; for RELOAD_OTHER we miss
6998 that there may be multiple uses of the previous output reload.
6999 Restricting to RELOAD_FOR_INPUT is mostly paranoia. */
7000 && rl->when_needed == RELOAD_FOR_INPUT
7001 && (reload_inherited[j] || reload_override_in[j])
7003 && REG_P (rl->reg_rtx)
7004 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7006 /* There doesn't seem to be any reason to restrict this to pseudos
7007 and doing so loses in the case where we are copying from a
7008 register of the wrong class. */
7009 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7010 >= FIRST_PSEUDO_REGISTER)
7012 /* The insn might have already some references to stackslots
7013 replaced by MEMs, while reload_out_reg still names the
7015 && (dead_or_set_p (insn,
7016 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7017 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7019 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7022 /* Do output reloading for reload RL, which is for the insn described by
7023 CHAIN and has the number J.
7024 ??? At some point we need to support handling output reloads of
7025 JUMP_INSNs or insns that set cc0. */
7027 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7030 rtx insn = chain->insn;
7031 /* If this is an output reload that stores something that is
7032 not loaded in this same reload, see if we can eliminate a previous
7034 rtx pseudo = rl->out_reg;
7039 && ! rtx_equal_p (rl->in_reg, pseudo)
7040 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7041 && reg_last_reload_reg[REGNO (pseudo)])
7043 int pseudo_no = REGNO (pseudo);
7044 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7046 /* We don't need to test full validity of last_regno for
7047 inherit here; we only want to know if the store actually
7048 matches the pseudo. */
7049 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7050 && reg_reloaded_contents[last_regno] == pseudo_no
7051 && spill_reg_store[last_regno]
7052 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7053 delete_output_reload (insn, j, last_regno);
7058 || rl->reg_rtx == old
7059 || rl->reg_rtx == 0)
7062 /* An output operand that dies right away does need a reload,
7063 but need not be copied from it. Show the new location in the
7065 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7066 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7068 XEXP (note, 0) = rl->reg_rtx;
7071 /* Likewise for a SUBREG of an operand that dies. */
7072 else if (GET_CODE (old) == SUBREG
7073 && REG_P (SUBREG_REG (old))
7074 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7077 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7081 else if (GET_CODE (old) == SCRATCH)
7082 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7083 but we don't want to make an output reload. */
7086 /* If is a JUMP_INSN, we can't support output reloads yet. */
7087 gcc_assert (NONJUMP_INSN_P (insn));
7089 emit_output_reload_insns (chain, rld + j, j);
7092 /* Reload number R reloads from or to a group of hard registers starting at
7093 register REGNO. Return true if it can be treated for inheritance purposes
7094 like a group of reloads, each one reloading a single hard register.
7095 The caller has already checked that the spill register and REGNO use
7096 the same number of registers to store the reload value. */
7099 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7101 #ifdef CANNOT_CHANGE_MODE_CLASS
7102 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7103 GET_MODE (rld[r].reg_rtx),
7104 reg_raw_mode[reload_spill_index[r]])
7105 && !REG_CANNOT_CHANGE_MODE_P (regno,
7106 GET_MODE (rld[r].reg_rtx),
7107 reg_raw_mode[regno]));
7113 /* Output insns to reload values in and out of the chosen reload regs. */
7116 emit_reload_insns (struct insn_chain *chain)
7118 rtx insn = chain->insn;
7122 CLEAR_HARD_REG_SET (reg_reloaded_died);
7124 for (j = 0; j < reload_n_operands; j++)
7125 input_reload_insns[j] = input_address_reload_insns[j]
7126 = inpaddr_address_reload_insns[j]
7127 = output_reload_insns[j] = output_address_reload_insns[j]
7128 = outaddr_address_reload_insns[j]
7129 = other_output_reload_insns[j] = 0;
7130 other_input_address_reload_insns = 0;
7131 other_input_reload_insns = 0;
7132 operand_reload_insns = 0;
7133 other_operand_reload_insns = 0;
7135 /* Dump reloads into the dump file. */
7138 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7139 debug_reload_to_stream (dump_file);
7142 /* Now output the instructions to copy the data into and out of the
7143 reload registers. Do these in the order that the reloads were reported,
7144 since reloads of base and index registers precede reloads of operands
7145 and the operands may need the base and index registers reloaded. */
7147 for (j = 0; j < n_reloads; j++)
7150 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7151 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7153 do_input_reload (chain, rld + j, j);
7154 do_output_reload (chain, rld + j, j);
7157 /* Now write all the insns we made for reloads in the order expected by
7158 the allocation functions. Prior to the insn being reloaded, we write
7159 the following reloads:
7161 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7163 RELOAD_OTHER reloads.
7165 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7166 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7167 RELOAD_FOR_INPUT reload for the operand.
7169 RELOAD_FOR_OPADDR_ADDRS reloads.
7171 RELOAD_FOR_OPERAND_ADDRESS reloads.
7173 After the insn being reloaded, we write the following:
7175 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7176 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7177 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7178 reloads for the operand. The RELOAD_OTHER output reloads are
7179 output in descending order by reload number. */
7181 emit_insn_before (other_input_address_reload_insns, insn);
7182 emit_insn_before (other_input_reload_insns, insn);
7184 for (j = 0; j < reload_n_operands; j++)
7186 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7187 emit_insn_before (input_address_reload_insns[j], insn);
7188 emit_insn_before (input_reload_insns[j], insn);
7191 emit_insn_before (other_operand_reload_insns, insn);
7192 emit_insn_before (operand_reload_insns, insn);
7194 for (j = 0; j < reload_n_operands; j++)
7196 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7197 x = emit_insn_after (output_address_reload_insns[j], x);
7198 x = emit_insn_after (output_reload_insns[j], x);
7199 emit_insn_after (other_output_reload_insns[j], x);
7202 /* For all the spill regs newly reloaded in this instruction,
7203 record what they were reloaded from, so subsequent instructions
7204 can inherit the reloads.
7206 Update spill_reg_store for the reloads of this insn.
7207 Copy the elements that were updated in the loop above. */
7209 for (j = 0; j < n_reloads; j++)
7211 int r = reload_order[j];
7212 int i = reload_spill_index[r];
7214 /* If this is a non-inherited input reload from a pseudo, we must
7215 clear any memory of a previous store to the same pseudo. Only do
7216 something if there will not be an output reload for the pseudo
7218 if (rld[r].in_reg != 0
7219 && ! (reload_inherited[r] || reload_override_in[r]))
7221 rtx reg = rld[r].in_reg;
7223 if (GET_CODE (reg) == SUBREG)
7224 reg = SUBREG_REG (reg);
7227 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7228 && ! reg_has_output_reload[REGNO (reg)])
7230 int nregno = REGNO (reg);
7232 if (reg_last_reload_reg[nregno])
7234 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7236 if (reg_reloaded_contents[last_regno] == nregno)
7237 spill_reg_store[last_regno] = 0;
7242 /* I is nonneg if this reload used a register.
7243 If rld[r].reg_rtx is 0, this is an optional reload
7244 that we opted to ignore. */
7246 if (i >= 0 && rld[r].reg_rtx != 0)
7248 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7250 int part_reaches_end = 0;
7251 int all_reaches_end = 1;
7253 /* For a multi register reload, we need to check if all or part
7254 of the value lives to the end. */
7255 for (k = 0; k < nr; k++)
7257 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7258 rld[r].when_needed))
7259 part_reaches_end = 1;
7261 all_reaches_end = 0;
7264 /* Ignore reloads that don't reach the end of the insn in
7266 if (all_reaches_end)
7268 /* First, clear out memory of what used to be in this spill reg.
7269 If consecutive registers are used, clear them all. */
7271 for (k = 0; k < nr; k++)
7273 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7274 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7277 /* Maybe the spill reg contains a copy of reload_out. */
7279 && (REG_P (rld[r].out)
7283 || REG_P (rld[r].out_reg)))
7285 rtx out = (REG_P (rld[r].out)
7289 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7290 int nregno = REGNO (out);
7291 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7292 : hard_regno_nregs[nregno]
7293 [GET_MODE (rld[r].reg_rtx)]);
7296 spill_reg_store[i] = new_spill_reg_store[i];
7297 spill_reg_stored_to[i] = out;
7298 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7300 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7302 && inherit_piecemeal_p (r, nregno));
7304 /* If NREGNO is a hard register, it may occupy more than
7305 one register. If it does, say what is in the
7306 rest of the registers assuming that both registers
7307 agree on how many words the object takes. If not,
7308 invalidate the subsequent registers. */
7310 if (nregno < FIRST_PSEUDO_REGISTER)
7311 for (k = 1; k < nnr; k++)
7312 reg_last_reload_reg[nregno + k]
7314 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7317 /* Now do the inverse operation. */
7318 for (k = 0; k < nr; k++)
7320 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7321 reg_reloaded_contents[i + k]
7322 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7325 reg_reloaded_insn[i + k] = insn;
7326 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7327 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7328 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7332 /* Maybe the spill reg contains a copy of reload_in. Only do
7333 something if there will not be an output reload for
7334 the register being reloaded. */
7335 else if (rld[r].out_reg == 0
7337 && ((REG_P (rld[r].in)
7338 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7339 && ! reg_has_output_reload[REGNO (rld[r].in)])
7340 || (REG_P (rld[r].in_reg)
7341 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7342 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7349 if (REG_P (rld[r].in)
7350 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7352 else if (REG_P (rld[r].in_reg))
7355 in = XEXP (rld[r].in_reg, 0);
7356 nregno = REGNO (in);
7358 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7359 : hard_regno_nregs[nregno]
7360 [GET_MODE (rld[r].reg_rtx)]);
7362 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7364 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7366 && inherit_piecemeal_p (r, nregno));
7368 if (nregno < FIRST_PSEUDO_REGISTER)
7369 for (k = 1; k < nnr; k++)
7370 reg_last_reload_reg[nregno + k]
7372 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7375 /* Unless we inherited this reload, show we haven't
7376 recently done a store.
7377 Previous stores of inherited auto_inc expressions
7378 also have to be discarded. */
7379 if (! reload_inherited[r]
7380 || (rld[r].out && ! rld[r].out_reg))
7381 spill_reg_store[i] = 0;
7383 for (k = 0; k < nr; k++)
7385 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7386 reg_reloaded_contents[i + k]
7387 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7390 reg_reloaded_insn[i + k] = insn;
7391 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7392 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7393 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7398 /* However, if part of the reload reaches the end, then we must
7399 invalidate the old info for the part that survives to the end. */
7400 else if (part_reaches_end)
7402 for (k = 0; k < nr; k++)
7403 if (reload_reg_reaches_end_p (i + k,
7405 rld[r].when_needed))
7406 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7410 /* The following if-statement was #if 0'd in 1.34 (or before...).
7411 It's reenabled in 1.35 because supposedly nothing else
7412 deals with this problem. */
7414 /* If a register gets output-reloaded from a non-spill register,
7415 that invalidates any previous reloaded copy of it.
7416 But forget_old_reloads_1 won't get to see it, because
7417 it thinks only about the original insn. So invalidate it here.
7418 Also do the same thing for RELOAD_OTHER constraints where the
7419 output is discarded. */
7421 && ((rld[r].out != 0
7422 && (REG_P (rld[r].out)
7423 || (MEM_P (rld[r].out)
7424 && REG_P (rld[r].out_reg))))
7425 || (rld[r].out == 0 && rld[r].out_reg
7426 && REG_P (rld[r].out_reg))))
7428 rtx out = ((rld[r].out && REG_P (rld[r].out))
7429 ? rld[r].out : rld[r].out_reg);
7430 int nregno = REGNO (out);
7431 if (nregno >= FIRST_PSEUDO_REGISTER)
7433 rtx src_reg, store_insn = NULL_RTX;
7435 reg_last_reload_reg[nregno] = 0;
7437 /* If we can find a hard register that is stored, record
7438 the storing insn so that we may delete this insn with
7439 delete_output_reload. */
7440 src_reg = rld[r].reg_rtx;
7442 /* If this is an optional reload, try to find the source reg
7443 from an input reload. */
7446 rtx set = single_set (insn);
7447 if (set && SET_DEST (set) == rld[r].out)
7451 src_reg = SET_SRC (set);
7453 for (k = 0; k < n_reloads; k++)
7455 if (rld[k].in == src_reg)
7457 src_reg = rld[k].reg_rtx;
7464 store_insn = new_spill_reg_store[REGNO (src_reg)];
7465 if (src_reg && REG_P (src_reg)
7466 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7468 int src_regno = REGNO (src_reg);
7469 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7470 /* The place where to find a death note varies with
7471 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7472 necessarily checked exactly in the code that moves
7473 notes, so just check both locations. */
7474 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7475 if (! note && store_insn)
7476 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7479 spill_reg_store[src_regno + nr] = store_insn;
7480 spill_reg_stored_to[src_regno + nr] = out;
7481 reg_reloaded_contents[src_regno + nr] = nregno;
7482 reg_reloaded_insn[src_regno + nr] = store_insn;
7483 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7484 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7485 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7486 GET_MODE (src_reg)))
7487 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7489 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7491 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7493 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7495 reg_last_reload_reg[nregno] = src_reg;
7496 /* We have to set reg_has_output_reload here, or else
7497 forget_old_reloads_1 will clear reg_last_reload_reg
7499 reg_has_output_reload[nregno] = 1;
7504 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7506 while (num_regs-- > 0)
7507 reg_last_reload_reg[nregno + num_regs] = 0;
7511 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7514 /* Go through the motions to emit INSN and test if it is strictly valid.
7515 Return the emitted insn if valid, else return NULL. */
7518 emit_insn_if_valid_for_reload (rtx insn)
7520 rtx last = get_last_insn ();
7523 insn = emit_insn (insn);
7524 code = recog_memoized (insn);
7528 extract_insn (insn);
7529 /* We want constrain operands to treat this insn strictly in its
7530 validity determination, i.e., the way it would after reload has
7532 if (constrain_operands (1))
7536 delete_insns_since (last);
7540 /* Emit code to perform a reload from IN (which may be a reload register) to
7541 OUT (which may also be a reload register). IN or OUT is from operand
7542 OPNUM with reload type TYPE.
7544 Returns first insn emitted. */
7547 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7549 rtx last = get_last_insn ();
7552 /* If IN is a paradoxical SUBREG, remove it and try to put the
7553 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7554 if (GET_CODE (in) == SUBREG
7555 && (GET_MODE_SIZE (GET_MODE (in))
7556 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7557 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7558 in = SUBREG_REG (in), out = tem;
7559 else if (GET_CODE (out) == SUBREG
7560 && (GET_MODE_SIZE (GET_MODE (out))
7561 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7562 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7563 out = SUBREG_REG (out), in = tem;
7565 /* How to do this reload can get quite tricky. Normally, we are being
7566 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7567 register that didn't get a hard register. In that case we can just
7568 call emit_move_insn.
7570 We can also be asked to reload a PLUS that adds a register or a MEM to
7571 another register, constant or MEM. This can occur during frame pointer
7572 elimination and while reloading addresses. This case is handled by
7573 trying to emit a single insn to perform the add. If it is not valid,
7574 we use a two insn sequence.
7576 Or we can be asked to reload an unary operand that was a fragment of
7577 an addressing mode, into a register. If it isn't recognized as-is,
7578 we try making the unop operand and the reload-register the same:
7579 (set reg:X (unop:X expr:Y))
7580 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7582 Finally, we could be called to handle an 'o' constraint by putting
7583 an address into a register. In that case, we first try to do this
7584 with a named pattern of "reload_load_address". If no such pattern
7585 exists, we just emit a SET insn and hope for the best (it will normally
7586 be valid on machines that use 'o').
7588 This entire process is made complex because reload will never
7589 process the insns we generate here and so we must ensure that
7590 they will fit their constraints and also by the fact that parts of
7591 IN might be being reloaded separately and replaced with spill registers.
7592 Because of this, we are, in some sense, just guessing the right approach
7593 here. The one listed above seems to work.
7595 ??? At some point, this whole thing needs to be rethought. */
7597 if (GET_CODE (in) == PLUS
7598 && (REG_P (XEXP (in, 0))
7599 || GET_CODE (XEXP (in, 0)) == SUBREG
7600 || MEM_P (XEXP (in, 0)))
7601 && (REG_P (XEXP (in, 1))
7602 || GET_CODE (XEXP (in, 1)) == SUBREG
7603 || CONSTANT_P (XEXP (in, 1))
7604 || MEM_P (XEXP (in, 1))))
7606 /* We need to compute the sum of a register or a MEM and another
7607 register, constant, or MEM, and put it into the reload
7608 register. The best possible way of doing this is if the machine
7609 has a three-operand ADD insn that accepts the required operands.
7611 The simplest approach is to try to generate such an insn and see if it
7612 is recognized and matches its constraints. If so, it can be used.
7614 It might be better not to actually emit the insn unless it is valid,
7615 but we need to pass the insn as an operand to `recog' and
7616 `extract_insn' and it is simpler to emit and then delete the insn if
7617 not valid than to dummy things up. */
7619 rtx op0, op1, tem, insn;
7622 op0 = find_replacement (&XEXP (in, 0));
7623 op1 = find_replacement (&XEXP (in, 1));
7625 /* Since constraint checking is strict, commutativity won't be
7626 checked, so we need to do that here to avoid spurious failure
7627 if the add instruction is two-address and the second operand
7628 of the add is the same as the reload reg, which is frequently
7629 the case. If the insn would be A = B + A, rearrange it so
7630 it will be A = A + B as constrain_operands expects. */
7632 if (REG_P (XEXP (in, 1))
7633 && REGNO (out) == REGNO (XEXP (in, 1)))
7634 tem = op0, op0 = op1, op1 = tem;
7636 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7637 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7639 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7643 /* If that failed, we must use a conservative two-insn sequence.
7645 Use a move to copy one operand into the reload register. Prefer
7646 to reload a constant, MEM or pseudo since the move patterns can
7647 handle an arbitrary operand. If OP1 is not a constant, MEM or
7648 pseudo and OP1 is not a valid operand for an add instruction, then
7651 After reloading one of the operands into the reload register, add
7652 the reload register to the output register.
7654 If there is another way to do this for a specific machine, a
7655 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7658 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7660 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7662 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7663 || (code != CODE_FOR_nothing
7664 && ! ((*insn_data[code].operand[2].predicate)
7665 (op1, insn_data[code].operand[2].mode))))
7666 tem = op0, op0 = op1, op1 = tem;
7668 gen_reload (out, op0, opnum, type);
7670 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7671 This fixes a problem on the 32K where the stack pointer cannot
7672 be used as an operand of an add insn. */
7674 if (rtx_equal_p (op0, op1))
7677 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7680 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7682 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7686 /* If that failed, copy the address register to the reload register.
7687 Then add the constant to the reload register. */
7689 gen_reload (out, op1, opnum, type);
7690 insn = emit_insn (gen_add2_insn (out, op0));
7691 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7694 #ifdef SECONDARY_MEMORY_NEEDED
7695 /* If we need a memory location to do the move, do it that way. */
7696 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7697 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7698 && (REG_P (out) || GET_CODE (out) == SUBREG)
7699 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7700 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7701 REGNO_REG_CLASS (reg_or_subregno (out)),
7704 /* Get the memory to use and rewrite both registers to its mode. */
7705 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7707 if (GET_MODE (loc) != GET_MODE (out))
7708 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7710 if (GET_MODE (loc) != GET_MODE (in))
7711 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7713 gen_reload (loc, in, opnum, type);
7714 gen_reload (out, loc, opnum, type);
7717 else if (REG_P (out) && UNARY_P (in))
7724 op1 = find_replacement (&XEXP (in, 0));
7725 if (op1 != XEXP (in, 0))
7726 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
7728 /* First, try a plain SET. */
7729 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7733 /* If that failed, move the inner operand to the reload
7734 register, and try the same unop with the inner expression
7735 replaced with the reload register. */
7737 if (GET_MODE (op1) != GET_MODE (out))
7738 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
7742 gen_reload (out_moded, op1, opnum, type);
7745 = gen_rtx_SET (VOIDmode, out,
7746 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
7748 insn = emit_insn_if_valid_for_reload (insn);
7752 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7756 fatal_insn ("Failure trying to reload:", set);
7758 /* If IN is a simple operand, use gen_move_insn. */
7759 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
7760 emit_insn (gen_move_insn (out, in));
7762 #ifdef HAVE_reload_load_address
7763 else if (HAVE_reload_load_address)
7764 emit_insn (gen_reload_load_address (out, in));
7767 /* Otherwise, just write (set OUT IN) and hope for the best. */
7769 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7771 /* Return the first insn emitted.
7772 We can not just return get_last_insn, because there may have
7773 been multiple instructions emitted. Also note that gen_move_insn may
7774 emit more than one insn itself, so we can not assume that there is one
7775 insn emitted per emit_insn_before call. */
7777 return last ? NEXT_INSN (last) : get_insns ();
7780 /* Delete a previously made output-reload whose result we now believe
7781 is not needed. First we double-check.
7783 INSN is the insn now being processed.
7784 LAST_RELOAD_REG is the hard register number for which we want to delete
7785 the last output reload.
7786 J is the reload-number that originally used REG. The caller has made
7787 certain that reload J doesn't use REG any longer for input. */
7790 delete_output_reload (rtx insn, int j, int last_reload_reg)
7792 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7793 rtx reg = spill_reg_stored_to[last_reload_reg];
7796 int n_inherited = 0;
7800 /* It is possible that this reload has been only used to set another reload
7801 we eliminated earlier and thus deleted this instruction too. */
7802 if (INSN_DELETED_P (output_reload_insn))
7805 /* Get the raw pseudo-register referred to. */
7807 while (GET_CODE (reg) == SUBREG)
7808 reg = SUBREG_REG (reg);
7809 substed = reg_equiv_memory_loc[REGNO (reg)];
7811 /* This is unsafe if the operand occurs more often in the current
7812 insn than it is inherited. */
7813 for (k = n_reloads - 1; k >= 0; k--)
7815 rtx reg2 = rld[k].in;
7818 if (MEM_P (reg2) || reload_override_in[k])
7819 reg2 = rld[k].in_reg;
7821 if (rld[k].out && ! rld[k].out_reg)
7822 reg2 = XEXP (rld[k].in_reg, 0);
7824 while (GET_CODE (reg2) == SUBREG)
7825 reg2 = SUBREG_REG (reg2);
7826 if (rtx_equal_p (reg2, reg))
7828 if (reload_inherited[k] || reload_override_in[k] || k == j)
7831 reg2 = rld[k].out_reg;
7834 while (GET_CODE (reg2) == SUBREG)
7835 reg2 = XEXP (reg2, 0);
7836 if (rtx_equal_p (reg2, reg))
7843 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7845 n_occurrences += count_occurrences (PATTERN (insn),
7846 eliminate_regs (substed, 0,
7848 if (n_occurrences > n_inherited)
7851 /* If the pseudo-reg we are reloading is no longer referenced
7852 anywhere between the store into it and here,
7853 and we're within the same basic block, then the value can only
7854 pass through the reload reg and end up here.
7855 Otherwise, give up--return. */
7856 for (i1 = NEXT_INSN (output_reload_insn);
7857 i1 != insn; i1 = NEXT_INSN (i1))
7859 if (NOTE_INSN_BASIC_BLOCK_P (i1))
7861 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
7862 && reg_mentioned_p (reg, PATTERN (i1)))
7864 /* If this is USE in front of INSN, we only have to check that
7865 there are no more references than accounted for by inheritance. */
7866 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
7868 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7869 i1 = NEXT_INSN (i1);
7871 if (n_occurrences <= n_inherited && i1 == insn)
7877 /* We will be deleting the insn. Remove the spill reg information. */
7878 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
7880 spill_reg_store[last_reload_reg + k] = 0;
7881 spill_reg_stored_to[last_reload_reg + k] = 0;
7884 /* The caller has already checked that REG dies or is set in INSN.
7885 It has also checked that we are optimizing, and thus some
7886 inaccuracies in the debugging information are acceptable.
7887 So we could just delete output_reload_insn. But in some cases
7888 we can improve the debugging information without sacrificing
7889 optimization - maybe even improving the code: See if the pseudo
7890 reg has been completely replaced with reload regs. If so, delete
7891 the store insn and forget we had a stack slot for the pseudo. */
7892 if (rld[j].out != rld[j].in
7893 && REG_N_DEATHS (REGNO (reg)) == 1
7894 && REG_N_SETS (REGNO (reg)) == 1
7895 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7896 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7900 /* We know that it was used only between here and the beginning of
7901 the current basic block. (We also know that the last use before
7902 INSN was the output reload we are thinking of deleting, but never
7903 mind that.) Search that range; see if any ref remains. */
7904 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7906 rtx set = single_set (i2);
7908 /* Uses which just store in the pseudo don't count,
7909 since if they are the only uses, they are dead. */
7910 if (set != 0 && SET_DEST (set) == reg)
7915 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
7916 && reg_mentioned_p (reg, PATTERN (i2)))
7918 /* Some other ref remains; just delete the output reload we
7920 delete_address_reloads (output_reload_insn, insn);
7921 delete_insn (output_reload_insn);
7926 /* Delete the now-dead stores into this pseudo. Note that this
7927 loop also takes care of deleting output_reload_insn. */
7928 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7930 rtx set = single_set (i2);
7932 if (set != 0 && SET_DEST (set) == reg)
7934 delete_address_reloads (i2, insn);
7942 /* For the debugging info, say the pseudo lives in this reload reg. */
7943 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7944 alter_reg (REGNO (reg), -1);
7948 delete_address_reloads (output_reload_insn, insn);
7949 delete_insn (output_reload_insn);
7953 /* We are going to delete DEAD_INSN. Recursively delete loads of
7954 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7955 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7957 delete_address_reloads (rtx dead_insn, rtx current_insn)
7959 rtx set = single_set (dead_insn);
7960 rtx set2, dst, prev, next;
7963 rtx dst = SET_DEST (set);
7965 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7967 /* If we deleted the store from a reloaded post_{in,de}c expression,
7968 we can delete the matching adds. */
7969 prev = PREV_INSN (dead_insn);
7970 next = NEXT_INSN (dead_insn);
7971 if (! prev || ! next)
7973 set = single_set (next);
7974 set2 = single_set (prev);
7976 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7977 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7978 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7980 dst = SET_DEST (set);
7981 if (! rtx_equal_p (dst, SET_DEST (set2))
7982 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7983 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7984 || (INTVAL (XEXP (SET_SRC (set), 1))
7985 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7987 delete_related_insns (prev);
7988 delete_related_insns (next);
7991 /* Subfunction of delete_address_reloads: process registers found in X. */
7993 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
7995 rtx prev, set, dst, i2;
7997 enum rtx_code code = GET_CODE (x);
8001 const char *fmt = GET_RTX_FORMAT (code);
8002 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8005 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8006 else if (fmt[i] == 'E')
8008 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8009 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8016 if (spill_reg_order[REGNO (x)] < 0)
8019 /* Scan backwards for the insn that sets x. This might be a way back due
8021 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8023 code = GET_CODE (prev);
8024 if (code == CODE_LABEL || code == JUMP_INSN)
8028 if (reg_set_p (x, PATTERN (prev)))
8030 if (reg_referenced_p (x, PATTERN (prev)))
8033 if (! prev || INSN_UID (prev) < reload_first_uid)
8035 /* Check that PREV only sets the reload register. */
8036 set = single_set (prev);
8039 dst = SET_DEST (set);
8041 || ! rtx_equal_p (dst, x))
8043 if (! reg_set_p (dst, PATTERN (dead_insn)))
8045 /* Check if DST was used in a later insn -
8046 it might have been inherited. */
8047 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8053 if (reg_referenced_p (dst, PATTERN (i2)))
8055 /* If there is a reference to the register in the current insn,
8056 it might be loaded in a non-inherited reload. If no other
8057 reload uses it, that means the register is set before
8059 if (i2 == current_insn)
8061 for (j = n_reloads - 1; j >= 0; j--)
8062 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8063 || reload_override_in[j] == dst)
8065 for (j = n_reloads - 1; j >= 0; j--)
8066 if (rld[j].in && rld[j].reg_rtx == dst)
8075 /* If DST is still live at CURRENT_INSN, check if it is used for
8076 any reload. Note that even if CURRENT_INSN sets DST, we still
8077 have to check the reloads. */
8078 if (i2 == current_insn)
8080 for (j = n_reloads - 1; j >= 0; j--)
8081 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8082 || reload_override_in[j] == dst)
8084 /* ??? We can't finish the loop here, because dst might be
8085 allocated to a pseudo in this block if no reload in this
8086 block needs any of the classes containing DST - see
8087 spill_hard_reg. There is no easy way to tell this, so we
8088 have to scan till the end of the basic block. */
8090 if (reg_set_p (dst, PATTERN (i2)))
8094 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8095 reg_reloaded_contents[REGNO (dst)] = -1;
8099 /* Output reload-insns to reload VALUE into RELOADREG.
8100 VALUE is an autoincrement or autodecrement RTX whose operand
8101 is a register or memory location;
8102 so reloading involves incrementing that location.
8103 IN is either identical to VALUE, or some cheaper place to reload from.
8105 INC_AMOUNT is the number to increment or decrement by (always positive).
8106 This cannot be deduced from VALUE.
8108 Return the instruction that stores into RELOADREG. */
8111 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8113 /* REG or MEM to be copied and incremented. */
8114 rtx incloc = XEXP (value, 0);
8115 /* Nonzero if increment after copying. */
8116 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8117 || GET_CODE (value) == POST_MODIFY);
8123 rtx real_in = in == value ? XEXP (in, 0) : in;
8125 /* No hard register is equivalent to this register after
8126 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8127 we could inc/dec that register as well (maybe even using it for
8128 the source), but I'm not sure it's worth worrying about. */
8130 reg_last_reload_reg[REGNO (incloc)] = 0;
8132 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8134 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8135 inc = XEXP (XEXP (value, 1), 1);
8139 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8140 inc_amount = -inc_amount;
8142 inc = GEN_INT (inc_amount);
8145 /* If this is post-increment, first copy the location to the reload reg. */
8146 if (post && real_in != reloadreg)
8147 emit_insn (gen_move_insn (reloadreg, real_in));
8151 /* See if we can directly increment INCLOC. Use a method similar to
8152 that in gen_reload. */
8154 last = get_last_insn ();
8155 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8156 gen_rtx_PLUS (GET_MODE (incloc),
8159 code = recog_memoized (add_insn);
8162 extract_insn (add_insn);
8163 if (constrain_operands (1))
8165 /* If this is a pre-increment and we have incremented the value
8166 where it lives, copy the incremented value to RELOADREG to
8167 be used as an address. */
8170 emit_insn (gen_move_insn (reloadreg, incloc));
8175 delete_insns_since (last);
8178 /* If couldn't do the increment directly, must increment in RELOADREG.
8179 The way we do this depends on whether this is pre- or post-increment.
8180 For pre-increment, copy INCLOC to the reload register, increment it
8181 there, then save back. */
8185 if (in != reloadreg)
8186 emit_insn (gen_move_insn (reloadreg, real_in));
8187 emit_insn (gen_add2_insn (reloadreg, inc));
8188 store = emit_insn (gen_move_insn (incloc, reloadreg));
8193 Because this might be a jump insn or a compare, and because RELOADREG
8194 may not be available after the insn in an input reload, we must do
8195 the incrementation before the insn being reloaded for.
8197 We have already copied IN to RELOADREG. Increment the copy in
8198 RELOADREG, save that back, then decrement RELOADREG so it has
8199 the original value. */
8201 emit_insn (gen_add2_insn (reloadreg, inc));
8202 store = emit_insn (gen_move_insn (incloc, reloadreg));
8203 if (GET_CODE (inc) == CONST_INT)
8204 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL(inc))));
8206 emit_insn (gen_sub2_insn (reloadreg, inc));
8214 add_auto_inc_notes (rtx insn, rtx x)
8216 enum rtx_code code = GET_CODE (x);
8220 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8223 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8227 /* Scan all the operand sub-expressions. */
8228 fmt = GET_RTX_FORMAT (code);
8229 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8232 add_auto_inc_notes (insn, XEXP (x, i));
8233 else if (fmt[i] == 'E')
8234 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8235 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8240 /* Copy EH notes from an insn to its reloads. */
8242 copy_eh_notes (rtx insn, rtx x)
8244 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8247 for (; x != 0; x = NEXT_INSN (x))
8249 if (may_trap_p (PATTERN (x)))
8251 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8257 /* This is used by reload pass, that does emit some instructions after
8258 abnormal calls moving basic block end, but in fact it wants to emit
8259 them on the edge. Looks for abnormal call edges, find backward the
8260 proper call and fix the damage.
8262 Similar handle instructions throwing exceptions internally. */
8264 fixup_abnormal_edges (void)
8266 bool inserted = false;
8274 /* Look for cases we are interested in - calls or instructions causing
8276 FOR_EACH_EDGE (e, ei, bb->succs)
8278 if (e->flags & EDGE_ABNORMAL_CALL)
8280 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8281 == (EDGE_ABNORMAL | EDGE_EH))
8284 if (e && !CALL_P (BB_END (bb))
8285 && !can_throw_internal (BB_END (bb)))
8289 /* Get past the new insns generated. Allow notes, as the insns
8290 may be already deleted. */
8292 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8293 && !can_throw_internal (insn)
8294 && insn != BB_HEAD (bb))
8295 insn = PREV_INSN (insn);
8297 if (CALL_P (insn) || can_throw_internal (insn))
8301 stop = NEXT_INSN (BB_END (bb));
8303 insn = NEXT_INSN (insn);
8305 FOR_EACH_EDGE (e, ei, bb->succs)
8306 if (e->flags & EDGE_FALLTHRU)
8309 while (insn && insn != stop)
8311 next = NEXT_INSN (insn);
8316 /* Sometimes there's still the return value USE.
8317 If it's placed after a trapping call (i.e. that
8318 call is the last insn anyway), we have no fallthru
8319 edge. Simply delete this use and don't try to insert
8320 on the non-existent edge. */
8321 if (GET_CODE (PATTERN (insn)) != USE)
8323 /* We're not deleting it, we're moving it. */
8324 INSN_DELETED_P (insn) = 0;
8325 PREV_INSN (insn) = NULL_RTX;
8326 NEXT_INSN (insn) = NULL_RTX;
8328 insert_insn_on_edge (insn, e);
8336 /* It may be that we don't find any such trapping insn. In this
8337 case we discovered quite late that the insn that had been
8338 marked as can_throw_internal in fact couldn't trap at all.
8339 So we should in fact delete the EH edges out of the block. */
8341 purge_dead_edges (bb);
8345 /* We've possibly turned single trapping insn into multiple ones. */
8346 if (flag_non_call_exceptions)
8349 blocks = sbitmap_alloc (last_basic_block);
8350 sbitmap_ones (blocks);
8351 find_many_sub_basic_blocks (blocks);
8355 commit_edge_insertions ();
8357 #ifdef ENABLE_CHECKING
8358 /* Verify that we didn't turn one trapping insn into many, and that
8359 we found and corrected all of the problems wrt fixups on the
8361 verify_flow_info ();
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