1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
52 /* This file contains the reload pass of the compiler, which is
53 run after register allocation has been done. It checks that
54 each insn is valid (operands required to be in registers really
55 are in registers of the proper class) and fixes up invalid ones
56 by copying values temporarily into registers for the insns
59 The results of register allocation are described by the vector
60 reg_renumber; the insns still contain pseudo regs, but reg_renumber
61 can be used to find which hard reg, if any, a pseudo reg is in.
63 The technique we always use is to free up a few hard regs that are
64 called ``reload regs'', and for each place where a pseudo reg
65 must be in a hard reg, copy it temporarily into one of the reload regs.
67 Reload regs are allocated locally for every instruction that needs
68 reloads. When there are pseudos which are allocated to a register that
69 has been chosen as a reload reg, such pseudos must be ``spilled''.
70 This means that they go to other hard regs, or to stack slots if no other
71 available hard regs can be found. Spilling can invalidate more
72 insns, requiring additional need for reloads, so we must keep checking
73 until the process stabilizes.
75 For machines with different classes of registers, we must keep track
76 of the register class needed for each reload, and make sure that
77 we allocate enough reload registers of each class.
79 The file reload.c contains the code that checks one insn for
80 validity and reports the reloads that it needs. This file
81 is in charge of scanning the entire rtl code, accumulating the
82 reload needs, spilling, assigning reload registers to use for
83 fixing up each insn, and generating the new insns to copy values
84 into the reload registers. */
86 /* During reload_as_needed, element N contains a REG rtx for the hard reg
87 into which reg N has been reloaded (perhaps for a previous insn). */
88 static rtx *reg_last_reload_reg;
90 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
91 for an output reload that stores into reg N. */
92 static regset_head reg_has_output_reload;
94 /* Indicates which hard regs are reload-registers for an output reload
95 in the current insn. */
96 static HARD_REG_SET reg_is_output_reload;
98 /* Element N is the constant value to which pseudo reg N is equivalent,
99 or zero if pseudo reg N is not equivalent to a constant.
100 find_reloads looks at this in order to replace pseudo reg N
101 with the constant it stands for. */
102 rtx *reg_equiv_constant;
104 /* Element N is an invariant value to which pseudo reg N is equivalent.
105 eliminate_regs_in_insn uses this to replace pseudos in particular
107 rtx *reg_equiv_invariant;
109 /* Element N is a memory location to which pseudo reg N is equivalent,
110 prior to any register elimination (such as frame pointer to stack
111 pointer). Depending on whether or not it is a valid address, this value
112 is transferred to either reg_equiv_address or reg_equiv_mem. */
113 rtx *reg_equiv_memory_loc;
115 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
116 collector can keep track of what is inside. */
117 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
119 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
120 This is used when the address is not valid as a memory address
121 (because its displacement is too big for the machine.) */
122 rtx *reg_equiv_address;
124 /* Element N is the memory slot to which pseudo reg N is equivalent,
125 or zero if pseudo reg N is not equivalent to a memory slot. */
128 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
129 alternate representations of the location of pseudo reg N. */
130 rtx *reg_equiv_alt_mem_list;
132 /* Widest width in which each pseudo reg is referred to (via subreg). */
133 static unsigned int *reg_max_ref_width;
135 /* Element N is the list of insns that initialized reg N from its equivalent
136 constant or memory slot. */
138 int reg_equiv_init_size;
140 /* Vector to remember old contents of reg_renumber before spilling. */
141 static short *reg_old_renumber;
143 /* During reload_as_needed, element N contains the last pseudo regno reloaded
144 into hard register N. If that pseudo reg occupied more than one register,
145 reg_reloaded_contents points to that pseudo for each spill register in
146 use; all of these must remain set for an inheritance to occur. */
147 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
149 /* During reload_as_needed, element N contains the insn for which
150 hard register N was last used. Its contents are significant only
151 when reg_reloaded_valid is set for this register. */
152 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
154 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
155 static HARD_REG_SET reg_reloaded_valid;
156 /* Indicate if the register was dead at the end of the reload.
157 This is only valid if reg_reloaded_contents is set and valid. */
158 static HARD_REG_SET reg_reloaded_dead;
160 /* Indicate whether the register's current value is one that is not
161 safe to retain across a call, even for registers that are normally
162 call-saved. This is only meaningful for members of reg_reloaded_valid. */
163 static HARD_REG_SET reg_reloaded_call_part_clobbered;
165 /* Number of spill-regs so far; number of valid elements of spill_regs. */
168 /* In parallel with spill_regs, contains REG rtx's for those regs.
169 Holds the last rtx used for any given reg, or 0 if it has never
170 been used for spilling yet. This rtx is reused, provided it has
172 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
174 /* In parallel with spill_regs, contains nonzero for a spill reg
175 that was stored after the last time it was used.
176 The precise value is the insn generated to do the store. */
177 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
179 /* This is the register that was stored with spill_reg_store. This is a
180 copy of reload_out / reload_out_reg when the value was stored; if
181 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
182 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
184 /* This table is the inverse mapping of spill_regs:
185 indexed by hard reg number,
186 it contains the position of that reg in spill_regs,
187 or -1 for something that is not in spill_regs.
189 ?!? This is no longer accurate. */
190 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
192 /* This reg set indicates registers that can't be used as spill registers for
193 the currently processed insn. These are the hard registers which are live
194 during the insn, but not allocated to pseudos, as well as fixed
196 static HARD_REG_SET bad_spill_regs;
198 /* These are the hard registers that can't be used as spill register for any
199 insn. This includes registers used for user variables and registers that
200 we can't eliminate. A register that appears in this set also can't be used
201 to retry register allocation. */
202 static HARD_REG_SET bad_spill_regs_global;
204 /* Describes order of use of registers for reloading
205 of spilled pseudo-registers. `n_spills' is the number of
206 elements that are actually valid; new ones are added at the end.
208 Both spill_regs and spill_reg_order are used on two occasions:
209 once during find_reload_regs, where they keep track of the spill registers
210 for a single insn, but also during reload_as_needed where they show all
211 the registers ever used by reload. For the latter case, the information
212 is calculated during finish_spills. */
213 static short spill_regs[FIRST_PSEUDO_REGISTER];
215 /* This vector of reg sets indicates, for each pseudo, which hard registers
216 may not be used for retrying global allocation because the register was
217 formerly spilled from one of them. If we allowed reallocating a pseudo to
218 a register that it was already allocated to, reload might not
220 static HARD_REG_SET *pseudo_previous_regs;
222 /* This vector of reg sets indicates, for each pseudo, which hard
223 registers may not be used for retrying global allocation because they
224 are used as spill registers during one of the insns in which the
226 static HARD_REG_SET *pseudo_forbidden_regs;
228 /* All hard regs that have been used as spill registers for any insn are
229 marked in this set. */
230 static HARD_REG_SET used_spill_regs;
232 /* Index of last register assigned as a spill register. We allocate in
233 a round-robin fashion. */
234 static int last_spill_reg;
236 /* Nonzero if indirect addressing is supported on the machine; this means
237 that spilling (REG n) does not require reloading it into a register in
238 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
239 value indicates the level of indirect addressing supported, e.g., two
240 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
242 static char spill_indirect_levels;
244 /* Nonzero if indirect addressing is supported when the innermost MEM is
245 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
246 which these are valid is the same as spill_indirect_levels, above. */
247 char indirect_symref_ok;
249 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
250 char double_reg_address_ok;
252 /* Record the stack slot for each spilled hard register. */
253 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
255 /* Width allocated so far for that stack slot. */
256 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
258 /* Record which pseudos needed to be spilled. */
259 static regset_head spilled_pseudos;
261 /* Record which pseudos changed their allocation in finish_spills. */
262 static regset_head changed_allocation_pseudos;
264 /* Used for communication between order_regs_for_reload and count_pseudo.
265 Used to avoid counting one pseudo twice. */
266 static regset_head pseudos_counted;
268 /* First uid used by insns created by reload in this function.
269 Used in find_equiv_reg. */
270 int reload_first_uid;
272 /* Flag set by local-alloc or global-alloc if anything is live in
273 a call-clobbered reg across calls. */
274 int caller_save_needed;
276 /* Set to 1 while reload_as_needed is operating.
277 Required by some machines to handle any generated moves differently. */
278 int reload_in_progress = 0;
280 /* These arrays record the insn_code of insns that may be needed to
281 perform input and output reloads of special objects. They provide a
282 place to pass a scratch register. */
283 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
284 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
286 /* This obstack is used for allocation of rtl during register elimination.
287 The allocated storage can be freed once find_reloads has processed the
289 static struct obstack reload_obstack;
291 /* Points to the beginning of the reload_obstack. All insn_chain structures
292 are allocated first. */
293 static char *reload_startobj;
295 /* The point after all insn_chain structures. Used to quickly deallocate
296 memory allocated in copy_reloads during calculate_needs_all_insns. */
297 static char *reload_firstobj;
299 /* This points before all local rtl generated by register elimination.
300 Used to quickly free all memory after processing one insn. */
301 static char *reload_insn_firstobj;
303 /* List of insn_chain instructions, one for every insn that reload needs to
305 struct insn_chain *reload_insn_chain;
307 /* List of all insns needing reloads. */
308 static struct insn_chain *insns_need_reload;
310 /* This structure is used to record information about register eliminations.
311 Each array entry describes one possible way of eliminating a register
312 in favor of another. If there is more than one way of eliminating a
313 particular register, the most preferred should be specified first. */
317 int from; /* Register number to be eliminated. */
318 int to; /* Register number used as replacement. */
319 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
320 int can_eliminate; /* Nonzero if this elimination can be done. */
321 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
322 insns made by reload. */
323 HOST_WIDE_INT offset; /* Current offset between the two regs. */
324 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
325 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
326 rtx from_rtx; /* REG rtx for the register to be eliminated.
327 We cannot simply compare the number since
328 we might then spuriously replace a hard
329 register corresponding to a pseudo
330 assigned to the reg to be eliminated. */
331 rtx to_rtx; /* REG rtx for the replacement. */
334 static struct elim_table *reg_eliminate = 0;
336 /* This is an intermediate structure to initialize the table. It has
337 exactly the members provided by ELIMINABLE_REGS. */
338 static const struct elim_table_1
342 } reg_eliminate_1[] =
344 /* If a set of eliminable registers was specified, define the table from it.
345 Otherwise, default to the normal case of the frame pointer being
346 replaced by the stack pointer. */
348 #ifdef ELIMINABLE_REGS
351 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
354 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
356 /* Record the number of pending eliminations that have an offset not equal
357 to their initial offset. If nonzero, we use a new copy of each
358 replacement result in any insns encountered. */
359 int num_not_at_initial_offset;
361 /* Count the number of registers that we may be able to eliminate. */
362 static int num_eliminable;
363 /* And the number of registers that are equivalent to a constant that
364 can be eliminated to frame_pointer / arg_pointer + constant. */
365 static int num_eliminable_invariants;
367 /* For each label, we record the offset of each elimination. If we reach
368 a label by more than one path and an offset differs, we cannot do the
369 elimination. This information is indexed by the difference of the
370 number of the label and the first label number. We can't offset the
371 pointer itself as this can cause problems on machines with segmented
372 memory. The first table is an array of flags that records whether we
373 have yet encountered a label and the second table is an array of arrays,
374 one entry in the latter array for each elimination. */
376 static int first_label_num;
377 static char *offsets_known_at;
378 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
380 /* Number of labels in the current function. */
382 static int num_labels;
384 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
385 static void maybe_fix_stack_asms (void);
386 static void copy_reloads (struct insn_chain *);
387 static void calculate_needs_all_insns (int);
388 static int find_reg (struct insn_chain *, int);
389 static void find_reload_regs (struct insn_chain *);
390 static void select_reload_regs (void);
391 static void delete_caller_save_insns (void);
393 static void spill_failure (rtx, enum reg_class);
394 static void count_spilled_pseudo (int, int, int);
395 static void delete_dead_insn (rtx);
396 static void alter_reg (int, int, bool);
397 static void set_label_offsets (rtx, rtx, int);
398 static void check_eliminable_occurrences (rtx);
399 static void elimination_effects (rtx, enum machine_mode);
400 static int eliminate_regs_in_insn (rtx, int);
401 static void update_eliminable_offsets (void);
402 static void mark_not_eliminable (rtx, const_rtx, void *);
403 static void set_initial_elim_offsets (void);
404 static bool verify_initial_elim_offsets (void);
405 static void set_initial_label_offsets (void);
406 static void set_offsets_for_label (rtx);
407 static void init_elim_table (void);
408 static void update_eliminables (HARD_REG_SET *);
409 static void spill_hard_reg (unsigned int, int);
410 static int finish_spills (int);
411 static void scan_paradoxical_subregs (rtx);
412 static void count_pseudo (int);
413 static void order_regs_for_reload (struct insn_chain *);
414 static void reload_as_needed (int);
415 static void forget_old_reloads_1 (rtx, const_rtx, void *);
416 static void forget_marked_reloads (regset);
417 static int reload_reg_class_lower (const void *, const void *);
418 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
420 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
422 static int reload_reg_free_p (unsigned int, int, enum reload_type);
423 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
425 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
427 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
428 static int allocate_reload_reg (struct insn_chain *, int, int);
429 static int conflicts_with_override (rtx);
430 static void failed_reload (rtx, int);
431 static int set_reload_reg (int, int);
432 static void choose_reload_regs_init (struct insn_chain *, rtx *);
433 static void choose_reload_regs (struct insn_chain *);
434 static void merge_assigned_reloads (rtx);
435 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
437 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
439 static void do_input_reload (struct insn_chain *, struct reload *, int);
440 static void do_output_reload (struct insn_chain *, struct reload *, int);
441 static void emit_reload_insns (struct insn_chain *);
442 static void delete_output_reload (rtx, int, int, rtx);
443 static void delete_address_reloads (rtx, rtx);
444 static void delete_address_reloads_1 (rtx, rtx, rtx);
445 static rtx inc_for_reload (rtx, rtx, rtx, int);
447 static void add_auto_inc_notes (rtx, rtx);
449 static void copy_eh_notes (rtx, rtx);
450 static void substitute (rtx *, const_rtx, rtx);
451 static bool gen_reload_chain_without_interm_reg_p (int, int);
452 static int reloads_conflict (int, int);
453 static rtx gen_reload (rtx, rtx, int, enum reload_type);
454 static rtx emit_insn_if_valid_for_reload (rtx);
456 /* Initialize the reload pass. This is called at the beginning of compilation
457 and may be called again if the target is reinitialized. */
464 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
465 Set spill_indirect_levels to the number of levels such addressing is
466 permitted, zero if it is not permitted at all. */
469 = gen_rtx_MEM (Pmode,
472 LAST_VIRTUAL_REGISTER + 1),
474 spill_indirect_levels = 0;
476 while (memory_address_p (QImode, tem))
478 spill_indirect_levels++;
479 tem = gen_rtx_MEM (Pmode, tem);
482 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
484 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
485 indirect_symref_ok = memory_address_p (QImode, tem);
487 /* See if reg+reg is a valid (and offsettable) address. */
489 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
491 tem = gen_rtx_PLUS (Pmode,
492 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
493 gen_rtx_REG (Pmode, i));
495 /* This way, we make sure that reg+reg is an offsettable address. */
496 tem = plus_constant (tem, 4);
498 if (memory_address_p (QImode, tem))
500 double_reg_address_ok = 1;
505 /* Initialize obstack for our rtl allocation. */
506 gcc_obstack_init (&reload_obstack);
507 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0);
509 INIT_REG_SET (&spilled_pseudos);
510 INIT_REG_SET (&changed_allocation_pseudos);
511 INIT_REG_SET (&pseudos_counted);
514 /* List of insn chains that are currently unused. */
515 static struct insn_chain *unused_insn_chains = 0;
517 /* Allocate an empty insn_chain structure. */
519 new_insn_chain (void)
521 struct insn_chain *c;
523 if (unused_insn_chains == 0)
525 c = XOBNEW (&reload_obstack, struct insn_chain);
526 INIT_REG_SET (&c->live_throughout);
527 INIT_REG_SET (&c->dead_or_set);
531 c = unused_insn_chains;
532 unused_insn_chains = c->next;
534 c->is_caller_save_insn = 0;
535 c->need_operand_change = 0;
541 /* Small utility function to set all regs in hard reg set TO which are
542 allocated to pseudos in regset FROM. */
545 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
548 reg_set_iterator rsi;
550 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
552 int r = reg_renumber[regno];
556 /* reload_combine uses the information from DF_LIVE_IN,
557 which might still contain registers that have not
558 actually been allocated since they have an
560 gcc_assert (ira_conflicts_p || reload_completed);
563 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
567 /* Replace all pseudos found in LOC with their corresponding
571 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
584 unsigned int regno = REGNO (x);
586 if (regno < FIRST_PSEUDO_REGISTER)
589 x = eliminate_regs (x, mem_mode, usage);
593 replace_pseudos_in (loc, mem_mode, usage);
597 if (reg_equiv_constant[regno])
598 *loc = reg_equiv_constant[regno];
599 else if (reg_equiv_mem[regno])
600 *loc = reg_equiv_mem[regno];
601 else if (reg_equiv_address[regno])
602 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
605 gcc_assert (!REG_P (regno_reg_rtx[regno])
606 || REGNO (regno_reg_rtx[regno]) != regno);
607 *loc = regno_reg_rtx[regno];
612 else if (code == MEM)
614 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
618 /* Process each of our operands recursively. */
619 fmt = GET_RTX_FORMAT (code);
620 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
622 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
623 else if (*fmt == 'E')
624 for (j = 0; j < XVECLEN (x, i); j++)
625 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
628 /* Determine if the current function has an exception receiver block
629 that reaches the exit block via non-exceptional edges */
632 has_nonexceptional_receiver (void)
636 basic_block *tos, *worklist, bb;
638 /* If we're not optimizing, then just err on the safe side. */
642 /* First determine which blocks can reach exit via normal paths. */
643 tos = worklist = XNEWVEC (basic_block, n_basic_blocks + 1);
646 bb->flags &= ~BB_REACHABLE;
648 /* Place the exit block on our worklist. */
649 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
650 *tos++ = EXIT_BLOCK_PTR;
652 /* Iterate: find everything reachable from what we've already seen. */
653 while (tos != worklist)
657 FOR_EACH_EDGE (e, ei, bb->preds)
658 if (!(e->flags & EDGE_ABNORMAL))
660 basic_block src = e->src;
662 if (!(src->flags & BB_REACHABLE))
664 src->flags |= BB_REACHABLE;
671 /* Now see if there's a reachable block with an exceptional incoming
674 if (bb->flags & BB_REACHABLE)
675 FOR_EACH_EDGE (e, ei, bb->preds)
676 if (e->flags & EDGE_ABNORMAL)
679 /* No exceptional block reached exit unexceptionally. */
684 /* Global variables used by reload and its subroutines. */
686 /* Set during calculate_needs if an insn needs register elimination. */
687 static int something_needs_elimination;
688 /* Set during calculate_needs if an insn needs an operand changed. */
689 static int something_needs_operands_changed;
691 /* Nonzero means we couldn't get enough spill regs. */
694 /* Temporary array of pseudo-register number. */
695 static int *temp_pseudo_reg_arr;
697 /* Main entry point for the reload pass.
699 FIRST is the first insn of the function being compiled.
701 GLOBAL nonzero means we were called from global_alloc
702 and should attempt to reallocate any pseudoregs that we
703 displace from hard regs we will use for reloads.
704 If GLOBAL is zero, we do not have enough information to do that,
705 so any pseudo reg that is spilled must go to the stack.
707 Return value is nonzero if reload failed
708 and we must not do any more for this function. */
711 reload (rtx first, int global)
715 struct elim_table *ep;
718 /* Make sure even insns with volatile mem refs are recognizable. */
723 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
725 /* Make sure that the last insn in the chain
726 is not something that needs reloading. */
727 emit_note (NOTE_INSN_DELETED);
729 /* Enable find_equiv_reg to distinguish insns made by reload. */
730 reload_first_uid = get_max_uid ();
732 #ifdef SECONDARY_MEMORY_NEEDED
733 /* Initialize the secondary memory table. */
734 clear_secondary_mem ();
737 /* We don't have a stack slot for any spill reg yet. */
738 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
739 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
741 /* Initialize the save area information for caller-save, in case some
745 /* Compute which hard registers are now in use
746 as homes for pseudo registers.
747 This is done here rather than (eg) in global_alloc
748 because this point is reached even if not optimizing. */
749 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
752 /* A function that has a nonlocal label that can reach the exit
753 block via non-exceptional paths must save all call-saved
755 if (cfun->has_nonlocal_label
756 && has_nonexceptional_receiver ())
757 crtl->saves_all_registers = 1;
759 if (crtl->saves_all_registers)
760 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
761 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
762 df_set_regs_ever_live (i, true);
764 /* Find all the pseudo registers that didn't get hard regs
765 but do have known equivalent constants or memory slots.
766 These include parameters (known equivalent to parameter slots)
767 and cse'd or loop-moved constant memory addresses.
769 Record constant equivalents in reg_equiv_constant
770 so they will be substituted by find_reloads.
771 Record memory equivalents in reg_mem_equiv so they can
772 be substituted eventually by altering the REG-rtx's. */
774 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
775 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
776 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
777 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
778 reg_equiv_address = XCNEWVEC (rtx, max_regno);
779 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
780 reg_old_renumber = XCNEWVEC (short, max_regno);
781 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
782 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
783 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
785 CLEAR_HARD_REG_SET (bad_spill_regs_global);
787 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
788 to. Also find all paradoxical subregs and find largest such for
791 num_eliminable_invariants = 0;
792 for (insn = first; insn; insn = NEXT_INSN (insn))
794 rtx set = single_set (insn);
796 /* We may introduce USEs that we want to remove at the end, so
797 we'll mark them with QImode. Make sure there are no
798 previously-marked insns left by say regmove. */
799 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
800 && GET_MODE (insn) != VOIDmode)
801 PUT_MODE (insn, VOIDmode);
804 scan_paradoxical_subregs (PATTERN (insn));
806 if (set != 0 && REG_P (SET_DEST (set)))
808 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
814 i = REGNO (SET_DEST (set));
817 if (i <= LAST_VIRTUAL_REGISTER)
820 if (! function_invariant_p (x)
822 /* A function invariant is often CONSTANT_P but may
823 include a register. We promise to only pass
824 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
826 && LEGITIMATE_PIC_OPERAND_P (x)))
828 /* It can happen that a REG_EQUIV note contains a MEM
829 that is not a legitimate memory operand. As later
830 stages of reload assume that all addresses found
831 in the reg_equiv_* arrays were originally legitimate,
832 we ignore such REG_EQUIV notes. */
833 if (memory_operand (x, VOIDmode))
835 /* Always unshare the equivalence, so we can
836 substitute into this insn without touching the
838 reg_equiv_memory_loc[i] = copy_rtx (x);
840 else if (function_invariant_p (x))
842 if (GET_CODE (x) == PLUS)
844 /* This is PLUS of frame pointer and a constant,
845 and might be shared. Unshare it. */
846 reg_equiv_invariant[i] = copy_rtx (x);
847 num_eliminable_invariants++;
849 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
851 reg_equiv_invariant[i] = x;
852 num_eliminable_invariants++;
854 else if (LEGITIMATE_CONSTANT_P (x))
855 reg_equiv_constant[i] = x;
858 reg_equiv_memory_loc[i]
859 = force_const_mem (GET_MODE (SET_DEST (set)), x);
860 if (! reg_equiv_memory_loc[i])
861 reg_equiv_init[i] = NULL_RTX;
866 reg_equiv_init[i] = NULL_RTX;
871 reg_equiv_init[i] = NULL_RTX;
876 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
877 if (reg_equiv_init[i])
879 fprintf (dump_file, "init_insns for %u: ", i);
880 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
881 fprintf (dump_file, "\n");
886 first_label_num = get_first_label_num ();
887 num_labels = max_label_num () - first_label_num;
889 /* Allocate the tables used to store offset information at labels. */
890 /* We used to use alloca here, but the size of what it would try to
891 allocate would occasionally cause it to exceed the stack limit and
892 cause a core dump. */
893 offsets_known_at = XNEWVEC (char, num_labels);
894 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
896 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign
897 stack slots to the pseudos that lack hard regs or equivalents.
898 Do not touch virtual registers. */
900 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1);
901 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
902 temp_pseudo_reg_arr[n++] = i;
905 /* Ask IRA to order pseudo-registers for better stack slot
907 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_width);
909 for (i = 0; i < n; i++)
910 alter_reg (temp_pseudo_reg_arr[i], -1, false);
912 /* If we have some registers we think can be eliminated, scan all insns to
913 see if there is an insn that sets one of these registers to something
914 other than itself plus a constant. If so, the register cannot be
915 eliminated. Doing this scan here eliminates an extra pass through the
916 main reload loop in the most common case where register elimination
918 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
920 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
922 maybe_fix_stack_asms ();
924 insns_need_reload = 0;
925 something_needs_elimination = 0;
927 /* Initialize to -1, which means take the first spill register. */
930 /* Spill any hard regs that we know we can't eliminate. */
931 CLEAR_HARD_REG_SET (used_spill_regs);
932 /* There can be multiple ways to eliminate a register;
933 they should be listed adjacently.
934 Elimination for any register fails only if all possible ways fail. */
935 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
938 int can_eliminate = 0;
941 can_eliminate |= ep->can_eliminate;
944 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
946 spill_hard_reg (from, 1);
949 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
950 if (frame_pointer_needed)
951 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
953 finish_spills (global);
955 /* From now on, we may need to generate moves differently. We may also
956 allow modifications of insns which cause them to not be recognized.
957 Any such modifications will be cleaned up during reload itself. */
958 reload_in_progress = 1;
960 /* This loop scans the entire function each go-round
961 and repeats until one repetition spills no additional hard regs. */
964 int something_changed;
966 HOST_WIDE_INT starting_frame_size;
968 starting_frame_size = get_frame_size ();
970 set_initial_elim_offsets ();
971 set_initial_label_offsets ();
973 /* For each pseudo register that has an equivalent location defined,
974 try to eliminate any eliminable registers (such as the frame pointer)
975 assuming initial offsets for the replacement register, which
978 If the resulting location is directly addressable, substitute
979 the MEM we just got directly for the old REG.
981 If it is not addressable but is a constant or the sum of a hard reg
982 and constant, it is probably not addressable because the constant is
983 out of range, in that case record the address; we will generate
984 hairy code to compute the address in a register each time it is
985 needed. Similarly if it is a hard register, but one that is not
986 valid as an address register.
988 If the location is not addressable, but does not have one of the
989 above forms, assign a stack slot. We have to do this to avoid the
990 potential of producing lots of reloads if, e.g., a location involves
991 a pseudo that didn't get a hard register and has an equivalent memory
992 location that also involves a pseudo that didn't get a hard register.
994 Perhaps at some point we will improve reload_when_needed handling
995 so this problem goes away. But that's very hairy. */
997 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
998 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
1000 rtx x = eliminate_regs (reg_equiv_memory_loc[i], VOIDmode,
1003 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
1005 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
1006 else if (CONSTANT_P (XEXP (x, 0))
1007 || (REG_P (XEXP (x, 0))
1008 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
1009 || (GET_CODE (XEXP (x, 0)) == PLUS
1010 && REG_P (XEXP (XEXP (x, 0), 0))
1011 && (REGNO (XEXP (XEXP (x, 0), 0))
1012 < FIRST_PSEUDO_REGISTER)
1013 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
1014 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
1017 /* Make a new stack slot. Then indicate that something
1018 changed so we go back and recompute offsets for
1019 eliminable registers because the allocation of memory
1020 below might change some offset. reg_equiv_{mem,address}
1021 will be set up for this pseudo on the next pass around
1023 reg_equiv_memory_loc[i] = 0;
1024 reg_equiv_init[i] = 0;
1025 alter_reg (i, -1, true);
1029 if (caller_save_needed)
1030 setup_save_areas ();
1032 /* If we allocated another stack slot, redo elimination bookkeeping. */
1033 if (starting_frame_size != get_frame_size ())
1035 if (starting_frame_size && crtl->stack_alignment_needed)
1037 /* If we have a stack frame, we must align it now. The
1038 stack size may be a part of the offset computation for
1039 register elimination. So if this changes the stack size,
1040 then repeat the elimination bookkeeping. We don't
1041 realign when there is no stack, as that will cause a
1042 stack frame when none is needed should
1043 STARTING_FRAME_OFFSET not be already aligned to
1045 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed);
1046 if (starting_frame_size != get_frame_size ())
1050 if (caller_save_needed)
1052 save_call_clobbered_regs ();
1053 /* That might have allocated new insn_chain structures. */
1054 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1057 calculate_needs_all_insns (global);
1059 if (! ira_conflicts_p)
1060 /* Don't do it for IRA. We need this info because we don't
1061 change live_throughout and dead_or_set for chains when IRA
1063 CLEAR_REG_SET (&spilled_pseudos);
1067 something_changed = 0;
1069 /* If we allocated any new memory locations, make another pass
1070 since it might have changed elimination offsets. */
1071 if (starting_frame_size != get_frame_size ())
1072 something_changed = 1;
1074 /* Even if the frame size remained the same, we might still have
1075 changed elimination offsets, e.g. if find_reloads called
1076 force_const_mem requiring the back end to allocate a constant
1077 pool base register that needs to be saved on the stack. */
1078 else if (!verify_initial_elim_offsets ())
1079 something_changed = 1;
1082 HARD_REG_SET to_spill;
1083 CLEAR_HARD_REG_SET (to_spill);
1084 update_eliminables (&to_spill);
1085 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1087 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1088 if (TEST_HARD_REG_BIT (to_spill, i))
1090 spill_hard_reg (i, 1);
1093 /* Regardless of the state of spills, if we previously had
1094 a register that we thought we could eliminate, but now can
1095 not eliminate, we must run another pass.
1097 Consider pseudos which have an entry in reg_equiv_* which
1098 reference an eliminable register. We must make another pass
1099 to update reg_equiv_* so that we do not substitute in the
1100 old value from when we thought the elimination could be
1102 something_changed = 1;
1106 select_reload_regs ();
1110 if (insns_need_reload != 0 || did_spill)
1111 something_changed |= finish_spills (global);
1113 if (! something_changed)
1116 if (caller_save_needed)
1117 delete_caller_save_insns ();
1119 obstack_free (&reload_obstack, reload_firstobj);
1122 /* If global-alloc was run, notify it of any register eliminations we have
1125 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1126 if (ep->can_eliminate)
1127 mark_elimination (ep->from, ep->to);
1129 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1130 If that insn didn't set the register (i.e., it copied the register to
1131 memory), just delete that insn instead of the equivalencing insn plus
1132 anything now dead. If we call delete_dead_insn on that insn, we may
1133 delete the insn that actually sets the register if the register dies
1134 there and that is incorrect. */
1136 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1138 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1141 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1143 rtx equiv_insn = XEXP (list, 0);
1145 /* If we already deleted the insn or if it may trap, we can't
1146 delete it. The latter case shouldn't happen, but can
1147 if an insn has a variable address, gets a REG_EH_REGION
1148 note added to it, and then gets converted into a load
1149 from a constant address. */
1150 if (NOTE_P (equiv_insn)
1151 || can_throw_internal (equiv_insn))
1153 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1154 delete_dead_insn (equiv_insn);
1156 SET_INSN_DELETED (equiv_insn);
1161 /* Use the reload registers where necessary
1162 by generating move instructions to move the must-be-register
1163 values into or out of the reload registers. */
1165 if (insns_need_reload != 0 || something_needs_elimination
1166 || something_needs_operands_changed)
1168 HOST_WIDE_INT old_frame_size = get_frame_size ();
1170 reload_as_needed (global);
1172 gcc_assert (old_frame_size == get_frame_size ());
1174 gcc_assert (verify_initial_elim_offsets ());
1177 /* If we were able to eliminate the frame pointer, show that it is no
1178 longer live at the start of any basic block. If it ls live by
1179 virtue of being in a pseudo, that pseudo will be marked live
1180 and hence the frame pointer will be known to be live via that
1183 if (! frame_pointer_needed)
1185 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1187 /* Come here (with failure set nonzero) if we can't get enough spill
1191 CLEAR_REG_SET (&changed_allocation_pseudos);
1192 CLEAR_REG_SET (&spilled_pseudos);
1193 reload_in_progress = 0;
1195 /* Now eliminate all pseudo regs by modifying them into
1196 their equivalent memory references.
1197 The REG-rtx's for the pseudos are modified in place,
1198 so all insns that used to refer to them now refer to memory.
1200 For a reg that has a reg_equiv_address, all those insns
1201 were changed by reloading so that no insns refer to it any longer;
1202 but the DECL_RTL of a variable decl may refer to it,
1203 and if so this causes the debugging info to mention the variable. */
1205 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1209 if (reg_equiv_mem[i])
1210 addr = XEXP (reg_equiv_mem[i], 0);
1212 if (reg_equiv_address[i])
1213 addr = reg_equiv_address[i];
1217 if (reg_renumber[i] < 0)
1219 rtx reg = regno_reg_rtx[i];
1221 REG_USERVAR_P (reg) = 0;
1222 PUT_CODE (reg, MEM);
1223 XEXP (reg, 0) = addr;
1224 if (reg_equiv_memory_loc[i])
1225 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1228 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1229 MEM_ATTRS (reg) = 0;
1231 MEM_NOTRAP_P (reg) = 1;
1233 else if (reg_equiv_mem[i])
1234 XEXP (reg_equiv_mem[i], 0) = addr;
1238 /* We must set reload_completed now since the cleanup_subreg_operands call
1239 below will re-recognize each insn and reload may have generated insns
1240 which are only valid during and after reload. */
1241 reload_completed = 1;
1243 /* Make a pass over all the insns and delete all USEs which we inserted
1244 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1245 notes. Delete all CLOBBER insns, except those that refer to the return
1246 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1247 from misarranging variable-array code, and simplify (subreg (reg))
1248 operands. Strip and regenerate REG_INC notes that may have been moved
1251 for (insn = first; insn; insn = NEXT_INSN (insn))
1257 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1258 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1260 if ((GET_CODE (PATTERN (insn)) == USE
1261 /* We mark with QImode USEs introduced by reload itself. */
1262 && (GET_MODE (insn) == QImode
1263 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1264 || (GET_CODE (PATTERN (insn)) == CLOBBER
1265 && (!MEM_P (XEXP (PATTERN (insn), 0))
1266 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1267 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1268 && XEXP (XEXP (PATTERN (insn), 0), 0)
1269 != stack_pointer_rtx))
1270 && (!REG_P (XEXP (PATTERN (insn), 0))
1271 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1277 /* Some CLOBBERs may survive until here and still reference unassigned
1278 pseudos with const equivalent, which may in turn cause ICE in later
1279 passes if the reference remains in place. */
1280 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1281 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1282 VOIDmode, PATTERN (insn));
1284 /* Discard obvious no-ops, even without -O. This optimization
1285 is fast and doesn't interfere with debugging. */
1286 if (NONJUMP_INSN_P (insn)
1287 && GET_CODE (PATTERN (insn)) == SET
1288 && REG_P (SET_SRC (PATTERN (insn)))
1289 && REG_P (SET_DEST (PATTERN (insn)))
1290 && (REGNO (SET_SRC (PATTERN (insn)))
1291 == REGNO (SET_DEST (PATTERN (insn)))))
1297 pnote = ®_NOTES (insn);
1300 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1301 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1302 || REG_NOTE_KIND (*pnote) == REG_INC)
1303 *pnote = XEXP (*pnote, 1);
1305 pnote = &XEXP (*pnote, 1);
1309 add_auto_inc_notes (insn, PATTERN (insn));
1312 /* Simplify (subreg (reg)) if it appears as an operand. */
1313 cleanup_subreg_operands (insn);
1315 /* Clean up invalid ASMs so that they don't confuse later passes.
1317 if (asm_noperands (PATTERN (insn)) >= 0)
1319 extract_insn (insn);
1320 if (!constrain_operands (1))
1322 error_for_asm (insn,
1323 "%<asm%> operand has impossible constraints");
1330 /* If we are doing generic stack checking, give a warning if this
1331 function's frame size is larger than we expect. */
1332 if (flag_stack_check == GENERIC_STACK_CHECK)
1334 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1335 static int verbose_warned = 0;
1337 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1338 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1339 size += UNITS_PER_WORD;
1341 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1343 warning (0, "frame size too large for reliable stack checking");
1344 if (! verbose_warned)
1346 warning (0, "try reducing the number of local variables");
1352 /* Indicate that we no longer have known memory locations or constants. */
1353 if (reg_equiv_constant)
1354 free (reg_equiv_constant);
1355 if (reg_equiv_invariant)
1356 free (reg_equiv_invariant);
1357 reg_equiv_constant = 0;
1358 reg_equiv_invariant = 0;
1359 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1360 reg_equiv_memory_loc = 0;
1362 free (temp_pseudo_reg_arr);
1364 if (offsets_known_at)
1365 free (offsets_known_at);
1369 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1370 if (reg_equiv_alt_mem_list[i])
1371 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1372 free (reg_equiv_alt_mem_list);
1374 free (reg_equiv_mem);
1376 free (reg_equiv_address);
1377 free (reg_max_ref_width);
1378 free (reg_old_renumber);
1379 free (pseudo_previous_regs);
1380 free (pseudo_forbidden_regs);
1382 CLEAR_HARD_REG_SET (used_spill_regs);
1383 for (i = 0; i < n_spills; i++)
1384 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1386 /* Free all the insn_chain structures at once. */
1387 obstack_free (&reload_obstack, reload_startobj);
1388 unused_insn_chains = 0;
1389 fixup_abnormal_edges ();
1391 /* Replacing pseudos with their memory equivalents might have
1392 created shared rtx. Subsequent passes would get confused
1393 by this, so unshare everything here. */
1394 unshare_all_rtl_again (first);
1396 #ifdef STACK_BOUNDARY
1397 /* init_emit has set the alignment of the hard frame pointer
1398 to STACK_BOUNDARY. It is very likely no longer valid if
1399 the hard frame pointer was used for register allocation. */
1400 if (!frame_pointer_needed)
1401 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1407 /* Yet another special case. Unfortunately, reg-stack forces people to
1408 write incorrect clobbers in asm statements. These clobbers must not
1409 cause the register to appear in bad_spill_regs, otherwise we'll call
1410 fatal_insn later. We clear the corresponding regnos in the live
1411 register sets to avoid this.
1412 The whole thing is rather sick, I'm afraid. */
1415 maybe_fix_stack_asms (void)
1418 const char *constraints[MAX_RECOG_OPERANDS];
1419 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1420 struct insn_chain *chain;
1422 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1425 HARD_REG_SET clobbered, allowed;
1428 if (! INSN_P (chain->insn)
1429 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1431 pat = PATTERN (chain->insn);
1432 if (GET_CODE (pat) != PARALLEL)
1435 CLEAR_HARD_REG_SET (clobbered);
1436 CLEAR_HARD_REG_SET (allowed);
1438 /* First, make a mask of all stack regs that are clobbered. */
1439 for (i = 0; i < XVECLEN (pat, 0); i++)
1441 rtx t = XVECEXP (pat, 0, i);
1442 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1443 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1446 /* Get the operand values and constraints out of the insn. */
1447 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1448 constraints, operand_mode, NULL);
1450 /* For every operand, see what registers are allowed. */
1451 for (i = 0; i < noperands; i++)
1453 const char *p = constraints[i];
1454 /* For every alternative, we compute the class of registers allowed
1455 for reloading in CLS, and merge its contents into the reg set
1457 int cls = (int) NO_REGS;
1463 if (c == '\0' || c == ',' || c == '#')
1465 /* End of one alternative - mark the regs in the current
1466 class, and reset the class. */
1467 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1473 } while (c != '\0' && c != ',');
1481 case '=': case '+': case '*': case '%': case '?': case '!':
1482 case '0': case '1': case '2': case '3': case '4': case '<':
1483 case '>': case 'V': case 'o': case '&': case 'E': case 'F':
1484 case 's': case 'i': case 'n': case 'X': case 'I': case 'J':
1485 case 'K': case 'L': case 'M': case 'N': case 'O': case 'P':
1486 case TARGET_MEM_CONSTRAINT:
1490 cls = (int) reg_class_subunion[cls]
1491 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1496 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1500 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1501 cls = (int) reg_class_subunion[cls]
1502 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1504 cls = (int) reg_class_subunion[cls]
1505 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1507 p += CONSTRAINT_LEN (c, p);
1510 /* Those of the registers which are clobbered, but allowed by the
1511 constraints, must be usable as reload registers. So clear them
1512 out of the life information. */
1513 AND_HARD_REG_SET (allowed, clobbered);
1514 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1515 if (TEST_HARD_REG_BIT (allowed, i))
1517 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1518 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1525 /* Copy the global variables n_reloads and rld into the corresponding elts
1528 copy_reloads (struct insn_chain *chain)
1530 chain->n_reloads = n_reloads;
1531 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads);
1532 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1533 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1536 /* Walk the chain of insns, and determine for each whether it needs reloads
1537 and/or eliminations. Build the corresponding insns_need_reload list, and
1538 set something_needs_elimination as appropriate. */
1540 calculate_needs_all_insns (int global)
1542 struct insn_chain **pprev_reload = &insns_need_reload;
1543 struct insn_chain *chain, *next = 0;
1545 something_needs_elimination = 0;
1547 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0);
1548 for (chain = reload_insn_chain; chain != 0; chain = next)
1550 rtx insn = chain->insn;
1554 /* Clear out the shortcuts. */
1555 chain->n_reloads = 0;
1556 chain->need_elim = 0;
1557 chain->need_reload = 0;
1558 chain->need_operand_change = 0;
1560 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1561 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1562 what effects this has on the known offsets at labels. */
1564 if (LABEL_P (insn) || JUMP_P (insn)
1565 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1566 set_label_offsets (insn, insn, 0);
1570 rtx old_body = PATTERN (insn);
1571 int old_code = INSN_CODE (insn);
1572 rtx old_notes = REG_NOTES (insn);
1573 int did_elimination = 0;
1574 int operands_changed = 0;
1575 rtx set = single_set (insn);
1577 /* Skip insns that only set an equivalence. */
1578 if (set && REG_P (SET_DEST (set))
1579 && reg_renumber[REGNO (SET_DEST (set))] < 0
1580 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1581 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1582 && reg_equiv_init[REGNO (SET_DEST (set))])
1585 /* If needed, eliminate any eliminable registers. */
1586 if (num_eliminable || num_eliminable_invariants)
1587 did_elimination = eliminate_regs_in_insn (insn, 0);
1589 /* Analyze the instruction. */
1590 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1591 global, spill_reg_order);
1593 /* If a no-op set needs more than one reload, this is likely
1594 to be something that needs input address reloads. We
1595 can't get rid of this cleanly later, and it is of no use
1596 anyway, so discard it now.
1597 We only do this when expensive_optimizations is enabled,
1598 since this complements reload inheritance / output
1599 reload deletion, and it can make debugging harder. */
1600 if (flag_expensive_optimizations && n_reloads > 1)
1602 rtx set = single_set (insn);
1605 ((SET_SRC (set) == SET_DEST (set)
1606 && REG_P (SET_SRC (set))
1607 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1608 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set))
1609 && reg_renumber[REGNO (SET_SRC (set))] < 0
1610 && reg_renumber[REGNO (SET_DEST (set))] < 0
1611 && reg_equiv_memory_loc[REGNO (SET_SRC (set))] != NULL
1612 && reg_equiv_memory_loc[REGNO (SET_DEST (set))] != NULL
1613 && rtx_equal_p (reg_equiv_memory_loc
1614 [REGNO (SET_SRC (set))],
1615 reg_equiv_memory_loc
1616 [REGNO (SET_DEST (set))]))))
1618 if (ira_conflicts_p)
1619 /* Inform IRA about the insn deletion. */
1620 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)),
1621 REGNO (SET_SRC (set)));
1623 /* Delete it from the reload chain. */
1625 chain->prev->next = next;
1627 reload_insn_chain = next;
1629 next->prev = chain->prev;
1630 chain->next = unused_insn_chains;
1631 unused_insn_chains = chain;
1636 update_eliminable_offsets ();
1638 /* Remember for later shortcuts which insns had any reloads or
1639 register eliminations. */
1640 chain->need_elim = did_elimination;
1641 chain->need_reload = n_reloads > 0;
1642 chain->need_operand_change = operands_changed;
1644 /* Discard any register replacements done. */
1645 if (did_elimination)
1647 obstack_free (&reload_obstack, reload_insn_firstobj);
1648 PATTERN (insn) = old_body;
1649 INSN_CODE (insn) = old_code;
1650 REG_NOTES (insn) = old_notes;
1651 something_needs_elimination = 1;
1654 something_needs_operands_changed |= operands_changed;
1658 copy_reloads (chain);
1659 *pprev_reload = chain;
1660 pprev_reload = &chain->next_need_reload;
1667 /* Comparison function for qsort to decide which of two reloads
1668 should be handled first. *P1 and *P2 are the reload numbers. */
1671 reload_reg_class_lower (const void *r1p, const void *r2p)
1673 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1676 /* Consider required reloads before optional ones. */
1677 t = rld[r1].optional - rld[r2].optional;
1681 /* Count all solitary classes before non-solitary ones. */
1682 t = ((reg_class_size[(int) rld[r2].rclass] == 1)
1683 - (reg_class_size[(int) rld[r1].rclass] == 1));
1687 /* Aside from solitaires, consider all multi-reg groups first. */
1688 t = rld[r2].nregs - rld[r1].nregs;
1692 /* Consider reloads in order of increasing reg-class number. */
1693 t = (int) rld[r1].rclass - (int) rld[r2].rclass;
1697 /* If reloads are equally urgent, sort by reload number,
1698 so that the results of qsort leave nothing to chance. */
1702 /* The cost of spilling each hard reg. */
1703 static int spill_cost[FIRST_PSEUDO_REGISTER];
1705 /* When spilling multiple hard registers, we use SPILL_COST for the first
1706 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1707 only the first hard reg for a multi-reg pseudo. */
1708 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1710 /* Map of hard regno to pseudo regno currently occupying the hard
1712 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER];
1714 /* Update the spill cost arrays, considering that pseudo REG is live. */
1717 count_pseudo (int reg)
1719 int freq = REG_FREQ (reg);
1720 int r = reg_renumber[reg];
1723 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1724 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1725 /* Ignore spilled pseudo-registers which can be here only if IRA
1727 || (ira_conflicts_p && r < 0))
1730 SET_REGNO_REG_SET (&pseudos_counted, reg);
1732 gcc_assert (r >= 0);
1734 spill_add_cost[r] += freq;
1735 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1738 hard_regno_to_pseudo_regno[r + nregs] = reg;
1739 spill_cost[r + nregs] += freq;
1743 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1744 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1747 order_regs_for_reload (struct insn_chain *chain)
1750 HARD_REG_SET used_by_pseudos;
1751 HARD_REG_SET used_by_pseudos2;
1752 reg_set_iterator rsi;
1754 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1756 memset (spill_cost, 0, sizeof spill_cost);
1757 memset (spill_add_cost, 0, sizeof spill_add_cost);
1758 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1759 hard_regno_to_pseudo_regno[i] = -1;
1761 /* Count number of uses of each hard reg by pseudo regs allocated to it
1762 and then order them by decreasing use. First exclude hard registers
1763 that are live in or across this insn. */
1765 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1766 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1767 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1768 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1770 /* Now find out which pseudos are allocated to it, and update
1772 CLEAR_REG_SET (&pseudos_counted);
1774 EXECUTE_IF_SET_IN_REG_SET
1775 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1779 EXECUTE_IF_SET_IN_REG_SET
1780 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1784 CLEAR_REG_SET (&pseudos_counted);
1787 /* Vector of reload-numbers showing the order in which the reloads should
1789 static short reload_order[MAX_RELOADS];
1791 /* This is used to keep track of the spill regs used in one insn. */
1792 static HARD_REG_SET used_spill_regs_local;
1794 /* We decided to spill hard register SPILLED, which has a size of
1795 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1796 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1797 update SPILL_COST/SPILL_ADD_COST. */
1800 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1802 int freq = REG_FREQ (reg);
1803 int r = reg_renumber[reg];
1804 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1806 /* Ignore spilled pseudo-registers which can be here only if IRA is
1808 if ((ira_conflicts_p && r < 0)
1809 || REGNO_REG_SET_P (&spilled_pseudos, reg)
1810 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1813 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1815 spill_add_cost[r] -= freq;
1818 hard_regno_to_pseudo_regno[r + nregs] = -1;
1819 spill_cost[r + nregs] -= freq;
1823 /* Find reload register to use for reload number ORDER. */
1826 find_reg (struct insn_chain *chain, int order)
1828 int rnum = reload_order[order];
1829 struct reload *rl = rld + rnum;
1830 int best_cost = INT_MAX;
1832 unsigned int i, j, n;
1834 HARD_REG_SET not_usable;
1835 HARD_REG_SET used_by_other_reload;
1836 reg_set_iterator rsi;
1837 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1838 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER];
1840 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1841 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1842 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->rclass]);
1844 CLEAR_HARD_REG_SET (used_by_other_reload);
1845 for (k = 0; k < order; k++)
1847 int other = reload_order[k];
1849 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1850 for (j = 0; j < rld[other].nregs; j++)
1851 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1854 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1856 #ifdef REG_ALLOC_ORDER
1857 unsigned int regno = reg_alloc_order[i];
1859 unsigned int regno = i;
1862 if (! TEST_HARD_REG_BIT (not_usable, regno)
1863 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1864 && HARD_REGNO_MODE_OK (regno, rl->mode))
1866 int this_cost = spill_cost[regno];
1868 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1870 for (j = 1; j < this_nregs; j++)
1872 this_cost += spill_add_cost[regno + j];
1873 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1874 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1880 if (ira_conflicts_p)
1882 /* Ask IRA to find a better pseudo-register for
1884 for (n = j = 0; j < this_nregs; j++)
1886 int r = hard_regno_to_pseudo_regno[regno + j];
1890 if (n == 0 || regno_pseudo_regs[n - 1] != r)
1891 regno_pseudo_regs[n++] = r;
1893 regno_pseudo_regs[n++] = -1;
1895 || ira_better_spill_reload_regno_p (regno_pseudo_regs,
1896 best_regno_pseudo_regs,
1903 best_regno_pseudo_regs[j] = regno_pseudo_regs[j];
1904 if (regno_pseudo_regs[j] < 0)
1911 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1913 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1915 if (this_cost < best_cost
1916 /* Among registers with equal cost, prefer caller-saved ones, or
1917 use REG_ALLOC_ORDER if it is defined. */
1918 || (this_cost == best_cost
1919 #ifdef REG_ALLOC_ORDER
1920 && (inv_reg_alloc_order[regno]
1921 < inv_reg_alloc_order[best_reg])
1923 && call_used_regs[regno]
1924 && ! call_used_regs[best_reg]
1929 best_cost = this_cost;
1937 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1939 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1940 rl->regno = best_reg;
1942 EXECUTE_IF_SET_IN_REG_SET
1943 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1945 count_spilled_pseudo (best_reg, rl->nregs, j);
1948 EXECUTE_IF_SET_IN_REG_SET
1949 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1951 count_spilled_pseudo (best_reg, rl->nregs, j);
1954 for (i = 0; i < rl->nregs; i++)
1956 gcc_assert (spill_cost[best_reg + i] == 0);
1957 gcc_assert (spill_add_cost[best_reg + i] == 0);
1958 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1);
1959 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1964 /* Find more reload regs to satisfy the remaining need of an insn, which
1966 Do it by ascending class number, since otherwise a reg
1967 might be spilled for a big class and might fail to count
1968 for a smaller class even though it belongs to that class. */
1971 find_reload_regs (struct insn_chain *chain)
1975 /* In order to be certain of getting the registers we need,
1976 we must sort the reloads into order of increasing register class.
1977 Then our grabbing of reload registers will parallel the process
1978 that provided the reload registers. */
1979 for (i = 0; i < chain->n_reloads; i++)
1981 /* Show whether this reload already has a hard reg. */
1982 if (chain->rld[i].reg_rtx)
1984 int regno = REGNO (chain->rld[i].reg_rtx);
1985 chain->rld[i].regno = regno;
1987 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1990 chain->rld[i].regno = -1;
1991 reload_order[i] = i;
1994 n_reloads = chain->n_reloads;
1995 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1997 CLEAR_HARD_REG_SET (used_spill_regs_local);
2000 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
2002 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
2004 /* Compute the order of preference for hard registers to spill. */
2006 order_regs_for_reload (chain);
2008 for (i = 0; i < n_reloads; i++)
2010 int r = reload_order[i];
2012 /* Ignore reloads that got marked inoperative. */
2013 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
2014 && ! rld[r].optional
2015 && rld[r].regno == -1)
2016 if (! find_reg (chain, i))
2019 fprintf (dump_file, "reload failure for reload %d\n", r);
2020 spill_failure (chain->insn, rld[r].rclass);
2026 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
2027 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
2029 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
2033 select_reload_regs (void)
2035 struct insn_chain *chain;
2037 /* Try to satisfy the needs for each insn. */
2038 for (chain = insns_need_reload; chain != 0;
2039 chain = chain->next_need_reload)
2040 find_reload_regs (chain);
2043 /* Delete all insns that were inserted by emit_caller_save_insns during
2046 delete_caller_save_insns (void)
2048 struct insn_chain *c = reload_insn_chain;
2052 while (c != 0 && c->is_caller_save_insn)
2054 struct insn_chain *next = c->next;
2057 if (c == reload_insn_chain)
2058 reload_insn_chain = next;
2062 next->prev = c->prev;
2064 c->prev->next = next;
2065 c->next = unused_insn_chains;
2066 unused_insn_chains = c;
2074 /* Handle the failure to find a register to spill.
2075 INSN should be one of the insns which needed this particular spill reg. */
2078 spill_failure (rtx insn, enum reg_class rclass)
2080 if (asm_noperands (PATTERN (insn)) >= 0)
2081 error_for_asm (insn, "can't find a register in class %qs while "
2082 "reloading %<asm%>",
2083 reg_class_names[rclass]);
2086 error ("unable to find a register to spill in class %qs",
2087 reg_class_names[rclass]);
2091 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
2092 debug_reload_to_stream (dump_file);
2094 fatal_insn ("this is the insn:", insn);
2098 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2099 data that is dead in INSN. */
2102 delete_dead_insn (rtx insn)
2104 rtx prev = prev_real_insn (insn);
2107 /* If the previous insn sets a register that dies in our insn, delete it
2109 if (prev && GET_CODE (PATTERN (prev)) == SET
2110 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2111 && reg_mentioned_p (prev_dest, PATTERN (insn))
2112 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2113 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2114 delete_dead_insn (prev);
2116 SET_INSN_DELETED (insn);
2119 /* Modify the home of pseudo-reg I.
2120 The new home is present in reg_renumber[I].
2122 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2123 or it may be -1, meaning there is none or it is not relevant.
2124 This is used so that all pseudos spilled from a given hard reg
2125 can share one stack slot. */
2128 alter_reg (int i, int from_reg, bool dont_share_p)
2130 /* When outputting an inline function, this can happen
2131 for a reg that isn't actually used. */
2132 if (regno_reg_rtx[i] == 0)
2135 /* If the reg got changed to a MEM at rtl-generation time,
2137 if (!REG_P (regno_reg_rtx[i]))
2140 /* Modify the reg-rtx to contain the new hard reg
2141 number or else to contain its pseudo reg number. */
2142 SET_REGNO (regno_reg_rtx[i],
2143 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2145 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2146 allocate a stack slot for it. */
2148 if (reg_renumber[i] < 0
2149 && REG_N_REFS (i) > 0
2150 && reg_equiv_constant[i] == 0
2151 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2152 && reg_equiv_memory_loc[i] == 0)
2155 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2156 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2157 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2158 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2159 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2162 if (ira_conflicts_p)
2164 /* Mark the spill for IRA. */
2165 SET_REGNO_REG_SET (&spilled_pseudos, i);
2167 x = ira_reuse_stack_slot (i, inherent_size, total_size);
2173 /* Each pseudo reg has an inherent size which comes from its own mode,
2174 and a total size which provides room for paradoxical subregs
2175 which refer to the pseudo reg in wider modes.
2177 We can use a slot already allocated if it provides both
2178 enough inherent space and enough total space.
2179 Otherwise, we allocate a new slot, making sure that it has no less
2180 inherent space, and no less total space, then the previous slot. */
2181 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p))
2185 /* No known place to spill from => no slot to reuse. */
2186 x = assign_stack_local (mode, total_size,
2187 min_align > inherent_align
2188 || total_size > inherent_size ? -1 : 0);
2192 /* Cancel the big-endian correction done in assign_stack_local.
2193 Get the address of the beginning of the slot. This is so we
2194 can do a big-endian correction unconditionally below. */
2195 if (BYTES_BIG_ENDIAN)
2197 adjust = inherent_size - total_size;
2200 = adjust_address_nv (x, mode_for_size (total_size
2206 if (! dont_share_p && ira_conflicts_p)
2207 /* Inform IRA about allocation a new stack slot. */
2208 ira_mark_new_stack_slot (stack_slot, i, total_size);
2211 /* Reuse a stack slot if possible. */
2212 else if (spill_stack_slot[from_reg] != 0
2213 && spill_stack_slot_width[from_reg] >= total_size
2214 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2216 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2217 x = spill_stack_slot[from_reg];
2219 /* Allocate a bigger slot. */
2222 /* Compute maximum size needed, both for inherent size
2223 and for total size. */
2226 if (spill_stack_slot[from_reg])
2228 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2230 mode = GET_MODE (spill_stack_slot[from_reg]);
2231 if (spill_stack_slot_width[from_reg] > total_size)
2232 total_size = spill_stack_slot_width[from_reg];
2233 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2234 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2237 /* Make a slot with that size. */
2238 x = assign_stack_local (mode, total_size,
2239 min_align > inherent_align
2240 || total_size > inherent_size ? -1 : 0);
2243 /* Cancel the big-endian correction done in assign_stack_local.
2244 Get the address of the beginning of the slot. This is so we
2245 can do a big-endian correction unconditionally below. */
2246 if (BYTES_BIG_ENDIAN)
2248 adjust = GET_MODE_SIZE (mode) - total_size;
2251 = adjust_address_nv (x, mode_for_size (total_size
2257 spill_stack_slot[from_reg] = stack_slot;
2258 spill_stack_slot_width[from_reg] = total_size;
2261 /* On a big endian machine, the "address" of the slot
2262 is the address of the low part that fits its inherent mode. */
2263 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2264 adjust += (total_size - inherent_size);
2266 /* If we have any adjustment to make, or if the stack slot is the
2267 wrong mode, make a new stack slot. */
2268 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2270 /* Set all of the memory attributes as appropriate for a spill. */
2271 set_mem_attrs_for_spill (x);
2273 /* Save the stack slot for later. */
2274 reg_equiv_memory_loc[i] = x;
2278 /* Mark the slots in regs_ever_live for the hard regs used by
2279 pseudo-reg number REGNO, accessed in MODE. */
2282 mark_home_live_1 (int regno, enum machine_mode mode)
2286 i = reg_renumber[regno];
2289 lim = end_hard_regno (mode, i);
2291 df_set_regs_ever_live(i++, true);
2294 /* Mark the slots in regs_ever_live for the hard regs
2295 used by pseudo-reg number REGNO. */
2298 mark_home_live (int regno)
2300 if (reg_renumber[regno] >= 0)
2301 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2304 /* This function handles the tracking of elimination offsets around branches.
2306 X is a piece of RTL being scanned.
2308 INSN is the insn that it came from, if any.
2310 INITIAL_P is nonzero if we are to set the offset to be the initial
2311 offset and zero if we are setting the offset of the label to be the
2315 set_label_offsets (rtx x, rtx insn, int initial_p)
2317 enum rtx_code code = GET_CODE (x);
2320 struct elim_table *p;
2325 if (LABEL_REF_NONLOCAL_P (x))
2330 /* ... fall through ... */
2333 /* If we know nothing about this label, set the desired offsets. Note
2334 that this sets the offset at a label to be the offset before a label
2335 if we don't know anything about the label. This is not correct for
2336 the label after a BARRIER, but is the best guess we can make. If
2337 we guessed wrong, we will suppress an elimination that might have
2338 been possible had we been able to guess correctly. */
2340 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2342 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2343 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2344 = (initial_p ? reg_eliminate[i].initial_offset
2345 : reg_eliminate[i].offset);
2346 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2349 /* Otherwise, if this is the definition of a label and it is
2350 preceded by a BARRIER, set our offsets to the known offset of
2354 && (tem = prev_nonnote_insn (insn)) != 0
2356 set_offsets_for_label (insn);
2358 /* If neither of the above cases is true, compare each offset
2359 with those previously recorded and suppress any eliminations
2360 where the offsets disagree. */
2362 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2363 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2364 != (initial_p ? reg_eliminate[i].initial_offset
2365 : reg_eliminate[i].offset))
2366 reg_eliminate[i].can_eliminate = 0;
2371 set_label_offsets (PATTERN (insn), insn, initial_p);
2373 /* ... fall through ... */
2377 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2378 to indirectly and hence must have all eliminations at their
2380 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2381 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2382 set_label_offsets (XEXP (tem, 0), insn, 1);
2388 /* Each of the labels in the parallel or address vector must be
2389 at their initial offsets. We want the first field for PARALLEL
2390 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2392 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2393 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2398 /* We only care about setting PC. If the source is not RETURN,
2399 IF_THEN_ELSE, or a label, disable any eliminations not at
2400 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2401 isn't one of those possibilities. For branches to a label,
2402 call ourselves recursively.
2404 Note that this can disable elimination unnecessarily when we have
2405 a non-local goto since it will look like a non-constant jump to
2406 someplace in the current function. This isn't a significant
2407 problem since such jumps will normally be when all elimination
2408 pairs are back to their initial offsets. */
2410 if (SET_DEST (x) != pc_rtx)
2413 switch (GET_CODE (SET_SRC (x)))
2420 set_label_offsets (SET_SRC (x), insn, initial_p);
2424 tem = XEXP (SET_SRC (x), 1);
2425 if (GET_CODE (tem) == LABEL_REF)
2426 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2427 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2430 tem = XEXP (SET_SRC (x), 2);
2431 if (GET_CODE (tem) == LABEL_REF)
2432 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2433 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2441 /* If we reach here, all eliminations must be at their initial
2442 offset because we are doing a jump to a variable address. */
2443 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2444 if (p->offset != p->initial_offset)
2445 p->can_eliminate = 0;
2453 /* Scan X and replace any eliminable registers (such as fp) with a
2454 replacement (such as sp), plus an offset.
2456 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2457 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2458 MEM, we are allowed to replace a sum of a register and the constant zero
2459 with the register, which we cannot do outside a MEM. In addition, we need
2460 to record the fact that a register is referenced outside a MEM.
2462 If INSN is an insn, it is the insn containing X. If we replace a REG
2463 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2464 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2465 the REG is being modified.
2467 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2468 That's used when we eliminate in expressions stored in notes.
2469 This means, do not set ref_outside_mem even if the reference
2472 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2473 replacements done assuming all offsets are at their initial values. If
2474 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2475 encounter, return the actual location so that find_reloads will do
2476 the proper thing. */
2479 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2480 bool may_use_invariant)
2482 enum rtx_code code = GET_CODE (x);
2483 struct elim_table *ep;
2490 if (! current_function_decl)
2513 /* First handle the case where we encounter a bare register that
2514 is eliminable. Replace it with a PLUS. */
2515 if (regno < FIRST_PSEUDO_REGISTER)
2517 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2519 if (ep->from_rtx == x && ep->can_eliminate)
2520 return plus_constant (ep->to_rtx, ep->previous_offset);
2523 else if (reg_renumber && reg_renumber[regno] < 0
2524 && reg_equiv_invariant && reg_equiv_invariant[regno])
2526 if (may_use_invariant)
2527 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2528 mem_mode, insn, true);
2529 /* There exists at least one use of REGNO that cannot be
2530 eliminated. Prevent the defining insn from being deleted. */
2531 reg_equiv_init[regno] = NULL_RTX;
2532 alter_reg (regno, -1, true);
2536 /* You might think handling MINUS in a manner similar to PLUS is a
2537 good idea. It is not. It has been tried multiple times and every
2538 time the change has had to have been reverted.
2540 Other parts of reload know a PLUS is special (gen_reload for example)
2541 and require special code to handle code a reloaded PLUS operand.
2543 Also consider backends where the flags register is clobbered by a
2544 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2545 lea instruction comes to mind). If we try to reload a MINUS, we
2546 may kill the flags register that was holding a useful value.
2548 So, please before trying to handle MINUS, consider reload as a
2549 whole instead of this little section as well as the backend issues. */
2551 /* If this is the sum of an eliminable register and a constant, rework
2553 if (REG_P (XEXP (x, 0))
2554 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2555 && CONSTANT_P (XEXP (x, 1)))
2557 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2559 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2561 /* The only time we want to replace a PLUS with a REG (this
2562 occurs when the constant operand of the PLUS is the negative
2563 of the offset) is when we are inside a MEM. We won't want
2564 to do so at other times because that would change the
2565 structure of the insn in a way that reload can't handle.
2566 We special-case the commonest situation in
2567 eliminate_regs_in_insn, so just replace a PLUS with a
2568 PLUS here, unless inside a MEM. */
2569 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2570 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2573 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2574 plus_constant (XEXP (x, 1),
2575 ep->previous_offset));
2578 /* If the register is not eliminable, we are done since the other
2579 operand is a constant. */
2583 /* If this is part of an address, we want to bring any constant to the
2584 outermost PLUS. We will do this by doing register replacement in
2585 our operands and seeing if a constant shows up in one of them.
2587 Note that there is no risk of modifying the structure of the insn,
2588 since we only get called for its operands, thus we are either
2589 modifying the address inside a MEM, or something like an address
2590 operand of a load-address insn. */
2593 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2594 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2596 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2598 /* If one side is a PLUS and the other side is a pseudo that
2599 didn't get a hard register but has a reg_equiv_constant,
2600 we must replace the constant here since it may no longer
2601 be in the position of any operand. */
2602 if (GET_CODE (new0) == PLUS && REG_P (new1)
2603 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2604 && reg_renumber[REGNO (new1)] < 0
2605 && reg_equiv_constant != 0
2606 && reg_equiv_constant[REGNO (new1)] != 0)
2607 new1 = reg_equiv_constant[REGNO (new1)];
2608 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2609 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2610 && reg_renumber[REGNO (new0)] < 0
2611 && reg_equiv_constant[REGNO (new0)] != 0)
2612 new0 = reg_equiv_constant[REGNO (new0)];
2614 new_rtx = form_sum (new0, new1);
2616 /* As above, if we are not inside a MEM we do not want to
2617 turn a PLUS into something else. We might try to do so here
2618 for an addition of 0 if we aren't optimizing. */
2619 if (! mem_mode && GET_CODE (new_rtx) != PLUS)
2620 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx);
2628 /* If this is the product of an eliminable register and a
2629 constant, apply the distribute law and move the constant out
2630 so that we have (plus (mult ..) ..). This is needed in order
2631 to keep load-address insns valid. This case is pathological.
2632 We ignore the possibility of overflow here. */
2633 if (REG_P (XEXP (x, 0))
2634 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2635 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2636 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2638 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2641 /* Refs inside notes don't count for this purpose. */
2642 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2643 || GET_CODE (insn) == INSN_LIST)))
2644 ep->ref_outside_mem = 1;
2647 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2648 ep->previous_offset * INTVAL (XEXP (x, 1)));
2651 /* ... fall through ... */
2655 /* See comments before PLUS about handling MINUS. */
2657 case DIV: case UDIV:
2658 case MOD: case UMOD:
2659 case AND: case IOR: case XOR:
2660 case ROTATERT: case ROTATE:
2661 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2663 case GE: case GT: case GEU: case GTU:
2664 case LE: case LT: case LEU: case LTU:
2666 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2667 rtx new1 = XEXP (x, 1)
2668 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2670 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2671 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2676 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2679 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2680 if (new_rtx != XEXP (x, 0))
2682 /* If this is a REG_DEAD note, it is not valid anymore.
2683 Using the eliminated version could result in creating a
2684 REG_DEAD note for the stack or frame pointer. */
2685 if (REG_NOTE_KIND (x) == REG_DEAD)
2687 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2690 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1));
2694 /* ... fall through ... */
2697 /* Now do eliminations in the rest of the chain. If this was
2698 an EXPR_LIST, this might result in allocating more memory than is
2699 strictly needed, but it simplifies the code. */
2702 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2703 if (new_rtx != XEXP (x, 1))
2705 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx);
2713 /* We do not support elimination of a register that is modified.
2714 elimination_effects has already make sure that this does not
2720 /* We do not support elimination of a register that is modified.
2721 elimination_effects has already make sure that this does not
2722 happen. The only remaining case we need to consider here is
2723 that the increment value may be an eliminable register. */
2724 if (GET_CODE (XEXP (x, 1)) == PLUS
2725 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2727 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2730 if (new_rtx != XEXP (XEXP (x, 1), 1))
2731 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2732 gen_rtx_PLUS (GET_MODE (x),
2733 XEXP (x, 0), new_rtx));
2737 case STRICT_LOW_PART:
2739 case SIGN_EXTEND: case ZERO_EXTEND:
2740 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2741 case FLOAT: case FIX:
2742 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2751 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2752 if (new_rtx != XEXP (x, 0))
2753 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx);
2757 /* Similar to above processing, but preserve SUBREG_BYTE.
2758 Convert (subreg (mem)) to (mem) if not paradoxical.
2759 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2760 pseudo didn't get a hard reg, we must replace this with the
2761 eliminated version of the memory location because push_reload
2762 may do the replacement in certain circumstances. */
2763 if (REG_P (SUBREG_REG (x))
2764 && (GET_MODE_SIZE (GET_MODE (x))
2765 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2766 && reg_equiv_memory_loc != 0
2767 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2769 new_rtx = SUBREG_REG (x);
2772 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2774 if (new_rtx != SUBREG_REG (x))
2776 int x_size = GET_MODE_SIZE (GET_MODE (x));
2777 int new_size = GET_MODE_SIZE (GET_MODE (new_rtx));
2780 && ((x_size < new_size
2781 #ifdef WORD_REGISTER_OPERATIONS
2782 /* On these machines, combine can create rtl of the form
2783 (set (subreg:m1 (reg:m2 R) 0) ...)
2784 where m1 < m2, and expects something interesting to
2785 happen to the entire word. Moreover, it will use the
2786 (reg:m2 R) later, expecting all bits to be preserved.
2787 So if the number of words is the same, preserve the
2788 subreg so that push_reload can see it. */
2789 && ! ((x_size - 1) / UNITS_PER_WORD
2790 == (new_size -1 ) / UNITS_PER_WORD)
2793 || x_size == new_size)
2795 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x));
2797 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x));
2803 /* Our only special processing is to pass the mode of the MEM to our
2804 recursive call and copy the flags. While we are here, handle this
2805 case more efficiently. */
2807 replace_equiv_address_nv (x,
2808 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2812 /* Handle insn_list USE that a call to a pure function may generate. */
2813 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false);
2814 if (new_rtx != XEXP (x, 0))
2815 return gen_rtx_USE (GET_MODE (x), new_rtx);
2827 /* Process each of our operands recursively. If any have changed, make a
2829 fmt = GET_RTX_FORMAT (code);
2830 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2834 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2835 if (new_rtx != XEXP (x, i) && ! copied)
2837 x = shallow_copy_rtx (x);
2840 XEXP (x, i) = new_rtx;
2842 else if (*fmt == 'E')
2845 for (j = 0; j < XVECLEN (x, i); j++)
2847 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2848 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec)
2850 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2854 x = shallow_copy_rtx (x);
2857 XVEC (x, i) = new_v;
2860 XVECEXP (x, i, j) = new_rtx;
2869 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2871 return eliminate_regs_1 (x, mem_mode, insn, false);
2874 /* Scan rtx X for modifications of elimination target registers. Update
2875 the table of eliminables to reflect the changed state. MEM_MODE is
2876 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2879 elimination_effects (rtx x, enum machine_mode mem_mode)
2881 enum rtx_code code = GET_CODE (x);
2882 struct elim_table *ep;
2907 /* First handle the case where we encounter a bare register that
2908 is eliminable. Replace it with a PLUS. */
2909 if (regno < FIRST_PSEUDO_REGISTER)
2911 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2913 if (ep->from_rtx == x && ep->can_eliminate)
2916 ep->ref_outside_mem = 1;
2921 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2922 && reg_equiv_constant[regno]
2923 && ! function_invariant_p (reg_equiv_constant[regno]))
2924 elimination_effects (reg_equiv_constant[regno], mem_mode);
2933 /* If we modify the source of an elimination rule, disable it. */
2934 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2935 if (ep->from_rtx == XEXP (x, 0))
2936 ep->can_eliminate = 0;
2938 /* If we modify the target of an elimination rule by adding a constant,
2939 update its offset. If we modify the target in any other way, we'll
2940 have to disable the rule as well. */
2941 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2942 if (ep->to_rtx == XEXP (x, 0))
2944 int size = GET_MODE_SIZE (mem_mode);
2946 /* If more bytes than MEM_MODE are pushed, account for them. */
2947 #ifdef PUSH_ROUNDING
2948 if (ep->to_rtx == stack_pointer_rtx)
2949 size = PUSH_ROUNDING (size);
2951 if (code == PRE_DEC || code == POST_DEC)
2953 else if (code == PRE_INC || code == POST_INC)
2955 else if (code == PRE_MODIFY || code == POST_MODIFY)
2957 if (GET_CODE (XEXP (x, 1)) == PLUS
2958 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2959 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2960 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2962 ep->can_eliminate = 0;
2966 /* These two aren't unary operators. */
2967 if (code == POST_MODIFY || code == PRE_MODIFY)
2970 /* Fall through to generic unary operation case. */
2971 case STRICT_LOW_PART:
2973 case SIGN_EXTEND: case ZERO_EXTEND:
2974 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2975 case FLOAT: case FIX:
2976 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2985 elimination_effects (XEXP (x, 0), mem_mode);
2989 if (REG_P (SUBREG_REG (x))
2990 && (GET_MODE_SIZE (GET_MODE (x))
2991 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2992 && reg_equiv_memory_loc != 0
2993 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2996 elimination_effects (SUBREG_REG (x), mem_mode);
3000 /* If using a register that is the source of an eliminate we still
3001 think can be performed, note it cannot be performed since we don't
3002 know how this register is used. */
3003 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3004 if (ep->from_rtx == XEXP (x, 0))
3005 ep->can_eliminate = 0;
3007 elimination_effects (XEXP (x, 0), mem_mode);
3011 /* If clobbering a register that is the replacement register for an
3012 elimination we still think can be performed, note that it cannot
3013 be performed. Otherwise, we need not be concerned about it. */
3014 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3015 if (ep->to_rtx == XEXP (x, 0))
3016 ep->can_eliminate = 0;
3018 elimination_effects (XEXP (x, 0), mem_mode);
3022 /* Check for setting a register that we know about. */
3023 if (REG_P (SET_DEST (x)))
3025 /* See if this is setting the replacement register for an
3028 If DEST is the hard frame pointer, we do nothing because we
3029 assume that all assignments to the frame pointer are for
3030 non-local gotos and are being done at a time when they are valid
3031 and do not disturb anything else. Some machines want to
3032 eliminate a fake argument pointer (or even a fake frame pointer)
3033 with either the real frame or the stack pointer. Assignments to
3034 the hard frame pointer must not prevent this elimination. */
3036 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3038 if (ep->to_rtx == SET_DEST (x)
3039 && SET_DEST (x) != hard_frame_pointer_rtx)
3041 /* If it is being incremented, adjust the offset. Otherwise,
3042 this elimination can't be done. */
3043 rtx src = SET_SRC (x);
3045 if (GET_CODE (src) == PLUS
3046 && XEXP (src, 0) == SET_DEST (x)
3047 && GET_CODE (XEXP (src, 1)) == CONST_INT)
3048 ep->offset -= INTVAL (XEXP (src, 1));
3050 ep->can_eliminate = 0;
3054 elimination_effects (SET_DEST (x), VOIDmode);
3055 elimination_effects (SET_SRC (x), VOIDmode);
3059 /* Our only special processing is to pass the mode of the MEM to our
3061 elimination_effects (XEXP (x, 0), GET_MODE (x));
3068 fmt = GET_RTX_FORMAT (code);
3069 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3072 elimination_effects (XEXP (x, i), mem_mode);
3073 else if (*fmt == 'E')
3074 for (j = 0; j < XVECLEN (x, i); j++)
3075 elimination_effects (XVECEXP (x, i, j), mem_mode);
3079 /* Descend through rtx X and verify that no references to eliminable registers
3080 remain. If any do remain, mark the involved register as not
3084 check_eliminable_occurrences (rtx x)
3093 code = GET_CODE (x);
3095 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3097 struct elim_table *ep;
3099 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3100 if (ep->from_rtx == x)
3101 ep->can_eliminate = 0;
3105 fmt = GET_RTX_FORMAT (code);
3106 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3109 check_eliminable_occurrences (XEXP (x, i));
3110 else if (*fmt == 'E')
3113 for (j = 0; j < XVECLEN (x, i); j++)
3114 check_eliminable_occurrences (XVECEXP (x, i, j));
3119 /* Scan INSN and eliminate all eliminable registers in it.
3121 If REPLACE is nonzero, do the replacement destructively. Also
3122 delete the insn as dead it if it is setting an eliminable register.
3124 If REPLACE is zero, do all our allocations in reload_obstack.
3126 If no eliminations were done and this insn doesn't require any elimination
3127 processing (these are not identical conditions: it might be updating sp,
3128 but not referencing fp; this needs to be seen during reload_as_needed so
3129 that the offset between fp and sp can be taken into consideration), zero
3130 is returned. Otherwise, 1 is returned. */
3133 eliminate_regs_in_insn (rtx insn, int replace)
3135 int icode = recog_memoized (insn);
3136 rtx old_body = PATTERN (insn);
3137 int insn_is_asm = asm_noperands (old_body) >= 0;
3138 rtx old_set = single_set (insn);
3142 rtx substed_operand[MAX_RECOG_OPERANDS];
3143 rtx orig_operand[MAX_RECOG_OPERANDS];
3144 struct elim_table *ep;
3145 rtx plus_src, plus_cst_src;
3147 if (! insn_is_asm && icode < 0)
3149 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3150 || GET_CODE (PATTERN (insn)) == CLOBBER
3151 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3152 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3153 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3157 if (old_set != 0 && REG_P (SET_DEST (old_set))
3158 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3160 /* Check for setting an eliminable register. */
3161 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3162 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3164 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3165 /* If this is setting the frame pointer register to the
3166 hardware frame pointer register and this is an elimination
3167 that will be done (tested above), this insn is really
3168 adjusting the frame pointer downward to compensate for
3169 the adjustment done before a nonlocal goto. */
3170 if (ep->from == FRAME_POINTER_REGNUM
3171 && ep->to == HARD_FRAME_POINTER_REGNUM)
3173 rtx base = SET_SRC (old_set);
3174 rtx base_insn = insn;
3175 HOST_WIDE_INT offset = 0;
3177 while (base != ep->to_rtx)
3179 rtx prev_insn, prev_set;
3181 if (GET_CODE (base) == PLUS
3182 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3184 offset += INTVAL (XEXP (base, 1));
3185 base = XEXP (base, 0);
3187 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3188 && (prev_set = single_set (prev_insn)) != 0
3189 && rtx_equal_p (SET_DEST (prev_set), base))
3191 base = SET_SRC (prev_set);
3192 base_insn = prev_insn;
3198 if (base == ep->to_rtx)
3201 = plus_constant (ep->to_rtx, offset - ep->offset);
3203 new_body = old_body;
3206 new_body = copy_insn (old_body);
3207 if (REG_NOTES (insn))
3208 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3210 PATTERN (insn) = new_body;
3211 old_set = single_set (insn);
3213 /* First see if this insn remains valid when we
3214 make the change. If not, keep the INSN_CODE
3215 the same and let reload fit it up. */
3216 validate_change (insn, &SET_SRC (old_set), src, 1);
3217 validate_change (insn, &SET_DEST (old_set),
3219 if (! apply_change_group ())
3221 SET_SRC (old_set) = src;
3222 SET_DEST (old_set) = ep->to_rtx;
3231 /* In this case this insn isn't serving a useful purpose. We
3232 will delete it in reload_as_needed once we know that this
3233 elimination is, in fact, being done.
3235 If REPLACE isn't set, we can't delete this insn, but needn't
3236 process it since it won't be used unless something changes. */
3239 delete_dead_insn (insn);
3247 /* We allow one special case which happens to work on all machines we
3248 currently support: a single set with the source or a REG_EQUAL
3249 note being a PLUS of an eliminable register and a constant. */
3250 plus_src = plus_cst_src = 0;
3251 if (old_set && REG_P (SET_DEST (old_set)))
3253 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3254 plus_src = SET_SRC (old_set);
3255 /* First see if the source is of the form (plus (...) CST). */
3257 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3258 plus_cst_src = plus_src;
3259 else if (REG_P (SET_SRC (old_set))
3262 /* Otherwise, see if we have a REG_EQUAL note of the form
3263 (plus (...) CST). */
3265 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3267 if ((REG_NOTE_KIND (links) == REG_EQUAL
3268 || REG_NOTE_KIND (links) == REG_EQUIV)
3269 && GET_CODE (XEXP (links, 0)) == PLUS
3270 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3272 plus_cst_src = XEXP (links, 0);
3278 /* Check that the first operand of the PLUS is a hard reg or
3279 the lowpart subreg of one. */
3282 rtx reg = XEXP (plus_cst_src, 0);
3283 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3284 reg = SUBREG_REG (reg);
3286 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3292 rtx reg = XEXP (plus_cst_src, 0);
3293 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3295 if (GET_CODE (reg) == SUBREG)
3296 reg = SUBREG_REG (reg);
3298 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3299 if (ep->from_rtx == reg && ep->can_eliminate)
3301 rtx to_rtx = ep->to_rtx;
3302 offset += ep->offset;
3303 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src));
3305 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3306 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3308 /* If we have a nonzero offset, and the source is already
3309 a simple REG, the following transformation would
3310 increase the cost of the insn by replacing a simple REG
3311 with (plus (reg sp) CST). So try only when we already
3312 had a PLUS before. */
3313 if (offset == 0 || plus_src)
3315 rtx new_src = plus_constant (to_rtx, offset);
3317 new_body = old_body;
3320 new_body = copy_insn (old_body);
3321 if (REG_NOTES (insn))
3322 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3324 PATTERN (insn) = new_body;
3325 old_set = single_set (insn);
3327 /* First see if this insn remains valid when we make the
3328 change. If not, try to replace the whole pattern with
3329 a simple set (this may help if the original insn was a
3330 PARALLEL that was only recognized as single_set due to
3331 REG_UNUSED notes). If this isn't valid either, keep
3332 the INSN_CODE the same and let reload fix it up. */
3333 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3335 rtx new_pat = gen_rtx_SET (VOIDmode,
3336 SET_DEST (old_set), new_src);
3338 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3339 SET_SRC (old_set) = new_src;
3346 /* This can't have an effect on elimination offsets, so skip right
3352 /* Determine the effects of this insn on elimination offsets. */
3353 elimination_effects (old_body, VOIDmode);
3355 /* Eliminate all eliminable registers occurring in operands that
3356 can be handled by reload. */
3357 extract_insn (insn);
3358 for (i = 0; i < recog_data.n_operands; i++)
3360 orig_operand[i] = recog_data.operand[i];
3361 substed_operand[i] = recog_data.operand[i];
3363 /* For an asm statement, every operand is eliminable. */
3364 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3366 bool is_set_src, in_plus;
3368 /* Check for setting a register that we know about. */
3369 if (recog_data.operand_type[i] != OP_IN
3370 && REG_P (orig_operand[i]))
3372 /* If we are assigning to a register that can be eliminated, it
3373 must be as part of a PARALLEL, since the code above handles
3374 single SETs. We must indicate that we can no longer
3375 eliminate this reg. */
3376 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3378 if (ep->from_rtx == orig_operand[i])
3379 ep->can_eliminate = 0;
3382 /* Companion to the above plus substitution, we can allow
3383 invariants as the source of a plain move. */
3385 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3389 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3390 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3394 = eliminate_regs_1 (recog_data.operand[i], VOIDmode,
3395 replace ? insn : NULL_RTX,
3396 is_set_src || in_plus);
3397 if (substed_operand[i] != orig_operand[i])
3399 /* Terminate the search in check_eliminable_occurrences at
3401 *recog_data.operand_loc[i] = 0;
3403 /* If an output operand changed from a REG to a MEM and INSN is an
3404 insn, write a CLOBBER insn. */
3405 if (recog_data.operand_type[i] != OP_IN
3406 && REG_P (orig_operand[i])
3407 && MEM_P (substed_operand[i])
3409 emit_insn_after (gen_clobber (orig_operand[i]), insn);
3413 for (i = 0; i < recog_data.n_dups; i++)
3414 *recog_data.dup_loc[i]
3415 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3417 /* If any eliminable remain, they aren't eliminable anymore. */
3418 check_eliminable_occurrences (old_body);
3420 /* Substitute the operands; the new values are in the substed_operand
3422 for (i = 0; i < recog_data.n_operands; i++)
3423 *recog_data.operand_loc[i] = substed_operand[i];
3424 for (i = 0; i < recog_data.n_dups; i++)
3425 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3427 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3428 re-recognize the insn. We do this in case we had a simple addition
3429 but now can do this as a load-address. This saves an insn in this
3431 If re-recognition fails, the old insn code number will still be used,
3432 and some register operands may have changed into PLUS expressions.
3433 These will be handled by find_reloads by loading them into a register
3438 /* If we aren't replacing things permanently and we changed something,
3439 make another copy to ensure that all the RTL is new. Otherwise
3440 things can go wrong if find_reload swaps commutative operands
3441 and one is inside RTL that has been copied while the other is not. */
3442 new_body = old_body;
3445 new_body = copy_insn (old_body);
3446 if (REG_NOTES (insn))
3447 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3449 PATTERN (insn) = new_body;
3451 /* If we had a move insn but now we don't, rerecognize it. This will
3452 cause spurious re-recognition if the old move had a PARALLEL since
3453 the new one still will, but we can't call single_set without
3454 having put NEW_BODY into the insn and the re-recognition won't
3455 hurt in this rare case. */
3456 /* ??? Why this huge if statement - why don't we just rerecognize the
3460 && ((REG_P (SET_SRC (old_set))
3461 && (GET_CODE (new_body) != SET
3462 || !REG_P (SET_SRC (new_body))))
3463 /* If this was a load from or store to memory, compare
3464 the MEM in recog_data.operand to the one in the insn.
3465 If they are not equal, then rerecognize the insn. */
3467 && ((MEM_P (SET_SRC (old_set))
3468 && SET_SRC (old_set) != recog_data.operand[1])
3469 || (MEM_P (SET_DEST (old_set))
3470 && SET_DEST (old_set) != recog_data.operand[0])))
3471 /* If this was an add insn before, rerecognize. */
3472 || GET_CODE (SET_SRC (old_set)) == PLUS))
3474 int new_icode = recog (PATTERN (insn), insn, 0);
3476 INSN_CODE (insn) = new_icode;
3480 /* Restore the old body. If there were any changes to it, we made a copy
3481 of it while the changes were still in place, so we'll correctly return
3482 a modified insn below. */
3485 /* Restore the old body. */
3486 for (i = 0; i < recog_data.n_operands; i++)
3487 *recog_data.operand_loc[i] = orig_operand[i];
3488 for (i = 0; i < recog_data.n_dups; i++)
3489 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3492 /* Update all elimination pairs to reflect the status after the current
3493 insn. The changes we make were determined by the earlier call to
3494 elimination_effects.
3496 We also detect cases where register elimination cannot be done,
3497 namely, if a register would be both changed and referenced outside a MEM
3498 in the resulting insn since such an insn is often undefined and, even if
3499 not, we cannot know what meaning will be given to it. Note that it is
3500 valid to have a register used in an address in an insn that changes it
3501 (presumably with a pre- or post-increment or decrement).
3503 If anything changes, return nonzero. */
3505 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3507 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3508 ep->can_eliminate = 0;
3510 ep->ref_outside_mem = 0;
3512 if (ep->previous_offset != ep->offset)
3517 /* If we changed something, perform elimination in REG_NOTES. This is
3518 needed even when REPLACE is zero because a REG_DEAD note might refer
3519 to a register that we eliminate and could cause a different number
3520 of spill registers to be needed in the final reload pass than in
3522 if (val && REG_NOTES (insn) != 0)
3524 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true);
3529 /* Loop through all elimination pairs.
3530 Recalculate the number not at initial offset.
3532 Compute the maximum offset (minimum offset if the stack does not
3533 grow downward) for each elimination pair. */
3536 update_eliminable_offsets (void)
3538 struct elim_table *ep;
3540 num_not_at_initial_offset = 0;
3541 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3543 ep->previous_offset = ep->offset;
3544 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3545 num_not_at_initial_offset++;
3549 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3550 replacement we currently believe is valid, mark it as not eliminable if X
3551 modifies DEST in any way other than by adding a constant integer to it.
3553 If DEST is the frame pointer, we do nothing because we assume that
3554 all assignments to the hard frame pointer are nonlocal gotos and are being
3555 done at a time when they are valid and do not disturb anything else.
3556 Some machines want to eliminate a fake argument pointer with either the
3557 frame or stack pointer. Assignments to the hard frame pointer must not
3558 prevent this elimination.
3560 Called via note_stores from reload before starting its passes to scan
3561 the insns of the function. */
3564 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3568 /* A SUBREG of a hard register here is just changing its mode. We should
3569 not see a SUBREG of an eliminable hard register, but check just in
3571 if (GET_CODE (dest) == SUBREG)
3572 dest = SUBREG_REG (dest);
3574 if (dest == hard_frame_pointer_rtx)
3577 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3578 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3579 && (GET_CODE (x) != SET
3580 || GET_CODE (SET_SRC (x)) != PLUS
3581 || XEXP (SET_SRC (x), 0) != dest
3582 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3584 reg_eliminate[i].can_eliminate_previous
3585 = reg_eliminate[i].can_eliminate = 0;
3590 /* Verify that the initial elimination offsets did not change since the
3591 last call to set_initial_elim_offsets. This is used to catch cases
3592 where something illegal happened during reload_as_needed that could
3593 cause incorrect code to be generated if we did not check for it. */
3596 verify_initial_elim_offsets (void)
3600 if (!num_eliminable)
3603 #ifdef ELIMINABLE_REGS
3605 struct elim_table *ep;
3607 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3609 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3610 if (t != ep->initial_offset)
3615 INITIAL_FRAME_POINTER_OFFSET (t);
3616 if (t != reg_eliminate[0].initial_offset)
3623 /* Reset all offsets on eliminable registers to their initial values. */
3626 set_initial_elim_offsets (void)
3628 struct elim_table *ep = reg_eliminate;
3630 #ifdef ELIMINABLE_REGS
3631 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3633 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3634 ep->previous_offset = ep->offset = ep->initial_offset;
3637 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3638 ep->previous_offset = ep->offset = ep->initial_offset;
3641 num_not_at_initial_offset = 0;
3644 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3647 set_initial_eh_label_offset (rtx label)
3649 set_label_offsets (label, NULL_RTX, 1);
3652 /* Initialize the known label offsets.
3653 Set a known offset for each forced label to be at the initial offset
3654 of each elimination. We do this because we assume that all
3655 computed jumps occur from a location where each elimination is
3656 at its initial offset.
3657 For all other labels, show that we don't know the offsets. */
3660 set_initial_label_offsets (void)
3663 memset (offsets_known_at, 0, num_labels);
3665 for (x = forced_labels; x; x = XEXP (x, 1))
3667 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3669 for_each_eh_label (set_initial_eh_label_offset);
3672 /* Set all elimination offsets to the known values for the code label given
3676 set_offsets_for_label (rtx insn)
3679 int label_nr = CODE_LABEL_NUMBER (insn);
3680 struct elim_table *ep;
3682 num_not_at_initial_offset = 0;
3683 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3685 ep->offset = ep->previous_offset
3686 = offsets_at[label_nr - first_label_num][i];
3687 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3688 num_not_at_initial_offset++;
3692 /* See if anything that happened changes which eliminations are valid.
3693 For example, on the SPARC, whether or not the frame pointer can
3694 be eliminated can depend on what registers have been used. We need
3695 not check some conditions again (such as flag_omit_frame_pointer)
3696 since they can't have changed. */
3699 update_eliminables (HARD_REG_SET *pset)
3701 int previous_frame_pointer_needed = frame_pointer_needed;
3702 struct elim_table *ep;
3704 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3705 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3706 #ifdef ELIMINABLE_REGS
3707 || ! CAN_ELIMINATE (ep->from, ep->to)
3710 ep->can_eliminate = 0;
3712 /* Look for the case where we have discovered that we can't replace
3713 register A with register B and that means that we will now be
3714 trying to replace register A with register C. This means we can
3715 no longer replace register C with register B and we need to disable
3716 such an elimination, if it exists. This occurs often with A == ap,
3717 B == sp, and C == fp. */
3719 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3721 struct elim_table *op;
3724 if (! ep->can_eliminate && ep->can_eliminate_previous)
3726 /* Find the current elimination for ep->from, if there is a
3728 for (op = reg_eliminate;
3729 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3730 if (op->from == ep->from && op->can_eliminate)
3736 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3738 for (op = reg_eliminate;
3739 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3740 if (op->from == new_to && op->to == ep->to)
3741 op->can_eliminate = 0;
3745 /* See if any registers that we thought we could eliminate the previous
3746 time are no longer eliminable. If so, something has changed and we
3747 must spill the register. Also, recompute the number of eliminable
3748 registers and see if the frame pointer is needed; it is if there is
3749 no elimination of the frame pointer that we can perform. */
3751 frame_pointer_needed = 1;
3752 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3754 if (ep->can_eliminate
3755 && ep->from == FRAME_POINTER_REGNUM
3756 && ep->to != HARD_FRAME_POINTER_REGNUM
3757 && (! SUPPORTS_STACK_ALIGNMENT
3758 || ! crtl->stack_realign_needed))
3759 frame_pointer_needed = 0;
3761 if (! ep->can_eliminate && ep->can_eliminate_previous)
3763 ep->can_eliminate_previous = 0;
3764 SET_HARD_REG_BIT (*pset, ep->from);
3769 /* If we didn't need a frame pointer last time, but we do now, spill
3770 the hard frame pointer. */
3771 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3772 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3775 /* Return true if X is used as the target register of an elimination. */
3778 elimination_target_reg_p (rtx x)
3780 struct elim_table *ep;
3782 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3783 if (ep->to_rtx == x && ep->can_eliminate)
3789 /* Initialize the table of registers to eliminate.
3790 Pre-condition: global flag frame_pointer_needed has been set before
3791 calling this function. */
3794 init_elim_table (void)
3796 struct elim_table *ep;
3797 #ifdef ELIMINABLE_REGS
3798 const struct elim_table_1 *ep1;
3802 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS);
3806 #ifdef ELIMINABLE_REGS
3807 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3808 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3810 ep->from = ep1->from;
3812 ep->can_eliminate = ep->can_eliminate_previous
3813 = (CAN_ELIMINATE (ep->from, ep->to)
3814 && ! (ep->to == STACK_POINTER_REGNUM
3815 && frame_pointer_needed
3816 && (! SUPPORTS_STACK_ALIGNMENT
3817 || ! stack_realign_fp)));
3820 reg_eliminate[0].from = reg_eliminate_1[0].from;
3821 reg_eliminate[0].to = reg_eliminate_1[0].to;
3822 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3823 = ! frame_pointer_needed;
3826 /* Count the number of eliminable registers and build the FROM and TO
3827 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3828 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3829 We depend on this. */
3830 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3832 num_eliminable += ep->can_eliminate;
3833 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3834 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3838 /* Kick all pseudos out of hard register REGNO.
3840 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3841 because we found we can't eliminate some register. In the case, no pseudos
3842 are allowed to be in the register, even if they are only in a block that
3843 doesn't require spill registers, unlike the case when we are spilling this
3844 hard reg to produce another spill register.
3846 Return nonzero if any pseudos needed to be kicked out. */
3849 spill_hard_reg (unsigned int regno, int cant_eliminate)
3855 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3856 df_set_regs_ever_live (regno, true);
3859 /* Spill every pseudo reg that was allocated to this reg
3860 or to something that overlaps this reg. */
3862 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3863 if (reg_renumber[i] >= 0
3864 && (unsigned int) reg_renumber[i] <= regno
3865 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3866 SET_REGNO_REG_SET (&spilled_pseudos, i);
3869 /* After find_reload_regs has been run for all insn that need reloads,
3870 and/or spill_hard_regs was called, this function is used to actually
3871 spill pseudo registers and try to reallocate them. It also sets up the
3872 spill_regs array for use by choose_reload_regs. */
3875 finish_spills (int global)
3877 struct insn_chain *chain;
3878 int something_changed = 0;
3880 reg_set_iterator rsi;
3882 /* Build the spill_regs array for the function. */
3883 /* If there are some registers still to eliminate and one of the spill regs
3884 wasn't ever used before, additional stack space may have to be
3885 allocated to store this register. Thus, we may have changed the offset
3886 between the stack and frame pointers, so mark that something has changed.
3888 One might think that we need only set VAL to 1 if this is a call-used
3889 register. However, the set of registers that must be saved by the
3890 prologue is not identical to the call-used set. For example, the
3891 register used by the call insn for the return PC is a call-used register,
3892 but must be saved by the prologue. */
3895 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3896 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3898 spill_reg_order[i] = n_spills;
3899 spill_regs[n_spills++] = i;
3900 if (num_eliminable && ! df_regs_ever_live_p (i))
3901 something_changed = 1;
3902 df_set_regs_ever_live (i, true);
3905 spill_reg_order[i] = -1;
3907 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3908 if (! ira_conflicts_p || reg_renumber[i] >= 0)
3910 /* Record the current hard register the pseudo is allocated to
3911 in pseudo_previous_regs so we avoid reallocating it to the
3912 same hard reg in a later pass. */
3913 gcc_assert (reg_renumber[i] >= 0);
3915 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3916 /* Mark it as no longer having a hard register home. */
3917 reg_renumber[i] = -1;
3918 if (ira_conflicts_p)
3919 /* Inform IRA about the change. */
3920 ira_mark_allocation_change (i);
3921 /* We will need to scan everything again. */
3922 something_changed = 1;
3925 /* Retry global register allocation if possible. */
3926 if (global && ira_conflicts_p)
3930 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3931 /* For every insn that needs reloads, set the registers used as spill
3932 regs in pseudo_forbidden_regs for every pseudo live across the
3934 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3936 EXECUTE_IF_SET_IN_REG_SET
3937 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3939 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3940 chain->used_spill_regs);
3942 EXECUTE_IF_SET_IN_REG_SET
3943 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3945 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3946 chain->used_spill_regs);
3950 /* Retry allocating the pseudos spilled in IRA and the
3951 reload. For each reg, merge the various reg sets that
3952 indicate which hard regs can't be used, and call
3953 ira_reassign_pseudos. */
3954 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++)
3955 if (reg_old_renumber[i] != reg_renumber[i])
3957 if (reg_renumber[i] < 0)
3958 temp_pseudo_reg_arr[n++] = i;
3960 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3962 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n,
3963 bad_spill_regs_global,
3964 pseudo_forbidden_regs, pseudo_previous_regs,
3966 something_changed = 1;
3968 /* Fix up the register information in the insn chain.
3969 This involves deleting those of the spilled pseudos which did not get
3970 a new hard register home from the live_{before,after} sets. */
3971 for (chain = reload_insn_chain; chain; chain = chain->next)
3973 HARD_REG_SET used_by_pseudos;
3974 HARD_REG_SET used_by_pseudos2;
3976 if (! ira_conflicts_p)
3978 /* Don't do it for IRA because IRA and the reload still can
3979 assign hard registers to the spilled pseudos on next
3980 reload iterations. */
3981 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3982 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3984 /* Mark any unallocated hard regs as available for spills. That
3985 makes inheritance work somewhat better. */
3986 if (chain->need_reload)
3988 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3989 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3990 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3992 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3993 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3994 /* Value of chain->used_spill_regs from previous iteration
3995 may be not included in the value calculated here because
3996 of possible removing caller-saves insns (see function
3997 delete_caller_save_insns. */
3998 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3999 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
4003 CLEAR_REG_SET (&changed_allocation_pseudos);
4004 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
4005 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
4007 int regno = reg_renumber[i];
4008 if (reg_old_renumber[i] == regno)
4011 SET_REGNO_REG_SET (&changed_allocation_pseudos, i);
4013 alter_reg (i, reg_old_renumber[i], false);
4014 reg_old_renumber[i] = regno;
4018 fprintf (dump_file, " Register %d now on stack.\n\n", i);
4020 fprintf (dump_file, " Register %d now in %d.\n\n",
4021 i, reg_renumber[i]);
4025 return something_changed;
4028 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
4031 scan_paradoxical_subregs (rtx x)
4035 enum rtx_code code = GET_CODE (x);
4046 case CONST_VECTOR: /* shouldn't happen, but just in case. */
4054 if (REG_P (SUBREG_REG (x))
4055 && (GET_MODE_SIZE (GET_MODE (x))
4056 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
4058 reg_max_ref_width[REGNO (SUBREG_REG (x))]
4059 = GET_MODE_SIZE (GET_MODE (x));
4060 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
4068 fmt = GET_RTX_FORMAT (code);
4069 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
4072 scan_paradoxical_subregs (XEXP (x, i));
4073 else if (fmt[i] == 'E')
4076 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
4077 scan_paradoxical_subregs (XVECEXP (x, i, j));
4082 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
4083 examine all of the reload insns between PREV and NEXT exclusive, and
4084 annotate all that may trap. */
4087 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4089 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4095 if (! may_trap_p (PATTERN (insn)))
4096 remove_note (insn, note);
4098 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4099 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4100 add_reg_note (i, REG_EH_REGION, XEXP (note, 0));
4103 /* Reload pseudo-registers into hard regs around each insn as needed.
4104 Additional register load insns are output before the insn that needs it
4105 and perhaps store insns after insns that modify the reloaded pseudo reg.
4107 reg_last_reload_reg and reg_reloaded_contents keep track of
4108 which registers are already available in reload registers.
4109 We update these for the reloads that we perform,
4110 as the insns are scanned. */
4113 reload_as_needed (int live_known)
4115 struct insn_chain *chain;
4116 #if defined (AUTO_INC_DEC)
4121 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4122 memset (spill_reg_store, 0, sizeof spill_reg_store);
4123 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4124 INIT_REG_SET (®_has_output_reload);
4125 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4126 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4128 set_initial_elim_offsets ();
4130 for (chain = reload_insn_chain; chain; chain = chain->next)
4133 rtx insn = chain->insn;
4134 rtx old_next = NEXT_INSN (insn);
4136 rtx old_prev = PREV_INSN (insn);
4139 /* If we pass a label, copy the offsets from the label information
4140 into the current offsets of each elimination. */
4142 set_offsets_for_label (insn);
4144 else if (INSN_P (insn))
4146 regset_head regs_to_forget;
4147 INIT_REG_SET (®s_to_forget);
4148 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4150 /* If this is a USE and CLOBBER of a MEM, ensure that any
4151 references to eliminable registers have been removed. */
4153 if ((GET_CODE (PATTERN (insn)) == USE
4154 || GET_CODE (PATTERN (insn)) == CLOBBER)
4155 && MEM_P (XEXP (PATTERN (insn), 0)))
4156 XEXP (XEXP (PATTERN (insn), 0), 0)
4157 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4158 GET_MODE (XEXP (PATTERN (insn), 0)),
4161 /* If we need to do register elimination processing, do so.
4162 This might delete the insn, in which case we are done. */
4163 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4165 eliminate_regs_in_insn (insn, 1);
4168 update_eliminable_offsets ();
4169 CLEAR_REG_SET (®s_to_forget);
4174 /* If need_elim is nonzero but need_reload is zero, one might think
4175 that we could simply set n_reloads to 0. However, find_reloads
4176 could have done some manipulation of the insn (such as swapping
4177 commutative operands), and these manipulations are lost during
4178 the first pass for every insn that needs register elimination.
4179 So the actions of find_reloads must be redone here. */
4181 if (! chain->need_elim && ! chain->need_reload
4182 && ! chain->need_operand_change)
4184 /* First find the pseudo regs that must be reloaded for this insn.
4185 This info is returned in the tables reload_... (see reload.h).
4186 Also modify the body of INSN by substituting RELOAD
4187 rtx's for those pseudo regs. */
4190 CLEAR_REG_SET (®_has_output_reload);
4191 CLEAR_HARD_REG_SET (reg_is_output_reload);
4193 find_reloads (insn, 1, spill_indirect_levels, live_known,
4199 rtx next = NEXT_INSN (insn);
4202 prev = PREV_INSN (insn);
4204 /* Now compute which reload regs to reload them into. Perhaps
4205 reusing reload regs from previous insns, or else output
4206 load insns to reload them. Maybe output store insns too.
4207 Record the choices of reload reg in reload_reg_rtx. */
4208 choose_reload_regs (chain);
4210 /* Merge any reloads that we didn't combine for fear of
4211 increasing the number of spill registers needed but now
4212 discover can be safely merged. */
4213 if (SMALL_REGISTER_CLASSES)
4214 merge_assigned_reloads (insn);
4216 /* Generate the insns to reload operands into or out of
4217 their reload regs. */
4218 emit_reload_insns (chain);
4220 /* Substitute the chosen reload regs from reload_reg_rtx
4221 into the insn's body (or perhaps into the bodies of other
4222 load and store insn that we just made for reloading
4223 and that we moved the structure into). */
4224 subst_reloads (insn);
4226 /* Adjust the exception region notes for loads and stores. */
4227 if (flag_non_call_exceptions && !CALL_P (insn))
4228 fixup_eh_region_note (insn, prev, next);
4230 /* If this was an ASM, make sure that all the reload insns
4231 we have generated are valid. If not, give an error
4233 if (asm_noperands (PATTERN (insn)) >= 0)
4234 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4235 if (p != insn && INSN_P (p)
4236 && GET_CODE (PATTERN (p)) != USE
4237 && (recog_memoized (p) < 0
4238 || (extract_insn (p), ! constrain_operands (1))))
4240 error_for_asm (insn,
4241 "%<asm%> operand requires "
4242 "impossible reload");
4247 if (num_eliminable && chain->need_elim)
4248 update_eliminable_offsets ();
4250 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4251 is no longer validly lying around to save a future reload.
4252 Note that this does not detect pseudos that were reloaded
4253 for this insn in order to be stored in
4254 (obeying register constraints). That is correct; such reload
4255 registers ARE still valid. */
4256 forget_marked_reloads (®s_to_forget);
4257 CLEAR_REG_SET (®s_to_forget);
4259 /* There may have been CLOBBER insns placed after INSN. So scan
4260 between INSN and NEXT and use them to forget old reloads. */
4261 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4262 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4263 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4266 /* Likewise for regs altered by auto-increment in this insn.
4267 REG_INC notes have been changed by reloading:
4268 find_reloads_address_1 records substitutions for them,
4269 which have been performed by subst_reloads above. */
4270 for (i = n_reloads - 1; i >= 0; i--)
4272 rtx in_reg = rld[i].in_reg;
4275 enum rtx_code code = GET_CODE (in_reg);
4276 /* PRE_INC / PRE_DEC will have the reload register ending up
4277 with the same value as the stack slot, but that doesn't
4278 hold true for POST_INC / POST_DEC. Either we have to
4279 convert the memory access to a true POST_INC / POST_DEC,
4280 or we can't use the reload register for inheritance. */
4281 if ((code == POST_INC || code == POST_DEC)
4282 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4283 REGNO (rld[i].reg_rtx))
4284 /* Make sure it is the inc/dec pseudo, and not
4285 some other (e.g. output operand) pseudo. */
4286 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4287 == REGNO (XEXP (in_reg, 0))))
4290 rtx reload_reg = rld[i].reg_rtx;
4291 enum machine_mode mode = GET_MODE (reload_reg);
4295 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4297 /* We really want to ignore REG_INC notes here, so
4298 use PATTERN (p) as argument to reg_set_p . */
4299 if (reg_set_p (reload_reg, PATTERN (p)))
4301 n = count_occurrences (PATTERN (p), reload_reg, 0);
4306 n = validate_replace_rtx (reload_reg,
4307 gen_rtx_fmt_e (code,
4312 /* We must also verify that the constraints
4313 are met after the replacement. */
4316 n = constrain_operands (1);
4320 /* If the constraints were not met, then
4321 undo the replacement. */
4324 validate_replace_rtx (gen_rtx_fmt_e (code,
4336 add_reg_note (p, REG_INC, reload_reg);
4337 /* Mark this as having an output reload so that the
4338 REG_INC processing code below won't invalidate
4339 the reload for inheritance. */
4340 SET_HARD_REG_BIT (reg_is_output_reload,
4341 REGNO (reload_reg));
4342 SET_REGNO_REG_SET (®_has_output_reload,
4343 REGNO (XEXP (in_reg, 0)));
4346 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4349 else if ((code == PRE_INC || code == PRE_DEC)
4350 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4351 REGNO (rld[i].reg_rtx))
4352 /* Make sure it is the inc/dec pseudo, and not
4353 some other (e.g. output operand) pseudo. */
4354 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4355 == REGNO (XEXP (in_reg, 0))))
4357 SET_HARD_REG_BIT (reg_is_output_reload,
4358 REGNO (rld[i].reg_rtx));
4359 SET_REGNO_REG_SET (®_has_output_reload,
4360 REGNO (XEXP (in_reg, 0)));
4362 else if (code == PRE_INC || code == PRE_DEC
4363 || code == POST_INC || code == POST_DEC)
4365 int in_regno = REGNO (XEXP (in_reg, 0));
4367 if (reg_last_reload_reg[in_regno] != NULL_RTX)
4370 bool forget_p = true;
4372 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]);
4373 if (TEST_HARD_REG_BIT (reg_reloaded_valid,
4376 for (x = old_prev ? NEXT_INSN (old_prev) : insn;
4379 if (x == reg_reloaded_insn[in_hard_regno])
4385 /* If for some reasons, we didn't set up
4386 reg_last_reload_reg in this insn,
4387 invalidate inheritance from previous
4388 insns for the incremented/decremented
4389 register. Such registers will be not in
4390 reg_has_output_reload. Invalidate it
4391 also if the corresponding element in
4392 reg_reloaded_insn is also
4395 forget_old_reloads_1 (XEXP (in_reg, 0),
4401 /* If a pseudo that got a hard register is auto-incremented,
4402 we must purge records of copying it into pseudos without
4404 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4405 if (REG_NOTE_KIND (x) == REG_INC)
4407 /* See if this pseudo reg was reloaded in this insn.
4408 If so, its last-reload info is still valid
4409 because it is based on this insn's reload. */
4410 for (i = 0; i < n_reloads; i++)
4411 if (rld[i].out == XEXP (x, 0))
4415 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4419 /* A reload reg's contents are unknown after a label. */
4421 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4423 /* Don't assume a reload reg is still good after a call insn
4424 if it is a call-used reg, or if it contains a value that will
4425 be partially clobbered by the call. */
4426 else if (CALL_P (insn))
4428 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4429 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4434 free (reg_last_reload_reg);
4435 CLEAR_REG_SET (®_has_output_reload);
4438 /* Discard all record of any value reloaded from X,
4439 or reloaded in X from someplace else;
4440 unless X is an output reload reg of the current insn.
4442 X may be a hard reg (the reload reg)
4443 or it may be a pseudo reg that was reloaded from.
4445 When DATA is non-NULL just mark the registers in regset
4446 to be forgotten later. */
4449 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4454 regset regs = (regset) data;
4456 /* note_stores does give us subregs of hard regs,
4457 subreg_regno_offset requires a hard reg. */
4458 while (GET_CODE (x) == SUBREG)
4460 /* We ignore the subreg offset when calculating the regno,
4461 because we are using the entire underlying hard register
4471 if (regno >= FIRST_PSEUDO_REGISTER)
4477 nr = hard_regno_nregs[regno][GET_MODE (x)];
4478 /* Storing into a spilled-reg invalidates its contents.
4479 This can happen if a block-local pseudo is allocated to that reg
4480 and it wasn't spilled because this block's total need is 0.
4481 Then some insn might have an optional reload and use this reg. */
4483 for (i = 0; i < nr; i++)
4484 /* But don't do this if the reg actually serves as an output
4485 reload reg in the current instruction. */
4487 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4489 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4490 spill_reg_store[regno + i] = 0;
4496 SET_REGNO_REG_SET (regs, regno + nr);
4499 /* Since value of X has changed,
4500 forget any value previously copied from it. */
4503 /* But don't forget a copy if this is the output reload
4504 that establishes the copy's validity. */
4506 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4507 reg_last_reload_reg[regno + nr] = 0;
4511 /* Forget the reloads marked in regset by previous function. */
4513 forget_marked_reloads (regset regs)
4516 reg_set_iterator rsi;
4517 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4519 if (reg < FIRST_PSEUDO_REGISTER
4520 /* But don't do this if the reg actually serves as an output
4521 reload reg in the current instruction. */
4523 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4525 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4526 spill_reg_store[reg] = 0;
4529 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4530 reg_last_reload_reg[reg] = 0;
4534 /* The following HARD_REG_SETs indicate when each hard register is
4535 used for a reload of various parts of the current insn. */
4537 /* If reg is unavailable for all reloads. */
4538 static HARD_REG_SET reload_reg_unavailable;
4539 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4540 static HARD_REG_SET reload_reg_used;
4541 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4542 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4543 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4544 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4545 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4546 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4547 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4548 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4549 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4550 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4551 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4552 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4553 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4554 static HARD_REG_SET reload_reg_used_in_op_addr;
4555 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4556 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4557 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4558 static HARD_REG_SET reload_reg_used_in_insn;
4559 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4560 static HARD_REG_SET reload_reg_used_in_other_addr;
4562 /* If reg is in use as a reload reg for any sort of reload. */
4563 static HARD_REG_SET reload_reg_used_at_all;
4565 /* If reg is use as an inherited reload. We just mark the first register
4567 static HARD_REG_SET reload_reg_used_for_inherit;
4569 /* Records which hard regs are used in any way, either as explicit use or
4570 by being allocated to a pseudo during any point of the current insn. */
4571 static HARD_REG_SET reg_used_in_insn;
4573 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4574 TYPE. MODE is used to indicate how many consecutive regs are
4578 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4579 enum machine_mode mode)
4581 unsigned int nregs = hard_regno_nregs[regno][mode];
4584 for (i = regno; i < nregs + regno; i++)
4589 SET_HARD_REG_BIT (reload_reg_used, i);
4592 case RELOAD_FOR_INPUT_ADDRESS:
4593 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4596 case RELOAD_FOR_INPADDR_ADDRESS:
4597 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4600 case RELOAD_FOR_OUTPUT_ADDRESS:
4601 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4604 case RELOAD_FOR_OUTADDR_ADDRESS:
4605 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4608 case RELOAD_FOR_OPERAND_ADDRESS:
4609 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4612 case RELOAD_FOR_OPADDR_ADDR:
4613 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4616 case RELOAD_FOR_OTHER_ADDRESS:
4617 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4620 case RELOAD_FOR_INPUT:
4621 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4624 case RELOAD_FOR_OUTPUT:
4625 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4628 case RELOAD_FOR_INSN:
4629 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4633 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4637 /* Similarly, but show REGNO is no longer in use for a reload. */
4640 clear_reload_reg_in_use (unsigned int regno, int opnum,
4641 enum reload_type type, enum machine_mode mode)
4643 unsigned int nregs = hard_regno_nregs[regno][mode];
4644 unsigned int start_regno, end_regno, r;
4646 /* A complication is that for some reload types, inheritance might
4647 allow multiple reloads of the same types to share a reload register.
4648 We set check_opnum if we have to check only reloads with the same
4649 operand number, and check_any if we have to check all reloads. */
4650 int check_opnum = 0;
4652 HARD_REG_SET *used_in_set;
4657 used_in_set = &reload_reg_used;
4660 case RELOAD_FOR_INPUT_ADDRESS:
4661 used_in_set = &reload_reg_used_in_input_addr[opnum];
4664 case RELOAD_FOR_INPADDR_ADDRESS:
4666 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4669 case RELOAD_FOR_OUTPUT_ADDRESS:
4670 used_in_set = &reload_reg_used_in_output_addr[opnum];
4673 case RELOAD_FOR_OUTADDR_ADDRESS:
4675 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4678 case RELOAD_FOR_OPERAND_ADDRESS:
4679 used_in_set = &reload_reg_used_in_op_addr;
4682 case RELOAD_FOR_OPADDR_ADDR:
4684 used_in_set = &reload_reg_used_in_op_addr_reload;
4687 case RELOAD_FOR_OTHER_ADDRESS:
4688 used_in_set = &reload_reg_used_in_other_addr;
4692 case RELOAD_FOR_INPUT:
4693 used_in_set = &reload_reg_used_in_input[opnum];
4696 case RELOAD_FOR_OUTPUT:
4697 used_in_set = &reload_reg_used_in_output[opnum];
4700 case RELOAD_FOR_INSN:
4701 used_in_set = &reload_reg_used_in_insn;
4706 /* We resolve conflicts with remaining reloads of the same type by
4707 excluding the intervals of reload registers by them from the
4708 interval of freed reload registers. Since we only keep track of
4709 one set of interval bounds, we might have to exclude somewhat
4710 more than what would be necessary if we used a HARD_REG_SET here.
4711 But this should only happen very infrequently, so there should
4712 be no reason to worry about it. */
4714 start_regno = regno;
4715 end_regno = regno + nregs;
4716 if (check_opnum || check_any)
4718 for (i = n_reloads - 1; i >= 0; i--)
4720 if (rld[i].when_needed == type
4721 && (check_any || rld[i].opnum == opnum)
4724 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4725 unsigned int conflict_end
4726 = end_hard_regno (rld[i].mode, conflict_start);
4728 /* If there is an overlap with the first to-be-freed register,
4729 adjust the interval start. */
4730 if (conflict_start <= start_regno && conflict_end > start_regno)
4731 start_regno = conflict_end;
4732 /* Otherwise, if there is a conflict with one of the other
4733 to-be-freed registers, adjust the interval end. */
4734 if (conflict_start > start_regno && conflict_start < end_regno)
4735 end_regno = conflict_start;
4740 for (r = start_regno; r < end_regno; r++)
4741 CLEAR_HARD_REG_BIT (*used_in_set, r);
4744 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4745 specified by OPNUM and TYPE. */
4748 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4752 /* In use for a RELOAD_OTHER means it's not available for anything. */
4753 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4754 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4760 /* In use for anything means we can't use it for RELOAD_OTHER. */
4761 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4762 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4763 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4764 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4767 for (i = 0; i < reload_n_operands; i++)
4768 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4769 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4770 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4771 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4772 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4773 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4778 case RELOAD_FOR_INPUT:
4779 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4780 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4783 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4786 /* If it is used for some other input, can't use it. */
4787 for (i = 0; i < reload_n_operands; i++)
4788 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4791 /* If it is used in a later operand's address, can't use it. */
4792 for (i = opnum + 1; i < reload_n_operands; i++)
4793 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4794 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4799 case RELOAD_FOR_INPUT_ADDRESS:
4800 /* Can't use a register if it is used for an input address for this
4801 operand or used as an input in an earlier one. */
4802 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4803 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4806 for (i = 0; i < opnum; i++)
4807 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4812 case RELOAD_FOR_INPADDR_ADDRESS:
4813 /* Can't use a register if it is used for an input address
4814 for this operand or used as an input in an earlier
4816 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4819 for (i = 0; i < opnum; i++)
4820 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4825 case RELOAD_FOR_OUTPUT_ADDRESS:
4826 /* Can't use a register if it is used for an output address for this
4827 operand or used as an output in this or a later operand. Note
4828 that multiple output operands are emitted in reverse order, so
4829 the conflicting ones are those with lower indices. */
4830 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4833 for (i = 0; i <= opnum; i++)
4834 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4839 case RELOAD_FOR_OUTADDR_ADDRESS:
4840 /* Can't use a register if it is used for an output address
4841 for this operand or used as an output in this or a
4842 later operand. Note that multiple output operands are
4843 emitted in reverse order, so the conflicting ones are
4844 those with lower indices. */
4845 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4848 for (i = 0; i <= opnum; i++)
4849 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4854 case RELOAD_FOR_OPERAND_ADDRESS:
4855 for (i = 0; i < reload_n_operands; i++)
4856 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4859 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4860 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4862 case RELOAD_FOR_OPADDR_ADDR:
4863 for (i = 0; i < reload_n_operands; i++)
4864 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4867 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4869 case RELOAD_FOR_OUTPUT:
4870 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4871 outputs, or an operand address for this or an earlier output.
4872 Note that multiple output operands are emitted in reverse order,
4873 so the conflicting ones are those with higher indices. */
4874 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4877 for (i = 0; i < reload_n_operands; i++)
4878 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4881 for (i = opnum; i < reload_n_operands; i++)
4882 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4883 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4888 case RELOAD_FOR_INSN:
4889 for (i = 0; i < reload_n_operands; i++)
4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4891 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4894 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4895 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4897 case RELOAD_FOR_OTHER_ADDRESS:
4898 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4905 /* Return 1 if the value in reload reg REGNO, as used by a reload
4906 needed for the part of the insn specified by OPNUM and TYPE,
4907 is still available in REGNO at the end of the insn.
4909 We can assume that the reload reg was already tested for availability
4910 at the time it is needed, and we should not check this again,
4911 in case the reg has already been marked in use. */
4914 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4921 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4922 its value must reach the end. */
4925 /* If this use is for part of the insn,
4926 its value reaches if no subsequent part uses the same register.
4927 Just like the above function, don't try to do this with lots
4930 case RELOAD_FOR_OTHER_ADDRESS:
4931 /* Here we check for everything else, since these don't conflict
4932 with anything else and everything comes later. */
4934 for (i = 0; i < reload_n_operands; i++)
4935 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4936 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4937 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4938 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4939 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4940 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4943 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4944 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4945 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4946 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4948 case RELOAD_FOR_INPUT_ADDRESS:
4949 case RELOAD_FOR_INPADDR_ADDRESS:
4950 /* Similar, except that we check only for this and subsequent inputs
4951 and the address of only subsequent inputs and we do not need
4952 to check for RELOAD_OTHER objects since they are known not to
4955 for (i = opnum; i < reload_n_operands; i++)
4956 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4959 for (i = opnum + 1; i < reload_n_operands; i++)
4960 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4961 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4964 for (i = 0; i < reload_n_operands; i++)
4965 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4966 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4967 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4970 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4973 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4974 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4975 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4977 case RELOAD_FOR_INPUT:
4978 /* Similar to input address, except we start at the next operand for
4979 both input and input address and we do not check for
4980 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4983 for (i = opnum + 1; i < reload_n_operands; i++)
4984 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4985 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4986 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4989 /* ... fall through ... */
4991 case RELOAD_FOR_OPERAND_ADDRESS:
4992 /* Check outputs and their addresses. */
4994 for (i = 0; i < reload_n_operands; i++)
4995 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4996 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4997 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5000 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
5002 case RELOAD_FOR_OPADDR_ADDR:
5003 for (i = 0; i < reload_n_operands; i++)
5004 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5005 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
5006 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
5009 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
5010 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
5011 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
5013 case RELOAD_FOR_INSN:
5014 /* These conflict with other outputs with RELOAD_OTHER. So
5015 we need only check for output addresses. */
5017 opnum = reload_n_operands;
5019 /* ... fall through ... */
5021 case RELOAD_FOR_OUTPUT:
5022 case RELOAD_FOR_OUTPUT_ADDRESS:
5023 case RELOAD_FOR_OUTADDR_ADDRESS:
5024 /* We already know these can't conflict with a later output. So the
5025 only thing to check are later output addresses.
5026 Note that multiple output operands are emitted in reverse order,
5027 so the conflicting ones are those with lower indices. */
5028 for (i = 0; i < opnum; i++)
5029 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
5030 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
5040 /* Like reload_reg_reaches_end_p, but check that the condition holds for
5041 every register in the range [REGNO, REGNO + NREGS). */
5044 reload_regs_reach_end_p (unsigned int regno, int nregs,
5045 int opnum, enum reload_type type)
5049 for (i = 0; i < nregs; i++)
5050 if (!reload_reg_reaches_end_p (regno + i, opnum, type))
5056 /* Returns whether R1 and R2 are uniquely chained: the value of one
5057 is used by the other, and that value is not used by any other
5058 reload for this insn. This is used to partially undo the decision
5059 made in find_reloads when in the case of multiple
5060 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
5061 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
5062 reloads. This code tries to avoid the conflict created by that
5063 change. It might be cleaner to explicitly keep track of which
5064 RELOAD_FOR_OPADDR_ADDR reload is associated with which
5065 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
5066 this after the fact. */
5068 reloads_unique_chain_p (int r1, int r2)
5072 /* We only check input reloads. */
5073 if (! rld[r1].in || ! rld[r2].in)
5076 /* Avoid anything with output reloads. */
5077 if (rld[r1].out || rld[r2].out)
5080 /* "chained" means one reload is a component of the other reload,
5081 not the same as the other reload. */
5082 if (rld[r1].opnum != rld[r2].opnum
5083 || rtx_equal_p (rld[r1].in, rld[r2].in)
5084 || rld[r1].optional || rld[r2].optional
5085 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
5086 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
5089 for (i = 0; i < n_reloads; i ++)
5090 /* Look for input reloads that aren't our two */
5091 if (i != r1 && i != r2 && rld[i].in)
5093 /* If our reload is mentioned at all, it isn't a simple chain. */
5094 if (reg_mentioned_p (rld[r1].in, rld[i].in))
5101 /* The recursive function change all occurrences of WHAT in *WHERE
5104 substitute (rtx *where, const_rtx what, rtx repl)
5113 if (*where == what || rtx_equal_p (*where, what))
5119 code = GET_CODE (*where);
5120 fmt = GET_RTX_FORMAT (code);
5121 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
5127 for (j = XVECLEN (*where, i) - 1; j >= 0; j--)
5128 substitute (&XVECEXP (*where, i, j), what, repl);
5130 else if (fmt[i] == 'e')
5131 substitute (&XEXP (*where, i), what, repl);
5135 /* The function returns TRUE if chain of reload R1 and R2 (in any
5136 order) can be evaluated without usage of intermediate register for
5137 the reload containing another reload. It is important to see
5138 gen_reload to understand what the function is trying to do. As an
5139 example, let us have reload chain
5142 r1: <something> + const
5144 and reload R2 got reload reg HR. The function returns true if
5145 there is a correct insn HR = HR + <something>. Otherwise,
5146 gen_reload will use intermediate register (and this is the reload
5147 reg for R1) to reload <something>.
5149 We need this function to find a conflict for chain reloads. In our
5150 example, if HR = HR + <something> is incorrect insn, then we cannot
5151 use HR as a reload register for R2. If we do use it then we get a
5160 gen_reload_chain_without_interm_reg_p (int r1, int r2)
5164 rtx out, in, tem, insn;
5165 rtx last = get_last_insn ();
5167 /* Make r2 a component of r1. */
5168 if (reg_mentioned_p (rld[r1].in, rld[r2].in))
5174 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in));
5175 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno;
5176 gcc_assert (regno >= 0);
5177 out = gen_rtx_REG (rld[r1].mode, regno);
5178 in = copy_rtx (rld[r1].in);
5179 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno));
5181 /* If IN is a paradoxical SUBREG, remove it and try to put the
5182 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
5183 if (GET_CODE (in) == SUBREG
5184 && (GET_MODE_SIZE (GET_MODE (in))
5185 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
5186 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
5187 in = SUBREG_REG (in), out = tem;
5189 if (GET_CODE (in) == PLUS
5190 && (REG_P (XEXP (in, 0))
5191 || GET_CODE (XEXP (in, 0)) == SUBREG
5192 || MEM_P (XEXP (in, 0)))
5193 && (REG_P (XEXP (in, 1))
5194 || GET_CODE (XEXP (in, 1)) == SUBREG
5195 || CONSTANT_P (XEXP (in, 1))
5196 || MEM_P (XEXP (in, 1))))
5198 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
5199 code = recog_memoized (insn);
5204 extract_insn (insn);
5205 /* We want constrain operands to treat this insn strictly in
5206 its validity determination, i.e., the way it would after
5207 reload has completed. */
5208 result = constrain_operands (1);
5211 delete_insns_since (last);
5215 /* It looks like other cases in gen_reload are not possible for
5216 chain reloads or do need an intermediate hard registers. */
5220 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
5223 This function uses the same algorithm as reload_reg_free_p above. */
5226 reloads_conflict (int r1, int r2)
5228 enum reload_type r1_type = rld[r1].when_needed;
5229 enum reload_type r2_type = rld[r2].when_needed;
5230 int r1_opnum = rld[r1].opnum;
5231 int r2_opnum = rld[r2].opnum;
5233 /* RELOAD_OTHER conflicts with everything. */
5234 if (r2_type == RELOAD_OTHER)
5237 /* Otherwise, check conflicts differently for each type. */
5241 case RELOAD_FOR_INPUT:
5242 return (r2_type == RELOAD_FOR_INSN
5243 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
5244 || r2_type == RELOAD_FOR_OPADDR_ADDR
5245 || r2_type == RELOAD_FOR_INPUT
5246 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
5247 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
5248 && r2_opnum > r1_opnum));
5250 case RELOAD_FOR_INPUT_ADDRESS:
5251 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5252 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5254 case RELOAD_FOR_INPADDR_ADDRESS:
5255 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5256 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5258 case RELOAD_FOR_OUTPUT_ADDRESS:
5259 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5260 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5262 case RELOAD_FOR_OUTADDR_ADDRESS:
5263 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5264 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5266 case RELOAD_FOR_OPERAND_ADDRESS:
5267 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5268 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5269 && (!reloads_unique_chain_p (r1, r2)
5270 || !gen_reload_chain_without_interm_reg_p (r1, r2))));
5272 case RELOAD_FOR_OPADDR_ADDR:
5273 return (r2_type == RELOAD_FOR_INPUT
5274 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5276 case RELOAD_FOR_OUTPUT:
5277 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5278 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5279 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5280 && r2_opnum >= r1_opnum));
5282 case RELOAD_FOR_INSN:
5283 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5284 || r2_type == RELOAD_FOR_INSN
5285 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5287 case RELOAD_FOR_OTHER_ADDRESS:
5288 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5298 /* Indexed by reload number, 1 if incoming value
5299 inherited from previous insns. */
5300 static char reload_inherited[MAX_RELOADS];
5302 /* For an inherited reload, this is the insn the reload was inherited from,
5303 if we know it. Otherwise, this is 0. */
5304 static rtx reload_inheritance_insn[MAX_RELOADS];
5306 /* If nonzero, this is a place to get the value of the reload,
5307 rather than using reload_in. */
5308 static rtx reload_override_in[MAX_RELOADS];
5310 /* For each reload, the hard register number of the register used,
5311 or -1 if we did not need a register for this reload. */
5312 static int reload_spill_index[MAX_RELOADS];
5314 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */
5315 static rtx reload_reg_rtx_for_input[MAX_RELOADS];
5317 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */
5318 static rtx reload_reg_rtx_for_output[MAX_RELOADS];
5320 /* Subroutine of free_for_value_p, used to check a single register.
5321 START_REGNO is the starting regno of the full reload register
5322 (possibly comprising multiple hard registers) that we are considering. */
5325 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5326 enum reload_type type, rtx value, rtx out,
5327 int reloadnum, int ignore_address_reloads)
5330 /* Set if we see an input reload that must not share its reload register
5331 with any new earlyclobber, but might otherwise share the reload
5332 register with an output or input-output reload. */
5333 int check_earlyclobber = 0;
5337 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5340 if (out == const0_rtx)
5346 /* We use some pseudo 'time' value to check if the lifetimes of the
5347 new register use would overlap with the one of a previous reload
5348 that is not read-only or uses a different value.
5349 The 'time' used doesn't have to be linear in any shape or form, just
5351 Some reload types use different 'buckets' for each operand.
5352 So there are MAX_RECOG_OPERANDS different time values for each
5354 We compute TIME1 as the time when the register for the prospective
5355 new reload ceases to be live, and TIME2 for each existing
5356 reload as the time when that the reload register of that reload
5358 Where there is little to be gained by exact lifetime calculations,
5359 we just make conservative assumptions, i.e. a longer lifetime;
5360 this is done in the 'default:' cases. */
5363 case RELOAD_FOR_OTHER_ADDRESS:
5364 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5365 time1 = copy ? 0 : 1;
5368 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5370 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5371 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5372 respectively, to the time values for these, we get distinct time
5373 values. To get distinct time values for each operand, we have to
5374 multiply opnum by at least three. We round that up to four because
5375 multiply by four is often cheaper. */
5376 case RELOAD_FOR_INPADDR_ADDRESS:
5377 time1 = opnum * 4 + 2;
5379 case RELOAD_FOR_INPUT_ADDRESS:
5380 time1 = opnum * 4 + 3;
5382 case RELOAD_FOR_INPUT:
5383 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5384 executes (inclusive). */
5385 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5387 case RELOAD_FOR_OPADDR_ADDR:
5389 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5390 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5392 case RELOAD_FOR_OPERAND_ADDRESS:
5393 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5395 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5397 case RELOAD_FOR_OUTADDR_ADDRESS:
5398 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5400 case RELOAD_FOR_OUTPUT_ADDRESS:
5401 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5404 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5407 for (i = 0; i < n_reloads; i++)
5409 rtx reg = rld[i].reg_rtx;
5410 if (reg && REG_P (reg)
5411 && ((unsigned) regno - true_regnum (reg)
5412 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5415 rtx other_input = rld[i].in;
5417 /* If the other reload loads the same input value, that
5418 will not cause a conflict only if it's loading it into
5419 the same register. */
5420 if (true_regnum (reg) != start_regno)
5421 other_input = NULL_RTX;
5422 if (! other_input || ! rtx_equal_p (other_input, value)
5423 || rld[i].out || out)
5426 switch (rld[i].when_needed)
5428 case RELOAD_FOR_OTHER_ADDRESS:
5431 case RELOAD_FOR_INPADDR_ADDRESS:
5432 /* find_reloads makes sure that a
5433 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5434 by at most one - the first -
5435 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5436 address reload is inherited, the address address reload
5437 goes away, so we can ignore this conflict. */
5438 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5439 && ignore_address_reloads
5440 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5441 Then the address address is still needed to store
5442 back the new address. */
5443 && ! rld[reloadnum].out)
5445 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5446 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5448 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5449 && ignore_address_reloads
5450 /* Unless we are reloading an auto_inc expression. */
5451 && ! rld[reloadnum].out)
5453 time2 = rld[i].opnum * 4 + 2;
5455 case RELOAD_FOR_INPUT_ADDRESS:
5456 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5457 && ignore_address_reloads
5458 && ! rld[reloadnum].out)
5460 time2 = rld[i].opnum * 4 + 3;
5462 case RELOAD_FOR_INPUT:
5463 time2 = rld[i].opnum * 4 + 4;
5464 check_earlyclobber = 1;
5466 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5467 == MAX_RECOG_OPERAND * 4 */
5468 case RELOAD_FOR_OPADDR_ADDR:
5469 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5470 && ignore_address_reloads
5471 && ! rld[reloadnum].out)
5473 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5475 case RELOAD_FOR_OPERAND_ADDRESS:
5476 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5477 check_earlyclobber = 1;
5479 case RELOAD_FOR_INSN:
5480 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5482 case RELOAD_FOR_OUTPUT:
5483 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5484 instruction is executed. */
5485 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5487 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5488 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5490 case RELOAD_FOR_OUTADDR_ADDRESS:
5491 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5492 && ignore_address_reloads
5493 && ! rld[reloadnum].out)
5495 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5497 case RELOAD_FOR_OUTPUT_ADDRESS:
5498 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5501 /* If there is no conflict in the input part, handle this
5502 like an output reload. */
5503 if (! rld[i].in || rtx_equal_p (other_input, value))
5505 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5506 /* Earlyclobbered outputs must conflict with inputs. */
5507 if (earlyclobber_operand_p (rld[i].out))
5508 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5513 /* RELOAD_OTHER might be live beyond instruction execution,
5514 but this is not obvious when we set time2 = 1. So check
5515 here if there might be a problem with the new reload
5516 clobbering the register used by the RELOAD_OTHER. */
5524 && (! rld[i].in || rld[i].out
5525 || ! rtx_equal_p (other_input, value)))
5526 || (out && rld[reloadnum].out_reg
5527 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5533 /* Earlyclobbered outputs must conflict with inputs. */
5534 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5540 /* Return 1 if the value in reload reg REGNO, as used by a reload
5541 needed for the part of the insn specified by OPNUM and TYPE,
5542 may be used to load VALUE into it.
5544 MODE is the mode in which the register is used, this is needed to
5545 determine how many hard regs to test.
5547 Other read-only reloads with the same value do not conflict
5548 unless OUT is nonzero and these other reloads have to live while
5549 output reloads live.
5550 If OUT is CONST0_RTX, this is a special case: it means that the
5551 test should not be for using register REGNO as reload register, but
5552 for copying from register REGNO into the reload register.
5554 RELOADNUM is the number of the reload we want to load this value for;
5555 a reload does not conflict with itself.
5557 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5558 reloads that load an address for the very reload we are considering.
5560 The caller has to make sure that there is no conflict with the return
5564 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5565 enum reload_type type, rtx value, rtx out, int reloadnum,
5566 int ignore_address_reloads)
5568 int nregs = hard_regno_nregs[regno][mode];
5570 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5571 value, out, reloadnum,
5572 ignore_address_reloads))
5577 /* Return nonzero if the rtx X is invariant over the current function. */
5578 /* ??? Actually, the places where we use this expect exactly what is
5579 tested here, and not everything that is function invariant. In
5580 particular, the frame pointer and arg pointer are special cased;
5581 pic_offset_table_rtx is not, and we must not spill these things to
5585 function_invariant_p (const_rtx x)
5589 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5591 if (GET_CODE (x) == PLUS
5592 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5593 && CONSTANT_P (XEXP (x, 1)))
5598 /* Determine whether the reload reg X overlaps any rtx'es used for
5599 overriding inheritance. Return nonzero if so. */
5602 conflicts_with_override (rtx x)
5605 for (i = 0; i < n_reloads; i++)
5606 if (reload_override_in[i]
5607 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5612 /* Give an error message saying we failed to find a reload for INSN,
5613 and clear out reload R. */
5615 failed_reload (rtx insn, int r)
5617 if (asm_noperands (PATTERN (insn)) < 0)
5618 /* It's the compiler's fault. */
5619 fatal_insn ("could not find a spill register", insn);
5621 /* It's the user's fault; the operand's mode and constraint
5622 don't match. Disable this reload so we don't crash in final. */
5623 error_for_asm (insn,
5624 "%<asm%> operand constraint incompatible with operand size");
5628 rld[r].optional = 1;
5629 rld[r].secondary_p = 1;
5632 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5633 for reload R. If it's valid, get an rtx for it. Return nonzero if
5636 set_reload_reg (int i, int r)
5639 rtx reg = spill_reg_rtx[i];
5641 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5642 spill_reg_rtx[i] = reg
5643 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5645 regno = true_regnum (reg);
5647 /* Detect when the reload reg can't hold the reload mode.
5648 This used to be one `if', but Sequent compiler can't handle that. */
5649 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5651 enum machine_mode test_mode = VOIDmode;
5653 test_mode = GET_MODE (rld[r].in);
5654 /* If rld[r].in has VOIDmode, it means we will load it
5655 in whatever mode the reload reg has: to wit, rld[r].mode.
5656 We have already tested that for validity. */
5657 /* Aside from that, we need to test that the expressions
5658 to reload from or into have modes which are valid for this
5659 reload register. Otherwise the reload insns would be invalid. */
5660 if (! (rld[r].in != 0 && test_mode != VOIDmode
5661 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5662 if (! (rld[r].out != 0
5663 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5665 /* The reg is OK. */
5668 /* Mark as in use for this insn the reload regs we use
5670 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5671 rld[r].when_needed, rld[r].mode);
5673 rld[r].reg_rtx = reg;
5674 reload_spill_index[r] = spill_regs[i];
5681 /* Find a spill register to use as a reload register for reload R.
5682 LAST_RELOAD is nonzero if this is the last reload for the insn being
5685 Set rld[R].reg_rtx to the register allocated.
5687 We return 1 if successful, or 0 if we couldn't find a spill reg and
5688 we didn't change anything. */
5691 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5696 /* If we put this reload ahead, thinking it is a group,
5697 then insist on finding a group. Otherwise we can grab a
5698 reg that some other reload needs.
5699 (That can happen when we have a 68000 DATA_OR_FP_REG
5700 which is a group of data regs or one fp reg.)
5701 We need not be so restrictive if there are no more reloads
5704 ??? Really it would be nicer to have smarter handling
5705 for that kind of reg class, where a problem like this is normal.
5706 Perhaps those classes should be avoided for reloading
5707 by use of more alternatives. */
5709 int force_group = rld[r].nregs > 1 && ! last_reload;
5711 /* If we want a single register and haven't yet found one,
5712 take any reg in the right class and not in use.
5713 If we want a consecutive group, here is where we look for it.
5715 We use two passes so we can first look for reload regs to
5716 reuse, which are already in use for other reloads in this insn,
5717 and only then use additional registers.
5718 I think that maximizing reuse is needed to make sure we don't
5719 run out of reload regs. Suppose we have three reloads, and
5720 reloads A and B can share regs. These need two regs.
5721 Suppose A and B are given different regs.
5722 That leaves none for C. */
5723 for (pass = 0; pass < 2; pass++)
5725 /* I is the index in spill_regs.
5726 We advance it round-robin between insns to use all spill regs
5727 equally, so that inherited reloads have a chance
5728 of leapfrogging each other. */
5732 for (count = 0; count < n_spills; count++)
5734 int rclass = (int) rld[r].rclass;
5740 regnum = spill_regs[i];
5742 if ((reload_reg_free_p (regnum, rld[r].opnum,
5745 /* We check reload_reg_used to make sure we
5746 don't clobber the return register. */
5747 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5748 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5749 rld[r].when_needed, rld[r].in,
5751 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum)
5752 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5753 /* Look first for regs to share, then for unshared. But
5754 don't share regs used for inherited reloads; they are
5755 the ones we want to preserve. */
5757 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5759 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5762 int nr = hard_regno_nregs[regnum][rld[r].mode];
5763 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5764 (on 68000) got us two FP regs. If NR is 1,
5765 we would reject both of them. */
5768 /* If we need only one reg, we have already won. */
5771 /* But reject a single reg if we demand a group. */
5776 /* Otherwise check that as many consecutive regs as we need
5777 are available here. */
5780 int regno = regnum + nr - 1;
5781 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno)
5782 && spill_reg_order[regno] >= 0
5783 && reload_reg_free_p (regno, rld[r].opnum,
5784 rld[r].when_needed)))
5793 /* If we found something on pass 1, omit pass 2. */
5794 if (count < n_spills)
5798 /* We should have found a spill register by now. */
5799 if (count >= n_spills)
5802 /* I is the index in SPILL_REG_RTX of the reload register we are to
5803 allocate. Get an rtx for it and find its register number. */
5805 return set_reload_reg (i, r);
5808 /* Initialize all the tables needed to allocate reload registers.
5809 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5810 is the array we use to restore the reg_rtx field for every reload. */
5813 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5817 for (i = 0; i < n_reloads; i++)
5818 rld[i].reg_rtx = save_reload_reg_rtx[i];
5820 memset (reload_inherited, 0, MAX_RELOADS);
5821 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5822 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5824 CLEAR_HARD_REG_SET (reload_reg_used);
5825 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5826 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5827 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5828 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5829 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5831 CLEAR_HARD_REG_SET (reg_used_in_insn);
5834 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5835 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5836 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5837 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5838 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5839 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5842 for (i = 0; i < reload_n_operands; i++)
5844 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5845 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5846 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5847 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5848 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5849 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5852 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5854 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5856 for (i = 0; i < n_reloads; i++)
5857 /* If we have already decided to use a certain register,
5858 don't use it in another way. */
5860 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5861 rld[i].when_needed, rld[i].mode);
5864 /* Assign hard reg targets for the pseudo-registers we must reload
5865 into hard regs for this insn.
5866 Also output the instructions to copy them in and out of the hard regs.
5868 For machines with register classes, we are responsible for
5869 finding a reload reg in the proper class. */
5872 choose_reload_regs (struct insn_chain *chain)
5874 rtx insn = chain->insn;
5876 unsigned int max_group_size = 1;
5877 enum reg_class group_class = NO_REGS;
5878 int pass, win, inheritance;
5880 rtx save_reload_reg_rtx[MAX_RELOADS];
5882 /* In order to be certain of getting the registers we need,
5883 we must sort the reloads into order of increasing register class.
5884 Then our grabbing of reload registers will parallel the process
5885 that provided the reload registers.
5887 Also note whether any of the reloads wants a consecutive group of regs.
5888 If so, record the maximum size of the group desired and what
5889 register class contains all the groups needed by this insn. */
5891 for (j = 0; j < n_reloads; j++)
5893 reload_order[j] = j;
5894 if (rld[j].reg_rtx != NULL_RTX)
5896 gcc_assert (REG_P (rld[j].reg_rtx)
5897 && HARD_REGISTER_P (rld[j].reg_rtx));
5898 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5901 reload_spill_index[j] = -1;
5903 if (rld[j].nregs > 1)
5905 max_group_size = MAX (rld[j].nregs, max_group_size);
5907 = reg_class_superunion[(int) rld[j].rclass][(int) group_class];
5910 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5914 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5916 /* If -O, try first with inheritance, then turning it off.
5917 If not -O, don't do inheritance.
5918 Using inheritance when not optimizing leads to paradoxes
5919 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5920 because one side of the comparison might be inherited. */
5922 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5924 choose_reload_regs_init (chain, save_reload_reg_rtx);
5926 /* Process the reloads in order of preference just found.
5927 Beyond this point, subregs can be found in reload_reg_rtx.
5929 This used to look for an existing reloaded home for all of the
5930 reloads, and only then perform any new reloads. But that could lose
5931 if the reloads were done out of reg-class order because a later
5932 reload with a looser constraint might have an old home in a register
5933 needed by an earlier reload with a tighter constraint.
5935 To solve this, we make two passes over the reloads, in the order
5936 described above. In the first pass we try to inherit a reload
5937 from a previous insn. If there is a later reload that needs a
5938 class that is a proper subset of the class being processed, we must
5939 also allocate a spill register during the first pass.
5941 Then make a second pass over the reloads to allocate any reloads
5942 that haven't been given registers yet. */
5944 for (j = 0; j < n_reloads; j++)
5946 int r = reload_order[j];
5947 rtx search_equiv = NULL_RTX;
5949 /* Ignore reloads that got marked inoperative. */
5950 if (rld[r].out == 0 && rld[r].in == 0
5951 && ! rld[r].secondary_p)
5954 /* If find_reloads chose to use reload_in or reload_out as a reload
5955 register, we don't need to chose one. Otherwise, try even if it
5956 found one since we might save an insn if we find the value lying
5958 Try also when reload_in is a pseudo without a hard reg. */
5959 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5960 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5961 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5962 && !MEM_P (rld[r].in)
5963 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5966 #if 0 /* No longer needed for correct operation.
5967 It might give better code, or might not; worth an experiment? */
5968 /* If this is an optional reload, we can't inherit from earlier insns
5969 until we are sure that any non-optional reloads have been allocated.
5970 The following code takes advantage of the fact that optional reloads
5971 are at the end of reload_order. */
5972 if (rld[r].optional != 0)
5973 for (i = 0; i < j; i++)
5974 if ((rld[reload_order[i]].out != 0
5975 || rld[reload_order[i]].in != 0
5976 || rld[reload_order[i]].secondary_p)
5977 && ! rld[reload_order[i]].optional
5978 && rld[reload_order[i]].reg_rtx == 0)
5979 allocate_reload_reg (chain, reload_order[i], 0);
5982 /* First see if this pseudo is already available as reloaded
5983 for a previous insn. We cannot try to inherit for reloads
5984 that are smaller than the maximum number of registers needed
5985 for groups unless the register we would allocate cannot be used
5988 We could check here to see if this is a secondary reload for
5989 an object that is already in a register of the desired class.
5990 This would avoid the need for the secondary reload register.
5991 But this is complex because we can't easily determine what
5992 objects might want to be loaded via this reload. So let a
5993 register be allocated here. In `emit_reload_insns' we suppress
5994 one of the loads in the case described above. */
6000 enum machine_mode mode = VOIDmode;
6004 else if (REG_P (rld[r].in))
6006 regno = REGNO (rld[r].in);
6007 mode = GET_MODE (rld[r].in);
6009 else if (REG_P (rld[r].in_reg))
6011 regno = REGNO (rld[r].in_reg);
6012 mode = GET_MODE (rld[r].in_reg);
6014 else if (GET_CODE (rld[r].in_reg) == SUBREG
6015 && REG_P (SUBREG_REG (rld[r].in_reg)))
6017 regno = REGNO (SUBREG_REG (rld[r].in_reg));
6018 if (regno < FIRST_PSEUDO_REGISTER)
6019 regno = subreg_regno (rld[r].in_reg);
6021 byte = SUBREG_BYTE (rld[r].in_reg);
6022 mode = GET_MODE (rld[r].in_reg);
6025 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
6026 && REG_P (XEXP (rld[r].in_reg, 0)))
6028 regno = REGNO (XEXP (rld[r].in_reg, 0));
6029 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
6030 rld[r].out = rld[r].in;
6034 /* This won't work, since REGNO can be a pseudo reg number.
6035 Also, it takes much more hair to keep track of all the things
6036 that can invalidate an inherited reload of part of a pseudoreg. */
6037 else if (GET_CODE (rld[r].in) == SUBREG
6038 && REG_P (SUBREG_REG (rld[r].in)))
6039 regno = subreg_regno (rld[r].in);
6043 && reg_last_reload_reg[regno] != 0
6044 #ifdef CANNOT_CHANGE_MODE_CLASS
6045 /* Verify that the register it's in can be used in
6047 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
6048 GET_MODE (reg_last_reload_reg[regno]),
6053 enum reg_class rclass = rld[r].rclass, last_class;
6054 rtx last_reg = reg_last_reload_reg[regno];
6055 enum machine_mode need_mode;
6057 i = REGNO (last_reg);
6058 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
6059 last_class = REGNO_REG_CLASS (i);
6065 = smallest_mode_for_size
6066 (GET_MODE_BITSIZE (mode) + byte * BITS_PER_UNIT,
6067 GET_MODE_CLASS (mode) == MODE_PARTIAL_INT
6068 ? MODE_INT : GET_MODE_CLASS (mode));
6070 if ((GET_MODE_SIZE (GET_MODE (last_reg))
6071 >= GET_MODE_SIZE (need_mode))
6072 && reg_reloaded_contents[i] == regno
6073 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
6074 && HARD_REGNO_MODE_OK (i, rld[r].mode)
6075 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i)
6076 /* Even if we can't use this register as a reload
6077 register, we might use it for reload_override_in,
6078 if copying it to the desired class is cheap
6080 || ((REGISTER_MOVE_COST (mode, last_class, rclass)
6081 < MEMORY_MOVE_COST (mode, rclass, 1))
6082 && (secondary_reload_class (1, rclass, mode,
6085 #ifdef SECONDARY_MEMORY_NEEDED
6086 && ! SECONDARY_MEMORY_NEEDED (last_class, rclass,
6091 && (rld[r].nregs == max_group_size
6092 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
6094 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
6095 rld[r].when_needed, rld[r].in,
6098 /* If a group is needed, verify that all the subsequent
6099 registers still have their values intact. */
6100 int nr = hard_regno_nregs[i][rld[r].mode];
6103 for (k = 1; k < nr; k++)
6104 if (reg_reloaded_contents[i + k] != regno
6105 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
6113 last_reg = (GET_MODE (last_reg) == mode
6114 ? last_reg : gen_rtx_REG (mode, i));
6117 for (k = 0; k < nr; k++)
6118 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6121 /* We found a register that contains the
6122 value we need. If this register is the
6123 same as an `earlyclobber' operand of the
6124 current insn, just mark it as a place to
6125 reload from since we can't use it as the
6126 reload register itself. */
6128 for (i1 = 0; i1 < n_earlyclobbers; i1++)
6129 if (reg_overlap_mentioned_for_reload_p
6130 (reg_last_reload_reg[regno],
6131 reload_earlyclobbers[i1]))
6134 if (i1 != n_earlyclobbers
6135 || ! (free_for_value_p (i, rld[r].mode,
6137 rld[r].when_needed, rld[r].in,
6139 /* Don't use it if we'd clobber a pseudo reg. */
6140 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
6142 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
6143 /* Don't clobber the frame pointer. */
6144 || (i == HARD_FRAME_POINTER_REGNUM
6145 && frame_pointer_needed
6147 /* Don't really use the inherited spill reg
6148 if we need it wider than we've got it. */
6149 || (GET_MODE_SIZE (rld[r].mode)
6150 > GET_MODE_SIZE (mode))
6153 /* If find_reloads chose reload_out as reload
6154 register, stay with it - that leaves the
6155 inherited register for subsequent reloads. */
6156 || (rld[r].out && rld[r].reg_rtx
6157 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
6159 if (! rld[r].optional)
6161 reload_override_in[r] = last_reg;
6162 reload_inheritance_insn[r]
6163 = reg_reloaded_insn[i];
6169 /* We can use this as a reload reg. */
6170 /* Mark the register as in use for this part of
6172 mark_reload_reg_in_use (i,
6176 rld[r].reg_rtx = last_reg;
6177 reload_inherited[r] = 1;
6178 reload_inheritance_insn[r]
6179 = reg_reloaded_insn[i];
6180 reload_spill_index[r] = i;
6181 for (k = 0; k < nr; k++)
6182 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6190 /* Here's another way to see if the value is already lying around. */
6193 && ! reload_inherited[r]
6195 && (CONSTANT_P (rld[r].in)
6196 || GET_CODE (rld[r].in) == PLUS
6197 || REG_P (rld[r].in)
6198 || MEM_P (rld[r].in))
6199 && (rld[r].nregs == max_group_size
6200 || ! reg_classes_intersect_p (rld[r].rclass, group_class)))
6201 search_equiv = rld[r].in;
6202 /* If this is an output reload from a simple move insn, look
6203 if an equivalence for the input is available. */
6204 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
6206 rtx set = single_set (insn);
6209 && rtx_equal_p (rld[r].out, SET_DEST (set))
6210 && CONSTANT_P (SET_SRC (set)))
6211 search_equiv = SET_SRC (set);
6217 = find_equiv_reg (search_equiv, insn, rld[r].rclass,
6218 -1, NULL, 0, rld[r].mode);
6224 regno = REGNO (equiv);
6227 /* This must be a SUBREG of a hard register.
6228 Make a new REG since this might be used in an
6229 address and not all machines support SUBREGs
6231 gcc_assert (GET_CODE (equiv) == SUBREG);
6232 regno = subreg_regno (equiv);
6233 equiv = gen_rtx_REG (rld[r].mode, regno);
6234 /* If we choose EQUIV as the reload register, but the
6235 loop below decides to cancel the inheritance, we'll
6236 end up reloading EQUIV in rld[r].mode, not the mode
6237 it had originally. That isn't safe when EQUIV isn't
6238 available as a spill register since its value might
6239 still be live at this point. */
6240 for (i = regno; i < regno + (int) rld[r].nregs; i++)
6241 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
6246 /* If we found a spill reg, reject it unless it is free
6247 and of the desired class. */
6251 int bad_for_class = 0;
6252 int max_regno = regno + rld[r].nregs;
6254 for (i = regno; i < max_regno; i++)
6256 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6258 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass],
6263 && ! free_for_value_p (regno, rld[r].mode,
6264 rld[r].opnum, rld[r].when_needed,
6265 rld[r].in, rld[r].out, r, 1))
6270 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6273 /* We found a register that contains the value we need.
6274 If this register is the same as an `earlyclobber' operand
6275 of the current insn, just mark it as a place to reload from
6276 since we can't use it as the reload register itself. */
6279 for (i = 0; i < n_earlyclobbers; i++)
6280 if (reg_overlap_mentioned_for_reload_p (equiv,
6281 reload_earlyclobbers[i]))
6283 if (! rld[r].optional)
6284 reload_override_in[r] = equiv;
6289 /* If the equiv register we have found is explicitly clobbered
6290 in the current insn, it depends on the reload type if we
6291 can use it, use it for reload_override_in, or not at all.
6292 In particular, we then can't use EQUIV for a
6293 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6297 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6298 switch (rld[r].when_needed)
6300 case RELOAD_FOR_OTHER_ADDRESS:
6301 case RELOAD_FOR_INPADDR_ADDRESS:
6302 case RELOAD_FOR_INPUT_ADDRESS:
6303 case RELOAD_FOR_OPADDR_ADDR:
6306 case RELOAD_FOR_INPUT:
6307 case RELOAD_FOR_OPERAND_ADDRESS:
6308 if (! rld[r].optional)
6309 reload_override_in[r] = equiv;
6315 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6316 switch (rld[r].when_needed)
6318 case RELOAD_FOR_OTHER_ADDRESS:
6319 case RELOAD_FOR_INPADDR_ADDRESS:
6320 case RELOAD_FOR_INPUT_ADDRESS:
6321 case RELOAD_FOR_OPADDR_ADDR:
6322 case RELOAD_FOR_OPERAND_ADDRESS:
6323 case RELOAD_FOR_INPUT:
6326 if (! rld[r].optional)
6327 reload_override_in[r] = equiv;
6335 /* If we found an equivalent reg, say no code need be generated
6336 to load it, and use it as our reload reg. */
6338 && (regno != HARD_FRAME_POINTER_REGNUM
6339 || !frame_pointer_needed))
6341 int nr = hard_regno_nregs[regno][rld[r].mode];
6343 rld[r].reg_rtx = equiv;
6344 reload_spill_index[r] = regno;
6345 reload_inherited[r] = 1;
6347 /* If reg_reloaded_valid is not set for this register,
6348 there might be a stale spill_reg_store lying around.
6349 We must clear it, since otherwise emit_reload_insns
6350 might delete the store. */
6351 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6352 spill_reg_store[regno] = NULL_RTX;
6353 /* If any of the hard registers in EQUIV are spill
6354 registers, mark them as in use for this insn. */
6355 for (k = 0; k < nr; k++)
6357 i = spill_reg_order[regno + k];
6360 mark_reload_reg_in_use (regno, rld[r].opnum,
6363 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6370 /* If we found a register to use already, or if this is an optional
6371 reload, we are done. */
6372 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6376 /* No longer needed for correct operation. Might or might
6377 not give better code on the average. Want to experiment? */
6379 /* See if there is a later reload that has a class different from our
6380 class that intersects our class or that requires less register
6381 than our reload. If so, we must allocate a register to this
6382 reload now, since that reload might inherit a previous reload
6383 and take the only available register in our class. Don't do this
6384 for optional reloads since they will force all previous reloads
6385 to be allocated. Also don't do this for reloads that have been
6388 for (i = j + 1; i < n_reloads; i++)
6390 int s = reload_order[i];
6392 if ((rld[s].in == 0 && rld[s].out == 0
6393 && ! rld[s].secondary_p)
6397 if ((rld[s].rclass != rld[r].rclass
6398 && reg_classes_intersect_p (rld[r].rclass,
6400 || rld[s].nregs < rld[r].nregs)
6407 allocate_reload_reg (chain, r, j == n_reloads - 1);
6411 /* Now allocate reload registers for anything non-optional that
6412 didn't get one yet. */
6413 for (j = 0; j < n_reloads; j++)
6415 int r = reload_order[j];
6417 /* Ignore reloads that got marked inoperative. */
6418 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6421 /* Skip reloads that already have a register allocated or are
6423 if (rld[r].reg_rtx != 0 || rld[r].optional)
6426 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6430 /* If that loop got all the way, we have won. */
6437 /* Loop around and try without any inheritance. */
6442 /* First undo everything done by the failed attempt
6443 to allocate with inheritance. */
6444 choose_reload_regs_init (chain, save_reload_reg_rtx);
6446 /* Some sanity tests to verify that the reloads found in the first
6447 pass are identical to the ones we have now. */
6448 gcc_assert (chain->n_reloads == n_reloads);
6450 for (i = 0; i < n_reloads; i++)
6452 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6454 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6455 for (j = 0; j < n_spills; j++)
6456 if (spill_regs[j] == chain->rld[i].regno)
6457 if (! set_reload_reg (j, i))
6458 failed_reload (chain->insn, i);
6462 /* If we thought we could inherit a reload, because it seemed that
6463 nothing else wanted the same reload register earlier in the insn,
6464 verify that assumption, now that all reloads have been assigned.
6465 Likewise for reloads where reload_override_in has been set. */
6467 /* If doing expensive optimizations, do one preliminary pass that doesn't
6468 cancel any inheritance, but removes reloads that have been needed only
6469 for reloads that we know can be inherited. */
6470 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6472 for (j = 0; j < n_reloads; j++)
6474 int r = reload_order[j];
6476 if (reload_inherited[r] && rld[r].reg_rtx)
6477 check_reg = rld[r].reg_rtx;
6478 else if (reload_override_in[r]
6479 && (REG_P (reload_override_in[r])
6480 || GET_CODE (reload_override_in[r]) == SUBREG))
6481 check_reg = reload_override_in[r];
6484 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6485 rld[r].opnum, rld[r].when_needed, rld[r].in,
6486 (reload_inherited[r]
6487 ? rld[r].out : const0_rtx),
6492 reload_inherited[r] = 0;
6493 reload_override_in[r] = 0;
6495 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6496 reload_override_in, then we do not need its related
6497 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6498 likewise for other reload types.
6499 We handle this by removing a reload when its only replacement
6500 is mentioned in reload_in of the reload we are going to inherit.
6501 A special case are auto_inc expressions; even if the input is
6502 inherited, we still need the address for the output. We can
6503 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6504 If we succeeded removing some reload and we are doing a preliminary
6505 pass just to remove such reloads, make another pass, since the
6506 removal of one reload might allow us to inherit another one. */
6508 && rld[r].out != rld[r].in
6509 && remove_address_replacements (rld[r].in) && pass)
6514 /* Now that reload_override_in is known valid,
6515 actually override reload_in. */
6516 for (j = 0; j < n_reloads; j++)
6517 if (reload_override_in[j])
6518 rld[j].in = reload_override_in[j];
6520 /* If this reload won't be done because it has been canceled or is
6521 optional and not inherited, clear reload_reg_rtx so other
6522 routines (such as subst_reloads) don't get confused. */
6523 for (j = 0; j < n_reloads; j++)
6524 if (rld[j].reg_rtx != 0
6525 && ((rld[j].optional && ! reload_inherited[j])
6526 || (rld[j].in == 0 && rld[j].out == 0
6527 && ! rld[j].secondary_p)))
6529 int regno = true_regnum (rld[j].reg_rtx);
6531 if (spill_reg_order[regno] >= 0)
6532 clear_reload_reg_in_use (regno, rld[j].opnum,
6533 rld[j].when_needed, rld[j].mode);
6535 reload_spill_index[j] = -1;
6538 /* Record which pseudos and which spill regs have output reloads. */
6539 for (j = 0; j < n_reloads; j++)
6541 int r = reload_order[j];
6543 i = reload_spill_index[r];
6545 /* I is nonneg if this reload uses a register.
6546 If rld[r].reg_rtx is 0, this is an optional reload
6547 that we opted to ignore. */
6548 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6549 && rld[r].reg_rtx != 0)
6551 int nregno = REGNO (rld[r].out_reg);
6554 if (nregno < FIRST_PSEUDO_REGISTER)
6555 nr = hard_regno_nregs[nregno][rld[r].mode];
6558 SET_REGNO_REG_SET (®_has_output_reload,
6563 nr = hard_regno_nregs[i][rld[r].mode];
6565 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6568 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6569 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6570 || rld[r].when_needed == RELOAD_FOR_INSN);
6575 /* Deallocate the reload register for reload R. This is called from
6576 remove_address_replacements. */
6579 deallocate_reload_reg (int r)
6583 if (! rld[r].reg_rtx)
6585 regno = true_regnum (rld[r].reg_rtx);
6587 if (spill_reg_order[regno] >= 0)
6588 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6590 reload_spill_index[r] = -1;
6593 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6594 reloads of the same item for fear that we might not have enough reload
6595 registers. However, normally they will get the same reload register
6596 and hence actually need not be loaded twice.
6598 Here we check for the most common case of this phenomenon: when we have
6599 a number of reloads for the same object, each of which were allocated
6600 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6601 reload, and is not modified in the insn itself. If we find such,
6602 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6603 This will not increase the number of spill registers needed and will
6604 prevent redundant code. */
6607 merge_assigned_reloads (rtx insn)
6611 /* Scan all the reloads looking for ones that only load values and
6612 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6613 assigned and not modified by INSN. */
6615 for (i = 0; i < n_reloads; i++)
6617 int conflicting_input = 0;
6618 int max_input_address_opnum = -1;
6619 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6621 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6622 || rld[i].out != 0 || rld[i].reg_rtx == 0
6623 || reg_set_p (rld[i].reg_rtx, insn))
6626 /* Look at all other reloads. Ensure that the only use of this
6627 reload_reg_rtx is in a reload that just loads the same value
6628 as we do. Note that any secondary reloads must be of the identical
6629 class since the values, modes, and result registers are the
6630 same, so we need not do anything with any secondary reloads. */
6632 for (j = 0; j < n_reloads; j++)
6634 if (i == j || rld[j].reg_rtx == 0
6635 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6639 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6640 && rld[j].opnum > max_input_address_opnum)
6641 max_input_address_opnum = rld[j].opnum;
6643 /* If the reload regs aren't exactly the same (e.g, different modes)
6644 or if the values are different, we can't merge this reload.
6645 But if it is an input reload, we might still merge
6646 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6648 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6649 || rld[j].out != 0 || rld[j].in == 0
6650 || ! rtx_equal_p (rld[i].in, rld[j].in))
6652 if (rld[j].when_needed != RELOAD_FOR_INPUT
6653 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6654 || rld[i].opnum > rld[j].opnum)
6655 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6657 conflicting_input = 1;
6658 if (min_conflicting_input_opnum > rld[j].opnum)
6659 min_conflicting_input_opnum = rld[j].opnum;
6663 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6664 we, in fact, found any matching reloads. */
6667 && max_input_address_opnum <= min_conflicting_input_opnum)
6669 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6671 for (j = 0; j < n_reloads; j++)
6672 if (i != j && rld[j].reg_rtx != 0
6673 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6674 && (! conflicting_input
6675 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6676 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6678 rld[i].when_needed = RELOAD_OTHER;
6680 reload_spill_index[j] = -1;
6681 transfer_replacements (i, j);
6684 /* If this is now RELOAD_OTHER, look for any reloads that
6685 load parts of this operand and set them to
6686 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6687 RELOAD_OTHER for outputs. Note that this test is
6688 equivalent to looking for reloads for this operand
6691 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6692 it may share registers with a RELOAD_FOR_INPUT, so we can
6693 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6694 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6696 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6697 instruction is assigned the same register as the earlier
6698 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6699 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6700 instruction to be deleted later on. */
6702 if (rld[i].when_needed == RELOAD_OTHER)
6703 for (j = 0; j < n_reloads; j++)
6705 && rld[j].when_needed != RELOAD_OTHER
6706 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6707 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6708 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6709 && (! conflicting_input
6710 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6711 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6712 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6718 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6719 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6720 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6722 /* Check to see if we accidentally converted two
6723 reloads that use the same reload register with
6724 different inputs to the same type. If so, the
6725 resulting code won't work. */
6727 for (k = 0; k < j; k++)
6728 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6729 || rld[k].when_needed != rld[j].when_needed
6730 || !rtx_equal_p (rld[k].reg_rtx,
6732 || rtx_equal_p (rld[k].in,
6739 /* These arrays are filled by emit_reload_insns and its subroutines. */
6740 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6741 static rtx other_input_address_reload_insns = 0;
6742 static rtx other_input_reload_insns = 0;
6743 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6744 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6745 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6746 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6747 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6748 static rtx operand_reload_insns = 0;
6749 static rtx other_operand_reload_insns = 0;
6750 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6752 /* Values to be put in spill_reg_store are put here first. */
6753 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6754 static HARD_REG_SET reg_reloaded_died;
6756 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6757 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6758 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6759 adjusted register, and return true. Otherwise, return false. */
6761 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6762 enum reg_class new_class,
6763 enum machine_mode new_mode)
6768 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6770 unsigned regno = REGNO (reg);
6772 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6774 if (GET_MODE (reg) != new_mode)
6776 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6778 if (hard_regno_nregs[regno][new_mode]
6779 > hard_regno_nregs[regno][GET_MODE (reg)])
6781 reg = reload_adjust_reg_for_mode (reg, new_mode);
6789 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6790 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6791 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6792 adjusted register, and return true. Otherwise, return false. */
6794 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6795 enum insn_code icode)
6798 enum reg_class new_class = scratch_reload_class (icode);
6799 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6801 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6802 new_class, new_mode);
6805 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6806 has the number J. OLD contains the value to be used as input. */
6809 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6812 rtx insn = chain->insn;
6814 rtx oldequiv_reg = 0;
6817 enum machine_mode mode;
6820 /* delete_output_reload is only invoked properly if old contains
6821 the original pseudo register. Since this is replaced with a
6822 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6823 find the pseudo in RELOAD_IN_REG. */
6824 if (reload_override_in[j]
6825 && REG_P (rl->in_reg))
6832 else if (REG_P (oldequiv))
6833 oldequiv_reg = oldequiv;
6834 else if (GET_CODE (oldequiv) == SUBREG)
6835 oldequiv_reg = SUBREG_REG (oldequiv);
6837 reloadreg = reload_reg_rtx_for_input[j];
6838 mode = GET_MODE (reloadreg);
6840 /* If we are reloading from a register that was recently stored in
6841 with an output-reload, see if we can prove there was
6842 actually no need to store the old value in it. */
6844 if (optimize && REG_P (oldequiv)
6845 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6846 && spill_reg_store[REGNO (oldequiv)]
6848 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6849 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6851 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6853 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from
6856 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6857 oldequiv = SUBREG_REG (oldequiv);
6858 if (GET_MODE (oldequiv) != VOIDmode
6859 && mode != GET_MODE (oldequiv))
6860 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6862 /* Switch to the right place to emit the reload insns. */
6863 switch (rl->when_needed)
6866 where = &other_input_reload_insns;
6868 case RELOAD_FOR_INPUT:
6869 where = &input_reload_insns[rl->opnum];
6871 case RELOAD_FOR_INPUT_ADDRESS:
6872 where = &input_address_reload_insns[rl->opnum];
6874 case RELOAD_FOR_INPADDR_ADDRESS:
6875 where = &inpaddr_address_reload_insns[rl->opnum];
6877 case RELOAD_FOR_OUTPUT_ADDRESS:
6878 where = &output_address_reload_insns[rl->opnum];
6880 case RELOAD_FOR_OUTADDR_ADDRESS:
6881 where = &outaddr_address_reload_insns[rl->opnum];
6883 case RELOAD_FOR_OPERAND_ADDRESS:
6884 where = &operand_reload_insns;
6886 case RELOAD_FOR_OPADDR_ADDR:
6887 where = &other_operand_reload_insns;
6889 case RELOAD_FOR_OTHER_ADDRESS:
6890 where = &other_input_address_reload_insns;
6896 push_to_sequence (*where);
6898 /* Auto-increment addresses must be reloaded in a special way. */
6899 if (rl->out && ! rl->out_reg)
6901 /* We are not going to bother supporting the case where a
6902 incremented register can't be copied directly from
6903 OLDEQUIV since this seems highly unlikely. */
6904 gcc_assert (rl->secondary_in_reload < 0);
6906 if (reload_inherited[j])
6907 oldequiv = reloadreg;
6909 old = XEXP (rl->in_reg, 0);
6911 if (optimize && REG_P (oldequiv)
6912 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6913 && spill_reg_store[REGNO (oldequiv)]
6915 && (dead_or_set_p (insn,
6916 spill_reg_stored_to[REGNO (oldequiv)])
6917 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6919 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg);
6921 /* Prevent normal processing of this reload. */
6923 /* Output a special code sequence for this case. */
6924 new_spill_reg_store[REGNO (reloadreg)]
6925 = inc_for_reload (reloadreg, oldequiv, rl->out,
6929 /* If we are reloading a pseudo-register that was set by the previous
6930 insn, see if we can get rid of that pseudo-register entirely
6931 by redirecting the previous insn into our reload register. */
6933 else if (optimize && REG_P (old)
6934 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6935 && dead_or_set_p (insn, old)
6936 /* This is unsafe if some other reload
6937 uses the same reg first. */
6938 && ! conflicts_with_override (reloadreg)
6939 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6940 rl->when_needed, old, rl->out, j, 0))
6942 rtx temp = PREV_INSN (insn);
6943 while (temp && NOTE_P (temp))
6944 temp = PREV_INSN (temp);
6946 && NONJUMP_INSN_P (temp)
6947 && GET_CODE (PATTERN (temp)) == SET
6948 && SET_DEST (PATTERN (temp)) == old
6949 /* Make sure we can access insn_operand_constraint. */
6950 && asm_noperands (PATTERN (temp)) < 0
6951 /* This is unsafe if operand occurs more than once in current
6952 insn. Perhaps some occurrences aren't reloaded. */
6953 && count_occurrences (PATTERN (insn), old, 0) == 1)
6955 rtx old = SET_DEST (PATTERN (temp));
6956 /* Store into the reload register instead of the pseudo. */
6957 SET_DEST (PATTERN (temp)) = reloadreg;
6959 /* Verify that resulting insn is valid. */
6960 extract_insn (temp);
6961 if (constrain_operands (1))
6963 /* If the previous insn is an output reload, the source is
6964 a reload register, and its spill_reg_store entry will
6965 contain the previous destination. This is now
6967 if (REG_P (SET_SRC (PATTERN (temp)))
6968 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6970 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6971 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6974 /* If these are the only uses of the pseudo reg,
6975 pretend for GDB it lives in the reload reg we used. */
6976 if (REG_N_DEATHS (REGNO (old)) == 1
6977 && REG_N_SETS (REGNO (old)) == 1)
6979 reg_renumber[REGNO (old)] = REGNO (reloadreg);
6980 if (ira_conflicts_p)
6981 /* Inform IRA about the change. */
6982 ira_mark_allocation_change (REGNO (old));
6983 alter_reg (REGNO (old), -1, false);
6989 SET_DEST (PATTERN (temp)) = old;
6994 /* We can't do that, so output an insn to load RELOADREG. */
6996 /* If we have a secondary reload, pick up the secondary register
6997 and icode, if any. If OLDEQUIV and OLD are different or
6998 if this is an in-out reload, recompute whether or not we
6999 still need a secondary register and what the icode should
7000 be. If we still need a secondary register and the class or
7001 icode is different, go back to reloading from OLD if using
7002 OLDEQUIV means that we got the wrong type of register. We
7003 cannot have different class or icode due to an in-out reload
7004 because we don't make such reloads when both the input and
7005 output need secondary reload registers. */
7007 if (! special && rl->secondary_in_reload >= 0)
7009 rtx second_reload_reg = 0;
7010 rtx third_reload_reg = 0;
7011 int secondary_reload = rl->secondary_in_reload;
7012 rtx real_oldequiv = oldequiv;
7015 enum insn_code icode;
7016 enum insn_code tertiary_icode = CODE_FOR_nothing;
7018 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
7019 and similarly for OLD.
7020 See comments in get_secondary_reload in reload.c. */
7021 /* If it is a pseudo that cannot be replaced with its
7022 equivalent MEM, we must fall back to reload_in, which
7023 will have all the necessary substitutions registered.
7024 Likewise for a pseudo that can't be replaced with its
7025 equivalent constant.
7027 Take extra care for subregs of such pseudos. Note that
7028 we cannot use reg_equiv_mem in this case because it is
7029 not in the right mode. */
7032 if (GET_CODE (tmp) == SUBREG)
7033 tmp = SUBREG_REG (tmp);
7035 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7036 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7037 || reg_equiv_constant[REGNO (tmp)] != 0))
7039 if (! reg_equiv_mem[REGNO (tmp)]
7040 || num_not_at_initial_offset
7041 || GET_CODE (oldequiv) == SUBREG)
7042 real_oldequiv = rl->in;
7044 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
7048 if (GET_CODE (tmp) == SUBREG)
7049 tmp = SUBREG_REG (tmp);
7051 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
7052 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
7053 || reg_equiv_constant[REGNO (tmp)] != 0))
7055 if (! reg_equiv_mem[REGNO (tmp)]
7056 || num_not_at_initial_offset
7057 || GET_CODE (old) == SUBREG)
7060 real_old = reg_equiv_mem[REGNO (tmp)];
7063 second_reload_reg = rld[secondary_reload].reg_rtx;
7064 if (rld[secondary_reload].secondary_in_reload >= 0)
7066 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
7068 third_reload_reg = rld[tertiary_reload].reg_rtx;
7069 tertiary_icode = rld[secondary_reload].secondary_in_icode;
7070 /* We'd have to add more code for quartary reloads. */
7071 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
7073 icode = rl->secondary_in_icode;
7075 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
7076 || (rl->in != 0 && rl->out != 0))
7078 secondary_reload_info sri, sri2;
7079 enum reg_class new_class, new_t_class;
7081 sri.icode = CODE_FOR_nothing;
7082 sri.prev_sri = NULL;
7083 new_class = targetm.secondary_reload (1, real_oldequiv, rl->rclass,
7086 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
7087 second_reload_reg = 0;
7088 else if (new_class == NO_REGS)
7090 if (reload_adjust_reg_for_icode (&second_reload_reg,
7092 (enum insn_code) sri.icode))
7094 icode = (enum insn_code) sri.icode;
7095 third_reload_reg = 0;
7100 real_oldequiv = real_old;
7103 else if (sri.icode != CODE_FOR_nothing)
7104 /* We currently lack a way to express this in reloads. */
7108 sri2.icode = CODE_FOR_nothing;
7109 sri2.prev_sri = &sri;
7110 new_t_class = targetm.secondary_reload (1, real_oldequiv,
7111 new_class, mode, &sri);
7112 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
7114 if (reload_adjust_reg_for_temp (&second_reload_reg,
7118 third_reload_reg = 0;
7119 tertiary_icode = (enum insn_code) sri2.icode;
7124 real_oldequiv = real_old;
7127 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
7129 rtx intermediate = second_reload_reg;
7131 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7133 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
7137 second_reload_reg = intermediate;
7138 tertiary_icode = (enum insn_code) sri2.icode;
7143 real_oldequiv = real_old;
7146 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
7148 rtx intermediate = second_reload_reg;
7150 if (reload_adjust_reg_for_temp (&intermediate, NULL,
7152 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
7155 second_reload_reg = intermediate;
7156 tertiary_icode = (enum insn_code) sri2.icode;
7161 real_oldequiv = real_old;
7166 /* This could be handled more intelligently too. */
7168 real_oldequiv = real_old;
7173 /* If we still need a secondary reload register, check
7174 to see if it is being used as a scratch or intermediate
7175 register and generate code appropriately. If we need
7176 a scratch register, use REAL_OLDEQUIV since the form of
7177 the insn may depend on the actual address if it is
7180 if (second_reload_reg)
7182 if (icode != CODE_FOR_nothing)
7184 /* We'd have to add extra code to handle this case. */
7185 gcc_assert (!third_reload_reg);
7187 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
7188 second_reload_reg));
7193 /* See if we need a scratch register to load the
7194 intermediate register (a tertiary reload). */
7195 if (tertiary_icode != CODE_FOR_nothing)
7197 emit_insn ((GEN_FCN (tertiary_icode)
7198 (second_reload_reg, real_oldequiv,
7199 third_reload_reg)));
7201 else if (third_reload_reg)
7203 gen_reload (third_reload_reg, real_oldequiv,
7206 gen_reload (second_reload_reg, third_reload_reg,
7211 gen_reload (second_reload_reg, real_oldequiv,
7215 oldequiv = second_reload_reg;
7220 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
7222 rtx real_oldequiv = oldequiv;
7224 if ((REG_P (oldequiv)
7225 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
7226 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
7227 || reg_equiv_constant[REGNO (oldequiv)] != 0))
7228 || (GET_CODE (oldequiv) == SUBREG
7229 && REG_P (SUBREG_REG (oldequiv))
7230 && (REGNO (SUBREG_REG (oldequiv))
7231 >= FIRST_PSEUDO_REGISTER)
7232 && ((reg_equiv_memory_loc
7233 [REGNO (SUBREG_REG (oldequiv))] != 0)
7234 || (reg_equiv_constant
7235 [REGNO (SUBREG_REG (oldequiv))] != 0)))
7236 || (CONSTANT_P (oldequiv)
7237 && (PREFERRED_RELOAD_CLASS (oldequiv,
7238 REGNO_REG_CLASS (REGNO (reloadreg)))
7240 real_oldequiv = rl->in;
7241 gen_reload (reloadreg, real_oldequiv, rl->opnum,
7245 if (flag_non_call_exceptions)
7246 copy_eh_notes (insn, get_insns ());
7248 /* End this sequence. */
7249 *where = get_insns ();
7252 /* Update reload_override_in so that delete_address_reloads_1
7253 can see the actual register usage. */
7255 reload_override_in[j] = oldequiv;
7258 /* Generate insns to for the output reload RL, which is for the insn described
7259 by CHAIN and has the number J. */
7261 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7265 rtx insn = chain->insn;
7268 enum machine_mode mode;
7272 if (rl->when_needed == RELOAD_OTHER)
7275 push_to_sequence (output_reload_insns[rl->opnum]);
7277 rl_reg_rtx = reload_reg_rtx_for_output[j];
7278 mode = GET_MODE (rl_reg_rtx);
7280 reloadreg = rl_reg_rtx;
7282 /* If we need two reload regs, set RELOADREG to the intermediate
7283 one, since it will be stored into OLD. We might need a secondary
7284 register only for an input reload, so check again here. */
7286 if (rl->secondary_out_reload >= 0)
7289 int secondary_reload = rl->secondary_out_reload;
7290 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7292 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7293 && reg_equiv_mem[REGNO (old)] != 0)
7294 real_old = reg_equiv_mem[REGNO (old)];
7296 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS)
7298 rtx second_reloadreg = reloadreg;
7299 reloadreg = rld[secondary_reload].reg_rtx;
7301 /* See if RELOADREG is to be used as a scratch register
7302 or as an intermediate register. */
7303 if (rl->secondary_out_icode != CODE_FOR_nothing)
7305 /* We'd have to add extra code to handle this case. */
7306 gcc_assert (tertiary_reload < 0);
7308 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7309 (real_old, second_reloadreg, reloadreg)));
7314 /* See if we need both a scratch and intermediate reload
7317 enum insn_code tertiary_icode
7318 = rld[secondary_reload].secondary_out_icode;
7320 /* We'd have to add more code for quartary reloads. */
7321 gcc_assert (tertiary_reload < 0
7322 || rld[tertiary_reload].secondary_out_reload < 0);
7324 if (GET_MODE (reloadreg) != mode)
7325 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7327 if (tertiary_icode != CODE_FOR_nothing)
7329 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7332 /* Copy primary reload reg to secondary reload reg.
7333 (Note that these have been swapped above, then
7334 secondary reload reg to OLD using our insn.) */
7336 /* If REAL_OLD is a paradoxical SUBREG, remove it
7337 and try to put the opposite SUBREG on
7339 if (GET_CODE (real_old) == SUBREG
7340 && (GET_MODE_SIZE (GET_MODE (real_old))
7341 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7342 && 0 != (tem = gen_lowpart_common
7343 (GET_MODE (SUBREG_REG (real_old)),
7345 real_old = SUBREG_REG (real_old), reloadreg = tem;
7347 gen_reload (reloadreg, second_reloadreg,
7348 rl->opnum, rl->when_needed);
7349 emit_insn ((GEN_FCN (tertiary_icode)
7350 (real_old, reloadreg, third_reloadreg)));
7356 /* Copy between the reload regs here and then to
7359 gen_reload (reloadreg, second_reloadreg,
7360 rl->opnum, rl->when_needed);
7361 if (tertiary_reload >= 0)
7363 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7365 gen_reload (third_reloadreg, reloadreg,
7366 rl->opnum, rl->when_needed);
7367 reloadreg = third_reloadreg;
7374 /* Output the last reload insn. */
7379 /* Don't output the last reload if OLD is not the dest of
7380 INSN and is in the src and is clobbered by INSN. */
7381 if (! flag_expensive_optimizations
7383 || !(set = single_set (insn))
7384 || rtx_equal_p (old, SET_DEST (set))
7385 || !reg_mentioned_p (old, SET_SRC (set))
7386 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7387 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7388 gen_reload (old, reloadreg, rl->opnum,
7392 /* Look at all insns we emitted, just to be safe. */
7393 for (p = get_insns (); p; p = NEXT_INSN (p))
7396 rtx pat = PATTERN (p);
7398 /* If this output reload doesn't come from a spill reg,
7399 clear any memory of reloaded copies of the pseudo reg.
7400 If this output reload comes from a spill reg,
7401 reg_has_output_reload will make this do nothing. */
7402 note_stores (pat, forget_old_reloads_1, NULL);
7404 if (reg_mentioned_p (rl_reg_rtx, pat))
7406 rtx set = single_set (insn);
7407 if (reload_spill_index[j] < 0
7409 && SET_SRC (set) == rl_reg_rtx)
7411 int src = REGNO (SET_SRC (set));
7413 reload_spill_index[j] = src;
7414 SET_HARD_REG_BIT (reg_is_output_reload, src);
7415 if (find_regno_note (insn, REG_DEAD, src))
7416 SET_HARD_REG_BIT (reg_reloaded_died, src);
7418 if (HARD_REGISTER_P (rl_reg_rtx))
7420 int s = rl->secondary_out_reload;
7421 set = single_set (p);
7422 /* If this reload copies only to the secondary reload
7423 register, the secondary reload does the actual
7425 if (s >= 0 && set == NULL_RTX)
7426 /* We can't tell what function the secondary reload
7427 has and where the actual store to the pseudo is
7428 made; leave new_spill_reg_store alone. */
7431 && SET_SRC (set) == rl_reg_rtx
7432 && SET_DEST (set) == rld[s].reg_rtx)
7434 /* Usually the next instruction will be the
7435 secondary reload insn; if we can confirm
7436 that it is, setting new_spill_reg_store to
7437 that insn will allow an extra optimization. */
7438 rtx s_reg = rld[s].reg_rtx;
7439 rtx next = NEXT_INSN (p);
7440 rld[s].out = rl->out;
7441 rld[s].out_reg = rl->out_reg;
7442 set = single_set (next);
7443 if (set && SET_SRC (set) == s_reg
7444 && ! new_spill_reg_store[REGNO (s_reg)])
7446 SET_HARD_REG_BIT (reg_is_output_reload,
7448 new_spill_reg_store[REGNO (s_reg)] = next;
7452 new_spill_reg_store[REGNO (rl_reg_rtx)] = p;
7457 if (rl->when_needed == RELOAD_OTHER)
7459 emit_insn (other_output_reload_insns[rl->opnum]);
7460 other_output_reload_insns[rl->opnum] = get_insns ();
7463 output_reload_insns[rl->opnum] = get_insns ();
7465 if (flag_non_call_exceptions)
7466 copy_eh_notes (insn, get_insns ());
7471 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7472 and has the number J. */
7474 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7476 rtx insn = chain->insn;
7477 rtx old = (rl->in && MEM_P (rl->in)
7478 ? rl->in_reg : rl->in);
7479 rtx reg_rtx = rl->reg_rtx;
7483 enum machine_mode mode;
7485 /* Determine the mode to reload in.
7486 This is very tricky because we have three to choose from.
7487 There is the mode the insn operand wants (rl->inmode).
7488 There is the mode of the reload register RELOADREG.
7489 There is the intrinsic mode of the operand, which we could find
7490 by stripping some SUBREGs.
7491 It turns out that RELOADREG's mode is irrelevant:
7492 we can change that arbitrarily.
7494 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
7495 then the reload reg may not support QImode moves, so use SImode.
7496 If foo is in memory due to spilling a pseudo reg, this is safe,
7497 because the QImode value is in the least significant part of a
7498 slot big enough for a SImode. If foo is some other sort of
7499 memory reference, then it is impossible to reload this case,
7500 so previous passes had better make sure this never happens.
7502 Then consider a one-word union which has SImode and one of its
7503 members is a float, being fetched as (SUBREG:SF union:SI).
7504 We must fetch that as SFmode because we could be loading into
7505 a float-only register. In this case OLD's mode is correct.
7507 Consider an immediate integer: it has VOIDmode. Here we need
7508 to get a mode from something else.
7510 In some cases, there is a fourth mode, the operand's
7511 containing mode. If the insn specifies a containing mode for
7512 this operand, it overrides all others.
7514 I am not sure whether the algorithm here is always right,
7515 but it does the right things in those cases. */
7517 mode = GET_MODE (old);
7518 if (mode == VOIDmode)
7521 /* We cannot use gen_lowpart_common since it can do the wrong thing
7522 when REG_RTX has a multi-word mode. Note that REG_RTX must
7523 always be a REG here. */
7524 if (GET_MODE (reg_rtx) != mode)
7525 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7527 reload_reg_rtx_for_input[j] = reg_rtx;
7530 /* AUTO_INC reloads need to be handled even if inherited. We got an
7531 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7532 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7533 && ! rtx_equal_p (reg_rtx, old)
7535 emit_input_reload_insns (chain, rld + j, old, j);
7537 /* When inheriting a wider reload, we have a MEM in rl->in,
7538 e.g. inheriting a SImode output reload for
7539 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7540 if (optimize && reload_inherited[j] && rl->in
7542 && MEM_P (rl->in_reg)
7543 && reload_spill_index[j] >= 0
7544 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7545 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7547 /* If we are reloading a register that was recently stored in with an
7548 output-reload, see if we can prove there was
7549 actually no need to store the old value in it. */
7552 && (reload_inherited[j] || reload_override_in[j])
7555 && spill_reg_store[REGNO (reg_rtx)] != 0
7557 /* There doesn't seem to be any reason to restrict this to pseudos
7558 and doing so loses in the case where we are copying from a
7559 register of the wrong class. */
7560 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)])
7562 /* The insn might have already some references to stackslots
7563 replaced by MEMs, while reload_out_reg still names the
7565 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)])
7566 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg)))
7567 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx);
7570 /* Do output reloading for reload RL, which is for the insn described by
7571 CHAIN and has the number J.
7572 ??? At some point we need to support handling output reloads of
7573 JUMP_INSNs or insns that set cc0. */
7575 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7578 rtx insn = chain->insn;
7579 /* If this is an output reload that stores something that is
7580 not loaded in this same reload, see if we can eliminate a previous
7582 rtx pseudo = rl->out_reg;
7583 rtx reg_rtx = rl->reg_rtx;
7585 if (rl->out && reg_rtx)
7587 enum machine_mode mode;
7589 /* Determine the mode to reload in.
7590 See comments above (for input reloading). */
7591 mode = GET_MODE (rl->out);
7592 if (mode == VOIDmode)
7594 /* VOIDmode should never happen for an output. */
7595 if (asm_noperands (PATTERN (insn)) < 0)
7596 /* It's the compiler's fault. */
7597 fatal_insn ("VOIDmode on an output", insn);
7598 error_for_asm (insn, "output operand is constant in %<asm%>");
7599 /* Prevent crash--use something we know is valid. */
7601 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx));
7603 if (GET_MODE (reg_rtx) != mode)
7604 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode);
7606 reload_reg_rtx_for_output[j] = reg_rtx;
7611 && ! rtx_equal_p (rl->in_reg, pseudo)
7612 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7613 && reg_last_reload_reg[REGNO (pseudo)])
7615 int pseudo_no = REGNO (pseudo);
7616 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7618 /* We don't need to test full validity of last_regno for
7619 inherit here; we only want to know if the store actually
7620 matches the pseudo. */
7621 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7622 && reg_reloaded_contents[last_regno] == pseudo_no
7623 && spill_reg_store[last_regno]
7624 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7625 delete_output_reload (insn, j, last_regno, reg_rtx);
7631 || rtx_equal_p (old, reg_rtx))
7634 /* An output operand that dies right away does need a reload,
7635 but need not be copied from it. Show the new location in the
7637 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7638 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7640 XEXP (note, 0) = reg_rtx;
7643 /* Likewise for a SUBREG of an operand that dies. */
7644 else if (GET_CODE (old) == SUBREG
7645 && REG_P (SUBREG_REG (old))
7646 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7649 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx);
7652 else if (GET_CODE (old) == SCRATCH)
7653 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7654 but we don't want to make an output reload. */
7657 /* If is a JUMP_INSN, we can't support output reloads yet. */
7658 gcc_assert (NONJUMP_INSN_P (insn));
7660 emit_output_reload_insns (chain, rld + j, j);
7663 /* A reload copies values of MODE from register SRC to register DEST.
7664 Return true if it can be treated for inheritance purposes like a
7665 group of reloads, each one reloading a single hard register. The
7666 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST)
7667 occupy the same number of hard registers. */
7670 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED,
7671 int src ATTRIBUTE_UNUSED,
7672 enum machine_mode mode ATTRIBUTE_UNUSED)
7674 #ifdef CANNOT_CHANGE_MODE_CLASS
7675 return (!REG_CANNOT_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest])
7676 && !REG_CANNOT_CHANGE_MODE_P (src, mode, reg_raw_mode[src]));
7682 /* Output insns to reload values in and out of the chosen reload regs. */
7685 emit_reload_insns (struct insn_chain *chain)
7687 rtx insn = chain->insn;
7691 CLEAR_HARD_REG_SET (reg_reloaded_died);
7693 for (j = 0; j < reload_n_operands; j++)
7694 input_reload_insns[j] = input_address_reload_insns[j]
7695 = inpaddr_address_reload_insns[j]
7696 = output_reload_insns[j] = output_address_reload_insns[j]
7697 = outaddr_address_reload_insns[j]
7698 = other_output_reload_insns[j] = 0;
7699 other_input_address_reload_insns = 0;
7700 other_input_reload_insns = 0;
7701 operand_reload_insns = 0;
7702 other_operand_reload_insns = 0;
7704 /* Dump reloads into the dump file. */
7707 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7708 debug_reload_to_stream (dump_file);
7711 /* Now output the instructions to copy the data into and out of the
7712 reload registers. Do these in the order that the reloads were reported,
7713 since reloads of base and index registers precede reloads of operands
7714 and the operands may need the base and index registers reloaded. */
7716 for (j = 0; j < n_reloads; j++)
7718 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx))
7722 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++)
7723 new_spill_reg_store[i] = 0;
7726 do_input_reload (chain, rld + j, j);
7727 do_output_reload (chain, rld + j, j);
7730 /* Now write all the insns we made for reloads in the order expected by
7731 the allocation functions. Prior to the insn being reloaded, we write
7732 the following reloads:
7734 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7736 RELOAD_OTHER reloads.
7738 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7739 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7740 RELOAD_FOR_INPUT reload for the operand.
7742 RELOAD_FOR_OPADDR_ADDRS reloads.
7744 RELOAD_FOR_OPERAND_ADDRESS reloads.
7746 After the insn being reloaded, we write the following:
7748 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7749 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7750 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7751 reloads for the operand. The RELOAD_OTHER output reloads are
7752 output in descending order by reload number. */
7754 emit_insn_before (other_input_address_reload_insns, insn);
7755 emit_insn_before (other_input_reload_insns, insn);
7757 for (j = 0; j < reload_n_operands; j++)
7759 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7760 emit_insn_before (input_address_reload_insns[j], insn);
7761 emit_insn_before (input_reload_insns[j], insn);
7764 emit_insn_before (other_operand_reload_insns, insn);
7765 emit_insn_before (operand_reload_insns, insn);
7767 for (j = 0; j < reload_n_operands; j++)
7769 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7770 x = emit_insn_after (output_address_reload_insns[j], x);
7771 x = emit_insn_after (output_reload_insns[j], x);
7772 emit_insn_after (other_output_reload_insns[j], x);
7775 /* For all the spill regs newly reloaded in this instruction,
7776 record what they were reloaded from, so subsequent instructions
7777 can inherit the reloads.
7779 Update spill_reg_store for the reloads of this insn.
7780 Copy the elements that were updated in the loop above. */
7782 for (j = 0; j < n_reloads; j++)
7784 int r = reload_order[j];
7785 int i = reload_spill_index[r];
7787 /* If this is a non-inherited input reload from a pseudo, we must
7788 clear any memory of a previous store to the same pseudo. Only do
7789 something if there will not be an output reload for the pseudo
7791 if (rld[r].in_reg != 0
7792 && ! (reload_inherited[r] || reload_override_in[r]))
7794 rtx reg = rld[r].in_reg;
7796 if (GET_CODE (reg) == SUBREG)
7797 reg = SUBREG_REG (reg);
7800 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7801 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7803 int nregno = REGNO (reg);
7805 if (reg_last_reload_reg[nregno])
7807 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7809 if (reg_reloaded_contents[last_regno] == nregno)
7810 spill_reg_store[last_regno] = 0;
7815 /* I is nonneg if this reload used a register.
7816 If rld[r].reg_rtx is 0, this is an optional reload
7817 that we opted to ignore. */
7819 if (i >= 0 && rld[r].reg_rtx != 0)
7821 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7824 /* For a multi register reload, we need to check if all or part
7825 of the value lives to the end. */
7826 for (k = 0; k < nr; k++)
7827 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7828 rld[r].when_needed))
7829 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7831 /* Maybe the spill reg contains a copy of reload_out. */
7833 && (REG_P (rld[r].out)
7837 || REG_P (rld[r].out_reg)))
7840 enum machine_mode mode;
7843 reg = reload_reg_rtx_for_output[r];
7844 mode = GET_MODE (reg);
7845 regno = REGNO (reg);
7846 nregs = hard_regno_nregs[regno][mode];
7847 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7848 rld[r].when_needed))
7850 rtx out = (REG_P (rld[r].out)
7854 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7855 int out_regno = REGNO (out);
7856 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1
7857 : hard_regno_nregs[out_regno][mode]);
7860 spill_reg_store[regno] = new_spill_reg_store[regno];
7861 spill_reg_stored_to[regno] = out;
7862 reg_last_reload_reg[out_regno] = reg;
7864 piecemeal = (HARD_REGISTER_NUM_P (out_regno)
7865 && nregs == out_nregs
7866 && inherit_piecemeal_p (out_regno, regno, mode));
7868 /* If OUT_REGNO is a hard register, it may occupy more than
7869 one register. If it does, say what is in the
7870 rest of the registers assuming that both registers
7871 agree on how many words the object takes. If not,
7872 invalidate the subsequent registers. */
7874 if (HARD_REGISTER_NUM_P (out_regno))
7875 for (k = 1; k < out_nregs; k++)
7876 reg_last_reload_reg[out_regno + k]
7877 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7879 /* Now do the inverse operation. */
7880 for (k = 0; k < nregs; k++)
7882 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7883 reg_reloaded_contents[regno + k]
7884 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal
7887 reg_reloaded_insn[regno + k] = insn;
7888 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7889 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7890 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7893 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7898 /* Maybe the spill reg contains a copy of reload_in. Only do
7899 something if there will not be an output reload for
7900 the register being reloaded. */
7901 else if (rld[r].out_reg == 0
7903 && ((REG_P (rld[r].in)
7904 && !HARD_REGISTER_P (rld[r].in)
7905 && !REGNO_REG_SET_P (®_has_output_reload,
7907 || (REG_P (rld[r].in_reg)
7908 && !REGNO_REG_SET_P (®_has_output_reload,
7909 REGNO (rld[r].in_reg))))
7910 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn)))
7913 enum machine_mode mode;
7916 reg = reload_reg_rtx_for_input[r];
7917 mode = GET_MODE (reg);
7918 regno = REGNO (reg);
7919 nregs = hard_regno_nregs[regno][mode];
7920 if (reload_regs_reach_end_p (regno, nregs, rld[r].opnum,
7921 rld[r].when_needed))
7928 if (REG_P (rld[r].in)
7929 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7931 else if (REG_P (rld[r].in_reg))
7934 in = XEXP (rld[r].in_reg, 0);
7935 in_regno = REGNO (in);
7937 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1
7938 : hard_regno_nregs[in_regno][mode]);
7940 reg_last_reload_reg[in_regno] = reg;
7942 piecemeal = (HARD_REGISTER_NUM_P (in_regno)
7943 && nregs == in_nregs
7944 && inherit_piecemeal_p (regno, in_regno, mode));
7946 if (HARD_REGISTER_NUM_P (in_regno))
7947 for (k = 1; k < in_nregs; k++)
7948 reg_last_reload_reg[in_regno + k]
7949 = (piecemeal ? regno_reg_rtx[regno + k] : 0);
7951 /* Unless we inherited this reload, show we haven't
7952 recently done a store.
7953 Previous stores of inherited auto_inc expressions
7954 also have to be discarded. */
7955 if (! reload_inherited[r]
7956 || (rld[r].out && ! rld[r].out_reg))
7957 spill_reg_store[regno] = 0;
7959 for (k = 0; k < nregs; k++)
7961 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k);
7962 reg_reloaded_contents[regno + k]
7963 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal
7966 reg_reloaded_insn[regno + k] = insn;
7967 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k);
7968 if (HARD_REGNO_CALL_PART_CLOBBERED (regno + k, mode))
7969 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7972 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7979 /* The following if-statement was #if 0'd in 1.34 (or before...).
7980 It's reenabled in 1.35 because supposedly nothing else
7981 deals with this problem. */
7983 /* If a register gets output-reloaded from a non-spill register,
7984 that invalidates any previous reloaded copy of it.
7985 But forget_old_reloads_1 won't get to see it, because
7986 it thinks only about the original insn. So invalidate it here.
7987 Also do the same thing for RELOAD_OTHER constraints where the
7988 output is discarded. */
7990 && ((rld[r].out != 0
7991 && (REG_P (rld[r].out)
7992 || (MEM_P (rld[r].out)
7993 && REG_P (rld[r].out_reg))))
7994 || (rld[r].out == 0 && rld[r].out_reg
7995 && REG_P (rld[r].out_reg))))
7997 rtx out = ((rld[r].out && REG_P (rld[r].out))
7998 ? rld[r].out : rld[r].out_reg);
7999 int out_regno = REGNO (out);
8000 enum machine_mode mode = GET_MODE (out);
8002 /* REG_RTX is now set or clobbered by the main instruction.
8003 As the comment above explains, forget_old_reloads_1 only
8004 sees the original instruction, and there is no guarantee
8005 that the original instruction also clobbered REG_RTX.
8006 For example, if find_reloads sees that the input side of
8007 a matched operand pair dies in this instruction, it may
8008 use the input register as the reload register.
8010 Calling forget_old_reloads_1 is a waste of effort if
8011 REG_RTX is also the output register.
8013 If we know that REG_RTX holds the value of a pseudo
8014 register, the code after the call will record that fact. */
8015 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
8016 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
8018 if (!HARD_REGISTER_NUM_P (out_regno))
8020 rtx src_reg, store_insn = NULL_RTX;
8022 reg_last_reload_reg[out_regno] = 0;
8024 /* If we can find a hard register that is stored, record
8025 the storing insn so that we may delete this insn with
8026 delete_output_reload. */
8027 src_reg = reload_reg_rtx_for_output[r];
8029 /* If this is an optional reload, try to find the source reg
8030 from an input reload. */
8033 rtx set = single_set (insn);
8034 if (set && SET_DEST (set) == rld[r].out)
8038 src_reg = SET_SRC (set);
8040 for (k = 0; k < n_reloads; k++)
8042 if (rld[k].in == src_reg)
8044 src_reg = reload_reg_rtx_for_input[k];
8051 store_insn = new_spill_reg_store[REGNO (src_reg)];
8052 if (src_reg && REG_P (src_reg)
8053 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
8055 int src_regno, src_nregs, k;
8058 gcc_assert (GET_MODE (src_reg) == mode);
8059 src_regno = REGNO (src_reg);
8060 src_nregs = hard_regno_nregs[src_regno][mode];
8061 /* The place where to find a death note varies with
8062 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
8063 necessarily checked exactly in the code that moves
8064 notes, so just check both locations. */
8065 note = find_regno_note (insn, REG_DEAD, src_regno);
8066 if (! note && store_insn)
8067 note = find_regno_note (store_insn, REG_DEAD, src_regno);
8068 for (k = 0; k < src_nregs; k++)
8070 spill_reg_store[src_regno + k] = store_insn;
8071 spill_reg_stored_to[src_regno + k] = out;
8072 reg_reloaded_contents[src_regno + k] = out_regno;
8073 reg_reloaded_insn[src_regno + k] = store_insn;
8074 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k);
8075 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k);
8076 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + k,
8078 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8081 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
8083 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k);
8085 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
8087 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
8089 reg_last_reload_reg[out_regno] = src_reg;
8090 /* We have to set reg_has_output_reload here, or else
8091 forget_old_reloads_1 will clear reg_last_reload_reg
8093 SET_REGNO_REG_SET (®_has_output_reload,
8099 int k, out_nregs = hard_regno_nregs[out_regno][mode];
8101 for (k = 0; k < out_nregs; k++)
8102 reg_last_reload_reg[out_regno + k] = 0;
8106 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
8109 /* Go through the motions to emit INSN and test if it is strictly valid.
8110 Return the emitted insn if valid, else return NULL. */
8113 emit_insn_if_valid_for_reload (rtx insn)
8115 rtx last = get_last_insn ();
8118 insn = emit_insn (insn);
8119 code = recog_memoized (insn);
8123 extract_insn (insn);
8124 /* We want constrain operands to treat this insn strictly in its
8125 validity determination, i.e., the way it would after reload has
8127 if (constrain_operands (1))
8131 delete_insns_since (last);
8135 /* Emit code to perform a reload from IN (which may be a reload register) to
8136 OUT (which may also be a reload register). IN or OUT is from operand
8137 OPNUM with reload type TYPE.
8139 Returns first insn emitted. */
8142 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
8144 rtx last = get_last_insn ();
8147 /* If IN is a paradoxical SUBREG, remove it and try to put the
8148 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
8149 if (GET_CODE (in) == SUBREG
8150 && (GET_MODE_SIZE (GET_MODE (in))
8151 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
8152 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
8153 in = SUBREG_REG (in), out = tem;
8154 else if (GET_CODE (out) == SUBREG
8155 && (GET_MODE_SIZE (GET_MODE (out))
8156 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
8157 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
8158 out = SUBREG_REG (out), in = tem;
8160 /* How to do this reload can get quite tricky. Normally, we are being
8161 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
8162 register that didn't get a hard register. In that case we can just
8163 call emit_move_insn.
8165 We can also be asked to reload a PLUS that adds a register or a MEM to
8166 another register, constant or MEM. This can occur during frame pointer
8167 elimination and while reloading addresses. This case is handled by
8168 trying to emit a single insn to perform the add. If it is not valid,
8169 we use a two insn sequence.
8171 Or we can be asked to reload an unary operand that was a fragment of
8172 an addressing mode, into a register. If it isn't recognized as-is,
8173 we try making the unop operand and the reload-register the same:
8174 (set reg:X (unop:X expr:Y))
8175 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
8177 Finally, we could be called to handle an 'o' constraint by putting
8178 an address into a register. In that case, we first try to do this
8179 with a named pattern of "reload_load_address". If no such pattern
8180 exists, we just emit a SET insn and hope for the best (it will normally
8181 be valid on machines that use 'o').
8183 This entire process is made complex because reload will never
8184 process the insns we generate here and so we must ensure that
8185 they will fit their constraints and also by the fact that parts of
8186 IN might be being reloaded separately and replaced with spill registers.
8187 Because of this, we are, in some sense, just guessing the right approach
8188 here. The one listed above seems to work.
8190 ??? At some point, this whole thing needs to be rethought. */
8192 if (GET_CODE (in) == PLUS
8193 && (REG_P (XEXP (in, 0))
8194 || GET_CODE (XEXP (in, 0)) == SUBREG
8195 || MEM_P (XEXP (in, 0)))
8196 && (REG_P (XEXP (in, 1))
8197 || GET_CODE (XEXP (in, 1)) == SUBREG
8198 || CONSTANT_P (XEXP (in, 1))
8199 || MEM_P (XEXP (in, 1))))
8201 /* We need to compute the sum of a register or a MEM and another
8202 register, constant, or MEM, and put it into the reload
8203 register. The best possible way of doing this is if the machine
8204 has a three-operand ADD insn that accepts the required operands.
8206 The simplest approach is to try to generate such an insn and see if it
8207 is recognized and matches its constraints. If so, it can be used.
8209 It might be better not to actually emit the insn unless it is valid,
8210 but we need to pass the insn as an operand to `recog' and
8211 `extract_insn' and it is simpler to emit and then delete the insn if
8212 not valid than to dummy things up. */
8214 rtx op0, op1, tem, insn;
8217 op0 = find_replacement (&XEXP (in, 0));
8218 op1 = find_replacement (&XEXP (in, 1));
8220 /* Since constraint checking is strict, commutativity won't be
8221 checked, so we need to do that here to avoid spurious failure
8222 if the add instruction is two-address and the second operand
8223 of the add is the same as the reload reg, which is frequently
8224 the case. If the insn would be A = B + A, rearrange it so
8225 it will be A = A + B as constrain_operands expects. */
8227 if (REG_P (XEXP (in, 1))
8228 && REGNO (out) == REGNO (XEXP (in, 1)))
8229 tem = op0, op0 = op1, op1 = tem;
8231 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
8232 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
8234 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8238 /* If that failed, we must use a conservative two-insn sequence.
8240 Use a move to copy one operand into the reload register. Prefer
8241 to reload a constant, MEM or pseudo since the move patterns can
8242 handle an arbitrary operand. If OP1 is not a constant, MEM or
8243 pseudo and OP1 is not a valid operand for an add instruction, then
8246 After reloading one of the operands into the reload register, add
8247 the reload register to the output register.
8249 If there is another way to do this for a specific machine, a
8250 DEFINE_PEEPHOLE should be specified that recognizes the sequence
8253 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
8255 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
8257 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
8258 || (code != CODE_FOR_nothing
8259 && ! ((*insn_data[code].operand[2].predicate)
8260 (op1, insn_data[code].operand[2].mode))))
8261 tem = op0, op0 = op1, op1 = tem;
8263 gen_reload (out, op0, opnum, type);
8265 /* If OP0 and OP1 are the same, we can use OUT for OP1.
8266 This fixes a problem on the 32K where the stack pointer cannot
8267 be used as an operand of an add insn. */
8269 if (rtx_equal_p (op0, op1))
8272 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
8275 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
8276 set_unique_reg_note (insn, REG_EQUIV, in);
8280 /* If that failed, copy the address register to the reload register.
8281 Then add the constant to the reload register. */
8283 gcc_assert (!reg_overlap_mentioned_p (out, op0));
8284 gen_reload (out, op1, opnum, type);
8285 insn = emit_insn (gen_add2_insn (out, op0));
8286 set_unique_reg_note (insn, REG_EQUIV, in);
8289 #ifdef SECONDARY_MEMORY_NEEDED
8290 /* If we need a memory location to do the move, do it that way. */
8291 else if ((REG_P (in)
8292 || (GET_CODE (in) == SUBREG && REG_P (SUBREG_REG (in))))
8293 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
8295 || (GET_CODE (out) == SUBREG && REG_P (SUBREG_REG (out))))
8296 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
8297 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
8298 REGNO_REG_CLASS (reg_or_subregno (out)),
8301 /* Get the memory to use and rewrite both registers to its mode. */
8302 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
8304 if (GET_MODE (loc) != GET_MODE (out))
8305 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
8307 if (GET_MODE (loc) != GET_MODE (in))
8308 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8310 gen_reload (loc, in, opnum, type);
8311 gen_reload (out, loc, opnum, type);
8314 else if (REG_P (out) && UNARY_P (in))
8321 op1 = find_replacement (&XEXP (in, 0));
8322 if (op1 != XEXP (in, 0))
8323 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8325 /* First, try a plain SET. */
8326 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8330 /* If that failed, move the inner operand to the reload
8331 register, and try the same unop with the inner expression
8332 replaced with the reload register. */
8334 if (GET_MODE (op1) != GET_MODE (out))
8335 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8339 gen_reload (out_moded, op1, opnum, type);
8342 = gen_rtx_SET (VOIDmode, out,
8343 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8345 insn = emit_insn_if_valid_for_reload (insn);
8348 set_unique_reg_note (insn, REG_EQUIV, in);
8352 fatal_insn ("Failure trying to reload:", set);
8354 /* If IN is a simple operand, use gen_move_insn. */
8355 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8357 tem = emit_insn (gen_move_insn (out, in));
8358 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8359 mark_jump_label (in, tem, 0);
8362 #ifdef HAVE_reload_load_address
8363 else if (HAVE_reload_load_address)
8364 emit_insn (gen_reload_load_address (out, in));
8367 /* Otherwise, just write (set OUT IN) and hope for the best. */
8369 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8371 /* Return the first insn emitted.
8372 We can not just return get_last_insn, because there may have
8373 been multiple instructions emitted. Also note that gen_move_insn may
8374 emit more than one insn itself, so we can not assume that there is one
8375 insn emitted per emit_insn_before call. */
8377 return last ? NEXT_INSN (last) : get_insns ();
8380 /* Delete a previously made output-reload whose result we now believe
8381 is not needed. First we double-check.
8383 INSN is the insn now being processed.
8384 LAST_RELOAD_REG is the hard register number for which we want to delete
8385 the last output reload.
8386 J is the reload-number that originally used REG. The caller has made
8387 certain that reload J doesn't use REG any longer for input.
8388 NEW_RELOAD_REG is reload register that reload J is using for REG. */
8391 delete_output_reload (rtx insn, int j, int last_reload_reg, rtx new_reload_reg)
8393 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8394 rtx reg = spill_reg_stored_to[last_reload_reg];
8397 int n_inherited = 0;
8401 /* It is possible that this reload has been only used to set another reload
8402 we eliminated earlier and thus deleted this instruction too. */
8403 if (INSN_DELETED_P (output_reload_insn))
8406 /* Get the raw pseudo-register referred to. */
8408 while (GET_CODE (reg) == SUBREG)
8409 reg = SUBREG_REG (reg);
8410 substed = reg_equiv_memory_loc[REGNO (reg)];
8412 /* This is unsafe if the operand occurs more often in the current
8413 insn than it is inherited. */
8414 for (k = n_reloads - 1; k >= 0; k--)
8416 rtx reg2 = rld[k].in;
8419 if (MEM_P (reg2) || reload_override_in[k])
8420 reg2 = rld[k].in_reg;
8422 if (rld[k].out && ! rld[k].out_reg)
8423 reg2 = XEXP (rld[k].in_reg, 0);
8425 while (GET_CODE (reg2) == SUBREG)
8426 reg2 = SUBREG_REG (reg2);
8427 if (rtx_equal_p (reg2, reg))
8429 if (reload_inherited[k] || reload_override_in[k] || k == j)
8435 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8436 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8437 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8440 n_occurrences += count_occurrences (PATTERN (insn),
8441 eliminate_regs (substed, VOIDmode,
8443 for (i1 = reg_equiv_alt_mem_list[REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8445 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8446 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8448 if (n_occurrences > n_inherited)
8451 /* If the pseudo-reg we are reloading is no longer referenced
8452 anywhere between the store into it and here,
8453 and we're within the same basic block, then the value can only
8454 pass through the reload reg and end up here.
8455 Otherwise, give up--return. */
8456 for (i1 = NEXT_INSN (output_reload_insn);
8457 i1 != insn; i1 = NEXT_INSN (i1))
8459 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8461 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8462 && reg_mentioned_p (reg, PATTERN (i1)))
8464 /* If this is USE in front of INSN, we only have to check that
8465 there are no more references than accounted for by inheritance. */
8466 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8468 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8469 i1 = NEXT_INSN (i1);
8471 if (n_occurrences <= n_inherited && i1 == insn)
8477 /* We will be deleting the insn. Remove the spill reg information. */
8478 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8480 spill_reg_store[last_reload_reg + k] = 0;
8481 spill_reg_stored_to[last_reload_reg + k] = 0;
8484 /* The caller has already checked that REG dies or is set in INSN.
8485 It has also checked that we are optimizing, and thus some
8486 inaccuracies in the debugging information are acceptable.
8487 So we could just delete output_reload_insn. But in some cases
8488 we can improve the debugging information without sacrificing
8489 optimization - maybe even improving the code: See if the pseudo
8490 reg has been completely replaced with reload regs. If so, delete
8491 the store insn and forget we had a stack slot for the pseudo. */
8492 if (rld[j].out != rld[j].in
8493 && REG_N_DEATHS (REGNO (reg)) == 1
8494 && REG_N_SETS (REGNO (reg)) == 1
8495 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8496 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8500 /* We know that it was used only between here and the beginning of
8501 the current basic block. (We also know that the last use before
8502 INSN was the output reload we are thinking of deleting, but never
8503 mind that.) Search that range; see if any ref remains. */
8504 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8506 rtx set = single_set (i2);
8508 /* Uses which just store in the pseudo don't count,
8509 since if they are the only uses, they are dead. */
8510 if (set != 0 && SET_DEST (set) == reg)
8515 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8516 && reg_mentioned_p (reg, PATTERN (i2)))
8518 /* Some other ref remains; just delete the output reload we
8520 delete_address_reloads (output_reload_insn, insn);
8521 delete_insn (output_reload_insn);
8526 /* Delete the now-dead stores into this pseudo. Note that this
8527 loop also takes care of deleting output_reload_insn. */
8528 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8530 rtx set = single_set (i2);
8532 if (set != 0 && SET_DEST (set) == reg)
8534 delete_address_reloads (i2, insn);
8542 /* For the debugging info, say the pseudo lives in this reload reg. */
8543 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg);
8544 if (ira_conflicts_p)
8545 /* Inform IRA about the change. */
8546 ira_mark_allocation_change (REGNO (reg));
8547 alter_reg (REGNO (reg), -1, false);
8551 delete_address_reloads (output_reload_insn, insn);
8552 delete_insn (output_reload_insn);
8556 /* We are going to delete DEAD_INSN. Recursively delete loads of
8557 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8558 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8560 delete_address_reloads (rtx dead_insn, rtx current_insn)
8562 rtx set = single_set (dead_insn);
8563 rtx set2, dst, prev, next;
8566 rtx dst = SET_DEST (set);
8568 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8570 /* If we deleted the store from a reloaded post_{in,de}c expression,
8571 we can delete the matching adds. */
8572 prev = PREV_INSN (dead_insn);
8573 next = NEXT_INSN (dead_insn);
8574 if (! prev || ! next)
8576 set = single_set (next);
8577 set2 = single_set (prev);
8579 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8580 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8581 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8583 dst = SET_DEST (set);
8584 if (! rtx_equal_p (dst, SET_DEST (set2))
8585 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8586 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8587 || (INTVAL (XEXP (SET_SRC (set), 1))
8588 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8590 delete_related_insns (prev);
8591 delete_related_insns (next);
8594 /* Subfunction of delete_address_reloads: process registers found in X. */
8596 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8598 rtx prev, set, dst, i2;
8600 enum rtx_code code = GET_CODE (x);
8604 const char *fmt = GET_RTX_FORMAT (code);
8605 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8608 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8609 else if (fmt[i] == 'E')
8611 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8612 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8619 if (spill_reg_order[REGNO (x)] < 0)
8622 /* Scan backwards for the insn that sets x. This might be a way back due
8624 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8626 code = GET_CODE (prev);
8627 if (code == CODE_LABEL || code == JUMP_INSN)
8631 if (reg_set_p (x, PATTERN (prev)))
8633 if (reg_referenced_p (x, PATTERN (prev)))
8636 if (! prev || INSN_UID (prev) < reload_first_uid)
8638 /* Check that PREV only sets the reload register. */
8639 set = single_set (prev);
8642 dst = SET_DEST (set);
8644 || ! rtx_equal_p (dst, x))
8646 if (! reg_set_p (dst, PATTERN (dead_insn)))
8648 /* Check if DST was used in a later insn -
8649 it might have been inherited. */
8650 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8656 if (reg_referenced_p (dst, PATTERN (i2)))
8658 /* If there is a reference to the register in the current insn,
8659 it might be loaded in a non-inherited reload. If no other
8660 reload uses it, that means the register is set before
8662 if (i2 == current_insn)
8664 for (j = n_reloads - 1; j >= 0; j--)
8665 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8666 || reload_override_in[j] == dst)
8668 for (j = n_reloads - 1; j >= 0; j--)
8669 if (rld[j].in && rld[j].reg_rtx == dst)
8678 /* If DST is still live at CURRENT_INSN, check if it is used for
8679 any reload. Note that even if CURRENT_INSN sets DST, we still
8680 have to check the reloads. */
8681 if (i2 == current_insn)
8683 for (j = n_reloads - 1; j >= 0; j--)
8684 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8685 || reload_override_in[j] == dst)
8687 /* ??? We can't finish the loop here, because dst might be
8688 allocated to a pseudo in this block if no reload in this
8689 block needs any of the classes containing DST - see
8690 spill_hard_reg. There is no easy way to tell this, so we
8691 have to scan till the end of the basic block. */
8693 if (reg_set_p (dst, PATTERN (i2)))
8697 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8698 reg_reloaded_contents[REGNO (dst)] = -1;
8702 /* Output reload-insns to reload VALUE into RELOADREG.
8703 VALUE is an autoincrement or autodecrement RTX whose operand
8704 is a register or memory location;
8705 so reloading involves incrementing that location.
8706 IN is either identical to VALUE, or some cheaper place to reload from.
8708 INC_AMOUNT is the number to increment or decrement by (always positive).
8709 This cannot be deduced from VALUE.
8711 Return the instruction that stores into RELOADREG. */
8714 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8716 /* REG or MEM to be copied and incremented. */
8717 rtx incloc = find_replacement (&XEXP (value, 0));
8718 /* Nonzero if increment after copying. */
8719 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8720 || GET_CODE (value) == POST_MODIFY);
8726 rtx real_in = in == value ? incloc : in;
8728 /* No hard register is equivalent to this register after
8729 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8730 we could inc/dec that register as well (maybe even using it for
8731 the source), but I'm not sure it's worth worrying about. */
8733 reg_last_reload_reg[REGNO (incloc)] = 0;
8735 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8737 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8738 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8742 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8743 inc_amount = -inc_amount;
8745 inc = GEN_INT (inc_amount);
8748 /* If this is post-increment, first copy the location to the reload reg. */
8749 if (post && real_in != reloadreg)
8750 emit_insn (gen_move_insn (reloadreg, real_in));
8754 /* See if we can directly increment INCLOC. Use a method similar to
8755 that in gen_reload. */
8757 last = get_last_insn ();
8758 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8759 gen_rtx_PLUS (GET_MODE (incloc),
8762 code = recog_memoized (add_insn);
8765 extract_insn (add_insn);
8766 if (constrain_operands (1))
8768 /* If this is a pre-increment and we have incremented the value
8769 where it lives, copy the incremented value to RELOADREG to
8770 be used as an address. */
8773 emit_insn (gen_move_insn (reloadreg, incloc));
8778 delete_insns_since (last);
8781 /* If couldn't do the increment directly, must increment in RELOADREG.
8782 The way we do this depends on whether this is pre- or post-increment.
8783 For pre-increment, copy INCLOC to the reload register, increment it
8784 there, then save back. */
8788 if (in != reloadreg)
8789 emit_insn (gen_move_insn (reloadreg, real_in));
8790 emit_insn (gen_add2_insn (reloadreg, inc));
8791 store = emit_insn (gen_move_insn (incloc, reloadreg));
8796 Because this might be a jump insn or a compare, and because RELOADREG
8797 may not be available after the insn in an input reload, we must do
8798 the incrementation before the insn being reloaded for.
8800 We have already copied IN to RELOADREG. Increment the copy in
8801 RELOADREG, save that back, then decrement RELOADREG so it has
8802 the original value. */
8804 emit_insn (gen_add2_insn (reloadreg, inc));
8805 store = emit_insn (gen_move_insn (incloc, reloadreg));
8806 if (GET_CODE (inc) == CONST_INT)
8807 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8809 emit_insn (gen_sub2_insn (reloadreg, inc));
8817 add_auto_inc_notes (rtx insn, rtx x)
8819 enum rtx_code code = GET_CODE (x);
8823 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8825 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0));
8829 /* Scan all the operand sub-expressions. */
8830 fmt = GET_RTX_FORMAT (code);
8831 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8834 add_auto_inc_notes (insn, XEXP (x, i));
8835 else if (fmt[i] == 'E')
8836 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8837 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8842 /* Copy EH notes from an insn to its reloads. */
8844 copy_eh_notes (rtx insn, rtx x)
8846 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8849 for (; x != 0; x = NEXT_INSN (x))
8851 if (may_trap_p (PATTERN (x)))
8852 add_reg_note (x, REG_EH_REGION, XEXP (eh_note, 0));
8857 /* This is used by reload pass, that does emit some instructions after
8858 abnormal calls moving basic block end, but in fact it wants to emit
8859 them on the edge. Looks for abnormal call edges, find backward the
8860 proper call and fix the damage.
8862 Similar handle instructions throwing exceptions internally. */
8864 fixup_abnormal_edges (void)
8866 bool inserted = false;
8874 /* Look for cases we are interested in - calls or instructions causing
8876 FOR_EACH_EDGE (e, ei, bb->succs)
8878 if (e->flags & EDGE_ABNORMAL_CALL)
8880 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8881 == (EDGE_ABNORMAL | EDGE_EH))
8884 if (e && !CALL_P (BB_END (bb))
8885 && !can_throw_internal (BB_END (bb)))
8889 /* Get past the new insns generated. Allow notes, as the insns
8890 may be already deleted. */
8892 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8893 && !can_throw_internal (insn)
8894 && insn != BB_HEAD (bb))
8895 insn = PREV_INSN (insn);
8897 if (CALL_P (insn) || can_throw_internal (insn))
8901 stop = NEXT_INSN (BB_END (bb));
8903 insn = NEXT_INSN (insn);
8905 FOR_EACH_EDGE (e, ei, bb->succs)
8906 if (e->flags & EDGE_FALLTHRU)
8909 while (insn && insn != stop)
8911 next = NEXT_INSN (insn);
8916 /* Sometimes there's still the return value USE.
8917 If it's placed after a trapping call (i.e. that
8918 call is the last insn anyway), we have no fallthru
8919 edge. Simply delete this use and don't try to insert
8920 on the non-existent edge. */
8921 if (GET_CODE (PATTERN (insn)) != USE)
8923 /* We're not deleting it, we're moving it. */
8924 INSN_DELETED_P (insn) = 0;
8925 PREV_INSN (insn) = NULL_RTX;
8926 NEXT_INSN (insn) = NULL_RTX;
8928 insert_insn_on_edge (insn, e);
8932 else if (!BARRIER_P (insn))
8933 set_block_for_insn (insn, NULL);
8938 /* It may be that we don't find any such trapping insn. In this
8939 case we discovered quite late that the insn that had been
8940 marked as can_throw_internal in fact couldn't trap at all.
8941 So we should in fact delete the EH edges out of the block. */
8943 purge_dead_edges (bb);
8947 /* We've possibly turned single trapping insn into multiple ones. */
8948 if (flag_non_call_exceptions)
8951 blocks = sbitmap_alloc (last_basic_block);
8952 sbitmap_ones (blocks);
8953 find_many_sub_basic_blocks (blocks);
8954 sbitmap_free (blocks);
8958 commit_edge_insertions ();
8960 #ifdef ENABLE_CHECKING
8961 /* Verify that we didn't turn one trapping insn into many, and that
8962 we found and corrected all of the problems wrt fixups on the
8964 verify_flow_info ();
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