1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001 Free Software Foundation, Inc.
5 This file is part of GNU CC.
7 GNU CC is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 2, or (at your option)
12 GNU CC is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with GNU CC; see the file COPYING. If not, write to
19 the Free Software Foundation, 59 Temple Place - Suite 330,
20 Boston, MA 02111-1307, USA. */
26 #include "hard-reg-set.h"
30 #include "insn-config.h"
35 #include "basic-block.h"
43 #if !defined PREFERRED_STACK_BOUNDARY && defined STACK_BOUNDARY
44 #define PREFERRED_STACK_BOUNDARY STACK_BOUNDARY
47 /* This file contains the reload pass of the compiler, which is
48 run after register allocation has been done. It checks that
49 each insn is valid (operands required to be in registers really
50 are in registers of the proper class) and fixes up invalid ones
51 by copying values temporarily into registers for the insns
54 The results of register allocation are described by the vector
55 reg_renumber; the insns still contain pseudo regs, but reg_renumber
56 can be used to find which hard reg, if any, a pseudo reg is in.
58 The technique we always use is to free up a few hard regs that are
59 called ``reload regs'', and for each place where a pseudo reg
60 must be in a hard reg, copy it temporarily into one of the reload regs.
62 Reload regs are allocated locally for every instruction that needs
63 reloads. When there are pseudos which are allocated to a register that
64 has been chosen as a reload reg, such pseudos must be ``spilled''.
65 This means that they go to other hard regs, or to stack slots if no other
66 available hard regs can be found. Spilling can invalidate more
67 insns, requiring additional need for reloads, so we must keep checking
68 until the process stabilizes.
70 For machines with different classes of registers, we must keep track
71 of the register class needed for each reload, and make sure that
72 we allocate enough reload registers of each class.
74 The file reload.c contains the code that checks one insn for
75 validity and reports the reloads that it needs. This file
76 is in charge of scanning the entire rtl code, accumulating the
77 reload needs, spilling, assigning reload registers to use for
78 fixing up each insn, and generating the new insns to copy values
79 into the reload registers. */
81 #ifndef REGISTER_MOVE_COST
82 #define REGISTER_MOVE_COST(m, x, y) 2
86 #define LOCAL_REGNO(REGNO) 0
89 /* During reload_as_needed, element N contains a REG rtx for the hard reg
90 into which reg N has been reloaded (perhaps for a previous insn). */
91 static rtx *reg_last_reload_reg;
93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
94 for an output reload that stores into reg N. */
95 static char *reg_has_output_reload;
97 /* Indicates which hard regs are reload-registers for an output reload
98 in the current insn. */
99 static HARD_REG_SET reg_is_output_reload;
101 /* Element N is the constant value to which pseudo reg N is equivalent,
102 or zero if pseudo reg N is not equivalent to a constant.
103 find_reloads looks at this in order to replace pseudo reg N
104 with the constant it stands for. */
105 rtx *reg_equiv_constant;
107 /* Element N is a memory location to which pseudo reg N is equivalent,
108 prior to any register elimination (such as frame pointer to stack
109 pointer). Depending on whether or not it is a valid address, this value
110 is transferred to either reg_equiv_address or reg_equiv_mem. */
111 rtx *reg_equiv_memory_loc;
113 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
114 This is used when the address is not valid as a memory address
115 (because its displacement is too big for the machine.) */
116 rtx *reg_equiv_address;
118 /* Element N is the memory slot to which pseudo reg N is equivalent,
119 or zero if pseudo reg N is not equivalent to a memory slot. */
122 /* Widest width in which each pseudo reg is referred to (via subreg). */
123 static unsigned int *reg_max_ref_width;
125 /* Element N is the list of insns that initialized reg N from its equivalent
126 constant or memory slot. */
127 static rtx *reg_equiv_init;
129 /* Vector to remember old contents of reg_renumber before spilling. */
130 static short *reg_old_renumber;
132 /* During reload_as_needed, element N contains the last pseudo regno reloaded
133 into hard register N. If that pseudo reg occupied more than one register,
134 reg_reloaded_contents points to that pseudo for each spill register in
135 use; all of these must remain set for an inheritance to occur. */
136 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
138 /* During reload_as_needed, element N contains the insn for which
139 hard register N was last used. Its contents are significant only
140 when reg_reloaded_valid is set for this register. */
141 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
143 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid */
144 static HARD_REG_SET reg_reloaded_valid;
145 /* Indicate if the register was dead at the end of the reload.
146 This is only valid if reg_reloaded_contents is set and valid. */
147 static HARD_REG_SET reg_reloaded_dead;
149 /* Number of spill-regs so far; number of valid elements of spill_regs. */
152 /* In parallel with spill_regs, contains REG rtx's for those regs.
153 Holds the last rtx used for any given reg, or 0 if it has never
154 been used for spilling yet. This rtx is reused, provided it has
156 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
158 /* In parallel with spill_regs, contains nonzero for a spill reg
159 that was stored after the last time it was used.
160 The precise value is the insn generated to do the store. */
161 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
163 /* This is the register that was stored with spill_reg_store. This is a
164 copy of reload_out / reload_out_reg when the value was stored; if
165 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
166 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
168 /* This table is the inverse mapping of spill_regs:
169 indexed by hard reg number,
170 it contains the position of that reg in spill_regs,
171 or -1 for something that is not in spill_regs.
173 ?!? This is no longer accurate. */
174 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
176 /* This reg set indicates registers that can't be used as spill registers for
177 the currently processed insn. These are the hard registers which are live
178 during the insn, but not allocated to pseudos, as well as fixed
180 static HARD_REG_SET bad_spill_regs;
182 /* These are the hard registers that can't be used as spill register for any
183 insn. This includes registers used for user variables and registers that
184 we can't eliminate. A register that appears in this set also can't be used
185 to retry register allocation. */
186 static HARD_REG_SET bad_spill_regs_global;
188 /* Describes order of use of registers for reloading
189 of spilled pseudo-registers. `n_spills' is the number of
190 elements that are actually valid; new ones are added at the end.
192 Both spill_regs and spill_reg_order are used on two occasions:
193 once during find_reload_regs, where they keep track of the spill registers
194 for a single insn, but also during reload_as_needed where they show all
195 the registers ever used by reload. For the latter case, the information
196 is calculated during finish_spills. */
197 static short spill_regs[FIRST_PSEUDO_REGISTER];
199 /* This vector of reg sets indicates, for each pseudo, which hard registers
200 may not be used for retrying global allocation because the register was
201 formerly spilled from one of them. If we allowed reallocating a pseudo to
202 a register that it was already allocated to, reload might not
204 static HARD_REG_SET *pseudo_previous_regs;
206 /* This vector of reg sets indicates, for each pseudo, which hard
207 registers may not be used for retrying global allocation because they
208 are used as spill registers during one of the insns in which the
210 static HARD_REG_SET *pseudo_forbidden_regs;
212 /* All hard regs that have been used as spill registers for any insn are
213 marked in this set. */
214 static HARD_REG_SET used_spill_regs;
216 /* Index of last register assigned as a spill register. We allocate in
217 a round-robin fashion. */
218 static int last_spill_reg;
220 /* Nonzero if indirect addressing is supported on the machine; this means
221 that spilling (REG n) does not require reloading it into a register in
222 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
223 value indicates the level of indirect addressing supported, e.g., two
224 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
226 static char spill_indirect_levels;
228 /* Nonzero if indirect addressing is supported when the innermost MEM is
229 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
230 which these are valid is the same as spill_indirect_levels, above. */
231 char indirect_symref_ok;
233 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
234 char double_reg_address_ok;
236 /* Record the stack slot for each spilled hard register. */
237 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
239 /* Width allocated so far for that stack slot. */
240 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
242 /* Record which pseudos needed to be spilled. */
243 static regset_head spilled_pseudos;
245 /* Used for communication between order_regs_for_reload and count_pseudo.
246 Used to avoid counting one pseudo twice. */
247 static regset_head pseudos_counted;
249 /* First uid used by insns created by reload in this function.
250 Used in find_equiv_reg. */
251 int reload_first_uid;
253 /* Flag set by local-alloc or global-alloc if anything is live in
254 a call-clobbered reg across calls. */
255 int caller_save_needed;
257 /* Set to 1 while reload_as_needed is operating.
258 Required by some machines to handle any generated moves differently. */
259 int reload_in_progress = 0;
261 /* These arrays record the insn_code of insns that may be needed to
262 perform input and output reloads of special objects. They provide a
263 place to pass a scratch register. */
264 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
265 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
267 /* This obstack is used for allocation of rtl during register elimination.
268 The allocated storage can be freed once find_reloads has processed the
270 struct obstack reload_obstack;
272 /* Points to the beginning of the reload_obstack. All insn_chain structures
273 are allocated first. */
274 char *reload_startobj;
276 /* The point after all insn_chain structures. Used to quickly deallocate
277 memory allocated in copy_reloads during calculate_needs_all_insns. */
278 char *reload_firstobj;
280 /* This points before all local rtl generated by register elimination.
281 Used to quickly free all memory after processing one insn. */
282 static char *reload_insn_firstobj;
284 #define obstack_chunk_alloc xmalloc
285 #define obstack_chunk_free free
287 /* List of insn_chain instructions, one for every insn that reload needs to
289 struct insn_chain *reload_insn_chain;
292 extern tree current_function_decl;
294 extern union tree_node *current_function_decl;
297 /* List of all insns needing reloads. */
298 static struct insn_chain *insns_need_reload;
300 /* This structure is used to record information about register eliminations.
301 Each array entry describes one possible way of eliminating a register
302 in favor of another. If there is more than one way of eliminating a
303 particular register, the most preferred should be specified first. */
307 int from; /* Register number to be eliminated. */
308 int to; /* Register number used as replacement. */
309 int initial_offset; /* Initial difference between values. */
310 int can_eliminate; /* Non-zero if this elimination can be done. */
311 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
312 insns made by reload. */
313 int offset; /* Current offset between the two regs. */
314 int previous_offset; /* Offset at end of previous insn. */
315 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
316 rtx from_rtx; /* REG rtx for the register to be eliminated.
317 We cannot simply compare the number since
318 we might then spuriously replace a hard
319 register corresponding to a pseudo
320 assigned to the reg to be eliminated. */
321 rtx to_rtx; /* REG rtx for the replacement. */
324 static struct elim_table *reg_eliminate = 0;
326 /* This is an intermediate structure to initialize the table. It has
327 exactly the members provided by ELIMINABLE_REGS. */
328 static struct elim_table_1
332 } reg_eliminate_1[] =
334 /* If a set of eliminable registers was specified, define the table from it.
335 Otherwise, default to the normal case of the frame pointer being
336 replaced by the stack pointer. */
338 #ifdef ELIMINABLE_REGS
341 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
344 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
346 /* Record the number of pending eliminations that have an offset not equal
347 to their initial offset. If non-zero, we use a new copy of each
348 replacement result in any insns encountered. */
349 int num_not_at_initial_offset;
351 /* Count the number of registers that we may be able to eliminate. */
352 static int num_eliminable;
353 /* And the number of registers that are equivalent to a constant that
354 can be eliminated to frame_pointer / arg_pointer + constant. */
355 static int num_eliminable_invariants;
357 /* For each label, we record the offset of each elimination. If we reach
358 a label by more than one path and an offset differs, we cannot do the
359 elimination. This information is indexed by the number of the label.
360 The first table is an array of flags that records whether we have yet
361 encountered a label and the second table is an array of arrays, one
362 entry in the latter array for each elimination. */
364 static char *offsets_known_at;
365 static int (*offsets_at)[NUM_ELIMINABLE_REGS];
367 /* Number of labels in the current function. */
369 static int num_labels;
371 static void replace_pseudos_in_call_usage PARAMS((rtx *,
374 static void maybe_fix_stack_asms PARAMS ((void));
375 static void copy_reloads PARAMS ((struct insn_chain *));
376 static void calculate_needs_all_insns PARAMS ((int));
377 static int find_reg PARAMS ((struct insn_chain *, int));
378 static void find_reload_regs PARAMS ((struct insn_chain *));
379 static void select_reload_regs PARAMS ((void));
380 static void delete_caller_save_insns PARAMS ((void));
382 static void spill_failure PARAMS ((rtx, enum reg_class));
383 static void count_spilled_pseudo PARAMS ((int, int, int));
384 static void delete_dead_insn PARAMS ((rtx));
385 static void alter_reg PARAMS ((int, int));
386 static void set_label_offsets PARAMS ((rtx, rtx, int));
387 static void check_eliminable_occurrences PARAMS ((rtx));
388 static void elimination_effects PARAMS ((rtx, enum machine_mode));
389 static int eliminate_regs_in_insn PARAMS ((rtx, int));
390 static void update_eliminable_offsets PARAMS ((void));
391 static void mark_not_eliminable PARAMS ((rtx, rtx, void *));
392 static void set_initial_elim_offsets PARAMS ((void));
393 static void verify_initial_elim_offsets PARAMS ((void));
394 static void set_initial_label_offsets PARAMS ((void));
395 static void set_offsets_for_label PARAMS ((rtx));
396 static void init_elim_table PARAMS ((void));
397 static void update_eliminables PARAMS ((HARD_REG_SET *));
398 static void spill_hard_reg PARAMS ((unsigned int, int));
399 static int finish_spills PARAMS ((int));
400 static void ior_hard_reg_set PARAMS ((HARD_REG_SET *, HARD_REG_SET *));
401 static void scan_paradoxical_subregs PARAMS ((rtx));
402 static void count_pseudo PARAMS ((int));
403 static void order_regs_for_reload PARAMS ((struct insn_chain *));
404 static void reload_as_needed PARAMS ((int));
405 static void forget_old_reloads_1 PARAMS ((rtx, rtx, void *));
406 static int reload_reg_class_lower PARAMS ((const PTR, const PTR));
407 static void mark_reload_reg_in_use PARAMS ((unsigned int, int,
410 static void clear_reload_reg_in_use PARAMS ((unsigned int, int,
413 static int reload_reg_free_p PARAMS ((unsigned int, int,
415 static int reload_reg_free_for_value_p PARAMS ((int, int, int,
417 rtx, rtx, int, int));
418 static int free_for_value_p PARAMS ((int, enum machine_mode, int,
419 enum reload_type, rtx, rtx,
421 static int reload_reg_reaches_end_p PARAMS ((unsigned int, int,
423 static int allocate_reload_reg PARAMS ((struct insn_chain *, int,
425 static int conflicts_with_override PARAMS ((rtx));
426 static void failed_reload PARAMS ((rtx, int));
427 static int set_reload_reg PARAMS ((int, int));
428 static void choose_reload_regs_init PARAMS ((struct insn_chain *, rtx *));
429 static void choose_reload_regs PARAMS ((struct insn_chain *));
430 static void merge_assigned_reloads PARAMS ((rtx));
431 static void emit_input_reload_insns PARAMS ((struct insn_chain *,
432 struct reload *, rtx, int));
433 static void emit_output_reload_insns PARAMS ((struct insn_chain *,
434 struct reload *, int));
435 static void do_input_reload PARAMS ((struct insn_chain *,
436 struct reload *, int));
437 static void do_output_reload PARAMS ((struct insn_chain *,
438 struct reload *, int));
439 static void emit_reload_insns PARAMS ((struct insn_chain *));
440 static void delete_output_reload PARAMS ((rtx, int, int));
441 static void delete_address_reloads PARAMS ((rtx, rtx));
442 static void delete_address_reloads_1 PARAMS ((rtx, rtx, rtx));
443 static rtx inc_for_reload PARAMS ((rtx, rtx, rtx, int));
444 static int constraint_accepts_reg_p PARAMS ((const char *, rtx));
445 static void reload_cse_regs_1 PARAMS ((rtx));
446 static int reload_cse_noop_set_p PARAMS ((rtx));
447 static int reload_cse_simplify_set PARAMS ((rtx, rtx));
448 static int reload_cse_simplify_operands PARAMS ((rtx));
449 static void reload_combine PARAMS ((void));
450 static void reload_combine_note_use PARAMS ((rtx *, rtx));
451 static void reload_combine_note_store PARAMS ((rtx, rtx, void *));
452 static void reload_cse_move2add PARAMS ((rtx));
453 static void move2add_note_store PARAMS ((rtx, rtx, void *));
455 static void add_auto_inc_notes PARAMS ((rtx, rtx));
457 static void copy_eh_notes PARAMS ((rtx, rtx));
458 static HOST_WIDE_INT sext_for_mode PARAMS ((enum machine_mode,
460 static void failed_reload PARAMS ((rtx, int));
461 static int set_reload_reg PARAMS ((int, int));
462 static void reload_cse_delete_noop_set PARAMS ((rtx, rtx));
463 static void reload_cse_simplify PARAMS ((rtx));
464 extern void dump_needs PARAMS ((struct insn_chain *));
466 /* Initialize the reload pass once per compilation. */
473 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
474 Set spill_indirect_levels to the number of levels such addressing is
475 permitted, zero if it is not permitted at all. */
478 = gen_rtx_MEM (Pmode,
481 LAST_VIRTUAL_REGISTER + 1),
483 spill_indirect_levels = 0;
485 while (memory_address_p (QImode, tem))
487 spill_indirect_levels++;
488 tem = gen_rtx_MEM (Pmode, tem);
491 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
493 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
494 indirect_symref_ok = memory_address_p (QImode, tem);
496 /* See if reg+reg is a valid (and offsettable) address. */
498 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
500 tem = gen_rtx_PLUS (Pmode,
501 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
502 gen_rtx_REG (Pmode, i));
504 /* This way, we make sure that reg+reg is an offsettable address. */
505 tem = plus_constant (tem, 4);
507 if (memory_address_p (QImode, tem))
509 double_reg_address_ok = 1;
514 /* Initialize obstack for our rtl allocation. */
515 gcc_obstack_init (&reload_obstack);
516 reload_startobj = (char *) obstack_alloc (&reload_obstack, 0);
518 INIT_REG_SET (&spilled_pseudos);
519 INIT_REG_SET (&pseudos_counted);
522 /* List of insn chains that are currently unused. */
523 static struct insn_chain *unused_insn_chains = 0;
525 /* Allocate an empty insn_chain structure. */
529 struct insn_chain *c;
531 if (unused_insn_chains == 0)
533 c = (struct insn_chain *)
534 obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
535 INIT_REG_SET (&c->live_throughout);
536 INIT_REG_SET (&c->dead_or_set);
540 c = unused_insn_chains;
541 unused_insn_chains = c->next;
543 c->is_caller_save_insn = 0;
544 c->need_operand_change = 0;
550 /* Small utility function to set all regs in hard reg set TO which are
551 allocated to pseudos in regset FROM. */
554 compute_use_by_pseudos (to, from)
560 EXECUTE_IF_SET_IN_REG_SET
561 (from, FIRST_PSEUDO_REGISTER, regno,
563 int r = reg_renumber[regno];
568 /* reload_combine uses the information from
569 BASIC_BLOCK->global_live_at_start, which might still
570 contain registers that have not actually been allocated
571 since they have an equivalence. */
572 if (! reload_completed)
577 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (regno));
579 SET_HARD_REG_BIT (*to, r + nregs);
584 /* Replace all pseudos found in LOC with their corresponding
588 replace_pseudos_in_call_usage (loc, mem_mode, usage)
590 enum machine_mode mem_mode;
604 int regno = REGNO (x);
606 if (regno < FIRST_PSEUDO_REGISTER)
609 x = eliminate_regs (x, mem_mode, usage);
613 replace_pseudos_in_call_usage (loc, mem_mode, usage);
617 if (reg_equiv_constant[regno])
618 *loc = reg_equiv_constant[regno];
619 else if (reg_equiv_mem[regno])
620 *loc = reg_equiv_mem[regno];
621 else if (reg_equiv_address[regno])
622 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
623 else if (GET_CODE (regno_reg_rtx[regno]) != REG
624 || REGNO (regno_reg_rtx[regno]) != regno)
625 *loc = regno_reg_rtx[regno];
631 else if (code == MEM)
633 replace_pseudos_in_call_usage (& XEXP (x, 0), GET_MODE (x), usage);
637 /* Process each of our operands recursively. */
638 fmt = GET_RTX_FORMAT (code);
639 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
641 replace_pseudos_in_call_usage (&XEXP (x, i), mem_mode, usage);
642 else if (*fmt == 'E')
643 for (j = 0; j < XVECLEN (x, i); j++)
644 replace_pseudos_in_call_usage (& XVECEXP (x, i, j), mem_mode, usage);
648 /* Global variables used by reload and its subroutines. */
650 /* Set during calculate_needs if an insn needs register elimination. */
651 static int something_needs_elimination;
652 /* Set during calculate_needs if an insn needs an operand changed. */
653 int something_needs_operands_changed;
655 /* Nonzero means we couldn't get enough spill regs. */
658 /* Main entry point for the reload pass.
660 FIRST is the first insn of the function being compiled.
662 GLOBAL nonzero means we were called from global_alloc
663 and should attempt to reallocate any pseudoregs that we
664 displace from hard regs we will use for reloads.
665 If GLOBAL is zero, we do not have enough information to do that,
666 so any pseudo reg that is spilled must go to the stack.
668 Return value is nonzero if reload failed
669 and we must not do any more for this function. */
672 reload (first, global)
678 register struct elim_table *ep;
680 /* The two pointers used to track the true location of the memory used
681 for label offsets. */
682 char *real_known_ptr = NULL;
683 int (*real_at_ptr)[NUM_ELIMINABLE_REGS];
685 /* Make sure even insns with volatile mem refs are recognizable. */
690 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
692 /* Make sure that the last insn in the chain
693 is not something that needs reloading. */
694 emit_note (NULL, NOTE_INSN_DELETED);
696 /* Enable find_equiv_reg to distinguish insns made by reload. */
697 reload_first_uid = get_max_uid ();
699 #ifdef SECONDARY_MEMORY_NEEDED
700 /* Initialize the secondary memory table. */
701 clear_secondary_mem ();
704 /* We don't have a stack slot for any spill reg yet. */
705 memset ((char *) spill_stack_slot, 0, sizeof spill_stack_slot);
706 memset ((char *) spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
708 /* Initialize the save area information for caller-save, in case some
712 /* Compute which hard registers are now in use
713 as homes for pseudo registers.
714 This is done here rather than (eg) in global_alloc
715 because this point is reached even if not optimizing. */
716 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
719 /* A function that receives a nonlocal goto must save all call-saved
721 if (current_function_has_nonlocal_label)
722 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
723 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
724 regs_ever_live[i] = 1;
726 /* Find all the pseudo registers that didn't get hard regs
727 but do have known equivalent constants or memory slots.
728 These include parameters (known equivalent to parameter slots)
729 and cse'd or loop-moved constant memory addresses.
731 Record constant equivalents in reg_equiv_constant
732 so they will be substituted by find_reloads.
733 Record memory equivalents in reg_mem_equiv so they can
734 be substituted eventually by altering the REG-rtx's. */
736 reg_equiv_constant = (rtx *) xcalloc (max_regno, sizeof (rtx));
737 reg_equiv_memory_loc = (rtx *) xcalloc (max_regno, sizeof (rtx));
738 reg_equiv_mem = (rtx *) xcalloc (max_regno, sizeof (rtx));
739 reg_equiv_init = (rtx *) xcalloc (max_regno, sizeof (rtx));
740 reg_equiv_address = (rtx *) xcalloc (max_regno, sizeof (rtx));
741 reg_max_ref_width = (unsigned int *) xcalloc (max_regno, sizeof (int));
742 reg_old_renumber = (short *) xcalloc (max_regno, sizeof (short));
743 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
744 pseudo_forbidden_regs
745 = (HARD_REG_SET *) xmalloc (max_regno * sizeof (HARD_REG_SET));
747 = (HARD_REG_SET *) xcalloc (max_regno, sizeof (HARD_REG_SET));
749 CLEAR_HARD_REG_SET (bad_spill_regs_global);
751 /* Look for REG_EQUIV notes; record what each pseudo is equivalent to.
752 Also find all paradoxical subregs and find largest such for each pseudo.
753 On machines with small register classes, record hard registers that
754 are used for user variables. These can never be used for spills.
755 Also look for a "constant" NOTE_INSN_SETJMP. This means that all
756 caller-saved registers must be marked live. */
758 num_eliminable_invariants = 0;
759 for (insn = first; insn; insn = NEXT_INSN (insn))
761 rtx set = single_set (insn);
763 if (GET_CODE (insn) == NOTE && CONST_CALL_P (insn)
764 && NOTE_LINE_NUMBER (insn) == NOTE_INSN_SETJMP)
765 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
766 if (! call_used_regs[i])
767 regs_ever_live[i] = 1;
769 if (set != 0 && GET_CODE (SET_DEST (set)) == REG)
771 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
773 #ifdef LEGITIMATE_PIC_OPERAND_P
774 && (! function_invariant_p (XEXP (note, 0))
776 || LEGITIMATE_PIC_OPERAND_P (XEXP (note, 0)))
780 rtx x = XEXP (note, 0);
781 i = REGNO (SET_DEST (set));
782 if (i > LAST_VIRTUAL_REGISTER)
784 if (GET_CODE (x) == MEM)
786 /* If the operand is a PLUS, the MEM may be shared,
787 so make sure we have an unshared copy here. */
788 if (GET_CODE (XEXP (x, 0)) == PLUS)
791 reg_equiv_memory_loc[i] = x;
793 else if (function_invariant_p (x))
795 if (GET_CODE (x) == PLUS)
797 /* This is PLUS of frame pointer and a constant,
798 and might be shared. Unshare it. */
799 reg_equiv_constant[i] = copy_rtx (x);
800 num_eliminable_invariants++;
802 else if (x == frame_pointer_rtx
803 || x == arg_pointer_rtx)
805 reg_equiv_constant[i] = x;
806 num_eliminable_invariants++;
808 else if (LEGITIMATE_CONSTANT_P (x))
809 reg_equiv_constant[i] = x;
811 reg_equiv_memory_loc[i]
812 = force_const_mem (GET_MODE (SET_DEST (set)), x);
817 /* If this register is being made equivalent to a MEM
818 and the MEM is not SET_SRC, the equivalencing insn
819 is one with the MEM as a SET_DEST and it occurs later.
820 So don't mark this insn now. */
821 if (GET_CODE (x) != MEM
822 || rtx_equal_p (SET_SRC (set), x))
824 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv_init[i]);
829 /* If this insn is setting a MEM from a register equivalent to it,
830 this is the equivalencing insn. */
831 else if (set && GET_CODE (SET_DEST (set)) == MEM
832 && GET_CODE (SET_SRC (set)) == REG
833 && reg_equiv_memory_loc[REGNO (SET_SRC (set))]
834 && rtx_equal_p (SET_DEST (set),
835 reg_equiv_memory_loc[REGNO (SET_SRC (set))]))
836 reg_equiv_init[REGNO (SET_SRC (set))]
837 = gen_rtx_INSN_LIST (VOIDmode, insn,
838 reg_equiv_init[REGNO (SET_SRC (set))]);
841 scan_paradoxical_subregs (PATTERN (insn));
846 num_labels = max_label_num () - get_first_label_num ();
848 /* Allocate the tables used to store offset information at labels. */
849 /* We used to use alloca here, but the size of what it would try to
850 allocate would occasionally cause it to exceed the stack limit and
851 cause a core dump. */
852 real_known_ptr = xmalloc (num_labels);
854 = (int (*)[NUM_ELIMINABLE_REGS])
855 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (int));
857 offsets_known_at = real_known_ptr - get_first_label_num ();
859 = (int (*)[NUM_ELIMINABLE_REGS]) (real_at_ptr - get_first_label_num ());
861 /* Alter each pseudo-reg rtx to contain its hard reg number.
862 Assign stack slots to the pseudos that lack hard regs or equivalents.
863 Do not touch virtual registers. */
865 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
868 /* If we have some registers we think can be eliminated, scan all insns to
869 see if there is an insn that sets one of these registers to something
870 other than itself plus a constant. If so, the register cannot be
871 eliminated. Doing this scan here eliminates an extra pass through the
872 main reload loop in the most common case where register elimination
874 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
875 if (GET_CODE (insn) == INSN || GET_CODE (insn) == JUMP_INSN
876 || GET_CODE (insn) == CALL_INSN)
877 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
879 maybe_fix_stack_asms ();
881 insns_need_reload = 0;
882 something_needs_elimination = 0;
884 /* Initialize to -1, which means take the first spill register. */
887 /* Spill any hard regs that we know we can't eliminate. */
888 CLEAR_HARD_REG_SET (used_spill_regs);
889 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
890 if (! ep->can_eliminate)
891 spill_hard_reg (ep->from, 1);
893 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
894 if (frame_pointer_needed)
895 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
897 finish_spills (global);
899 /* From now on, we may need to generate moves differently. We may also
900 allow modifications of insns which cause them to not be recognized.
901 Any such modifications will be cleaned up during reload itself. */
902 reload_in_progress = 1;
904 /* This loop scans the entire function each go-round
905 and repeats until one repetition spills no additional hard regs. */
908 int something_changed;
911 HOST_WIDE_INT starting_frame_size;
913 /* Round size of stack frame to stack_alignment_needed. This must be done
914 here because the stack size may be a part of the offset computation
915 for register elimination, and there might have been new stack slots
916 created in the last iteration of this loop. */
917 if (cfun->stack_alignment_needed)
918 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
920 starting_frame_size = get_frame_size ();
922 set_initial_elim_offsets ();
923 set_initial_label_offsets ();
925 /* For each pseudo register that has an equivalent location defined,
926 try to eliminate any eliminable registers (such as the frame pointer)
927 assuming initial offsets for the replacement register, which
930 If the resulting location is directly addressable, substitute
931 the MEM we just got directly for the old REG.
933 If it is not addressable but is a constant or the sum of a hard reg
934 and constant, it is probably not addressable because the constant is
935 out of range, in that case record the address; we will generate
936 hairy code to compute the address in a register each time it is
937 needed. Similarly if it is a hard register, but one that is not
938 valid as an address register.
940 If the location is not addressable, but does not have one of the
941 above forms, assign a stack slot. We have to do this to avoid the
942 potential of producing lots of reloads if, e.g., a location involves
943 a pseudo that didn't get a hard register and has an equivalent memory
944 location that also involves a pseudo that didn't get a hard register.
946 Perhaps at some point we will improve reload_when_needed handling
947 so this problem goes away. But that's very hairy. */
949 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
950 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
952 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
954 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
956 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
957 else if (CONSTANT_P (XEXP (x, 0))
958 || (GET_CODE (XEXP (x, 0)) == REG
959 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
960 || (GET_CODE (XEXP (x, 0)) == PLUS
961 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG
962 && (REGNO (XEXP (XEXP (x, 0), 0))
963 < FIRST_PSEUDO_REGISTER)
964 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
965 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
968 /* Make a new stack slot. Then indicate that something
969 changed so we go back and recompute offsets for
970 eliminable registers because the allocation of memory
971 below might change some offset. reg_equiv_{mem,address}
972 will be set up for this pseudo on the next pass around
974 reg_equiv_memory_loc[i] = 0;
975 reg_equiv_init[i] = 0;
980 if (caller_save_needed)
983 /* If we allocated another stack slot, redo elimination bookkeeping. */
984 if (starting_frame_size != get_frame_size ())
987 if (caller_save_needed)
989 save_call_clobbered_regs ();
990 /* That might have allocated new insn_chain structures. */
991 reload_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
994 calculate_needs_all_insns (global);
996 CLEAR_REG_SET (&spilled_pseudos);
999 something_changed = 0;
1001 /* If we allocated any new memory locations, make another pass
1002 since it might have changed elimination offsets. */
1003 if (starting_frame_size != get_frame_size ())
1004 something_changed = 1;
1007 HARD_REG_SET to_spill;
1008 CLEAR_HARD_REG_SET (to_spill);
1009 update_eliminables (&to_spill);
1010 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1011 if (TEST_HARD_REG_BIT (to_spill, i))
1013 spill_hard_reg (i, 1);
1016 /* Regardless of the state of spills, if we previously had
1017 a register that we thought we could eliminate, but no can
1018 not eliminate, we must run another pass.
1020 Consider pseudos which have an entry in reg_equiv_* which
1021 reference an eliminable register. We must make another pass
1022 to update reg_equiv_* so that we do not substitute in the
1023 old value from when we thought the elimination could be
1025 something_changed = 1;
1029 select_reload_regs ();
1033 if (insns_need_reload != 0 || did_spill)
1034 something_changed |= finish_spills (global);
1036 if (! something_changed)
1039 if (caller_save_needed)
1040 delete_caller_save_insns ();
1042 obstack_free (&reload_obstack, reload_firstobj);
1045 /* If global-alloc was run, notify it of any register eliminations we have
1048 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1049 if (ep->can_eliminate)
1050 mark_elimination (ep->from, ep->to);
1052 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1053 If that insn didn't set the register (i.e., it copied the register to
1054 memory), just delete that insn instead of the equivalencing insn plus
1055 anything now dead. If we call delete_dead_insn on that insn, we may
1056 delete the insn that actually sets the register if the register dies
1057 there and that is incorrect. */
1059 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1061 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1064 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1066 rtx equiv_insn = XEXP (list, 0);
1067 if (GET_CODE (equiv_insn) == NOTE)
1069 if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1070 delete_dead_insn (equiv_insn);
1073 PUT_CODE (equiv_insn, NOTE);
1074 NOTE_SOURCE_FILE (equiv_insn) = 0;
1075 NOTE_LINE_NUMBER (equiv_insn) = NOTE_INSN_DELETED;
1081 /* Use the reload registers where necessary
1082 by generating move instructions to move the must-be-register
1083 values into or out of the reload registers. */
1085 if (insns_need_reload != 0 || something_needs_elimination
1086 || something_needs_operands_changed)
1088 HOST_WIDE_INT old_frame_size = get_frame_size ();
1090 reload_as_needed (global);
1092 if (old_frame_size != get_frame_size ())
1096 verify_initial_elim_offsets ();
1099 /* If we were able to eliminate the frame pointer, show that it is no
1100 longer live at the start of any basic block. If it ls live by
1101 virtue of being in a pseudo, that pseudo will be marked live
1102 and hence the frame pointer will be known to be live via that
1105 if (! frame_pointer_needed)
1106 for (i = 0; i < n_basic_blocks; i++)
1107 CLEAR_REGNO_REG_SET (BASIC_BLOCK (i)->global_live_at_start,
1108 HARD_FRAME_POINTER_REGNUM);
1110 /* Come here (with failure set nonzero) if we can't get enough spill regs
1111 and we decide not to abort about it. */
1114 CLEAR_REG_SET (&spilled_pseudos);
1115 reload_in_progress = 0;
1117 /* Now eliminate all pseudo regs by modifying them into
1118 their equivalent memory references.
1119 The REG-rtx's for the pseudos are modified in place,
1120 so all insns that used to refer to them now refer to memory.
1122 For a reg that has a reg_equiv_address, all those insns
1123 were changed by reloading so that no insns refer to it any longer;
1124 but the DECL_RTL of a variable decl may refer to it,
1125 and if so this causes the debugging info to mention the variable. */
1127 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1132 int is_readonly = 0;
1134 if (reg_equiv_memory_loc[i])
1136 in_struct = MEM_IN_STRUCT_P (reg_equiv_memory_loc[i]);
1137 is_scalar = MEM_SCALAR_P (reg_equiv_memory_loc[i]);
1138 is_readonly = RTX_UNCHANGING_P (reg_equiv_memory_loc[i]);
1141 if (reg_equiv_mem[i])
1142 addr = XEXP (reg_equiv_mem[i], 0);
1144 if (reg_equiv_address[i])
1145 addr = reg_equiv_address[i];
1149 if (reg_renumber[i] < 0)
1151 rtx reg = regno_reg_rtx[i];
1152 PUT_CODE (reg, MEM);
1153 XEXP (reg, 0) = addr;
1154 REG_USERVAR_P (reg) = 0;
1155 RTX_UNCHANGING_P (reg) = is_readonly;
1156 MEM_IN_STRUCT_P (reg) = in_struct;
1157 MEM_SCALAR_P (reg) = is_scalar;
1158 /* We have no alias information about this newly created
1160 MEM_ALIAS_SET (reg) = 0;
1162 else if (reg_equiv_mem[i])
1163 XEXP (reg_equiv_mem[i], 0) = addr;
1167 /* We must set reload_completed now since the cleanup_subreg_operands call
1168 below will re-recognize each insn and reload may have generated insns
1169 which are only valid during and after reload. */
1170 reload_completed = 1;
1172 /* Make a pass over all the insns and delete all USEs which we inserted
1173 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1174 notes. Delete all CLOBBER insns that don't refer to the return value
1175 and simplify (subreg (reg)) operands. Also remove all REG_RETVAL and
1176 REG_LIBCALL notes since they are no longer useful or accurate. Strip
1177 and regenerate REG_INC notes that may have been moved around. */
1179 for (insn = first; insn; insn = NEXT_INSN (insn))
1184 if (GET_CODE (insn) == CALL_INSN)
1185 replace_pseudos_in_call_usage (& CALL_INSN_FUNCTION_USAGE (insn),
1187 CALL_INSN_FUNCTION_USAGE (insn));
1189 if ((GET_CODE (PATTERN (insn)) == USE
1190 && find_reg_note (insn, REG_EQUAL, NULL_RTX))
1191 || (GET_CODE (PATTERN (insn)) == CLOBBER
1192 && (GET_CODE (XEXP (PATTERN (insn), 0)) != REG
1193 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1195 PUT_CODE (insn, NOTE);
1196 NOTE_SOURCE_FILE (insn) = 0;
1197 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1201 pnote = ®_NOTES (insn);
1204 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1205 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1206 || REG_NOTE_KIND (*pnote) == REG_INC
1207 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1208 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1209 *pnote = XEXP (*pnote, 1);
1211 pnote = &XEXP (*pnote, 1);
1215 add_auto_inc_notes (insn, PATTERN (insn));
1218 /* And simplify (subreg (reg)) if it appears as an operand. */
1219 cleanup_subreg_operands (insn);
1222 /* If we are doing stack checking, give a warning if this function's
1223 frame size is larger than we expect. */
1224 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1226 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1227 static int verbose_warned = 0;
1229 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1230 if (regs_ever_live[i] && ! fixed_regs[i] && call_used_regs[i])
1231 size += UNITS_PER_WORD;
1233 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1235 warning ("frame size too large for reliable stack checking");
1236 if (! verbose_warned)
1238 warning ("try reducing the number of local variables");
1244 /* Indicate that we no longer have known memory locations or constants. */
1245 if (reg_equiv_constant)
1246 free (reg_equiv_constant);
1247 reg_equiv_constant = 0;
1248 if (reg_equiv_memory_loc)
1249 free (reg_equiv_memory_loc);
1250 reg_equiv_memory_loc = 0;
1253 free (real_known_ptr);
1257 free (reg_equiv_mem);
1258 free (reg_equiv_init);
1259 free (reg_equiv_address);
1260 free (reg_max_ref_width);
1261 free (reg_old_renumber);
1262 free (pseudo_previous_regs);
1263 free (pseudo_forbidden_regs);
1265 CLEAR_HARD_REG_SET (used_spill_regs);
1266 for (i = 0; i < n_spills; i++)
1267 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1269 /* Free all the insn_chain structures at once. */
1270 obstack_free (&reload_obstack, reload_startobj);
1271 unused_insn_chains = 0;
1276 /* Yet another special case. Unfortunately, reg-stack forces people to
1277 write incorrect clobbers in asm statements. These clobbers must not
1278 cause the register to appear in bad_spill_regs, otherwise we'll call
1279 fatal_insn later. We clear the corresponding regnos in the live
1280 register sets to avoid this.
1281 The whole thing is rather sick, I'm afraid. */
1284 maybe_fix_stack_asms ()
1287 const char *constraints[MAX_RECOG_OPERANDS];
1288 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1289 struct insn_chain *chain;
1291 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1294 HARD_REG_SET clobbered, allowed;
1297 if (! INSN_P (chain->insn)
1298 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1300 pat = PATTERN (chain->insn);
1301 if (GET_CODE (pat) != PARALLEL)
1304 CLEAR_HARD_REG_SET (clobbered);
1305 CLEAR_HARD_REG_SET (allowed);
1307 /* First, make a mask of all stack regs that are clobbered. */
1308 for (i = 0; i < XVECLEN (pat, 0); i++)
1310 rtx t = XVECEXP (pat, 0, i);
1311 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1312 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1315 /* Get the operand values and constraints out of the insn. */
1316 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1317 constraints, operand_mode);
1319 /* For every operand, see what registers are allowed. */
1320 for (i = 0; i < noperands; i++)
1322 const char *p = constraints[i];
1323 /* For every alternative, we compute the class of registers allowed
1324 for reloading in CLS, and merge its contents into the reg set
1326 int cls = (int) NO_REGS;
1332 if (c == '\0' || c == ',' || c == '#')
1334 /* End of one alternative - mark the regs in the current
1335 class, and reset the class. */
1336 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1341 } while (c != '\0' && c != ',');
1349 case '=': case '+': case '*': case '%': case '?': case '!':
1350 case '0': case '1': case '2': case '3': case '4': case 'm':
1351 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1352 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1353 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1358 cls = (int) reg_class_subunion[cls][(int) BASE_REG_CLASS];
1363 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1367 cls = (int) reg_class_subunion[cls][(int) REG_CLASS_FROM_LETTER (c)];
1372 /* Those of the registers which are clobbered, but allowed by the
1373 constraints, must be usable as reload registers. So clear them
1374 out of the life information. */
1375 AND_HARD_REG_SET (allowed, clobbered);
1376 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1377 if (TEST_HARD_REG_BIT (allowed, i))
1379 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1380 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1387 /* Copy the global variables n_reloads and rld into the corresponding elts
1390 copy_reloads (chain)
1391 struct insn_chain *chain;
1393 chain->n_reloads = n_reloads;
1395 = (struct reload *) obstack_alloc (&reload_obstack,
1396 n_reloads * sizeof (struct reload));
1397 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1398 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1401 /* Walk the chain of insns, and determine for each whether it needs reloads
1402 and/or eliminations. Build the corresponding insns_need_reload list, and
1403 set something_needs_elimination as appropriate. */
1405 calculate_needs_all_insns (global)
1408 struct insn_chain **pprev_reload = &insns_need_reload;
1409 struct insn_chain *chain, *next = 0;
1411 something_needs_elimination = 0;
1413 reload_insn_firstobj = (char *) obstack_alloc (&reload_obstack, 0);
1414 for (chain = reload_insn_chain; chain != 0; chain = next)
1416 rtx insn = chain->insn;
1420 /* Clear out the shortcuts. */
1421 chain->n_reloads = 0;
1422 chain->need_elim = 0;
1423 chain->need_reload = 0;
1424 chain->need_operand_change = 0;
1426 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1427 include REG_LABEL), we need to see what effects this has on the
1428 known offsets at labels. */
1430 if (GET_CODE (insn) == CODE_LABEL || GET_CODE (insn) == JUMP_INSN
1431 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1432 set_label_offsets (insn, insn, 0);
1436 rtx old_body = PATTERN (insn);
1437 int old_code = INSN_CODE (insn);
1438 rtx old_notes = REG_NOTES (insn);
1439 int did_elimination = 0;
1440 int operands_changed = 0;
1441 rtx set = single_set (insn);
1443 /* Skip insns that only set an equivalence. */
1444 if (set && GET_CODE (SET_DEST (set)) == REG
1445 && reg_renumber[REGNO (SET_DEST (set))] < 0
1446 && reg_equiv_constant[REGNO (SET_DEST (set))])
1449 /* If needed, eliminate any eliminable registers. */
1450 if (num_eliminable || num_eliminable_invariants)
1451 did_elimination = eliminate_regs_in_insn (insn, 0);
1453 /* Analyze the instruction. */
1454 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1455 global, spill_reg_order);
1457 /* If a no-op set needs more than one reload, this is likely
1458 to be something that needs input address reloads. We
1459 can't get rid of this cleanly later, and it is of no use
1460 anyway, so discard it now.
1461 We only do this when expensive_optimizations is enabled,
1462 since this complements reload inheritance / output
1463 reload deletion, and it can make debugging harder. */
1464 if (flag_expensive_optimizations && n_reloads > 1)
1466 rtx set = single_set (insn);
1468 && SET_SRC (set) == SET_DEST (set)
1469 && GET_CODE (SET_SRC (set)) == REG
1470 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1472 PUT_CODE (insn, NOTE);
1473 NOTE_SOURCE_FILE (insn) = 0;
1474 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1475 /* Delete it from the reload chain */
1477 chain->prev->next = next;
1479 reload_insn_chain = next;
1481 next->prev = chain->prev;
1482 chain->next = unused_insn_chains;
1483 unused_insn_chains = chain;
1488 update_eliminable_offsets ();
1490 /* Remember for later shortcuts which insns had any reloads or
1491 register eliminations. */
1492 chain->need_elim = did_elimination;
1493 chain->need_reload = n_reloads > 0;
1494 chain->need_operand_change = operands_changed;
1496 /* Discard any register replacements done. */
1497 if (did_elimination)
1499 obstack_free (&reload_obstack, reload_insn_firstobj);
1500 PATTERN (insn) = old_body;
1501 INSN_CODE (insn) = old_code;
1502 REG_NOTES (insn) = old_notes;
1503 something_needs_elimination = 1;
1506 something_needs_operands_changed |= operands_changed;
1510 copy_reloads (chain);
1511 *pprev_reload = chain;
1512 pprev_reload = &chain->next_need_reload;
1519 /* Comparison function for qsort to decide which of two reloads
1520 should be handled first. *P1 and *P2 are the reload numbers. */
1523 reload_reg_class_lower (r1p, r2p)
1527 register int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1530 /* Consider required reloads before optional ones. */
1531 t = rld[r1].optional - rld[r2].optional;
1535 /* Count all solitary classes before non-solitary ones. */
1536 t = ((reg_class_size[(int) rld[r2].class] == 1)
1537 - (reg_class_size[(int) rld[r1].class] == 1));
1541 /* Aside from solitaires, consider all multi-reg groups first. */
1542 t = rld[r2].nregs - rld[r1].nregs;
1546 /* Consider reloads in order of increasing reg-class number. */
1547 t = (int) rld[r1].class - (int) rld[r2].class;
1551 /* If reloads are equally urgent, sort by reload number,
1552 so that the results of qsort leave nothing to chance. */
1556 /* The cost of spilling each hard reg. */
1557 static int spill_cost[FIRST_PSEUDO_REGISTER];
1559 /* When spilling multiple hard registers, we use SPILL_COST for the first
1560 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1561 only the first hard reg for a multi-reg pseudo. */
1562 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1564 /* Update the spill cost arrays, considering that pseudo REG is live. */
1570 int n_refs = REG_N_REFS (reg);
1571 int r = reg_renumber[reg];
1574 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1575 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1578 SET_REGNO_REG_SET (&pseudos_counted, reg);
1583 spill_add_cost[r] += n_refs;
1585 nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1587 spill_cost[r + nregs] += n_refs;
1590 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1591 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1594 order_regs_for_reload (chain)
1595 struct insn_chain *chain;
1598 HARD_REG_SET used_by_pseudos;
1599 HARD_REG_SET used_by_pseudos2;
1601 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1603 memset (spill_cost, 0, sizeof spill_cost);
1604 memset (spill_add_cost, 0, sizeof spill_add_cost);
1606 /* Count number of uses of each hard reg by pseudo regs allocated to it
1607 and then order them by decreasing use. First exclude hard registers
1608 that are live in or across this insn. */
1610 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1611 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1612 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1613 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1615 /* Now find out which pseudos are allocated to it, and update
1617 CLEAR_REG_SET (&pseudos_counted);
1619 EXECUTE_IF_SET_IN_REG_SET
1620 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
1624 EXECUTE_IF_SET_IN_REG_SET
1625 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
1629 CLEAR_REG_SET (&pseudos_counted);
1632 /* Vector of reload-numbers showing the order in which the reloads should
1634 static short reload_order[MAX_RELOADS];
1636 /* This is used to keep track of the spill regs used in one insn. */
1637 static HARD_REG_SET used_spill_regs_local;
1639 /* We decided to spill hard register SPILLED, which has a size of
1640 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1641 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1642 update SPILL_COST/SPILL_ADD_COST. */
1645 count_spilled_pseudo (spilled, spilled_nregs, reg)
1646 int spilled, spilled_nregs, reg;
1648 int r = reg_renumber[reg];
1649 int nregs = HARD_REGNO_NREGS (r, PSEUDO_REGNO_MODE (reg));
1651 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1652 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1655 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1657 spill_add_cost[r] -= REG_N_REFS (reg);
1659 spill_cost[r + nregs] -= REG_N_REFS (reg);
1662 /* Find reload register to use for reload number ORDER. */
1665 find_reg (chain, order)
1666 struct insn_chain *chain;
1669 int rnum = reload_order[order];
1670 struct reload *rl = rld + rnum;
1671 int best_cost = INT_MAX;
1675 HARD_REG_SET not_usable;
1676 HARD_REG_SET used_by_other_reload;
1678 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1679 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1680 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1682 CLEAR_HARD_REG_SET (used_by_other_reload);
1683 for (k = 0; k < order; k++)
1685 int other = reload_order[k];
1687 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1688 for (j = 0; j < rld[other].nregs; j++)
1689 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1692 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1694 unsigned int regno = i;
1696 if (! TEST_HARD_REG_BIT (not_usable, regno)
1697 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1698 && HARD_REGNO_MODE_OK (regno, rl->mode))
1700 int this_cost = spill_cost[regno];
1702 unsigned int this_nregs = HARD_REGNO_NREGS (regno, rl->mode);
1704 for (j = 1; j < this_nregs; j++)
1706 this_cost += spill_add_cost[regno + j];
1707 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1708 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1713 if (rl->in && GET_CODE (rl->in) == REG && REGNO (rl->in) == regno)
1715 if (rl->out && GET_CODE (rl->out) == REG && REGNO (rl->out) == regno)
1717 if (this_cost < best_cost
1718 /* Among registers with equal cost, prefer caller-saved ones, or
1719 use REG_ALLOC_ORDER if it is defined. */
1720 || (this_cost == best_cost
1721 #ifdef REG_ALLOC_ORDER
1722 && (inv_reg_alloc_order[regno]
1723 < inv_reg_alloc_order[best_reg])
1725 && call_used_regs[regno]
1726 && ! call_used_regs[best_reg]
1731 best_cost = this_cost;
1739 fprintf (rtl_dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1741 rl->nregs = HARD_REGNO_NREGS (best_reg, rl->mode);
1742 rl->regno = best_reg;
1744 EXECUTE_IF_SET_IN_REG_SET
1745 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j,
1747 count_spilled_pseudo (best_reg, rl->nregs, j);
1750 EXECUTE_IF_SET_IN_REG_SET
1751 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j,
1753 count_spilled_pseudo (best_reg, rl->nregs, j);
1756 for (i = 0; i < rl->nregs; i++)
1758 if (spill_cost[best_reg + i] != 0
1759 || spill_add_cost[best_reg + i] != 0)
1761 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1766 /* Find more reload regs to satisfy the remaining need of an insn, which
1768 Do it by ascending class number, since otherwise a reg
1769 might be spilled for a big class and might fail to count
1770 for a smaller class even though it belongs to that class. */
1773 find_reload_regs (chain)
1774 struct insn_chain *chain;
1778 /* In order to be certain of getting the registers we need,
1779 we must sort the reloads into order of increasing register class.
1780 Then our grabbing of reload registers will parallel the process
1781 that provided the reload registers. */
1782 for (i = 0; i < chain->n_reloads; i++)
1784 /* Show whether this reload already has a hard reg. */
1785 if (chain->rld[i].reg_rtx)
1787 int regno = REGNO (chain->rld[i].reg_rtx);
1788 chain->rld[i].regno = regno;
1790 = HARD_REGNO_NREGS (regno, GET_MODE (chain->rld[i].reg_rtx));
1793 chain->rld[i].regno = -1;
1794 reload_order[i] = i;
1797 n_reloads = chain->n_reloads;
1798 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1800 CLEAR_HARD_REG_SET (used_spill_regs_local);
1803 fprintf (rtl_dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1805 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1807 /* Compute the order of preference for hard registers to spill. */
1809 order_regs_for_reload (chain);
1811 for (i = 0; i < n_reloads; i++)
1813 int r = reload_order[i];
1815 /* Ignore reloads that got marked inoperative. */
1816 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1817 && ! rld[r].optional
1818 && rld[r].regno == -1)
1819 if (! find_reg (chain, i))
1821 spill_failure (chain->insn, rld[r].class);
1827 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1828 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1830 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1834 select_reload_regs ()
1836 struct insn_chain *chain;
1838 /* Try to satisfy the needs for each insn. */
1839 for (chain = insns_need_reload; chain != 0;
1840 chain = chain->next_need_reload)
1841 find_reload_regs (chain);
1844 /* Delete all insns that were inserted by emit_caller_save_insns during
1847 delete_caller_save_insns ()
1849 struct insn_chain *c = reload_insn_chain;
1853 while (c != 0 && c->is_caller_save_insn)
1855 struct insn_chain *next = c->next;
1858 if (insn == BLOCK_HEAD (c->block))
1859 BLOCK_HEAD (c->block) = NEXT_INSN (insn);
1860 if (insn == BLOCK_END (c->block))
1861 BLOCK_END (c->block) = PREV_INSN (insn);
1862 if (c == reload_insn_chain)
1863 reload_insn_chain = next;
1865 if (NEXT_INSN (insn) != 0)
1866 PREV_INSN (NEXT_INSN (insn)) = PREV_INSN (insn);
1867 if (PREV_INSN (insn) != 0)
1868 NEXT_INSN (PREV_INSN (insn)) = NEXT_INSN (insn);
1871 next->prev = c->prev;
1873 c->prev->next = next;
1874 c->next = unused_insn_chains;
1875 unused_insn_chains = c;
1883 /* Handle the failure to find a register to spill.
1884 INSN should be one of the insns which needed this particular spill reg. */
1887 spill_failure (insn, class)
1889 enum reg_class class;
1891 static const char *const reg_class_names[] = REG_CLASS_NAMES;
1892 if (asm_noperands (PATTERN (insn)) >= 0)
1893 error_for_asm (insn, "Can't find a register in class `%s' while reloading `asm'.",
1894 reg_class_names[class]);
1897 error ("Unable to find a register to spill in class `%s'.",
1898 reg_class_names[class]);
1899 fatal_insn ("This is the insn:", insn);
1903 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
1904 data that is dead in INSN. */
1907 delete_dead_insn (insn)
1910 rtx prev = prev_real_insn (insn);
1913 /* If the previous insn sets a register that dies in our insn, delete it
1915 if (prev && GET_CODE (PATTERN (prev)) == SET
1916 && (prev_dest = SET_DEST (PATTERN (prev)), GET_CODE (prev_dest) == REG)
1917 && reg_mentioned_p (prev_dest, PATTERN (insn))
1918 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
1919 && ! side_effects_p (SET_SRC (PATTERN (prev))))
1920 delete_dead_insn (prev);
1922 PUT_CODE (insn, NOTE);
1923 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
1924 NOTE_SOURCE_FILE (insn) = 0;
1927 /* Modify the home of pseudo-reg I.
1928 The new home is present in reg_renumber[I].
1930 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
1931 or it may be -1, meaning there is none or it is not relevant.
1932 This is used so that all pseudos spilled from a given hard reg
1933 can share one stack slot. */
1936 alter_reg (i, from_reg)
1940 /* When outputting an inline function, this can happen
1941 for a reg that isn't actually used. */
1942 if (regno_reg_rtx[i] == 0)
1945 /* If the reg got changed to a MEM at rtl-generation time,
1947 if (GET_CODE (regno_reg_rtx[i]) != REG)
1950 /* Modify the reg-rtx to contain the new hard reg
1951 number or else to contain its pseudo reg number. */
1952 REGNO (regno_reg_rtx[i])
1953 = reg_renumber[i] >= 0 ? reg_renumber[i] : i;
1955 /* If we have a pseudo that is needed but has no hard reg or equivalent,
1956 allocate a stack slot for it. */
1958 if (reg_renumber[i] < 0
1959 && REG_N_REFS (i) > 0
1960 && reg_equiv_constant[i] == 0
1961 && reg_equiv_memory_loc[i] == 0)
1964 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
1965 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
1968 /* Each pseudo reg has an inherent size which comes from its own mode,
1969 and a total size which provides room for paradoxical subregs
1970 which refer to the pseudo reg in wider modes.
1972 We can use a slot already allocated if it provides both
1973 enough inherent space and enough total space.
1974 Otherwise, we allocate a new slot, making sure that it has no less
1975 inherent space, and no less total space, then the previous slot. */
1978 /* No known place to spill from => no slot to reuse. */
1979 x = assign_stack_local (GET_MODE (regno_reg_rtx[i]), total_size,
1980 inherent_size == total_size ? 0 : -1);
1981 if (BYTES_BIG_ENDIAN)
1982 /* Cancel the big-endian correction done in assign_stack_local.
1983 Get the address of the beginning of the slot.
1984 This is so we can do a big-endian correction unconditionally
1986 adjust = inherent_size - total_size;
1988 RTX_UNCHANGING_P (x) = RTX_UNCHANGING_P (regno_reg_rtx[i]);
1990 /* Nothing can alias this slot except this pseudo. */
1991 MEM_ALIAS_SET (x) = new_alias_set ();
1994 /* Reuse a stack slot if possible. */
1995 else if (spill_stack_slot[from_reg] != 0
1996 && spill_stack_slot_width[from_reg] >= total_size
1997 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
1999 x = spill_stack_slot[from_reg];
2001 /* Allocate a bigger slot. */
2004 /* Compute maximum size needed, both for inherent size
2005 and for total size. */
2006 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2009 if (spill_stack_slot[from_reg])
2011 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2013 mode = GET_MODE (spill_stack_slot[from_reg]);
2014 if (spill_stack_slot_width[from_reg] > total_size)
2015 total_size = spill_stack_slot_width[from_reg];
2018 /* Make a slot with that size. */
2019 x = assign_stack_local (mode, total_size,
2020 inherent_size == total_size ? 0 : -1);
2023 /* All pseudos mapped to this slot can alias each other. */
2024 if (spill_stack_slot[from_reg])
2025 MEM_ALIAS_SET (x) = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2027 MEM_ALIAS_SET (x) = new_alias_set ();
2029 if (BYTES_BIG_ENDIAN)
2031 /* Cancel the big-endian correction done in assign_stack_local.
2032 Get the address of the beginning of the slot.
2033 This is so we can do a big-endian correction unconditionally
2035 adjust = GET_MODE_SIZE (mode) - total_size;
2037 stack_slot = gen_rtx_MEM (mode_for_size (total_size
2040 plus_constant (XEXP (x, 0), adjust));
2043 spill_stack_slot[from_reg] = stack_slot;
2044 spill_stack_slot_width[from_reg] = total_size;
2047 /* On a big endian machine, the "address" of the slot
2048 is the address of the low part that fits its inherent mode. */
2049 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2050 adjust += (total_size - inherent_size);
2052 /* If we have any adjustment to make, or if the stack slot is the
2053 wrong mode, make a new stack slot. */
2054 if (adjust != 0 || GET_MODE (x) != GET_MODE (regno_reg_rtx[i]))
2056 rtx new = gen_rtx_MEM (GET_MODE (regno_reg_rtx[i]),
2057 plus_constant (XEXP (x, 0), adjust));
2059 MEM_COPY_ATTRIBUTES (new, x);
2063 /* Save the stack slot for later. */
2064 reg_equiv_memory_loc[i] = x;
2068 /* Mark the slots in regs_ever_live for the hard regs
2069 used by pseudo-reg number REGNO. */
2072 mark_home_live (regno)
2075 register int i, lim;
2077 i = reg_renumber[regno];
2080 lim = i + HARD_REGNO_NREGS (i, PSEUDO_REGNO_MODE (regno));
2082 regs_ever_live[i++] = 1;
2085 /* This function handles the tracking of elimination offsets around branches.
2087 X is a piece of RTL being scanned.
2089 INSN is the insn that it came from, if any.
2091 INITIAL_P is non-zero if we are to set the offset to be the initial
2092 offset and zero if we are setting the offset of the label to be the
2096 set_label_offsets (x, insn, initial_p)
2101 enum rtx_code code = GET_CODE (x);
2104 struct elim_table *p;
2109 if (LABEL_REF_NONLOCAL_P (x))
2114 /* ... fall through ... */
2117 /* If we know nothing about this label, set the desired offsets. Note
2118 that this sets the offset at a label to be the offset before a label
2119 if we don't know anything about the label. This is not correct for
2120 the label after a BARRIER, but is the best guess we can make. If
2121 we guessed wrong, we will suppress an elimination that might have
2122 been possible had we been able to guess correctly. */
2124 if (! offsets_known_at[CODE_LABEL_NUMBER (x)])
2126 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2127 offsets_at[CODE_LABEL_NUMBER (x)][i]
2128 = (initial_p ? reg_eliminate[i].initial_offset
2129 : reg_eliminate[i].offset);
2130 offsets_known_at[CODE_LABEL_NUMBER (x)] = 1;
2133 /* Otherwise, if this is the definition of a label and it is
2134 preceded by a BARRIER, set our offsets to the known offset of
2138 && (tem = prev_nonnote_insn (insn)) != 0
2139 && GET_CODE (tem) == BARRIER)
2140 set_offsets_for_label (insn);
2142 /* If neither of the above cases is true, compare each offset
2143 with those previously recorded and suppress any eliminations
2144 where the offsets disagree. */
2146 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2147 if (offsets_at[CODE_LABEL_NUMBER (x)][i]
2148 != (initial_p ? reg_eliminate[i].initial_offset
2149 : reg_eliminate[i].offset))
2150 reg_eliminate[i].can_eliminate = 0;
2155 set_label_offsets (PATTERN (insn), insn, initial_p);
2157 /* ... fall through ... */
2161 /* Any labels mentioned in REG_LABEL notes can be branched to indirectly
2162 and hence must have all eliminations at their initial offsets. */
2163 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2164 if (REG_NOTE_KIND (tem) == REG_LABEL)
2165 set_label_offsets (XEXP (tem, 0), insn, 1);
2171 /* Each of the labels in the parallel or address vector must be
2172 at their initial offsets. We want the first field for PARALLEL
2173 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2175 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2176 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2181 /* We only care about setting PC. If the source is not RETURN,
2182 IF_THEN_ELSE, or a label, disable any eliminations not at
2183 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2184 isn't one of those possibilities. For branches to a label,
2185 call ourselves recursively.
2187 Note that this can disable elimination unnecessarily when we have
2188 a non-local goto since it will look like a non-constant jump to
2189 someplace in the current function. This isn't a significant
2190 problem since such jumps will normally be when all elimination
2191 pairs are back to their initial offsets. */
2193 if (SET_DEST (x) != pc_rtx)
2196 switch (GET_CODE (SET_SRC (x)))
2203 set_label_offsets (XEXP (SET_SRC (x), 0), insn, initial_p);
2207 tem = XEXP (SET_SRC (x), 1);
2208 if (GET_CODE (tem) == LABEL_REF)
2209 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2210 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2213 tem = XEXP (SET_SRC (x), 2);
2214 if (GET_CODE (tem) == LABEL_REF)
2215 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2216 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2224 /* If we reach here, all eliminations must be at their initial
2225 offset because we are doing a jump to a variable address. */
2226 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2227 if (p->offset != p->initial_offset)
2228 p->can_eliminate = 0;
2236 /* Scan X and replace any eliminable registers (such as fp) with a
2237 replacement (such as sp), plus an offset.
2239 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2240 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2241 MEM, we are allowed to replace a sum of a register and the constant zero
2242 with the register, which we cannot do outside a MEM. In addition, we need
2243 to record the fact that a register is referenced outside a MEM.
2245 If INSN is an insn, it is the insn containing X. If we replace a REG
2246 in a SET_DEST with an equivalent MEM and INSN is non-zero, write a
2247 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2248 the REG is being modified.
2250 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2251 That's used when we eliminate in expressions stored in notes.
2252 This means, do not set ref_outside_mem even if the reference
2255 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2256 replacements done assuming all offsets are at their initial values. If
2257 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2258 encounter, return the actual location so that find_reloads will do
2259 the proper thing. */
2262 eliminate_regs (x, mem_mode, insn)
2264 enum machine_mode mem_mode;
2267 enum rtx_code code = GET_CODE (x);
2268 struct elim_table *ep;
2275 if (! current_function_decl)
2294 /* This is only for the benefit of the debugging backends, which call
2295 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2296 removed after CSE. */
2297 new = eliminate_regs (XEXP (x, 0), 0, insn);
2298 if (GET_CODE (new) == MEM)
2299 return XEXP (new, 0);
2305 /* First handle the case where we encounter a bare register that
2306 is eliminable. Replace it with a PLUS. */
2307 if (regno < FIRST_PSEUDO_REGISTER)
2309 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2311 if (ep->from_rtx == x && ep->can_eliminate)
2312 return plus_constant (ep->to_rtx, ep->previous_offset);
2315 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2316 && reg_equiv_constant[regno]
2317 && ! CONSTANT_P (reg_equiv_constant[regno]))
2318 return eliminate_regs (copy_rtx (reg_equiv_constant[regno]),
2322 /* You might think handling MINUS in a manner similar to PLUS is a
2323 good idea. It is not. It has been tried multiple times and every
2324 time the change has had to have been reverted.
2326 Other parts of reload know a PLUS is special (gen_reload for example)
2327 and require special code to handle code a reloaded PLUS operand.
2329 Also consider backends where the flags register is clobbered by a
2330 MINUS, but we can emit a PLUS that does not clobber flags (ia32,
2331 lea instruction comes to mind). If we try to reload a MINUS, we
2332 may kill the flags register that was holding a useful value.
2334 So, please before trying to handle MINUS, consider reload as a
2335 whole instead of this little section as well as the backend issues. */
2337 /* If this is the sum of an eliminable register and a constant, rework
2339 if (GET_CODE (XEXP (x, 0)) == REG
2340 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2341 && CONSTANT_P (XEXP (x, 1)))
2343 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2345 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2347 /* The only time we want to replace a PLUS with a REG (this
2348 occurs when the constant operand of the PLUS is the negative
2349 of the offset) is when we are inside a MEM. We won't want
2350 to do so at other times because that would change the
2351 structure of the insn in a way that reload can't handle.
2352 We special-case the commonest situation in
2353 eliminate_regs_in_insn, so just replace a PLUS with a
2354 PLUS here, unless inside a MEM. */
2355 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2356 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2359 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2360 plus_constant (XEXP (x, 1),
2361 ep->previous_offset));
2364 /* If the register is not eliminable, we are done since the other
2365 operand is a constant. */
2369 /* If this is part of an address, we want to bring any constant to the
2370 outermost PLUS. We will do this by doing register replacement in
2371 our operands and seeing if a constant shows up in one of them.
2373 Note that there is no risk of modifying the structure of the insn,
2374 since we only get called for its operands, thus we are either
2375 modifying the address inside a MEM, or something like an address
2376 operand of a load-address insn. */
2379 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2380 rtx new1 = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2382 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2384 /* If one side is a PLUS and the other side is a pseudo that
2385 didn't get a hard register but has a reg_equiv_constant,
2386 we must replace the constant here since it may no longer
2387 be in the position of any operand. */
2388 if (GET_CODE (new0) == PLUS && GET_CODE (new1) == REG
2389 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2390 && reg_renumber[REGNO (new1)] < 0
2391 && reg_equiv_constant != 0
2392 && reg_equiv_constant[REGNO (new1)] != 0)
2393 new1 = reg_equiv_constant[REGNO (new1)];
2394 else if (GET_CODE (new1) == PLUS && GET_CODE (new0) == REG
2395 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2396 && reg_renumber[REGNO (new0)] < 0
2397 && reg_equiv_constant[REGNO (new0)] != 0)
2398 new0 = reg_equiv_constant[REGNO (new0)];
2400 new = form_sum (new0, new1);
2402 /* As above, if we are not inside a MEM we do not want to
2403 turn a PLUS into something else. We might try to do so here
2404 for an addition of 0 if we aren't optimizing. */
2405 if (! mem_mode && GET_CODE (new) != PLUS)
2406 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2414 /* If this is the product of an eliminable register and a
2415 constant, apply the distribute law and move the constant out
2416 so that we have (plus (mult ..) ..). This is needed in order
2417 to keep load-address insns valid. This case is pathological.
2418 We ignore the possibility of overflow here. */
2419 if (GET_CODE (XEXP (x, 0)) == REG
2420 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2421 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2422 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2424 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2427 /* Refs inside notes don't count for this purpose. */
2428 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2429 || GET_CODE (insn) == INSN_LIST)))
2430 ep->ref_outside_mem = 1;
2433 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2434 ep->previous_offset * INTVAL (XEXP (x, 1)));
2437 /* ... fall through ... */
2441 /* See comments before PLUS about handling MINUS. */
2443 case DIV: case UDIV:
2444 case MOD: case UMOD:
2445 case AND: case IOR: case XOR:
2446 case ROTATERT: case ROTATE:
2447 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2449 case GE: case GT: case GEU: case GTU:
2450 case LE: case LT: case LEU: case LTU:
2452 rtx new0 = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2454 = XEXP (x, 1) ? eliminate_regs (XEXP (x, 1), mem_mode, insn) : 0;
2456 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2457 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2462 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2465 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2466 if (new != XEXP (x, 0))
2468 /* If this is a REG_DEAD note, it is not valid anymore.
2469 Using the eliminated version could result in creating a
2470 REG_DEAD note for the stack or frame pointer. */
2471 if (GET_MODE (x) == REG_DEAD)
2473 ? eliminate_regs (XEXP (x, 1), mem_mode, insn)
2476 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2480 /* ... fall through ... */
2483 /* Now do eliminations in the rest of the chain. If this was
2484 an EXPR_LIST, this might result in allocating more memory than is
2485 strictly needed, but it simplifies the code. */
2488 new = eliminate_regs (XEXP (x, 1), mem_mode, insn);
2489 if (new != XEXP (x, 1))
2490 return gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2498 case STRICT_LOW_PART:
2500 case SIGN_EXTEND: case ZERO_EXTEND:
2501 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2502 case FLOAT: case FIX:
2503 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2507 new = eliminate_regs (XEXP (x, 0), mem_mode, insn);
2508 if (new != XEXP (x, 0))
2509 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2513 /* Similar to above processing, but preserve SUBREG_BYTE.
2514 Convert (subreg (mem)) to (mem) if not paradoxical.
2515 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2516 pseudo didn't get a hard reg, we must replace this with the
2517 eliminated version of the memory location because push_reloads
2518 may do the replacement in certain circumstances. */
2519 if (GET_CODE (SUBREG_REG (x)) == REG
2520 && (GET_MODE_SIZE (GET_MODE (x))
2521 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2522 && reg_equiv_memory_loc != 0
2523 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2525 new = SUBREG_REG (x);
2528 new = eliminate_regs (SUBREG_REG (x), mem_mode, insn);
2530 if (new != SUBREG_REG (x))
2532 int x_size = GET_MODE_SIZE (GET_MODE (x));
2533 int new_size = GET_MODE_SIZE (GET_MODE (new));
2535 if (GET_CODE (new) == MEM
2536 && ((x_size < new_size
2537 #ifdef WORD_REGISTER_OPERATIONS
2538 /* On these machines, combine can create rtl of the form
2539 (set (subreg:m1 (reg:m2 R) 0) ...)
2540 where m1 < m2, and expects something interesting to
2541 happen to the entire word. Moreover, it will use the
2542 (reg:m2 R) later, expecting all bits to be preserved.
2543 So if the number of words is the same, preserve the
2544 subreg so that push_reloads can see it. */
2545 && ! ((x_size-1)/UNITS_PER_WORD == (new_size-1)/UNITS_PER_WORD)
2548 || (x_size == new_size))
2551 int offset = SUBREG_BYTE (x);
2552 enum machine_mode mode = GET_MODE (x);
2554 PUT_MODE (new, mode);
2555 XEXP (new, 0) = plus_constant (XEXP (new, 0), offset);
2559 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2565 /* This is only for the benefit of the debugging backends, which call
2566 eliminate_regs on DECL_RTL; any ADDRESSOFs in the actual insns are
2567 removed after CSE. */
2568 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2569 return eliminate_regs (XEXP (XEXP (x, 0), 0), 0, insn);
2571 /* Our only special processing is to pass the mode of the MEM to our
2572 recursive call and copy the flags. While we are here, handle this
2573 case more efficiently. */
2574 new = eliminate_regs (XEXP (x, 0), GET_MODE (x), insn);
2575 if (new != XEXP (x, 0))
2577 new = gen_rtx_MEM (GET_MODE (x), new);
2578 MEM_COPY_ATTRIBUTES (new, x);
2585 /* Handle insn_list USE that a call to a pure function may generate. */
2586 new = eliminate_regs (XEXP (x, 0), 0, insn);
2587 if (new != XEXP (x, 0))
2588 return gen_rtx_USE (GET_MODE (x), new);
2600 /* Process each of our operands recursively. If any have changed, make a
2602 fmt = GET_RTX_FORMAT (code);
2603 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2607 new = eliminate_regs (XEXP (x, i), mem_mode, insn);
2608 if (new != XEXP (x, i) && ! copied)
2610 rtx new_x = rtx_alloc (code);
2612 (sizeof (*new_x) - sizeof (new_x->fld)
2613 + sizeof (new_x->fld[0]) * GET_RTX_LENGTH (code)));
2619 else if (*fmt == 'E')
2622 for (j = 0; j < XVECLEN (x, i); j++)
2624 new = eliminate_regs (XVECEXP (x, i, j), mem_mode, insn);
2625 if (new != XVECEXP (x, i, j) && ! copied_vec)
2627 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2631 rtx new_x = rtx_alloc (code);
2633 (sizeof (*new_x) - sizeof (new_x->fld)
2634 + (sizeof (new_x->fld[0])
2635 * GET_RTX_LENGTH (code))));
2639 XVEC (x, i) = new_v;
2642 XVECEXP (x, i, j) = new;
2650 /* Scan rtx X for modifications of elimination target registers. Update
2651 the table of eliminables to reflect the changed state. MEM_MODE is
2652 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2655 elimination_effects (x, mem_mode)
2657 enum machine_mode mem_mode;
2660 enum rtx_code code = GET_CODE (x);
2661 struct elim_table *ep;
2687 /* First handle the case where we encounter a bare register that
2688 is eliminable. Replace it with a PLUS. */
2689 if (regno < FIRST_PSEUDO_REGISTER)
2691 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2693 if (ep->from_rtx == x && ep->can_eliminate)
2696 ep->ref_outside_mem = 1;
2701 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2702 && reg_equiv_constant[regno]
2703 && ! CONSTANT_P (reg_equiv_constant[regno]))
2704 elimination_effects (reg_equiv_constant[regno], mem_mode);
2713 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2714 if (ep->to_rtx == XEXP (x, 0))
2716 int size = GET_MODE_SIZE (mem_mode);
2718 /* If more bytes than MEM_MODE are pushed, account for them. */
2719 #ifdef PUSH_ROUNDING
2720 if (ep->to_rtx == stack_pointer_rtx)
2721 size = PUSH_ROUNDING (size);
2723 if (code == PRE_DEC || code == POST_DEC)
2725 else if (code == PRE_INC || code == POST_INC)
2727 else if ((code == PRE_MODIFY || code == POST_MODIFY)
2728 && GET_CODE (XEXP (x, 1)) == PLUS
2729 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2730 && CONSTANT_P (XEXP (XEXP (x, 1), 1)))
2731 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2734 /* These two aren't unary operators. */
2735 if (code == POST_MODIFY || code == PRE_MODIFY)
2738 /* Fall through to generic unary operation case. */
2739 case STRICT_LOW_PART:
2741 case SIGN_EXTEND: case ZERO_EXTEND:
2742 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2743 case FLOAT: case FIX:
2744 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2748 elimination_effects (XEXP (x, 0), mem_mode);
2752 if (GET_CODE (SUBREG_REG (x)) == REG
2753 && (GET_MODE_SIZE (GET_MODE (x))
2754 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2755 && reg_equiv_memory_loc != 0
2756 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2759 elimination_effects (SUBREG_REG (x), mem_mode);
2763 /* If using a register that is the source of an eliminate we still
2764 think can be performed, note it cannot be performed since we don't
2765 know how this register is used. */
2766 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2767 if (ep->from_rtx == XEXP (x, 0))
2768 ep->can_eliminate = 0;
2770 elimination_effects (XEXP (x, 0), mem_mode);
2774 /* If clobbering a register that is the replacement register for an
2775 elimination we still think can be performed, note that it cannot
2776 be performed. Otherwise, we need not be concerned about it. */
2777 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2778 if (ep->to_rtx == XEXP (x, 0))
2779 ep->can_eliminate = 0;
2781 elimination_effects (XEXP (x, 0), mem_mode);
2785 /* Check for setting a register that we know about. */
2786 if (GET_CODE (SET_DEST (x)) == REG)
2788 /* See if this is setting the replacement register for an
2791 If DEST is the hard frame pointer, we do nothing because we
2792 assume that all assignments to the frame pointer are for
2793 non-local gotos and are being done at a time when they are valid
2794 and do not disturb anything else. Some machines want to
2795 eliminate a fake argument pointer (or even a fake frame pointer)
2796 with either the real frame or the stack pointer. Assignments to
2797 the hard frame pointer must not prevent this elimination. */
2799 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2801 if (ep->to_rtx == SET_DEST (x)
2802 && SET_DEST (x) != hard_frame_pointer_rtx)
2804 /* If it is being incremented, adjust the offset. Otherwise,
2805 this elimination can't be done. */
2806 rtx src = SET_SRC (x);
2808 if (GET_CODE (src) == PLUS
2809 && XEXP (src, 0) == SET_DEST (x)
2810 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2811 ep->offset -= INTVAL (XEXP (src, 1));
2813 ep->can_eliminate = 0;
2817 elimination_effects (SET_DEST (x), 0);
2818 elimination_effects (SET_SRC (x), 0);
2822 if (GET_CODE (XEXP (x, 0)) == ADDRESSOF)
2825 /* Our only special processing is to pass the mode of the MEM to our
2827 elimination_effects (XEXP (x, 0), GET_MODE (x));
2834 fmt = GET_RTX_FORMAT (code);
2835 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2838 elimination_effects (XEXP (x, i), mem_mode);
2839 else if (*fmt == 'E')
2840 for (j = 0; j < XVECLEN (x, i); j++)
2841 elimination_effects (XVECEXP (x, i, j), mem_mode);
2845 /* Descend through rtx X and verify that no references to eliminable registers
2846 remain. If any do remain, mark the involved register as not
2850 check_eliminable_occurrences (x)
2860 code = GET_CODE (x);
2862 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
2864 struct elim_table *ep;
2866 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2867 if (ep->from_rtx == x && ep->can_eliminate)
2868 ep->can_eliminate = 0;
2872 fmt = GET_RTX_FORMAT (code);
2873 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2876 check_eliminable_occurrences (XEXP (x, i));
2877 else if (*fmt == 'E')
2880 for (j = 0; j < XVECLEN (x, i); j++)
2881 check_eliminable_occurrences (XVECEXP (x, i, j));
2886 /* Scan INSN and eliminate all eliminable registers in it.
2888 If REPLACE is nonzero, do the replacement destructively. Also
2889 delete the insn as dead it if it is setting an eliminable register.
2891 If REPLACE is zero, do all our allocations in reload_obstack.
2893 If no eliminations were done and this insn doesn't require any elimination
2894 processing (these are not identical conditions: it might be updating sp,
2895 but not referencing fp; this needs to be seen during reload_as_needed so
2896 that the offset between fp and sp can be taken into consideration), zero
2897 is returned. Otherwise, 1 is returned. */
2900 eliminate_regs_in_insn (insn, replace)
2904 int icode = recog_memoized (insn);
2905 rtx old_body = PATTERN (insn);
2906 int insn_is_asm = asm_noperands (old_body) >= 0;
2907 rtx old_set = single_set (insn);
2911 rtx substed_operand[MAX_RECOG_OPERANDS];
2912 rtx orig_operand[MAX_RECOG_OPERANDS];
2913 struct elim_table *ep;
2915 if (! insn_is_asm && icode < 0)
2917 if (GET_CODE (PATTERN (insn)) == USE
2918 || GET_CODE (PATTERN (insn)) == CLOBBER
2919 || GET_CODE (PATTERN (insn)) == ADDR_VEC
2920 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
2921 || GET_CODE (PATTERN (insn)) == ASM_INPUT)
2926 if (old_set != 0 && GET_CODE (SET_DEST (old_set)) == REG
2927 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
2929 /* Check for setting an eliminable register. */
2930 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2931 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
2933 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
2934 /* If this is setting the frame pointer register to the
2935 hardware frame pointer register and this is an elimination
2936 that will be done (tested above), this insn is really
2937 adjusting the frame pointer downward to compensate for
2938 the adjustment done before a nonlocal goto. */
2939 if (ep->from == FRAME_POINTER_REGNUM
2940 && ep->to == HARD_FRAME_POINTER_REGNUM)
2942 rtx src = SET_SRC (old_set);
2943 int offset = 0, ok = 0;
2944 rtx prev_insn, prev_set;
2946 if (src == ep->to_rtx)
2948 else if (GET_CODE (src) == PLUS
2949 && GET_CODE (XEXP (src, 0)) == CONST_INT
2950 && XEXP (src, 1) == ep->to_rtx)
2951 offset = INTVAL (XEXP (src, 0)), ok = 1;
2952 else if (GET_CODE (src) == PLUS
2953 && GET_CODE (XEXP (src, 1)) == CONST_INT
2954 && XEXP (src, 0) == ep->to_rtx)
2955 offset = INTVAL (XEXP (src, 1)), ok = 1;
2956 else if ((prev_insn = prev_nonnote_insn (insn)) != 0
2957 && (prev_set = single_set (prev_insn)) != 0
2958 && rtx_equal_p (SET_DEST (prev_set), src))
2960 src = SET_SRC (prev_set);
2961 if (src == ep->to_rtx)
2963 else if (GET_CODE (src) == PLUS
2964 && GET_CODE (XEXP (src, 0)) == CONST_INT
2965 && XEXP (src, 1) == ep->to_rtx)
2966 offset = INTVAL (XEXP (src, 0)), ok = 1;
2967 else if (GET_CODE (src) == PLUS
2968 && GET_CODE (XEXP (src, 1)) == CONST_INT
2969 && XEXP (src, 0) == ep->to_rtx)
2970 offset = INTVAL (XEXP (src, 1)), ok = 1;
2978 = plus_constant (ep->to_rtx, offset - ep->offset);
2980 /* First see if this insn remains valid when we
2981 make the change. If not, keep the INSN_CODE
2982 the same and let reload fit it up. */
2983 validate_change (insn, &SET_SRC (old_set), src, 1);
2984 validate_change (insn, &SET_DEST (old_set),
2986 if (! apply_change_group ())
2988 SET_SRC (old_set) = src;
2989 SET_DEST (old_set) = ep->to_rtx;
2999 /* In this case this insn isn't serving a useful purpose. We
3000 will delete it in reload_as_needed once we know that this
3001 elimination is, in fact, being done.
3003 If REPLACE isn't set, we can't delete this insn, but needn't
3004 process it since it won't be used unless something changes. */
3007 delete_dead_insn (insn);
3015 /* We allow one special case which happens to work on all machines we
3016 currently support: a single set with the source being a PLUS of an
3017 eliminable register and a constant. */
3019 && GET_CODE (SET_DEST (old_set)) == REG
3020 && GET_CODE (SET_SRC (old_set)) == PLUS
3021 && GET_CODE (XEXP (SET_SRC (old_set), 0)) == REG
3022 && GET_CODE (XEXP (SET_SRC (old_set), 1)) == CONST_INT
3023 && REGNO (XEXP (SET_SRC (old_set), 0)) < FIRST_PSEUDO_REGISTER)
3025 rtx reg = XEXP (SET_SRC (old_set), 0);
3026 int offset = INTVAL (XEXP (SET_SRC (old_set), 1));
3028 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3029 if (ep->from_rtx == reg && ep->can_eliminate)
3031 offset += ep->offset;
3036 /* We assume here that if we need a PARALLEL with
3037 CLOBBERs for this assignment, we can do with the
3038 MATCH_SCRATCHes that add_clobbers allocates.
3039 There's not much we can do if that doesn't work. */
3040 PATTERN (insn) = gen_rtx_SET (VOIDmode,
3044 INSN_CODE (insn) = recog (PATTERN (insn), insn, &num_clobbers);
3047 rtvec vec = rtvec_alloc (num_clobbers + 1);
3049 vec->elem[0] = PATTERN (insn);
3050 PATTERN (insn) = gen_rtx_PARALLEL (VOIDmode, vec);
3051 add_clobbers (PATTERN (insn), INSN_CODE (insn));
3053 if (INSN_CODE (insn) < 0)
3058 new_body = old_body;
3061 new_body = copy_insn (old_body);
3062 if (REG_NOTES (insn))
3063 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3065 PATTERN (insn) = new_body;
3066 old_set = single_set (insn);
3068 XEXP (SET_SRC (old_set), 0) = ep->to_rtx;
3069 XEXP (SET_SRC (old_set), 1) = GEN_INT (offset);
3072 /* This can't have an effect on elimination offsets, so skip right
3078 /* Determine the effects of this insn on elimination offsets. */
3079 elimination_effects (old_body, 0);
3081 /* Eliminate all eliminable registers occurring in operands that
3082 can be handled by reload. */
3083 extract_insn (insn);
3085 for (i = 0; i < recog_data.n_operands; i++)
3087 orig_operand[i] = recog_data.operand[i];
3088 substed_operand[i] = recog_data.operand[i];
3090 /* For an asm statement, every operand is eliminable. */
3091 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3093 /* Check for setting a register that we know about. */
3094 if (recog_data.operand_type[i] != OP_IN
3095 && GET_CODE (orig_operand[i]) == REG)
3097 /* If we are assigning to a register that can be eliminated, it
3098 must be as part of a PARALLEL, since the code above handles
3099 single SETs. We must indicate that we can no longer
3100 eliminate this reg. */
3101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3103 if (ep->from_rtx == orig_operand[i] && ep->can_eliminate)
3104 ep->can_eliminate = 0;
3107 substed_operand[i] = eliminate_regs (recog_data.operand[i], 0,
3108 replace ? insn : NULL_RTX);
3109 if (substed_operand[i] != orig_operand[i])
3110 val = any_changes = 1;
3111 /* Terminate the search in check_eliminable_occurrences at
3113 *recog_data.operand_loc[i] = 0;
3115 /* If an output operand changed from a REG to a MEM and INSN is an
3116 insn, write a CLOBBER insn. */
3117 if (recog_data.operand_type[i] != OP_IN
3118 && GET_CODE (orig_operand[i]) == REG
3119 && GET_CODE (substed_operand[i]) == MEM
3121 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3126 for (i = 0; i < recog_data.n_dups; i++)
3127 *recog_data.dup_loc[i]
3128 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3130 /* If any eliminable remain, they aren't eliminable anymore. */
3131 check_eliminable_occurrences (old_body);
3133 /* Substitute the operands; the new values are in the substed_operand
3135 for (i = 0; i < recog_data.n_operands; i++)
3136 *recog_data.operand_loc[i] = substed_operand[i];
3137 for (i = 0; i < recog_data.n_dups; i++)
3138 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3140 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3141 re-recognize the insn. We do this in case we had a simple addition
3142 but now can do this as a load-address. This saves an insn in this
3144 If re-recognition fails, the old insn code number will still be used,
3145 and some register operands may have changed into PLUS expressions.
3146 These will be handled by find_reloads by loading them into a register
3151 /* If we aren't replacing things permanently and we changed something,
3152 make another copy to ensure that all the RTL is new. Otherwise
3153 things can go wrong if find_reload swaps commutative operands
3154 and one is inside RTL that has been copied while the other is not. */
3155 new_body = old_body;
3158 new_body = copy_insn (old_body);
3159 if (REG_NOTES (insn))
3160 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3162 PATTERN (insn) = new_body;
3164 /* If we had a move insn but now we don't, rerecognize it. This will
3165 cause spurious re-recognition if the old move had a PARALLEL since
3166 the new one still will, but we can't call single_set without
3167 having put NEW_BODY into the insn and the re-recognition won't
3168 hurt in this rare case. */
3169 /* ??? Why this huge if statement - why don't we just rerecognize the
3173 && ((GET_CODE (SET_SRC (old_set)) == REG
3174 && (GET_CODE (new_body) != SET
3175 || GET_CODE (SET_SRC (new_body)) != REG))
3176 /* If this was a load from or store to memory, compare
3177 the MEM in recog_data.operand to the one in the insn.
3178 If they are not equal, then rerecognize the insn. */
3180 && ((GET_CODE (SET_SRC (old_set)) == MEM
3181 && SET_SRC (old_set) != recog_data.operand[1])
3182 || (GET_CODE (SET_DEST (old_set)) == MEM
3183 && SET_DEST (old_set) != recog_data.operand[0])))
3184 /* If this was an add insn before, rerecognize. */
3185 || GET_CODE (SET_SRC (old_set)) == PLUS))
3187 int new_icode = recog (PATTERN (insn), insn, 0);
3189 INSN_CODE (insn) = icode;
3193 /* Restore the old body. If there were any changes to it, we made a copy
3194 of it while the changes were still in place, so we'll correctly return
3195 a modified insn below. */
3198 /* Restore the old body. */
3199 for (i = 0; i < recog_data.n_operands; i++)
3200 *recog_data.operand_loc[i] = orig_operand[i];
3201 for (i = 0; i < recog_data.n_dups; i++)
3202 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3205 /* Update all elimination pairs to reflect the status after the current
3206 insn. The changes we make were determined by the earlier call to
3207 elimination_effects.
3209 We also detect a cases where register elimination cannot be done,
3210 namely, if a register would be both changed and referenced outside a MEM
3211 in the resulting insn since such an insn is often undefined and, even if
3212 not, we cannot know what meaning will be given to it. Note that it is
3213 valid to have a register used in an address in an insn that changes it
3214 (presumably with a pre- or post-increment or decrement).
3216 If anything changes, return nonzero. */
3218 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3220 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3221 ep->can_eliminate = 0;
3223 ep->ref_outside_mem = 0;
3225 if (ep->previous_offset != ep->offset)
3230 /* If we changed something, perform elimination in REG_NOTES. This is
3231 needed even when REPLACE is zero because a REG_DEAD note might refer
3232 to a register that we eliminate and could cause a different number
3233 of spill registers to be needed in the final reload pass than in
3235 if (val && REG_NOTES (insn) != 0)
3236 REG_NOTES (insn) = eliminate_regs (REG_NOTES (insn), 0, REG_NOTES (insn));
3241 /* Loop through all elimination pairs.
3242 Recalculate the number not at initial offset.
3244 Compute the maximum offset (minimum offset if the stack does not
3245 grow downward) for each elimination pair. */
3248 update_eliminable_offsets ()
3250 struct elim_table *ep;
3252 num_not_at_initial_offset = 0;
3253 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3255 ep->previous_offset = ep->offset;
3256 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3257 num_not_at_initial_offset++;
3261 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3262 replacement we currently believe is valid, mark it as not eliminable if X
3263 modifies DEST in any way other than by adding a constant integer to it.
3265 If DEST is the frame pointer, we do nothing because we assume that
3266 all assignments to the hard frame pointer are nonlocal gotos and are being
3267 done at a time when they are valid and do not disturb anything else.
3268 Some machines want to eliminate a fake argument pointer with either the
3269 frame or stack pointer. Assignments to the hard frame pointer must not
3270 prevent this elimination.
3272 Called via note_stores from reload before starting its passes to scan
3273 the insns of the function. */
3276 mark_not_eliminable (dest, x, data)
3279 void *data ATTRIBUTE_UNUSED;
3281 register unsigned int i;
3283 /* A SUBREG of a hard register here is just changing its mode. We should
3284 not see a SUBREG of an eliminable hard register, but check just in
3286 if (GET_CODE (dest) == SUBREG)
3287 dest = SUBREG_REG (dest);
3289 if (dest == hard_frame_pointer_rtx)
3292 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3293 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3294 && (GET_CODE (x) != SET
3295 || GET_CODE (SET_SRC (x)) != PLUS
3296 || XEXP (SET_SRC (x), 0) != dest
3297 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3299 reg_eliminate[i].can_eliminate_previous
3300 = reg_eliminate[i].can_eliminate = 0;
3305 /* Verify that the initial elimination offsets did not change since the
3306 last call to set_initial_elim_offsets. This is used to catch cases
3307 where something illegal happened during reload_as_needed that could
3308 cause incorrect code to be generated if we did not check for it. */
3311 verify_initial_elim_offsets ()
3315 #ifdef ELIMINABLE_REGS
3316 struct elim_table *ep;
3318 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3320 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3321 if (t != ep->initial_offset)
3325 INITIAL_FRAME_POINTER_OFFSET (t);
3326 if (t != reg_eliminate[0].initial_offset)
3331 /* Reset all offsets on eliminable registers to their initial values. */
3334 set_initial_elim_offsets ()
3336 struct elim_table *ep = reg_eliminate;
3338 #ifdef ELIMINABLE_REGS
3339 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3341 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3342 ep->previous_offset = ep->offset = ep->initial_offset;
3345 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3346 ep->previous_offset = ep->offset = ep->initial_offset;
3349 num_not_at_initial_offset = 0;
3352 /* Initialize the known label offsets.
3353 Set a known offset for each forced label to be at the initial offset
3354 of each elimination. We do this because we assume that all
3355 computed jumps occur from a location where each elimination is
3356 at its initial offset.
3357 For all other labels, show that we don't know the offsets. */
3360 set_initial_label_offsets ()
3363 memset ((char *) &offsets_known_at[get_first_label_num ()], 0, num_labels);
3365 for (x = forced_labels; x; x = XEXP (x, 1))
3367 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3370 /* Set all elimination offsets to the known values for the code label given
3374 set_offsets_for_label (insn)
3378 int label_nr = CODE_LABEL_NUMBER (insn);
3379 struct elim_table *ep;
3381 num_not_at_initial_offset = 0;
3382 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3384 ep->offset = ep->previous_offset = offsets_at[label_nr][i];
3385 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3386 num_not_at_initial_offset++;
3390 /* See if anything that happened changes which eliminations are valid.
3391 For example, on the Sparc, whether or not the frame pointer can
3392 be eliminated can depend on what registers have been used. We need
3393 not check some conditions again (such as flag_omit_frame_pointer)
3394 since they can't have changed. */
3397 update_eliminables (pset)
3400 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3401 int previous_frame_pointer_needed = frame_pointer_needed;
3403 struct elim_table *ep;
3405 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3406 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3407 #ifdef ELIMINABLE_REGS
3408 || ! CAN_ELIMINATE (ep->from, ep->to)
3411 ep->can_eliminate = 0;
3413 /* Look for the case where we have discovered that we can't replace
3414 register A with register B and that means that we will now be
3415 trying to replace register A with register C. This means we can
3416 no longer replace register C with register B and we need to disable
3417 such an elimination, if it exists. This occurs often with A == ap,
3418 B == sp, and C == fp. */
3420 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3422 struct elim_table *op;
3423 register int new_to = -1;
3425 if (! ep->can_eliminate && ep->can_eliminate_previous)
3427 /* Find the current elimination for ep->from, if there is a
3429 for (op = reg_eliminate;
3430 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3431 if (op->from == ep->from && op->can_eliminate)
3437 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3439 for (op = reg_eliminate;
3440 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3441 if (op->from == new_to && op->to == ep->to)
3442 op->can_eliminate = 0;
3446 /* See if any registers that we thought we could eliminate the previous
3447 time are no longer eliminable. If so, something has changed and we
3448 must spill the register. Also, recompute the number of eliminable
3449 registers and see if the frame pointer is needed; it is if there is
3450 no elimination of the frame pointer that we can perform. */
3452 frame_pointer_needed = 1;
3453 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3455 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3456 && ep->to != HARD_FRAME_POINTER_REGNUM)
3457 frame_pointer_needed = 0;
3459 if (! ep->can_eliminate && ep->can_eliminate_previous)
3461 ep->can_eliminate_previous = 0;
3462 SET_HARD_REG_BIT (*pset, ep->from);
3467 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3468 /* If we didn't need a frame pointer last time, but we do now, spill
3469 the hard frame pointer. */
3470 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3471 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3475 /* Initialize the table of registers to eliminate. */
3480 struct elim_table *ep;
3481 #ifdef ELIMINABLE_REGS
3482 struct elim_table_1 *ep1;
3486 reg_eliminate = (struct elim_table *)
3487 xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3489 /* Does this function require a frame pointer? */
3491 frame_pointer_needed = (! flag_omit_frame_pointer
3492 #ifdef EXIT_IGNORE_STACK
3493 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3494 and restore sp for alloca. So we can't eliminate
3495 the frame pointer in that case. At some point,
3496 we should improve this by emitting the
3497 sp-adjusting insns for this case. */
3498 || (current_function_calls_alloca
3499 && EXIT_IGNORE_STACK)
3501 || FRAME_POINTER_REQUIRED);
3505 #ifdef ELIMINABLE_REGS
3506 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3507 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3509 ep->from = ep1->from;
3511 ep->can_eliminate = ep->can_eliminate_previous
3512 = (CAN_ELIMINATE (ep->from, ep->to)
3513 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3516 reg_eliminate[0].from = reg_eliminate_1[0].from;
3517 reg_eliminate[0].to = reg_eliminate_1[0].to;
3518 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3519 = ! frame_pointer_needed;
3522 /* Count the number of eliminable registers and build the FROM and TO
3523 REG rtx's. Note that code in gen_rtx will cause, e.g.,
3524 gen_rtx (REG, Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3525 We depend on this. */
3526 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3528 num_eliminable += ep->can_eliminate;
3529 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3530 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3534 /* Kick all pseudos out of hard register REGNO.
3536 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3537 because we found we can't eliminate some register. In the case, no pseudos
3538 are allowed to be in the register, even if they are only in a block that
3539 doesn't require spill registers, unlike the case when we are spilling this
3540 hard reg to produce another spill register.
3542 Return nonzero if any pseudos needed to be kicked out. */
3545 spill_hard_reg (regno, cant_eliminate)
3553 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3554 regs_ever_live[regno] = 1;
3557 /* Spill every pseudo reg that was allocated to this reg
3558 or to something that overlaps this reg. */
3560 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3561 if (reg_renumber[i] >= 0
3562 && (unsigned int) reg_renumber[i] <= regno
3563 && ((unsigned int) reg_renumber[i]
3564 + HARD_REGNO_NREGS ((unsigned int) reg_renumber[i],
3565 PSEUDO_REGNO_MODE (i))
3567 SET_REGNO_REG_SET (&spilled_pseudos, i);
3570 /* I'm getting weird preprocessor errors if I use IOR_HARD_REG_SET
3571 from within EXECUTE_IF_SET_IN_REG_SET. Hence this awkwardness. */
3574 ior_hard_reg_set (set1, set2)
3575 HARD_REG_SET *set1, *set2;
3577 IOR_HARD_REG_SET (*set1, *set2);
3580 /* After find_reload_regs has been run for all insn that need reloads,
3581 and/or spill_hard_regs was called, this function is used to actually
3582 spill pseudo registers and try to reallocate them. It also sets up the
3583 spill_regs array for use by choose_reload_regs. */
3586 finish_spills (global)
3589 struct insn_chain *chain;
3590 int something_changed = 0;
3593 /* Build the spill_regs array for the function. */
3594 /* If there are some registers still to eliminate and one of the spill regs
3595 wasn't ever used before, additional stack space may have to be
3596 allocated to store this register. Thus, we may have changed the offset
3597 between the stack and frame pointers, so mark that something has changed.
3599 One might think that we need only set VAL to 1 if this is a call-used
3600 register. However, the set of registers that must be saved by the
3601 prologue is not identical to the call-used set. For example, the
3602 register used by the call insn for the return PC is a call-used register,
3603 but must be saved by the prologue. */
3606 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3607 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3609 spill_reg_order[i] = n_spills;
3610 spill_regs[n_spills++] = i;
3611 if (num_eliminable && ! regs_ever_live[i])
3612 something_changed = 1;
3613 regs_ever_live[i] = 1;
3616 spill_reg_order[i] = -1;
3618 EXECUTE_IF_SET_IN_REG_SET
3619 (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i,
3621 /* Record the current hard register the pseudo is allocated to in
3622 pseudo_previous_regs so we avoid reallocating it to the same
3623 hard reg in a later pass. */
3624 if (reg_renumber[i] < 0)
3627 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3628 /* Mark it as no longer having a hard register home. */
3629 reg_renumber[i] = -1;
3630 /* We will need to scan everything again. */
3631 something_changed = 1;
3634 /* Retry global register allocation if possible. */
3637 memset ((char *) pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3638 /* For every insn that needs reloads, set the registers used as spill
3639 regs in pseudo_forbidden_regs for every pseudo live across the
3641 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3643 EXECUTE_IF_SET_IN_REG_SET
3644 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i,
3646 ior_hard_reg_set (pseudo_forbidden_regs + i,
3647 &chain->used_spill_regs);
3649 EXECUTE_IF_SET_IN_REG_SET
3650 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i,
3652 ior_hard_reg_set (pseudo_forbidden_regs + i,
3653 &chain->used_spill_regs);
3657 /* Retry allocating the spilled pseudos. For each reg, merge the
3658 various reg sets that indicate which hard regs can't be used,
3659 and call retry_global_alloc.
3660 We change spill_pseudos here to only contain pseudos that did not
3661 get a new hard register. */
3662 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3663 if (reg_old_renumber[i] != reg_renumber[i])
3665 HARD_REG_SET forbidden;
3666 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3667 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3668 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3669 retry_global_alloc (i, forbidden);
3670 if (reg_renumber[i] >= 0)
3671 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3675 /* Fix up the register information in the insn chain.
3676 This involves deleting those of the spilled pseudos which did not get
3677 a new hard register home from the live_{before,after} sets. */
3678 for (chain = reload_insn_chain; chain; chain = chain->next)
3680 HARD_REG_SET used_by_pseudos;
3681 HARD_REG_SET used_by_pseudos2;
3683 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3684 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3686 /* Mark any unallocated hard regs as available for spills. That
3687 makes inheritance work somewhat better. */
3688 if (chain->need_reload)
3690 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3691 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3692 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3694 /* Save the old value for the sanity test below. */
3695 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3697 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3698 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3699 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3700 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3702 /* Make sure we only enlarge the set. */
3703 GO_IF_HARD_REG_SUBSET (used_by_pseudos2, chain->used_spill_regs, ok);
3709 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3710 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3712 int regno = reg_renumber[i];
3713 if (reg_old_renumber[i] == regno)
3716 alter_reg (i, reg_old_renumber[i]);
3717 reg_old_renumber[i] = regno;
3721 fprintf (rtl_dump_file, " Register %d now on stack.\n\n", i);
3723 fprintf (rtl_dump_file, " Register %d now in %d.\n\n",
3724 i, reg_renumber[i]);
3728 return something_changed;
3731 /* Find all paradoxical subregs within X and update reg_max_ref_width.
3732 Also mark any hard registers used to store user variables as
3733 forbidden from being used for spill registers. */
3736 scan_paradoxical_subregs (x)
3740 register const char *fmt;
3741 register enum rtx_code code = GET_CODE (x);
3747 if (SMALL_REGISTER_CLASSES && REGNO (x) < FIRST_PSEUDO_REGISTER
3748 && REG_USERVAR_P (x))
3749 SET_HARD_REG_BIT (bad_spill_regs_global, REGNO (x));
3765 if (GET_CODE (SUBREG_REG (x)) == REG
3766 && GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
3767 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3768 = GET_MODE_SIZE (GET_MODE (x));
3775 fmt = GET_RTX_FORMAT (code);
3776 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3779 scan_paradoxical_subregs (XEXP (x, i));
3780 else if (fmt[i] == 'E')
3783 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3784 scan_paradoxical_subregs (XVECEXP (x, i, j));
3789 /* Reload pseudo-registers into hard regs around each insn as needed.
3790 Additional register load insns are output before the insn that needs it
3791 and perhaps store insns after insns that modify the reloaded pseudo reg.
3793 reg_last_reload_reg and reg_reloaded_contents keep track of
3794 which registers are already available in reload registers.
3795 We update these for the reloads that we perform,
3796 as the insns are scanned. */
3799 reload_as_needed (live_known)
3802 struct insn_chain *chain;
3803 #if defined (AUTO_INC_DEC)
3808 memset ((char *) spill_reg_rtx, 0, sizeof spill_reg_rtx);
3809 memset ((char *) spill_reg_store, 0, sizeof spill_reg_store);
3810 reg_last_reload_reg = (rtx *) xcalloc (max_regno, sizeof (rtx));
3811 reg_has_output_reload = (char *) xmalloc (max_regno);
3812 CLEAR_HARD_REG_SET (reg_reloaded_valid);
3814 set_initial_elim_offsets ();
3816 for (chain = reload_insn_chain; chain; chain = chain->next)
3819 rtx insn = chain->insn;
3820 rtx old_next = NEXT_INSN (insn);
3822 /* If we pass a label, copy the offsets from the label information
3823 into the current offsets of each elimination. */
3824 if (GET_CODE (insn) == CODE_LABEL)
3825 set_offsets_for_label (insn);
3827 else if (INSN_P (insn))
3829 rtx oldpat = PATTERN (insn);
3831 /* If this is a USE and CLOBBER of a MEM, ensure that any
3832 references to eliminable registers have been removed. */
3834 if ((GET_CODE (PATTERN (insn)) == USE
3835 || GET_CODE (PATTERN (insn)) == CLOBBER)
3836 && GET_CODE (XEXP (PATTERN (insn), 0)) == MEM)
3837 XEXP (XEXP (PATTERN (insn), 0), 0)
3838 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
3839 GET_MODE (XEXP (PATTERN (insn), 0)),
3842 /* If we need to do register elimination processing, do so.
3843 This might delete the insn, in which case we are done. */
3844 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
3846 eliminate_regs_in_insn (insn, 1);
3847 if (GET_CODE (insn) == NOTE)
3849 update_eliminable_offsets ();
3854 /* If need_elim is nonzero but need_reload is zero, one might think
3855 that we could simply set n_reloads to 0. However, find_reloads
3856 could have done some manipulation of the insn (such as swapping
3857 commutative operands), and these manipulations are lost during
3858 the first pass for every insn that needs register elimination.
3859 So the actions of find_reloads must be redone here. */
3861 if (! chain->need_elim && ! chain->need_reload
3862 && ! chain->need_operand_change)
3864 /* First find the pseudo regs that must be reloaded for this insn.
3865 This info is returned in the tables reload_... (see reload.h).
3866 Also modify the body of INSN by substituting RELOAD
3867 rtx's for those pseudo regs. */
3870 memset (reg_has_output_reload, 0, max_regno);
3871 CLEAR_HARD_REG_SET (reg_is_output_reload);
3873 find_reloads (insn, 1, spill_indirect_levels, live_known,
3877 if (num_eliminable && chain->need_elim)
3878 update_eliminable_offsets ();
3882 rtx next = NEXT_INSN (insn);
3885 prev = PREV_INSN (insn);
3887 /* Now compute which reload regs to reload them into. Perhaps
3888 reusing reload regs from previous insns, or else output
3889 load insns to reload them. Maybe output store insns too.
3890 Record the choices of reload reg in reload_reg_rtx. */
3891 choose_reload_regs (chain);
3893 /* Merge any reloads that we didn't combine for fear of
3894 increasing the number of spill registers needed but now
3895 discover can be safely merged. */
3896 if (SMALL_REGISTER_CLASSES)
3897 merge_assigned_reloads (insn);
3899 /* Generate the insns to reload operands into or out of
3900 their reload regs. */
3901 emit_reload_insns (chain);
3903 /* Substitute the chosen reload regs from reload_reg_rtx
3904 into the insn's body (or perhaps into the bodies of other
3905 load and store insn that we just made for reloading
3906 and that we moved the structure into). */
3907 subst_reloads (insn);
3909 /* If this was an ASM, make sure that all the reload insns
3910 we have generated are valid. If not, give an error
3913 if (asm_noperands (PATTERN (insn)) >= 0)
3914 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
3915 if (p != insn && INSN_P (p)
3916 && (recog_memoized (p) < 0
3917 || (extract_insn (p), ! constrain_operands (1))))
3919 error_for_asm (insn,
3920 "`asm' operand requires impossible reload");
3922 NOTE_SOURCE_FILE (p) = 0;
3923 NOTE_LINE_NUMBER (p) = NOTE_INSN_DELETED;
3926 /* Any previously reloaded spilled pseudo reg, stored in this insn,
3927 is no longer validly lying around to save a future reload.
3928 Note that this does not detect pseudos that were reloaded
3929 for this insn in order to be stored in
3930 (obeying register constraints). That is correct; such reload
3931 registers ARE still valid. */
3932 note_stores (oldpat, forget_old_reloads_1, NULL);
3934 /* There may have been CLOBBER insns placed after INSN. So scan
3935 between INSN and NEXT and use them to forget old reloads. */
3936 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
3937 if (GET_CODE (x) == INSN && GET_CODE (PATTERN (x)) == CLOBBER)
3938 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
3941 /* Likewise for regs altered by auto-increment in this insn.
3942 REG_INC notes have been changed by reloading:
3943 find_reloads_address_1 records substitutions for them,
3944 which have been performed by subst_reloads above. */
3945 for (i = n_reloads - 1; i >= 0; i--)
3947 rtx in_reg = rld[i].in_reg;
3950 enum rtx_code code = GET_CODE (in_reg);
3951 /* PRE_INC / PRE_DEC will have the reload register ending up
3952 with the same value as the stack slot, but that doesn't
3953 hold true for POST_INC / POST_DEC. Either we have to
3954 convert the memory access to a true POST_INC / POST_DEC,
3955 or we can't use the reload register for inheritance. */
3956 if ((code == POST_INC || code == POST_DEC)
3957 && TEST_HARD_REG_BIT (reg_reloaded_valid,
3958 REGNO (rld[i].reg_rtx))
3959 /* Make sure it is the inc/dec pseudo, and not
3960 some other (e.g. output operand) pseudo. */
3961 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
3962 == REGNO (XEXP (in_reg, 0))))
3965 rtx reload_reg = rld[i].reg_rtx;
3966 enum machine_mode mode = GET_MODE (reload_reg);
3970 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
3972 /* We really want to ignore REG_INC notes here, so
3973 use PATTERN (p) as argument to reg_set_p . */
3974 if (reg_set_p (reload_reg, PATTERN (p)))
3976 n = count_occurrences (PATTERN (p), reload_reg, 0);
3981 n = validate_replace_rtx (reload_reg,
3982 gen_rtx (code, mode,
3986 /* We must also verify that the constraints
3987 are met after the replacement. */
3990 n = constrain_operands (1);
3994 /* If the constraints were not met, then
3995 undo the replacement. */
3998 validate_replace_rtx (gen_rtx (code, mode,
4010 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4012 /* Mark this as having an output reload so that the
4013 REG_INC processing code below won't invalidate
4014 the reload for inheritance. */
4015 SET_HARD_REG_BIT (reg_is_output_reload,
4016 REGNO (reload_reg));
4017 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4020 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4023 else if ((code == PRE_INC || code == PRE_DEC)
4024 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4025 REGNO (rld[i].reg_rtx))
4026 /* Make sure it is the inc/dec pseudo, and not
4027 some other (e.g. output operand) pseudo. */
4028 && (reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4029 == REGNO (XEXP (in_reg, 0))))
4031 SET_HARD_REG_BIT (reg_is_output_reload,
4032 REGNO (rld[i].reg_rtx));
4033 reg_has_output_reload[REGNO (XEXP (in_reg, 0))] = 1;
4037 /* If a pseudo that got a hard register is auto-incremented,
4038 we must purge records of copying it into pseudos without
4040 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4041 if (REG_NOTE_KIND (x) == REG_INC)
4043 /* See if this pseudo reg was reloaded in this insn.
4044 If so, its last-reload info is still valid
4045 because it is based on this insn's reload. */
4046 for (i = 0; i < n_reloads; i++)
4047 if (rld[i].out == XEXP (x, 0))
4051 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4055 /* A reload reg's contents are unknown after a label. */
4056 if (GET_CODE (insn) == CODE_LABEL)
4057 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4059 /* Don't assume a reload reg is still good after a call insn
4060 if it is a call-used reg. */
4061 else if (GET_CODE (insn) == CALL_INSN)
4062 AND_COMPL_HARD_REG_SET(reg_reloaded_valid, call_used_reg_set);
4066 free (reg_last_reload_reg);
4067 free (reg_has_output_reload);
4070 /* Discard all record of any value reloaded from X,
4071 or reloaded in X from someplace else;
4072 unless X is an output reload reg of the current insn.
4074 X may be a hard reg (the reload reg)
4075 or it may be a pseudo reg that was reloaded from. */
4078 forget_old_reloads_1 (x, ignored, data)
4080 rtx ignored ATTRIBUTE_UNUSED;
4081 void *data ATTRIBUTE_UNUSED;
4087 /* note_stores does give us subregs of hard regs,
4088 subreg_regno_offset will abort if it is not a hard reg. */
4089 while (GET_CODE (x) == SUBREG)
4091 offset += subreg_regno_offset (REGNO (SUBREG_REG (x)),
4092 GET_MODE (SUBREG_REG (x)),
4098 if (GET_CODE (x) != REG)
4101 regno = REGNO (x) + offset;
4103 if (regno >= FIRST_PSEUDO_REGISTER)
4109 nr = HARD_REGNO_NREGS (regno, GET_MODE (x));
4110 /* Storing into a spilled-reg invalidates its contents.
4111 This can happen if a block-local pseudo is allocated to that reg
4112 and it wasn't spilled because this block's total need is 0.
4113 Then some insn might have an optional reload and use this reg. */
4114 for (i = 0; i < nr; i++)
4115 /* But don't do this if the reg actually serves as an output
4116 reload reg in the current instruction. */
4118 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4120 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4121 spill_reg_store[regno + i] = 0;
4125 /* Since value of X has changed,
4126 forget any value previously copied from it. */
4129 /* But don't forget a copy if this is the output reload
4130 that establishes the copy's validity. */
4131 if (n_reloads == 0 || reg_has_output_reload[regno + nr] == 0)
4132 reg_last_reload_reg[regno + nr] = 0;
4135 /* The following HARD_REG_SETs indicate when each hard register is
4136 used for a reload of various parts of the current insn. */
4138 /* If reg is unavailable for all reloads. */
4139 static HARD_REG_SET reload_reg_unavailable;
4140 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4141 static HARD_REG_SET reload_reg_used;
4142 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4143 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4144 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4145 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4146 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4147 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4148 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4149 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4150 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4151 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4152 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4153 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4154 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4155 static HARD_REG_SET reload_reg_used_in_op_addr;
4156 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4157 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4158 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4159 static HARD_REG_SET reload_reg_used_in_insn;
4160 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4161 static HARD_REG_SET reload_reg_used_in_other_addr;
4163 /* If reg is in use as a reload reg for any sort of reload. */
4164 static HARD_REG_SET reload_reg_used_at_all;
4166 /* If reg is use as an inherited reload. We just mark the first register
4168 static HARD_REG_SET reload_reg_used_for_inherit;
4170 /* Records which hard regs are used in any way, either as explicit use or
4171 by being allocated to a pseudo during any point of the current insn. */
4172 static HARD_REG_SET reg_used_in_insn;
4174 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4175 TYPE. MODE is used to indicate how many consecutive regs are
4179 mark_reload_reg_in_use (regno, opnum, type, mode)
4182 enum reload_type type;
4183 enum machine_mode mode;
4185 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4188 for (i = regno; i < nregs + regno; i++)
4193 SET_HARD_REG_BIT (reload_reg_used, i);
4196 case RELOAD_FOR_INPUT_ADDRESS:
4197 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4200 case RELOAD_FOR_INPADDR_ADDRESS:
4201 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4204 case RELOAD_FOR_OUTPUT_ADDRESS:
4205 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4208 case RELOAD_FOR_OUTADDR_ADDRESS:
4209 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4212 case RELOAD_FOR_OPERAND_ADDRESS:
4213 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4216 case RELOAD_FOR_OPADDR_ADDR:
4217 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4220 case RELOAD_FOR_OTHER_ADDRESS:
4221 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4224 case RELOAD_FOR_INPUT:
4225 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4228 case RELOAD_FOR_OUTPUT:
4229 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4232 case RELOAD_FOR_INSN:
4233 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4237 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4241 /* Similarly, but show REGNO is no longer in use for a reload. */
4244 clear_reload_reg_in_use (regno, opnum, type, mode)
4247 enum reload_type type;
4248 enum machine_mode mode;
4250 unsigned int nregs = HARD_REGNO_NREGS (regno, mode);
4251 unsigned int start_regno, end_regno, r;
4253 /* A complication is that for some reload types, inheritance might
4254 allow multiple reloads of the same types to share a reload register.
4255 We set check_opnum if we have to check only reloads with the same
4256 operand number, and check_any if we have to check all reloads. */
4257 int check_opnum = 0;
4259 HARD_REG_SET *used_in_set;
4264 used_in_set = &reload_reg_used;
4267 case RELOAD_FOR_INPUT_ADDRESS:
4268 used_in_set = &reload_reg_used_in_input_addr[opnum];
4271 case RELOAD_FOR_INPADDR_ADDRESS:
4273 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4276 case RELOAD_FOR_OUTPUT_ADDRESS:
4277 used_in_set = &reload_reg_used_in_output_addr[opnum];
4280 case RELOAD_FOR_OUTADDR_ADDRESS:
4282 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4285 case RELOAD_FOR_OPERAND_ADDRESS:
4286 used_in_set = &reload_reg_used_in_op_addr;
4289 case RELOAD_FOR_OPADDR_ADDR:
4291 used_in_set = &reload_reg_used_in_op_addr_reload;
4294 case RELOAD_FOR_OTHER_ADDRESS:
4295 used_in_set = &reload_reg_used_in_other_addr;
4299 case RELOAD_FOR_INPUT:
4300 used_in_set = &reload_reg_used_in_input[opnum];
4303 case RELOAD_FOR_OUTPUT:
4304 used_in_set = &reload_reg_used_in_output[opnum];
4307 case RELOAD_FOR_INSN:
4308 used_in_set = &reload_reg_used_in_insn;
4313 /* We resolve conflicts with remaining reloads of the same type by
4314 excluding the intervals of of reload registers by them from the
4315 interval of freed reload registers. Since we only keep track of
4316 one set of interval bounds, we might have to exclude somewhat
4317 more then what would be necessary if we used a HARD_REG_SET here.
4318 But this should only happen very infrequently, so there should
4319 be no reason to worry about it. */
4321 start_regno = regno;
4322 end_regno = regno + nregs;
4323 if (check_opnum || check_any)
4325 for (i = n_reloads - 1; i >= 0; i--)
4327 if (rld[i].when_needed == type
4328 && (check_any || rld[i].opnum == opnum)
4331 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4332 unsigned int conflict_end
4334 + HARD_REGNO_NREGS (conflict_start, rld[i].mode));
4336 /* If there is an overlap with the first to-be-freed register,
4337 adjust the interval start. */
4338 if (conflict_start <= start_regno && conflict_end > start_regno)
4339 start_regno = conflict_end;
4340 /* Otherwise, if there is a conflict with one of the other
4341 to-be-freed registers, adjust the interval end. */
4342 if (conflict_start > start_regno && conflict_start < end_regno)
4343 end_regno = conflict_start;
4348 for (r = start_regno; r < end_regno; r++)
4349 CLEAR_HARD_REG_BIT (*used_in_set, r);
4352 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4353 specified by OPNUM and TYPE. */
4356 reload_reg_free_p (regno, opnum, type)
4359 enum reload_type type;
4363 /* In use for a RELOAD_OTHER means it's not available for anything. */
4364 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4365 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4371 /* In use for anything means we can't use it for RELOAD_OTHER. */
4372 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4373 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4374 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4377 for (i = 0; i < reload_n_operands; i++)
4378 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4379 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4380 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4381 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4382 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4383 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4388 case RELOAD_FOR_INPUT:
4389 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4390 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4393 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4396 /* If it is used for some other input, can't use it. */
4397 for (i = 0; i < reload_n_operands; i++)
4398 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4401 /* If it is used in a later operand's address, can't use it. */
4402 for (i = opnum + 1; i < reload_n_operands; i++)
4403 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4404 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4409 case RELOAD_FOR_INPUT_ADDRESS:
4410 /* Can't use a register if it is used for an input address for this
4411 operand or used as an input in an earlier one. */
4412 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4413 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4416 for (i = 0; i < opnum; i++)
4417 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4422 case RELOAD_FOR_INPADDR_ADDRESS:
4423 /* Can't use a register if it is used for an input address
4424 for this operand or used as an input in an earlier
4426 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4429 for (i = 0; i < opnum; i++)
4430 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4435 case RELOAD_FOR_OUTPUT_ADDRESS:
4436 /* Can't use a register if it is used for an output address for this
4437 operand or used as an output in this or a later operand. */
4438 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4441 for (i = opnum; i < reload_n_operands; i++)
4442 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4447 case RELOAD_FOR_OUTADDR_ADDRESS:
4448 /* Can't use a register if it is used for an output address
4449 for this operand or used as an output in this or a
4451 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4454 for (i = opnum; i < reload_n_operands; i++)
4455 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4460 case RELOAD_FOR_OPERAND_ADDRESS:
4461 for (i = 0; i < reload_n_operands; i++)
4462 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4465 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4466 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4468 case RELOAD_FOR_OPADDR_ADDR:
4469 for (i = 0; i < reload_n_operands; i++)
4470 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4473 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4475 case RELOAD_FOR_OUTPUT:
4476 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4477 outputs, or an operand address for this or an earlier output. */
4478 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4481 for (i = 0; i < reload_n_operands; i++)
4482 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4485 for (i = 0; i <= opnum; i++)
4486 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4487 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4492 case RELOAD_FOR_INSN:
4493 for (i = 0; i < reload_n_operands; i++)
4494 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4495 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4498 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4499 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4501 case RELOAD_FOR_OTHER_ADDRESS:
4502 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4507 /* Return 1 if the value in reload reg REGNO, as used by a reload
4508 needed for the part of the insn specified by OPNUM and TYPE,
4509 is still available in REGNO at the end of the insn.
4511 We can assume that the reload reg was already tested for availability
4512 at the time it is needed, and we should not check this again,
4513 in case the reg has already been marked in use. */
4516 reload_reg_reaches_end_p (regno, opnum, type)
4519 enum reload_type type;
4526 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4527 its value must reach the end. */
4530 /* If this use is for part of the insn,
4531 its value reaches if no subsequent part uses the same register.
4532 Just like the above function, don't try to do this with lots
4535 case RELOAD_FOR_OTHER_ADDRESS:
4536 /* Here we check for everything else, since these don't conflict
4537 with anything else and everything comes later. */
4539 for (i = 0; i < reload_n_operands; i++)
4540 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4541 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4542 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4543 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4544 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4545 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4548 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4549 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4550 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4552 case RELOAD_FOR_INPUT_ADDRESS:
4553 case RELOAD_FOR_INPADDR_ADDRESS:
4554 /* Similar, except that we check only for this and subsequent inputs
4555 and the address of only subsequent inputs and we do not need
4556 to check for RELOAD_OTHER objects since they are known not to
4559 for (i = opnum; i < reload_n_operands; i++)
4560 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4563 for (i = opnum + 1; i < reload_n_operands; i++)
4564 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4565 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4568 for (i = 0; i < reload_n_operands; i++)
4569 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4570 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4571 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4574 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4577 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4578 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4579 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4581 case RELOAD_FOR_INPUT:
4582 /* Similar to input address, except we start at the next operand for
4583 both input and input address and we do not check for
4584 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4587 for (i = opnum + 1; i < reload_n_operands; i++)
4588 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4589 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4590 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4593 /* ... fall through ... */
4595 case RELOAD_FOR_OPERAND_ADDRESS:
4596 /* Check outputs and their addresses. */
4598 for (i = 0; i < reload_n_operands; i++)
4599 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4600 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4601 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4604 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4606 case RELOAD_FOR_OPADDR_ADDR:
4607 for (i = 0; i < reload_n_operands; i++)
4608 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4609 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4610 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4613 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4614 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4615 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4617 case RELOAD_FOR_INSN:
4618 /* These conflict with other outputs with RELOAD_OTHER. So
4619 we need only check for output addresses. */
4623 /* ... fall through ... */
4625 case RELOAD_FOR_OUTPUT:
4626 case RELOAD_FOR_OUTPUT_ADDRESS:
4627 case RELOAD_FOR_OUTADDR_ADDRESS:
4628 /* We already know these can't conflict with a later output. So the
4629 only thing to check are later output addresses. */
4630 for (i = opnum + 1; i < reload_n_operands; i++)
4631 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4632 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4641 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4644 This function uses the same algorithm as reload_reg_free_p above. */
4647 reloads_conflict (r1, r2)
4650 enum reload_type r1_type = rld[r1].when_needed;
4651 enum reload_type r2_type = rld[r2].when_needed;
4652 int r1_opnum = rld[r1].opnum;
4653 int r2_opnum = rld[r2].opnum;
4655 /* RELOAD_OTHER conflicts with everything. */
4656 if (r2_type == RELOAD_OTHER)
4659 /* Otherwise, check conflicts differently for each type. */
4663 case RELOAD_FOR_INPUT:
4664 return (r2_type == RELOAD_FOR_INSN
4665 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4666 || r2_type == RELOAD_FOR_OPADDR_ADDR
4667 || r2_type == RELOAD_FOR_INPUT
4668 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4669 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4670 && r2_opnum > r1_opnum));
4672 case RELOAD_FOR_INPUT_ADDRESS:
4673 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
4674 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4676 case RELOAD_FOR_INPADDR_ADDRESS:
4677 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
4678 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
4680 case RELOAD_FOR_OUTPUT_ADDRESS:
4681 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
4682 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4684 case RELOAD_FOR_OUTADDR_ADDRESS:
4685 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
4686 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum >= r1_opnum));
4688 case RELOAD_FOR_OPERAND_ADDRESS:
4689 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
4690 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4692 case RELOAD_FOR_OPADDR_ADDR:
4693 return (r2_type == RELOAD_FOR_INPUT
4694 || r2_type == RELOAD_FOR_OPADDR_ADDR);
4696 case RELOAD_FOR_OUTPUT:
4697 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
4698 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
4699 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
4700 && r2_opnum <= r1_opnum));
4702 case RELOAD_FOR_INSN:
4703 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
4704 || r2_type == RELOAD_FOR_INSN
4705 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
4707 case RELOAD_FOR_OTHER_ADDRESS:
4708 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
4718 /* Indexed by reload number, 1 if incoming value
4719 inherited from previous insns. */
4720 char reload_inherited[MAX_RELOADS];
4722 /* For an inherited reload, this is the insn the reload was inherited from,
4723 if we know it. Otherwise, this is 0. */
4724 rtx reload_inheritance_insn[MAX_RELOADS];
4726 /* If non-zero, this is a place to get the value of the reload,
4727 rather than using reload_in. */
4728 rtx reload_override_in[MAX_RELOADS];
4730 /* For each reload, the hard register number of the register used,
4731 or -1 if we did not need a register for this reload. */
4732 int reload_spill_index[MAX_RELOADS];
4734 /* Subroutine of free_for_value_p, used to check a single register.
4735 START_REGNO is the starting regno of the full reload register
4736 (possibly comprising multiple hard registers) that we are considering. */
4739 reload_reg_free_for_value_p (start_regno, regno, opnum, type, value, out,
4740 reloadnum, ignore_address_reloads)
4741 int start_regno, regno;
4743 enum reload_type type;
4746 int ignore_address_reloads;
4749 /* Set if we see an input reload that must not share its reload register
4750 with any new earlyclobber, but might otherwise share the reload
4751 register with an output or input-output reload. */
4752 int check_earlyclobber = 0;
4756 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4759 if (out == const0_rtx)
4765 /* We use some pseudo 'time' value to check if the lifetimes of the
4766 new register use would overlap with the one of a previous reload
4767 that is not read-only or uses a different value.
4768 The 'time' used doesn't have to be linear in any shape or form, just
4770 Some reload types use different 'buckets' for each operand.
4771 So there are MAX_RECOG_OPERANDS different time values for each
4773 We compute TIME1 as the time when the register for the prospective
4774 new reload ceases to be live, and TIME2 for each existing
4775 reload as the time when that the reload register of that reload
4777 Where there is little to be gained by exact lifetime calculations,
4778 we just make conservative assumptions, i.e. a longer lifetime;
4779 this is done in the 'default:' cases. */
4782 case RELOAD_FOR_OTHER_ADDRESS:
4783 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
4784 time1 = copy ? 0 : 1;
4787 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
4789 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
4790 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
4791 respectively, to the time values for these, we get distinct time
4792 values. To get distinct time values for each operand, we have to
4793 multiply opnum by at least three. We round that up to four because
4794 multiply by four is often cheaper. */
4795 case RELOAD_FOR_INPADDR_ADDRESS:
4796 time1 = opnum * 4 + 2;
4798 case RELOAD_FOR_INPUT_ADDRESS:
4799 time1 = opnum * 4 + 3;
4801 case RELOAD_FOR_INPUT:
4802 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
4803 executes (inclusive). */
4804 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
4806 case RELOAD_FOR_OPADDR_ADDR:
4808 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
4809 time1 = MAX_RECOG_OPERANDS * 4 + 1;
4811 case RELOAD_FOR_OPERAND_ADDRESS:
4812 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
4814 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
4816 case RELOAD_FOR_OUTADDR_ADDRESS:
4817 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
4819 case RELOAD_FOR_OUTPUT_ADDRESS:
4820 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
4823 time1 = MAX_RECOG_OPERANDS * 5 + 5;
4826 for (i = 0; i < n_reloads; i++)
4828 rtx reg = rld[i].reg_rtx;
4829 if (reg && GET_CODE (reg) == REG
4830 && ((unsigned) regno - true_regnum (reg)
4831 <= HARD_REGNO_NREGS (REGNO (reg), GET_MODE (reg)) - (unsigned)1)
4834 rtx other_input = rld[i].in;
4836 /* If the other reload loads the same input value, that
4837 will not cause a conflict only if it's loading it into
4838 the same register. */
4839 if (true_regnum (reg) != start_regno)
4840 other_input = NULL_RTX;
4841 if (! other_input || ! rtx_equal_p (other_input, value)
4842 || rld[i].out || out)
4845 switch (rld[i].when_needed)
4847 case RELOAD_FOR_OTHER_ADDRESS:
4850 case RELOAD_FOR_INPADDR_ADDRESS:
4851 /* find_reloads makes sure that a
4852 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
4853 by at most one - the first -
4854 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
4855 address reload is inherited, the address address reload
4856 goes away, so we can ignore this conflict. */
4857 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
4858 && ignore_address_reloads
4859 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
4860 Then the address address is still needed to store
4861 back the new address. */
4862 && ! rld[reloadnum].out)
4864 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
4865 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
4867 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4868 && ignore_address_reloads
4869 /* Unless we are reloading an auto_inc expression. */
4870 && ! rld[reloadnum].out)
4872 time2 = rld[i].opnum * 4 + 2;
4874 case RELOAD_FOR_INPUT_ADDRESS:
4875 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
4876 && ignore_address_reloads
4877 && ! rld[reloadnum].out)
4879 time2 = rld[i].opnum * 4 + 3;
4881 case RELOAD_FOR_INPUT:
4882 time2 = rld[i].opnum * 4 + 4;
4883 check_earlyclobber = 1;
4885 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
4886 == MAX_RECOG_OPERAND * 4 */
4887 case RELOAD_FOR_OPADDR_ADDR:
4888 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
4889 && ignore_address_reloads
4890 && ! rld[reloadnum].out)
4892 time2 = MAX_RECOG_OPERANDS * 4 + 1;
4894 case RELOAD_FOR_OPERAND_ADDRESS:
4895 time2 = MAX_RECOG_OPERANDS * 4 + 2;
4896 check_earlyclobber = 1;
4898 case RELOAD_FOR_INSN:
4899 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4901 case RELOAD_FOR_OUTPUT:
4902 /* All RELOAD_FOR_OUTPUT reloads become live just after the
4903 instruction is executed. */
4904 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4906 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
4907 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
4909 case RELOAD_FOR_OUTADDR_ADDRESS:
4910 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
4911 && ignore_address_reloads
4912 && ! rld[reloadnum].out)
4914 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
4916 case RELOAD_FOR_OUTPUT_ADDRESS:
4917 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
4920 /* If there is no conflict in the input part, handle this
4921 like an output reload. */
4922 if (! rld[i].in || rtx_equal_p (other_input, value))
4924 time2 = MAX_RECOG_OPERANDS * 4 + 4;
4925 /* Earlyclobbered outputs must conflict with inputs. */
4926 if (earlyclobber_operand_p (rld[i].out))
4927 time2 = MAX_RECOG_OPERANDS * 4 + 3;
4932 /* RELOAD_OTHER might be live beyond instruction execution,
4933 but this is not obvious when we set time2 = 1. So check
4934 here if there might be a problem with the new reload
4935 clobbering the register used by the RELOAD_OTHER. */
4943 && (! rld[i].in || rld[i].out
4944 || ! rtx_equal_p (other_input, value)))
4945 || (out && rld[reloadnum].out_reg
4946 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
4952 /* Earlyclobbered outputs must conflict with inputs. */
4953 if (check_earlyclobber && out && earlyclobber_operand_p (out))
4959 /* Return 1 if the value in reload reg REGNO, as used by a reload
4960 needed for the part of the insn specified by OPNUM and TYPE,
4961 may be used to load VALUE into it.
4963 MODE is the mode in which the register is used, this is needed to
4964 determine how many hard regs to test.
4966 Other read-only reloads with the same value do not conflict
4967 unless OUT is non-zero and these other reloads have to live while
4968 output reloads live.
4969 If OUT is CONST0_RTX, this is a special case: it means that the
4970 test should not be for using register REGNO as reload register, but
4971 for copying from register REGNO into the reload register.
4973 RELOADNUM is the number of the reload we want to load this value for;
4974 a reload does not conflict with itself.
4976 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
4977 reloads that load an address for the very reload we are considering.
4979 The caller has to make sure that there is no conflict with the return
4983 free_for_value_p (regno, mode, opnum, type, value, out, reloadnum,
4984 ignore_address_reloads)
4986 enum machine_mode mode;
4988 enum reload_type type;
4991 int ignore_address_reloads;
4993 int nregs = HARD_REGNO_NREGS (regno, mode);
4995 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
4996 value, out, reloadnum,
4997 ignore_address_reloads))
5002 /* Determine whether the reload reg X overlaps any rtx'es used for
5003 overriding inheritance. Return nonzero if so. */
5006 conflicts_with_override (x)
5010 for (i = 0; i < n_reloads; i++)
5011 if (reload_override_in[i]
5012 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5017 /* Give an error message saying we failed to find a reload for INSN,
5018 and clear out reload R. */
5020 failed_reload (insn, r)
5024 if (asm_noperands (PATTERN (insn)) < 0)
5025 /* It's the compiler's fault. */
5026 fatal_insn ("Could not find a spill register", insn);
5028 /* It's the user's fault; the operand's mode and constraint
5029 don't match. Disable this reload so we don't crash in final. */
5030 error_for_asm (insn,
5031 "`asm' operand constraint incompatible with operand size");
5035 rld[r].optional = 1;
5036 rld[r].secondary_p = 1;
5039 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5040 for reload R. If it's valid, get an rtx for it. Return nonzero if
5043 set_reload_reg (i, r)
5047 rtx reg = spill_reg_rtx[i];
5049 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5050 spill_reg_rtx[i] = reg
5051 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5053 regno = true_regnum (reg);
5055 /* Detect when the reload reg can't hold the reload mode.
5056 This used to be one `if', but Sequent compiler can't handle that. */
5057 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5059 enum machine_mode test_mode = VOIDmode;
5061 test_mode = GET_MODE (rld[r].in);
5062 /* If rld[r].in has VOIDmode, it means we will load it
5063 in whatever mode the reload reg has: to wit, rld[r].mode.
5064 We have already tested that for validity. */
5065 /* Aside from that, we need to test that the expressions
5066 to reload from or into have modes which are valid for this
5067 reload register. Otherwise the reload insns would be invalid. */
5068 if (! (rld[r].in != 0 && test_mode != VOIDmode
5069 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5070 if (! (rld[r].out != 0
5071 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5073 /* The reg is OK. */
5076 /* Mark as in use for this insn the reload regs we use
5078 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5079 rld[r].when_needed, rld[r].mode);
5081 rld[r].reg_rtx = reg;
5082 reload_spill_index[r] = spill_regs[i];
5089 /* Find a spill register to use as a reload register for reload R.
5090 LAST_RELOAD is non-zero if this is the last reload for the insn being
5093 Set rld[R].reg_rtx to the register allocated.
5095 We return 1 if successful, or 0 if we couldn't find a spill reg and
5096 we didn't change anything. */
5099 allocate_reload_reg (chain, r, last_reload)
5100 struct insn_chain *chain ATTRIBUTE_UNUSED;
5106 /* If we put this reload ahead, thinking it is a group,
5107 then insist on finding a group. Otherwise we can grab a
5108 reg that some other reload needs.
5109 (That can happen when we have a 68000 DATA_OR_FP_REG
5110 which is a group of data regs or one fp reg.)
5111 We need not be so restrictive if there are no more reloads
5114 ??? Really it would be nicer to have smarter handling
5115 for that kind of reg class, where a problem like this is normal.
5116 Perhaps those classes should be avoided for reloading
5117 by use of more alternatives. */
5119 int force_group = rld[r].nregs > 1 && ! last_reload;
5121 /* If we want a single register and haven't yet found one,
5122 take any reg in the right class and not in use.
5123 If we want a consecutive group, here is where we look for it.
5125 We use two passes so we can first look for reload regs to
5126 reuse, which are already in use for other reloads in this insn,
5127 and only then use additional registers.
5128 I think that maximizing reuse is needed to make sure we don't
5129 run out of reload regs. Suppose we have three reloads, and
5130 reloads A and B can share regs. These need two regs.
5131 Suppose A and B are given different regs.
5132 That leaves none for C. */
5133 for (pass = 0; pass < 2; pass++)
5135 /* I is the index in spill_regs.
5136 We advance it round-robin between insns to use all spill regs
5137 equally, so that inherited reloads have a chance
5138 of leapfrogging each other. */
5142 for (count = 0; count < n_spills; count++)
5144 int class = (int) rld[r].class;
5150 regnum = spill_regs[i];
5152 if ((reload_reg_free_p (regnum, rld[r].opnum,
5155 /* We check reload_reg_used to make sure we
5156 don't clobber the return register. */
5157 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5158 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5159 rld[r].when_needed, rld[r].in,
5161 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5162 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5163 /* Look first for regs to share, then for unshared. But
5164 don't share regs used for inherited reloads; they are
5165 the ones we want to preserve. */
5167 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5169 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5172 int nr = HARD_REGNO_NREGS (regnum, rld[r].mode);
5173 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5174 (on 68000) got us two FP regs. If NR is 1,
5175 we would reject both of them. */
5178 /* If we need only one reg, we have already won. */
5181 /* But reject a single reg if we demand a group. */
5186 /* Otherwise check that as many consecutive regs as we need
5187 are available here. */
5190 int regno = regnum + nr - 1;
5191 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5192 && spill_reg_order[regno] >= 0
5193 && reload_reg_free_p (regno, rld[r].opnum,
5194 rld[r].when_needed)))
5203 /* If we found something on pass 1, omit pass 2. */
5204 if (count < n_spills)
5208 /* We should have found a spill register by now. */
5209 if (count >= n_spills)
5212 /* I is the index in SPILL_REG_RTX of the reload register we are to
5213 allocate. Get an rtx for it and find its register number. */
5215 return set_reload_reg (i, r);
5218 /* Initialize all the tables needed to allocate reload registers.
5219 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5220 is the array we use to restore the reg_rtx field for every reload. */
5223 choose_reload_regs_init (chain, save_reload_reg_rtx)
5224 struct insn_chain *chain;
5225 rtx *save_reload_reg_rtx;
5229 for (i = 0; i < n_reloads; i++)
5230 rld[i].reg_rtx = save_reload_reg_rtx[i];
5232 memset (reload_inherited, 0, MAX_RELOADS);
5233 memset ((char *) reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5234 memset ((char *) reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5236 CLEAR_HARD_REG_SET (reload_reg_used);
5237 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5238 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5239 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5240 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5241 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5243 CLEAR_HARD_REG_SET (reg_used_in_insn);
5246 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5247 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5248 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5249 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5250 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5251 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5254 for (i = 0; i < reload_n_operands; i++)
5256 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5257 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5258 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5259 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5260 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5261 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5264 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5266 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5268 for (i = 0; i < n_reloads; i++)
5269 /* If we have already decided to use a certain register,
5270 don't use it in another way. */
5272 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5273 rld[i].when_needed, rld[i].mode);
5276 /* Assign hard reg targets for the pseudo-registers we must reload
5277 into hard regs for this insn.
5278 Also output the instructions to copy them in and out of the hard regs.
5280 For machines with register classes, we are responsible for
5281 finding a reload reg in the proper class. */
5284 choose_reload_regs (chain)
5285 struct insn_chain *chain;
5287 rtx insn = chain->insn;
5289 unsigned int max_group_size = 1;
5290 enum reg_class group_class = NO_REGS;
5291 int pass, win, inheritance;
5293 rtx save_reload_reg_rtx[MAX_RELOADS];
5295 /* In order to be certain of getting the registers we need,
5296 we must sort the reloads into order of increasing register class.
5297 Then our grabbing of reload registers will parallel the process
5298 that provided the reload registers.
5300 Also note whether any of the reloads wants a consecutive group of regs.
5301 If so, record the maximum size of the group desired and what
5302 register class contains all the groups needed by this insn. */
5304 for (j = 0; j < n_reloads; j++)
5306 reload_order[j] = j;
5307 reload_spill_index[j] = -1;
5309 if (rld[j].nregs > 1)
5311 max_group_size = MAX (rld[j].nregs, max_group_size);
5313 = reg_class_superunion[(int) rld[j].class][(int)group_class];
5316 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5320 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5322 /* If -O, try first with inheritance, then turning it off.
5323 If not -O, don't do inheritance.
5324 Using inheritance when not optimizing leads to paradoxes
5325 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5326 because one side of the comparison might be inherited. */
5328 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5330 choose_reload_regs_init (chain, save_reload_reg_rtx);
5332 /* Process the reloads in order of preference just found.
5333 Beyond this point, subregs can be found in reload_reg_rtx.
5335 This used to look for an existing reloaded home for all of the
5336 reloads, and only then perform any new reloads. But that could lose
5337 if the reloads were done out of reg-class order because a later
5338 reload with a looser constraint might have an old home in a register
5339 needed by an earlier reload with a tighter constraint.
5341 To solve this, we make two passes over the reloads, in the order
5342 described above. In the first pass we try to inherit a reload
5343 from a previous insn. If there is a later reload that needs a
5344 class that is a proper subset of the class being processed, we must
5345 also allocate a spill register during the first pass.
5347 Then make a second pass over the reloads to allocate any reloads
5348 that haven't been given registers yet. */
5350 for (j = 0; j < n_reloads; j++)
5352 register int r = reload_order[j];
5353 rtx search_equiv = NULL_RTX;
5355 /* Ignore reloads that got marked inoperative. */
5356 if (rld[r].out == 0 && rld[r].in == 0
5357 && ! rld[r].secondary_p)
5360 /* If find_reloads chose to use reload_in or reload_out as a reload
5361 register, we don't need to chose one. Otherwise, try even if it
5362 found one since we might save an insn if we find the value lying
5364 Try also when reload_in is a pseudo without a hard reg. */
5365 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5366 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5367 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5368 && GET_CODE (rld[r].in) != MEM
5369 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5372 #if 0 /* No longer needed for correct operation.
5373 It might give better code, or might not; worth an experiment? */
5374 /* If this is an optional reload, we can't inherit from earlier insns
5375 until we are sure that any non-optional reloads have been allocated.
5376 The following code takes advantage of the fact that optional reloads
5377 are at the end of reload_order. */
5378 if (rld[r].optional != 0)
5379 for (i = 0; i < j; i++)
5380 if ((rld[reload_order[i]].out != 0
5381 || rld[reload_order[i]].in != 0
5382 || rld[reload_order[i]].secondary_p)
5383 && ! rld[reload_order[i]].optional
5384 && rld[reload_order[i]].reg_rtx == 0)
5385 allocate_reload_reg (chain, reload_order[i], 0);
5388 /* First see if this pseudo is already available as reloaded
5389 for a previous insn. We cannot try to inherit for reloads
5390 that are smaller than the maximum number of registers needed
5391 for groups unless the register we would allocate cannot be used
5394 We could check here to see if this is a secondary reload for
5395 an object that is already in a register of the desired class.
5396 This would avoid the need for the secondary reload register.
5397 But this is complex because we can't easily determine what
5398 objects might want to be loaded via this reload. So let a
5399 register be allocated here. In `emit_reload_insns' we suppress
5400 one of the loads in the case described above. */
5405 register int regno = -1;
5406 enum machine_mode mode = VOIDmode;
5410 else if (GET_CODE (rld[r].in) == REG)
5412 regno = REGNO (rld[r].in);
5413 mode = GET_MODE (rld[r].in);
5415 else if (GET_CODE (rld[r].in_reg) == REG)
5417 regno = REGNO (rld[r].in_reg);
5418 mode = GET_MODE (rld[r].in_reg);
5420 else if (GET_CODE (rld[r].in_reg) == SUBREG
5421 && GET_CODE (SUBREG_REG (rld[r].in_reg)) == REG)
5423 byte = SUBREG_BYTE (rld[r].in_reg);
5424 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5425 if (regno < FIRST_PSEUDO_REGISTER)
5426 regno = subreg_regno (rld[r].in_reg);
5427 mode = GET_MODE (rld[r].in_reg);
5430 else if ((GET_CODE (rld[r].in_reg) == PRE_INC
5431 || GET_CODE (rld[r].in_reg) == PRE_DEC
5432 || GET_CODE (rld[r].in_reg) == POST_INC
5433 || GET_CODE (rld[r].in_reg) == POST_DEC)
5434 && GET_CODE (XEXP (rld[r].in_reg, 0)) == REG)
5436 regno = REGNO (XEXP (rld[r].in_reg, 0));
5437 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5438 rld[r].out = rld[r].in;
5442 /* This won't work, since REGNO can be a pseudo reg number.
5443 Also, it takes much more hair to keep track of all the things
5444 that can invalidate an inherited reload of part of a pseudoreg. */
5445 else if (GET_CODE (rld[r].in) == SUBREG
5446 && GET_CODE (SUBREG_REG (rld[r].in)) == REG)
5447 regno = subreg_regno (rld[r].in);
5450 if (regno >= 0 && reg_last_reload_reg[regno] != 0)
5452 enum reg_class class = rld[r].class, last_class;
5453 rtx last_reg = reg_last_reload_reg[regno];
5454 enum machine_mode need_mode;
5456 i = REGNO (last_reg);
5457 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5458 last_class = REGNO_REG_CLASS (i);
5464 = smallest_mode_for_size (GET_MODE_SIZE (mode) + byte,
5465 GET_MODE_CLASS (mode));
5468 #ifdef CLASS_CANNOT_CHANGE_MODE
5470 (reg_class_contents[(int) CLASS_CANNOT_CHANGE_MODE], i)
5471 ? ! CLASS_CANNOT_CHANGE_MODE_P (GET_MODE (last_reg),
5473 : (GET_MODE_SIZE (GET_MODE (last_reg))
5474 >= GET_MODE_SIZE (need_mode)))
5476 (GET_MODE_SIZE (GET_MODE (last_reg))
5477 >= GET_MODE_SIZE (need_mode))
5479 && reg_reloaded_contents[i] == regno
5480 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5481 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5482 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5483 /* Even if we can't use this register as a reload
5484 register, we might use it for reload_override_in,
5485 if copying it to the desired class is cheap
5487 || ((REGISTER_MOVE_COST (mode, last_class, class)
5488 < MEMORY_MOVE_COST (mode, class, 1))
5489 #ifdef SECONDARY_INPUT_RELOAD_CLASS
5490 && (SECONDARY_INPUT_RELOAD_CLASS (class, mode,
5494 #ifdef SECONDARY_MEMORY_NEEDED
5495 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5500 && (rld[r].nregs == max_group_size
5501 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5503 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5504 rld[r].when_needed, rld[r].in,
5507 /* If a group is needed, verify that all the subsequent
5508 registers still have their values intact. */
5509 int nr = HARD_REGNO_NREGS (i, rld[r].mode);
5512 for (k = 1; k < nr; k++)
5513 if (reg_reloaded_contents[i + k] != regno
5514 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5521 last_reg = (GET_MODE (last_reg) == mode
5522 ? last_reg : gen_rtx_REG (mode, i));
5524 /* We found a register that contains the
5525 value we need. If this register is the
5526 same as an `earlyclobber' operand of the
5527 current insn, just mark it as a place to
5528 reload from since we can't use it as the
5529 reload register itself. */
5531 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5532 if (reg_overlap_mentioned_for_reload_p
5533 (reg_last_reload_reg[regno],
5534 reload_earlyclobbers[i1]))
5537 if (i1 != n_earlyclobbers
5538 || ! (free_for_value_p (i, rld[r].mode,
5540 rld[r].when_needed, rld[r].in,
5542 /* Don't use it if we'd clobber a pseudo reg. */
5543 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5545 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5546 /* Don't clobber the frame pointer. */
5547 || (i == HARD_FRAME_POINTER_REGNUM
5549 /* Don't really use the inherited spill reg
5550 if we need it wider than we've got it. */
5551 || (GET_MODE_SIZE (rld[r].mode)
5552 > GET_MODE_SIZE (mode))
5553 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5556 /* If find_reloads chose reload_out as reload
5557 register, stay with it - that leaves the
5558 inherited register for subsequent reloads. */
5559 || (rld[r].out && rld[r].reg_rtx
5560 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5562 if (! rld[r].optional)
5564 reload_override_in[r] = last_reg;
5565 reload_inheritance_insn[r]
5566 = reg_reloaded_insn[i];
5572 /* We can use this as a reload reg. */
5573 /* Mark the register as in use for this part of
5575 mark_reload_reg_in_use (i,
5579 rld[r].reg_rtx = last_reg;
5580 reload_inherited[r] = 1;
5581 reload_inheritance_insn[r]
5582 = reg_reloaded_insn[i];
5583 reload_spill_index[r] = i;
5584 for (k = 0; k < nr; k++)
5585 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5593 /* Here's another way to see if the value is already lying around. */
5596 && ! reload_inherited[r]
5598 && (CONSTANT_P (rld[r].in)
5599 || GET_CODE (rld[r].in) == PLUS
5600 || GET_CODE (rld[r].in) == REG
5601 || GET_CODE (rld[r].in) == MEM)
5602 && (rld[r].nregs == max_group_size
5603 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5604 search_equiv = rld[r].in;
5605 /* If this is an output reload from a simple move insn, look
5606 if an equivalence for the input is available. */
5607 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5609 rtx set = single_set (insn);
5612 && rtx_equal_p (rld[r].out, SET_DEST (set))
5613 && CONSTANT_P (SET_SRC (set)))
5614 search_equiv = SET_SRC (set);
5620 = find_equiv_reg (search_equiv, insn, rld[r].class,
5621 -1, NULL, 0, rld[r].mode);
5626 if (GET_CODE (equiv) == REG)
5627 regno = REGNO (equiv);
5628 else if (GET_CODE (equiv) == SUBREG)
5630 /* This must be a SUBREG of a hard register.
5631 Make a new REG since this might be used in an
5632 address and not all machines support SUBREGs
5634 regno = subreg_regno (equiv);
5635 equiv = gen_rtx_REG (rld[r].mode, regno);
5641 /* If we found a spill reg, reject it unless it is free
5642 and of the desired class. */
5644 && ((TEST_HARD_REG_BIT (reload_reg_used_at_all, regno)
5645 && ! free_for_value_p (regno, rld[r].mode,
5646 rld[r].opnum, rld[r].when_needed,
5647 rld[r].in, rld[r].out, r, 1))
5648 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5652 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
5655 /* We found a register that contains the value we need.
5656 If this register is the same as an `earlyclobber' operand
5657 of the current insn, just mark it as a place to reload from
5658 since we can't use it as the reload register itself. */
5661 for (i = 0; i < n_earlyclobbers; i++)
5662 if (reg_overlap_mentioned_for_reload_p (equiv,
5663 reload_earlyclobbers[i]))
5665 if (! rld[r].optional)
5666 reload_override_in[r] = equiv;
5671 /* If the equiv register we have found is explicitly clobbered
5672 in the current insn, it depends on the reload type if we
5673 can use it, use it for reload_override_in, or not at all.
5674 In particular, we then can't use EQUIV for a
5675 RELOAD_FOR_OUTPUT_ADDRESS reload. */
5679 if (regno_clobbered_p (regno, insn, rld[r].mode, 0))
5680 switch (rld[r].when_needed)
5682 case RELOAD_FOR_OTHER_ADDRESS:
5683 case RELOAD_FOR_INPADDR_ADDRESS:
5684 case RELOAD_FOR_INPUT_ADDRESS:
5685 case RELOAD_FOR_OPADDR_ADDR:
5688 case RELOAD_FOR_INPUT:
5689 case RELOAD_FOR_OPERAND_ADDRESS:
5690 if (! rld[r].optional)
5691 reload_override_in[r] = equiv;
5697 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
5698 switch (rld[r].when_needed)
5700 case RELOAD_FOR_OTHER_ADDRESS:
5701 case RELOAD_FOR_INPADDR_ADDRESS:
5702 case RELOAD_FOR_INPUT_ADDRESS:
5703 case RELOAD_FOR_OPADDR_ADDR:
5704 case RELOAD_FOR_OPERAND_ADDRESS:
5705 case RELOAD_FOR_INPUT:
5708 if (! rld[r].optional)
5709 reload_override_in[r] = equiv;
5717 /* If we found an equivalent reg, say no code need be generated
5718 to load it, and use it as our reload reg. */
5719 if (equiv != 0 && regno != HARD_FRAME_POINTER_REGNUM)
5721 int nr = HARD_REGNO_NREGS (regno, rld[r].mode);
5723 rld[r].reg_rtx = equiv;
5724 reload_inherited[r] = 1;
5726 /* If reg_reloaded_valid is not set for this register,
5727 there might be a stale spill_reg_store lying around.
5728 We must clear it, since otherwise emit_reload_insns
5729 might delete the store. */
5730 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
5731 spill_reg_store[regno] = NULL_RTX;
5732 /* If any of the hard registers in EQUIV are spill
5733 registers, mark them as in use for this insn. */
5734 for (k = 0; k < nr; k++)
5736 i = spill_reg_order[regno + k];
5739 mark_reload_reg_in_use (regno, rld[r].opnum,
5742 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5749 /* If we found a register to use already, or if this is an optional
5750 reload, we are done. */
5751 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
5755 /* No longer needed for correct operation. Might or might
5756 not give better code on the average. Want to experiment? */
5758 /* See if there is a later reload that has a class different from our
5759 class that intersects our class or that requires less register
5760 than our reload. If so, we must allocate a register to this
5761 reload now, since that reload might inherit a previous reload
5762 and take the only available register in our class. Don't do this
5763 for optional reloads since they will force all previous reloads
5764 to be allocated. Also don't do this for reloads that have been
5767 for (i = j + 1; i < n_reloads; i++)
5769 int s = reload_order[i];
5771 if ((rld[s].in == 0 && rld[s].out == 0
5772 && ! rld[s].secondary_p)
5776 if ((rld[s].class != rld[r].class
5777 && reg_classes_intersect_p (rld[r].class,
5779 || rld[s].nregs < rld[r].nregs)
5786 allocate_reload_reg (chain, r, j == n_reloads - 1);
5790 /* Now allocate reload registers for anything non-optional that
5791 didn't get one yet. */
5792 for (j = 0; j < n_reloads; j++)
5794 register int r = reload_order[j];
5796 /* Ignore reloads that got marked inoperative. */
5797 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
5800 /* Skip reloads that already have a register allocated or are
5802 if (rld[r].reg_rtx != 0 || rld[r].optional)
5805 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
5809 /* If that loop got all the way, we have won. */
5816 /* Loop around and try without any inheritance. */
5821 /* First undo everything done by the failed attempt
5822 to allocate with inheritance. */
5823 choose_reload_regs_init (chain, save_reload_reg_rtx);
5825 /* Some sanity tests to verify that the reloads found in the first
5826 pass are identical to the ones we have now. */
5827 if (chain->n_reloads != n_reloads)
5830 for (i = 0; i < n_reloads; i++)
5832 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
5834 if (chain->rld[i].when_needed != rld[i].when_needed)
5836 for (j = 0; j < n_spills; j++)
5837 if (spill_regs[j] == chain->rld[i].regno)
5838 if (! set_reload_reg (j, i))
5839 failed_reload (chain->insn, i);
5843 /* If we thought we could inherit a reload, because it seemed that
5844 nothing else wanted the same reload register earlier in the insn,
5845 verify that assumption, now that all reloads have been assigned.
5846 Likewise for reloads where reload_override_in has been set. */
5848 /* If doing expensive optimizations, do one preliminary pass that doesn't
5849 cancel any inheritance, but removes reloads that have been needed only
5850 for reloads that we know can be inherited. */
5851 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
5853 for (j = 0; j < n_reloads; j++)
5855 register int r = reload_order[j];
5857 if (reload_inherited[r] && rld[r].reg_rtx)
5858 check_reg = rld[r].reg_rtx;
5859 else if (reload_override_in[r]
5860 && (GET_CODE (reload_override_in[r]) == REG
5861 || GET_CODE (reload_override_in[r]) == SUBREG))
5862 check_reg = reload_override_in[r];
5865 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
5866 rld[r].opnum, rld[r].when_needed, rld[r].in,
5867 (reload_inherited[r]
5868 ? rld[r].out : const0_rtx),
5873 reload_inherited[r] = 0;
5874 reload_override_in[r] = 0;
5876 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
5877 reload_override_in, then we do not need its related
5878 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
5879 likewise for other reload types.
5880 We handle this by removing a reload when its only replacement
5881 is mentioned in reload_in of the reload we are going to inherit.
5882 A special case are auto_inc expressions; even if the input is
5883 inherited, we still need the address for the output. We can
5884 recognize them because they have RELOAD_OUT set to RELOAD_IN.
5885 If we suceeded removing some reload and we are doing a preliminary
5886 pass just to remove such reloads, make another pass, since the
5887 removal of one reload might allow us to inherit another one. */
5889 && rld[r].out != rld[r].in
5890 && remove_address_replacements (rld[r].in) && pass)
5895 /* Now that reload_override_in is known valid,
5896 actually override reload_in. */
5897 for (j = 0; j < n_reloads; j++)
5898 if (reload_override_in[j])
5899 rld[j].in = reload_override_in[j];
5901 /* If this reload won't be done because it has been cancelled or is
5902 optional and not inherited, clear reload_reg_rtx so other
5903 routines (such as subst_reloads) don't get confused. */
5904 for (j = 0; j < n_reloads; j++)
5905 if (rld[j].reg_rtx != 0
5906 && ((rld[j].optional && ! reload_inherited[j])
5907 || (rld[j].in == 0 && rld[j].out == 0
5908 && ! rld[j].secondary_p)))
5910 int regno = true_regnum (rld[j].reg_rtx);
5912 if (spill_reg_order[regno] >= 0)
5913 clear_reload_reg_in_use (regno, rld[j].opnum,
5914 rld[j].when_needed, rld[j].mode);
5916 reload_spill_index[j] = -1;
5919 /* Record which pseudos and which spill regs have output reloads. */
5920 for (j = 0; j < n_reloads; j++)
5922 register int r = reload_order[j];
5924 i = reload_spill_index[r];
5926 /* I is nonneg if this reload uses a register.
5927 If rld[r].reg_rtx is 0, this is an optional reload
5928 that we opted to ignore. */
5929 if (rld[r].out_reg != 0 && GET_CODE (rld[r].out_reg) == REG
5930 && rld[r].reg_rtx != 0)
5932 register int nregno = REGNO (rld[r].out_reg);
5935 if (nregno < FIRST_PSEUDO_REGISTER)
5936 nr = HARD_REGNO_NREGS (nregno, rld[r].mode);
5939 reg_has_output_reload[nregno + nr] = 1;
5943 nr = HARD_REGNO_NREGS (i, rld[r].mode);
5945 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
5948 if (rld[r].when_needed != RELOAD_OTHER
5949 && rld[r].when_needed != RELOAD_FOR_OUTPUT
5950 && rld[r].when_needed != RELOAD_FOR_INSN)
5956 /* Deallocate the reload register for reload R. This is called from
5957 remove_address_replacements. */
5960 deallocate_reload_reg (r)
5965 if (! rld[r].reg_rtx)
5967 regno = true_regnum (rld[r].reg_rtx);
5969 if (spill_reg_order[regno] >= 0)
5970 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
5972 reload_spill_index[r] = -1;
5975 /* If SMALL_REGISTER_CLASSES is non-zero, we may not have merged two
5976 reloads of the same item for fear that we might not have enough reload
5977 registers. However, normally they will get the same reload register
5978 and hence actually need not be loaded twice.
5980 Here we check for the most common case of this phenomenon: when we have
5981 a number of reloads for the same object, each of which were allocated
5982 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
5983 reload, and is not modified in the insn itself. If we find such,
5984 merge all the reloads and set the resulting reload to RELOAD_OTHER.
5985 This will not increase the number of spill registers needed and will
5986 prevent redundant code. */
5989 merge_assigned_reloads (insn)
5994 /* Scan all the reloads looking for ones that only load values and
5995 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
5996 assigned and not modified by INSN. */
5998 for (i = 0; i < n_reloads; i++)
6000 int conflicting_input = 0;
6001 int max_input_address_opnum = -1;
6002 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6004 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6005 || rld[i].out != 0 || rld[i].reg_rtx == 0
6006 || reg_set_p (rld[i].reg_rtx, insn))
6009 /* Look at all other reloads. Ensure that the only use of this
6010 reload_reg_rtx is in a reload that just loads the same value
6011 as we do. Note that any secondary reloads must be of the identical
6012 class since the values, modes, and result registers are the
6013 same, so we need not do anything with any secondary reloads. */
6015 for (j = 0; j < n_reloads; j++)
6017 if (i == j || rld[j].reg_rtx == 0
6018 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6022 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6023 && rld[j].opnum > max_input_address_opnum)
6024 max_input_address_opnum = rld[j].opnum;
6026 /* If the reload regs aren't exactly the same (e.g, different modes)
6027 or if the values are different, we can't merge this reload.
6028 But if it is an input reload, we might still merge
6029 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6031 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6032 || rld[j].out != 0 || rld[j].in == 0
6033 || ! rtx_equal_p (rld[i].in, rld[j].in))
6035 if (rld[j].when_needed != RELOAD_FOR_INPUT
6036 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6037 || rld[i].opnum > rld[j].opnum)
6038 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6040 conflicting_input = 1;
6041 if (min_conflicting_input_opnum > rld[j].opnum)
6042 min_conflicting_input_opnum = rld[j].opnum;
6046 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6047 we, in fact, found any matching reloads. */
6050 && max_input_address_opnum <= min_conflicting_input_opnum)
6052 for (j = 0; j < n_reloads; j++)
6053 if (i != j && rld[j].reg_rtx != 0
6054 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6055 && (! conflicting_input
6056 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6057 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6059 rld[i].when_needed = RELOAD_OTHER;
6061 reload_spill_index[j] = -1;
6062 transfer_replacements (i, j);
6065 /* If this is now RELOAD_OTHER, look for any reloads that load
6066 parts of this operand and set them to RELOAD_FOR_OTHER_ADDRESS
6067 if they were for inputs, RELOAD_OTHER for outputs. Note that
6068 this test is equivalent to looking for reloads for this operand
6071 if (rld[i].when_needed == RELOAD_OTHER)
6072 for (j = 0; j < n_reloads; j++)
6074 && rld[i].when_needed != RELOAD_OTHER
6075 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6078 = ((rld[i].when_needed == RELOAD_FOR_INPUT_ADDRESS
6079 || rld[i].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6080 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6085 /* These arrays are filled by emit_reload_insns and its subroutines. */
6086 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6087 static rtx other_input_address_reload_insns = 0;
6088 static rtx other_input_reload_insns = 0;
6089 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6090 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6091 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6092 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6093 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6094 static rtx operand_reload_insns = 0;
6095 static rtx other_operand_reload_insns = 0;
6096 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6098 /* Values to be put in spill_reg_store are put here first. */
6099 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6100 static HARD_REG_SET reg_reloaded_died;
6102 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6103 has the number J. OLD contains the value to be used as input. */
6106 emit_input_reload_insns (chain, rl, old, j)
6107 struct insn_chain *chain;
6112 rtx insn = chain->insn;
6113 register rtx reloadreg = rl->reg_rtx;
6114 rtx oldequiv_reg = 0;
6117 enum machine_mode mode;
6120 /* Determine the mode to reload in.
6121 This is very tricky because we have three to choose from.
6122 There is the mode the insn operand wants (rl->inmode).
6123 There is the mode of the reload register RELOADREG.
6124 There is the intrinsic mode of the operand, which we could find
6125 by stripping some SUBREGs.
6126 It turns out that RELOADREG's mode is irrelevant:
6127 we can change that arbitrarily.
6129 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6130 then the reload reg may not support QImode moves, so use SImode.
6131 If foo is in memory due to spilling a pseudo reg, this is safe,
6132 because the QImode value is in the least significant part of a
6133 slot big enough for a SImode. If foo is some other sort of
6134 memory reference, then it is impossible to reload this case,
6135 so previous passes had better make sure this never happens.
6137 Then consider a one-word union which has SImode and one of its
6138 members is a float, being fetched as (SUBREG:SF union:SI).
6139 We must fetch that as SFmode because we could be loading into
6140 a float-only register. In this case OLD's mode is correct.
6142 Consider an immediate integer: it has VOIDmode. Here we need
6143 to get a mode from something else.
6145 In some cases, there is a fourth mode, the operand's
6146 containing mode. If the insn specifies a containing mode for
6147 this operand, it overrides all others.
6149 I am not sure whether the algorithm here is always right,
6150 but it does the right things in those cases. */
6152 mode = GET_MODE (old);
6153 if (mode == VOIDmode)
6156 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6157 /* If we need a secondary register for this operation, see if
6158 the value is already in a register in that class. Don't
6159 do this if the secondary register will be used as a scratch
6162 if (rl->secondary_in_reload >= 0
6163 && rl->secondary_in_icode == CODE_FOR_nothing
6166 = find_equiv_reg (old, insn,
6167 rld[rl->secondary_in_reload].class,
6171 /* If reloading from memory, see if there is a register
6172 that already holds the same value. If so, reload from there.
6173 We can pass 0 as the reload_reg_p argument because
6174 any other reload has either already been emitted,
6175 in which case find_equiv_reg will see the reload-insn,
6176 or has yet to be emitted, in which case it doesn't matter
6177 because we will use this equiv reg right away. */
6179 if (oldequiv == 0 && optimize
6180 && (GET_CODE (old) == MEM
6181 || (GET_CODE (old) == REG
6182 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6183 && reg_renumber[REGNO (old)] < 0)))
6184 oldequiv = find_equiv_reg (old, insn, ALL_REGS, -1, NULL, 0, mode);
6188 unsigned int regno = true_regnum (oldequiv);
6190 /* Don't use OLDEQUIV if any other reload changes it at an
6191 earlier stage of this insn or at this stage. */
6192 if (! free_for_value_p (regno, rl->mode, rl->opnum, rl->when_needed,
6193 rl->in, const0_rtx, j, 0))
6196 /* If it is no cheaper to copy from OLDEQUIV into the
6197 reload register than it would be to move from memory,
6198 don't use it. Likewise, if we need a secondary register
6202 && ((REGNO_REG_CLASS (regno) != rl->class
6203 && (REGISTER_MOVE_COST (mode, REGNO_REG_CLASS (regno),
6205 >= MEMORY_MOVE_COST (mode, rl->class, 1)))
6206 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6207 || (SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6211 #ifdef SECONDARY_MEMORY_NEEDED
6212 || SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (regno),
6220 /* delete_output_reload is only invoked properly if old contains
6221 the original pseudo register. Since this is replaced with a
6222 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6223 find the pseudo in RELOAD_IN_REG. */
6225 && reload_override_in[j]
6226 && GET_CODE (rl->in_reg) == REG)
6233 else if (GET_CODE (oldequiv) == REG)
6234 oldequiv_reg = oldequiv;
6235 else if (GET_CODE (oldequiv) == SUBREG)
6236 oldequiv_reg = SUBREG_REG (oldequiv);
6238 /* If we are reloading from a register that was recently stored in
6239 with an output-reload, see if we can prove there was
6240 actually no need to store the old value in it. */
6242 if (optimize && GET_CODE (oldequiv) == REG
6243 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6244 && spill_reg_store[REGNO (oldequiv)]
6245 && GET_CODE (old) == REG
6246 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6247 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6249 delete_output_reload (insn, j, REGNO (oldequiv));
6251 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6252 then load RELOADREG from OLDEQUIV. Note that we cannot use
6253 gen_lowpart_common since it can do the wrong thing when
6254 RELOADREG has a multi-word mode. Note that RELOADREG
6255 must always be a REG here. */
6257 if (GET_MODE (reloadreg) != mode)
6258 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6259 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6260 oldequiv = SUBREG_REG (oldequiv);
6261 if (GET_MODE (oldequiv) != VOIDmode
6262 && mode != GET_MODE (oldequiv))
6263 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6265 /* Switch to the right place to emit the reload insns. */
6266 switch (rl->when_needed)
6269 where = &other_input_reload_insns;
6271 case RELOAD_FOR_INPUT:
6272 where = &input_reload_insns[rl->opnum];
6274 case RELOAD_FOR_INPUT_ADDRESS:
6275 where = &input_address_reload_insns[rl->opnum];
6277 case RELOAD_FOR_INPADDR_ADDRESS:
6278 where = &inpaddr_address_reload_insns[rl->opnum];
6280 case RELOAD_FOR_OUTPUT_ADDRESS:
6281 where = &output_address_reload_insns[rl->opnum];
6283 case RELOAD_FOR_OUTADDR_ADDRESS:
6284 where = &outaddr_address_reload_insns[rl->opnum];
6286 case RELOAD_FOR_OPERAND_ADDRESS:
6287 where = &operand_reload_insns;
6289 case RELOAD_FOR_OPADDR_ADDR:
6290 where = &other_operand_reload_insns;
6292 case RELOAD_FOR_OTHER_ADDRESS:
6293 where = &other_input_address_reload_insns;
6299 push_to_sequence (*where);
6301 /* Auto-increment addresses must be reloaded in a special way. */
6302 if (rl->out && ! rl->out_reg)
6304 /* We are not going to bother supporting the case where a
6305 incremented register can't be copied directly from
6306 OLDEQUIV since this seems highly unlikely. */
6307 if (rl->secondary_in_reload >= 0)
6310 if (reload_inherited[j])
6311 oldequiv = reloadreg;
6313 old = XEXP (rl->in_reg, 0);
6315 if (optimize && GET_CODE (oldequiv) == REG
6316 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6317 && spill_reg_store[REGNO (oldequiv)]
6318 && GET_CODE (old) == REG
6319 && (dead_or_set_p (insn,
6320 spill_reg_stored_to[REGNO (oldequiv)])
6321 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6323 delete_output_reload (insn, j, REGNO (oldequiv));
6325 /* Prevent normal processing of this reload. */
6327 /* Output a special code sequence for this case. */
6328 new_spill_reg_store[REGNO (reloadreg)]
6329 = inc_for_reload (reloadreg, oldequiv, rl->out,
6333 /* If we are reloading a pseudo-register that was set by the previous
6334 insn, see if we can get rid of that pseudo-register entirely
6335 by redirecting the previous insn into our reload register. */
6337 else if (optimize && GET_CODE (old) == REG
6338 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6339 && dead_or_set_p (insn, old)
6340 /* This is unsafe if some other reload
6341 uses the same reg first. */
6342 && ! conflicts_with_override (reloadreg)
6343 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6344 rl->when_needed, old, rl->out, j, 0))
6346 rtx temp = PREV_INSN (insn);
6347 while (temp && GET_CODE (temp) == NOTE)
6348 temp = PREV_INSN (temp);
6350 && GET_CODE (temp) == INSN
6351 && GET_CODE (PATTERN (temp)) == SET
6352 && SET_DEST (PATTERN (temp)) == old
6353 /* Make sure we can access insn_operand_constraint. */
6354 && asm_noperands (PATTERN (temp)) < 0
6355 /* This is unsafe if prev insn rejects our reload reg. */
6356 && constraint_accepts_reg_p (insn_data[recog_memoized (temp)].operand[0].constraint,
6358 /* This is unsafe if operand occurs more than once in current
6359 insn. Perhaps some occurrences aren't reloaded. */
6360 && count_occurrences (PATTERN (insn), old, 0) == 1
6361 /* Don't risk splitting a matching pair of operands. */
6362 && ! reg_mentioned_p (old, SET_SRC (PATTERN (temp))))
6364 /* Store into the reload register instead of the pseudo. */
6365 SET_DEST (PATTERN (temp)) = reloadreg;
6367 /* If the previous insn is an output reload, the source is
6368 a reload register, and its spill_reg_store entry will
6369 contain the previous destination. This is now
6371 if (GET_CODE (SET_SRC (PATTERN (temp))) == REG
6372 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6374 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6375 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6378 /* If these are the only uses of the pseudo reg,
6379 pretend for GDB it lives in the reload reg we used. */
6380 if (REG_N_DEATHS (REGNO (old)) == 1
6381 && REG_N_SETS (REGNO (old)) == 1)
6383 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6384 alter_reg (REGNO (old), -1);
6390 /* We can't do that, so output an insn to load RELOADREG. */
6392 #ifdef SECONDARY_INPUT_RELOAD_CLASS
6393 /* If we have a secondary reload, pick up the secondary register
6394 and icode, if any. If OLDEQUIV and OLD are different or
6395 if this is an in-out reload, recompute whether or not we
6396 still need a secondary register and what the icode should
6397 be. If we still need a secondary register and the class or
6398 icode is different, go back to reloading from OLD if using
6399 OLDEQUIV means that we got the wrong type of register. We
6400 cannot have different class or icode due to an in-out reload
6401 because we don't make such reloads when both the input and
6402 output need secondary reload registers. */
6404 if (! special && rl->secondary_in_reload >= 0)
6406 rtx second_reload_reg = 0;
6407 int secondary_reload = rl->secondary_in_reload;
6408 rtx real_oldequiv = oldequiv;
6411 enum insn_code icode;
6413 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6414 and similarly for OLD.
6415 See comments in get_secondary_reload in reload.c. */
6416 /* If it is a pseudo that cannot be replaced with its
6417 equivalent MEM, we must fall back to reload_in, which
6418 will have all the necessary substitutions registered.
6419 Likewise for a pseudo that can't be replaced with its
6420 equivalent constant.
6422 Take extra care for subregs of such pseudos. Note that
6423 we cannot use reg_equiv_mem in this case because it is
6424 not in the right mode. */
6427 if (GET_CODE (tmp) == SUBREG)
6428 tmp = SUBREG_REG (tmp);
6429 if (GET_CODE (tmp) == REG
6430 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6431 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6432 || reg_equiv_constant[REGNO (tmp)] != 0))
6434 if (! reg_equiv_mem[REGNO (tmp)]
6435 || num_not_at_initial_offset
6436 || GET_CODE (oldequiv) == SUBREG)
6437 real_oldequiv = rl->in;
6439 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6443 if (GET_CODE (tmp) == SUBREG)
6444 tmp = SUBREG_REG (tmp);
6445 if (GET_CODE (tmp) == REG
6446 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6447 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6448 || reg_equiv_constant[REGNO (tmp)] != 0))
6450 if (! reg_equiv_mem[REGNO (tmp)]
6451 || num_not_at_initial_offset
6452 || GET_CODE (old) == SUBREG)
6455 real_old = reg_equiv_mem[REGNO (tmp)];
6458 second_reload_reg = rld[secondary_reload].reg_rtx;
6459 icode = rl->secondary_in_icode;
6461 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6462 || (rl->in != 0 && rl->out != 0))
6464 enum reg_class new_class
6465 = SECONDARY_INPUT_RELOAD_CLASS (rl->class,
6466 mode, real_oldequiv);
6468 if (new_class == NO_REGS)
6469 second_reload_reg = 0;
6472 enum insn_code new_icode;
6473 enum machine_mode new_mode;
6475 if (! TEST_HARD_REG_BIT (reg_class_contents[(int) new_class],
6476 REGNO (second_reload_reg)))
6477 oldequiv = old, real_oldequiv = real_old;
6480 new_icode = reload_in_optab[(int) mode];
6481 if (new_icode != CODE_FOR_nothing
6482 && ((insn_data[(int) new_icode].operand[0].predicate
6483 && ! ((*insn_data[(int) new_icode].operand[0].predicate)
6485 || (insn_data[(int) new_icode].operand[1].predicate
6486 && ! ((*insn_data[(int) new_icode].operand[1].predicate)
6487 (real_oldequiv, mode)))))
6488 new_icode = CODE_FOR_nothing;
6490 if (new_icode == CODE_FOR_nothing)
6493 new_mode = insn_data[(int) new_icode].operand[2].mode;
6495 if (GET_MODE (second_reload_reg) != new_mode)
6497 if (!HARD_REGNO_MODE_OK (REGNO (second_reload_reg),
6499 oldequiv = old, real_oldequiv = real_old;
6502 = gen_rtx_REG (new_mode,
6503 REGNO (second_reload_reg));
6509 /* If we still need a secondary reload register, check
6510 to see if it is being used as a scratch or intermediate
6511 register and generate code appropriately. If we need
6512 a scratch register, use REAL_OLDEQUIV since the form of
6513 the insn may depend on the actual address if it is
6516 if (second_reload_reg)
6518 if (icode != CODE_FOR_nothing)
6520 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6521 second_reload_reg));
6526 /* See if we need a scratch register to load the
6527 intermediate register (a tertiary reload). */
6528 enum insn_code tertiary_icode
6529 = rld[secondary_reload].secondary_in_icode;
6531 if (tertiary_icode != CODE_FOR_nothing)
6533 rtx third_reload_reg
6534 = rld[rld[secondary_reload].secondary_in_reload].reg_rtx;
6536 emit_insn ((GEN_FCN (tertiary_icode)
6537 (second_reload_reg, real_oldequiv,
6538 third_reload_reg)));
6541 gen_reload (second_reload_reg, real_oldequiv,
6545 oldequiv = second_reload_reg;
6551 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6553 rtx real_oldequiv = oldequiv;
6555 if ((GET_CODE (oldequiv) == REG
6556 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6557 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6558 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6559 || (GET_CODE (oldequiv) == SUBREG
6560 && GET_CODE (SUBREG_REG (oldequiv)) == REG
6561 && (REGNO (SUBREG_REG (oldequiv))
6562 >= FIRST_PSEUDO_REGISTER)
6563 && ((reg_equiv_memory_loc
6564 [REGNO (SUBREG_REG (oldequiv))] != 0)
6565 || (reg_equiv_constant
6566 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6567 || (CONSTANT_P (oldequiv)
6568 && PREFERRED_RELOAD_CLASS (oldequiv,
6569 REGNO_REG_CLASS (REGNO (reloadreg))) == NO_REGS))
6570 real_oldequiv = rl->in;
6571 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6575 if (flag_non_call_exceptions)
6576 copy_eh_notes (insn, get_insns ());
6578 /* End this sequence. */
6579 *where = get_insns ();
6582 /* Update reload_override_in so that delete_address_reloads_1
6583 can see the actual register usage. */
6585 reload_override_in[j] = oldequiv;
6588 /* Generate insns to for the output reload RL, which is for the insn described
6589 by CHAIN and has the number J. */
6591 emit_output_reload_insns (chain, rl, j)
6592 struct insn_chain *chain;
6596 rtx reloadreg = rl->reg_rtx;
6597 rtx insn = chain->insn;
6600 enum machine_mode mode = GET_MODE (old);
6603 if (rl->when_needed == RELOAD_OTHER)
6606 push_to_sequence (output_reload_insns[rl->opnum]);
6608 /* Determine the mode to reload in.
6609 See comments above (for input reloading). */
6611 if (mode == VOIDmode)
6613 /* VOIDmode should never happen for an output. */
6614 if (asm_noperands (PATTERN (insn)) < 0)
6615 /* It's the compiler's fault. */
6616 fatal_insn ("VOIDmode on an output", insn);
6617 error_for_asm (insn, "output operand is constant in `asm'");
6618 /* Prevent crash--use something we know is valid. */
6620 old = gen_rtx_REG (mode, REGNO (reloadreg));
6623 if (GET_MODE (reloadreg) != mode)
6624 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6626 #ifdef SECONDARY_OUTPUT_RELOAD_CLASS
6628 /* If we need two reload regs, set RELOADREG to the intermediate
6629 one, since it will be stored into OLD. We might need a secondary
6630 register only for an input reload, so check again here. */
6632 if (rl->secondary_out_reload >= 0)
6636 if (GET_CODE (old) == REG && REGNO (old) >= FIRST_PSEUDO_REGISTER
6637 && reg_equiv_mem[REGNO (old)] != 0)
6638 real_old = reg_equiv_mem[REGNO (old)];
6640 if ((SECONDARY_OUTPUT_RELOAD_CLASS (rl->class,
6644 rtx second_reloadreg = reloadreg;
6645 reloadreg = rld[rl->secondary_out_reload].reg_rtx;
6647 /* See if RELOADREG is to be used as a scratch register
6648 or as an intermediate register. */
6649 if (rl->secondary_out_icode != CODE_FOR_nothing)
6651 emit_insn ((GEN_FCN (rl->secondary_out_icode)
6652 (real_old, second_reloadreg, reloadreg)));
6657 /* See if we need both a scratch and intermediate reload
6660 int secondary_reload = rl->secondary_out_reload;
6661 enum insn_code tertiary_icode
6662 = rld[secondary_reload].secondary_out_icode;
6664 if (GET_MODE (reloadreg) != mode)
6665 reloadreg = gen_rtx_REG (mode, REGNO (reloadreg));
6667 if (tertiary_icode != CODE_FOR_nothing)
6670 = rld[rld[secondary_reload].secondary_out_reload].reg_rtx;
6673 /* Copy primary reload reg to secondary reload reg.
6674 (Note that these have been swapped above, then
6675 secondary reload reg to OLD using our insn.) */
6677 /* If REAL_OLD is a paradoxical SUBREG, remove it
6678 and try to put the opposite SUBREG on
6680 if (GET_CODE (real_old) == SUBREG
6681 && (GET_MODE_SIZE (GET_MODE (real_old))
6682 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
6683 && 0 != (tem = gen_lowpart_common
6684 (GET_MODE (SUBREG_REG (real_old)),
6686 real_old = SUBREG_REG (real_old), reloadreg = tem;
6688 gen_reload (reloadreg, second_reloadreg,
6689 rl->opnum, rl->when_needed);
6690 emit_insn ((GEN_FCN (tertiary_icode)
6691 (real_old, reloadreg, third_reloadreg)));
6696 /* Copy between the reload regs here and then to
6699 gen_reload (reloadreg, second_reloadreg,
6700 rl->opnum, rl->when_needed);
6706 /* Output the last reload insn. */
6711 /* Don't output the last reload if OLD is not the dest of
6712 INSN and is in the src and is clobbered by INSN. */
6713 if (! flag_expensive_optimizations
6714 || GET_CODE (old) != REG
6715 || !(set = single_set (insn))
6716 || rtx_equal_p (old, SET_DEST (set))
6717 || !reg_mentioned_p (old, SET_SRC (set))
6718 || !regno_clobbered_p (REGNO (old), insn, rl->mode, 0))
6719 gen_reload (old, reloadreg, rl->opnum,
6723 /* Look at all insns we emitted, just to be safe. */
6724 for (p = get_insns (); p; p = NEXT_INSN (p))
6727 rtx pat = PATTERN (p);
6729 /* If this output reload doesn't come from a spill reg,
6730 clear any memory of reloaded copies of the pseudo reg.
6731 If this output reload comes from a spill reg,
6732 reg_has_output_reload will make this do nothing. */
6733 note_stores (pat, forget_old_reloads_1, NULL);
6735 if (reg_mentioned_p (rl->reg_rtx, pat))
6737 rtx set = single_set (insn);
6738 if (reload_spill_index[j] < 0
6740 && SET_SRC (set) == rl->reg_rtx)
6742 int src = REGNO (SET_SRC (set));
6744 reload_spill_index[j] = src;
6745 SET_HARD_REG_BIT (reg_is_output_reload, src);
6746 if (find_regno_note (insn, REG_DEAD, src))
6747 SET_HARD_REG_BIT (reg_reloaded_died, src);
6749 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
6751 int s = rl->secondary_out_reload;
6752 set = single_set (p);
6753 /* If this reload copies only to the secondary reload
6754 register, the secondary reload does the actual
6756 if (s >= 0 && set == NULL_RTX)
6757 /* We can't tell what function the secondary reload
6758 has and where the actual store to the pseudo is
6759 made; leave new_spill_reg_store alone. */
6762 && SET_SRC (set) == rl->reg_rtx
6763 && SET_DEST (set) == rld[s].reg_rtx)
6765 /* Usually the next instruction will be the
6766 secondary reload insn; if we can confirm
6767 that it is, setting new_spill_reg_store to
6768 that insn will allow an extra optimization. */
6769 rtx s_reg = rld[s].reg_rtx;
6770 rtx next = NEXT_INSN (p);
6771 rld[s].out = rl->out;
6772 rld[s].out_reg = rl->out_reg;
6773 set = single_set (next);
6774 if (set && SET_SRC (set) == s_reg
6775 && ! new_spill_reg_store[REGNO (s_reg)])
6777 SET_HARD_REG_BIT (reg_is_output_reload,
6779 new_spill_reg_store[REGNO (s_reg)] = next;
6783 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
6788 if (rl->when_needed == RELOAD_OTHER)
6790 emit_insns (other_output_reload_insns[rl->opnum]);
6791 other_output_reload_insns[rl->opnum] = get_insns ();
6794 output_reload_insns[rl->opnum] = get_insns ();
6796 if (flag_non_call_exceptions)
6797 copy_eh_notes (insn, get_insns ());
6802 /* Do input reloading for reload RL, which is for the insn described by CHAIN
6803 and has the number J. */
6805 do_input_reload (chain, rl, j)
6806 struct insn_chain *chain;
6810 int expect_occurrences = 1;
6811 rtx insn = chain->insn;
6812 rtx old = (rl->in && GET_CODE (rl->in) == MEM
6813 ? rl->in_reg : rl->in);
6816 /* AUTO_INC reloads need to be handled even if inherited. We got an
6817 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
6818 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
6819 && ! rtx_equal_p (rl->reg_rtx, old)
6820 && rl->reg_rtx != 0)
6821 emit_input_reload_insns (chain, rld + j, old, j);
6823 /* When inheriting a wider reload, we have a MEM in rl->in,
6824 e.g. inheriting a SImode output reload for
6825 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
6826 if (optimize && reload_inherited[j] && rl->in
6827 && GET_CODE (rl->in) == MEM
6828 && GET_CODE (rl->in_reg) == MEM
6829 && reload_spill_index[j] >= 0
6830 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
6833 = count_occurrences (PATTERN (insn), rl->in, 0) == 1 ? 0 : -1;
6834 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
6837 /* If we are reloading a register that was recently stored in with an
6838 output-reload, see if we can prove there was
6839 actually no need to store the old value in it. */
6842 && (reload_inherited[j] || reload_override_in[j])
6844 && GET_CODE (rl->reg_rtx) == REG
6845 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
6847 /* There doesn't seem to be any reason to restrict this to pseudos
6848 and doing so loses in the case where we are copying from a
6849 register of the wrong class. */
6850 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
6851 >= FIRST_PSEUDO_REGISTER)
6853 /* The insn might have already some references to stackslots
6854 replaced by MEMs, while reload_out_reg still names the
6856 && (dead_or_set_p (insn,
6857 spill_reg_stored_to[REGNO (rl->reg_rtx)])
6858 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
6860 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
6863 /* Do output reloading for reload RL, which is for the insn described by
6864 CHAIN and has the number J.
6865 ??? At some point we need to support handling output reloads of
6866 JUMP_INSNs or insns that set cc0. */
6868 do_output_reload (chain, rl, j)
6869 struct insn_chain *chain;
6874 rtx insn = chain->insn;
6875 /* If this is an output reload that stores something that is
6876 not loaded in this same reload, see if we can eliminate a previous
6878 rtx pseudo = rl->out_reg;
6881 && GET_CODE (pseudo) == REG
6882 && ! rtx_equal_p (rl->in_reg, pseudo)
6883 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
6884 && reg_last_reload_reg[REGNO (pseudo)])
6886 int pseudo_no = REGNO (pseudo);
6887 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
6889 /* We don't need to test full validity of last_regno for
6890 inherit here; we only want to know if the store actually
6891 matches the pseudo. */
6892 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
6893 && reg_reloaded_contents[last_regno] == pseudo_no
6894 && spill_reg_store[last_regno]
6895 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
6896 delete_output_reload (insn, j, last_regno);
6901 || rl->reg_rtx == old
6902 || rl->reg_rtx == 0)
6905 /* An output operand that dies right away does need a reload,
6906 but need not be copied from it. Show the new location in the
6908 if ((GET_CODE (old) == REG || GET_CODE (old) == SCRATCH)
6909 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
6911 XEXP (note, 0) = rl->reg_rtx;
6914 /* Likewise for a SUBREG of an operand that dies. */
6915 else if (GET_CODE (old) == SUBREG
6916 && GET_CODE (SUBREG_REG (old)) == REG
6917 && 0 != (note = find_reg_note (insn, REG_UNUSED,
6920 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
6924 else if (GET_CODE (old) == SCRATCH)
6925 /* If we aren't optimizing, there won't be a REG_UNUSED note,
6926 but we don't want to make an output reload. */
6929 /* If is a JUMP_INSN, we can't support output reloads yet. */
6930 if (GET_CODE (insn) == JUMP_INSN)
6933 emit_output_reload_insns (chain, rld + j, j);
6936 /* Output insns to reload values in and out of the chosen reload regs. */
6939 emit_reload_insns (chain)
6940 struct insn_chain *chain;
6942 rtx insn = chain->insn;
6945 rtx following_insn = NEXT_INSN (insn);
6946 rtx before_insn = PREV_INSN (insn);
6948 CLEAR_HARD_REG_SET (reg_reloaded_died);
6950 for (j = 0; j < reload_n_operands; j++)
6951 input_reload_insns[j] = input_address_reload_insns[j]
6952 = inpaddr_address_reload_insns[j]
6953 = output_reload_insns[j] = output_address_reload_insns[j]
6954 = outaddr_address_reload_insns[j]
6955 = other_output_reload_insns[j] = 0;
6956 other_input_address_reload_insns = 0;
6957 other_input_reload_insns = 0;
6958 operand_reload_insns = 0;
6959 other_operand_reload_insns = 0;
6961 /* Dump reloads into the dump file. */
6964 fprintf (rtl_dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
6965 debug_reload_to_stream (rtl_dump_file);
6968 /* Now output the instructions to copy the data into and out of the
6969 reload registers. Do these in the order that the reloads were reported,
6970 since reloads of base and index registers precede reloads of operands
6971 and the operands may need the base and index registers reloaded. */
6973 for (j = 0; j < n_reloads; j++)
6976 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
6977 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
6979 do_input_reload (chain, rld + j, j);
6980 do_output_reload (chain, rld + j, j);
6983 /* Now write all the insns we made for reloads in the order expected by
6984 the allocation functions. Prior to the insn being reloaded, we write
6985 the following reloads:
6987 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
6989 RELOAD_OTHER reloads.
6991 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
6992 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
6993 RELOAD_FOR_INPUT reload for the operand.
6995 RELOAD_FOR_OPADDR_ADDRS reloads.
6997 RELOAD_FOR_OPERAND_ADDRESS reloads.
6999 After the insn being reloaded, we write the following:
7001 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7002 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7003 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7004 reloads for the operand. The RELOAD_OTHER output reloads are
7005 output in descending order by reload number. */
7007 emit_insns_before (other_input_address_reload_insns, insn);
7008 emit_insns_before (other_input_reload_insns, insn);
7010 for (j = 0; j < reload_n_operands; j++)
7012 emit_insns_before (inpaddr_address_reload_insns[j], insn);
7013 emit_insns_before (input_address_reload_insns[j], insn);
7014 emit_insns_before (input_reload_insns[j], insn);
7017 emit_insns_before (other_operand_reload_insns, insn);
7018 emit_insns_before (operand_reload_insns, insn);
7020 for (j = 0; j < reload_n_operands; j++)
7022 emit_insns_before (outaddr_address_reload_insns[j], following_insn);
7023 emit_insns_before (output_address_reload_insns[j], following_insn);
7024 emit_insns_before (output_reload_insns[j], following_insn);
7025 emit_insns_before (other_output_reload_insns[j], following_insn);
7028 /* Keep basic block info up to date. */
7031 if (BLOCK_HEAD (chain->block) == insn)
7032 BLOCK_HEAD (chain->block) = NEXT_INSN (before_insn);
7033 if (BLOCK_END (chain->block) == insn)
7034 BLOCK_END (chain->block) = PREV_INSN (following_insn);
7037 /* For all the spill regs newly reloaded in this instruction,
7038 record what they were reloaded from, so subsequent instructions
7039 can inherit the reloads.
7041 Update spill_reg_store for the reloads of this insn.
7042 Copy the elements that were updated in the loop above. */
7044 for (j = 0; j < n_reloads; j++)
7046 register int r = reload_order[j];
7047 register int i = reload_spill_index[r];
7049 /* If this is a non-inherited input reload from a pseudo, we must
7050 clear any memory of a previous store to the same pseudo. Only do
7051 something if there will not be an output reload for the pseudo
7053 if (rld[r].in_reg != 0
7054 && ! (reload_inherited[r] || reload_override_in[r]))
7056 rtx reg = rld[r].in_reg;
7058 if (GET_CODE (reg) == SUBREG)
7059 reg = SUBREG_REG (reg);
7061 if (GET_CODE (reg) == REG
7062 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7063 && ! reg_has_output_reload[REGNO (reg)])
7065 int nregno = REGNO (reg);
7067 if (reg_last_reload_reg[nregno])
7069 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7071 if (reg_reloaded_contents[last_regno] == nregno)
7072 spill_reg_store[last_regno] = 0;
7077 /* I is nonneg if this reload used a register.
7078 If rld[r].reg_rtx is 0, this is an optional reload
7079 that we opted to ignore. */
7081 if (i >= 0 && rld[r].reg_rtx != 0)
7083 int nr = HARD_REGNO_NREGS (i, GET_MODE (rld[r].reg_rtx));
7085 int part_reaches_end = 0;
7086 int all_reaches_end = 1;
7088 /* For a multi register reload, we need to check if all or part
7089 of the value lives to the end. */
7090 for (k = 0; k < nr; k++)
7092 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7093 rld[r].when_needed))
7094 part_reaches_end = 1;
7096 all_reaches_end = 0;
7099 /* Ignore reloads that don't reach the end of the insn in
7101 if (all_reaches_end)
7103 /* First, clear out memory of what used to be in this spill reg.
7104 If consecutive registers are used, clear them all. */
7106 for (k = 0; k < nr; k++)
7107 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7109 /* Maybe the spill reg contains a copy of reload_out. */
7111 && (GET_CODE (rld[r].out) == REG
7115 || GET_CODE (rld[r].out_reg) == REG))
7117 rtx out = (GET_CODE (rld[r].out) == REG
7121 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7122 register int nregno = REGNO (out);
7123 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7124 : HARD_REGNO_NREGS (nregno,
7125 GET_MODE (rld[r].reg_rtx)));
7127 spill_reg_store[i] = new_spill_reg_store[i];
7128 spill_reg_stored_to[i] = out;
7129 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7131 /* If NREGNO is a hard register, it may occupy more than
7132 one register. If it does, say what is in the
7133 rest of the registers assuming that both registers
7134 agree on how many words the object takes. If not,
7135 invalidate the subsequent registers. */
7137 if (nregno < FIRST_PSEUDO_REGISTER)
7138 for (k = 1; k < nnr; k++)
7139 reg_last_reload_reg[nregno + k]
7141 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7142 REGNO (rld[r].reg_rtx) + k)
7145 /* Now do the inverse operation. */
7146 for (k = 0; k < nr; k++)
7148 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7149 reg_reloaded_contents[i + k]
7150 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7153 reg_reloaded_insn[i + k] = insn;
7154 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7158 /* Maybe the spill reg contains a copy of reload_in. Only do
7159 something if there will not be an output reload for
7160 the register being reloaded. */
7161 else if (rld[r].out_reg == 0
7163 && ((GET_CODE (rld[r].in) == REG
7164 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7165 && ! reg_has_output_reload[REGNO (rld[r].in)])
7166 || (GET_CODE (rld[r].in_reg) == REG
7167 && ! reg_has_output_reload[REGNO (rld[r].in_reg)]))
7168 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7170 register int nregno;
7173 if (GET_CODE (rld[r].in) == REG
7174 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7175 nregno = REGNO (rld[r].in);
7176 else if (GET_CODE (rld[r].in_reg) == REG)
7177 nregno = REGNO (rld[r].in_reg);
7179 nregno = REGNO (XEXP (rld[r].in_reg, 0));
7181 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7182 : HARD_REGNO_NREGS (nregno,
7183 GET_MODE (rld[r].reg_rtx)));
7185 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7187 if (nregno < FIRST_PSEUDO_REGISTER)
7188 for (k = 1; k < nnr; k++)
7189 reg_last_reload_reg[nregno + k]
7191 ? gen_rtx_REG (reg_raw_mode[REGNO (rld[r].reg_rtx) + k],
7192 REGNO (rld[r].reg_rtx) + k)
7195 /* Unless we inherited this reload, show we haven't
7196 recently done a store.
7197 Previous stores of inherited auto_inc expressions
7198 also have to be discarded. */
7199 if (! reload_inherited[r]
7200 || (rld[r].out && ! rld[r].out_reg))
7201 spill_reg_store[i] = 0;
7203 for (k = 0; k < nr; k++)
7205 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7206 reg_reloaded_contents[i + k]
7207 = (nregno >= FIRST_PSEUDO_REGISTER || nr != nnr
7210 reg_reloaded_insn[i + k] = insn;
7211 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7216 /* However, if part of the reload reaches the end, then we must
7217 invalidate the old info for the part that survives to the end. */
7218 else if (part_reaches_end)
7220 for (k = 0; k < nr; k++)
7221 if (reload_reg_reaches_end_p (i + k,
7223 rld[r].when_needed))
7224 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7228 /* The following if-statement was #if 0'd in 1.34 (or before...).
7229 It's reenabled in 1.35 because supposedly nothing else
7230 deals with this problem. */
7232 /* If a register gets output-reloaded from a non-spill register,
7233 that invalidates any previous reloaded copy of it.
7234 But forget_old_reloads_1 won't get to see it, because
7235 it thinks only about the original insn. So invalidate it here. */
7236 if (i < 0 && rld[r].out != 0
7237 && (GET_CODE (rld[r].out) == REG
7238 || (GET_CODE (rld[r].out) == MEM
7239 && GET_CODE (rld[r].out_reg) == REG)))
7241 rtx out = (GET_CODE (rld[r].out) == REG
7242 ? rld[r].out : rld[r].out_reg);
7243 register int nregno = REGNO (out);
7244 if (nregno >= FIRST_PSEUDO_REGISTER)
7246 rtx src_reg, store_insn = NULL_RTX;
7248 reg_last_reload_reg[nregno] = 0;
7250 /* If we can find a hard register that is stored, record
7251 the storing insn so that we may delete this insn with
7252 delete_output_reload. */
7253 src_reg = rld[r].reg_rtx;
7255 /* If this is an optional reload, try to find the source reg
7256 from an input reload. */
7259 rtx set = single_set (insn);
7260 if (set && SET_DEST (set) == rld[r].out)
7264 src_reg = SET_SRC (set);
7266 for (k = 0; k < n_reloads; k++)
7268 if (rld[k].in == src_reg)
7270 src_reg = rld[k].reg_rtx;
7277 store_insn = new_spill_reg_store[REGNO (src_reg)];
7278 if (src_reg && GET_CODE (src_reg) == REG
7279 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7281 int src_regno = REGNO (src_reg);
7282 int nr = HARD_REGNO_NREGS (src_regno, rld[r].mode);
7283 /* The place where to find a death note varies with
7284 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7285 necessarily checked exactly in the code that moves
7286 notes, so just check both locations. */
7287 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7289 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7292 spill_reg_store[src_regno + nr] = store_insn;
7293 spill_reg_stored_to[src_regno + nr] = out;
7294 reg_reloaded_contents[src_regno + nr] = nregno;
7295 reg_reloaded_insn[src_regno + nr] = store_insn;
7296 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7297 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7298 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7300 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7302 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7304 reg_last_reload_reg[nregno] = src_reg;
7309 int num_regs = HARD_REGNO_NREGS (nregno, GET_MODE (rld[r].out));
7311 while (num_regs-- > 0)
7312 reg_last_reload_reg[nregno + num_regs] = 0;
7316 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7319 /* Emit code to perform a reload from IN (which may be a reload register) to
7320 OUT (which may also be a reload register). IN or OUT is from operand
7321 OPNUM with reload type TYPE.
7323 Returns first insn emitted. */
7326 gen_reload (out, in, opnum, type)
7330 enum reload_type type;
7332 rtx last = get_last_insn ();
7335 /* If IN is a paradoxical SUBREG, remove it and try to put the
7336 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7337 if (GET_CODE (in) == SUBREG
7338 && (GET_MODE_SIZE (GET_MODE (in))
7339 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7340 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7341 in = SUBREG_REG (in), out = tem;
7342 else if (GET_CODE (out) == SUBREG
7343 && (GET_MODE_SIZE (GET_MODE (out))
7344 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7345 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7346 out = SUBREG_REG (out), in = tem;
7348 /* How to do this reload can get quite tricky. Normally, we are being
7349 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7350 register that didn't get a hard register. In that case we can just
7351 call emit_move_insn.
7353 We can also be asked to reload a PLUS that adds a register or a MEM to
7354 another register, constant or MEM. This can occur during frame pointer
7355 elimination and while reloading addresses. This case is handled by
7356 trying to emit a single insn to perform the add. If it is not valid,
7357 we use a two insn sequence.
7359 Finally, we could be called to handle an 'o' constraint by putting
7360 an address into a register. In that case, we first try to do this
7361 with a named pattern of "reload_load_address". If no such pattern
7362 exists, we just emit a SET insn and hope for the best (it will normally
7363 be valid on machines that use 'o').
7365 This entire process is made complex because reload will never
7366 process the insns we generate here and so we must ensure that
7367 they will fit their constraints and also by the fact that parts of
7368 IN might be being reloaded separately and replaced with spill registers.
7369 Because of this, we are, in some sense, just guessing the right approach
7370 here. The one listed above seems to work.
7372 ??? At some point, this whole thing needs to be rethought. */
7374 if (GET_CODE (in) == PLUS
7375 && (GET_CODE (XEXP (in, 0)) == REG
7376 || GET_CODE (XEXP (in, 0)) == SUBREG
7377 || GET_CODE (XEXP (in, 0)) == MEM)
7378 && (GET_CODE (XEXP (in, 1)) == REG
7379 || GET_CODE (XEXP (in, 1)) == SUBREG
7380 || CONSTANT_P (XEXP (in, 1))
7381 || GET_CODE (XEXP (in, 1)) == MEM))
7383 /* We need to compute the sum of a register or a MEM and another
7384 register, constant, or MEM, and put it into the reload
7385 register. The best possible way of doing this is if the machine
7386 has a three-operand ADD insn that accepts the required operands.
7388 The simplest approach is to try to generate such an insn and see if it
7389 is recognized and matches its constraints. If so, it can be used.
7391 It might be better not to actually emit the insn unless it is valid,
7392 but we need to pass the insn as an operand to `recog' and
7393 `extract_insn' and it is simpler to emit and then delete the insn if
7394 not valid than to dummy things up. */
7396 rtx op0, op1, tem, insn;
7399 op0 = find_replacement (&XEXP (in, 0));
7400 op1 = find_replacement (&XEXP (in, 1));
7402 /* Since constraint checking is strict, commutativity won't be
7403 checked, so we need to do that here to avoid spurious failure
7404 if the add instruction is two-address and the second operand
7405 of the add is the same as the reload reg, which is frequently
7406 the case. If the insn would be A = B + A, rearrange it so
7407 it will be A = A + B as constrain_operands expects. */
7409 if (GET_CODE (XEXP (in, 1)) == REG
7410 && REGNO (out) == REGNO (XEXP (in, 1)))
7411 tem = op0, op0 = op1, op1 = tem;
7413 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7414 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7416 insn = emit_insn (gen_rtx_SET (VOIDmode, out, in));
7417 code = recog_memoized (insn);
7421 extract_insn (insn);
7422 /* We want constrain operands to treat this insn strictly in
7423 its validity determination, i.e., the way it would after reload
7425 if (constrain_operands (1))
7429 delete_insns_since (last);
7431 /* If that failed, we must use a conservative two-insn sequence.
7433 Use a move to copy one operand into the reload register. Prefer
7434 to reload a constant, MEM or pseudo since the move patterns can
7435 handle an arbitrary operand. If OP1 is not a constant, MEM or
7436 pseudo and OP1 is not a valid operand for an add instruction, then
7439 After reloading one of the operands into the reload register, add
7440 the reload register to the output register.
7442 If there is another way to do this for a specific machine, a
7443 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7446 code = (int) add_optab->handlers[(int) GET_MODE (out)].insn_code;
7448 if (CONSTANT_P (op1) || GET_CODE (op1) == MEM || GET_CODE (op1) == SUBREG
7449 || (GET_CODE (op1) == REG
7450 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7451 || (code != CODE_FOR_nothing
7452 && ! ((*insn_data[code].operand[2].predicate)
7453 (op1, insn_data[code].operand[2].mode))))
7454 tem = op0, op0 = op1, op1 = tem;
7456 gen_reload (out, op0, opnum, type);
7458 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7459 This fixes a problem on the 32K where the stack pointer cannot
7460 be used as an operand of an add insn. */
7462 if (rtx_equal_p (op0, op1))
7465 insn = emit_insn (gen_add2_insn (out, op1));
7467 /* If that failed, copy the address register to the reload register.
7468 Then add the constant to the reload register. */
7470 code = recog_memoized (insn);
7474 extract_insn (insn);
7475 /* We want constrain operands to treat this insn strictly in
7476 its validity determination, i.e., the way it would after reload
7478 if (constrain_operands (1))
7480 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7482 = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7487 delete_insns_since (last);
7489 gen_reload (out, op1, opnum, type);
7490 insn = emit_insn (gen_add2_insn (out, op0));
7491 REG_NOTES (insn) = gen_rtx_EXPR_LIST (REG_EQUIV, in, REG_NOTES (insn));
7494 #ifdef SECONDARY_MEMORY_NEEDED
7495 /* If we need a memory location to do the move, do it that way. */
7496 else if (GET_CODE (in) == REG && REGNO (in) < FIRST_PSEUDO_REGISTER
7497 && GET_CODE (out) == REG && REGNO (out) < FIRST_PSEUDO_REGISTER
7498 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (REGNO (in)),
7499 REGNO_REG_CLASS (REGNO (out)),
7502 /* Get the memory to use and rewrite both registers to its mode. */
7503 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7505 if (GET_MODE (loc) != GET_MODE (out))
7506 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7508 if (GET_MODE (loc) != GET_MODE (in))
7509 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
7511 gen_reload (loc, in, opnum, type);
7512 gen_reload (out, loc, opnum, type);
7516 /* If IN is a simple operand, use gen_move_insn. */
7517 else if (GET_RTX_CLASS (GET_CODE (in)) == 'o' || GET_CODE (in) == SUBREG)
7518 emit_insn (gen_move_insn (out, in));
7520 #ifdef HAVE_reload_load_address
7521 else if (HAVE_reload_load_address)
7522 emit_insn (gen_reload_load_address (out, in));
7525 /* Otherwise, just write (set OUT IN) and hope for the best. */
7527 emit_insn (gen_rtx_SET (VOIDmode, out, in));
7529 /* Return the first insn emitted.
7530 We can not just return get_last_insn, because there may have
7531 been multiple instructions emitted. Also note that gen_move_insn may
7532 emit more than one insn itself, so we can not assume that there is one
7533 insn emitted per emit_insn_before call. */
7535 return last ? NEXT_INSN (last) : get_insns ();
7538 /* Delete a previously made output-reload
7539 whose result we now believe is not needed.
7540 First we double-check.
7542 INSN is the insn now being processed.
7543 LAST_RELOAD_REG is the hard register number for which we want to delete
7544 the last output reload.
7545 J is the reload-number that originally used REG. The caller has made
7546 certain that reload J doesn't use REG any longer for input. */
7549 delete_output_reload (insn, j, last_reload_reg)
7552 int last_reload_reg;
7554 rtx output_reload_insn = spill_reg_store[last_reload_reg];
7555 rtx reg = spill_reg_stored_to[last_reload_reg];
7558 int n_inherited = 0;
7562 /* Get the raw pseudo-register referred to. */
7564 while (GET_CODE (reg) == SUBREG)
7565 reg = SUBREG_REG (reg);
7566 substed = reg_equiv_memory_loc[REGNO (reg)];
7568 /* This is unsafe if the operand occurs more often in the current
7569 insn than it is inherited. */
7570 for (k = n_reloads - 1; k >= 0; k--)
7572 rtx reg2 = rld[k].in;
7575 if (GET_CODE (reg2) == MEM || reload_override_in[k])
7576 reg2 = rld[k].in_reg;
7578 if (rld[k].out && ! rld[k].out_reg)
7579 reg2 = XEXP (rld[k].in_reg, 0);
7581 while (GET_CODE (reg2) == SUBREG)
7582 reg2 = SUBREG_REG (reg2);
7583 if (rtx_equal_p (reg2, reg))
7585 if (reload_inherited[k] || reload_override_in[k] || k == j)
7588 reg2 = rld[k].out_reg;
7591 while (GET_CODE (reg2) == SUBREG)
7592 reg2 = XEXP (reg2, 0);
7593 if (rtx_equal_p (reg2, reg))
7600 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
7602 n_occurrences += count_occurrences (PATTERN (insn), substed, 0);
7603 if (n_occurrences > n_inherited)
7606 /* If the pseudo-reg we are reloading is no longer referenced
7607 anywhere between the store into it and here,
7608 and no jumps or labels intervene, then the value can get
7609 here through the reload reg alone.
7610 Otherwise, give up--return. */
7611 for (i1 = NEXT_INSN (output_reload_insn);
7612 i1 != insn; i1 = NEXT_INSN (i1))
7614 if (GET_CODE (i1) == CODE_LABEL || GET_CODE (i1) == JUMP_INSN)
7616 if ((GET_CODE (i1) == INSN || GET_CODE (i1) == CALL_INSN)
7617 && reg_mentioned_p (reg, PATTERN (i1)))
7619 /* If this is USE in front of INSN, we only have to check that
7620 there are no more references than accounted for by inheritance. */
7621 while (GET_CODE (i1) == INSN && GET_CODE (PATTERN (i1)) == USE)
7623 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
7624 i1 = NEXT_INSN (i1);
7626 if (n_occurrences <= n_inherited && i1 == insn)
7632 /* The caller has already checked that REG dies or is set in INSN.
7633 It has also checked that we are optimizing, and thus some inaccurancies
7634 in the debugging information are acceptable.
7635 So we could just delete output_reload_insn.
7636 But in some cases we can improve the debugging information without
7637 sacrificing optimization - maybe even improving the code:
7638 See if the pseudo reg has been completely replaced
7639 with reload regs. If so, delete the store insn
7640 and forget we had a stack slot for the pseudo. */
7641 if (rld[j].out != rld[j].in
7642 && REG_N_DEATHS (REGNO (reg)) == 1
7643 && REG_N_SETS (REGNO (reg)) == 1
7644 && REG_BASIC_BLOCK (REGNO (reg)) >= 0
7645 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
7649 /* We know that it was used only between here
7650 and the beginning of the current basic block.
7651 (We also know that the last use before INSN was
7652 the output reload we are thinking of deleting, but never mind that.)
7653 Search that range; see if any ref remains. */
7654 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7656 rtx set = single_set (i2);
7658 /* Uses which just store in the pseudo don't count,
7659 since if they are the only uses, they are dead. */
7660 if (set != 0 && SET_DEST (set) == reg)
7662 if (GET_CODE (i2) == CODE_LABEL
7663 || GET_CODE (i2) == JUMP_INSN)
7665 if ((GET_CODE (i2) == INSN || GET_CODE (i2) == CALL_INSN)
7666 && reg_mentioned_p (reg, PATTERN (i2)))
7668 /* Some other ref remains; just delete the output reload we
7670 delete_address_reloads (output_reload_insn, insn);
7671 PUT_CODE (output_reload_insn, NOTE);
7672 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7673 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7678 /* Delete the now-dead stores into this pseudo. */
7679 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
7681 rtx set = single_set (i2);
7683 if (set != 0 && SET_DEST (set) == reg)
7685 delete_address_reloads (i2, insn);
7686 /* This might be a basic block head,
7687 thus don't use delete_insn. */
7688 PUT_CODE (i2, NOTE);
7689 NOTE_SOURCE_FILE (i2) = 0;
7690 NOTE_LINE_NUMBER (i2) = NOTE_INSN_DELETED;
7692 if (GET_CODE (i2) == CODE_LABEL
7693 || GET_CODE (i2) == JUMP_INSN)
7697 /* For the debugging info,
7698 say the pseudo lives in this reload reg. */
7699 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
7700 alter_reg (REGNO (reg), -1);
7702 delete_address_reloads (output_reload_insn, insn);
7703 PUT_CODE (output_reload_insn, NOTE);
7704 NOTE_SOURCE_FILE (output_reload_insn) = 0;
7705 NOTE_LINE_NUMBER (output_reload_insn) = NOTE_INSN_DELETED;
7709 /* We are going to delete DEAD_INSN. Recursively delete loads of
7710 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
7711 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
7713 delete_address_reloads (dead_insn, current_insn)
7714 rtx dead_insn, current_insn;
7716 rtx set = single_set (dead_insn);
7717 rtx set2, dst, prev, next;
7720 rtx dst = SET_DEST (set);
7721 if (GET_CODE (dst) == MEM)
7722 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
7724 /* If we deleted the store from a reloaded post_{in,de}c expression,
7725 we can delete the matching adds. */
7726 prev = PREV_INSN (dead_insn);
7727 next = NEXT_INSN (dead_insn);
7728 if (! prev || ! next)
7730 set = single_set (next);
7731 set2 = single_set (prev);
7733 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
7734 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
7735 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
7737 dst = SET_DEST (set);
7738 if (! rtx_equal_p (dst, SET_DEST (set2))
7739 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
7740 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
7741 || (INTVAL (XEXP (SET_SRC (set), 1))
7742 != -INTVAL (XEXP (SET_SRC (set2), 1))))
7748 /* Subfunction of delete_address_reloads: process registers found in X. */
7750 delete_address_reloads_1 (dead_insn, x, current_insn)
7751 rtx dead_insn, x, current_insn;
7753 rtx prev, set, dst, i2;
7755 enum rtx_code code = GET_CODE (x);
7759 const char *fmt = GET_RTX_FORMAT (code);
7760 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
7763 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
7764 else if (fmt[i] == 'E')
7766 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
7767 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
7774 if (spill_reg_order[REGNO (x)] < 0)
7777 /* Scan backwards for the insn that sets x. This might be a way back due
7779 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
7781 code = GET_CODE (prev);
7782 if (code == CODE_LABEL || code == JUMP_INSN)
7784 if (GET_RTX_CLASS (code) != 'i')
7786 if (reg_set_p (x, PATTERN (prev)))
7788 if (reg_referenced_p (x, PATTERN (prev)))
7791 if (! prev || INSN_UID (prev) < reload_first_uid)
7793 /* Check that PREV only sets the reload register. */
7794 set = single_set (prev);
7797 dst = SET_DEST (set);
7798 if (GET_CODE (dst) != REG
7799 || ! rtx_equal_p (dst, x))
7801 if (! reg_set_p (dst, PATTERN (dead_insn)))
7803 /* Check if DST was used in a later insn -
7804 it might have been inherited. */
7805 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
7807 if (GET_CODE (i2) == CODE_LABEL)
7811 if (reg_referenced_p (dst, PATTERN (i2)))
7813 /* If there is a reference to the register in the current insn,
7814 it might be loaded in a non-inherited reload. If no other
7815 reload uses it, that means the register is set before
7817 if (i2 == current_insn)
7819 for (j = n_reloads - 1; j >= 0; j--)
7820 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7821 || reload_override_in[j] == dst)
7823 for (j = n_reloads - 1; j >= 0; j--)
7824 if (rld[j].in && rld[j].reg_rtx == dst)
7831 if (GET_CODE (i2) == JUMP_INSN)
7833 /* If DST is still live at CURRENT_INSN, check if it is used for
7834 any reload. Note that even if CURRENT_INSN sets DST, we still
7835 have to check the reloads. */
7836 if (i2 == current_insn)
7838 for (j = n_reloads - 1; j >= 0; j--)
7839 if ((rld[j].reg_rtx == dst && reload_inherited[j])
7840 || reload_override_in[j] == dst)
7842 /* ??? We can't finish the loop here, because dst might be
7843 allocated to a pseudo in this block if no reload in this
7844 block needs any of the clsses containing DST - see
7845 spill_hard_reg. There is no easy way to tell this, so we
7846 have to scan till the end of the basic block. */
7848 if (reg_set_p (dst, PATTERN (i2)))
7852 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
7853 reg_reloaded_contents[REGNO (dst)] = -1;
7854 /* Can't use delete_insn here because PREV might be a basic block head. */
7855 PUT_CODE (prev, NOTE);
7856 NOTE_LINE_NUMBER (prev) = NOTE_INSN_DELETED;
7857 NOTE_SOURCE_FILE (prev) = 0;
7860 /* Output reload-insns to reload VALUE into RELOADREG.
7861 VALUE is an autoincrement or autodecrement RTX whose operand
7862 is a register or memory location;
7863 so reloading involves incrementing that location.
7864 IN is either identical to VALUE, or some cheaper place to reload from.
7866 INC_AMOUNT is the number to increment or decrement by (always positive).
7867 This cannot be deduced from VALUE.
7869 Return the instruction that stores into RELOADREG. */
7872 inc_for_reload (reloadreg, in, value, inc_amount)
7877 /* REG or MEM to be copied and incremented. */
7878 rtx incloc = XEXP (value, 0);
7879 /* Nonzero if increment after copying. */
7880 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC);
7886 rtx real_in = in == value ? XEXP (in, 0) : in;
7888 /* No hard register is equivalent to this register after
7889 inc/dec operation. If REG_LAST_RELOAD_REG were non-zero,
7890 we could inc/dec that register as well (maybe even using it for
7891 the source), but I'm not sure it's worth worrying about. */
7892 if (GET_CODE (incloc) == REG)
7893 reg_last_reload_reg[REGNO (incloc)] = 0;
7895 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
7896 inc_amount = -inc_amount;
7898 inc = GEN_INT (inc_amount);
7900 /* If this is post-increment, first copy the location to the reload reg. */
7901 if (post && real_in != reloadreg)
7902 emit_insn (gen_move_insn (reloadreg, real_in));
7906 /* See if we can directly increment INCLOC. Use a method similar to
7907 that in gen_reload. */
7909 last = get_last_insn ();
7910 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
7911 gen_rtx_PLUS (GET_MODE (incloc),
7914 code = recog_memoized (add_insn);
7917 extract_insn (add_insn);
7918 if (constrain_operands (1))
7920 /* If this is a pre-increment and we have incremented the value
7921 where it lives, copy the incremented value to RELOADREG to
7922 be used as an address. */
7925 emit_insn (gen_move_insn (reloadreg, incloc));
7930 delete_insns_since (last);
7933 /* If couldn't do the increment directly, must increment in RELOADREG.
7934 The way we do this depends on whether this is pre- or post-increment.
7935 For pre-increment, copy INCLOC to the reload register, increment it
7936 there, then save back. */
7940 if (in != reloadreg)
7941 emit_insn (gen_move_insn (reloadreg, real_in));
7942 emit_insn (gen_add2_insn (reloadreg, inc));
7943 store = emit_insn (gen_move_insn (incloc, reloadreg));
7948 Because this might be a jump insn or a compare, and because RELOADREG
7949 may not be available after the insn in an input reload, we must do
7950 the incrementation before the insn being reloaded for.
7952 We have already copied IN to RELOADREG. Increment the copy in
7953 RELOADREG, save that back, then decrement RELOADREG so it has
7954 the original value. */
7956 emit_insn (gen_add2_insn (reloadreg, inc));
7957 store = emit_insn (gen_move_insn (incloc, reloadreg));
7958 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-inc_amount)));
7964 /* Return 1 if we are certain that the constraint-string STRING allows
7965 the hard register REG. Return 0 if we can't be sure of this. */
7968 constraint_accepts_reg_p (string, reg)
7973 int regno = true_regnum (reg);
7976 /* Initialize for first alternative. */
7978 /* Check that each alternative contains `g' or `r'. */
7980 switch (c = *string++)
7983 /* If an alternative lacks `g' or `r', we lose. */
7986 /* If an alternative lacks `g' or `r', we lose. */
7989 /* Initialize for next alternative. */
7994 /* Any general reg wins for this alternative. */
7995 if (TEST_HARD_REG_BIT (reg_class_contents[(int) GENERAL_REGS], regno))
7999 /* Any reg in specified class wins for this alternative. */
8001 enum reg_class class = REG_CLASS_FROM_LETTER (c);
8003 if (TEST_HARD_REG_BIT (reg_class_contents[(int) class], regno))
8009 /* INSN is a no-op; delete it.
8010 If this sets the return value of the function, we must keep a USE around,
8011 in case this is in a different basic block than the final USE. Otherwise,
8012 we could loose important register lifeness information on
8013 SMALL_REGISTER_CLASSES machines, where return registers might be used as
8014 spills: subsequent passes assume that spill registers are dead at the end
8016 VALUE must be the return value in such a case, NULL otherwise. */
8018 reload_cse_delete_noop_set (insn, value)
8023 PATTERN (insn) = gen_rtx_USE (VOIDmode, value);
8024 INSN_CODE (insn) = -1;
8025 REG_NOTES (insn) = NULL_RTX;
8029 PUT_CODE (insn, NOTE);
8030 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8031 NOTE_SOURCE_FILE (insn) = 0;
8035 /* See whether a single set SET is a noop. */
8037 reload_cse_noop_set_p (set)
8040 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set));
8043 /* Try to simplify INSN. */
8045 reload_cse_simplify (insn)
8048 rtx body = PATTERN (insn);
8050 if (GET_CODE (body) == SET)
8054 /* Simplify even if we may think it is a no-op.
8055 We may think a memory load of a value smaller than WORD_SIZE
8056 is redundant because we haven't taken into account possible
8057 implicit extension. reload_cse_simplify_set() will bring
8058 this out, so it's safer to simplify before we delete. */
8059 count += reload_cse_simplify_set (body, insn);
8061 if (!count && reload_cse_noop_set_p (body))
8063 rtx value = SET_DEST (body);
8064 if (! REG_FUNCTION_VALUE_P (SET_DEST (body)))
8066 reload_cse_delete_noop_set (insn, value);
8071 apply_change_group ();
8073 reload_cse_simplify_operands (insn);
8075 else if (GET_CODE (body) == PARALLEL)
8079 rtx value = NULL_RTX;
8081 /* If every action in a PARALLEL is a noop, we can delete
8082 the entire PARALLEL. */
8083 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8085 rtx part = XVECEXP (body, 0, i);
8086 if (GET_CODE (part) == SET)
8088 if (! reload_cse_noop_set_p (part))
8090 if (REG_FUNCTION_VALUE_P (SET_DEST (part)))
8094 value = SET_DEST (part);
8097 else if (GET_CODE (part) != CLOBBER)
8103 reload_cse_delete_noop_set (insn, value);
8104 /* We're done with this insn. */
8108 /* It's not a no-op, but we can try to simplify it. */
8109 for (i = XVECLEN (body, 0) - 1; i >= 0; --i)
8110 if (GET_CODE (XVECEXP (body, 0, i)) == SET)
8111 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn);
8114 apply_change_group ();
8116 reload_cse_simplify_operands (insn);
8120 /* Do a very simple CSE pass over the hard registers.
8122 This function detects no-op moves where we happened to assign two
8123 different pseudo-registers to the same hard register, and then
8124 copied one to the other. Reload will generate a useless
8125 instruction copying a register to itself.
8127 This function also detects cases where we load a value from memory
8128 into two different registers, and (if memory is more expensive than
8129 registers) changes it to simply copy the first register into the
8132 Another optimization is performed that scans the operands of each
8133 instruction to see whether the value is already available in a
8134 hard register. It then replaces the operand with the hard register
8135 if possible, much like an optional reload would. */
8138 reload_cse_regs_1 (first)
8144 init_alias_analysis ();
8146 for (insn = first; insn; insn = NEXT_INSN (insn))
8149 reload_cse_simplify (insn);
8151 cselib_process_insn (insn);
8155 end_alias_analysis ();
8159 /* Call cse / combine like post-reload optimization phases.
8160 FIRST is the first instruction. */
8162 reload_cse_regs (first)
8165 reload_cse_regs_1 (first);
8167 reload_cse_move2add (first);
8168 if (flag_expensive_optimizations)
8169 reload_cse_regs_1 (first);
8172 /* Try to simplify a single SET instruction. SET is the set pattern.
8173 INSN is the instruction it came from.
8174 This function only handles one case: if we set a register to a value
8175 which is not a register, we try to find that value in some other register
8176 and change the set into a register copy. */
8179 reload_cse_simplify_set (set, insn)
8186 enum reg_class dclass;
8189 struct elt_loc_list *l;
8190 #ifdef LOAD_EXTEND_OP
8191 enum rtx_code extend_op = NIL;
8194 dreg = true_regnum (SET_DEST (set));
8198 src = SET_SRC (set);
8199 if (side_effects_p (src) || true_regnum (src) >= 0)
8202 dclass = REGNO_REG_CLASS (dreg);
8204 #ifdef LOAD_EXTEND_OP
8205 /* When replacing a memory with a register, we need to honor assumptions
8206 that combine made wrt the contents of sign bits. We'll do this by
8207 generating an extend instruction instead of a reg->reg copy. Thus
8208 the destination must be a register that we can widen. */
8209 if (GET_CODE (src) == MEM
8210 && GET_MODE_BITSIZE (GET_MODE (src)) < BITS_PER_WORD
8211 && (extend_op = LOAD_EXTEND_OP (GET_MODE (src))) != NIL
8212 && GET_CODE (SET_DEST (set)) != REG)
8216 /* If memory loads are cheaper than register copies, don't change them. */
8217 if (GET_CODE (src) == MEM)
8218 old_cost = MEMORY_MOVE_COST (GET_MODE (src), dclass, 1);
8219 else if (CONSTANT_P (src))
8220 old_cost = rtx_cost (src, SET);
8221 else if (GET_CODE (src) == REG)
8222 old_cost = REGISTER_MOVE_COST (GET_MODE (src),
8223 REGNO_REG_CLASS (REGNO (src)), dclass);
8226 old_cost = rtx_cost (src, SET);
8228 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0);
8231 for (l = val->locs; l; l = l->next)
8233 rtx this_rtx = l->loc;
8236 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0))
8238 #ifdef LOAD_EXTEND_OP
8239 if (extend_op != NIL)
8241 HOST_WIDE_INT this_val;
8243 /* ??? I'm lazy and don't wish to handle CONST_DOUBLE. Other
8244 constants, such as SYMBOL_REF, cannot be extended. */
8245 if (GET_CODE (this_rtx) != CONST_INT)
8248 this_val = INTVAL (this_rtx);
8252 this_val &= GET_MODE_MASK (GET_MODE (src));
8255 /* ??? In theory we're already extended. */
8256 if (this_val == trunc_int_for_mode (this_val, GET_MODE (src)))
8261 this_rtx = GEN_INT (this_val);
8264 this_cost = rtx_cost (this_rtx, SET);
8266 else if (GET_CODE (this_rtx) == REG)
8268 #ifdef LOAD_EXTEND_OP
8269 if (extend_op != NIL)
8271 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx);
8272 this_cost = rtx_cost (this_rtx, SET);
8276 this_cost = REGISTER_MOVE_COST (GET_MODE (this_rtx),
8277 REGNO_REG_CLASS (REGNO (this_rtx)),
8283 /* If equal costs, prefer registers over anything else. That
8284 tends to lead to smaller instructions on some machines. */
8285 if (this_cost < old_cost
8286 || (this_cost == old_cost
8287 && GET_CODE (this_rtx) == REG
8288 && GET_CODE (SET_SRC (set)) != REG))
8290 #ifdef LOAD_EXTEND_OP
8291 if (GET_MODE_BITSIZE (GET_MODE (SET_DEST (set))) < BITS_PER_WORD
8292 && extend_op != NIL)
8294 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set)));
8295 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set));
8296 validate_change (insn, &SET_DEST (set), wide_dest, 1);
8300 validate_change (insn, &SET_SRC (set), copy_rtx (this_rtx), 1);
8301 old_cost = this_cost, did_change = 1;
8308 /* Try to replace operands in INSN with equivalent values that are already
8309 in registers. This can be viewed as optional reloading.
8311 For each non-register operand in the insn, see if any hard regs are
8312 known to be equivalent to that operand. Record the alternatives which
8313 can accept these hard registers. Among all alternatives, select the
8314 ones which are better or equal to the one currently matching, where
8315 "better" is in terms of '?' and '!' constraints. Among the remaining
8316 alternatives, select the one which replaces most operands with
8320 reload_cse_simplify_operands (insn)
8325 /* For each operand, all registers that are equivalent to it. */
8326 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS];
8328 const char *constraints[MAX_RECOG_OPERANDS];
8330 /* Vector recording how bad an alternative is. */
8331 int *alternative_reject;
8332 /* Vector recording how many registers can be introduced by choosing
8333 this alternative. */
8334 int *alternative_nregs;
8335 /* Array of vectors recording, for each operand and each alternative,
8336 which hard register to substitute, or -1 if the operand should be
8338 int *op_alt_regno[MAX_RECOG_OPERANDS];
8339 /* Array of alternatives, sorted in order of decreasing desirability. */
8340 int *alternative_order;
8341 rtx reg = gen_rtx_REG (VOIDmode, -1);
8343 extract_insn (insn);
8345 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0)
8348 /* Figure out which alternative currently matches. */
8349 if (! constrain_operands (1))
8350 fatal_insn_not_found (insn);
8352 alternative_reject = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8353 alternative_nregs = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8354 alternative_order = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8355 memset ((char *)alternative_reject, 0, recog_data.n_alternatives * sizeof (int));
8356 memset ((char *)alternative_nregs, 0, recog_data.n_alternatives * sizeof (int));
8358 /* For each operand, find out which regs are equivalent. */
8359 for (i = 0; i < recog_data.n_operands; i++)
8362 struct elt_loc_list *l;
8364 CLEAR_HARD_REG_SET (equiv_regs[i]);
8366 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem
8367 right, so avoid the problem here. Likewise if we have a constant
8368 and the insn pattern doesn't tell us the mode we need. */
8369 if (GET_CODE (recog_data.operand[i]) == CODE_LABEL
8370 || (CONSTANT_P (recog_data.operand[i])
8371 && recog_data.operand_mode[i] == VOIDmode))
8374 v = cselib_lookup (recog_data.operand[i], recog_data.operand_mode[i], 0);
8378 for (l = v->locs; l; l = l->next)
8379 if (GET_CODE (l->loc) == REG)
8380 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc));
8383 for (i = 0; i < recog_data.n_operands; i++)
8385 enum machine_mode mode;
8389 op_alt_regno[i] = (int *) alloca (recog_data.n_alternatives * sizeof (int));
8390 for (j = 0; j < recog_data.n_alternatives; j++)
8391 op_alt_regno[i][j] = -1;
8393 p = constraints[i] = recog_data.constraints[i];
8394 mode = recog_data.operand_mode[i];
8396 /* Add the reject values for each alternative given by the constraints
8397 for this operand. */
8405 alternative_reject[j] += 3;
8407 alternative_reject[j] += 300;
8410 /* We won't change operands which are already registers. We
8411 also don't want to modify output operands. */
8412 regno = true_regnum (recog_data.operand[i]);
8414 || constraints[i][0] == '='
8415 || constraints[i][0] == '+')
8418 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++)
8420 int class = (int) NO_REGS;
8422 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno))
8425 REGNO (reg) = regno;
8426 PUT_MODE (reg, mode);
8428 /* We found a register equal to this operand. Now look for all
8429 alternatives that can accept this register and have not been
8430 assigned a register they can use yet. */
8439 case '=': case '+': case '?':
8440 case '#': case '&': case '!':
8442 case '0': case '1': case '2': case '3': case '4':
8443 case '5': case '6': case '7': case '8': case '9':
8444 case 'm': case '<': case '>': case 'V': case 'o':
8445 case 'E': case 'F': case 'G': case 'H':
8446 case 's': case 'i': case 'n':
8447 case 'I': case 'J': case 'K': case 'L':
8448 case 'M': case 'N': case 'O': case 'P':
8450 /* These don't say anything we care about. */
8454 class = reg_class_subunion[(int) class][(int) GENERAL_REGS];
8459 = reg_class_subunion[(int) class][(int) REG_CLASS_FROM_LETTER ((unsigned char)c)];
8462 case ',': case '\0':
8463 /* See if REGNO fits this alternative, and set it up as the
8464 replacement register if we don't have one for this
8465 alternative yet and the operand being replaced is not
8466 a cheap CONST_INT. */
8467 if (op_alt_regno[i][j] == -1
8468 && reg_fits_class_p (reg, class, 0, mode)
8469 && (GET_CODE (recog_data.operand[i]) != CONST_INT
8470 || (rtx_cost (recog_data.operand[i], SET)
8471 > rtx_cost (reg, SET))))
8473 alternative_nregs[j]++;
8474 op_alt_regno[i][j] = regno;
8486 /* Record all alternatives which are better or equal to the currently
8487 matching one in the alternative_order array. */
8488 for (i = j = 0; i < recog_data.n_alternatives; i++)
8489 if (alternative_reject[i] <= alternative_reject[which_alternative])
8490 alternative_order[j++] = i;
8491 recog_data.n_alternatives = j;
8493 /* Sort it. Given a small number of alternatives, a dumb algorithm
8494 won't hurt too much. */
8495 for (i = 0; i < recog_data.n_alternatives - 1; i++)
8498 int best_reject = alternative_reject[alternative_order[i]];
8499 int best_nregs = alternative_nregs[alternative_order[i]];
8502 for (j = i + 1; j < recog_data.n_alternatives; j++)
8504 int this_reject = alternative_reject[alternative_order[j]];
8505 int this_nregs = alternative_nregs[alternative_order[j]];
8507 if (this_reject < best_reject
8508 || (this_reject == best_reject && this_nregs < best_nregs))
8511 best_reject = this_reject;
8512 best_nregs = this_nregs;
8516 tmp = alternative_order[best];
8517 alternative_order[best] = alternative_order[i];
8518 alternative_order[i] = tmp;
8521 /* Substitute the operands as determined by op_alt_regno for the best
8523 j = alternative_order[0];
8525 for (i = 0; i < recog_data.n_operands; i++)
8527 enum machine_mode mode = recog_data.operand_mode[i];
8528 if (op_alt_regno[i][j] == -1)
8531 validate_change (insn, recog_data.operand_loc[i],
8532 gen_rtx_REG (mode, op_alt_regno[i][j]), 1);
8535 for (i = recog_data.n_dups - 1; i >= 0; i--)
8537 int op = recog_data.dup_num[i];
8538 enum machine_mode mode = recog_data.operand_mode[op];
8540 if (op_alt_regno[op][j] == -1)
8543 validate_change (insn, recog_data.dup_loc[i],
8544 gen_rtx_REG (mode, op_alt_regno[op][j]), 1);
8547 return apply_change_group ();
8550 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg
8552 This code might also be useful when reload gave up on reg+reg addresssing
8553 because of clashes between the return register and INDEX_REG_CLASS. */
8555 /* The maximum number of uses of a register we can keep track of to
8556 replace them with reg+reg addressing. */
8557 #define RELOAD_COMBINE_MAX_USES 6
8559 /* INSN is the insn where a register has ben used, and USEP points to the
8560 location of the register within the rtl. */
8561 struct reg_use { rtx insn, *usep; };
8563 /* If the register is used in some unknown fashion, USE_INDEX is negative.
8564 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID
8565 indicates where it becomes live again.
8566 Otherwise, USE_INDEX is the index of the last encountered use of the
8567 register (which is first among these we have seen since we scan backwards),
8568 OFFSET contains the constant offset that is added to the register in
8569 all encountered uses, and USE_RUID indicates the first encountered, i.e.
8570 last, of these uses.
8571 STORE_RUID is always meaningful if we only want to use a value in a
8572 register in a different place: it denotes the next insn in the insn
8573 stream (i.e. the last ecountered) that sets or clobbers the register. */
8576 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES];
8581 } reg_state[FIRST_PSEUDO_REGISTER];
8583 /* Reverse linear uid. This is increased in reload_combine while scanning
8584 the instructions from last to first. It is used to set last_label_ruid
8585 and the store_ruid / use_ruid fields in reg_state. */
8586 static int reload_combine_ruid;
8588 #define LABEL_LIVE(LABEL) \
8589 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno])
8595 int first_index_reg = -1, last_index_reg;
8598 int last_label_ruid;
8599 int min_labelno, n_labels;
8600 HARD_REG_SET ever_live_at_start, *label_live;
8602 /* If reg+reg can be used in offsetable memory adresses, the main chunk of
8603 reload has already used it where appropriate, so there is no use in
8604 trying to generate it now. */
8605 if (double_reg_address_ok && INDEX_REG_CLASS != NO_REGS)
8608 /* To avoid wasting too much time later searching for an index register,
8609 determine the minimum and maximum index register numbers. */
8610 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8611 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r))
8613 if (first_index_reg == -1)
8614 first_index_reg = r;
8619 /* If no index register is available, we can quit now. */
8620 if (first_index_reg == -1)
8623 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime
8624 information is a bit fuzzy immediately after reload, but it's
8625 still good enough to determine which registers are live at a jump
8627 min_labelno = get_first_label_num ();
8628 n_labels = max_label_num () - min_labelno;
8629 label_live = (HARD_REG_SET *) xmalloc (n_labels * sizeof (HARD_REG_SET));
8630 CLEAR_HARD_REG_SET (ever_live_at_start);
8632 for (i = n_basic_blocks - 1; i >= 0; i--)
8634 insn = BLOCK_HEAD (i);
8635 if (GET_CODE (insn) == CODE_LABEL)
8639 REG_SET_TO_HARD_REG_SET (live,
8640 BASIC_BLOCK (i)->global_live_at_start);
8641 compute_use_by_pseudos (&live,
8642 BASIC_BLOCK (i)->global_live_at_start);
8643 COPY_HARD_REG_SET (LABEL_LIVE (insn), live);
8644 IOR_HARD_REG_SET (ever_live_at_start, live);
8648 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */
8649 last_label_ruid = reload_combine_ruid = 0;
8650 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8652 reg_state[r].store_ruid = reload_combine_ruid;
8654 reg_state[r].use_index = -1;
8656 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8659 for (insn = get_last_insn (); insn; insn = PREV_INSN (insn))
8663 /* We cannot do our optimization across labels. Invalidating all the use
8664 information we have would be costly, so we just note where the label
8665 is and then later disable any optimization that would cross it. */
8666 if (GET_CODE (insn) == CODE_LABEL)
8667 last_label_ruid = reload_combine_ruid;
8668 else if (GET_CODE (insn) == BARRIER)
8669 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8670 if (! fixed_regs[r])
8671 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8673 if (! INSN_P (insn))
8676 reload_combine_ruid++;
8678 /* Look for (set (REGX) (CONST_INT))
8679 (set (REGX) (PLUS (REGX) (REGY)))
8681 ... (MEM (REGX)) ...
8683 (set (REGZ) (CONST_INT))
8685 ... (MEM (PLUS (REGZ) (REGY)))... .
8687 First, check that we have (set (REGX) (PLUS (REGX) (REGY)))
8688 and that we know all uses of REGX before it dies. */
8689 set = single_set (insn);
8691 && GET_CODE (SET_DEST (set)) == REG
8692 && (HARD_REGNO_NREGS (REGNO (SET_DEST (set)),
8693 GET_MODE (SET_DEST (set)))
8695 && GET_CODE (SET_SRC (set)) == PLUS
8696 && GET_CODE (XEXP (SET_SRC (set), 1)) == REG
8697 && rtx_equal_p (XEXP (SET_SRC (set), 0), SET_DEST (set))
8698 && last_label_ruid < reg_state[REGNO (SET_DEST (set))].use_ruid)
8700 rtx reg = SET_DEST (set);
8701 rtx plus = SET_SRC (set);
8702 rtx base = XEXP (plus, 1);
8703 rtx prev = prev_nonnote_insn (insn);
8704 rtx prev_set = prev ? single_set (prev) : NULL_RTX;
8705 unsigned int regno = REGNO (reg);
8706 rtx const_reg = NULL_RTX;
8707 rtx reg_sum = NULL_RTX;
8709 /* Now, we need an index register.
8710 We'll set index_reg to this index register, const_reg to the
8711 register that is to be loaded with the constant
8712 (denoted as REGZ in the substitution illustration above),
8713 and reg_sum to the register-register that we want to use to
8714 substitute uses of REG (typically in MEMs) with.
8715 First check REG and BASE for being index registers;
8716 we can use them even if they are not dead. */
8717 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno)
8718 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8726 /* Otherwise, look for a free index register. Since we have
8727 checked above that neiter REG nor BASE are index registers,
8728 if we find anything at all, it will be different from these
8730 for (i = first_index_reg; i <= last_index_reg; i++)
8732 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS],
8734 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES
8735 && reg_state[i].store_ruid <= reg_state[regno].use_ruid
8736 && HARD_REGNO_NREGS (i, GET_MODE (reg)) == 1)
8738 rtx index_reg = gen_rtx_REG (GET_MODE (reg), i);
8740 const_reg = index_reg;
8741 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base);
8747 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that
8748 (REGY), i.e. BASE, is not clobbered before the last use we'll
8751 && GET_CODE (SET_SRC (prev_set)) == CONST_INT
8752 && rtx_equal_p (SET_DEST (prev_set), reg)
8753 && reg_state[regno].use_index >= 0
8754 && (reg_state[REGNO (base)].store_ruid
8755 <= reg_state[regno].use_ruid)
8760 /* Change destination register and, if necessary, the
8761 constant value in PREV, the constant loading instruction. */
8762 validate_change (prev, &SET_DEST (prev_set), const_reg, 1);
8763 if (reg_state[regno].offset != const0_rtx)
8764 validate_change (prev,
8765 &SET_SRC (prev_set),
8766 GEN_INT (INTVAL (SET_SRC (prev_set))
8767 + INTVAL (reg_state[regno].offset)),
8770 /* Now for every use of REG that we have recorded, replace REG
8772 for (i = reg_state[regno].use_index;
8773 i < RELOAD_COMBINE_MAX_USES; i++)
8774 validate_change (reg_state[regno].reg_use[i].insn,
8775 reg_state[regno].reg_use[i].usep,
8778 if (apply_change_group ())
8782 /* Delete the reg-reg addition. */
8783 PUT_CODE (insn, NOTE);
8784 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
8785 NOTE_SOURCE_FILE (insn) = 0;
8787 if (reg_state[regno].offset != const0_rtx)
8788 /* Previous REG_EQUIV / REG_EQUAL notes for PREV
8790 for (np = ®_NOTES (prev); *np;)
8792 if (REG_NOTE_KIND (*np) == REG_EQUAL
8793 || REG_NOTE_KIND (*np) == REG_EQUIV)
8794 *np = XEXP (*np, 1);
8796 np = &XEXP (*np, 1);
8799 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES;
8800 reg_state[REGNO (const_reg)].store_ruid
8801 = reload_combine_ruid;
8807 note_stores (PATTERN (insn), reload_combine_note_store, NULL);
8809 if (GET_CODE (insn) == CALL_INSN)
8813 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++)
8814 if (call_used_regs[r])
8816 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES;
8817 reg_state[r].store_ruid = reload_combine_ruid;
8820 for (link = CALL_INSN_FUNCTION_USAGE (insn); link;
8821 link = XEXP (link, 1))
8823 rtx usage_rtx = XEXP (XEXP (link, 0), 0);
8824 if (GET_CODE (usage_rtx) == REG)
8827 unsigned int start_reg = REGNO (usage_rtx);
8828 unsigned int num_regs =
8829 HARD_REGNO_NREGS (start_reg, GET_MODE (usage_rtx));
8830 unsigned int end_reg = start_reg + num_regs - 1;
8831 for (i = start_reg; i <= end_reg; i++)
8832 if (GET_CODE (XEXP (link, 0)) == CLOBBER)
8834 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8835 reg_state[i].store_ruid = reload_combine_ruid;
8838 reg_state[i].use_index = -1;
8843 else if (GET_CODE (insn) == JUMP_INSN
8844 && GET_CODE (PATTERN (insn)) != RETURN)
8846 /* Non-spill registers might be used at the call destination in
8847 some unknown fashion, so we have to mark the unknown use. */
8850 if ((condjump_p (insn) || condjump_in_parallel_p (insn))
8851 && JUMP_LABEL (insn))
8852 live = &LABEL_LIVE (JUMP_LABEL (insn));
8854 live = &ever_live_at_start;
8856 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; --i)
8857 if (TEST_HARD_REG_BIT (*live, i))
8858 reg_state[i].use_index = -1;
8861 reload_combine_note_use (&PATTERN (insn), insn);
8862 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
8864 if (REG_NOTE_KIND (note) == REG_INC
8865 && GET_CODE (XEXP (note, 0)) == REG)
8867 int regno = REGNO (XEXP (note, 0));
8869 reg_state[regno].store_ruid = reload_combine_ruid;
8870 reg_state[regno].use_index = -1;
8878 /* Check if DST is a register or a subreg of a register; if it is,
8879 update reg_state[regno].store_ruid and reg_state[regno].use_index
8880 accordingly. Called via note_stores from reload_combine. */
8883 reload_combine_note_store (dst, set, data)
8885 void *data ATTRIBUTE_UNUSED;
8889 enum machine_mode mode = GET_MODE (dst);
8891 if (GET_CODE (dst) == SUBREG)
8893 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
8894 GET_MODE (SUBREG_REG (dst)),
8897 dst = SUBREG_REG (dst);
8899 if (GET_CODE (dst) != REG)
8901 regno += REGNO (dst);
8903 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be
8904 careful with registers / register parts that are not full words.
8906 Similarly for ZERO_EXTRACT and SIGN_EXTRACT. */
8907 if (GET_CODE (set) != SET
8908 || GET_CODE (SET_DEST (set)) == ZERO_EXTRACT
8909 || GET_CODE (SET_DEST (set)) == SIGN_EXTRACT
8910 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART)
8912 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8914 reg_state[i].use_index = -1;
8915 reg_state[i].store_ruid = reload_combine_ruid;
8920 for (i = HARD_REGNO_NREGS (regno, mode) - 1 + regno; i >= regno; i--)
8922 reg_state[i].store_ruid = reload_combine_ruid;
8923 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES;
8928 /* XP points to a piece of rtl that has to be checked for any uses of
8930 *XP is the pattern of INSN, or a part of it.
8931 Called from reload_combine, and recursively by itself. */
8933 reload_combine_note_use (xp, insn)
8937 enum rtx_code code = x->code;
8940 rtx offset = const0_rtx; /* For the REG case below. */
8945 if (GET_CODE (SET_DEST (x)) == REG)
8947 reload_combine_note_use (&SET_SRC (x), insn);
8953 /* If this is the USE of a return value, we can't change it. */
8954 if (GET_CODE (XEXP (x, 0)) == REG && REG_FUNCTION_VALUE_P (XEXP (x, 0)))
8956 /* Mark the return register as used in an unknown fashion. */
8957 rtx reg = XEXP (x, 0);
8958 int regno = REGNO (reg);
8959 int nregs = HARD_REGNO_NREGS (regno, GET_MODE (reg));
8961 while (--nregs >= 0)
8962 reg_state[regno + nregs].use_index = -1;
8968 if (GET_CODE (SET_DEST (x)) == REG)
8973 /* We are interested in (plus (reg) (const_int)) . */
8974 if (GET_CODE (XEXP (x, 0)) != REG
8975 || GET_CODE (XEXP (x, 1)) != CONST_INT)
8977 offset = XEXP (x, 1);
8982 int regno = REGNO (x);
8986 /* Some spurious USEs of pseudo registers might remain.
8987 Just ignore them. */
8988 if (regno >= FIRST_PSEUDO_REGISTER)
8991 nregs = HARD_REGNO_NREGS (regno, GET_MODE (x));
8993 /* We can't substitute into multi-hard-reg uses. */
8996 while (--nregs >= 0)
8997 reg_state[regno + nregs].use_index = -1;
9001 /* If this register is already used in some unknown fashion, we
9003 If we decrement the index from zero to -1, we can't store more
9004 uses, so this register becomes used in an unknown fashion. */
9005 use_index = --reg_state[regno].use_index;
9009 if (use_index != RELOAD_COMBINE_MAX_USES - 1)
9011 /* We have found another use for a register that is already
9012 used later. Check if the offsets match; if not, mark the
9013 register as used in an unknown fashion. */
9014 if (! rtx_equal_p (offset, reg_state[regno].offset))
9016 reg_state[regno].use_index = -1;
9022 /* This is the first use of this register we have seen since we
9023 marked it as dead. */
9024 reg_state[regno].offset = offset;
9025 reg_state[regno].use_ruid = reload_combine_ruid;
9027 reg_state[regno].reg_use[use_index].insn = insn;
9028 reg_state[regno].reg_use[use_index].usep = xp;
9036 /* Recursively process the components of X. */
9037 fmt = GET_RTX_FORMAT (code);
9038 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9041 reload_combine_note_use (&XEXP (x, i), insn);
9042 else if (fmt[i] == 'E')
9044 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9045 reload_combine_note_use (&XVECEXP (x, i, j), insn);
9050 /* See if we can reduce the cost of a constant by replacing a move
9051 with an add. We track situations in which a register is set to a
9052 constant or to a register plus a constant. */
9053 /* We cannot do our optimization across labels. Invalidating all the
9054 information about register contents we have would be costly, so we
9055 use move2add_last_label_luid to note where the label is and then
9056 later disable any optimization that would cross it.
9057 reg_offset[n] / reg_base_reg[n] / reg_mode[n] are only valid if
9058 reg_set_luid[n] is greater than last_label_luid[n] . */
9059 static int reg_set_luid[FIRST_PSEUDO_REGISTER];
9061 /* If reg_base_reg[n] is negative, register n has been set to
9062 reg_offset[n] in mode reg_mode[n] .
9063 If reg_base_reg[n] is non-negative, register n has been set to the
9064 sum of reg_offset[n] and the value of register reg_base_reg[n]
9065 before reg_set_luid[n], calculated in mode reg_mode[n] . */
9066 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER];
9067 static int reg_base_reg[FIRST_PSEUDO_REGISTER];
9068 static enum machine_mode reg_mode[FIRST_PSEUDO_REGISTER];
9070 /* move2add_luid is linearily increased while scanning the instructions
9071 from first to last. It is used to set reg_set_luid in
9072 reload_cse_move2add and move2add_note_store. */
9073 static int move2add_luid;
9075 /* move2add_last_label_luid is set whenever a label is found. Labels
9076 invalidate all previously collected reg_offset data. */
9077 static int move2add_last_label_luid;
9079 /* Generate a CONST_INT and force it in the range of MODE. */
9081 static HOST_WIDE_INT
9082 sext_for_mode (mode, value)
9083 enum machine_mode mode;
9084 HOST_WIDE_INT value;
9086 HOST_WIDE_INT cval = value & GET_MODE_MASK (mode);
9087 int width = GET_MODE_BITSIZE (mode);
9089 /* If MODE is narrower than HOST_WIDE_INT and CVAL is a negative number,
9091 if (width > 0 && width < HOST_BITS_PER_WIDE_INT
9092 && (cval & ((HOST_WIDE_INT) 1 << (width - 1))) != 0)
9093 cval |= (HOST_WIDE_INT) -1 << width;
9098 /* ??? We don't know how zero / sign extension is handled, hence we
9099 can't go from a narrower to a wider mode. */
9100 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \
9101 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \
9102 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \
9103 && TRULY_NOOP_TRUNCATION (GET_MODE_BITSIZE (OUTMODE), \
9104 GET_MODE_BITSIZE (INMODE))))
9107 reload_cse_move2add (first)
9113 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9114 reg_set_luid[i] = 0;
9116 move2add_last_label_luid = 0;
9118 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++)
9122 if (GET_CODE (insn) == CODE_LABEL)
9124 move2add_last_label_luid = move2add_luid;
9125 /* We're going to increment move2add_luid twice after a
9126 label, so that we can use move2add_last_label_luid + 1 as
9127 the luid for constants. */
9131 if (! INSN_P (insn))
9133 pat = PATTERN (insn);
9134 /* For simplicity, we only perform this optimization on
9135 straightforward SETs. */
9136 if (GET_CODE (pat) == SET
9137 && GET_CODE (SET_DEST (pat)) == REG)
9139 rtx reg = SET_DEST (pat);
9140 int regno = REGNO (reg);
9141 rtx src = SET_SRC (pat);
9143 /* Check if we have valid information on the contents of this
9144 register in the mode of REG. */
9145 if (reg_set_luid[regno] > move2add_last_label_luid
9146 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg), reg_mode[regno]))
9148 /* Try to transform (set (REGX) (CONST_INT A))
9150 (set (REGX) (CONST_INT B))
9152 (set (REGX) (CONST_INT A))
9154 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9156 if (GET_CODE (src) == CONST_INT && reg_base_reg[regno] < 0)
9159 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9161 - reg_offset[regno]));
9162 /* (set (reg) (plus (reg) (const_int 0))) is not canonical;
9163 use (set (reg) (reg)) instead.
9164 We don't delete this insn, nor do we convert it into a
9165 note, to avoid losing register notes or the return
9166 value flag. jump2 already knowns how to get rid of
9168 if (new_src == const0_rtx)
9169 success = validate_change (insn, &SET_SRC (pat), reg, 0);
9170 else if (rtx_cost (new_src, PLUS) < rtx_cost (src, SET)
9171 && have_add2_insn (GET_MODE (reg)))
9172 success = validate_change (insn, &PATTERN (insn),
9173 gen_add2_insn (reg, new_src), 0);
9174 reg_set_luid[regno] = move2add_luid;
9175 reg_mode[regno] = GET_MODE (reg);
9176 reg_offset[regno] = INTVAL (src);
9180 /* Try to transform (set (REGX) (REGY))
9181 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9184 (set (REGX) (PLUS (REGX) (CONST_INT B)))
9187 (set (REGX) (PLUS (REGX) (CONST_INT A)))
9189 (set (REGX) (plus (REGX) (CONST_INT B-A))) */
9190 else if (GET_CODE (src) == REG
9191 && reg_set_luid[regno] == reg_set_luid[REGNO (src)]
9192 && reg_base_reg[regno] == reg_base_reg[REGNO (src)]
9193 && MODES_OK_FOR_MOVE2ADD (GET_MODE (reg),
9194 reg_mode[REGNO (src)]))
9196 rtx next = next_nonnote_insn (insn);
9199 set = single_set (next);
9201 && SET_DEST (set) == reg
9202 && GET_CODE (SET_SRC (set)) == PLUS
9203 && XEXP (SET_SRC (set), 0) == reg
9204 && GET_CODE (XEXP (SET_SRC (set), 1)) == CONST_INT)
9206 rtx src3 = XEXP (SET_SRC (set), 1);
9207 HOST_WIDE_INT added_offset = INTVAL (src3);
9208 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)];
9209 HOST_WIDE_INT regno_offset = reg_offset[regno];
9210 rtx new_src = GEN_INT (sext_for_mode (GET_MODE (reg),
9216 if (new_src == const0_rtx)
9217 /* See above why we create (set (reg) (reg)) here. */
9219 = validate_change (next, &SET_SRC (set), reg, 0);
9220 else if ((rtx_cost (new_src, PLUS)
9221 < COSTS_N_INSNS (1) + rtx_cost (src3, SET))
9222 && have_add2_insn (GET_MODE (reg)))
9224 = validate_change (next, &PATTERN (next),
9225 gen_add2_insn (reg, new_src), 0);
9228 /* INSN might be the first insn in a basic block
9229 if the preceding insn is a conditional jump
9230 or a possible-throwing call. */
9231 PUT_CODE (insn, NOTE);
9232 NOTE_LINE_NUMBER (insn) = NOTE_INSN_DELETED;
9233 NOTE_SOURCE_FILE (insn) = 0;
9236 reg_mode[regno] = GET_MODE (reg);
9237 reg_offset[regno] = sext_for_mode (GET_MODE (reg),
9246 for (note = REG_NOTES (insn); note; note = XEXP (note, 1))
9248 if (REG_NOTE_KIND (note) == REG_INC
9249 && GET_CODE (XEXP (note, 0)) == REG)
9251 /* Reset the information about this register. */
9252 int regno = REGNO (XEXP (note, 0));
9253 if (regno < FIRST_PSEUDO_REGISTER)
9254 reg_set_luid[regno] = 0;
9257 note_stores (PATTERN (insn), move2add_note_store, NULL);
9258 /* If this is a CALL_INSN, all call used registers are stored with
9260 if (GET_CODE (insn) == CALL_INSN)
9262 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--)
9264 if (call_used_regs[i])
9265 /* Reset the information about this register. */
9266 reg_set_luid[i] = 0;
9272 /* SET is a SET or CLOBBER that sets DST.
9273 Update reg_set_luid, reg_offset and reg_base_reg accordingly.
9274 Called from reload_cse_move2add via note_stores. */
9277 move2add_note_store (dst, set, data)
9279 void *data ATTRIBUTE_UNUSED;
9281 unsigned int regno = 0;
9283 enum machine_mode mode = GET_MODE (dst);
9285 if (GET_CODE (dst) == SUBREG)
9287 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)),
9288 GET_MODE (SUBREG_REG (dst)),
9291 dst = SUBREG_REG (dst);
9294 /* Some targets do argument pushes without adding REG_INC notes. */
9296 if (GET_CODE (dst) == MEM)
9298 dst = XEXP (dst, 0);
9299 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_DEC
9300 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC)
9301 reg_set_luid[REGNO (XEXP (dst, 0))] = 0;
9304 if (GET_CODE (dst) != REG)
9307 regno += REGNO (dst);
9309 if (HARD_REGNO_NREGS (regno, mode) == 1 && GET_CODE (set) == SET
9310 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT
9311 && GET_CODE (SET_DEST (set)) != SIGN_EXTRACT
9312 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART)
9314 rtx src = SET_SRC (set);
9316 HOST_WIDE_INT offset;
9318 /* This may be different from mode, if SET_DEST (set) is a
9320 enum machine_mode dst_mode = GET_MODE (dst);
9322 switch (GET_CODE (src))
9325 if (GET_CODE (XEXP (src, 0)) == REG)
9327 base_reg = XEXP (src, 0);
9329 if (GET_CODE (XEXP (src, 1)) == CONST_INT)
9330 offset = INTVAL (XEXP (src, 1));
9331 else if (GET_CODE (XEXP (src, 1)) == REG
9332 && (reg_set_luid[REGNO (XEXP (src, 1))]
9333 > move2add_last_label_luid)
9334 && (MODES_OK_FOR_MOVE2ADD
9335 (dst_mode, reg_mode[REGNO (XEXP (src, 1))])))
9337 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0)
9338 offset = reg_offset[REGNO (XEXP (src, 1))];
9339 /* Maybe the first register is known to be a
9341 else if (reg_set_luid[REGNO (base_reg)]
9342 > move2add_last_label_luid
9343 && (MODES_OK_FOR_MOVE2ADD
9344 (dst_mode, reg_mode[REGNO (XEXP (src, 1))]))
9345 && reg_base_reg[REGNO (base_reg)] < 0)
9347 offset = reg_offset[REGNO (base_reg)];
9348 base_reg = XEXP (src, 1);
9367 /* Start tracking the register as a constant. */
9368 reg_base_reg[regno] = -1;
9369 reg_offset[regno] = INTVAL (SET_SRC (set));
9370 /* We assign the same luid to all registers set to constants. */
9371 reg_set_luid[regno] = move2add_last_label_luid + 1;
9372 reg_mode[regno] = mode;
9377 /* Invalidate the contents of the register. */
9378 reg_set_luid[regno] = 0;
9382 base_regno = REGNO (base_reg);
9383 /* If information about the base register is not valid, set it
9384 up as a new base register, pretending its value is known
9385 starting from the current insn. */
9386 if (reg_set_luid[base_regno] <= move2add_last_label_luid)
9388 reg_base_reg[base_regno] = base_regno;
9389 reg_offset[base_regno] = 0;
9390 reg_set_luid[base_regno] = move2add_luid;
9391 reg_mode[base_regno] = mode;
9393 else if (! MODES_OK_FOR_MOVE2ADD (dst_mode,
9394 reg_mode[base_regno]))
9397 reg_mode[regno] = mode;
9399 /* Copy base information from our base register. */
9400 reg_set_luid[regno] = reg_set_luid[base_regno];
9401 reg_base_reg[regno] = reg_base_reg[base_regno];
9403 /* Compute the sum of the offsets or constants. */
9404 reg_offset[regno] = sext_for_mode (dst_mode,
9406 + reg_offset[base_regno]);
9410 unsigned int endregno = regno + HARD_REGNO_NREGS (regno, mode);
9412 for (i = regno; i < endregno; i++)
9413 /* Reset the information about this register. */
9414 reg_set_luid[i] = 0;
9420 add_auto_inc_notes (insn, x)
9424 enum rtx_code code = GET_CODE (x);
9428 if (code == MEM && auto_inc_p (XEXP (x, 0)))
9431 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
9435 /* Scan all the operand sub-expressions. */
9436 fmt = GET_RTX_FORMAT (code);
9437 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
9440 add_auto_inc_notes (insn, XEXP (x, i));
9441 else if (fmt[i] == 'E')
9442 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
9443 add_auto_inc_notes (insn, XVECEXP (x, i, j));
9448 /* Copy EH notes from an insn to its reloads. */
9450 copy_eh_notes (insn, x)
9454 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
9457 for (; x != 0; x = NEXT_INSN (x))
9459 if (may_trap_p (PATTERN (x)))
9461 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
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