1 /* Reload pseudo regs into hard regs for insns that require hard regs.
2 Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
3 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
4 Free Software Foundation, Inc.
6 This file is part of GCC.
8 GCC is free software; you can redistribute it and/or modify it under
9 the terms of the GNU General Public License as published by the Free
10 Software Foundation; either version 3, or (at your option) any later
13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
15 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
18 You should have received a copy of the GNU General Public License
19 along with GCC; see the file COPYING3. If not see
20 <http://www.gnu.org/licenses/>. */
24 #include "coretypes.h"
28 #include "hard-reg-set.h"
32 #include "insn-config.h"
38 #include "addresses.h"
39 #include "basic-block.h"
51 /* This file contains the reload pass of the compiler, which is
52 run after register allocation has been done. It checks that
53 each insn is valid (operands required to be in registers really
54 are in registers of the proper class) and fixes up invalid ones
55 by copying values temporarily into registers for the insns
58 The results of register allocation are described by the vector
59 reg_renumber; the insns still contain pseudo regs, but reg_renumber
60 can be used to find which hard reg, if any, a pseudo reg is in.
62 The technique we always use is to free up a few hard regs that are
63 called ``reload regs'', and for each place where a pseudo reg
64 must be in a hard reg, copy it temporarily into one of the reload regs.
66 Reload regs are allocated locally for every instruction that needs
67 reloads. When there are pseudos which are allocated to a register that
68 has been chosen as a reload reg, such pseudos must be ``spilled''.
69 This means that they go to other hard regs, or to stack slots if no other
70 available hard regs can be found. Spilling can invalidate more
71 insns, requiring additional need for reloads, so we must keep checking
72 until the process stabilizes.
74 For machines with different classes of registers, we must keep track
75 of the register class needed for each reload, and make sure that
76 we allocate enough reload registers of each class.
78 The file reload.c contains the code that checks one insn for
79 validity and reports the reloads that it needs. This file
80 is in charge of scanning the entire rtl code, accumulating the
81 reload needs, spilling, assigning reload registers to use for
82 fixing up each insn, and generating the new insns to copy values
83 into the reload registers. */
85 /* During reload_as_needed, element N contains a REG rtx for the hard reg
86 into which reg N has been reloaded (perhaps for a previous insn). */
87 static rtx *reg_last_reload_reg;
89 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn
90 for an output reload that stores into reg N. */
91 static regset_head reg_has_output_reload;
93 /* Indicates which hard regs are reload-registers for an output reload
94 in the current insn. */
95 static HARD_REG_SET reg_is_output_reload;
97 /* Element N is the constant value to which pseudo reg N is equivalent,
98 or zero if pseudo reg N is not equivalent to a constant.
99 find_reloads looks at this in order to replace pseudo reg N
100 with the constant it stands for. */
101 rtx *reg_equiv_constant;
103 /* Element N is an invariant value to which pseudo reg N is equivalent.
104 eliminate_regs_in_insn uses this to replace pseudos in particular
106 rtx *reg_equiv_invariant;
108 /* Element N is a memory location to which pseudo reg N is equivalent,
109 prior to any register elimination (such as frame pointer to stack
110 pointer). Depending on whether or not it is a valid address, this value
111 is transferred to either reg_equiv_address or reg_equiv_mem. */
112 rtx *reg_equiv_memory_loc;
114 /* We allocate reg_equiv_memory_loc inside a varray so that the garbage
115 collector can keep track of what is inside. */
116 VEC(rtx,gc) *reg_equiv_memory_loc_vec;
118 /* Element N is the address of stack slot to which pseudo reg N is equivalent.
119 This is used when the address is not valid as a memory address
120 (because its displacement is too big for the machine.) */
121 rtx *reg_equiv_address;
123 /* Element N is the memory slot to which pseudo reg N is equivalent,
124 or zero if pseudo reg N is not equivalent to a memory slot. */
127 /* Element N is an EXPR_LIST of REG_EQUIVs containing MEMs with
128 alternate representations of the location of pseudo reg N. */
129 rtx *reg_equiv_alt_mem_list;
131 /* Widest width in which each pseudo reg is referred to (via subreg). */
132 static unsigned int *reg_max_ref_width;
134 /* Element N is the list of insns that initialized reg N from its equivalent
135 constant or memory slot. */
137 int reg_equiv_init_size;
139 /* Vector to remember old contents of reg_renumber before spilling. */
140 static short *reg_old_renumber;
142 /* During reload_as_needed, element N contains the last pseudo regno reloaded
143 into hard register N. If that pseudo reg occupied more than one register,
144 reg_reloaded_contents points to that pseudo for each spill register in
145 use; all of these must remain set for an inheritance to occur. */
146 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER];
148 /* During reload_as_needed, element N contains the insn for which
149 hard register N was last used. Its contents are significant only
150 when reg_reloaded_valid is set for this register. */
151 static rtx reg_reloaded_insn[FIRST_PSEUDO_REGISTER];
153 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */
154 static HARD_REG_SET reg_reloaded_valid;
155 /* Indicate if the register was dead at the end of the reload.
156 This is only valid if reg_reloaded_contents is set and valid. */
157 static HARD_REG_SET reg_reloaded_dead;
159 /* Indicate whether the register's current value is one that is not
160 safe to retain across a call, even for registers that are normally
162 static HARD_REG_SET reg_reloaded_call_part_clobbered;
164 /* Number of spill-regs so far; number of valid elements of spill_regs. */
167 /* In parallel with spill_regs, contains REG rtx's for those regs.
168 Holds the last rtx used for any given reg, or 0 if it has never
169 been used for spilling yet. This rtx is reused, provided it has
171 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER];
173 /* In parallel with spill_regs, contains nonzero for a spill reg
174 that was stored after the last time it was used.
175 The precise value is the insn generated to do the store. */
176 static rtx spill_reg_store[FIRST_PSEUDO_REGISTER];
178 /* This is the register that was stored with spill_reg_store. This is a
179 copy of reload_out / reload_out_reg when the value was stored; if
180 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */
181 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER];
183 /* This table is the inverse mapping of spill_regs:
184 indexed by hard reg number,
185 it contains the position of that reg in spill_regs,
186 or -1 for something that is not in spill_regs.
188 ?!? This is no longer accurate. */
189 static short spill_reg_order[FIRST_PSEUDO_REGISTER];
191 /* This reg set indicates registers that can't be used as spill registers for
192 the currently processed insn. These are the hard registers which are live
193 during the insn, but not allocated to pseudos, as well as fixed
195 static HARD_REG_SET bad_spill_regs;
197 /* These are the hard registers that can't be used as spill register for any
198 insn. This includes registers used for user variables and registers that
199 we can't eliminate. A register that appears in this set also can't be used
200 to retry register allocation. */
201 static HARD_REG_SET bad_spill_regs_global;
203 /* Describes order of use of registers for reloading
204 of spilled pseudo-registers. `n_spills' is the number of
205 elements that are actually valid; new ones are added at the end.
207 Both spill_regs and spill_reg_order are used on two occasions:
208 once during find_reload_regs, where they keep track of the spill registers
209 for a single insn, but also during reload_as_needed where they show all
210 the registers ever used by reload. For the latter case, the information
211 is calculated during finish_spills. */
212 static short spill_regs[FIRST_PSEUDO_REGISTER];
214 /* This vector of reg sets indicates, for each pseudo, which hard registers
215 may not be used for retrying global allocation because the register was
216 formerly spilled from one of them. If we allowed reallocating a pseudo to
217 a register that it was already allocated to, reload might not
219 static HARD_REG_SET *pseudo_previous_regs;
221 /* This vector of reg sets indicates, for each pseudo, which hard
222 registers may not be used for retrying global allocation because they
223 are used as spill registers during one of the insns in which the
225 static HARD_REG_SET *pseudo_forbidden_regs;
227 /* All hard regs that have been used as spill registers for any insn are
228 marked in this set. */
229 static HARD_REG_SET used_spill_regs;
231 /* Index of last register assigned as a spill register. We allocate in
232 a round-robin fashion. */
233 static int last_spill_reg;
235 /* Nonzero if indirect addressing is supported on the machine; this means
236 that spilling (REG n) does not require reloading it into a register in
237 order to do (MEM (REG n)) or (MEM (PLUS (REG n) (CONST_INT c))). The
238 value indicates the level of indirect addressing supported, e.g., two
239 means that (MEM (MEM (REG n))) is also valid if (REG n) does not get
241 static char spill_indirect_levels;
243 /* Nonzero if indirect addressing is supported when the innermost MEM is
244 of the form (MEM (SYMBOL_REF sym)). It is assumed that the level to
245 which these are valid is the same as spill_indirect_levels, above. */
246 char indirect_symref_ok;
248 /* Nonzero if an address (plus (reg frame_pointer) (reg ...)) is valid. */
249 char double_reg_address_ok;
251 /* Record the stack slot for each spilled hard register. */
252 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER];
254 /* Width allocated so far for that stack slot. */
255 static unsigned int spill_stack_slot_width[FIRST_PSEUDO_REGISTER];
257 /* Record which pseudos needed to be spilled. */
258 static regset_head spilled_pseudos;
260 /* Used for communication between order_regs_for_reload and count_pseudo.
261 Used to avoid counting one pseudo twice. */
262 static regset_head pseudos_counted;
264 /* First uid used by insns created by reload in this function.
265 Used in find_equiv_reg. */
266 int reload_first_uid;
268 /* Flag set by local-alloc or global-alloc if anything is live in
269 a call-clobbered reg across calls. */
270 int caller_save_needed;
272 /* Set to 1 while reload_as_needed is operating.
273 Required by some machines to handle any generated moves differently. */
274 int reload_in_progress = 0;
276 /* These arrays record the insn_code of insns that may be needed to
277 perform input and output reloads of special objects. They provide a
278 place to pass a scratch register. */
279 enum insn_code reload_in_optab[NUM_MACHINE_MODES];
280 enum insn_code reload_out_optab[NUM_MACHINE_MODES];
282 /* This obstack is used for allocation of rtl during register elimination.
283 The allocated storage can be freed once find_reloads has processed the
285 static struct obstack reload_obstack;
287 /* Points to the beginning of the reload_obstack. All insn_chain structures
288 are allocated first. */
289 static char *reload_startobj;
291 /* The point after all insn_chain structures. Used to quickly deallocate
292 memory allocated in copy_reloads during calculate_needs_all_insns. */
293 static char *reload_firstobj;
295 /* This points before all local rtl generated by register elimination.
296 Used to quickly free all memory after processing one insn. */
297 static char *reload_insn_firstobj;
299 /* List of insn_chain instructions, one for every insn that reload needs to
301 struct insn_chain *reload_insn_chain;
303 /* List of all insns needing reloads. */
304 static struct insn_chain *insns_need_reload;
306 /* This structure is used to record information about register eliminations.
307 Each array entry describes one possible way of eliminating a register
308 in favor of another. If there is more than one way of eliminating a
309 particular register, the most preferred should be specified first. */
313 int from; /* Register number to be eliminated. */
314 int to; /* Register number used as replacement. */
315 HOST_WIDE_INT initial_offset; /* Initial difference between values. */
316 int can_eliminate; /* Nonzero if this elimination can be done. */
317 int can_eliminate_previous; /* Value of CAN_ELIMINATE in previous scan over
318 insns made by reload. */
319 HOST_WIDE_INT offset; /* Current offset between the two regs. */
320 HOST_WIDE_INT previous_offset;/* Offset at end of previous insn. */
321 int ref_outside_mem; /* "to" has been referenced outside a MEM. */
322 rtx from_rtx; /* REG rtx for the register to be eliminated.
323 We cannot simply compare the number since
324 we might then spuriously replace a hard
325 register corresponding to a pseudo
326 assigned to the reg to be eliminated. */
327 rtx to_rtx; /* REG rtx for the replacement. */
330 static struct elim_table *reg_eliminate = 0;
332 /* This is an intermediate structure to initialize the table. It has
333 exactly the members provided by ELIMINABLE_REGS. */
334 static const struct elim_table_1
338 } reg_eliminate_1[] =
340 /* If a set of eliminable registers was specified, define the table from it.
341 Otherwise, default to the normal case of the frame pointer being
342 replaced by the stack pointer. */
344 #ifdef ELIMINABLE_REGS
347 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}};
350 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1)
352 /* Record the number of pending eliminations that have an offset not equal
353 to their initial offset. If nonzero, we use a new copy of each
354 replacement result in any insns encountered. */
355 int num_not_at_initial_offset;
357 /* Count the number of registers that we may be able to eliminate. */
358 static int num_eliminable;
359 /* And the number of registers that are equivalent to a constant that
360 can be eliminated to frame_pointer / arg_pointer + constant. */
361 static int num_eliminable_invariants;
363 /* For each label, we record the offset of each elimination. If we reach
364 a label by more than one path and an offset differs, we cannot do the
365 elimination. This information is indexed by the difference of the
366 number of the label and the first label number. We can't offset the
367 pointer itself as this can cause problems on machines with segmented
368 memory. The first table is an array of flags that records whether we
369 have yet encountered a label and the second table is an array of arrays,
370 one entry in the latter array for each elimination. */
372 static int first_label_num;
373 static char *offsets_known_at;
374 static HOST_WIDE_INT (*offsets_at)[NUM_ELIMINABLE_REGS];
376 /* Number of labels in the current function. */
378 static int num_labels;
380 static void replace_pseudos_in (rtx *, enum machine_mode, rtx);
381 static void maybe_fix_stack_asms (void);
382 static void copy_reloads (struct insn_chain *);
383 static void calculate_needs_all_insns (int);
384 static int find_reg (struct insn_chain *, int);
385 static void find_reload_regs (struct insn_chain *);
386 static void select_reload_regs (void);
387 static void delete_caller_save_insns (void);
389 static void spill_failure (rtx, enum reg_class);
390 static void count_spilled_pseudo (int, int, int);
391 static void delete_dead_insn (rtx);
392 static void alter_reg (int, int);
393 static void set_label_offsets (rtx, rtx, int);
394 static void check_eliminable_occurrences (rtx);
395 static void elimination_effects (rtx, enum machine_mode);
396 static int eliminate_regs_in_insn (rtx, int);
397 static void update_eliminable_offsets (void);
398 static void mark_not_eliminable (rtx, const_rtx, void *);
399 static void set_initial_elim_offsets (void);
400 static bool verify_initial_elim_offsets (void);
401 static void set_initial_label_offsets (void);
402 static void set_offsets_for_label (rtx);
403 static void init_elim_table (void);
404 static void update_eliminables (HARD_REG_SET *);
405 static void spill_hard_reg (unsigned int, int);
406 static int finish_spills (int);
407 static void scan_paradoxical_subregs (rtx);
408 static void count_pseudo (int);
409 static void order_regs_for_reload (struct insn_chain *);
410 static void reload_as_needed (int);
411 static void forget_old_reloads_1 (rtx, const_rtx, void *);
412 static void forget_marked_reloads (regset);
413 static int reload_reg_class_lower (const void *, const void *);
414 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type,
416 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type,
418 static int reload_reg_free_p (unsigned int, int, enum reload_type);
419 static int reload_reg_free_for_value_p (int, int, int, enum reload_type,
421 static int free_for_value_p (int, enum machine_mode, int, enum reload_type,
423 static int reload_reg_reaches_end_p (unsigned int, int, enum reload_type);
424 static int allocate_reload_reg (struct insn_chain *, int, int);
425 static int conflicts_with_override (rtx);
426 static void failed_reload (rtx, int);
427 static int set_reload_reg (int, int);
428 static void choose_reload_regs_init (struct insn_chain *, rtx *);
429 static void choose_reload_regs (struct insn_chain *);
430 static void merge_assigned_reloads (rtx);
431 static void emit_input_reload_insns (struct insn_chain *, struct reload *,
433 static void emit_output_reload_insns (struct insn_chain *, struct reload *,
435 static void do_input_reload (struct insn_chain *, struct reload *, int);
436 static void do_output_reload (struct insn_chain *, struct reload *, int);
437 static bool inherit_piecemeal_p (int, int);
438 static void emit_reload_insns (struct insn_chain *);
439 static void delete_output_reload (rtx, int, int);
440 static void delete_address_reloads (rtx, rtx);
441 static void delete_address_reloads_1 (rtx, rtx, rtx);
442 static rtx inc_for_reload (rtx, rtx, rtx, int);
444 static void add_auto_inc_notes (rtx, rtx);
446 static void copy_eh_notes (rtx, rtx);
447 static int reloads_conflict (int, int);
448 static rtx gen_reload (rtx, rtx, int, enum reload_type);
449 static rtx emit_insn_if_valid_for_reload (rtx);
451 /* Initialize the reload pass. This is called at the beginning of compilation
452 and may be called again if the target is reinitialized. */
459 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack.
460 Set spill_indirect_levels to the number of levels such addressing is
461 permitted, zero if it is not permitted at all. */
464 = gen_rtx_MEM (Pmode,
467 LAST_VIRTUAL_REGISTER + 1),
469 spill_indirect_levels = 0;
471 while (memory_address_p (QImode, tem))
473 spill_indirect_levels++;
474 tem = gen_rtx_MEM (Pmode, tem);
477 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */
479 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo"));
480 indirect_symref_ok = memory_address_p (QImode, tem);
482 /* See if reg+reg is a valid (and offsettable) address. */
484 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
486 tem = gen_rtx_PLUS (Pmode,
487 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM),
488 gen_rtx_REG (Pmode, i));
490 /* This way, we make sure that reg+reg is an offsettable address. */
491 tem = plus_constant (tem, 4);
493 if (memory_address_p (QImode, tem))
495 double_reg_address_ok = 1;
500 /* Initialize obstack for our rtl allocation. */
501 gcc_obstack_init (&reload_obstack);
502 reload_startobj = obstack_alloc (&reload_obstack, 0);
504 INIT_REG_SET (&spilled_pseudos);
505 INIT_REG_SET (&pseudos_counted);
508 /* List of insn chains that are currently unused. */
509 static struct insn_chain *unused_insn_chains = 0;
511 /* Allocate an empty insn_chain structure. */
513 new_insn_chain (void)
515 struct insn_chain *c;
517 if (unused_insn_chains == 0)
519 c = obstack_alloc (&reload_obstack, sizeof (struct insn_chain));
520 INIT_REG_SET (&c->live_throughout);
521 INIT_REG_SET (&c->dead_or_set);
525 c = unused_insn_chains;
526 unused_insn_chains = c->next;
528 c->is_caller_save_insn = 0;
529 c->need_operand_change = 0;
535 /* Small utility function to set all regs in hard reg set TO which are
536 allocated to pseudos in regset FROM. */
539 compute_use_by_pseudos (HARD_REG_SET *to, regset from)
542 reg_set_iterator rsi;
544 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi)
546 int r = reg_renumber[regno];
550 /* reload_combine uses the information from
551 DF_LIVE_IN (BASIC_BLOCK), which might still
552 contain registers that have not actually been allocated
553 since they have an equivalence. */
554 gcc_assert (reload_completed);
557 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r);
561 /* Replace all pseudos found in LOC with their corresponding
565 replace_pseudos_in (rtx *loc, enum machine_mode mem_mode, rtx usage)
578 unsigned int regno = REGNO (x);
580 if (regno < FIRST_PSEUDO_REGISTER)
583 x = eliminate_regs (x, mem_mode, usage);
587 replace_pseudos_in (loc, mem_mode, usage);
591 if (reg_equiv_constant[regno])
592 *loc = reg_equiv_constant[regno];
593 else if (reg_equiv_mem[regno])
594 *loc = reg_equiv_mem[regno];
595 else if (reg_equiv_address[regno])
596 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address[regno]);
599 gcc_assert (!REG_P (regno_reg_rtx[regno])
600 || REGNO (regno_reg_rtx[regno]) != regno);
601 *loc = regno_reg_rtx[regno];
606 else if (code == MEM)
608 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage);
612 /* Process each of our operands recursively. */
613 fmt = GET_RTX_FORMAT (code);
614 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
616 replace_pseudos_in (&XEXP (x, i), mem_mode, usage);
617 else if (*fmt == 'E')
618 for (j = 0; j < XVECLEN (x, i); j++)
619 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage);
622 /* Determine if the current function has an exception receiver block
623 that reaches the exit block via non-exceptional edges */
626 has_nonexceptional_receiver (void)
630 basic_block *tos, *worklist, bb;
632 /* If we're not optimizing, then just err on the safe side. */
636 /* First determine which blocks can reach exit via normal paths. */
637 tos = worklist = xmalloc (sizeof (basic_block) * (n_basic_blocks + 1));
640 bb->flags &= ~BB_REACHABLE;
642 /* Place the exit block on our worklist. */
643 EXIT_BLOCK_PTR->flags |= BB_REACHABLE;
644 *tos++ = EXIT_BLOCK_PTR;
646 /* Iterate: find everything reachable from what we've already seen. */
647 while (tos != worklist)
651 FOR_EACH_EDGE (e, ei, bb->preds)
652 if (!(e->flags & EDGE_ABNORMAL))
654 basic_block src = e->src;
656 if (!(src->flags & BB_REACHABLE))
658 src->flags |= BB_REACHABLE;
665 /* Now see if there's a reachable block with an exceptional incoming
668 if (bb->flags & BB_REACHABLE)
669 FOR_EACH_EDGE (e, ei, bb->preds)
670 if (e->flags & EDGE_ABNORMAL)
673 /* No exceptional block reached exit unexceptionally. */
678 /* Global variables used by reload and its subroutines. */
680 /* Set during calculate_needs if an insn needs register elimination. */
681 static int something_needs_elimination;
682 /* Set during calculate_needs if an insn needs an operand changed. */
683 static int something_needs_operands_changed;
685 /* Nonzero means we couldn't get enough spill regs. */
688 /* Main entry point for the reload pass.
690 FIRST is the first insn of the function being compiled.
692 GLOBAL nonzero means we were called from global_alloc
693 and should attempt to reallocate any pseudoregs that we
694 displace from hard regs we will use for reloads.
695 If GLOBAL is zero, we do not have enough information to do that,
696 so any pseudo reg that is spilled must go to the stack.
698 Return value is nonzero if reload failed
699 and we must not do any more for this function. */
702 reload (rtx first, int global)
706 struct elim_table *ep;
709 /* Make sure even insns with volatile mem refs are recognizable. */
714 reload_firstobj = obstack_alloc (&reload_obstack, 0);
716 /* Make sure that the last insn in the chain
717 is not something that needs reloading. */
718 emit_note (NOTE_INSN_DELETED);
720 /* Enable find_equiv_reg to distinguish insns made by reload. */
721 reload_first_uid = get_max_uid ();
723 #ifdef SECONDARY_MEMORY_NEEDED
724 /* Initialize the secondary memory table. */
725 clear_secondary_mem ();
728 /* We don't have a stack slot for any spill reg yet. */
729 memset (spill_stack_slot, 0, sizeof spill_stack_slot);
730 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width);
732 /* Initialize the save area information for caller-save, in case some
736 /* Compute which hard registers are now in use
737 as homes for pseudo registers.
738 This is done here rather than (eg) in global_alloc
739 because this point is reached even if not optimizing. */
740 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
743 /* A function that has a nonlocal label that can reach the exit
744 block via non-exceptional paths must save all call-saved
746 if (current_function_has_nonlocal_label
747 && has_nonexceptional_receiver ())
748 current_function_saves_all_registers = 1;
750 if (current_function_saves_all_registers)
751 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
752 if (! call_used_regs[i] && ! fixed_regs[i] && ! LOCAL_REGNO (i))
753 df_set_regs_ever_live (i, true);
755 /* Find all the pseudo registers that didn't get hard regs
756 but do have known equivalent constants or memory slots.
757 These include parameters (known equivalent to parameter slots)
758 and cse'd or loop-moved constant memory addresses.
760 Record constant equivalents in reg_equiv_constant
761 so they will be substituted by find_reloads.
762 Record memory equivalents in reg_mem_equiv so they can
763 be substituted eventually by altering the REG-rtx's. */
765 reg_equiv_constant = XCNEWVEC (rtx, max_regno);
766 reg_equiv_invariant = XCNEWVEC (rtx, max_regno);
767 reg_equiv_mem = XCNEWVEC (rtx, max_regno);
768 reg_equiv_alt_mem_list = XCNEWVEC (rtx, max_regno);
769 reg_equiv_address = XCNEWVEC (rtx, max_regno);
770 reg_max_ref_width = XCNEWVEC (unsigned int, max_regno);
771 reg_old_renumber = XCNEWVEC (short, max_regno);
772 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short));
773 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno);
774 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno);
776 CLEAR_HARD_REG_SET (bad_spill_regs_global);
778 /* Look for REG_EQUIV notes; record what each pseudo is equivalent
779 to. Also find all paradoxical subregs and find largest such for
782 num_eliminable_invariants = 0;
783 for (insn = first; insn; insn = NEXT_INSN (insn))
785 rtx set = single_set (insn);
787 /* We may introduce USEs that we want to remove at the end, so
788 we'll mark them with QImode. Make sure there are no
789 previously-marked insns left by say regmove. */
790 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE
791 && GET_MODE (insn) != VOIDmode)
792 PUT_MODE (insn, VOIDmode);
795 scan_paradoxical_subregs (PATTERN (insn));
797 if (set != 0 && REG_P (SET_DEST (set)))
799 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX);
805 i = REGNO (SET_DEST (set));
808 if (i <= LAST_VIRTUAL_REGISTER)
811 if (! function_invariant_p (x)
813 /* A function invariant is often CONSTANT_P but may
814 include a register. We promise to only pass
815 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */
817 && LEGITIMATE_PIC_OPERAND_P (x)))
819 /* It can happen that a REG_EQUIV note contains a MEM
820 that is not a legitimate memory operand. As later
821 stages of reload assume that all addresses found
822 in the reg_equiv_* arrays were originally legitimate,
823 we ignore such REG_EQUIV notes. */
824 if (memory_operand (x, VOIDmode))
826 /* Always unshare the equivalence, so we can
827 substitute into this insn without touching the
829 reg_equiv_memory_loc[i] = copy_rtx (x);
831 else if (function_invariant_p (x))
833 if (GET_CODE (x) == PLUS)
835 /* This is PLUS of frame pointer and a constant,
836 and might be shared. Unshare it. */
837 reg_equiv_invariant[i] = copy_rtx (x);
838 num_eliminable_invariants++;
840 else if (x == frame_pointer_rtx || x == arg_pointer_rtx)
842 reg_equiv_invariant[i] = x;
843 num_eliminable_invariants++;
845 else if (LEGITIMATE_CONSTANT_P (x))
846 reg_equiv_constant[i] = x;
849 reg_equiv_memory_loc[i]
850 = force_const_mem (GET_MODE (SET_DEST (set)), x);
851 if (! reg_equiv_memory_loc[i])
852 reg_equiv_init[i] = NULL_RTX;
857 reg_equiv_init[i] = NULL_RTX;
862 reg_equiv_init[i] = NULL_RTX;
867 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
868 if (reg_equiv_init[i])
870 fprintf (dump_file, "init_insns for %u: ", i);
871 print_inline_rtx (dump_file, reg_equiv_init[i], 20);
872 fprintf (dump_file, "\n");
877 first_label_num = get_first_label_num ();
878 num_labels = max_label_num () - first_label_num;
880 /* Allocate the tables used to store offset information at labels. */
881 /* We used to use alloca here, but the size of what it would try to
882 allocate would occasionally cause it to exceed the stack limit and
883 cause a core dump. */
884 offsets_known_at = XNEWVEC (char, num_labels);
885 offsets_at = (HOST_WIDE_INT (*)[NUM_ELIMINABLE_REGS]) xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (HOST_WIDE_INT));
887 /* Alter each pseudo-reg rtx to contain its hard reg number.
888 Assign stack slots to the pseudos that lack hard regs or equivalents.
889 Do not touch virtual registers. */
891 for (i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++)
894 /* If we have some registers we think can be eliminated, scan all insns to
895 see if there is an insn that sets one of these registers to something
896 other than itself plus a constant. If so, the register cannot be
897 eliminated. Doing this scan here eliminates an extra pass through the
898 main reload loop in the most common case where register elimination
900 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn))
902 note_stores (PATTERN (insn), mark_not_eliminable, NULL);
904 maybe_fix_stack_asms ();
906 insns_need_reload = 0;
907 something_needs_elimination = 0;
909 /* Initialize to -1, which means take the first spill register. */
912 /* Spill any hard regs that we know we can't eliminate. */
913 CLEAR_HARD_REG_SET (used_spill_regs);
914 /* There can be multiple ways to eliminate a register;
915 they should be listed adjacently.
916 Elimination for any register fails only if all possible ways fail. */
917 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; )
920 int can_eliminate = 0;
923 can_eliminate |= ep->can_eliminate;
926 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from);
928 spill_hard_reg (from, 1);
931 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
932 if (frame_pointer_needed)
933 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1);
935 finish_spills (global);
937 /* From now on, we may need to generate moves differently. We may also
938 allow modifications of insns which cause them to not be recognized.
939 Any such modifications will be cleaned up during reload itself. */
940 reload_in_progress = 1;
942 /* This loop scans the entire function each go-round
943 and repeats until one repetition spills no additional hard regs. */
946 int something_changed;
948 HOST_WIDE_INT starting_frame_size;
950 starting_frame_size = get_frame_size ();
952 set_initial_elim_offsets ();
953 set_initial_label_offsets ();
955 /* For each pseudo register that has an equivalent location defined,
956 try to eliminate any eliminable registers (such as the frame pointer)
957 assuming initial offsets for the replacement register, which
960 If the resulting location is directly addressable, substitute
961 the MEM we just got directly for the old REG.
963 If it is not addressable but is a constant or the sum of a hard reg
964 and constant, it is probably not addressable because the constant is
965 out of range, in that case record the address; we will generate
966 hairy code to compute the address in a register each time it is
967 needed. Similarly if it is a hard register, but one that is not
968 valid as an address register.
970 If the location is not addressable, but does not have one of the
971 above forms, assign a stack slot. We have to do this to avoid the
972 potential of producing lots of reloads if, e.g., a location involves
973 a pseudo that didn't get a hard register and has an equivalent memory
974 location that also involves a pseudo that didn't get a hard register.
976 Perhaps at some point we will improve reload_when_needed handling
977 so this problem goes away. But that's very hairy. */
979 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
980 if (reg_renumber[i] < 0 && reg_equiv_memory_loc[i])
982 rtx x = eliminate_regs (reg_equiv_memory_loc[i], 0, NULL_RTX);
984 if (strict_memory_address_p (GET_MODE (regno_reg_rtx[i]),
986 reg_equiv_mem[i] = x, reg_equiv_address[i] = 0;
987 else if (CONSTANT_P (XEXP (x, 0))
988 || (REG_P (XEXP (x, 0))
989 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)
990 || (GET_CODE (XEXP (x, 0)) == PLUS
991 && REG_P (XEXP (XEXP (x, 0), 0))
992 && (REGNO (XEXP (XEXP (x, 0), 0))
993 < FIRST_PSEUDO_REGISTER)
994 && CONSTANT_P (XEXP (XEXP (x, 0), 1))))
995 reg_equiv_address[i] = XEXP (x, 0), reg_equiv_mem[i] = 0;
998 /* Make a new stack slot. Then indicate that something
999 changed so we go back and recompute offsets for
1000 eliminable registers because the allocation of memory
1001 below might change some offset. reg_equiv_{mem,address}
1002 will be set up for this pseudo on the next pass around
1004 reg_equiv_memory_loc[i] = 0;
1005 reg_equiv_init[i] = 0;
1010 if (caller_save_needed)
1011 setup_save_areas ();
1013 /* If we allocated another stack slot, redo elimination bookkeeping. */
1014 if (starting_frame_size != get_frame_size ())
1016 if (starting_frame_size && cfun->stack_alignment_needed)
1018 /* If we have a stack frame, we must align it now. The
1019 stack size may be a part of the offset computation for
1020 register elimination. So if this changes the stack size,
1021 then repeat the elimination bookkeeping. We don't
1022 realign when there is no stack, as that will cause a
1023 stack frame when none is needed should
1024 STARTING_FRAME_OFFSET not be already aligned to
1026 assign_stack_local (BLKmode, 0, cfun->stack_alignment_needed);
1027 if (starting_frame_size != get_frame_size ())
1031 if (caller_save_needed)
1033 save_call_clobbered_regs ();
1034 /* That might have allocated new insn_chain structures. */
1035 reload_firstobj = obstack_alloc (&reload_obstack, 0);
1038 calculate_needs_all_insns (global);
1040 CLEAR_REG_SET (&spilled_pseudos);
1043 something_changed = 0;
1045 /* If we allocated any new memory locations, make another pass
1046 since it might have changed elimination offsets. */
1047 if (starting_frame_size != get_frame_size ())
1048 something_changed = 1;
1050 /* Even if the frame size remained the same, we might still have
1051 changed elimination offsets, e.g. if find_reloads called
1052 force_const_mem requiring the back end to allocate a constant
1053 pool base register that needs to be saved on the stack. */
1054 else if (!verify_initial_elim_offsets ())
1055 something_changed = 1;
1058 HARD_REG_SET to_spill;
1059 CLEAR_HARD_REG_SET (to_spill);
1060 update_eliminables (&to_spill);
1061 AND_COMPL_HARD_REG_SET (used_spill_regs, to_spill);
1063 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1064 if (TEST_HARD_REG_BIT (to_spill, i))
1066 spill_hard_reg (i, 1);
1069 /* Regardless of the state of spills, if we previously had
1070 a register that we thought we could eliminate, but now can
1071 not eliminate, we must run another pass.
1073 Consider pseudos which have an entry in reg_equiv_* which
1074 reference an eliminable register. We must make another pass
1075 to update reg_equiv_* so that we do not substitute in the
1076 old value from when we thought the elimination could be
1078 something_changed = 1;
1082 select_reload_regs ();
1086 if (insns_need_reload != 0 || did_spill)
1087 something_changed |= finish_spills (global);
1089 if (! something_changed)
1092 if (caller_save_needed)
1093 delete_caller_save_insns ();
1095 obstack_free (&reload_obstack, reload_firstobj);
1098 /* If global-alloc was run, notify it of any register eliminations we have
1101 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
1102 if (ep->can_eliminate)
1103 mark_elimination (ep->from, ep->to);
1105 /* If a pseudo has no hard reg, delete the insns that made the equivalence.
1106 If that insn didn't set the register (i.e., it copied the register to
1107 memory), just delete that insn instead of the equivalencing insn plus
1108 anything now dead. If we call delete_dead_insn on that insn, we may
1109 delete the insn that actually sets the register if the register dies
1110 there and that is incorrect. */
1112 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1114 if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
1117 for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
1119 rtx equiv_insn = XEXP (list, 0);
1121 /* If we already deleted the insn or if it may trap, we can't
1122 delete it. The latter case shouldn't happen, but can
1123 if an insn has a variable address, gets a REG_EH_REGION
1124 note added to it, and then gets converted into a load
1125 from a constant address. */
1126 if (NOTE_P (equiv_insn)
1127 || can_throw_internal (equiv_insn))
1129 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
1130 delete_dead_insn (equiv_insn);
1132 SET_INSN_DELETED (equiv_insn);
1137 /* Use the reload registers where necessary
1138 by generating move instructions to move the must-be-register
1139 values into or out of the reload registers. */
1141 if (insns_need_reload != 0 || something_needs_elimination
1142 || something_needs_operands_changed)
1144 HOST_WIDE_INT old_frame_size = get_frame_size ();
1146 reload_as_needed (global);
1148 gcc_assert (old_frame_size == get_frame_size ());
1150 gcc_assert (verify_initial_elim_offsets ());
1153 /* If we were able to eliminate the frame pointer, show that it is no
1154 longer live at the start of any basic block. If it ls live by
1155 virtue of being in a pseudo, that pseudo will be marked live
1156 and hence the frame pointer will be known to be live via that
1159 if (! frame_pointer_needed)
1161 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM);
1163 /* Come here (with failure set nonzero) if we can't get enough spill
1167 CLEAR_REG_SET (&spilled_pseudos);
1168 reload_in_progress = 0;
1170 /* Now eliminate all pseudo regs by modifying them into
1171 their equivalent memory references.
1172 The REG-rtx's for the pseudos are modified in place,
1173 so all insns that used to refer to them now refer to memory.
1175 For a reg that has a reg_equiv_address, all those insns
1176 were changed by reloading so that no insns refer to it any longer;
1177 but the DECL_RTL of a variable decl may refer to it,
1178 and if so this causes the debugging info to mention the variable. */
1180 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
1184 if (reg_equiv_mem[i])
1185 addr = XEXP (reg_equiv_mem[i], 0);
1187 if (reg_equiv_address[i])
1188 addr = reg_equiv_address[i];
1192 if (reg_renumber[i] < 0)
1194 rtx reg = regno_reg_rtx[i];
1196 REG_USERVAR_P (reg) = 0;
1197 PUT_CODE (reg, MEM);
1198 XEXP (reg, 0) = addr;
1199 if (reg_equiv_memory_loc[i])
1200 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc[i]);
1203 MEM_IN_STRUCT_P (reg) = MEM_SCALAR_P (reg) = 0;
1204 MEM_ATTRS (reg) = 0;
1206 MEM_NOTRAP_P (reg) = 1;
1208 else if (reg_equiv_mem[i])
1209 XEXP (reg_equiv_mem[i], 0) = addr;
1213 /* We must set reload_completed now since the cleanup_subreg_operands call
1214 below will re-recognize each insn and reload may have generated insns
1215 which are only valid during and after reload. */
1216 reload_completed = 1;
1218 /* Make a pass over all the insns and delete all USEs which we inserted
1219 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED
1220 notes. Delete all CLOBBER insns, except those that refer to the return
1221 value and the special mem:BLK CLOBBERs added to prevent the scheduler
1222 from misarranging variable-array code, and simplify (subreg (reg))
1223 operands. Also remove all REG_RETVAL and REG_LIBCALL notes since they
1224 are no longer useful or accurate. Strip and regenerate REG_INC notes
1225 that may have been moved around. */
1227 for (insn = first; insn; insn = NEXT_INSN (insn))
1233 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn),
1234 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn));
1236 if ((GET_CODE (PATTERN (insn)) == USE
1237 /* We mark with QImode USEs introduced by reload itself. */
1238 && (GET_MODE (insn) == QImode
1239 || find_reg_note (insn, REG_EQUAL, NULL_RTX)))
1240 || (GET_CODE (PATTERN (insn)) == CLOBBER
1241 && (!MEM_P (XEXP (PATTERN (insn), 0))
1242 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode
1243 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH
1244 && XEXP (XEXP (PATTERN (insn), 0), 0)
1245 != stack_pointer_rtx))
1246 && (!REG_P (XEXP (PATTERN (insn), 0))
1247 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0)))))
1253 /* Some CLOBBERs may survive until here and still reference unassigned
1254 pseudos with const equivalent, which may in turn cause ICE in later
1255 passes if the reference remains in place. */
1256 if (GET_CODE (PATTERN (insn)) == CLOBBER)
1257 replace_pseudos_in (& XEXP (PATTERN (insn), 0),
1258 VOIDmode, PATTERN (insn));
1260 /* Discard obvious no-ops, even without -O. This optimization
1261 is fast and doesn't interfere with debugging. */
1262 if (NONJUMP_INSN_P (insn)
1263 && GET_CODE (PATTERN (insn)) == SET
1264 && REG_P (SET_SRC (PATTERN (insn)))
1265 && REG_P (SET_DEST (PATTERN (insn)))
1266 && (REGNO (SET_SRC (PATTERN (insn)))
1267 == REGNO (SET_DEST (PATTERN (insn)))))
1273 pnote = ®_NOTES (insn);
1276 if (REG_NOTE_KIND (*pnote) == REG_DEAD
1277 || REG_NOTE_KIND (*pnote) == REG_UNUSED
1278 || REG_NOTE_KIND (*pnote) == REG_INC
1279 || REG_NOTE_KIND (*pnote) == REG_RETVAL
1280 || REG_NOTE_KIND (*pnote) == REG_LIBCALL)
1281 *pnote = XEXP (*pnote, 1);
1283 pnote = &XEXP (*pnote, 1);
1287 add_auto_inc_notes (insn, PATTERN (insn));
1290 /* Simplify (subreg (reg)) if it appears as an operand. */
1291 cleanup_subreg_operands (insn);
1293 /* Clean up invalid ASMs so that they don't confuse later passes.
1295 if (asm_noperands (PATTERN (insn)) >= 0)
1297 extract_insn (insn);
1298 if (!constrain_operands (1))
1300 error_for_asm (insn,
1301 "%<asm%> operand has impossible constraints");
1308 /* If we are doing stack checking, give a warning if this function's
1309 frame size is larger than we expect. */
1310 if (flag_stack_check && ! STACK_CHECK_BUILTIN)
1312 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE;
1313 static int verbose_warned = 0;
1315 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1316 if (df_regs_ever_live_p (i) && ! fixed_regs[i] && call_used_regs[i])
1317 size += UNITS_PER_WORD;
1319 if (size > STACK_CHECK_MAX_FRAME_SIZE)
1321 warning (0, "frame size too large for reliable stack checking");
1322 if (! verbose_warned)
1324 warning (0, "try reducing the number of local variables");
1330 /* Indicate that we no longer have known memory locations or constants. */
1331 if (reg_equiv_constant)
1332 free (reg_equiv_constant);
1333 if (reg_equiv_invariant)
1334 free (reg_equiv_invariant);
1335 reg_equiv_constant = 0;
1336 reg_equiv_invariant = 0;
1337 VEC_free (rtx, gc, reg_equiv_memory_loc_vec);
1338 reg_equiv_memory_loc = 0;
1340 if (offsets_known_at)
1341 free (offsets_known_at);
1345 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1346 if (reg_equiv_alt_mem_list[i])
1347 free_EXPR_LIST_list (®_equiv_alt_mem_list[i]);
1348 free (reg_equiv_alt_mem_list);
1350 free (reg_equiv_mem);
1352 free (reg_equiv_address);
1353 free (reg_max_ref_width);
1354 free (reg_old_renumber);
1355 free (pseudo_previous_regs);
1356 free (pseudo_forbidden_regs);
1358 CLEAR_HARD_REG_SET (used_spill_regs);
1359 for (i = 0; i < n_spills; i++)
1360 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]);
1362 /* Free all the insn_chain structures at once. */
1363 obstack_free (&reload_obstack, reload_startobj);
1364 unused_insn_chains = 0;
1365 fixup_abnormal_edges ();
1367 /* Replacing pseudos with their memory equivalents might have
1368 created shared rtx. Subsequent passes would get confused
1369 by this, so unshare everything here. */
1370 unshare_all_rtl_again (first);
1372 #ifdef STACK_BOUNDARY
1373 /* init_emit has set the alignment of the hard frame pointer
1374 to STACK_BOUNDARY. It is very likely no longer valid if
1375 the hard frame pointer was used for register allocation. */
1376 if (!frame_pointer_needed)
1377 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT;
1383 /* Yet another special case. Unfortunately, reg-stack forces people to
1384 write incorrect clobbers in asm statements. These clobbers must not
1385 cause the register to appear in bad_spill_regs, otherwise we'll call
1386 fatal_insn later. We clear the corresponding regnos in the live
1387 register sets to avoid this.
1388 The whole thing is rather sick, I'm afraid. */
1391 maybe_fix_stack_asms (void)
1394 const char *constraints[MAX_RECOG_OPERANDS];
1395 enum machine_mode operand_mode[MAX_RECOG_OPERANDS];
1396 struct insn_chain *chain;
1398 for (chain = reload_insn_chain; chain != 0; chain = chain->next)
1401 HARD_REG_SET clobbered, allowed;
1404 if (! INSN_P (chain->insn)
1405 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0)
1407 pat = PATTERN (chain->insn);
1408 if (GET_CODE (pat) != PARALLEL)
1411 CLEAR_HARD_REG_SET (clobbered);
1412 CLEAR_HARD_REG_SET (allowed);
1414 /* First, make a mask of all stack regs that are clobbered. */
1415 for (i = 0; i < XVECLEN (pat, 0); i++)
1417 rtx t = XVECEXP (pat, 0, i);
1418 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0)))
1419 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0)));
1422 /* Get the operand values and constraints out of the insn. */
1423 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc,
1424 constraints, operand_mode, NULL);
1426 /* For every operand, see what registers are allowed. */
1427 for (i = 0; i < noperands; i++)
1429 const char *p = constraints[i];
1430 /* For every alternative, we compute the class of registers allowed
1431 for reloading in CLS, and merge its contents into the reg set
1433 int cls = (int) NO_REGS;
1439 if (c == '\0' || c == ',' || c == '#')
1441 /* End of one alternative - mark the regs in the current
1442 class, and reset the class. */
1443 IOR_HARD_REG_SET (allowed, reg_class_contents[cls]);
1449 } while (c != '\0' && c != ',');
1457 case '=': case '+': case '*': case '%': case '?': case '!':
1458 case '0': case '1': case '2': case '3': case '4': case 'm':
1459 case '<': case '>': case 'V': case 'o': case '&': case 'E':
1460 case 'F': case 's': case 'i': case 'n': case 'X': case 'I':
1461 case 'J': case 'K': case 'L': case 'M': case 'N': case 'O':
1466 cls = (int) reg_class_subunion[cls]
1467 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1472 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS];
1476 if (EXTRA_ADDRESS_CONSTRAINT (c, p))
1477 cls = (int) reg_class_subunion[cls]
1478 [(int) base_reg_class (VOIDmode, ADDRESS, SCRATCH)];
1480 cls = (int) reg_class_subunion[cls]
1481 [(int) REG_CLASS_FROM_CONSTRAINT (c, p)];
1483 p += CONSTRAINT_LEN (c, p);
1486 /* Those of the registers which are clobbered, but allowed by the
1487 constraints, must be usable as reload registers. So clear them
1488 out of the life information. */
1489 AND_HARD_REG_SET (allowed, clobbered);
1490 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1491 if (TEST_HARD_REG_BIT (allowed, i))
1493 CLEAR_REGNO_REG_SET (&chain->live_throughout, i);
1494 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i);
1501 /* Copy the global variables n_reloads and rld into the corresponding elts
1504 copy_reloads (struct insn_chain *chain)
1506 chain->n_reloads = n_reloads;
1507 chain->rld = obstack_alloc (&reload_obstack,
1508 n_reloads * sizeof (struct reload));
1509 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1510 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1513 /* Walk the chain of insns, and determine for each whether it needs reloads
1514 and/or eliminations. Build the corresponding insns_need_reload list, and
1515 set something_needs_elimination as appropriate. */
1517 calculate_needs_all_insns (int global)
1519 struct insn_chain **pprev_reload = &insns_need_reload;
1520 struct insn_chain *chain, *next = 0;
1522 something_needs_elimination = 0;
1524 reload_insn_firstobj = obstack_alloc (&reload_obstack, 0);
1525 for (chain = reload_insn_chain; chain != 0; chain = next)
1527 rtx insn = chain->insn;
1531 /* Clear out the shortcuts. */
1532 chain->n_reloads = 0;
1533 chain->need_elim = 0;
1534 chain->need_reload = 0;
1535 chain->need_operand_change = 0;
1537 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might
1538 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see
1539 what effects this has on the known offsets at labels. */
1541 if (LABEL_P (insn) || JUMP_P (insn)
1542 || (INSN_P (insn) && REG_NOTES (insn) != 0))
1543 set_label_offsets (insn, insn, 0);
1547 rtx old_body = PATTERN (insn);
1548 int old_code = INSN_CODE (insn);
1549 rtx old_notes = REG_NOTES (insn);
1550 int did_elimination = 0;
1551 int operands_changed = 0;
1552 rtx set = single_set (insn);
1554 /* Skip insns that only set an equivalence. */
1555 if (set && REG_P (SET_DEST (set))
1556 && reg_renumber[REGNO (SET_DEST (set))] < 0
1557 && (reg_equiv_constant[REGNO (SET_DEST (set))]
1558 || (reg_equiv_invariant[REGNO (SET_DEST (set))]))
1559 && reg_equiv_init[REGNO (SET_DEST (set))])
1562 /* If needed, eliminate any eliminable registers. */
1563 if (num_eliminable || num_eliminable_invariants)
1564 did_elimination = eliminate_regs_in_insn (insn, 0);
1566 /* Analyze the instruction. */
1567 operands_changed = find_reloads (insn, 0, spill_indirect_levels,
1568 global, spill_reg_order);
1570 /* If a no-op set needs more than one reload, this is likely
1571 to be something that needs input address reloads. We
1572 can't get rid of this cleanly later, and it is of no use
1573 anyway, so discard it now.
1574 We only do this when expensive_optimizations is enabled,
1575 since this complements reload inheritance / output
1576 reload deletion, and it can make debugging harder. */
1577 if (flag_expensive_optimizations && n_reloads > 1)
1579 rtx set = single_set (insn);
1581 && SET_SRC (set) == SET_DEST (set)
1582 && REG_P (SET_SRC (set))
1583 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER)
1586 /* Delete it from the reload chain. */
1588 chain->prev->next = next;
1590 reload_insn_chain = next;
1592 next->prev = chain->prev;
1593 chain->next = unused_insn_chains;
1594 unused_insn_chains = chain;
1599 update_eliminable_offsets ();
1601 /* Remember for later shortcuts which insns had any reloads or
1602 register eliminations. */
1603 chain->need_elim = did_elimination;
1604 chain->need_reload = n_reloads > 0;
1605 chain->need_operand_change = operands_changed;
1607 /* Discard any register replacements done. */
1608 if (did_elimination)
1610 obstack_free (&reload_obstack, reload_insn_firstobj);
1611 PATTERN (insn) = old_body;
1612 INSN_CODE (insn) = old_code;
1613 REG_NOTES (insn) = old_notes;
1614 something_needs_elimination = 1;
1617 something_needs_operands_changed |= operands_changed;
1621 copy_reloads (chain);
1622 *pprev_reload = chain;
1623 pprev_reload = &chain->next_need_reload;
1630 /* Comparison function for qsort to decide which of two reloads
1631 should be handled first. *P1 and *P2 are the reload numbers. */
1634 reload_reg_class_lower (const void *r1p, const void *r2p)
1636 int r1 = *(const short *) r1p, r2 = *(const short *) r2p;
1639 /* Consider required reloads before optional ones. */
1640 t = rld[r1].optional - rld[r2].optional;
1644 /* Count all solitary classes before non-solitary ones. */
1645 t = ((reg_class_size[(int) rld[r2].class] == 1)
1646 - (reg_class_size[(int) rld[r1].class] == 1));
1650 /* Aside from solitaires, consider all multi-reg groups first. */
1651 t = rld[r2].nregs - rld[r1].nregs;
1655 /* Consider reloads in order of increasing reg-class number. */
1656 t = (int) rld[r1].class - (int) rld[r2].class;
1660 /* If reloads are equally urgent, sort by reload number,
1661 so that the results of qsort leave nothing to chance. */
1665 /* The cost of spilling each hard reg. */
1666 static int spill_cost[FIRST_PSEUDO_REGISTER];
1668 /* When spilling multiple hard registers, we use SPILL_COST for the first
1669 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST
1670 only the first hard reg for a multi-reg pseudo. */
1671 static int spill_add_cost[FIRST_PSEUDO_REGISTER];
1673 /* Update the spill cost arrays, considering that pseudo REG is live. */
1676 count_pseudo (int reg)
1678 int freq = REG_FREQ (reg);
1679 int r = reg_renumber[reg];
1682 if (REGNO_REG_SET_P (&pseudos_counted, reg)
1683 || REGNO_REG_SET_P (&spilled_pseudos, reg))
1686 SET_REGNO_REG_SET (&pseudos_counted, reg);
1688 gcc_assert (r >= 0);
1690 spill_add_cost[r] += freq;
1692 nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1694 spill_cost[r + nregs] += freq;
1697 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the
1698 contents of BAD_SPILL_REGS for the insn described by CHAIN. */
1701 order_regs_for_reload (struct insn_chain *chain)
1704 HARD_REG_SET used_by_pseudos;
1705 HARD_REG_SET used_by_pseudos2;
1706 reg_set_iterator rsi;
1708 COPY_HARD_REG_SET (bad_spill_regs, fixed_reg_set);
1710 memset (spill_cost, 0, sizeof spill_cost);
1711 memset (spill_add_cost, 0, sizeof spill_add_cost);
1713 /* Count number of uses of each hard reg by pseudo regs allocated to it
1714 and then order them by decreasing use. First exclude hard registers
1715 that are live in or across this insn. */
1717 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
1718 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
1719 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos);
1720 IOR_HARD_REG_SET (bad_spill_regs, used_by_pseudos2);
1722 /* Now find out which pseudos are allocated to it, and update
1724 CLEAR_REG_SET (&pseudos_counted);
1726 EXECUTE_IF_SET_IN_REG_SET
1727 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
1731 EXECUTE_IF_SET_IN_REG_SET
1732 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
1736 CLEAR_REG_SET (&pseudos_counted);
1739 /* Vector of reload-numbers showing the order in which the reloads should
1741 static short reload_order[MAX_RELOADS];
1743 /* This is used to keep track of the spill regs used in one insn. */
1744 static HARD_REG_SET used_spill_regs_local;
1746 /* We decided to spill hard register SPILLED, which has a size of
1747 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn,
1748 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will
1749 update SPILL_COST/SPILL_ADD_COST. */
1752 count_spilled_pseudo (int spilled, int spilled_nregs, int reg)
1754 int r = reg_renumber[reg];
1755 int nregs = hard_regno_nregs[r][PSEUDO_REGNO_MODE (reg)];
1757 if (REGNO_REG_SET_P (&spilled_pseudos, reg)
1758 || spilled + spilled_nregs <= r || r + nregs <= spilled)
1761 SET_REGNO_REG_SET (&spilled_pseudos, reg);
1763 spill_add_cost[r] -= REG_FREQ (reg);
1765 spill_cost[r + nregs] -= REG_FREQ (reg);
1768 /* Find reload register to use for reload number ORDER. */
1771 find_reg (struct insn_chain *chain, int order)
1773 int rnum = reload_order[order];
1774 struct reload *rl = rld + rnum;
1775 int best_cost = INT_MAX;
1779 HARD_REG_SET not_usable;
1780 HARD_REG_SET used_by_other_reload;
1781 reg_set_iterator rsi;
1783 COPY_HARD_REG_SET (not_usable, bad_spill_regs);
1784 IOR_HARD_REG_SET (not_usable, bad_spill_regs_global);
1785 IOR_COMPL_HARD_REG_SET (not_usable, reg_class_contents[rl->class]);
1787 CLEAR_HARD_REG_SET (used_by_other_reload);
1788 for (k = 0; k < order; k++)
1790 int other = reload_order[k];
1792 if (rld[other].regno >= 0 && reloads_conflict (other, rnum))
1793 for (j = 0; j < rld[other].nregs; j++)
1794 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j);
1797 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
1799 unsigned int regno = i;
1801 if (! TEST_HARD_REG_BIT (not_usable, regno)
1802 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno)
1803 && HARD_REGNO_MODE_OK (regno, rl->mode))
1805 int this_cost = spill_cost[regno];
1807 unsigned int this_nregs = hard_regno_nregs[regno][rl->mode];
1809 for (j = 1; j < this_nregs; j++)
1811 this_cost += spill_add_cost[regno + j];
1812 if ((TEST_HARD_REG_BIT (not_usable, regno + j))
1813 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j))
1818 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno)
1820 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno)
1822 if (this_cost < best_cost
1823 /* Among registers with equal cost, prefer caller-saved ones, or
1824 use REG_ALLOC_ORDER if it is defined. */
1825 || (this_cost == best_cost
1826 #ifdef REG_ALLOC_ORDER
1827 && (inv_reg_alloc_order[regno]
1828 < inv_reg_alloc_order[best_reg])
1830 && call_used_regs[regno]
1831 && ! call_used_regs[best_reg]
1836 best_cost = this_cost;
1844 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum);
1846 rl->nregs = hard_regno_nregs[best_reg][rl->mode];
1847 rl->regno = best_reg;
1849 EXECUTE_IF_SET_IN_REG_SET
1850 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi)
1852 count_spilled_pseudo (best_reg, rl->nregs, j);
1855 EXECUTE_IF_SET_IN_REG_SET
1856 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi)
1858 count_spilled_pseudo (best_reg, rl->nregs, j);
1861 for (i = 0; i < rl->nregs; i++)
1863 gcc_assert (spill_cost[best_reg + i] == 0);
1864 gcc_assert (spill_add_cost[best_reg + i] == 0);
1865 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i);
1870 /* Find more reload regs to satisfy the remaining need of an insn, which
1872 Do it by ascending class number, since otherwise a reg
1873 might be spilled for a big class and might fail to count
1874 for a smaller class even though it belongs to that class. */
1877 find_reload_regs (struct insn_chain *chain)
1881 /* In order to be certain of getting the registers we need,
1882 we must sort the reloads into order of increasing register class.
1883 Then our grabbing of reload registers will parallel the process
1884 that provided the reload registers. */
1885 for (i = 0; i < chain->n_reloads; i++)
1887 /* Show whether this reload already has a hard reg. */
1888 if (chain->rld[i].reg_rtx)
1890 int regno = REGNO (chain->rld[i].reg_rtx);
1891 chain->rld[i].regno = regno;
1893 = hard_regno_nregs[regno][GET_MODE (chain->rld[i].reg_rtx)];
1896 chain->rld[i].regno = -1;
1897 reload_order[i] = i;
1900 n_reloads = chain->n_reloads;
1901 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload));
1903 CLEAR_HARD_REG_SET (used_spill_regs_local);
1906 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn));
1908 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
1910 /* Compute the order of preference for hard registers to spill. */
1912 order_regs_for_reload (chain);
1914 for (i = 0; i < n_reloads; i++)
1916 int r = reload_order[i];
1918 /* Ignore reloads that got marked inoperative. */
1919 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p)
1920 && ! rld[r].optional
1921 && rld[r].regno == -1)
1922 if (! find_reg (chain, i))
1925 fprintf (dump_file, "reload failure for reload %d\n", r);
1926 spill_failure (chain->insn, rld[r].class);
1932 COPY_HARD_REG_SET (chain->used_spill_regs, used_spill_regs_local);
1933 IOR_HARD_REG_SET (used_spill_regs, used_spill_regs_local);
1935 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload));
1939 select_reload_regs (void)
1941 struct insn_chain *chain;
1943 /* Try to satisfy the needs for each insn. */
1944 for (chain = insns_need_reload; chain != 0;
1945 chain = chain->next_need_reload)
1946 find_reload_regs (chain);
1949 /* Delete all insns that were inserted by emit_caller_save_insns during
1952 delete_caller_save_insns (void)
1954 struct insn_chain *c = reload_insn_chain;
1958 while (c != 0 && c->is_caller_save_insn)
1960 struct insn_chain *next = c->next;
1963 if (c == reload_insn_chain)
1964 reload_insn_chain = next;
1968 next->prev = c->prev;
1970 c->prev->next = next;
1971 c->next = unused_insn_chains;
1972 unused_insn_chains = c;
1980 /* Handle the failure to find a register to spill.
1981 INSN should be one of the insns which needed this particular spill reg. */
1984 spill_failure (rtx insn, enum reg_class class)
1986 if (asm_noperands (PATTERN (insn)) >= 0)
1987 error_for_asm (insn, "can't find a register in class %qs while "
1988 "reloading %<asm%>",
1989 reg_class_names[class]);
1992 error ("unable to find a register to spill in class %qs",
1993 reg_class_names[class]);
1997 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
1998 debug_reload_to_stream (dump_file);
2000 fatal_insn ("this is the insn:", insn);
2004 /* Delete an unneeded INSN and any previous insns who sole purpose is loading
2005 data that is dead in INSN. */
2008 delete_dead_insn (rtx insn)
2010 rtx prev = prev_real_insn (insn);
2013 /* If the previous insn sets a register that dies in our insn, delete it
2015 if (prev && GET_CODE (PATTERN (prev)) == SET
2016 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest))
2017 && reg_mentioned_p (prev_dest, PATTERN (insn))
2018 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest))
2019 && ! side_effects_p (SET_SRC (PATTERN (prev))))
2020 delete_dead_insn (prev);
2022 SET_INSN_DELETED (insn);
2025 /* Modify the home of pseudo-reg I.
2026 The new home is present in reg_renumber[I].
2028 FROM_REG may be the hard reg that the pseudo-reg is being spilled from;
2029 or it may be -1, meaning there is none or it is not relevant.
2030 This is used so that all pseudos spilled from a given hard reg
2031 can share one stack slot. */
2034 alter_reg (int i, int from_reg)
2036 /* When outputting an inline function, this can happen
2037 for a reg that isn't actually used. */
2038 if (regno_reg_rtx[i] == 0)
2041 /* If the reg got changed to a MEM at rtl-generation time,
2043 if (!REG_P (regno_reg_rtx[i]))
2046 /* Modify the reg-rtx to contain the new hard reg
2047 number or else to contain its pseudo reg number. */
2048 SET_REGNO (regno_reg_rtx[i],
2049 reg_renumber[i] >= 0 ? reg_renumber[i] : i);
2051 /* If we have a pseudo that is needed but has no hard reg or equivalent,
2052 allocate a stack slot for it. */
2054 if (reg_renumber[i] < 0
2055 && REG_N_REFS (i) > 0
2056 && reg_equiv_constant[i] == 0
2057 && (reg_equiv_invariant[i] == 0 || reg_equiv_init[i] == 0)
2058 && reg_equiv_memory_loc[i] == 0)
2061 enum machine_mode mode = GET_MODE (regno_reg_rtx[i]);
2062 unsigned int inherent_size = PSEUDO_REGNO_BYTES (i);
2063 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode);
2064 unsigned int total_size = MAX (inherent_size, reg_max_ref_width[i]);
2065 unsigned int min_align = reg_max_ref_width[i] * BITS_PER_UNIT;
2068 /* Each pseudo reg has an inherent size which comes from its own mode,
2069 and a total size which provides room for paradoxical subregs
2070 which refer to the pseudo reg in wider modes.
2072 We can use a slot already allocated if it provides both
2073 enough inherent space and enough total space.
2074 Otherwise, we allocate a new slot, making sure that it has no less
2075 inherent space, and no less total space, then the previous slot. */
2078 alias_set_type alias_set = new_alias_set ();
2080 /* No known place to spill from => no slot to reuse. */
2081 x = assign_stack_local (mode, total_size,
2082 min_align > inherent_align
2083 || total_size > inherent_size ? -1 : 0);
2084 if (BYTES_BIG_ENDIAN)
2085 /* Cancel the big-endian correction done in assign_stack_local.
2086 Get the address of the beginning of the slot.
2087 This is so we can do a big-endian correction unconditionally
2089 adjust = inherent_size - total_size;
2091 /* Nothing can alias this slot except this pseudo. */
2092 set_mem_alias_set (x, alias_set);
2093 dse_record_singleton_alias_set (alias_set, mode);
2096 /* Reuse a stack slot if possible. */
2097 else if (spill_stack_slot[from_reg] != 0
2098 && spill_stack_slot_width[from_reg] >= total_size
2099 && (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2101 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align)
2102 x = spill_stack_slot[from_reg];
2103 /* Allocate a bigger slot. */
2106 /* Compute maximum size needed, both for inherent size
2107 and for total size. */
2110 if (spill_stack_slot[from_reg])
2112 if (GET_MODE_SIZE (GET_MODE (spill_stack_slot[from_reg]))
2114 mode = GET_MODE (spill_stack_slot[from_reg]);
2115 if (spill_stack_slot_width[from_reg] > total_size)
2116 total_size = spill_stack_slot_width[from_reg];
2117 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align)
2118 min_align = MEM_ALIGN (spill_stack_slot[from_reg]);
2121 /* Make a slot with that size. */
2122 x = assign_stack_local (mode, total_size,
2123 min_align > inherent_align
2124 || total_size > inherent_size ? -1 : 0);
2127 /* All pseudos mapped to this slot can alias each other. */
2128 if (spill_stack_slot[from_reg])
2130 alias_set_type alias_set
2131 = MEM_ALIAS_SET (spill_stack_slot[from_reg]);
2132 set_mem_alias_set (x, alias_set);
2133 dse_invalidate_singleton_alias_set (alias_set);
2137 alias_set_type alias_set = new_alias_set ();
2138 set_mem_alias_set (x, alias_set);
2139 dse_record_singleton_alias_set (alias_set, mode);
2142 if (BYTES_BIG_ENDIAN)
2144 /* Cancel the big-endian correction done in assign_stack_local.
2145 Get the address of the beginning of the slot.
2146 This is so we can do a big-endian correction unconditionally
2148 adjust = GET_MODE_SIZE (mode) - total_size;
2151 = adjust_address_nv (x, mode_for_size (total_size
2157 spill_stack_slot[from_reg] = stack_slot;
2158 spill_stack_slot_width[from_reg] = total_size;
2161 /* On a big endian machine, the "address" of the slot
2162 is the address of the low part that fits its inherent mode. */
2163 if (BYTES_BIG_ENDIAN && inherent_size < total_size)
2164 adjust += (total_size - inherent_size);
2166 /* If we have any adjustment to make, or if the stack slot is the
2167 wrong mode, make a new stack slot. */
2168 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust);
2170 /* If we have a decl for the original register, set it for the
2171 memory. If this is a shared MEM, make a copy. */
2172 if (REG_EXPR (regno_reg_rtx[i])
2173 && DECL_P (REG_EXPR (regno_reg_rtx[i])))
2175 rtx decl = DECL_RTL_IF_SET (REG_EXPR (regno_reg_rtx[i]));
2177 /* We can do this only for the DECLs home pseudo, not for
2178 any copies of it, since otherwise when the stack slot
2179 is reused, nonoverlapping_memrefs_p might think they
2181 if (decl && REG_P (decl) && REGNO (decl) == (unsigned) i)
2183 if (from_reg != -1 && spill_stack_slot[from_reg] == x)
2186 set_mem_attrs_from_reg (x, regno_reg_rtx[i]);
2190 /* Save the stack slot for later. */
2191 reg_equiv_memory_loc[i] = x;
2195 /* Mark the slots in regs_ever_live for the hard regs used by
2196 pseudo-reg number REGNO, accessed in MODE. */
2199 mark_home_live_1 (int regno, enum machine_mode mode)
2203 i = reg_renumber[regno];
2206 lim = end_hard_regno (mode, i);
2208 df_set_regs_ever_live(i++, true);
2211 /* Mark the slots in regs_ever_live for the hard regs
2212 used by pseudo-reg number REGNO. */
2215 mark_home_live (int regno)
2217 if (reg_renumber[regno] >= 0)
2218 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno));
2221 /* This function handles the tracking of elimination offsets around branches.
2223 X is a piece of RTL being scanned.
2225 INSN is the insn that it came from, if any.
2227 INITIAL_P is nonzero if we are to set the offset to be the initial
2228 offset and zero if we are setting the offset of the label to be the
2232 set_label_offsets (rtx x, rtx insn, int initial_p)
2234 enum rtx_code code = GET_CODE (x);
2237 struct elim_table *p;
2242 if (LABEL_REF_NONLOCAL_P (x))
2247 /* ... fall through ... */
2250 /* If we know nothing about this label, set the desired offsets. Note
2251 that this sets the offset at a label to be the offset before a label
2252 if we don't know anything about the label. This is not correct for
2253 the label after a BARRIER, but is the best guess we can make. If
2254 we guessed wrong, we will suppress an elimination that might have
2255 been possible had we been able to guess correctly. */
2257 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num])
2259 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2260 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2261 = (initial_p ? reg_eliminate[i].initial_offset
2262 : reg_eliminate[i].offset);
2263 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1;
2266 /* Otherwise, if this is the definition of a label and it is
2267 preceded by a BARRIER, set our offsets to the known offset of
2271 && (tem = prev_nonnote_insn (insn)) != 0
2273 set_offsets_for_label (insn);
2275 /* If neither of the above cases is true, compare each offset
2276 with those previously recorded and suppress any eliminations
2277 where the offsets disagree. */
2279 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
2280 if (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i]
2281 != (initial_p ? reg_eliminate[i].initial_offset
2282 : reg_eliminate[i].offset))
2283 reg_eliminate[i].can_eliminate = 0;
2288 set_label_offsets (PATTERN (insn), insn, initial_p);
2290 /* ... fall through ... */
2294 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched
2295 to indirectly and hence must have all eliminations at their
2297 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1))
2298 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND)
2299 set_label_offsets (XEXP (tem, 0), insn, 1);
2305 /* Each of the labels in the parallel or address vector must be
2306 at their initial offsets. We want the first field for PARALLEL
2307 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */
2309 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++)
2310 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i),
2315 /* We only care about setting PC. If the source is not RETURN,
2316 IF_THEN_ELSE, or a label, disable any eliminations not at
2317 their initial offsets. Similarly if any arm of the IF_THEN_ELSE
2318 isn't one of those possibilities. For branches to a label,
2319 call ourselves recursively.
2321 Note that this can disable elimination unnecessarily when we have
2322 a non-local goto since it will look like a non-constant jump to
2323 someplace in the current function. This isn't a significant
2324 problem since such jumps will normally be when all elimination
2325 pairs are back to their initial offsets. */
2327 if (SET_DEST (x) != pc_rtx)
2330 switch (GET_CODE (SET_SRC (x)))
2337 set_label_offsets (SET_SRC (x), insn, initial_p);
2341 tem = XEXP (SET_SRC (x), 1);
2342 if (GET_CODE (tem) == LABEL_REF)
2343 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2344 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2347 tem = XEXP (SET_SRC (x), 2);
2348 if (GET_CODE (tem) == LABEL_REF)
2349 set_label_offsets (XEXP (tem, 0), insn, initial_p);
2350 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN)
2358 /* If we reach here, all eliminations must be at their initial
2359 offset because we are doing a jump to a variable address. */
2360 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++)
2361 if (p->offset != p->initial_offset)
2362 p->can_eliminate = 0;
2370 /* Scan X and replace any eliminable registers (such as fp) with a
2371 replacement (such as sp), plus an offset.
2373 MEM_MODE is the mode of an enclosing MEM. We need this to know how
2374 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a
2375 MEM, we are allowed to replace a sum of a register and the constant zero
2376 with the register, which we cannot do outside a MEM. In addition, we need
2377 to record the fact that a register is referenced outside a MEM.
2379 If INSN is an insn, it is the insn containing X. If we replace a REG
2380 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a
2381 CLOBBER of the pseudo after INSN so find_equiv_regs will know that
2382 the REG is being modified.
2384 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST).
2385 That's used when we eliminate in expressions stored in notes.
2386 This means, do not set ref_outside_mem even if the reference
2389 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had
2390 replacements done assuming all offsets are at their initial values. If
2391 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we
2392 encounter, return the actual location so that find_reloads will do
2393 the proper thing. */
2396 eliminate_regs_1 (rtx x, enum machine_mode mem_mode, rtx insn,
2397 bool may_use_invariant)
2399 enum rtx_code code = GET_CODE (x);
2400 struct elim_table *ep;
2407 if (! current_function_decl)
2430 /* First handle the case where we encounter a bare register that
2431 is eliminable. Replace it with a PLUS. */
2432 if (regno < FIRST_PSEUDO_REGISTER)
2434 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2436 if (ep->from_rtx == x && ep->can_eliminate)
2437 return plus_constant (ep->to_rtx, ep->previous_offset);
2440 else if (reg_renumber && reg_renumber[regno] < 0
2441 && reg_equiv_invariant && reg_equiv_invariant[regno])
2443 if (may_use_invariant)
2444 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant[regno]),
2445 mem_mode, insn, true);
2446 /* There exists at least one use of REGNO that cannot be
2447 eliminated. Prevent the defining insn from being deleted. */
2448 reg_equiv_init[regno] = NULL_RTX;
2449 alter_reg (regno, -1);
2453 /* You might think handling MINUS in a manner similar to PLUS is a
2454 good idea. It is not. It has been tried multiple times and every
2455 time the change has had to have been reverted.
2457 Other parts of reload know a PLUS is special (gen_reload for example)
2458 and require special code to handle code a reloaded PLUS operand.
2460 Also consider backends where the flags register is clobbered by a
2461 MINUS, but we can emit a PLUS that does not clobber flags (IA-32,
2462 lea instruction comes to mind). If we try to reload a MINUS, we
2463 may kill the flags register that was holding a useful value.
2465 So, please before trying to handle MINUS, consider reload as a
2466 whole instead of this little section as well as the backend issues. */
2468 /* If this is the sum of an eliminable register and a constant, rework
2470 if (REG_P (XEXP (x, 0))
2471 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2472 && CONSTANT_P (XEXP (x, 1)))
2474 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2476 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2478 /* The only time we want to replace a PLUS with a REG (this
2479 occurs when the constant operand of the PLUS is the negative
2480 of the offset) is when we are inside a MEM. We won't want
2481 to do so at other times because that would change the
2482 structure of the insn in a way that reload can't handle.
2483 We special-case the commonest situation in
2484 eliminate_regs_in_insn, so just replace a PLUS with a
2485 PLUS here, unless inside a MEM. */
2486 if (mem_mode != 0 && GET_CODE (XEXP (x, 1)) == CONST_INT
2487 && INTVAL (XEXP (x, 1)) == - ep->previous_offset)
2490 return gen_rtx_PLUS (Pmode, ep->to_rtx,
2491 plus_constant (XEXP (x, 1),
2492 ep->previous_offset));
2495 /* If the register is not eliminable, we are done since the other
2496 operand is a constant. */
2500 /* If this is part of an address, we want to bring any constant to the
2501 outermost PLUS. We will do this by doing register replacement in
2502 our operands and seeing if a constant shows up in one of them.
2504 Note that there is no risk of modifying the structure of the insn,
2505 since we only get called for its operands, thus we are either
2506 modifying the address inside a MEM, or something like an address
2507 operand of a load-address insn. */
2510 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2511 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2513 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)))
2515 /* If one side is a PLUS and the other side is a pseudo that
2516 didn't get a hard register but has a reg_equiv_constant,
2517 we must replace the constant here since it may no longer
2518 be in the position of any operand. */
2519 if (GET_CODE (new0) == PLUS && REG_P (new1)
2520 && REGNO (new1) >= FIRST_PSEUDO_REGISTER
2521 && reg_renumber[REGNO (new1)] < 0
2522 && reg_equiv_constant != 0
2523 && reg_equiv_constant[REGNO (new1)] != 0)
2524 new1 = reg_equiv_constant[REGNO (new1)];
2525 else if (GET_CODE (new1) == PLUS && REG_P (new0)
2526 && REGNO (new0) >= FIRST_PSEUDO_REGISTER
2527 && reg_renumber[REGNO (new0)] < 0
2528 && reg_equiv_constant[REGNO (new0)] != 0)
2529 new0 = reg_equiv_constant[REGNO (new0)];
2531 new = form_sum (new0, new1);
2533 /* As above, if we are not inside a MEM we do not want to
2534 turn a PLUS into something else. We might try to do so here
2535 for an addition of 0 if we aren't optimizing. */
2536 if (! mem_mode && GET_CODE (new) != PLUS)
2537 return gen_rtx_PLUS (GET_MODE (x), new, const0_rtx);
2545 /* If this is the product of an eliminable register and a
2546 constant, apply the distribute law and move the constant out
2547 so that we have (plus (mult ..) ..). This is needed in order
2548 to keep load-address insns valid. This case is pathological.
2549 We ignore the possibility of overflow here. */
2550 if (REG_P (XEXP (x, 0))
2551 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER
2552 && GET_CODE (XEXP (x, 1)) == CONST_INT)
2553 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2555 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate)
2558 /* Refs inside notes don't count for this purpose. */
2559 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST
2560 || GET_CODE (insn) == INSN_LIST)))
2561 ep->ref_outside_mem = 1;
2564 plus_constant (gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)),
2565 ep->previous_offset * INTVAL (XEXP (x, 1)));
2568 /* ... fall through ... */
2572 /* See comments before PLUS about handling MINUS. */
2574 case DIV: case UDIV:
2575 case MOD: case UMOD:
2576 case AND: case IOR: case XOR:
2577 case ROTATERT: case ROTATE:
2578 case ASHIFTRT: case LSHIFTRT: case ASHIFT:
2580 case GE: case GT: case GEU: case GTU:
2581 case LE: case LT: case LEU: case LTU:
2583 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2584 rtx new1 = XEXP (x, 1)
2585 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false) : 0;
2587 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))
2588 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1);
2593 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */
2596 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true);
2597 if (new != XEXP (x, 0))
2599 /* If this is a REG_DEAD note, it is not valid anymore.
2600 Using the eliminated version could result in creating a
2601 REG_DEAD note for the stack or frame pointer. */
2602 if (GET_MODE (x) == REG_DEAD)
2604 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true)
2607 x = gen_rtx_EXPR_LIST (REG_NOTE_KIND (x), new, XEXP (x, 1));
2611 /* ... fall through ... */
2614 /* Now do eliminations in the rest of the chain. If this was
2615 an EXPR_LIST, this might result in allocating more memory than is
2616 strictly needed, but it simplifies the code. */
2619 new = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true);
2620 if (new != XEXP (x, 1))
2622 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new);
2630 /* We do not support elimination of a register that is modified.
2631 elimination_effects has already make sure that this does not
2637 /* We do not support elimination of a register that is modified.
2638 elimination_effects has already make sure that this does not
2639 happen. The only remaining case we need to consider here is
2640 that the increment value may be an eliminable register. */
2641 if (GET_CODE (XEXP (x, 1)) == PLUS
2642 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0))
2644 rtx new = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode,
2647 if (new != XEXP (XEXP (x, 1), 1))
2648 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0),
2649 gen_rtx_PLUS (GET_MODE (x),
2654 case STRICT_LOW_PART:
2656 case SIGN_EXTEND: case ZERO_EXTEND:
2657 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2658 case FLOAT: case FIX:
2659 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2668 new = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false);
2669 if (new != XEXP (x, 0))
2670 return gen_rtx_fmt_e (code, GET_MODE (x), new);
2674 /* Similar to above processing, but preserve SUBREG_BYTE.
2675 Convert (subreg (mem)) to (mem) if not paradoxical.
2676 Also, if we have a non-paradoxical (subreg (pseudo)) and the
2677 pseudo didn't get a hard reg, we must replace this with the
2678 eliminated version of the memory location because push_reload
2679 may do the replacement in certain circumstances. */
2680 if (REG_P (SUBREG_REG (x))
2681 && (GET_MODE_SIZE (GET_MODE (x))
2682 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2683 && reg_equiv_memory_loc != 0
2684 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2686 new = SUBREG_REG (x);
2689 new = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false);
2691 if (new != SUBREG_REG (x))
2693 int x_size = GET_MODE_SIZE (GET_MODE (x));
2694 int new_size = GET_MODE_SIZE (GET_MODE (new));
2697 && ((x_size < new_size
2698 #ifdef WORD_REGISTER_OPERATIONS
2699 /* On these machines, combine can create rtl of the form
2700 (set (subreg:m1 (reg:m2 R) 0) ...)
2701 where m1 < m2, and expects something interesting to
2702 happen to the entire word. Moreover, it will use the
2703 (reg:m2 R) later, expecting all bits to be preserved.
2704 So if the number of words is the same, preserve the
2705 subreg so that push_reload can see it. */
2706 && ! ((x_size - 1) / UNITS_PER_WORD
2707 == (new_size -1 ) / UNITS_PER_WORD)
2710 || x_size == new_size)
2712 return adjust_address_nv (new, GET_MODE (x), SUBREG_BYTE (x));
2714 return gen_rtx_SUBREG (GET_MODE (x), new, SUBREG_BYTE (x));
2720 /* Our only special processing is to pass the mode of the MEM to our
2721 recursive call and copy the flags. While we are here, handle this
2722 case more efficiently. */
2724 replace_equiv_address_nv (x,
2725 eliminate_regs_1 (XEXP (x, 0), GET_MODE (x),
2729 /* Handle insn_list USE that a call to a pure function may generate. */
2730 new = eliminate_regs_1 (XEXP (x, 0), 0, insn, false);
2731 if (new != XEXP (x, 0))
2732 return gen_rtx_USE (GET_MODE (x), new);
2744 /* Process each of our operands recursively. If any have changed, make a
2746 fmt = GET_RTX_FORMAT (code);
2747 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2751 new = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false);
2752 if (new != XEXP (x, i) && ! copied)
2754 x = shallow_copy_rtx (x);
2759 else if (*fmt == 'E')
2762 for (j = 0; j < XVECLEN (x, i); j++)
2764 new = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false);
2765 if (new != XVECEXP (x, i, j) && ! copied_vec)
2767 rtvec new_v = gen_rtvec_v (XVECLEN (x, i),
2771 x = shallow_copy_rtx (x);
2774 XVEC (x, i) = new_v;
2777 XVECEXP (x, i, j) = new;
2786 eliminate_regs (rtx x, enum machine_mode mem_mode, rtx insn)
2788 return eliminate_regs_1 (x, mem_mode, insn, false);
2791 /* Scan rtx X for modifications of elimination target registers. Update
2792 the table of eliminables to reflect the changed state. MEM_MODE is
2793 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */
2796 elimination_effects (rtx x, enum machine_mode mem_mode)
2798 enum rtx_code code = GET_CODE (x);
2799 struct elim_table *ep;
2824 /* First handle the case where we encounter a bare register that
2825 is eliminable. Replace it with a PLUS. */
2826 if (regno < FIRST_PSEUDO_REGISTER)
2828 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2830 if (ep->from_rtx == x && ep->can_eliminate)
2833 ep->ref_outside_mem = 1;
2838 else if (reg_renumber[regno] < 0 && reg_equiv_constant
2839 && reg_equiv_constant[regno]
2840 && ! function_invariant_p (reg_equiv_constant[regno]))
2841 elimination_effects (reg_equiv_constant[regno], mem_mode);
2850 /* If we modify the source of an elimination rule, disable it. */
2851 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2852 if (ep->from_rtx == XEXP (x, 0))
2853 ep->can_eliminate = 0;
2855 /* If we modify the target of an elimination rule by adding a constant,
2856 update its offset. If we modify the target in any other way, we'll
2857 have to disable the rule as well. */
2858 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2859 if (ep->to_rtx == XEXP (x, 0))
2861 int size = GET_MODE_SIZE (mem_mode);
2863 /* If more bytes than MEM_MODE are pushed, account for them. */
2864 #ifdef PUSH_ROUNDING
2865 if (ep->to_rtx == stack_pointer_rtx)
2866 size = PUSH_ROUNDING (size);
2868 if (code == PRE_DEC || code == POST_DEC)
2870 else if (code == PRE_INC || code == POST_INC)
2872 else if (code == PRE_MODIFY || code == POST_MODIFY)
2874 if (GET_CODE (XEXP (x, 1)) == PLUS
2875 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0)
2876 && CONST_INT_P (XEXP (XEXP (x, 1), 1)))
2877 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1));
2879 ep->can_eliminate = 0;
2883 /* These two aren't unary operators. */
2884 if (code == POST_MODIFY || code == PRE_MODIFY)
2887 /* Fall through to generic unary operation case. */
2888 case STRICT_LOW_PART:
2890 case SIGN_EXTEND: case ZERO_EXTEND:
2891 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE:
2892 case FLOAT: case FIX:
2893 case UNSIGNED_FIX: case UNSIGNED_FLOAT:
2902 elimination_effects (XEXP (x, 0), mem_mode);
2906 if (REG_P (SUBREG_REG (x))
2907 && (GET_MODE_SIZE (GET_MODE (x))
2908 <= GET_MODE_SIZE (GET_MODE (SUBREG_REG (x))))
2909 && reg_equiv_memory_loc != 0
2910 && reg_equiv_memory_loc[REGNO (SUBREG_REG (x))] != 0)
2913 elimination_effects (SUBREG_REG (x), mem_mode);
2917 /* If using a register that is the source of an eliminate we still
2918 think can be performed, note it cannot be performed since we don't
2919 know how this register is used. */
2920 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2921 if (ep->from_rtx == XEXP (x, 0))
2922 ep->can_eliminate = 0;
2924 elimination_effects (XEXP (x, 0), mem_mode);
2928 /* If clobbering a register that is the replacement register for an
2929 elimination we still think can be performed, note that it cannot
2930 be performed. Otherwise, we need not be concerned about it. */
2931 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
2932 if (ep->to_rtx == XEXP (x, 0))
2933 ep->can_eliminate = 0;
2935 elimination_effects (XEXP (x, 0), mem_mode);
2939 /* Check for setting a register that we know about. */
2940 if (REG_P (SET_DEST (x)))
2942 /* See if this is setting the replacement register for an
2945 If DEST is the hard frame pointer, we do nothing because we
2946 assume that all assignments to the frame pointer are for
2947 non-local gotos and are being done at a time when they are valid
2948 and do not disturb anything else. Some machines want to
2949 eliminate a fake argument pointer (or even a fake frame pointer)
2950 with either the real frame or the stack pointer. Assignments to
2951 the hard frame pointer must not prevent this elimination. */
2953 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
2955 if (ep->to_rtx == SET_DEST (x)
2956 && SET_DEST (x) != hard_frame_pointer_rtx)
2958 /* If it is being incremented, adjust the offset. Otherwise,
2959 this elimination can't be done. */
2960 rtx src = SET_SRC (x);
2962 if (GET_CODE (src) == PLUS
2963 && XEXP (src, 0) == SET_DEST (x)
2964 && GET_CODE (XEXP (src, 1)) == CONST_INT)
2965 ep->offset -= INTVAL (XEXP (src, 1));
2967 ep->can_eliminate = 0;
2971 elimination_effects (SET_DEST (x), 0);
2972 elimination_effects (SET_SRC (x), 0);
2976 /* Our only special processing is to pass the mode of the MEM to our
2978 elimination_effects (XEXP (x, 0), GET_MODE (x));
2985 fmt = GET_RTX_FORMAT (code);
2986 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
2989 elimination_effects (XEXP (x, i), mem_mode);
2990 else if (*fmt == 'E')
2991 for (j = 0; j < XVECLEN (x, i); j++)
2992 elimination_effects (XVECEXP (x, i, j), mem_mode);
2996 /* Descend through rtx X and verify that no references to eliminable registers
2997 remain. If any do remain, mark the involved register as not
3001 check_eliminable_occurrences (rtx x)
3010 code = GET_CODE (x);
3012 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER)
3014 struct elim_table *ep;
3016 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3017 if (ep->from_rtx == x)
3018 ep->can_eliminate = 0;
3022 fmt = GET_RTX_FORMAT (code);
3023 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++)
3026 check_eliminable_occurrences (XEXP (x, i));
3027 else if (*fmt == 'E')
3030 for (j = 0; j < XVECLEN (x, i); j++)
3031 check_eliminable_occurrences (XVECEXP (x, i, j));
3036 /* Scan INSN and eliminate all eliminable registers in it.
3038 If REPLACE is nonzero, do the replacement destructively. Also
3039 delete the insn as dead it if it is setting an eliminable register.
3041 If REPLACE is zero, do all our allocations in reload_obstack.
3043 If no eliminations were done and this insn doesn't require any elimination
3044 processing (these are not identical conditions: it might be updating sp,
3045 but not referencing fp; this needs to be seen during reload_as_needed so
3046 that the offset between fp and sp can be taken into consideration), zero
3047 is returned. Otherwise, 1 is returned. */
3050 eliminate_regs_in_insn (rtx insn, int replace)
3052 int icode = recog_memoized (insn);
3053 rtx old_body = PATTERN (insn);
3054 int insn_is_asm = asm_noperands (old_body) >= 0;
3055 rtx old_set = single_set (insn);
3059 rtx substed_operand[MAX_RECOG_OPERANDS];
3060 rtx orig_operand[MAX_RECOG_OPERANDS];
3061 struct elim_table *ep;
3062 rtx plus_src, plus_cst_src;
3064 if (! insn_is_asm && icode < 0)
3066 gcc_assert (GET_CODE (PATTERN (insn)) == USE
3067 || GET_CODE (PATTERN (insn)) == CLOBBER
3068 || GET_CODE (PATTERN (insn)) == ADDR_VEC
3069 || GET_CODE (PATTERN (insn)) == ADDR_DIFF_VEC
3070 || GET_CODE (PATTERN (insn)) == ASM_INPUT);
3074 if (old_set != 0 && REG_P (SET_DEST (old_set))
3075 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER)
3077 /* Check for setting an eliminable register. */
3078 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3079 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate)
3081 #if HARD_FRAME_POINTER_REGNUM != FRAME_POINTER_REGNUM
3082 /* If this is setting the frame pointer register to the
3083 hardware frame pointer register and this is an elimination
3084 that will be done (tested above), this insn is really
3085 adjusting the frame pointer downward to compensate for
3086 the adjustment done before a nonlocal goto. */
3087 if (ep->from == FRAME_POINTER_REGNUM
3088 && ep->to == HARD_FRAME_POINTER_REGNUM)
3090 rtx base = SET_SRC (old_set);
3091 rtx base_insn = insn;
3092 HOST_WIDE_INT offset = 0;
3094 while (base != ep->to_rtx)
3096 rtx prev_insn, prev_set;
3098 if (GET_CODE (base) == PLUS
3099 && GET_CODE (XEXP (base, 1)) == CONST_INT)
3101 offset += INTVAL (XEXP (base, 1));
3102 base = XEXP (base, 0);
3104 else if ((prev_insn = prev_nonnote_insn (base_insn)) != 0
3105 && (prev_set = single_set (prev_insn)) != 0
3106 && rtx_equal_p (SET_DEST (prev_set), base))
3108 base = SET_SRC (prev_set);
3109 base_insn = prev_insn;
3115 if (base == ep->to_rtx)
3118 = plus_constant (ep->to_rtx, offset - ep->offset);
3120 new_body = old_body;
3123 new_body = copy_insn (old_body);
3124 if (REG_NOTES (insn))
3125 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3127 PATTERN (insn) = new_body;
3128 old_set = single_set (insn);
3130 /* First see if this insn remains valid when we
3131 make the change. If not, keep the INSN_CODE
3132 the same and let reload fit it up. */
3133 validate_change (insn, &SET_SRC (old_set), src, 1);
3134 validate_change (insn, &SET_DEST (old_set),
3136 if (! apply_change_group ())
3138 SET_SRC (old_set) = src;
3139 SET_DEST (old_set) = ep->to_rtx;
3148 /* In this case this insn isn't serving a useful purpose. We
3149 will delete it in reload_as_needed once we know that this
3150 elimination is, in fact, being done.
3152 If REPLACE isn't set, we can't delete this insn, but needn't
3153 process it since it won't be used unless something changes. */
3156 delete_dead_insn (insn);
3164 /* We allow one special case which happens to work on all machines we
3165 currently support: a single set with the source or a REG_EQUAL
3166 note being a PLUS of an eliminable register and a constant. */
3167 plus_src = plus_cst_src = 0;
3168 if (old_set && REG_P (SET_DEST (old_set)))
3170 if (GET_CODE (SET_SRC (old_set)) == PLUS)
3171 plus_src = SET_SRC (old_set);
3172 /* First see if the source is of the form (plus (...) CST). */
3174 && GET_CODE (XEXP (plus_src, 1)) == CONST_INT)
3175 plus_cst_src = plus_src;
3176 else if (REG_P (SET_SRC (old_set))
3179 /* Otherwise, see if we have a REG_EQUAL note of the form
3180 (plus (...) CST). */
3182 for (links = REG_NOTES (insn); links; links = XEXP (links, 1))
3184 if ((REG_NOTE_KIND (links) == REG_EQUAL
3185 || REG_NOTE_KIND (links) == REG_EQUIV)
3186 && GET_CODE (XEXP (links, 0)) == PLUS
3187 && GET_CODE (XEXP (XEXP (links, 0), 1)) == CONST_INT)
3189 plus_cst_src = XEXP (links, 0);
3195 /* Check that the first operand of the PLUS is a hard reg or
3196 the lowpart subreg of one. */
3199 rtx reg = XEXP (plus_cst_src, 0);
3200 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg))
3201 reg = SUBREG_REG (reg);
3203 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER)
3209 rtx reg = XEXP (plus_cst_src, 0);
3210 HOST_WIDE_INT offset = INTVAL (XEXP (plus_cst_src, 1));
3212 if (GET_CODE (reg) == SUBREG)
3213 reg = SUBREG_REG (reg);
3215 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3216 if (ep->from_rtx == reg && ep->can_eliminate)
3218 rtx to_rtx = ep->to_rtx;
3219 offset += ep->offset;
3220 offset = trunc_int_for_mode (offset, GET_MODE (reg));
3222 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG)
3223 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)),
3225 /* If we have a nonzero offset, and the source is already
3226 a simple REG, the following transformation would
3227 increase the cost of the insn by replacing a simple REG
3228 with (plus (reg sp) CST). So try only when we already
3229 had a PLUS before. */
3230 if (offset == 0 || plus_src)
3232 rtx new_src = plus_constant (to_rtx, offset);
3234 new_body = old_body;
3237 new_body = copy_insn (old_body);
3238 if (REG_NOTES (insn))
3239 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3241 PATTERN (insn) = new_body;
3242 old_set = single_set (insn);
3244 /* First see if this insn remains valid when we make the
3245 change. If not, try to replace the whole pattern with
3246 a simple set (this may help if the original insn was a
3247 PARALLEL that was only recognized as single_set due to
3248 REG_UNUSED notes). If this isn't valid either, keep
3249 the INSN_CODE the same and let reload fix it up. */
3250 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0))
3252 rtx new_pat = gen_rtx_SET (VOIDmode,
3253 SET_DEST (old_set), new_src);
3255 if (!validate_change (insn, &PATTERN (insn), new_pat, 0))
3256 SET_SRC (old_set) = new_src;
3263 /* This can't have an effect on elimination offsets, so skip right
3269 /* Determine the effects of this insn on elimination offsets. */
3270 elimination_effects (old_body, 0);
3272 /* Eliminate all eliminable registers occurring in operands that
3273 can be handled by reload. */
3274 extract_insn (insn);
3275 for (i = 0; i < recog_data.n_operands; i++)
3277 orig_operand[i] = recog_data.operand[i];
3278 substed_operand[i] = recog_data.operand[i];
3280 /* For an asm statement, every operand is eliminable. */
3281 if (insn_is_asm || insn_data[icode].operand[i].eliminable)
3283 bool is_set_src, in_plus;
3285 /* Check for setting a register that we know about. */
3286 if (recog_data.operand_type[i] != OP_IN
3287 && REG_P (orig_operand[i]))
3289 /* If we are assigning to a register that can be eliminated, it
3290 must be as part of a PARALLEL, since the code above handles
3291 single SETs. We must indicate that we can no longer
3292 eliminate this reg. */
3293 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS];
3295 if (ep->from_rtx == orig_operand[i])
3296 ep->can_eliminate = 0;
3299 /* Companion to the above plus substitution, we can allow
3300 invariants as the source of a plain move. */
3302 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set))
3306 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0)
3307 || recog_data.operand_loc[i] == &XEXP (plus_src, 1)))
3311 = eliminate_regs_1 (recog_data.operand[i], 0,
3312 replace ? insn : NULL_RTX,
3313 is_set_src || in_plus);
3314 if (substed_operand[i] != orig_operand[i])
3316 /* Terminate the search in check_eliminable_occurrences at
3318 *recog_data.operand_loc[i] = 0;
3320 /* If an output operand changed from a REG to a MEM and INSN is an
3321 insn, write a CLOBBER insn. */
3322 if (recog_data.operand_type[i] != OP_IN
3323 && REG_P (orig_operand[i])
3324 && MEM_P (substed_operand[i])
3326 emit_insn_after (gen_rtx_CLOBBER (VOIDmode, orig_operand[i]),
3331 for (i = 0; i < recog_data.n_dups; i++)
3332 *recog_data.dup_loc[i]
3333 = *recog_data.operand_loc[(int) recog_data.dup_num[i]];
3335 /* If any eliminable remain, they aren't eliminable anymore. */
3336 check_eliminable_occurrences (old_body);
3338 /* Substitute the operands; the new values are in the substed_operand
3340 for (i = 0; i < recog_data.n_operands; i++)
3341 *recog_data.operand_loc[i] = substed_operand[i];
3342 for (i = 0; i < recog_data.n_dups; i++)
3343 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]];
3345 /* If we are replacing a body that was a (set X (plus Y Z)), try to
3346 re-recognize the insn. We do this in case we had a simple addition
3347 but now can do this as a load-address. This saves an insn in this
3349 If re-recognition fails, the old insn code number will still be used,
3350 and some register operands may have changed into PLUS expressions.
3351 These will be handled by find_reloads by loading them into a register
3356 /* If we aren't replacing things permanently and we changed something,
3357 make another copy to ensure that all the RTL is new. Otherwise
3358 things can go wrong if find_reload swaps commutative operands
3359 and one is inside RTL that has been copied while the other is not. */
3360 new_body = old_body;
3363 new_body = copy_insn (old_body);
3364 if (REG_NOTES (insn))
3365 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn));
3367 PATTERN (insn) = new_body;
3369 /* If we had a move insn but now we don't, rerecognize it. This will
3370 cause spurious re-recognition if the old move had a PARALLEL since
3371 the new one still will, but we can't call single_set without
3372 having put NEW_BODY into the insn and the re-recognition won't
3373 hurt in this rare case. */
3374 /* ??? Why this huge if statement - why don't we just rerecognize the
3378 && ((REG_P (SET_SRC (old_set))
3379 && (GET_CODE (new_body) != SET
3380 || !REG_P (SET_SRC (new_body))))
3381 /* If this was a load from or store to memory, compare
3382 the MEM in recog_data.operand to the one in the insn.
3383 If they are not equal, then rerecognize the insn. */
3385 && ((MEM_P (SET_SRC (old_set))
3386 && SET_SRC (old_set) != recog_data.operand[1])
3387 || (MEM_P (SET_DEST (old_set))
3388 && SET_DEST (old_set) != recog_data.operand[0])))
3389 /* If this was an add insn before, rerecognize. */
3390 || GET_CODE (SET_SRC (old_set)) == PLUS))
3392 int new_icode = recog (PATTERN (insn), insn, 0);
3394 INSN_CODE (insn) = new_icode;
3398 /* Restore the old body. If there were any changes to it, we made a copy
3399 of it while the changes were still in place, so we'll correctly return
3400 a modified insn below. */
3403 /* Restore the old body. */
3404 for (i = 0; i < recog_data.n_operands; i++)
3405 *recog_data.operand_loc[i] = orig_operand[i];
3406 for (i = 0; i < recog_data.n_dups; i++)
3407 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]];
3410 /* Update all elimination pairs to reflect the status after the current
3411 insn. The changes we make were determined by the earlier call to
3412 elimination_effects.
3414 We also detect cases where register elimination cannot be done,
3415 namely, if a register would be both changed and referenced outside a MEM
3416 in the resulting insn since such an insn is often undefined and, even if
3417 not, we cannot know what meaning will be given to it. Note that it is
3418 valid to have a register used in an address in an insn that changes it
3419 (presumably with a pre- or post-increment or decrement).
3421 If anything changes, return nonzero. */
3423 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3425 if (ep->previous_offset != ep->offset && ep->ref_outside_mem)
3426 ep->can_eliminate = 0;
3428 ep->ref_outside_mem = 0;
3430 if (ep->previous_offset != ep->offset)
3435 /* If we changed something, perform elimination in REG_NOTES. This is
3436 needed even when REPLACE is zero because a REG_DEAD note might refer
3437 to a register that we eliminate and could cause a different number
3438 of spill registers to be needed in the final reload pass than in
3440 if (val && REG_NOTES (insn) != 0)
3442 = eliminate_regs_1 (REG_NOTES (insn), 0, REG_NOTES (insn), true);
3447 /* Loop through all elimination pairs.
3448 Recalculate the number not at initial offset.
3450 Compute the maximum offset (minimum offset if the stack does not
3451 grow downward) for each elimination pair. */
3454 update_eliminable_offsets (void)
3456 struct elim_table *ep;
3458 num_not_at_initial_offset = 0;
3459 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3461 ep->previous_offset = ep->offset;
3462 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3463 num_not_at_initial_offset++;
3467 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register
3468 replacement we currently believe is valid, mark it as not eliminable if X
3469 modifies DEST in any way other than by adding a constant integer to it.
3471 If DEST is the frame pointer, we do nothing because we assume that
3472 all assignments to the hard frame pointer are nonlocal gotos and are being
3473 done at a time when they are valid and do not disturb anything else.
3474 Some machines want to eliminate a fake argument pointer with either the
3475 frame or stack pointer. Assignments to the hard frame pointer must not
3476 prevent this elimination.
3478 Called via note_stores from reload before starting its passes to scan
3479 the insns of the function. */
3482 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED)
3486 /* A SUBREG of a hard register here is just changing its mode. We should
3487 not see a SUBREG of an eliminable hard register, but check just in
3489 if (GET_CODE (dest) == SUBREG)
3490 dest = SUBREG_REG (dest);
3492 if (dest == hard_frame_pointer_rtx)
3495 for (i = 0; i < NUM_ELIMINABLE_REGS; i++)
3496 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx
3497 && (GET_CODE (x) != SET
3498 || GET_CODE (SET_SRC (x)) != PLUS
3499 || XEXP (SET_SRC (x), 0) != dest
3500 || GET_CODE (XEXP (SET_SRC (x), 1)) != CONST_INT))
3502 reg_eliminate[i].can_eliminate_previous
3503 = reg_eliminate[i].can_eliminate = 0;
3508 /* Verify that the initial elimination offsets did not change since the
3509 last call to set_initial_elim_offsets. This is used to catch cases
3510 where something illegal happened during reload_as_needed that could
3511 cause incorrect code to be generated if we did not check for it. */
3514 verify_initial_elim_offsets (void)
3518 if (!num_eliminable)
3521 #ifdef ELIMINABLE_REGS
3523 struct elim_table *ep;
3525 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3527 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t);
3528 if (t != ep->initial_offset)
3533 INITIAL_FRAME_POINTER_OFFSET (t);
3534 if (t != reg_eliminate[0].initial_offset)
3541 /* Reset all offsets on eliminable registers to their initial values. */
3544 set_initial_elim_offsets (void)
3546 struct elim_table *ep = reg_eliminate;
3548 #ifdef ELIMINABLE_REGS
3549 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3551 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset);
3552 ep->previous_offset = ep->offset = ep->initial_offset;
3555 INITIAL_FRAME_POINTER_OFFSET (ep->initial_offset);
3556 ep->previous_offset = ep->offset = ep->initial_offset;
3559 num_not_at_initial_offset = 0;
3562 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */
3565 set_initial_eh_label_offset (rtx label)
3567 set_label_offsets (label, NULL_RTX, 1);
3570 /* Initialize the known label offsets.
3571 Set a known offset for each forced label to be at the initial offset
3572 of each elimination. We do this because we assume that all
3573 computed jumps occur from a location where each elimination is
3574 at its initial offset.
3575 For all other labels, show that we don't know the offsets. */
3578 set_initial_label_offsets (void)
3581 memset (offsets_known_at, 0, num_labels);
3583 for (x = forced_labels; x; x = XEXP (x, 1))
3585 set_label_offsets (XEXP (x, 0), NULL_RTX, 1);
3587 for_each_eh_label (set_initial_eh_label_offset);
3590 /* Set all elimination offsets to the known values for the code label given
3594 set_offsets_for_label (rtx insn)
3597 int label_nr = CODE_LABEL_NUMBER (insn);
3598 struct elim_table *ep;
3600 num_not_at_initial_offset = 0;
3601 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++)
3603 ep->offset = ep->previous_offset
3604 = offsets_at[label_nr - first_label_num][i];
3605 if (ep->can_eliminate && ep->offset != ep->initial_offset)
3606 num_not_at_initial_offset++;
3610 /* See if anything that happened changes which eliminations are valid.
3611 For example, on the SPARC, whether or not the frame pointer can
3612 be eliminated can depend on what registers have been used. We need
3613 not check some conditions again (such as flag_omit_frame_pointer)
3614 since they can't have changed. */
3617 update_eliminables (HARD_REG_SET *pset)
3619 int previous_frame_pointer_needed = frame_pointer_needed;
3620 struct elim_table *ep;
3622 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3623 if ((ep->from == HARD_FRAME_POINTER_REGNUM && FRAME_POINTER_REQUIRED)
3624 #ifdef ELIMINABLE_REGS
3625 || ! CAN_ELIMINATE (ep->from, ep->to)
3628 ep->can_eliminate = 0;
3630 /* Look for the case where we have discovered that we can't replace
3631 register A with register B and that means that we will now be
3632 trying to replace register A with register C. This means we can
3633 no longer replace register C with register B and we need to disable
3634 such an elimination, if it exists. This occurs often with A == ap,
3635 B == sp, and C == fp. */
3637 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3639 struct elim_table *op;
3642 if (! ep->can_eliminate && ep->can_eliminate_previous)
3644 /* Find the current elimination for ep->from, if there is a
3646 for (op = reg_eliminate;
3647 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3648 if (op->from == ep->from && op->can_eliminate)
3654 /* See if there is an elimination of NEW_TO -> EP->TO. If so,
3656 for (op = reg_eliminate;
3657 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++)
3658 if (op->from == new_to && op->to == ep->to)
3659 op->can_eliminate = 0;
3663 /* See if any registers that we thought we could eliminate the previous
3664 time are no longer eliminable. If so, something has changed and we
3665 must spill the register. Also, recompute the number of eliminable
3666 registers and see if the frame pointer is needed; it is if there is
3667 no elimination of the frame pointer that we can perform. */
3669 frame_pointer_needed = 1;
3670 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3672 if (ep->can_eliminate && ep->from == FRAME_POINTER_REGNUM
3673 && ep->to != HARD_FRAME_POINTER_REGNUM)
3674 frame_pointer_needed = 0;
3676 if (! ep->can_eliminate && ep->can_eliminate_previous)
3678 ep->can_eliminate_previous = 0;
3679 SET_HARD_REG_BIT (*pset, ep->from);
3684 /* If we didn't need a frame pointer last time, but we do now, spill
3685 the hard frame pointer. */
3686 if (frame_pointer_needed && ! previous_frame_pointer_needed)
3687 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM);
3690 /* Return true if X is used as the target register of an elimination. */
3693 elimination_target_reg_p (rtx x)
3695 struct elim_table *ep;
3697 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3698 if (ep->to_rtx == x && ep->can_eliminate)
3704 /* Initialize the table of registers to eliminate. */
3707 init_elim_table (void)
3709 struct elim_table *ep;
3710 #ifdef ELIMINABLE_REGS
3711 const struct elim_table_1 *ep1;
3715 reg_eliminate = xcalloc (sizeof (struct elim_table), NUM_ELIMINABLE_REGS);
3717 /* Does this function require a frame pointer? */
3719 frame_pointer_needed = (! flag_omit_frame_pointer
3720 /* ?? If EXIT_IGNORE_STACK is set, we will not save
3721 and restore sp for alloca. So we can't eliminate
3722 the frame pointer in that case. At some point,
3723 we should improve this by emitting the
3724 sp-adjusting insns for this case. */
3725 || (current_function_calls_alloca
3726 && EXIT_IGNORE_STACK)
3727 || current_function_accesses_prior_frames
3728 || FRAME_POINTER_REQUIRED);
3732 #ifdef ELIMINABLE_REGS
3733 for (ep = reg_eliminate, ep1 = reg_eliminate_1;
3734 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++)
3736 ep->from = ep1->from;
3738 ep->can_eliminate = ep->can_eliminate_previous
3739 = (CAN_ELIMINATE (ep->from, ep->to)
3740 && ! (ep->to == STACK_POINTER_REGNUM && frame_pointer_needed));
3743 reg_eliminate[0].from = reg_eliminate_1[0].from;
3744 reg_eliminate[0].to = reg_eliminate_1[0].to;
3745 reg_eliminate[0].can_eliminate = reg_eliminate[0].can_eliminate_previous
3746 = ! frame_pointer_needed;
3749 /* Count the number of eliminable registers and build the FROM and TO
3750 REG rtx's. Note that code in gen_rtx_REG will cause, e.g.,
3751 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx.
3752 We depend on this. */
3753 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++)
3755 num_eliminable += ep->can_eliminate;
3756 ep->from_rtx = gen_rtx_REG (Pmode, ep->from);
3757 ep->to_rtx = gen_rtx_REG (Pmode, ep->to);
3761 /* Kick all pseudos out of hard register REGNO.
3763 If CANT_ELIMINATE is nonzero, it means that we are doing this spill
3764 because we found we can't eliminate some register. In the case, no pseudos
3765 are allowed to be in the register, even if they are only in a block that
3766 doesn't require spill registers, unlike the case when we are spilling this
3767 hard reg to produce another spill register.
3769 Return nonzero if any pseudos needed to be kicked out. */
3772 spill_hard_reg (unsigned int regno, int cant_eliminate)
3778 SET_HARD_REG_BIT (bad_spill_regs_global, regno);
3779 df_set_regs_ever_live (regno, true);
3782 /* Spill every pseudo reg that was allocated to this reg
3783 or to something that overlaps this reg. */
3785 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
3786 if (reg_renumber[i] >= 0
3787 && (unsigned int) reg_renumber[i] <= regno
3788 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno)
3789 SET_REGNO_REG_SET (&spilled_pseudos, i);
3792 /* After find_reload_regs has been run for all insn that need reloads,
3793 and/or spill_hard_regs was called, this function is used to actually
3794 spill pseudo registers and try to reallocate them. It also sets up the
3795 spill_regs array for use by choose_reload_regs. */
3798 finish_spills (int global)
3800 struct insn_chain *chain;
3801 int something_changed = 0;
3803 reg_set_iterator rsi;
3805 /* Build the spill_regs array for the function. */
3806 /* If there are some registers still to eliminate and one of the spill regs
3807 wasn't ever used before, additional stack space may have to be
3808 allocated to store this register. Thus, we may have changed the offset
3809 between the stack and frame pointers, so mark that something has changed.
3811 One might think that we need only set VAL to 1 if this is a call-used
3812 register. However, the set of registers that must be saved by the
3813 prologue is not identical to the call-used set. For example, the
3814 register used by the call insn for the return PC is a call-used register,
3815 but must be saved by the prologue. */
3818 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++)
3819 if (TEST_HARD_REG_BIT (used_spill_regs, i))
3821 spill_reg_order[i] = n_spills;
3822 spill_regs[n_spills++] = i;
3823 if (num_eliminable && ! df_regs_ever_live_p (i))
3824 something_changed = 1;
3825 df_set_regs_ever_live (i, true);
3828 spill_reg_order[i] = -1;
3830 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi)
3832 /* Record the current hard register the pseudo is allocated to in
3833 pseudo_previous_regs so we avoid reallocating it to the same
3834 hard reg in a later pass. */
3835 gcc_assert (reg_renumber[i] >= 0);
3837 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]);
3838 /* Mark it as no longer having a hard register home. */
3839 reg_renumber[i] = -1;
3840 /* We will need to scan everything again. */
3841 something_changed = 1;
3844 /* Retry global register allocation if possible. */
3847 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET));
3848 /* For every insn that needs reloads, set the registers used as spill
3849 regs in pseudo_forbidden_regs for every pseudo live across the
3851 for (chain = insns_need_reload; chain; chain = chain->next_need_reload)
3853 EXECUTE_IF_SET_IN_REG_SET
3854 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi)
3856 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3857 chain->used_spill_regs);
3859 EXECUTE_IF_SET_IN_REG_SET
3860 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi)
3862 IOR_HARD_REG_SET (pseudo_forbidden_regs[i],
3863 chain->used_spill_regs);
3867 /* Retry allocating the spilled pseudos. For each reg, merge the
3868 various reg sets that indicate which hard regs can't be used,
3869 and call retry_global_alloc.
3870 We change spill_pseudos here to only contain pseudos that did not
3871 get a new hard register. */
3872 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3873 if (reg_old_renumber[i] != reg_renumber[i])
3875 HARD_REG_SET forbidden;
3876 COPY_HARD_REG_SET (forbidden, bad_spill_regs_global);
3877 IOR_HARD_REG_SET (forbidden, pseudo_forbidden_regs[i]);
3878 IOR_HARD_REG_SET (forbidden, pseudo_previous_regs[i]);
3879 retry_global_alloc (i, forbidden);
3880 if (reg_renumber[i] >= 0)
3881 CLEAR_REGNO_REG_SET (&spilled_pseudos, i);
3885 /* Fix up the register information in the insn chain.
3886 This involves deleting those of the spilled pseudos which did not get
3887 a new hard register home from the live_{before,after} sets. */
3888 for (chain = reload_insn_chain; chain; chain = chain->next)
3890 HARD_REG_SET used_by_pseudos;
3891 HARD_REG_SET used_by_pseudos2;
3893 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos);
3894 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos);
3896 /* Mark any unallocated hard regs as available for spills. That
3897 makes inheritance work somewhat better. */
3898 if (chain->need_reload)
3900 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout);
3901 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set);
3902 IOR_HARD_REG_SET (used_by_pseudos, used_by_pseudos2);
3904 /* Save the old value for the sanity test below. */
3905 COPY_HARD_REG_SET (used_by_pseudos2, chain->used_spill_regs);
3907 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout);
3908 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set);
3909 COMPL_HARD_REG_SET (chain->used_spill_regs, used_by_pseudos);
3910 AND_HARD_REG_SET (chain->used_spill_regs, used_spill_regs);
3912 /* Make sure we only enlarge the set. */
3913 gcc_assert (hard_reg_set_subset_p (used_by_pseudos2,
3914 chain->used_spill_regs));
3918 /* Let alter_reg modify the reg rtx's for the modified pseudos. */
3919 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++)
3921 int regno = reg_renumber[i];
3922 if (reg_old_renumber[i] == regno)
3925 alter_reg (i, reg_old_renumber[i]);
3926 reg_old_renumber[i] = regno;
3930 fprintf (dump_file, " Register %d now on stack.\n\n", i);
3932 fprintf (dump_file, " Register %d now in %d.\n\n",
3933 i, reg_renumber[i]);
3937 return something_changed;
3940 /* Find all paradoxical subregs within X and update reg_max_ref_width. */
3943 scan_paradoxical_subregs (rtx x)
3947 enum rtx_code code = GET_CODE (x);
3958 case CONST_VECTOR: /* shouldn't happen, but just in case. */
3966 if (REG_P (SUBREG_REG (x))
3967 && (GET_MODE_SIZE (GET_MODE (x))
3968 > reg_max_ref_width[REGNO (SUBREG_REG (x))]))
3970 reg_max_ref_width[REGNO (SUBREG_REG (x))]
3971 = GET_MODE_SIZE (GET_MODE (x));
3972 mark_home_live_1 (REGNO (SUBREG_REG (x)), GET_MODE (x));
3980 fmt = GET_RTX_FORMAT (code);
3981 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
3984 scan_paradoxical_subregs (XEXP (x, i));
3985 else if (fmt[i] == 'E')
3988 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
3989 scan_paradoxical_subregs (XVECEXP (x, i, j));
3994 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note,
3995 examine all of the reload insns between PREV and NEXT exclusive, and
3996 annotate all that may trap. */
3999 fixup_eh_region_note (rtx insn, rtx prev, rtx next)
4001 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
4002 unsigned int trap_count;
4008 if (may_trap_p (PATTERN (insn)))
4012 remove_note (insn, note);
4016 for (i = NEXT_INSN (prev); i != next; i = NEXT_INSN (i))
4017 if (INSN_P (i) && i != insn && may_trap_p (PATTERN (i)))
4021 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (note, 0), REG_NOTES (i));
4025 /* Reload pseudo-registers into hard regs around each insn as needed.
4026 Additional register load insns are output before the insn that needs it
4027 and perhaps store insns after insns that modify the reloaded pseudo reg.
4029 reg_last_reload_reg and reg_reloaded_contents keep track of
4030 which registers are already available in reload registers.
4031 We update these for the reloads that we perform,
4032 as the insns are scanned. */
4035 reload_as_needed (int live_known)
4037 struct insn_chain *chain;
4038 #if defined (AUTO_INC_DEC)
4043 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx);
4044 memset (spill_reg_store, 0, sizeof spill_reg_store);
4045 reg_last_reload_reg = XCNEWVEC (rtx, max_regno);
4046 INIT_REG_SET (®_has_output_reload);
4047 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4048 CLEAR_HARD_REG_SET (reg_reloaded_call_part_clobbered);
4050 set_initial_elim_offsets ();
4052 for (chain = reload_insn_chain; chain; chain = chain->next)
4055 rtx insn = chain->insn;
4056 rtx old_next = NEXT_INSN (insn);
4058 /* If we pass a label, copy the offsets from the label information
4059 into the current offsets of each elimination. */
4061 set_offsets_for_label (insn);
4063 else if (INSN_P (insn))
4065 regset_head regs_to_forget;
4066 INIT_REG_SET (®s_to_forget);
4067 note_stores (PATTERN (insn), forget_old_reloads_1, ®s_to_forget);
4069 /* If this is a USE and CLOBBER of a MEM, ensure that any
4070 references to eliminable registers have been removed. */
4072 if ((GET_CODE (PATTERN (insn)) == USE
4073 || GET_CODE (PATTERN (insn)) == CLOBBER)
4074 && MEM_P (XEXP (PATTERN (insn), 0)))
4075 XEXP (XEXP (PATTERN (insn), 0), 0)
4076 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0),
4077 GET_MODE (XEXP (PATTERN (insn), 0)),
4080 /* If we need to do register elimination processing, do so.
4081 This might delete the insn, in which case we are done. */
4082 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim)
4084 eliminate_regs_in_insn (insn, 1);
4087 update_eliminable_offsets ();
4088 CLEAR_REG_SET (®s_to_forget);
4093 /* If need_elim is nonzero but need_reload is zero, one might think
4094 that we could simply set n_reloads to 0. However, find_reloads
4095 could have done some manipulation of the insn (such as swapping
4096 commutative operands), and these manipulations are lost during
4097 the first pass for every insn that needs register elimination.
4098 So the actions of find_reloads must be redone here. */
4100 if (! chain->need_elim && ! chain->need_reload
4101 && ! chain->need_operand_change)
4103 /* First find the pseudo regs that must be reloaded for this insn.
4104 This info is returned in the tables reload_... (see reload.h).
4105 Also modify the body of INSN by substituting RELOAD
4106 rtx's for those pseudo regs. */
4109 CLEAR_REG_SET (®_has_output_reload);
4110 CLEAR_HARD_REG_SET (reg_is_output_reload);
4112 find_reloads (insn, 1, spill_indirect_levels, live_known,
4118 rtx next = NEXT_INSN (insn);
4121 prev = PREV_INSN (insn);
4123 /* Now compute which reload regs to reload them into. Perhaps
4124 reusing reload regs from previous insns, or else output
4125 load insns to reload them. Maybe output store insns too.
4126 Record the choices of reload reg in reload_reg_rtx. */
4127 choose_reload_regs (chain);
4129 /* Merge any reloads that we didn't combine for fear of
4130 increasing the number of spill registers needed but now
4131 discover can be safely merged. */
4132 if (SMALL_REGISTER_CLASSES)
4133 merge_assigned_reloads (insn);
4135 /* Generate the insns to reload operands into or out of
4136 their reload regs. */
4137 emit_reload_insns (chain);
4139 /* Substitute the chosen reload regs from reload_reg_rtx
4140 into the insn's body (or perhaps into the bodies of other
4141 load and store insn that we just made for reloading
4142 and that we moved the structure into). */
4143 subst_reloads (insn);
4145 /* Adjust the exception region notes for loads and stores. */
4146 if (flag_non_call_exceptions && !CALL_P (insn))
4147 fixup_eh_region_note (insn, prev, next);
4149 /* If this was an ASM, make sure that all the reload insns
4150 we have generated are valid. If not, give an error
4152 if (asm_noperands (PATTERN (insn)) >= 0)
4153 for (p = NEXT_INSN (prev); p != next; p = NEXT_INSN (p))
4154 if (p != insn && INSN_P (p)
4155 && GET_CODE (PATTERN (p)) != USE
4156 && (recog_memoized (p) < 0
4157 || (extract_insn (p), ! constrain_operands (1))))
4159 error_for_asm (insn,
4160 "%<asm%> operand requires "
4161 "impossible reload");
4166 if (num_eliminable && chain->need_elim)
4167 update_eliminable_offsets ();
4169 /* Any previously reloaded spilled pseudo reg, stored in this insn,
4170 is no longer validly lying around to save a future reload.
4171 Note that this does not detect pseudos that were reloaded
4172 for this insn in order to be stored in
4173 (obeying register constraints). That is correct; such reload
4174 registers ARE still valid. */
4175 forget_marked_reloads (®s_to_forget);
4176 CLEAR_REG_SET (®s_to_forget);
4178 /* There may have been CLOBBER insns placed after INSN. So scan
4179 between INSN and NEXT and use them to forget old reloads. */
4180 for (x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x))
4181 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER)
4182 note_stores (PATTERN (x), forget_old_reloads_1, NULL);
4185 /* Likewise for regs altered by auto-increment in this insn.
4186 REG_INC notes have been changed by reloading:
4187 find_reloads_address_1 records substitutions for them,
4188 which have been performed by subst_reloads above. */
4189 for (i = n_reloads - 1; i >= 0; i--)
4191 rtx in_reg = rld[i].in_reg;
4194 enum rtx_code code = GET_CODE (in_reg);
4195 /* PRE_INC / PRE_DEC will have the reload register ending up
4196 with the same value as the stack slot, but that doesn't
4197 hold true for POST_INC / POST_DEC. Either we have to
4198 convert the memory access to a true POST_INC / POST_DEC,
4199 or we can't use the reload register for inheritance. */
4200 if ((code == POST_INC || code == POST_DEC)
4201 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4202 REGNO (rld[i].reg_rtx))
4203 /* Make sure it is the inc/dec pseudo, and not
4204 some other (e.g. output operand) pseudo. */
4205 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4206 == REGNO (XEXP (in_reg, 0))))
4209 rtx reload_reg = rld[i].reg_rtx;
4210 enum machine_mode mode = GET_MODE (reload_reg);
4214 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p))
4216 /* We really want to ignore REG_INC notes here, so
4217 use PATTERN (p) as argument to reg_set_p . */
4218 if (reg_set_p (reload_reg, PATTERN (p)))
4220 n = count_occurrences (PATTERN (p), reload_reg, 0);
4225 n = validate_replace_rtx (reload_reg,
4226 gen_rtx_fmt_e (code,
4231 /* We must also verify that the constraints
4232 are met after the replacement. */
4235 n = constrain_operands (1);
4239 /* If the constraints were not met, then
4240 undo the replacement. */
4243 validate_replace_rtx (gen_rtx_fmt_e (code,
4256 = gen_rtx_EXPR_LIST (REG_INC, reload_reg,
4258 /* Mark this as having an output reload so that the
4259 REG_INC processing code below won't invalidate
4260 the reload for inheritance. */
4261 SET_HARD_REG_BIT (reg_is_output_reload,
4262 REGNO (reload_reg));
4263 SET_REGNO_REG_SET (®_has_output_reload,
4264 REGNO (XEXP (in_reg, 0)));
4267 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX,
4270 else if ((code == PRE_INC || code == PRE_DEC)
4271 && TEST_HARD_REG_BIT (reg_reloaded_valid,
4272 REGNO (rld[i].reg_rtx))
4273 /* Make sure it is the inc/dec pseudo, and not
4274 some other (e.g. output operand) pseudo. */
4275 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)]
4276 == REGNO (XEXP (in_reg, 0))))
4278 SET_HARD_REG_BIT (reg_is_output_reload,
4279 REGNO (rld[i].reg_rtx));
4280 SET_REGNO_REG_SET (®_has_output_reload,
4281 REGNO (XEXP (in_reg, 0)));
4285 /* If a pseudo that got a hard register is auto-incremented,
4286 we must purge records of copying it into pseudos without
4288 for (x = REG_NOTES (insn); x; x = XEXP (x, 1))
4289 if (REG_NOTE_KIND (x) == REG_INC)
4291 /* See if this pseudo reg was reloaded in this insn.
4292 If so, its last-reload info is still valid
4293 because it is based on this insn's reload. */
4294 for (i = 0; i < n_reloads; i++)
4295 if (rld[i].out == XEXP (x, 0))
4299 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL);
4303 /* A reload reg's contents are unknown after a label. */
4305 CLEAR_HARD_REG_SET (reg_reloaded_valid);
4307 /* Don't assume a reload reg is still good after a call insn
4308 if it is a call-used reg, or if it contains a value that will
4309 be partially clobbered by the call. */
4310 else if (CALL_P (insn))
4312 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, call_used_reg_set);
4313 AND_COMPL_HARD_REG_SET (reg_reloaded_valid, reg_reloaded_call_part_clobbered);
4318 free (reg_last_reload_reg);
4319 CLEAR_REG_SET (®_has_output_reload);
4322 /* Discard all record of any value reloaded from X,
4323 or reloaded in X from someplace else;
4324 unless X is an output reload reg of the current insn.
4326 X may be a hard reg (the reload reg)
4327 or it may be a pseudo reg that was reloaded from.
4329 When DATA is non-NULL just mark the registers in regset
4330 to be forgotten later. */
4333 forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED,
4338 regset regs = (regset) data;
4340 /* note_stores does give us subregs of hard regs,
4341 subreg_regno_offset requires a hard reg. */
4342 while (GET_CODE (x) == SUBREG)
4344 /* We ignore the subreg offset when calculating the regno,
4345 because we are using the entire underlying hard register
4355 if (regno >= FIRST_PSEUDO_REGISTER)
4361 nr = hard_regno_nregs[regno][GET_MODE (x)];
4362 /* Storing into a spilled-reg invalidates its contents.
4363 This can happen if a block-local pseudo is allocated to that reg
4364 and it wasn't spilled because this block's total need is 0.
4365 Then some insn might have an optional reload and use this reg. */
4367 for (i = 0; i < nr; i++)
4368 /* But don't do this if the reg actually serves as an output
4369 reload reg in the current instruction. */
4371 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i))
4373 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i);
4374 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, regno + i);
4375 spill_reg_store[regno + i] = 0;
4381 SET_REGNO_REG_SET (regs, regno + nr);
4384 /* Since value of X has changed,
4385 forget any value previously copied from it. */
4388 /* But don't forget a copy if this is the output reload
4389 that establishes the copy's validity. */
4391 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr))
4392 reg_last_reload_reg[regno + nr] = 0;
4396 /* Forget the reloads marked in regset by previous function. */
4398 forget_marked_reloads (regset regs)
4401 reg_set_iterator rsi;
4402 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi)
4404 if (reg < FIRST_PSEUDO_REGISTER
4405 /* But don't do this if the reg actually serves as an output
4406 reload reg in the current instruction. */
4408 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg)))
4410 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg);
4411 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, reg);
4412 spill_reg_store[reg] = 0;
4415 || !REGNO_REG_SET_P (®_has_output_reload, reg))
4416 reg_last_reload_reg[reg] = 0;
4420 /* The following HARD_REG_SETs indicate when each hard register is
4421 used for a reload of various parts of the current insn. */
4423 /* If reg is unavailable for all reloads. */
4424 static HARD_REG_SET reload_reg_unavailable;
4425 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */
4426 static HARD_REG_SET reload_reg_used;
4427 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */
4428 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS];
4429 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */
4430 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS];
4431 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */
4432 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS];
4433 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */
4434 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS];
4435 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */
4436 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS];
4437 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */
4438 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS];
4439 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */
4440 static HARD_REG_SET reload_reg_used_in_op_addr;
4441 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */
4442 static HARD_REG_SET reload_reg_used_in_op_addr_reload;
4443 /* If reg is in use for a RELOAD_FOR_INSN reload. */
4444 static HARD_REG_SET reload_reg_used_in_insn;
4445 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */
4446 static HARD_REG_SET reload_reg_used_in_other_addr;
4448 /* If reg is in use as a reload reg for any sort of reload. */
4449 static HARD_REG_SET reload_reg_used_at_all;
4451 /* If reg is use as an inherited reload. We just mark the first register
4453 static HARD_REG_SET reload_reg_used_for_inherit;
4455 /* Records which hard regs are used in any way, either as explicit use or
4456 by being allocated to a pseudo during any point of the current insn. */
4457 static HARD_REG_SET reg_used_in_insn;
4459 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and
4460 TYPE. MODE is used to indicate how many consecutive regs are
4464 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type,
4465 enum machine_mode mode)
4467 unsigned int nregs = hard_regno_nregs[regno][mode];
4470 for (i = regno; i < nregs + regno; i++)
4475 SET_HARD_REG_BIT (reload_reg_used, i);
4478 case RELOAD_FOR_INPUT_ADDRESS:
4479 SET_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], i);
4482 case RELOAD_FOR_INPADDR_ADDRESS:
4483 SET_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], i);
4486 case RELOAD_FOR_OUTPUT_ADDRESS:
4487 SET_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], i);
4490 case RELOAD_FOR_OUTADDR_ADDRESS:
4491 SET_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], i);
4494 case RELOAD_FOR_OPERAND_ADDRESS:
4495 SET_HARD_REG_BIT (reload_reg_used_in_op_addr, i);
4498 case RELOAD_FOR_OPADDR_ADDR:
4499 SET_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, i);
4502 case RELOAD_FOR_OTHER_ADDRESS:
4503 SET_HARD_REG_BIT (reload_reg_used_in_other_addr, i);
4506 case RELOAD_FOR_INPUT:
4507 SET_HARD_REG_BIT (reload_reg_used_in_input[opnum], i);
4510 case RELOAD_FOR_OUTPUT:
4511 SET_HARD_REG_BIT (reload_reg_used_in_output[opnum], i);
4514 case RELOAD_FOR_INSN:
4515 SET_HARD_REG_BIT (reload_reg_used_in_insn, i);
4519 SET_HARD_REG_BIT (reload_reg_used_at_all, i);
4523 /* Similarly, but show REGNO is no longer in use for a reload. */
4526 clear_reload_reg_in_use (unsigned int regno, int opnum,
4527 enum reload_type type, enum machine_mode mode)
4529 unsigned int nregs = hard_regno_nregs[regno][mode];
4530 unsigned int start_regno, end_regno, r;
4532 /* A complication is that for some reload types, inheritance might
4533 allow multiple reloads of the same types to share a reload register.
4534 We set check_opnum if we have to check only reloads with the same
4535 operand number, and check_any if we have to check all reloads. */
4536 int check_opnum = 0;
4538 HARD_REG_SET *used_in_set;
4543 used_in_set = &reload_reg_used;
4546 case RELOAD_FOR_INPUT_ADDRESS:
4547 used_in_set = &reload_reg_used_in_input_addr[opnum];
4550 case RELOAD_FOR_INPADDR_ADDRESS:
4552 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum];
4555 case RELOAD_FOR_OUTPUT_ADDRESS:
4556 used_in_set = &reload_reg_used_in_output_addr[opnum];
4559 case RELOAD_FOR_OUTADDR_ADDRESS:
4561 used_in_set = &reload_reg_used_in_outaddr_addr[opnum];
4564 case RELOAD_FOR_OPERAND_ADDRESS:
4565 used_in_set = &reload_reg_used_in_op_addr;
4568 case RELOAD_FOR_OPADDR_ADDR:
4570 used_in_set = &reload_reg_used_in_op_addr_reload;
4573 case RELOAD_FOR_OTHER_ADDRESS:
4574 used_in_set = &reload_reg_used_in_other_addr;
4578 case RELOAD_FOR_INPUT:
4579 used_in_set = &reload_reg_used_in_input[opnum];
4582 case RELOAD_FOR_OUTPUT:
4583 used_in_set = &reload_reg_used_in_output[opnum];
4586 case RELOAD_FOR_INSN:
4587 used_in_set = &reload_reg_used_in_insn;
4592 /* We resolve conflicts with remaining reloads of the same type by
4593 excluding the intervals of reload registers by them from the
4594 interval of freed reload registers. Since we only keep track of
4595 one set of interval bounds, we might have to exclude somewhat
4596 more than what would be necessary if we used a HARD_REG_SET here.
4597 But this should only happen very infrequently, so there should
4598 be no reason to worry about it. */
4600 start_regno = regno;
4601 end_regno = regno + nregs;
4602 if (check_opnum || check_any)
4604 for (i = n_reloads - 1; i >= 0; i--)
4606 if (rld[i].when_needed == type
4607 && (check_any || rld[i].opnum == opnum)
4610 unsigned int conflict_start = true_regnum (rld[i].reg_rtx);
4611 unsigned int conflict_end
4612 = end_hard_regno (rld[i].mode, conflict_start);
4614 /* If there is an overlap with the first to-be-freed register,
4615 adjust the interval start. */
4616 if (conflict_start <= start_regno && conflict_end > start_regno)
4617 start_regno = conflict_end;
4618 /* Otherwise, if there is a conflict with one of the other
4619 to-be-freed registers, adjust the interval end. */
4620 if (conflict_start > start_regno && conflict_start < end_regno)
4621 end_regno = conflict_start;
4626 for (r = start_regno; r < end_regno; r++)
4627 CLEAR_HARD_REG_BIT (*used_in_set, r);
4630 /* 1 if reg REGNO is free as a reload reg for a reload of the sort
4631 specified by OPNUM and TYPE. */
4634 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type)
4638 /* In use for a RELOAD_OTHER means it's not available for anything. */
4639 if (TEST_HARD_REG_BIT (reload_reg_used, regno)
4640 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
4646 /* In use for anything means we can't use it for RELOAD_OTHER. */
4647 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno)
4648 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4649 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4650 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4653 for (i = 0; i < reload_n_operands; i++)
4654 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4655 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4656 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4657 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4658 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4659 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4664 case RELOAD_FOR_INPUT:
4665 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4666 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno))
4669 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4672 /* If it is used for some other input, can't use it. */
4673 for (i = 0; i < reload_n_operands; i++)
4674 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4677 /* If it is used in a later operand's address, can't use it. */
4678 for (i = opnum + 1; i < reload_n_operands; i++)
4679 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4680 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4685 case RELOAD_FOR_INPUT_ADDRESS:
4686 /* Can't use a register if it is used for an input address for this
4687 operand or used as an input in an earlier one. */
4688 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)
4689 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4692 for (i = 0; i < opnum; i++)
4693 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4698 case RELOAD_FOR_INPADDR_ADDRESS:
4699 /* Can't use a register if it is used for an input address
4700 for this operand or used as an input in an earlier
4702 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno))
4705 for (i = 0; i < opnum; i++)
4706 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4711 case RELOAD_FOR_OUTPUT_ADDRESS:
4712 /* Can't use a register if it is used for an output address for this
4713 operand or used as an output in this or a later operand. Note
4714 that multiple output operands are emitted in reverse order, so
4715 the conflicting ones are those with lower indices. */
4716 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno))
4719 for (i = 0; i <= opnum; i++)
4720 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4725 case RELOAD_FOR_OUTADDR_ADDRESS:
4726 /* Can't use a register if it is used for an output address
4727 for this operand or used as an output in this or a
4728 later operand. Note that multiple output operands are
4729 emitted in reverse order, so the conflicting ones are
4730 those with lower indices. */
4731 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno))
4734 for (i = 0; i <= opnum; i++)
4735 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4740 case RELOAD_FOR_OPERAND_ADDRESS:
4741 for (i = 0; i < reload_n_operands; i++)
4742 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4745 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4746 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4748 case RELOAD_FOR_OPADDR_ADDR:
4749 for (i = 0; i < reload_n_operands; i++)
4750 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4753 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno));
4755 case RELOAD_FOR_OUTPUT:
4756 /* This cannot share a register with RELOAD_FOR_INSN reloads, other
4757 outputs, or an operand address for this or an earlier output.
4758 Note that multiple output operands are emitted in reverse order,
4759 so the conflicting ones are those with higher indices. */
4760 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno))
4763 for (i = 0; i < reload_n_operands; i++)
4764 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4767 for (i = opnum; i < reload_n_operands; i++)
4768 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4769 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4774 case RELOAD_FOR_INSN:
4775 for (i = 0; i < reload_n_operands; i++)
4776 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)
4777 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4780 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4781 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno));
4783 case RELOAD_FOR_OTHER_ADDRESS:
4784 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno);
4791 /* Return 1 if the value in reload reg REGNO, as used by a reload
4792 needed for the part of the insn specified by OPNUM and TYPE,
4793 is still available in REGNO at the end of the insn.
4795 We can assume that the reload reg was already tested for availability
4796 at the time it is needed, and we should not check this again,
4797 in case the reg has already been marked in use. */
4800 reload_reg_reaches_end_p (unsigned int regno, int opnum, enum reload_type type)
4807 /* Since a RELOAD_OTHER reload claims the reg for the entire insn,
4808 its value must reach the end. */
4811 /* If this use is for part of the insn,
4812 its value reaches if no subsequent part uses the same register.
4813 Just like the above function, don't try to do this with lots
4816 case RELOAD_FOR_OTHER_ADDRESS:
4817 /* Here we check for everything else, since these don't conflict
4818 with anything else and everything comes later. */
4820 for (i = 0; i < reload_n_operands; i++)
4821 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4822 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4823 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)
4824 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4825 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4826 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4829 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4830 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)
4831 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4832 && ! TEST_HARD_REG_BIT (reload_reg_used, regno));
4834 case RELOAD_FOR_INPUT_ADDRESS:
4835 case RELOAD_FOR_INPADDR_ADDRESS:
4836 /* Similar, except that we check only for this and subsequent inputs
4837 and the address of only subsequent inputs and we do not need
4838 to check for RELOAD_OTHER objects since they are known not to
4841 for (i = opnum; i < reload_n_operands; i++)
4842 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4845 for (i = opnum + 1; i < reload_n_operands; i++)
4846 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4847 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno))
4850 for (i = 0; i < reload_n_operands; i++)
4851 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4852 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4853 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4856 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno))
4859 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4860 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4861 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4863 case RELOAD_FOR_INPUT:
4864 /* Similar to input address, except we start at the next operand for
4865 both input and input address and we do not check for
4866 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these
4869 for (i = opnum + 1; i < reload_n_operands; i++)
4870 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno)
4871 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)
4872 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno))
4875 /* ... fall through ... */
4877 case RELOAD_FOR_OPERAND_ADDRESS:
4878 /* Check outputs and their addresses. */
4880 for (i = 0; i < reload_n_operands; i++)
4881 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4882 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4883 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4886 return (!TEST_HARD_REG_BIT (reload_reg_used, regno));
4888 case RELOAD_FOR_OPADDR_ADDR:
4889 for (i = 0; i < reload_n_operands; i++)
4890 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4891 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)
4892 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno))
4895 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)
4896 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)
4897 && !TEST_HARD_REG_BIT (reload_reg_used, regno));
4899 case RELOAD_FOR_INSN:
4900 /* These conflict with other outputs with RELOAD_OTHER. So
4901 we need only check for output addresses. */
4903 opnum = reload_n_operands;
4905 /* ... fall through ... */
4907 case RELOAD_FOR_OUTPUT:
4908 case RELOAD_FOR_OUTPUT_ADDRESS:
4909 case RELOAD_FOR_OUTADDR_ADDRESS:
4910 /* We already know these can't conflict with a later output. So the
4911 only thing to check are later output addresses.
4912 Note that multiple output operands are emitted in reverse order,
4913 so the conflicting ones are those with lower indices. */
4914 for (i = 0; i < opnum; i++)
4915 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno)
4916 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno))
4927 /* Returns whether R1 and R2 are uniquely chained: the value of one
4928 is used by the other, and that value is not used by any other
4929 reload for this insn. This is used to partially undo the decision
4930 made in find_reloads when in the case of multiple
4931 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all
4932 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS
4933 reloads. This code tries to avoid the conflict created by that
4934 change. It might be cleaner to explicitly keep track of which
4935 RELOAD_FOR_OPADDR_ADDR reload is associated with which
4936 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect
4937 this after the fact. */
4939 reloads_unique_chain_p (int r1, int r2)
4943 /* We only check input reloads. */
4944 if (! rld[r1].in || ! rld[r2].in)
4947 /* Avoid anything with output reloads. */
4948 if (rld[r1].out || rld[r2].out)
4951 /* "chained" means one reload is a component of the other reload,
4952 not the same as the other reload. */
4953 if (rld[r1].opnum != rld[r2].opnum
4954 || rtx_equal_p (rld[r1].in, rld[r2].in)
4955 || rld[r1].optional || rld[r2].optional
4956 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in)
4957 || reg_mentioned_p (rld[r2].in, rld[r1].in)))
4960 for (i = 0; i < n_reloads; i ++)
4961 /* Look for input reloads that aren't our two */
4962 if (i != r1 && i != r2 && rld[i].in)
4964 /* If our reload is mentioned at all, it isn't a simple chain. */
4965 if (reg_mentioned_p (rld[r1].in, rld[i].in))
4971 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register.
4974 This function uses the same algorithm as reload_reg_free_p above. */
4977 reloads_conflict (int r1, int r2)
4979 enum reload_type r1_type = rld[r1].when_needed;
4980 enum reload_type r2_type = rld[r2].when_needed;
4981 int r1_opnum = rld[r1].opnum;
4982 int r2_opnum = rld[r2].opnum;
4984 /* RELOAD_OTHER conflicts with everything. */
4985 if (r2_type == RELOAD_OTHER)
4988 /* Otherwise, check conflicts differently for each type. */
4992 case RELOAD_FOR_INPUT:
4993 return (r2_type == RELOAD_FOR_INSN
4994 || r2_type == RELOAD_FOR_OPERAND_ADDRESS
4995 || r2_type == RELOAD_FOR_OPADDR_ADDR
4996 || r2_type == RELOAD_FOR_INPUT
4997 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS
4998 || r2_type == RELOAD_FOR_INPADDR_ADDRESS)
4999 && r2_opnum > r1_opnum));
5001 case RELOAD_FOR_INPUT_ADDRESS:
5002 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum)
5003 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5005 case RELOAD_FOR_INPADDR_ADDRESS:
5006 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum)
5007 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum));
5009 case RELOAD_FOR_OUTPUT_ADDRESS:
5010 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum)
5011 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5013 case RELOAD_FOR_OUTADDR_ADDRESS:
5014 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum)
5015 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum));
5017 case RELOAD_FOR_OPERAND_ADDRESS:
5018 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN
5019 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS
5020 && !reloads_unique_chain_p (r1, r2)));
5022 case RELOAD_FOR_OPADDR_ADDR:
5023 return (r2_type == RELOAD_FOR_INPUT
5024 || r2_type == RELOAD_FOR_OPADDR_ADDR);
5026 case RELOAD_FOR_OUTPUT:
5027 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT
5028 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS
5029 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS)
5030 && r2_opnum >= r1_opnum));
5032 case RELOAD_FOR_INSN:
5033 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT
5034 || r2_type == RELOAD_FOR_INSN
5035 || r2_type == RELOAD_FOR_OPERAND_ADDRESS);
5037 case RELOAD_FOR_OTHER_ADDRESS:
5038 return r2_type == RELOAD_FOR_OTHER_ADDRESS;
5048 /* Indexed by reload number, 1 if incoming value
5049 inherited from previous insns. */
5050 static char reload_inherited[MAX_RELOADS];
5052 /* For an inherited reload, this is the insn the reload was inherited from,
5053 if we know it. Otherwise, this is 0. */
5054 static rtx reload_inheritance_insn[MAX_RELOADS];
5056 /* If nonzero, this is a place to get the value of the reload,
5057 rather than using reload_in. */
5058 static rtx reload_override_in[MAX_RELOADS];
5060 /* For each reload, the hard register number of the register used,
5061 or -1 if we did not need a register for this reload. */
5062 static int reload_spill_index[MAX_RELOADS];
5064 /* Subroutine of free_for_value_p, used to check a single register.
5065 START_REGNO is the starting regno of the full reload register
5066 (possibly comprising multiple hard registers) that we are considering. */
5069 reload_reg_free_for_value_p (int start_regno, int regno, int opnum,
5070 enum reload_type type, rtx value, rtx out,
5071 int reloadnum, int ignore_address_reloads)
5074 /* Set if we see an input reload that must not share its reload register
5075 with any new earlyclobber, but might otherwise share the reload
5076 register with an output or input-output reload. */
5077 int check_earlyclobber = 0;
5081 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno))
5084 if (out == const0_rtx)
5090 /* We use some pseudo 'time' value to check if the lifetimes of the
5091 new register use would overlap with the one of a previous reload
5092 that is not read-only or uses a different value.
5093 The 'time' used doesn't have to be linear in any shape or form, just
5095 Some reload types use different 'buckets' for each operand.
5096 So there are MAX_RECOG_OPERANDS different time values for each
5098 We compute TIME1 as the time when the register for the prospective
5099 new reload ceases to be live, and TIME2 for each existing
5100 reload as the time when that the reload register of that reload
5102 Where there is little to be gained by exact lifetime calculations,
5103 we just make conservative assumptions, i.e. a longer lifetime;
5104 this is done in the 'default:' cases. */
5107 case RELOAD_FOR_OTHER_ADDRESS:
5108 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */
5109 time1 = copy ? 0 : 1;
5112 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5;
5114 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS,
5115 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 ,
5116 respectively, to the time values for these, we get distinct time
5117 values. To get distinct time values for each operand, we have to
5118 multiply opnum by at least three. We round that up to four because
5119 multiply by four is often cheaper. */
5120 case RELOAD_FOR_INPADDR_ADDRESS:
5121 time1 = opnum * 4 + 2;
5123 case RELOAD_FOR_INPUT_ADDRESS:
5124 time1 = opnum * 4 + 3;
5126 case RELOAD_FOR_INPUT:
5127 /* All RELOAD_FOR_INPUT reloads remain live till the instruction
5128 executes (inclusive). */
5129 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3;
5131 case RELOAD_FOR_OPADDR_ADDR:
5133 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */
5134 time1 = MAX_RECOG_OPERANDS * 4 + 1;
5136 case RELOAD_FOR_OPERAND_ADDRESS:
5137 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn
5139 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3;
5141 case RELOAD_FOR_OUTADDR_ADDRESS:
5142 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum;
5144 case RELOAD_FOR_OUTPUT_ADDRESS:
5145 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum;
5148 time1 = MAX_RECOG_OPERANDS * 5 + 5;
5151 for (i = 0; i < n_reloads; i++)
5153 rtx reg = rld[i].reg_rtx;
5154 if (reg && REG_P (reg)
5155 && ((unsigned) regno - true_regnum (reg)
5156 <= hard_regno_nregs[REGNO (reg)][GET_MODE (reg)] - (unsigned) 1)
5159 rtx other_input = rld[i].in;
5161 /* If the other reload loads the same input value, that
5162 will not cause a conflict only if it's loading it into
5163 the same register. */
5164 if (true_regnum (reg) != start_regno)
5165 other_input = NULL_RTX;
5166 if (! other_input || ! rtx_equal_p (other_input, value)
5167 || rld[i].out || out)
5170 switch (rld[i].when_needed)
5172 case RELOAD_FOR_OTHER_ADDRESS:
5175 case RELOAD_FOR_INPADDR_ADDRESS:
5176 /* find_reloads makes sure that a
5177 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used
5178 by at most one - the first -
5179 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the
5180 address reload is inherited, the address address reload
5181 goes away, so we can ignore this conflict. */
5182 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1
5183 && ignore_address_reloads
5184 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression.
5185 Then the address address is still needed to store
5186 back the new address. */
5187 && ! rld[reloadnum].out)
5189 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its
5190 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS
5192 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5193 && ignore_address_reloads
5194 /* Unless we are reloading an auto_inc expression. */
5195 && ! rld[reloadnum].out)
5197 time2 = rld[i].opnum * 4 + 2;
5199 case RELOAD_FOR_INPUT_ADDRESS:
5200 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum
5201 && ignore_address_reloads
5202 && ! rld[reloadnum].out)
5204 time2 = rld[i].opnum * 4 + 3;
5206 case RELOAD_FOR_INPUT:
5207 time2 = rld[i].opnum * 4 + 4;
5208 check_earlyclobber = 1;
5210 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4
5211 == MAX_RECOG_OPERAND * 4 */
5212 case RELOAD_FOR_OPADDR_ADDR:
5213 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1
5214 && ignore_address_reloads
5215 && ! rld[reloadnum].out)
5217 time2 = MAX_RECOG_OPERANDS * 4 + 1;
5219 case RELOAD_FOR_OPERAND_ADDRESS:
5220 time2 = MAX_RECOG_OPERANDS * 4 + 2;
5221 check_earlyclobber = 1;
5223 case RELOAD_FOR_INSN:
5224 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5226 case RELOAD_FOR_OUTPUT:
5227 /* All RELOAD_FOR_OUTPUT reloads become live just after the
5228 instruction is executed. */
5229 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5231 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with
5232 the RELOAD_FOR_OUTPUT reloads, so assign it the same time
5234 case RELOAD_FOR_OUTADDR_ADDRESS:
5235 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1
5236 && ignore_address_reloads
5237 && ! rld[reloadnum].out)
5239 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum;
5241 case RELOAD_FOR_OUTPUT_ADDRESS:
5242 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum;
5245 /* If there is no conflict in the input part, handle this
5246 like an output reload. */
5247 if (! rld[i].in || rtx_equal_p (other_input, value))
5249 time2 = MAX_RECOG_OPERANDS * 4 + 4;
5250 /* Earlyclobbered outputs must conflict with inputs. */
5251 if (earlyclobber_operand_p (rld[i].out))
5252 time2 = MAX_RECOG_OPERANDS * 4 + 3;
5257 /* RELOAD_OTHER might be live beyond instruction execution,
5258 but this is not obvious when we set time2 = 1. So check
5259 here if there might be a problem with the new reload
5260 clobbering the register used by the RELOAD_OTHER. */
5268 && (! rld[i].in || rld[i].out
5269 || ! rtx_equal_p (other_input, value)))
5270 || (out && rld[reloadnum].out_reg
5271 && time2 >= MAX_RECOG_OPERANDS * 4 + 3))
5277 /* Earlyclobbered outputs must conflict with inputs. */
5278 if (check_earlyclobber && out && earlyclobber_operand_p (out))
5284 /* Return 1 if the value in reload reg REGNO, as used by a reload
5285 needed for the part of the insn specified by OPNUM and TYPE,
5286 may be used to load VALUE into it.
5288 MODE is the mode in which the register is used, this is needed to
5289 determine how many hard regs to test.
5291 Other read-only reloads with the same value do not conflict
5292 unless OUT is nonzero and these other reloads have to live while
5293 output reloads live.
5294 If OUT is CONST0_RTX, this is a special case: it means that the
5295 test should not be for using register REGNO as reload register, but
5296 for copying from register REGNO into the reload register.
5298 RELOADNUM is the number of the reload we want to load this value for;
5299 a reload does not conflict with itself.
5301 When IGNORE_ADDRESS_RELOADS is set, we can not have conflicts with
5302 reloads that load an address for the very reload we are considering.
5304 The caller has to make sure that there is no conflict with the return
5308 free_for_value_p (int regno, enum machine_mode mode, int opnum,
5309 enum reload_type type, rtx value, rtx out, int reloadnum,
5310 int ignore_address_reloads)
5312 int nregs = hard_regno_nregs[regno][mode];
5314 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type,
5315 value, out, reloadnum,
5316 ignore_address_reloads))
5321 /* Return nonzero if the rtx X is invariant over the current function. */
5322 /* ??? Actually, the places where we use this expect exactly what is
5323 tested here, and not everything that is function invariant. In
5324 particular, the frame pointer and arg pointer are special cased;
5325 pic_offset_table_rtx is not, and we must not spill these things to
5329 function_invariant_p (const_rtx x)
5333 if (x == frame_pointer_rtx || x == arg_pointer_rtx)
5335 if (GET_CODE (x) == PLUS
5336 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx)
5337 && CONSTANT_P (XEXP (x, 1)))
5342 /* Determine whether the reload reg X overlaps any rtx'es used for
5343 overriding inheritance. Return nonzero if so. */
5346 conflicts_with_override (rtx x)
5349 for (i = 0; i < n_reloads; i++)
5350 if (reload_override_in[i]
5351 && reg_overlap_mentioned_p (x, reload_override_in[i]))
5356 /* Give an error message saying we failed to find a reload for INSN,
5357 and clear out reload R. */
5359 failed_reload (rtx insn, int r)
5361 if (asm_noperands (PATTERN (insn)) < 0)
5362 /* It's the compiler's fault. */
5363 fatal_insn ("could not find a spill register", insn);
5365 /* It's the user's fault; the operand's mode and constraint
5366 don't match. Disable this reload so we don't crash in final. */
5367 error_for_asm (insn,
5368 "%<asm%> operand constraint incompatible with operand size");
5372 rld[r].optional = 1;
5373 rld[r].secondary_p = 1;
5376 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate
5377 for reload R. If it's valid, get an rtx for it. Return nonzero if
5380 set_reload_reg (int i, int r)
5383 rtx reg = spill_reg_rtx[i];
5385 if (reg == 0 || GET_MODE (reg) != rld[r].mode)
5386 spill_reg_rtx[i] = reg
5387 = gen_rtx_REG (rld[r].mode, spill_regs[i]);
5389 regno = true_regnum (reg);
5391 /* Detect when the reload reg can't hold the reload mode.
5392 This used to be one `if', but Sequent compiler can't handle that. */
5393 if (HARD_REGNO_MODE_OK (regno, rld[r].mode))
5395 enum machine_mode test_mode = VOIDmode;
5397 test_mode = GET_MODE (rld[r].in);
5398 /* If rld[r].in has VOIDmode, it means we will load it
5399 in whatever mode the reload reg has: to wit, rld[r].mode.
5400 We have already tested that for validity. */
5401 /* Aside from that, we need to test that the expressions
5402 to reload from or into have modes which are valid for this
5403 reload register. Otherwise the reload insns would be invalid. */
5404 if (! (rld[r].in != 0 && test_mode != VOIDmode
5405 && ! HARD_REGNO_MODE_OK (regno, test_mode)))
5406 if (! (rld[r].out != 0
5407 && ! HARD_REGNO_MODE_OK (regno, GET_MODE (rld[r].out))))
5409 /* The reg is OK. */
5412 /* Mark as in use for this insn the reload regs we use
5414 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum,
5415 rld[r].when_needed, rld[r].mode);
5417 rld[r].reg_rtx = reg;
5418 reload_spill_index[r] = spill_regs[i];
5425 /* Find a spill register to use as a reload register for reload R.
5426 LAST_RELOAD is nonzero if this is the last reload for the insn being
5429 Set rld[R].reg_rtx to the register allocated.
5431 We return 1 if successful, or 0 if we couldn't find a spill reg and
5432 we didn't change anything. */
5435 allocate_reload_reg (struct insn_chain *chain ATTRIBUTE_UNUSED, int r,
5440 /* If we put this reload ahead, thinking it is a group,
5441 then insist on finding a group. Otherwise we can grab a
5442 reg that some other reload needs.
5443 (That can happen when we have a 68000 DATA_OR_FP_REG
5444 which is a group of data regs or one fp reg.)
5445 We need not be so restrictive if there are no more reloads
5448 ??? Really it would be nicer to have smarter handling
5449 for that kind of reg class, where a problem like this is normal.
5450 Perhaps those classes should be avoided for reloading
5451 by use of more alternatives. */
5453 int force_group = rld[r].nregs > 1 && ! last_reload;
5455 /* If we want a single register and haven't yet found one,
5456 take any reg in the right class and not in use.
5457 If we want a consecutive group, here is where we look for it.
5459 We use two passes so we can first look for reload regs to
5460 reuse, which are already in use for other reloads in this insn,
5461 and only then use additional registers.
5462 I think that maximizing reuse is needed to make sure we don't
5463 run out of reload regs. Suppose we have three reloads, and
5464 reloads A and B can share regs. These need two regs.
5465 Suppose A and B are given different regs.
5466 That leaves none for C. */
5467 for (pass = 0; pass < 2; pass++)
5469 /* I is the index in spill_regs.
5470 We advance it round-robin between insns to use all spill regs
5471 equally, so that inherited reloads have a chance
5472 of leapfrogging each other. */
5476 for (count = 0; count < n_spills; count++)
5478 int class = (int) rld[r].class;
5484 regnum = spill_regs[i];
5486 if ((reload_reg_free_p (regnum, rld[r].opnum,
5489 /* We check reload_reg_used to make sure we
5490 don't clobber the return register. */
5491 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum)
5492 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum,
5493 rld[r].when_needed, rld[r].in,
5495 && TEST_HARD_REG_BIT (reg_class_contents[class], regnum)
5496 && HARD_REGNO_MODE_OK (regnum, rld[r].mode)
5497 /* Look first for regs to share, then for unshared. But
5498 don't share regs used for inherited reloads; they are
5499 the ones we want to preserve. */
5501 || (TEST_HARD_REG_BIT (reload_reg_used_at_all,
5503 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit,
5506 int nr = hard_regno_nregs[regnum][rld[r].mode];
5507 /* Avoid the problem where spilling a GENERAL_OR_FP_REG
5508 (on 68000) got us two FP regs. If NR is 1,
5509 we would reject both of them. */
5512 /* If we need only one reg, we have already won. */
5515 /* But reject a single reg if we demand a group. */
5520 /* Otherwise check that as many consecutive regs as we need
5521 are available here. */
5524 int regno = regnum + nr - 1;
5525 if (!(TEST_HARD_REG_BIT (reg_class_contents[class], regno)
5526 && spill_reg_order[regno] >= 0
5527 && reload_reg_free_p (regno, rld[r].opnum,
5528 rld[r].when_needed)))
5537 /* If we found something on pass 1, omit pass 2. */
5538 if (count < n_spills)
5542 /* We should have found a spill register by now. */
5543 if (count >= n_spills)
5546 /* I is the index in SPILL_REG_RTX of the reload register we are to
5547 allocate. Get an rtx for it and find its register number. */
5549 return set_reload_reg (i, r);
5552 /* Initialize all the tables needed to allocate reload registers.
5553 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX
5554 is the array we use to restore the reg_rtx field for every reload. */
5557 choose_reload_regs_init (struct insn_chain *chain, rtx *save_reload_reg_rtx)
5561 for (i = 0; i < n_reloads; i++)
5562 rld[i].reg_rtx = save_reload_reg_rtx[i];
5564 memset (reload_inherited, 0, MAX_RELOADS);
5565 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx));
5566 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx));
5568 CLEAR_HARD_REG_SET (reload_reg_used);
5569 CLEAR_HARD_REG_SET (reload_reg_used_at_all);
5570 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr);
5571 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload);
5572 CLEAR_HARD_REG_SET (reload_reg_used_in_insn);
5573 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr);
5575 CLEAR_HARD_REG_SET (reg_used_in_insn);
5578 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout);
5579 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5580 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set);
5581 IOR_HARD_REG_SET (reg_used_in_insn, tmp);
5582 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout);
5583 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set);
5586 for (i = 0; i < reload_n_operands; i++)
5588 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]);
5589 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]);
5590 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]);
5591 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]);
5592 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]);
5593 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]);
5596 COMPL_HARD_REG_SET (reload_reg_unavailable, chain->used_spill_regs);
5598 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit);
5600 for (i = 0; i < n_reloads; i++)
5601 /* If we have already decided to use a certain register,
5602 don't use it in another way. */
5604 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum,
5605 rld[i].when_needed, rld[i].mode);
5608 /* Assign hard reg targets for the pseudo-registers we must reload
5609 into hard regs for this insn.
5610 Also output the instructions to copy them in and out of the hard regs.
5612 For machines with register classes, we are responsible for
5613 finding a reload reg in the proper class. */
5616 choose_reload_regs (struct insn_chain *chain)
5618 rtx insn = chain->insn;
5620 unsigned int max_group_size = 1;
5621 enum reg_class group_class = NO_REGS;
5622 int pass, win, inheritance;
5624 rtx save_reload_reg_rtx[MAX_RELOADS];
5626 /* In order to be certain of getting the registers we need,
5627 we must sort the reloads into order of increasing register class.
5628 Then our grabbing of reload registers will parallel the process
5629 that provided the reload registers.
5631 Also note whether any of the reloads wants a consecutive group of regs.
5632 If so, record the maximum size of the group desired and what
5633 register class contains all the groups needed by this insn. */
5635 for (j = 0; j < n_reloads; j++)
5637 reload_order[j] = j;
5638 if (rld[j].reg_rtx != NULL_RTX)
5640 gcc_assert (REG_P (rld[j].reg_rtx)
5641 && HARD_REGISTER_P (rld[j].reg_rtx));
5642 reload_spill_index[j] = REGNO (rld[j].reg_rtx);
5645 reload_spill_index[j] = -1;
5647 if (rld[j].nregs > 1)
5649 max_group_size = MAX (rld[j].nregs, max_group_size);
5651 = reg_class_superunion[(int) rld[j].class][(int) group_class];
5654 save_reload_reg_rtx[j] = rld[j].reg_rtx;
5658 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower);
5660 /* If -O, try first with inheritance, then turning it off.
5661 If not -O, don't do inheritance.
5662 Using inheritance when not optimizing leads to paradoxes
5663 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves
5664 because one side of the comparison might be inherited. */
5666 for (inheritance = optimize > 0; inheritance >= 0; inheritance--)
5668 choose_reload_regs_init (chain, save_reload_reg_rtx);
5670 /* Process the reloads in order of preference just found.
5671 Beyond this point, subregs can be found in reload_reg_rtx.
5673 This used to look for an existing reloaded home for all of the
5674 reloads, and only then perform any new reloads. But that could lose
5675 if the reloads were done out of reg-class order because a later
5676 reload with a looser constraint might have an old home in a register
5677 needed by an earlier reload with a tighter constraint.
5679 To solve this, we make two passes over the reloads, in the order
5680 described above. In the first pass we try to inherit a reload
5681 from a previous insn. If there is a later reload that needs a
5682 class that is a proper subset of the class being processed, we must
5683 also allocate a spill register during the first pass.
5685 Then make a second pass over the reloads to allocate any reloads
5686 that haven't been given registers yet. */
5688 for (j = 0; j < n_reloads; j++)
5690 int r = reload_order[j];
5691 rtx search_equiv = NULL_RTX;
5693 /* Ignore reloads that got marked inoperative. */
5694 if (rld[r].out == 0 && rld[r].in == 0
5695 && ! rld[r].secondary_p)
5698 /* If find_reloads chose to use reload_in or reload_out as a reload
5699 register, we don't need to chose one. Otherwise, try even if it
5700 found one since we might save an insn if we find the value lying
5702 Try also when reload_in is a pseudo without a hard reg. */
5703 if (rld[r].in != 0 && rld[r].reg_rtx != 0
5704 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx)
5705 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx)
5706 && !MEM_P (rld[r].in)
5707 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER)))
5710 #if 0 /* No longer needed for correct operation.
5711 It might give better code, or might not; worth an experiment? */
5712 /* If this is an optional reload, we can't inherit from earlier insns
5713 until we are sure that any non-optional reloads have been allocated.
5714 The following code takes advantage of the fact that optional reloads
5715 are at the end of reload_order. */
5716 if (rld[r].optional != 0)
5717 for (i = 0; i < j; i++)
5718 if ((rld[reload_order[i]].out != 0
5719 || rld[reload_order[i]].in != 0
5720 || rld[reload_order[i]].secondary_p)
5721 && ! rld[reload_order[i]].optional
5722 && rld[reload_order[i]].reg_rtx == 0)
5723 allocate_reload_reg (chain, reload_order[i], 0);
5726 /* First see if this pseudo is already available as reloaded
5727 for a previous insn. We cannot try to inherit for reloads
5728 that are smaller than the maximum number of registers needed
5729 for groups unless the register we would allocate cannot be used
5732 We could check here to see if this is a secondary reload for
5733 an object that is already in a register of the desired class.
5734 This would avoid the need for the secondary reload register.
5735 But this is complex because we can't easily determine what
5736 objects might want to be loaded via this reload. So let a
5737 register be allocated here. In `emit_reload_insns' we suppress
5738 one of the loads in the case described above. */
5744 enum machine_mode mode = VOIDmode;
5748 else if (REG_P (rld[r].in))
5750 regno = REGNO (rld[r].in);
5751 mode = GET_MODE (rld[r].in);
5753 else if (REG_P (rld[r].in_reg))
5755 regno = REGNO (rld[r].in_reg);
5756 mode = GET_MODE (rld[r].in_reg);
5758 else if (GET_CODE (rld[r].in_reg) == SUBREG
5759 && REG_P (SUBREG_REG (rld[r].in_reg)))
5761 regno = REGNO (SUBREG_REG (rld[r].in_reg));
5762 if (regno < FIRST_PSEUDO_REGISTER)
5763 regno = subreg_regno (rld[r].in_reg);
5765 byte = SUBREG_BYTE (rld[r].in_reg);
5766 mode = GET_MODE (rld[r].in_reg);
5769 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC
5770 && REG_P (XEXP (rld[r].in_reg, 0)))
5772 regno = REGNO (XEXP (rld[r].in_reg, 0));
5773 mode = GET_MODE (XEXP (rld[r].in_reg, 0));
5774 rld[r].out = rld[r].in;
5778 /* This won't work, since REGNO can be a pseudo reg number.
5779 Also, it takes much more hair to keep track of all the things
5780 that can invalidate an inherited reload of part of a pseudoreg. */
5781 else if (GET_CODE (rld[r].in) == SUBREG
5782 && REG_P (SUBREG_REG (rld[r].in)))
5783 regno = subreg_regno (rld[r].in);
5787 && reg_last_reload_reg[regno] != 0
5788 #ifdef CANNOT_CHANGE_MODE_CLASS
5789 /* Verify that the register it's in can be used in
5791 && !REG_CANNOT_CHANGE_MODE_P (REGNO (reg_last_reload_reg[regno]),
5792 GET_MODE (reg_last_reload_reg[regno]),
5797 enum reg_class class = rld[r].class, last_class;
5798 rtx last_reg = reg_last_reload_reg[regno];
5799 enum machine_mode need_mode;
5801 i = REGNO (last_reg);
5802 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode);
5803 last_class = REGNO_REG_CLASS (i);
5809 = smallest_mode_for_size (GET_MODE_BITSIZE (mode)
5810 + byte * BITS_PER_UNIT,
5811 GET_MODE_CLASS (mode));
5813 if ((GET_MODE_SIZE (GET_MODE (last_reg))
5814 >= GET_MODE_SIZE (need_mode))
5815 && reg_reloaded_contents[i] == regno
5816 && TEST_HARD_REG_BIT (reg_reloaded_valid, i)
5817 && HARD_REGNO_MODE_OK (i, rld[r].mode)
5818 && (TEST_HARD_REG_BIT (reg_class_contents[(int) class], i)
5819 /* Even if we can't use this register as a reload
5820 register, we might use it for reload_override_in,
5821 if copying it to the desired class is cheap
5823 || ((REGISTER_MOVE_COST (mode, last_class, class)
5824 < MEMORY_MOVE_COST (mode, class, 1))
5825 && (secondary_reload_class (1, class, mode,
5828 #ifdef SECONDARY_MEMORY_NEEDED
5829 && ! SECONDARY_MEMORY_NEEDED (last_class, class,
5834 && (rld[r].nregs == max_group_size
5835 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class],
5837 && free_for_value_p (i, rld[r].mode, rld[r].opnum,
5838 rld[r].when_needed, rld[r].in,
5841 /* If a group is needed, verify that all the subsequent
5842 registers still have their values intact. */
5843 int nr = hard_regno_nregs[i][rld[r].mode];
5846 for (k = 1; k < nr; k++)
5847 if (reg_reloaded_contents[i + k] != regno
5848 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k))
5856 last_reg = (GET_MODE (last_reg) == mode
5857 ? last_reg : gen_rtx_REG (mode, i));
5860 for (k = 0; k < nr; k++)
5861 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
5864 /* We found a register that contains the
5865 value we need. If this register is the
5866 same as an `earlyclobber' operand of the
5867 current insn, just mark it as a place to
5868 reload from since we can't use it as the
5869 reload register itself. */
5871 for (i1 = 0; i1 < n_earlyclobbers; i1++)
5872 if (reg_overlap_mentioned_for_reload_p
5873 (reg_last_reload_reg[regno],
5874 reload_earlyclobbers[i1]))
5877 if (i1 != n_earlyclobbers
5878 || ! (free_for_value_p (i, rld[r].mode,
5880 rld[r].when_needed, rld[r].in,
5882 /* Don't use it if we'd clobber a pseudo reg. */
5883 || (TEST_HARD_REG_BIT (reg_used_in_insn, i)
5885 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i))
5886 /* Don't clobber the frame pointer. */
5887 || (i == HARD_FRAME_POINTER_REGNUM
5888 && frame_pointer_needed
5890 /* Don't really use the inherited spill reg
5891 if we need it wider than we've got it. */
5892 || (GET_MODE_SIZE (rld[r].mode)
5893 > GET_MODE_SIZE (mode))
5896 /* If find_reloads chose reload_out as reload
5897 register, stay with it - that leaves the
5898 inherited register for subsequent reloads. */
5899 || (rld[r].out && rld[r].reg_rtx
5900 && rtx_equal_p (rld[r].out, rld[r].reg_rtx)))
5902 if (! rld[r].optional)
5904 reload_override_in[r] = last_reg;
5905 reload_inheritance_insn[r]
5906 = reg_reloaded_insn[i];
5912 /* We can use this as a reload reg. */
5913 /* Mark the register as in use for this part of
5915 mark_reload_reg_in_use (i,
5919 rld[r].reg_rtx = last_reg;
5920 reload_inherited[r] = 1;
5921 reload_inheritance_insn[r]
5922 = reg_reloaded_insn[i];
5923 reload_spill_index[r] = i;
5924 for (k = 0; k < nr; k++)
5925 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
5933 /* Here's another way to see if the value is already lying around. */
5936 && ! reload_inherited[r]
5938 && (CONSTANT_P (rld[r].in)
5939 || GET_CODE (rld[r].in) == PLUS
5940 || REG_P (rld[r].in)
5941 || MEM_P (rld[r].in))
5942 && (rld[r].nregs == max_group_size
5943 || ! reg_classes_intersect_p (rld[r].class, group_class)))
5944 search_equiv = rld[r].in;
5945 /* If this is an output reload from a simple move insn, look
5946 if an equivalence for the input is available. */
5947 else if (inheritance && rld[r].in == 0 && rld[r].out != 0)
5949 rtx set = single_set (insn);
5952 && rtx_equal_p (rld[r].out, SET_DEST (set))
5953 && CONSTANT_P (SET_SRC (set)))
5954 search_equiv = SET_SRC (set);
5960 = find_equiv_reg (search_equiv, insn, rld[r].class,
5961 -1, NULL, 0, rld[r].mode);
5967 regno = REGNO (equiv);
5970 /* This must be a SUBREG of a hard register.
5971 Make a new REG since this might be used in an
5972 address and not all machines support SUBREGs
5974 gcc_assert (GET_CODE (equiv) == SUBREG);
5975 regno = subreg_regno (equiv);
5976 equiv = gen_rtx_REG (rld[r].mode, regno);
5977 /* If we choose EQUIV as the reload register, but the
5978 loop below decides to cancel the inheritance, we'll
5979 end up reloading EQUIV in rld[r].mode, not the mode
5980 it had originally. That isn't safe when EQUIV isn't
5981 available as a spill register since its value might
5982 still be live at this point. */
5983 for (i = regno; i < regno + (int) rld[r].nregs; i++)
5984 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i))
5989 /* If we found a spill reg, reject it unless it is free
5990 and of the desired class. */
5994 int bad_for_class = 0;
5995 int max_regno = regno + rld[r].nregs;
5997 for (i = regno; i < max_regno; i++)
5999 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all,
6001 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].class],
6006 && ! free_for_value_p (regno, rld[r].mode,
6007 rld[r].opnum, rld[r].when_needed,
6008 rld[r].in, rld[r].out, r, 1))
6013 if (equiv != 0 && ! HARD_REGNO_MODE_OK (regno, rld[r].mode))
6016 /* We found a register that contains the value we need.
6017 If this register is the same as an `earlyclobber' operand
6018 of the current insn, just mark it as a place to reload from
6019 since we can't use it as the reload register itself. */
6022 for (i = 0; i < n_earlyclobbers; i++)
6023 if (reg_overlap_mentioned_for_reload_p (equiv,
6024 reload_earlyclobbers[i]))
6026 if (! rld[r].optional)
6027 reload_override_in[r] = equiv;
6032 /* If the equiv register we have found is explicitly clobbered
6033 in the current insn, it depends on the reload type if we
6034 can use it, use it for reload_override_in, or not at all.
6035 In particular, we then can't use EQUIV for a
6036 RELOAD_FOR_OUTPUT_ADDRESS reload. */
6040 if (regno_clobbered_p (regno, insn, rld[r].mode, 2))
6041 switch (rld[r].when_needed)
6043 case RELOAD_FOR_OTHER_ADDRESS:
6044 case RELOAD_FOR_INPADDR_ADDRESS:
6045 case RELOAD_FOR_INPUT_ADDRESS:
6046 case RELOAD_FOR_OPADDR_ADDR:
6049 case RELOAD_FOR_INPUT:
6050 case RELOAD_FOR_OPERAND_ADDRESS:
6051 if (! rld[r].optional)
6052 reload_override_in[r] = equiv;
6058 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1))
6059 switch (rld[r].when_needed)
6061 case RELOAD_FOR_OTHER_ADDRESS:
6062 case RELOAD_FOR_INPADDR_ADDRESS:
6063 case RELOAD_FOR_INPUT_ADDRESS:
6064 case RELOAD_FOR_OPADDR_ADDR:
6065 case RELOAD_FOR_OPERAND_ADDRESS:
6066 case RELOAD_FOR_INPUT:
6069 if (! rld[r].optional)
6070 reload_override_in[r] = equiv;
6078 /* If we found an equivalent reg, say no code need be generated
6079 to load it, and use it as our reload reg. */
6081 && (regno != HARD_FRAME_POINTER_REGNUM
6082 || !frame_pointer_needed))
6084 int nr = hard_regno_nregs[regno][rld[r].mode];
6086 rld[r].reg_rtx = equiv;
6087 reload_inherited[r] = 1;
6089 /* If reg_reloaded_valid is not set for this register,
6090 there might be a stale spill_reg_store lying around.
6091 We must clear it, since otherwise emit_reload_insns
6092 might delete the store. */
6093 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno))
6094 spill_reg_store[regno] = NULL_RTX;
6095 /* If any of the hard registers in EQUIV are spill
6096 registers, mark them as in use for this insn. */
6097 for (k = 0; k < nr; k++)
6099 i = spill_reg_order[regno + k];
6102 mark_reload_reg_in_use (regno, rld[r].opnum,
6105 SET_HARD_REG_BIT (reload_reg_used_for_inherit,
6112 /* If we found a register to use already, or if this is an optional
6113 reload, we are done. */
6114 if (rld[r].reg_rtx != 0 || rld[r].optional != 0)
6118 /* No longer needed for correct operation. Might or might
6119 not give better code on the average. Want to experiment? */
6121 /* See if there is a later reload that has a class different from our
6122 class that intersects our class or that requires less register
6123 than our reload. If so, we must allocate a register to this
6124 reload now, since that reload might inherit a previous reload
6125 and take the only available register in our class. Don't do this
6126 for optional reloads since they will force all previous reloads
6127 to be allocated. Also don't do this for reloads that have been
6130 for (i = j + 1; i < n_reloads; i++)
6132 int s = reload_order[i];
6134 if ((rld[s].in == 0 && rld[s].out == 0
6135 && ! rld[s].secondary_p)
6139 if ((rld[s].class != rld[r].class
6140 && reg_classes_intersect_p (rld[r].class,
6142 || rld[s].nregs < rld[r].nregs)
6149 allocate_reload_reg (chain, r, j == n_reloads - 1);
6153 /* Now allocate reload registers for anything non-optional that
6154 didn't get one yet. */
6155 for (j = 0; j < n_reloads; j++)
6157 int r = reload_order[j];
6159 /* Ignore reloads that got marked inoperative. */
6160 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p)
6163 /* Skip reloads that already have a register allocated or are
6165 if (rld[r].reg_rtx != 0 || rld[r].optional)
6168 if (! allocate_reload_reg (chain, r, j == n_reloads - 1))
6172 /* If that loop got all the way, we have won. */
6179 /* Loop around and try without any inheritance. */
6184 /* First undo everything done by the failed attempt
6185 to allocate with inheritance. */
6186 choose_reload_regs_init (chain, save_reload_reg_rtx);
6188 /* Some sanity tests to verify that the reloads found in the first
6189 pass are identical to the ones we have now. */
6190 gcc_assert (chain->n_reloads == n_reloads);
6192 for (i = 0; i < n_reloads; i++)
6194 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0)
6196 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed);
6197 for (j = 0; j < n_spills; j++)
6198 if (spill_regs[j] == chain->rld[i].regno)
6199 if (! set_reload_reg (j, i))
6200 failed_reload (chain->insn, i);
6204 /* If we thought we could inherit a reload, because it seemed that
6205 nothing else wanted the same reload register earlier in the insn,
6206 verify that assumption, now that all reloads have been assigned.
6207 Likewise for reloads where reload_override_in has been set. */
6209 /* If doing expensive optimizations, do one preliminary pass that doesn't
6210 cancel any inheritance, but removes reloads that have been needed only
6211 for reloads that we know can be inherited. */
6212 for (pass = flag_expensive_optimizations; pass >= 0; pass--)
6214 for (j = 0; j < n_reloads; j++)
6216 int r = reload_order[j];
6218 if (reload_inherited[r] && rld[r].reg_rtx)
6219 check_reg = rld[r].reg_rtx;
6220 else if (reload_override_in[r]
6221 && (REG_P (reload_override_in[r])
6222 || GET_CODE (reload_override_in[r]) == SUBREG))
6223 check_reg = reload_override_in[r];
6226 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode,
6227 rld[r].opnum, rld[r].when_needed, rld[r].in,
6228 (reload_inherited[r]
6229 ? rld[r].out : const0_rtx),
6234 reload_inherited[r] = 0;
6235 reload_override_in[r] = 0;
6237 /* If we can inherit a RELOAD_FOR_INPUT, or can use a
6238 reload_override_in, then we do not need its related
6239 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads;
6240 likewise for other reload types.
6241 We handle this by removing a reload when its only replacement
6242 is mentioned in reload_in of the reload we are going to inherit.
6243 A special case are auto_inc expressions; even if the input is
6244 inherited, we still need the address for the output. We can
6245 recognize them because they have RELOAD_OUT set to RELOAD_IN.
6246 If we succeeded removing some reload and we are doing a preliminary
6247 pass just to remove such reloads, make another pass, since the
6248 removal of one reload might allow us to inherit another one. */
6250 && rld[r].out != rld[r].in
6251 && remove_address_replacements (rld[r].in) && pass)
6256 /* Now that reload_override_in is known valid,
6257 actually override reload_in. */
6258 for (j = 0; j < n_reloads; j++)
6259 if (reload_override_in[j])
6260 rld[j].in = reload_override_in[j];
6262 /* If this reload won't be done because it has been canceled or is
6263 optional and not inherited, clear reload_reg_rtx so other
6264 routines (such as subst_reloads) don't get confused. */
6265 for (j = 0; j < n_reloads; j++)
6266 if (rld[j].reg_rtx != 0
6267 && ((rld[j].optional && ! reload_inherited[j])
6268 || (rld[j].in == 0 && rld[j].out == 0
6269 && ! rld[j].secondary_p)))
6271 int regno = true_regnum (rld[j].reg_rtx);
6273 if (spill_reg_order[regno] >= 0)
6274 clear_reload_reg_in_use (regno, rld[j].opnum,
6275 rld[j].when_needed, rld[j].mode);
6277 reload_spill_index[j] = -1;
6280 /* Record which pseudos and which spill regs have output reloads. */
6281 for (j = 0; j < n_reloads; j++)
6283 int r = reload_order[j];
6285 i = reload_spill_index[r];
6287 /* I is nonneg if this reload uses a register.
6288 If rld[r].reg_rtx is 0, this is an optional reload
6289 that we opted to ignore. */
6290 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg)
6291 && rld[r].reg_rtx != 0)
6293 int nregno = REGNO (rld[r].out_reg);
6296 if (nregno < FIRST_PSEUDO_REGISTER)
6297 nr = hard_regno_nregs[nregno][rld[r].mode];
6300 SET_REGNO_REG_SET (®_has_output_reload,
6305 nr = hard_regno_nregs[i][rld[r].mode];
6307 SET_HARD_REG_BIT (reg_is_output_reload, i + nr);
6310 gcc_assert (rld[r].when_needed == RELOAD_OTHER
6311 || rld[r].when_needed == RELOAD_FOR_OUTPUT
6312 || rld[r].when_needed == RELOAD_FOR_INSN);
6317 /* Deallocate the reload register for reload R. This is called from
6318 remove_address_replacements. */
6321 deallocate_reload_reg (int r)
6325 if (! rld[r].reg_rtx)
6327 regno = true_regnum (rld[r].reg_rtx);
6329 if (spill_reg_order[regno] >= 0)
6330 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed,
6332 reload_spill_index[r] = -1;
6335 /* If SMALL_REGISTER_CLASSES is nonzero, we may not have merged two
6336 reloads of the same item for fear that we might not have enough reload
6337 registers. However, normally they will get the same reload register
6338 and hence actually need not be loaded twice.
6340 Here we check for the most common case of this phenomenon: when we have
6341 a number of reloads for the same object, each of which were allocated
6342 the same reload_reg_rtx, that reload_reg_rtx is not used for any other
6343 reload, and is not modified in the insn itself. If we find such,
6344 merge all the reloads and set the resulting reload to RELOAD_OTHER.
6345 This will not increase the number of spill registers needed and will
6346 prevent redundant code. */
6349 merge_assigned_reloads (rtx insn)
6353 /* Scan all the reloads looking for ones that only load values and
6354 are not already RELOAD_OTHER and ones whose reload_reg_rtx are
6355 assigned and not modified by INSN. */
6357 for (i = 0; i < n_reloads; i++)
6359 int conflicting_input = 0;
6360 int max_input_address_opnum = -1;
6361 int min_conflicting_input_opnum = MAX_RECOG_OPERANDS;
6363 if (rld[i].in == 0 || rld[i].when_needed == RELOAD_OTHER
6364 || rld[i].out != 0 || rld[i].reg_rtx == 0
6365 || reg_set_p (rld[i].reg_rtx, insn))
6368 /* Look at all other reloads. Ensure that the only use of this
6369 reload_reg_rtx is in a reload that just loads the same value
6370 as we do. Note that any secondary reloads must be of the identical
6371 class since the values, modes, and result registers are the
6372 same, so we need not do anything with any secondary reloads. */
6374 for (j = 0; j < n_reloads; j++)
6376 if (i == j || rld[j].reg_rtx == 0
6377 || ! reg_overlap_mentioned_p (rld[j].reg_rtx,
6381 if (rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6382 && rld[j].opnum > max_input_address_opnum)
6383 max_input_address_opnum = rld[j].opnum;
6385 /* If the reload regs aren't exactly the same (e.g, different modes)
6386 or if the values are different, we can't merge this reload.
6387 But if it is an input reload, we might still merge
6388 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_OTHER_ADDRESS reloads. */
6390 if (! rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6391 || rld[j].out != 0 || rld[j].in == 0
6392 || ! rtx_equal_p (rld[i].in, rld[j].in))
6394 if (rld[j].when_needed != RELOAD_FOR_INPUT
6395 || ((rld[i].when_needed != RELOAD_FOR_INPUT_ADDRESS
6396 || rld[i].opnum > rld[j].opnum)
6397 && rld[i].when_needed != RELOAD_FOR_OTHER_ADDRESS))
6399 conflicting_input = 1;
6400 if (min_conflicting_input_opnum > rld[j].opnum)
6401 min_conflicting_input_opnum = rld[j].opnum;
6405 /* If all is OK, merge the reloads. Only set this to RELOAD_OTHER if
6406 we, in fact, found any matching reloads. */
6409 && max_input_address_opnum <= min_conflicting_input_opnum)
6411 gcc_assert (rld[i].when_needed != RELOAD_FOR_OUTPUT);
6413 for (j = 0; j < n_reloads; j++)
6414 if (i != j && rld[j].reg_rtx != 0
6415 && rtx_equal_p (rld[i].reg_rtx, rld[j].reg_rtx)
6416 && (! conflicting_input
6417 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6418 || rld[j].when_needed == RELOAD_FOR_OTHER_ADDRESS))
6420 rld[i].when_needed = RELOAD_OTHER;
6422 reload_spill_index[j] = -1;
6423 transfer_replacements (i, j);
6426 /* If this is now RELOAD_OTHER, look for any reloads that
6427 load parts of this operand and set them to
6428 RELOAD_FOR_OTHER_ADDRESS if they were for inputs,
6429 RELOAD_OTHER for outputs. Note that this test is
6430 equivalent to looking for reloads for this operand
6433 We must take special care with RELOAD_FOR_OUTPUT_ADDRESS;
6434 it may share registers with a RELOAD_FOR_INPUT, so we can
6435 not change it to RELOAD_FOR_OTHER_ADDRESS. We should
6436 never need to, since we do not modify RELOAD_FOR_OUTPUT.
6438 It is possible that the RELOAD_FOR_OPERAND_ADDRESS
6439 instruction is assigned the same register as the earlier
6440 RELOAD_FOR_OTHER_ADDRESS instruction. Merging these two
6441 instructions will cause the RELOAD_FOR_OTHER_ADDRESS
6442 instruction to be deleted later on. */
6444 if (rld[i].when_needed == RELOAD_OTHER)
6445 for (j = 0; j < n_reloads; j++)
6447 && rld[j].when_needed != RELOAD_OTHER
6448 && rld[j].when_needed != RELOAD_FOR_OTHER_ADDRESS
6449 && rld[j].when_needed != RELOAD_FOR_OUTPUT_ADDRESS
6450 && rld[j].when_needed != RELOAD_FOR_OPERAND_ADDRESS
6451 && (! conflicting_input
6452 || rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6453 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6454 && reg_overlap_mentioned_for_reload_p (rld[j].in,
6460 = ((rld[j].when_needed == RELOAD_FOR_INPUT_ADDRESS
6461 || rld[j].when_needed == RELOAD_FOR_INPADDR_ADDRESS)
6462 ? RELOAD_FOR_OTHER_ADDRESS : RELOAD_OTHER);
6464 /* Check to see if we accidentally converted two
6465 reloads that use the same reload register with
6466 different inputs to the same type. If so, the
6467 resulting code won't work. */
6469 for (k = 0; k < j; k++)
6470 gcc_assert (rld[k].in == 0 || rld[k].reg_rtx == 0
6471 || rld[k].when_needed != rld[j].when_needed
6472 || !rtx_equal_p (rld[k].reg_rtx,
6474 || rtx_equal_p (rld[k].in,
6481 /* These arrays are filled by emit_reload_insns and its subroutines. */
6482 static rtx input_reload_insns[MAX_RECOG_OPERANDS];
6483 static rtx other_input_address_reload_insns = 0;
6484 static rtx other_input_reload_insns = 0;
6485 static rtx input_address_reload_insns[MAX_RECOG_OPERANDS];
6486 static rtx inpaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6487 static rtx output_reload_insns[MAX_RECOG_OPERANDS];
6488 static rtx output_address_reload_insns[MAX_RECOG_OPERANDS];
6489 static rtx outaddr_address_reload_insns[MAX_RECOG_OPERANDS];
6490 static rtx operand_reload_insns = 0;
6491 static rtx other_operand_reload_insns = 0;
6492 static rtx other_output_reload_insns[MAX_RECOG_OPERANDS];
6494 /* Values to be put in spill_reg_store are put here first. */
6495 static rtx new_spill_reg_store[FIRST_PSEUDO_REGISTER];
6496 static HARD_REG_SET reg_reloaded_died;
6498 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register
6499 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg
6500 is nonzero, if that is suitable. On success, change *RELOAD_REG to the
6501 adjusted register, and return true. Otherwise, return false. */
6503 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg,
6504 enum reg_class new_class,
6505 enum machine_mode new_mode)
6510 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0)
6512 unsigned regno = REGNO (reg);
6514 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno))
6516 if (GET_MODE (reg) != new_mode)
6518 if (!HARD_REGNO_MODE_OK (regno, new_mode))
6520 if (hard_regno_nregs[regno][new_mode]
6521 > hard_regno_nregs[regno][GET_MODE (reg)])
6523 reg = reload_adjust_reg_for_mode (reg, new_mode);
6531 /* Check if *RELOAD_REG is suitable as a scratch register for the reload
6532 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is
6533 nonzero, if that is suitable. On success, change *RELOAD_REG to the
6534 adjusted register, and return true. Otherwise, return false. */
6536 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg,
6537 enum insn_code icode)
6540 enum reg_class new_class = scratch_reload_class (icode);
6541 enum machine_mode new_mode = insn_data[(int) icode].operand[2].mode;
6543 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg,
6544 new_class, new_mode);
6547 /* Generate insns to perform reload RL, which is for the insn in CHAIN and
6548 has the number J. OLD contains the value to be used as input. */
6551 emit_input_reload_insns (struct insn_chain *chain, struct reload *rl,
6554 rtx insn = chain->insn;
6555 rtx reloadreg = rl->reg_rtx;
6556 rtx oldequiv_reg = 0;
6559 enum machine_mode mode;
6562 /* Determine the mode to reload in.
6563 This is very tricky because we have three to choose from.
6564 There is the mode the insn operand wants (rl->inmode).
6565 There is the mode of the reload register RELOADREG.
6566 There is the intrinsic mode of the operand, which we could find
6567 by stripping some SUBREGs.
6568 It turns out that RELOADREG's mode is irrelevant:
6569 we can change that arbitrarily.
6571 Consider (SUBREG:SI foo:QI) as an operand that must be SImode;
6572 then the reload reg may not support QImode moves, so use SImode.
6573 If foo is in memory due to spilling a pseudo reg, this is safe,
6574 because the QImode value is in the least significant part of a
6575 slot big enough for a SImode. If foo is some other sort of
6576 memory reference, then it is impossible to reload this case,
6577 so previous passes had better make sure this never happens.
6579 Then consider a one-word union which has SImode and one of its
6580 members is a float, being fetched as (SUBREG:SF union:SI).
6581 We must fetch that as SFmode because we could be loading into
6582 a float-only register. In this case OLD's mode is correct.
6584 Consider an immediate integer: it has VOIDmode. Here we need
6585 to get a mode from something else.
6587 In some cases, there is a fourth mode, the operand's
6588 containing mode. If the insn specifies a containing mode for
6589 this operand, it overrides all others.
6591 I am not sure whether the algorithm here is always right,
6592 but it does the right things in those cases. */
6594 mode = GET_MODE (old);
6595 if (mode == VOIDmode)
6598 /* delete_output_reload is only invoked properly if old contains
6599 the original pseudo register. Since this is replaced with a
6600 hard reg when RELOAD_OVERRIDE_IN is set, see if we can
6601 find the pseudo in RELOAD_IN_REG. */
6602 if (reload_override_in[j]
6603 && REG_P (rl->in_reg))
6610 else if (REG_P (oldequiv))
6611 oldequiv_reg = oldequiv;
6612 else if (GET_CODE (oldequiv) == SUBREG)
6613 oldequiv_reg = SUBREG_REG (oldequiv);
6615 /* If we are reloading from a register that was recently stored in
6616 with an output-reload, see if we can prove there was
6617 actually no need to store the old value in it. */
6619 if (optimize && REG_P (oldequiv)
6620 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6621 && spill_reg_store[REGNO (oldequiv)]
6623 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)])
6624 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6626 delete_output_reload (insn, j, REGNO (oldequiv));
6628 /* Encapsulate both RELOADREG and OLDEQUIV into that mode,
6629 then load RELOADREG from OLDEQUIV. Note that we cannot use
6630 gen_lowpart_common since it can do the wrong thing when
6631 RELOADREG has a multi-word mode. Note that RELOADREG
6632 must always be a REG here. */
6634 if (GET_MODE (reloadreg) != mode)
6635 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
6636 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode)
6637 oldequiv = SUBREG_REG (oldequiv);
6638 if (GET_MODE (oldequiv) != VOIDmode
6639 && mode != GET_MODE (oldequiv))
6640 oldequiv = gen_lowpart_SUBREG (mode, oldequiv);
6642 /* Switch to the right place to emit the reload insns. */
6643 switch (rl->when_needed)
6646 where = &other_input_reload_insns;
6648 case RELOAD_FOR_INPUT:
6649 where = &input_reload_insns[rl->opnum];
6651 case RELOAD_FOR_INPUT_ADDRESS:
6652 where = &input_address_reload_insns[rl->opnum];
6654 case RELOAD_FOR_INPADDR_ADDRESS:
6655 where = &inpaddr_address_reload_insns[rl->opnum];
6657 case RELOAD_FOR_OUTPUT_ADDRESS:
6658 where = &output_address_reload_insns[rl->opnum];
6660 case RELOAD_FOR_OUTADDR_ADDRESS:
6661 where = &outaddr_address_reload_insns[rl->opnum];
6663 case RELOAD_FOR_OPERAND_ADDRESS:
6664 where = &operand_reload_insns;
6666 case RELOAD_FOR_OPADDR_ADDR:
6667 where = &other_operand_reload_insns;
6669 case RELOAD_FOR_OTHER_ADDRESS:
6670 where = &other_input_address_reload_insns;
6676 push_to_sequence (*where);
6678 /* Auto-increment addresses must be reloaded in a special way. */
6679 if (rl->out && ! rl->out_reg)
6681 /* We are not going to bother supporting the case where a
6682 incremented register can't be copied directly from
6683 OLDEQUIV since this seems highly unlikely. */
6684 gcc_assert (rl->secondary_in_reload < 0);
6686 if (reload_inherited[j])
6687 oldequiv = reloadreg;
6689 old = XEXP (rl->in_reg, 0);
6691 if (optimize && REG_P (oldequiv)
6692 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER
6693 && spill_reg_store[REGNO (oldequiv)]
6695 && (dead_or_set_p (insn,
6696 spill_reg_stored_to[REGNO (oldequiv)])
6697 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)],
6699 delete_output_reload (insn, j, REGNO (oldequiv));
6701 /* Prevent normal processing of this reload. */
6703 /* Output a special code sequence for this case. */
6704 new_spill_reg_store[REGNO (reloadreg)]
6705 = inc_for_reload (reloadreg, oldequiv, rl->out,
6709 /* If we are reloading a pseudo-register that was set by the previous
6710 insn, see if we can get rid of that pseudo-register entirely
6711 by redirecting the previous insn into our reload register. */
6713 else if (optimize && REG_P (old)
6714 && REGNO (old) >= FIRST_PSEUDO_REGISTER
6715 && dead_or_set_p (insn, old)
6716 /* This is unsafe if some other reload
6717 uses the same reg first. */
6718 && ! conflicts_with_override (reloadreg)
6719 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum,
6720 rl->when_needed, old, rl->out, j, 0))
6722 rtx temp = PREV_INSN (insn);
6723 while (temp && NOTE_P (temp))
6724 temp = PREV_INSN (temp);
6726 && NONJUMP_INSN_P (temp)
6727 && GET_CODE (PATTERN (temp)) == SET
6728 && SET_DEST (PATTERN (temp)) == old
6729 /* Make sure we can access insn_operand_constraint. */
6730 && asm_noperands (PATTERN (temp)) < 0
6731 /* This is unsafe if operand occurs more than once in current
6732 insn. Perhaps some occurrences aren't reloaded. */
6733 && count_occurrences (PATTERN (insn), old, 0) == 1)
6735 rtx old = SET_DEST (PATTERN (temp));
6736 /* Store into the reload register instead of the pseudo. */
6737 SET_DEST (PATTERN (temp)) = reloadreg;
6739 /* Verify that resulting insn is valid. */
6740 extract_insn (temp);
6741 if (constrain_operands (1))
6743 /* If the previous insn is an output reload, the source is
6744 a reload register, and its spill_reg_store entry will
6745 contain the previous destination. This is now
6747 if (REG_P (SET_SRC (PATTERN (temp)))
6748 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER)
6750 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6751 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0;
6754 /* If these are the only uses of the pseudo reg,
6755 pretend for GDB it lives in the reload reg we used. */
6756 if (REG_N_DEATHS (REGNO (old)) == 1
6757 && REG_N_SETS (REGNO (old)) == 1)
6759 reg_renumber[REGNO (old)] = REGNO (rl->reg_rtx);
6760 alter_reg (REGNO (old), -1);
6766 SET_DEST (PATTERN (temp)) = old;
6771 /* We can't do that, so output an insn to load RELOADREG. */
6773 /* If we have a secondary reload, pick up the secondary register
6774 and icode, if any. If OLDEQUIV and OLD are different or
6775 if this is an in-out reload, recompute whether or not we
6776 still need a secondary register and what the icode should
6777 be. If we still need a secondary register and the class or
6778 icode is different, go back to reloading from OLD if using
6779 OLDEQUIV means that we got the wrong type of register. We
6780 cannot have different class or icode due to an in-out reload
6781 because we don't make such reloads when both the input and
6782 output need secondary reload registers. */
6784 if (! special && rl->secondary_in_reload >= 0)
6786 rtx second_reload_reg = 0;
6787 rtx third_reload_reg = 0;
6788 int secondary_reload = rl->secondary_in_reload;
6789 rtx real_oldequiv = oldequiv;
6792 enum insn_code icode;
6793 enum insn_code tertiary_icode = CODE_FOR_nothing;
6795 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM
6796 and similarly for OLD.
6797 See comments in get_secondary_reload in reload.c. */
6798 /* If it is a pseudo that cannot be replaced with its
6799 equivalent MEM, we must fall back to reload_in, which
6800 will have all the necessary substitutions registered.
6801 Likewise for a pseudo that can't be replaced with its
6802 equivalent constant.
6804 Take extra care for subregs of such pseudos. Note that
6805 we cannot use reg_equiv_mem in this case because it is
6806 not in the right mode. */
6809 if (GET_CODE (tmp) == SUBREG)
6810 tmp = SUBREG_REG (tmp);
6812 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6813 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6814 || reg_equiv_constant[REGNO (tmp)] != 0))
6816 if (! reg_equiv_mem[REGNO (tmp)]
6817 || num_not_at_initial_offset
6818 || GET_CODE (oldequiv) == SUBREG)
6819 real_oldequiv = rl->in;
6821 real_oldequiv = reg_equiv_mem[REGNO (tmp)];
6825 if (GET_CODE (tmp) == SUBREG)
6826 tmp = SUBREG_REG (tmp);
6828 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER
6829 && (reg_equiv_memory_loc[REGNO (tmp)] != 0
6830 || reg_equiv_constant[REGNO (tmp)] != 0))
6832 if (! reg_equiv_mem[REGNO (tmp)]
6833 || num_not_at_initial_offset
6834 || GET_CODE (old) == SUBREG)
6837 real_old = reg_equiv_mem[REGNO (tmp)];
6840 second_reload_reg = rld[secondary_reload].reg_rtx;
6841 if (rld[secondary_reload].secondary_in_reload >= 0)
6843 int tertiary_reload = rld[secondary_reload].secondary_in_reload;
6845 third_reload_reg = rld[tertiary_reload].reg_rtx;
6846 tertiary_icode = rld[secondary_reload].secondary_in_icode;
6847 /* We'd have to add more code for quartary reloads. */
6848 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0);
6850 icode = rl->secondary_in_icode;
6852 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv))
6853 || (rl->in != 0 && rl->out != 0))
6855 secondary_reload_info sri, sri2;
6856 enum reg_class new_class, new_t_class;
6858 sri.icode = CODE_FOR_nothing;
6859 sri.prev_sri = NULL;
6860 new_class = targetm.secondary_reload (1, real_oldequiv, rl->class,
6863 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing)
6864 second_reload_reg = 0;
6865 else if (new_class == NO_REGS)
6867 if (reload_adjust_reg_for_icode (&second_reload_reg,
6868 third_reload_reg, sri.icode))
6869 icode = sri.icode, third_reload_reg = 0;
6871 oldequiv = old, real_oldequiv = real_old;
6873 else if (sri.icode != CODE_FOR_nothing)
6874 /* We currently lack a way to express this in reloads. */
6878 sri2.icode = CODE_FOR_nothing;
6879 sri2.prev_sri = &sri;
6880 new_t_class = targetm.secondary_reload (1, real_oldequiv,
6881 new_class, mode, &sri);
6882 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing)
6884 if (reload_adjust_reg_for_temp (&second_reload_reg,
6887 third_reload_reg = 0, tertiary_icode = sri2.icode;
6889 oldequiv = old, real_oldequiv = real_old;
6891 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing)
6893 rtx intermediate = second_reload_reg;
6895 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6897 && reload_adjust_reg_for_icode (&third_reload_reg, NULL,
6900 second_reload_reg = intermediate;
6901 tertiary_icode = sri2.icode;
6904 oldequiv = old, real_oldequiv = real_old;
6906 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing)
6908 rtx intermediate = second_reload_reg;
6910 if (reload_adjust_reg_for_temp (&intermediate, NULL,
6912 && reload_adjust_reg_for_temp (&third_reload_reg, NULL,
6915 second_reload_reg = intermediate;
6916 tertiary_icode = sri2.icode;
6919 oldequiv = old, real_oldequiv = real_old;
6922 /* This could be handled more intelligently too. */
6923 oldequiv = old, real_oldequiv = real_old;
6927 /* If we still need a secondary reload register, check
6928 to see if it is being used as a scratch or intermediate
6929 register and generate code appropriately. If we need
6930 a scratch register, use REAL_OLDEQUIV since the form of
6931 the insn may depend on the actual address if it is
6934 if (second_reload_reg)
6936 if (icode != CODE_FOR_nothing)
6938 /* We'd have to add extra code to handle this case. */
6939 gcc_assert (!third_reload_reg);
6941 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv,
6942 second_reload_reg));
6947 /* See if we need a scratch register to load the
6948 intermediate register (a tertiary reload). */
6949 if (tertiary_icode != CODE_FOR_nothing)
6951 emit_insn ((GEN_FCN (tertiary_icode)
6952 (second_reload_reg, real_oldequiv,
6953 third_reload_reg)));
6955 else if (third_reload_reg)
6957 gen_reload (third_reload_reg, real_oldequiv,
6960 gen_reload (second_reload_reg, third_reload_reg,
6965 gen_reload (second_reload_reg, real_oldequiv,
6969 oldequiv = second_reload_reg;
6974 if (! special && ! rtx_equal_p (reloadreg, oldequiv))
6976 rtx real_oldequiv = oldequiv;
6978 if ((REG_P (oldequiv)
6979 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER
6980 && (reg_equiv_memory_loc[REGNO (oldequiv)] != 0
6981 || reg_equiv_constant[REGNO (oldequiv)] != 0))
6982 || (GET_CODE (oldequiv) == SUBREG
6983 && REG_P (SUBREG_REG (oldequiv))
6984 && (REGNO (SUBREG_REG (oldequiv))
6985 >= FIRST_PSEUDO_REGISTER)
6986 && ((reg_equiv_memory_loc
6987 [REGNO (SUBREG_REG (oldequiv))] != 0)
6988 || (reg_equiv_constant
6989 [REGNO (SUBREG_REG (oldequiv))] != 0)))
6990 || (CONSTANT_P (oldequiv)
6991 && (PREFERRED_RELOAD_CLASS (oldequiv,
6992 REGNO_REG_CLASS (REGNO (reloadreg)))
6994 real_oldequiv = rl->in;
6995 gen_reload (reloadreg, real_oldequiv, rl->opnum,
6999 if (flag_non_call_exceptions)
7000 copy_eh_notes (insn, get_insns ());
7002 /* End this sequence. */
7003 *where = get_insns ();
7006 /* Update reload_override_in so that delete_address_reloads_1
7007 can see the actual register usage. */
7009 reload_override_in[j] = oldequiv;
7012 /* Generate insns to for the output reload RL, which is for the insn described
7013 by CHAIN and has the number J. */
7015 emit_output_reload_insns (struct insn_chain *chain, struct reload *rl,
7018 rtx reloadreg = rl->reg_rtx;
7019 rtx insn = chain->insn;
7022 enum machine_mode mode = GET_MODE (old);
7025 if (rl->when_needed == RELOAD_OTHER)
7028 push_to_sequence (output_reload_insns[rl->opnum]);
7030 /* Determine the mode to reload in.
7031 See comments above (for input reloading). */
7033 if (mode == VOIDmode)
7035 /* VOIDmode should never happen for an output. */
7036 if (asm_noperands (PATTERN (insn)) < 0)
7037 /* It's the compiler's fault. */
7038 fatal_insn ("VOIDmode on an output", insn);
7039 error_for_asm (insn, "output operand is constant in %<asm%>");
7040 /* Prevent crash--use something we know is valid. */
7042 old = gen_rtx_REG (mode, REGNO (reloadreg));
7045 if (GET_MODE (reloadreg) != mode)
7046 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7048 /* If we need two reload regs, set RELOADREG to the intermediate
7049 one, since it will be stored into OLD. We might need a secondary
7050 register only for an input reload, so check again here. */
7052 if (rl->secondary_out_reload >= 0)
7055 int secondary_reload = rl->secondary_out_reload;
7056 int tertiary_reload = rld[secondary_reload].secondary_out_reload;
7058 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER
7059 && reg_equiv_mem[REGNO (old)] != 0)
7060 real_old = reg_equiv_mem[REGNO (old)];
7062 if (secondary_reload_class (0, rl->class, mode, real_old) != NO_REGS)
7064 rtx second_reloadreg = reloadreg;
7065 reloadreg = rld[secondary_reload].reg_rtx;
7067 /* See if RELOADREG is to be used as a scratch register
7068 or as an intermediate register. */
7069 if (rl->secondary_out_icode != CODE_FOR_nothing)
7071 /* We'd have to add extra code to handle this case. */
7072 gcc_assert (tertiary_reload < 0);
7074 emit_insn ((GEN_FCN (rl->secondary_out_icode)
7075 (real_old, second_reloadreg, reloadreg)));
7080 /* See if we need both a scratch and intermediate reload
7083 enum insn_code tertiary_icode
7084 = rld[secondary_reload].secondary_out_icode;
7086 /* We'd have to add more code for quartary reloads. */
7087 gcc_assert (tertiary_reload < 0
7088 || rld[tertiary_reload].secondary_out_reload < 0);
7090 if (GET_MODE (reloadreg) != mode)
7091 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode);
7093 if (tertiary_icode != CODE_FOR_nothing)
7095 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7098 /* Copy primary reload reg to secondary reload reg.
7099 (Note that these have been swapped above, then
7100 secondary reload reg to OLD using our insn.) */
7102 /* If REAL_OLD is a paradoxical SUBREG, remove it
7103 and try to put the opposite SUBREG on
7105 if (GET_CODE (real_old) == SUBREG
7106 && (GET_MODE_SIZE (GET_MODE (real_old))
7107 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (real_old))))
7108 && 0 != (tem = gen_lowpart_common
7109 (GET_MODE (SUBREG_REG (real_old)),
7111 real_old = SUBREG_REG (real_old), reloadreg = tem;
7113 gen_reload (reloadreg, second_reloadreg,
7114 rl->opnum, rl->when_needed);
7115 emit_insn ((GEN_FCN (tertiary_icode)
7116 (real_old, reloadreg, third_reloadreg)));
7122 /* Copy between the reload regs here and then to
7125 gen_reload (reloadreg, second_reloadreg,
7126 rl->opnum, rl->when_needed);
7127 if (tertiary_reload >= 0)
7129 rtx third_reloadreg = rld[tertiary_reload].reg_rtx;
7131 gen_reload (third_reloadreg, reloadreg,
7132 rl->opnum, rl->when_needed);
7133 reloadreg = third_reloadreg;
7140 /* Output the last reload insn. */
7145 /* Don't output the last reload if OLD is not the dest of
7146 INSN and is in the src and is clobbered by INSN. */
7147 if (! flag_expensive_optimizations
7149 || !(set = single_set (insn))
7150 || rtx_equal_p (old, SET_DEST (set))
7151 || !reg_mentioned_p (old, SET_SRC (set))
7152 || !((REGNO (old) < FIRST_PSEUDO_REGISTER)
7153 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0)))
7154 gen_reload (old, reloadreg, rl->opnum,
7158 /* Look at all insns we emitted, just to be safe. */
7159 for (p = get_insns (); p; p = NEXT_INSN (p))
7162 rtx pat = PATTERN (p);
7164 /* If this output reload doesn't come from a spill reg,
7165 clear any memory of reloaded copies of the pseudo reg.
7166 If this output reload comes from a spill reg,
7167 reg_has_output_reload will make this do nothing. */
7168 note_stores (pat, forget_old_reloads_1, NULL);
7170 if (reg_mentioned_p (rl->reg_rtx, pat))
7172 rtx set = single_set (insn);
7173 if (reload_spill_index[j] < 0
7175 && SET_SRC (set) == rl->reg_rtx)
7177 int src = REGNO (SET_SRC (set));
7179 reload_spill_index[j] = src;
7180 SET_HARD_REG_BIT (reg_is_output_reload, src);
7181 if (find_regno_note (insn, REG_DEAD, src))
7182 SET_HARD_REG_BIT (reg_reloaded_died, src);
7184 if (REGNO (rl->reg_rtx) < FIRST_PSEUDO_REGISTER)
7186 int s = rl->secondary_out_reload;
7187 set = single_set (p);
7188 /* If this reload copies only to the secondary reload
7189 register, the secondary reload does the actual
7191 if (s >= 0 && set == NULL_RTX)
7192 /* We can't tell what function the secondary reload
7193 has and where the actual store to the pseudo is
7194 made; leave new_spill_reg_store alone. */
7197 && SET_SRC (set) == rl->reg_rtx
7198 && SET_DEST (set) == rld[s].reg_rtx)
7200 /* Usually the next instruction will be the
7201 secondary reload insn; if we can confirm
7202 that it is, setting new_spill_reg_store to
7203 that insn will allow an extra optimization. */
7204 rtx s_reg = rld[s].reg_rtx;
7205 rtx next = NEXT_INSN (p);
7206 rld[s].out = rl->out;
7207 rld[s].out_reg = rl->out_reg;
7208 set = single_set (next);
7209 if (set && SET_SRC (set) == s_reg
7210 && ! new_spill_reg_store[REGNO (s_reg)])
7212 SET_HARD_REG_BIT (reg_is_output_reload,
7214 new_spill_reg_store[REGNO (s_reg)] = next;
7218 new_spill_reg_store[REGNO (rl->reg_rtx)] = p;
7223 if (rl->when_needed == RELOAD_OTHER)
7225 emit_insn (other_output_reload_insns[rl->opnum]);
7226 other_output_reload_insns[rl->opnum] = get_insns ();
7229 output_reload_insns[rl->opnum] = get_insns ();
7231 if (flag_non_call_exceptions)
7232 copy_eh_notes (insn, get_insns ());
7237 /* Do input reloading for reload RL, which is for the insn described by CHAIN
7238 and has the number J. */
7240 do_input_reload (struct insn_chain *chain, struct reload *rl, int j)
7242 rtx insn = chain->insn;
7243 rtx old = (rl->in && MEM_P (rl->in)
7244 ? rl->in_reg : rl->in);
7247 /* AUTO_INC reloads need to be handled even if inherited. We got an
7248 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */
7249 && (! reload_inherited[j] || (rl->out && ! rl->out_reg))
7250 && ! rtx_equal_p (rl->reg_rtx, old)
7251 && rl->reg_rtx != 0)
7252 emit_input_reload_insns (chain, rld + j, old, j);
7254 /* When inheriting a wider reload, we have a MEM in rl->in,
7255 e.g. inheriting a SImode output reload for
7256 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */
7257 if (optimize && reload_inherited[j] && rl->in
7259 && MEM_P (rl->in_reg)
7260 && reload_spill_index[j] >= 0
7261 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j]))
7262 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]];
7264 /* If we are reloading a register that was recently stored in with an
7265 output-reload, see if we can prove there was
7266 actually no need to store the old value in it. */
7269 && (reload_inherited[j] || reload_override_in[j])
7271 && REG_P (rl->reg_rtx)
7272 && spill_reg_store[REGNO (rl->reg_rtx)] != 0
7274 /* There doesn't seem to be any reason to restrict this to pseudos
7275 and doing so loses in the case where we are copying from a
7276 register of the wrong class. */
7277 && (REGNO (spill_reg_stored_to[REGNO (rl->reg_rtx)])
7278 >= FIRST_PSEUDO_REGISTER)
7280 /* The insn might have already some references to stackslots
7281 replaced by MEMs, while reload_out_reg still names the
7283 && (dead_or_set_p (insn,
7284 spill_reg_stored_to[REGNO (rl->reg_rtx)])
7285 || rtx_equal_p (spill_reg_stored_to[REGNO (rl->reg_rtx)],
7287 delete_output_reload (insn, j, REGNO (rl->reg_rtx));
7290 /* Do output reloading for reload RL, which is for the insn described by
7291 CHAIN and has the number J.
7292 ??? At some point we need to support handling output reloads of
7293 JUMP_INSNs or insns that set cc0. */
7295 do_output_reload (struct insn_chain *chain, struct reload *rl, int j)
7298 rtx insn = chain->insn;
7299 /* If this is an output reload that stores something that is
7300 not loaded in this same reload, see if we can eliminate a previous
7302 rtx pseudo = rl->out_reg;
7307 && ! rtx_equal_p (rl->in_reg, pseudo)
7308 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER
7309 && reg_last_reload_reg[REGNO (pseudo)])
7311 int pseudo_no = REGNO (pseudo);
7312 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]);
7314 /* We don't need to test full validity of last_regno for
7315 inherit here; we only want to know if the store actually
7316 matches the pseudo. */
7317 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno)
7318 && reg_reloaded_contents[last_regno] == pseudo_no
7319 && spill_reg_store[last_regno]
7320 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno]))
7321 delete_output_reload (insn, j, last_regno);
7326 || rl->reg_rtx == old
7327 || rl->reg_rtx == 0)
7330 /* An output operand that dies right away does need a reload,
7331 but need not be copied from it. Show the new location in the
7333 if ((REG_P (old) || GET_CODE (old) == SCRATCH)
7334 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0)
7336 XEXP (note, 0) = rl->reg_rtx;
7339 /* Likewise for a SUBREG of an operand that dies. */
7340 else if (GET_CODE (old) == SUBREG
7341 && REG_P (SUBREG_REG (old))
7342 && 0 != (note = find_reg_note (insn, REG_UNUSED,
7345 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old),
7349 else if (GET_CODE (old) == SCRATCH)
7350 /* If we aren't optimizing, there won't be a REG_UNUSED note,
7351 but we don't want to make an output reload. */
7354 /* If is a JUMP_INSN, we can't support output reloads yet. */
7355 gcc_assert (NONJUMP_INSN_P (insn));
7357 emit_output_reload_insns (chain, rld + j, j);
7360 /* Reload number R reloads from or to a group of hard registers starting at
7361 register REGNO. Return true if it can be treated for inheritance purposes
7362 like a group of reloads, each one reloading a single hard register.
7363 The caller has already checked that the spill register and REGNO use
7364 the same number of registers to store the reload value. */
7367 inherit_piecemeal_p (int r ATTRIBUTE_UNUSED, int regno ATTRIBUTE_UNUSED)
7369 #ifdef CANNOT_CHANGE_MODE_CLASS
7370 return (!REG_CANNOT_CHANGE_MODE_P (reload_spill_index[r],
7371 GET_MODE (rld[r].reg_rtx),
7372 reg_raw_mode[reload_spill_index[r]])
7373 && !REG_CANNOT_CHANGE_MODE_P (regno,
7374 GET_MODE (rld[r].reg_rtx),
7375 reg_raw_mode[regno]));
7381 /* Output insns to reload values in and out of the chosen reload regs. */
7384 emit_reload_insns (struct insn_chain *chain)
7386 rtx insn = chain->insn;
7390 CLEAR_HARD_REG_SET (reg_reloaded_died);
7392 for (j = 0; j < reload_n_operands; j++)
7393 input_reload_insns[j] = input_address_reload_insns[j]
7394 = inpaddr_address_reload_insns[j]
7395 = output_reload_insns[j] = output_address_reload_insns[j]
7396 = outaddr_address_reload_insns[j]
7397 = other_output_reload_insns[j] = 0;
7398 other_input_address_reload_insns = 0;
7399 other_input_reload_insns = 0;
7400 operand_reload_insns = 0;
7401 other_operand_reload_insns = 0;
7403 /* Dump reloads into the dump file. */
7406 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn));
7407 debug_reload_to_stream (dump_file);
7410 /* Now output the instructions to copy the data into and out of the
7411 reload registers. Do these in the order that the reloads were reported,
7412 since reloads of base and index registers precede reloads of operands
7413 and the operands may need the base and index registers reloaded. */
7415 for (j = 0; j < n_reloads; j++)
7418 && REGNO (rld[j].reg_rtx) < FIRST_PSEUDO_REGISTER)
7419 new_spill_reg_store[REGNO (rld[j].reg_rtx)] = 0;
7421 do_input_reload (chain, rld + j, j);
7422 do_output_reload (chain, rld + j, j);
7425 /* Now write all the insns we made for reloads in the order expected by
7426 the allocation functions. Prior to the insn being reloaded, we write
7427 the following reloads:
7429 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses.
7431 RELOAD_OTHER reloads.
7433 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed
7434 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the
7435 RELOAD_FOR_INPUT reload for the operand.
7437 RELOAD_FOR_OPADDR_ADDRS reloads.
7439 RELOAD_FOR_OPERAND_ADDRESS reloads.
7441 After the insn being reloaded, we write the following:
7443 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed
7444 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the
7445 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output
7446 reloads for the operand. The RELOAD_OTHER output reloads are
7447 output in descending order by reload number. */
7449 emit_insn_before (other_input_address_reload_insns, insn);
7450 emit_insn_before (other_input_reload_insns, insn);
7452 for (j = 0; j < reload_n_operands; j++)
7454 emit_insn_before (inpaddr_address_reload_insns[j], insn);
7455 emit_insn_before (input_address_reload_insns[j], insn);
7456 emit_insn_before (input_reload_insns[j], insn);
7459 emit_insn_before (other_operand_reload_insns, insn);
7460 emit_insn_before (operand_reload_insns, insn);
7462 for (j = 0; j < reload_n_operands; j++)
7464 rtx x = emit_insn_after (outaddr_address_reload_insns[j], insn);
7465 x = emit_insn_after (output_address_reload_insns[j], x);
7466 x = emit_insn_after (output_reload_insns[j], x);
7467 emit_insn_after (other_output_reload_insns[j], x);
7470 /* For all the spill regs newly reloaded in this instruction,
7471 record what they were reloaded from, so subsequent instructions
7472 can inherit the reloads.
7474 Update spill_reg_store for the reloads of this insn.
7475 Copy the elements that were updated in the loop above. */
7477 for (j = 0; j < n_reloads; j++)
7479 int r = reload_order[j];
7480 int i = reload_spill_index[r];
7482 /* If this is a non-inherited input reload from a pseudo, we must
7483 clear any memory of a previous store to the same pseudo. Only do
7484 something if there will not be an output reload for the pseudo
7486 if (rld[r].in_reg != 0
7487 && ! (reload_inherited[r] || reload_override_in[r]))
7489 rtx reg = rld[r].in_reg;
7491 if (GET_CODE (reg) == SUBREG)
7492 reg = SUBREG_REG (reg);
7495 && REGNO (reg) >= FIRST_PSEUDO_REGISTER
7496 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg)))
7498 int nregno = REGNO (reg);
7500 if (reg_last_reload_reg[nregno])
7502 int last_regno = REGNO (reg_last_reload_reg[nregno]);
7504 if (reg_reloaded_contents[last_regno] == nregno)
7505 spill_reg_store[last_regno] = 0;
7510 /* I is nonneg if this reload used a register.
7511 If rld[r].reg_rtx is 0, this is an optional reload
7512 that we opted to ignore. */
7514 if (i >= 0 && rld[r].reg_rtx != 0)
7516 int nr = hard_regno_nregs[i][GET_MODE (rld[r].reg_rtx)];
7518 int part_reaches_end = 0;
7519 int all_reaches_end = 1;
7521 /* For a multi register reload, we need to check if all or part
7522 of the value lives to the end. */
7523 for (k = 0; k < nr; k++)
7525 if (reload_reg_reaches_end_p (i + k, rld[r].opnum,
7526 rld[r].when_needed))
7527 part_reaches_end = 1;
7529 all_reaches_end = 0;
7532 /* Ignore reloads that don't reach the end of the insn in
7534 if (all_reaches_end)
7536 /* First, clear out memory of what used to be in this spill reg.
7537 If consecutive registers are used, clear them all. */
7539 for (k = 0; k < nr; k++)
7541 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7542 CLEAR_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7545 /* Maybe the spill reg contains a copy of reload_out. */
7547 && (REG_P (rld[r].out)
7551 || REG_P (rld[r].out_reg)))
7553 rtx out = (REG_P (rld[r].out)
7557 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0));
7558 int nregno = REGNO (out);
7559 int nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7560 : hard_regno_nregs[nregno]
7561 [GET_MODE (rld[r].reg_rtx)]);
7564 spill_reg_store[i] = new_spill_reg_store[i];
7565 spill_reg_stored_to[i] = out;
7566 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7568 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7570 && inherit_piecemeal_p (r, nregno));
7572 /* If NREGNO is a hard register, it may occupy more than
7573 one register. If it does, say what is in the
7574 rest of the registers assuming that both registers
7575 agree on how many words the object takes. If not,
7576 invalidate the subsequent registers. */
7578 if (nregno < FIRST_PSEUDO_REGISTER)
7579 for (k = 1; k < nnr; k++)
7580 reg_last_reload_reg[nregno + k]
7582 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7585 /* Now do the inverse operation. */
7586 for (k = 0; k < nr; k++)
7588 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7589 reg_reloaded_contents[i + k]
7590 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7593 reg_reloaded_insn[i + k] = insn;
7594 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7595 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (out)))
7596 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7600 /* Maybe the spill reg contains a copy of reload_in. Only do
7601 something if there will not be an output reload for
7602 the register being reloaded. */
7603 else if (rld[r].out_reg == 0
7605 && ((REG_P (rld[r].in)
7606 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER
7607 && !REGNO_REG_SET_P (®_has_output_reload,
7609 || (REG_P (rld[r].in_reg)
7610 && !REGNO_REG_SET_P (®_has_output_reload,
7611 REGNO (rld[r].in_reg))))
7612 && ! reg_set_p (rld[r].reg_rtx, PATTERN (insn)))
7619 if (REG_P (rld[r].in)
7620 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER)
7622 else if (REG_P (rld[r].in_reg))
7625 in = XEXP (rld[r].in_reg, 0);
7626 nregno = REGNO (in);
7628 nnr = (nregno >= FIRST_PSEUDO_REGISTER ? 1
7629 : hard_regno_nregs[nregno]
7630 [GET_MODE (rld[r].reg_rtx)]);
7632 reg_last_reload_reg[nregno] = rld[r].reg_rtx;
7634 piecemeal = (nregno < FIRST_PSEUDO_REGISTER
7636 && inherit_piecemeal_p (r, nregno));
7638 if (nregno < FIRST_PSEUDO_REGISTER)
7639 for (k = 1; k < nnr; k++)
7640 reg_last_reload_reg[nregno + k]
7642 ? regno_reg_rtx[REGNO (rld[r].reg_rtx) + k]
7645 /* Unless we inherited this reload, show we haven't
7646 recently done a store.
7647 Previous stores of inherited auto_inc expressions
7648 also have to be discarded. */
7649 if (! reload_inherited[r]
7650 || (rld[r].out && ! rld[r].out_reg))
7651 spill_reg_store[i] = 0;
7653 for (k = 0; k < nr; k++)
7655 CLEAR_HARD_REG_BIT (reg_reloaded_dead, i + k);
7656 reg_reloaded_contents[i + k]
7657 = (nregno >= FIRST_PSEUDO_REGISTER || !piecemeal
7660 reg_reloaded_insn[i + k] = insn;
7661 SET_HARD_REG_BIT (reg_reloaded_valid, i + k);
7662 if (HARD_REGNO_CALL_PART_CLOBBERED (i + k, GET_MODE (in)))
7663 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered, i + k);
7668 /* However, if part of the reload reaches the end, then we must
7669 invalidate the old info for the part that survives to the end. */
7670 else if (part_reaches_end)
7672 for (k = 0; k < nr; k++)
7673 if (reload_reg_reaches_end_p (i + k,
7675 rld[r].when_needed))
7676 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k);
7680 /* The following if-statement was #if 0'd in 1.34 (or before...).
7681 It's reenabled in 1.35 because supposedly nothing else
7682 deals with this problem. */
7684 /* If a register gets output-reloaded from a non-spill register,
7685 that invalidates any previous reloaded copy of it.
7686 But forget_old_reloads_1 won't get to see it, because
7687 it thinks only about the original insn. So invalidate it here.
7688 Also do the same thing for RELOAD_OTHER constraints where the
7689 output is discarded. */
7691 && ((rld[r].out != 0
7692 && (REG_P (rld[r].out)
7693 || (MEM_P (rld[r].out)
7694 && REG_P (rld[r].out_reg))))
7695 || (rld[r].out == 0 && rld[r].out_reg
7696 && REG_P (rld[r].out_reg))))
7698 rtx out = ((rld[r].out && REG_P (rld[r].out))
7699 ? rld[r].out : rld[r].out_reg);
7700 int nregno = REGNO (out);
7702 /* REG_RTX is now set or clobbered by the main instruction.
7703 As the comment above explains, forget_old_reloads_1 only
7704 sees the original instruction, and there is no guarantee
7705 that the original instruction also clobbered REG_RTX.
7706 For example, if find_reloads sees that the input side of
7707 a matched operand pair dies in this instruction, it may
7708 use the input register as the reload register.
7710 Calling forget_old_reloads_1 is a waste of effort if
7711 REG_RTX is also the output register.
7713 If we know that REG_RTX holds the value of a pseudo
7714 register, the code after the call will record that fact. */
7715 if (rld[r].reg_rtx && rld[r].reg_rtx != out)
7716 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL);
7718 if (nregno >= FIRST_PSEUDO_REGISTER)
7720 rtx src_reg, store_insn = NULL_RTX;
7722 reg_last_reload_reg[nregno] = 0;
7724 /* If we can find a hard register that is stored, record
7725 the storing insn so that we may delete this insn with
7726 delete_output_reload. */
7727 src_reg = rld[r].reg_rtx;
7729 /* If this is an optional reload, try to find the source reg
7730 from an input reload. */
7733 rtx set = single_set (insn);
7734 if (set && SET_DEST (set) == rld[r].out)
7738 src_reg = SET_SRC (set);
7740 for (k = 0; k < n_reloads; k++)
7742 if (rld[k].in == src_reg)
7744 src_reg = rld[k].reg_rtx;
7751 store_insn = new_spill_reg_store[REGNO (src_reg)];
7752 if (src_reg && REG_P (src_reg)
7753 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER)
7755 int src_regno = REGNO (src_reg);
7756 int nr = hard_regno_nregs[src_regno][rld[r].mode];
7757 /* The place where to find a death note varies with
7758 PRESERVE_DEATH_INFO_REGNO_P . The condition is not
7759 necessarily checked exactly in the code that moves
7760 notes, so just check both locations. */
7761 rtx note = find_regno_note (insn, REG_DEAD, src_regno);
7762 if (! note && store_insn)
7763 note = find_regno_note (store_insn, REG_DEAD, src_regno);
7766 spill_reg_store[src_regno + nr] = store_insn;
7767 spill_reg_stored_to[src_regno + nr] = out;
7768 reg_reloaded_contents[src_regno + nr] = nregno;
7769 reg_reloaded_insn[src_regno + nr] = store_insn;
7770 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + nr);
7771 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + nr);
7772 if (HARD_REGNO_CALL_PART_CLOBBERED (src_regno + nr,
7773 GET_MODE (src_reg)))
7774 SET_HARD_REG_BIT (reg_reloaded_call_part_clobbered,
7776 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + nr);
7778 SET_HARD_REG_BIT (reg_reloaded_died, src_regno);
7780 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno);
7782 reg_last_reload_reg[nregno] = src_reg;
7783 /* We have to set reg_has_output_reload here, or else
7784 forget_old_reloads_1 will clear reg_last_reload_reg
7786 SET_REGNO_REG_SET (®_has_output_reload,
7792 int num_regs = hard_regno_nregs[nregno][GET_MODE (out)];
7794 while (num_regs-- > 0)
7795 reg_last_reload_reg[nregno + num_regs] = 0;
7799 IOR_HARD_REG_SET (reg_reloaded_dead, reg_reloaded_died);
7802 /* Go through the motions to emit INSN and test if it is strictly valid.
7803 Return the emitted insn if valid, else return NULL. */
7806 emit_insn_if_valid_for_reload (rtx insn)
7808 rtx last = get_last_insn ();
7811 insn = emit_insn (insn);
7812 code = recog_memoized (insn);
7816 extract_insn (insn);
7817 /* We want constrain operands to treat this insn strictly in its
7818 validity determination, i.e., the way it would after reload has
7820 if (constrain_operands (1))
7824 delete_insns_since (last);
7828 /* Emit code to perform a reload from IN (which may be a reload register) to
7829 OUT (which may also be a reload register). IN or OUT is from operand
7830 OPNUM with reload type TYPE.
7832 Returns first insn emitted. */
7835 gen_reload (rtx out, rtx in, int opnum, enum reload_type type)
7837 rtx last = get_last_insn ();
7840 /* If IN is a paradoxical SUBREG, remove it and try to put the
7841 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */
7842 if (GET_CODE (in) == SUBREG
7843 && (GET_MODE_SIZE (GET_MODE (in))
7844 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (in))))
7845 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (in)), out)) != 0)
7846 in = SUBREG_REG (in), out = tem;
7847 else if (GET_CODE (out) == SUBREG
7848 && (GET_MODE_SIZE (GET_MODE (out))
7849 > GET_MODE_SIZE (GET_MODE (SUBREG_REG (out))))
7850 && (tem = gen_lowpart_common (GET_MODE (SUBREG_REG (out)), in)) != 0)
7851 out = SUBREG_REG (out), in = tem;
7853 /* How to do this reload can get quite tricky. Normally, we are being
7854 asked to reload a simple operand, such as a MEM, a constant, or a pseudo
7855 register that didn't get a hard register. In that case we can just
7856 call emit_move_insn.
7858 We can also be asked to reload a PLUS that adds a register or a MEM to
7859 another register, constant or MEM. This can occur during frame pointer
7860 elimination and while reloading addresses. This case is handled by
7861 trying to emit a single insn to perform the add. If it is not valid,
7862 we use a two insn sequence.
7864 Or we can be asked to reload an unary operand that was a fragment of
7865 an addressing mode, into a register. If it isn't recognized as-is,
7866 we try making the unop operand and the reload-register the same:
7867 (set reg:X (unop:X expr:Y))
7868 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)).
7870 Finally, we could be called to handle an 'o' constraint by putting
7871 an address into a register. In that case, we first try to do this
7872 with a named pattern of "reload_load_address". If no such pattern
7873 exists, we just emit a SET insn and hope for the best (it will normally
7874 be valid on machines that use 'o').
7876 This entire process is made complex because reload will never
7877 process the insns we generate here and so we must ensure that
7878 they will fit their constraints and also by the fact that parts of
7879 IN might be being reloaded separately and replaced with spill registers.
7880 Because of this, we are, in some sense, just guessing the right approach
7881 here. The one listed above seems to work.
7883 ??? At some point, this whole thing needs to be rethought. */
7885 if (GET_CODE (in) == PLUS
7886 && (REG_P (XEXP (in, 0))
7887 || GET_CODE (XEXP (in, 0)) == SUBREG
7888 || MEM_P (XEXP (in, 0)))
7889 && (REG_P (XEXP (in, 1))
7890 || GET_CODE (XEXP (in, 1)) == SUBREG
7891 || CONSTANT_P (XEXP (in, 1))
7892 || MEM_P (XEXP (in, 1))))
7894 /* We need to compute the sum of a register or a MEM and another
7895 register, constant, or MEM, and put it into the reload
7896 register. The best possible way of doing this is if the machine
7897 has a three-operand ADD insn that accepts the required operands.
7899 The simplest approach is to try to generate such an insn and see if it
7900 is recognized and matches its constraints. If so, it can be used.
7902 It might be better not to actually emit the insn unless it is valid,
7903 but we need to pass the insn as an operand to `recog' and
7904 `extract_insn' and it is simpler to emit and then delete the insn if
7905 not valid than to dummy things up. */
7907 rtx op0, op1, tem, insn;
7910 op0 = find_replacement (&XEXP (in, 0));
7911 op1 = find_replacement (&XEXP (in, 1));
7913 /* Since constraint checking is strict, commutativity won't be
7914 checked, so we need to do that here to avoid spurious failure
7915 if the add instruction is two-address and the second operand
7916 of the add is the same as the reload reg, which is frequently
7917 the case. If the insn would be A = B + A, rearrange it so
7918 it will be A = A + B as constrain_operands expects. */
7920 if (REG_P (XEXP (in, 1))
7921 && REGNO (out) == REGNO (XEXP (in, 1)))
7922 tem = op0, op0 = op1, op1 = tem;
7924 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1))
7925 in = gen_rtx_PLUS (GET_MODE (in), op0, op1);
7927 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
7931 /* If that failed, we must use a conservative two-insn sequence.
7933 Use a move to copy one operand into the reload register. Prefer
7934 to reload a constant, MEM or pseudo since the move patterns can
7935 handle an arbitrary operand. If OP1 is not a constant, MEM or
7936 pseudo and OP1 is not a valid operand for an add instruction, then
7939 After reloading one of the operands into the reload register, add
7940 the reload register to the output register.
7942 If there is another way to do this for a specific machine, a
7943 DEFINE_PEEPHOLE should be specified that recognizes the sequence
7946 code = (int) optab_handler (add_optab, GET_MODE (out))->insn_code;
7948 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG
7950 && REGNO (op1) >= FIRST_PSEUDO_REGISTER)
7951 || (code != CODE_FOR_nothing
7952 && ! ((*insn_data[code].operand[2].predicate)
7953 (op1, insn_data[code].operand[2].mode))))
7954 tem = op0, op0 = op1, op1 = tem;
7956 gen_reload (out, op0, opnum, type);
7958 /* If OP0 and OP1 are the same, we can use OUT for OP1.
7959 This fixes a problem on the 32K where the stack pointer cannot
7960 be used as an operand of an add insn. */
7962 if (rtx_equal_p (op0, op1))
7965 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1));
7968 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */
7969 set_unique_reg_note (insn, REG_EQUIV, in);
7973 /* If that failed, copy the address register to the reload register.
7974 Then add the constant to the reload register. */
7976 gcc_assert (!reg_overlap_mentioned_p (out, op0));
7977 gen_reload (out, op1, opnum, type);
7978 insn = emit_insn (gen_add2_insn (out, op0));
7979 set_unique_reg_note (insn, REG_EQUIV, in);
7982 #ifdef SECONDARY_MEMORY_NEEDED
7983 /* If we need a memory location to do the move, do it that way. */
7984 else if ((REG_P (in) || GET_CODE (in) == SUBREG)
7985 && reg_or_subregno (in) < FIRST_PSEUDO_REGISTER
7986 && (REG_P (out) || GET_CODE (out) == SUBREG)
7987 && reg_or_subregno (out) < FIRST_PSEUDO_REGISTER
7988 && SECONDARY_MEMORY_NEEDED (REGNO_REG_CLASS (reg_or_subregno (in)),
7989 REGNO_REG_CLASS (reg_or_subregno (out)),
7992 /* Get the memory to use and rewrite both registers to its mode. */
7993 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type);
7995 if (GET_MODE (loc) != GET_MODE (out))
7996 out = gen_rtx_REG (GET_MODE (loc), REGNO (out));
7998 if (GET_MODE (loc) != GET_MODE (in))
7999 in = gen_rtx_REG (GET_MODE (loc), REGNO (in));
8001 gen_reload (loc, in, opnum, type);
8002 gen_reload (out, loc, opnum, type);
8005 else if (REG_P (out) && UNARY_P (in))
8012 op1 = find_replacement (&XEXP (in, 0));
8013 if (op1 != XEXP (in, 0))
8014 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1);
8016 /* First, try a plain SET. */
8017 set = emit_insn_if_valid_for_reload (gen_rtx_SET (VOIDmode, out, in));
8021 /* If that failed, move the inner operand to the reload
8022 register, and try the same unop with the inner expression
8023 replaced with the reload register. */
8025 if (GET_MODE (op1) != GET_MODE (out))
8026 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out));
8030 gen_reload (out_moded, op1, opnum, type);
8033 = gen_rtx_SET (VOIDmode, out,
8034 gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in),
8036 insn = emit_insn_if_valid_for_reload (insn);
8039 set_unique_reg_note (insn, REG_EQUIV, in);
8043 fatal_insn ("Failure trying to reload:", set);
8045 /* If IN is a simple operand, use gen_move_insn. */
8046 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG)
8048 tem = emit_insn (gen_move_insn (out, in));
8049 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */
8050 mark_jump_label (in, tem, 0);
8053 #ifdef HAVE_reload_load_address
8054 else if (HAVE_reload_load_address)
8055 emit_insn (gen_reload_load_address (out, in));
8058 /* Otherwise, just write (set OUT IN) and hope for the best. */
8060 emit_insn (gen_rtx_SET (VOIDmode, out, in));
8062 /* Return the first insn emitted.
8063 We can not just return get_last_insn, because there may have
8064 been multiple instructions emitted. Also note that gen_move_insn may
8065 emit more than one insn itself, so we can not assume that there is one
8066 insn emitted per emit_insn_before call. */
8068 return last ? NEXT_INSN (last) : get_insns ();
8071 /* Delete a previously made output-reload whose result we now believe
8072 is not needed. First we double-check.
8074 INSN is the insn now being processed.
8075 LAST_RELOAD_REG is the hard register number for which we want to delete
8076 the last output reload.
8077 J is the reload-number that originally used REG. The caller has made
8078 certain that reload J doesn't use REG any longer for input. */
8081 delete_output_reload (rtx insn, int j, int last_reload_reg)
8083 rtx output_reload_insn = spill_reg_store[last_reload_reg];
8084 rtx reg = spill_reg_stored_to[last_reload_reg];
8087 int n_inherited = 0;
8091 /* It is possible that this reload has been only used to set another reload
8092 we eliminated earlier and thus deleted this instruction too. */
8093 if (INSN_DELETED_P (output_reload_insn))
8096 /* Get the raw pseudo-register referred to. */
8098 while (GET_CODE (reg) == SUBREG)
8099 reg = SUBREG_REG (reg);
8100 substed = reg_equiv_memory_loc[REGNO (reg)];
8102 /* This is unsafe if the operand occurs more often in the current
8103 insn than it is inherited. */
8104 for (k = n_reloads - 1; k >= 0; k--)
8106 rtx reg2 = rld[k].in;
8109 if (MEM_P (reg2) || reload_override_in[k])
8110 reg2 = rld[k].in_reg;
8112 if (rld[k].out && ! rld[k].out_reg)
8113 reg2 = XEXP (rld[k].in_reg, 0);
8115 while (GET_CODE (reg2) == SUBREG)
8116 reg2 = SUBREG_REG (reg2);
8117 if (rtx_equal_p (reg2, reg))
8119 if (reload_inherited[k] || reload_override_in[k] || k == j)
8125 n_occurrences = count_occurrences (PATTERN (insn), reg, 0);
8126 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn))
8127 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn),
8130 n_occurrences += count_occurrences (PATTERN (insn),
8131 eliminate_regs (substed, 0,
8133 for (i1 = reg_equiv_alt_mem_list [REGNO (reg)]; i1; i1 = XEXP (i1, 1))
8135 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed));
8136 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0);
8138 if (n_occurrences > n_inherited)
8141 /* If the pseudo-reg we are reloading is no longer referenced
8142 anywhere between the store into it and here,
8143 and we're within the same basic block, then the value can only
8144 pass through the reload reg and end up here.
8145 Otherwise, give up--return. */
8146 for (i1 = NEXT_INSN (output_reload_insn);
8147 i1 != insn; i1 = NEXT_INSN (i1))
8149 if (NOTE_INSN_BASIC_BLOCK_P (i1))
8151 if ((NONJUMP_INSN_P (i1) || CALL_P (i1))
8152 && reg_mentioned_p (reg, PATTERN (i1)))
8154 /* If this is USE in front of INSN, we only have to check that
8155 there are no more references than accounted for by inheritance. */
8156 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE)
8158 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0;
8159 i1 = NEXT_INSN (i1);
8161 if (n_occurrences <= n_inherited && i1 == insn)
8167 /* We will be deleting the insn. Remove the spill reg information. */
8168 for (k = hard_regno_nregs[last_reload_reg][GET_MODE (reg)]; k-- > 0; )
8170 spill_reg_store[last_reload_reg + k] = 0;
8171 spill_reg_stored_to[last_reload_reg + k] = 0;
8174 /* The caller has already checked that REG dies or is set in INSN.
8175 It has also checked that we are optimizing, and thus some
8176 inaccuracies in the debugging information are acceptable.
8177 So we could just delete output_reload_insn. But in some cases
8178 we can improve the debugging information without sacrificing
8179 optimization - maybe even improving the code: See if the pseudo
8180 reg has been completely replaced with reload regs. If so, delete
8181 the store insn and forget we had a stack slot for the pseudo. */
8182 if (rld[j].out != rld[j].in
8183 && REG_N_DEATHS (REGNO (reg)) == 1
8184 && REG_N_SETS (REGNO (reg)) == 1
8185 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS
8186 && find_regno_note (insn, REG_DEAD, REGNO (reg)))
8190 /* We know that it was used only between here and the beginning of
8191 the current basic block. (We also know that the last use before
8192 INSN was the output reload we are thinking of deleting, but never
8193 mind that.) Search that range; see if any ref remains. */
8194 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8196 rtx set = single_set (i2);
8198 /* Uses which just store in the pseudo don't count,
8199 since if they are the only uses, they are dead. */
8200 if (set != 0 && SET_DEST (set) == reg)
8205 if ((NONJUMP_INSN_P (i2) || CALL_P (i2))
8206 && reg_mentioned_p (reg, PATTERN (i2)))
8208 /* Some other ref remains; just delete the output reload we
8210 delete_address_reloads (output_reload_insn, insn);
8211 delete_insn (output_reload_insn);
8216 /* Delete the now-dead stores into this pseudo. Note that this
8217 loop also takes care of deleting output_reload_insn. */
8218 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2))
8220 rtx set = single_set (i2);
8222 if (set != 0 && SET_DEST (set) == reg)
8224 delete_address_reloads (i2, insn);
8232 /* For the debugging info, say the pseudo lives in this reload reg. */
8233 reg_renumber[REGNO (reg)] = REGNO (rld[j].reg_rtx);
8234 alter_reg (REGNO (reg), -1);
8238 delete_address_reloads (output_reload_insn, insn);
8239 delete_insn (output_reload_insn);
8243 /* We are going to delete DEAD_INSN. Recursively delete loads of
8244 reload registers used in DEAD_INSN that are not used till CURRENT_INSN.
8245 CURRENT_INSN is being reloaded, so we have to check its reloads too. */
8247 delete_address_reloads (rtx dead_insn, rtx current_insn)
8249 rtx set = single_set (dead_insn);
8250 rtx set2, dst, prev, next;
8253 rtx dst = SET_DEST (set);
8255 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn);
8257 /* If we deleted the store from a reloaded post_{in,de}c expression,
8258 we can delete the matching adds. */
8259 prev = PREV_INSN (dead_insn);
8260 next = NEXT_INSN (dead_insn);
8261 if (! prev || ! next)
8263 set = single_set (next);
8264 set2 = single_set (prev);
8266 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS
8267 || GET_CODE (XEXP (SET_SRC (set), 1)) != CONST_INT
8268 || GET_CODE (XEXP (SET_SRC (set2), 1)) != CONST_INT)
8270 dst = SET_DEST (set);
8271 if (! rtx_equal_p (dst, SET_DEST (set2))
8272 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0))
8273 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0))
8274 || (INTVAL (XEXP (SET_SRC (set), 1))
8275 != -INTVAL (XEXP (SET_SRC (set2), 1))))
8277 delete_related_insns (prev);
8278 delete_related_insns (next);
8281 /* Subfunction of delete_address_reloads: process registers found in X. */
8283 delete_address_reloads_1 (rtx dead_insn, rtx x, rtx current_insn)
8285 rtx prev, set, dst, i2;
8287 enum rtx_code code = GET_CODE (x);
8291 const char *fmt = GET_RTX_FORMAT (code);
8292 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8295 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn);
8296 else if (fmt[i] == 'E')
8298 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8299 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j),
8306 if (spill_reg_order[REGNO (x)] < 0)
8309 /* Scan backwards for the insn that sets x. This might be a way back due
8311 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev))
8313 code = GET_CODE (prev);
8314 if (code == CODE_LABEL || code == JUMP_INSN)
8318 if (reg_set_p (x, PATTERN (prev)))
8320 if (reg_referenced_p (x, PATTERN (prev)))
8323 if (! prev || INSN_UID (prev) < reload_first_uid)
8325 /* Check that PREV only sets the reload register. */
8326 set = single_set (prev);
8329 dst = SET_DEST (set);
8331 || ! rtx_equal_p (dst, x))
8333 if (! reg_set_p (dst, PATTERN (dead_insn)))
8335 /* Check if DST was used in a later insn -
8336 it might have been inherited. */
8337 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2))
8343 if (reg_referenced_p (dst, PATTERN (i2)))
8345 /* If there is a reference to the register in the current insn,
8346 it might be loaded in a non-inherited reload. If no other
8347 reload uses it, that means the register is set before
8349 if (i2 == current_insn)
8351 for (j = n_reloads - 1; j >= 0; j--)
8352 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8353 || reload_override_in[j] == dst)
8355 for (j = n_reloads - 1; j >= 0; j--)
8356 if (rld[j].in && rld[j].reg_rtx == dst)
8365 /* If DST is still live at CURRENT_INSN, check if it is used for
8366 any reload. Note that even if CURRENT_INSN sets DST, we still
8367 have to check the reloads. */
8368 if (i2 == current_insn)
8370 for (j = n_reloads - 1; j >= 0; j--)
8371 if ((rld[j].reg_rtx == dst && reload_inherited[j])
8372 || reload_override_in[j] == dst)
8374 /* ??? We can't finish the loop here, because dst might be
8375 allocated to a pseudo in this block if no reload in this
8376 block needs any of the classes containing DST - see
8377 spill_hard_reg. There is no easy way to tell this, so we
8378 have to scan till the end of the basic block. */
8380 if (reg_set_p (dst, PATTERN (i2)))
8384 delete_address_reloads_1 (prev, SET_SRC (set), current_insn);
8385 reg_reloaded_contents[REGNO (dst)] = -1;
8389 /* Output reload-insns to reload VALUE into RELOADREG.
8390 VALUE is an autoincrement or autodecrement RTX whose operand
8391 is a register or memory location;
8392 so reloading involves incrementing that location.
8393 IN is either identical to VALUE, or some cheaper place to reload from.
8395 INC_AMOUNT is the number to increment or decrement by (always positive).
8396 This cannot be deduced from VALUE.
8398 Return the instruction that stores into RELOADREG. */
8401 inc_for_reload (rtx reloadreg, rtx in, rtx value, int inc_amount)
8403 /* REG or MEM to be copied and incremented. */
8404 rtx incloc = find_replacement (&XEXP (value, 0));
8405 /* Nonzero if increment after copying. */
8406 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC
8407 || GET_CODE (value) == POST_MODIFY);
8413 rtx real_in = in == value ? incloc : in;
8415 /* No hard register is equivalent to this register after
8416 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero,
8417 we could inc/dec that register as well (maybe even using it for
8418 the source), but I'm not sure it's worth worrying about. */
8420 reg_last_reload_reg[REGNO (incloc)] = 0;
8422 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY)
8424 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS);
8425 inc = find_replacement (&XEXP (XEXP (value, 1), 1));
8429 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC)
8430 inc_amount = -inc_amount;
8432 inc = GEN_INT (inc_amount);
8435 /* If this is post-increment, first copy the location to the reload reg. */
8436 if (post && real_in != reloadreg)
8437 emit_insn (gen_move_insn (reloadreg, real_in));
8441 /* See if we can directly increment INCLOC. Use a method similar to
8442 that in gen_reload. */
8444 last = get_last_insn ();
8445 add_insn = emit_insn (gen_rtx_SET (VOIDmode, incloc,
8446 gen_rtx_PLUS (GET_MODE (incloc),
8449 code = recog_memoized (add_insn);
8452 extract_insn (add_insn);
8453 if (constrain_operands (1))
8455 /* If this is a pre-increment and we have incremented the value
8456 where it lives, copy the incremented value to RELOADREG to
8457 be used as an address. */
8460 emit_insn (gen_move_insn (reloadreg, incloc));
8465 delete_insns_since (last);
8468 /* If couldn't do the increment directly, must increment in RELOADREG.
8469 The way we do this depends on whether this is pre- or post-increment.
8470 For pre-increment, copy INCLOC to the reload register, increment it
8471 there, then save back. */
8475 if (in != reloadreg)
8476 emit_insn (gen_move_insn (reloadreg, real_in));
8477 emit_insn (gen_add2_insn (reloadreg, inc));
8478 store = emit_insn (gen_move_insn (incloc, reloadreg));
8483 Because this might be a jump insn or a compare, and because RELOADREG
8484 may not be available after the insn in an input reload, we must do
8485 the incrementation before the insn being reloaded for.
8487 We have already copied IN to RELOADREG. Increment the copy in
8488 RELOADREG, save that back, then decrement RELOADREG so it has
8489 the original value. */
8491 emit_insn (gen_add2_insn (reloadreg, inc));
8492 store = emit_insn (gen_move_insn (incloc, reloadreg));
8493 if (GET_CODE (inc) == CONST_INT)
8494 emit_insn (gen_add2_insn (reloadreg, GEN_INT (-INTVAL (inc))));
8496 emit_insn (gen_sub2_insn (reloadreg, inc));
8504 add_auto_inc_notes (rtx insn, rtx x)
8506 enum rtx_code code = GET_CODE (x);
8510 if (code == MEM && auto_inc_p (XEXP (x, 0)))
8513 = gen_rtx_EXPR_LIST (REG_INC, XEXP (XEXP (x, 0), 0), REG_NOTES (insn));
8517 /* Scan all the operand sub-expressions. */
8518 fmt = GET_RTX_FORMAT (code);
8519 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--)
8522 add_auto_inc_notes (insn, XEXP (x, i));
8523 else if (fmt[i] == 'E')
8524 for (j = XVECLEN (x, i) - 1; j >= 0; j--)
8525 add_auto_inc_notes (insn, XVECEXP (x, i, j));
8530 /* Copy EH notes from an insn to its reloads. */
8532 copy_eh_notes (rtx insn, rtx x)
8534 rtx eh_note = find_reg_note (insn, REG_EH_REGION, NULL_RTX);
8537 for (; x != 0; x = NEXT_INSN (x))
8539 if (may_trap_p (PATTERN (x)))
8541 = gen_rtx_EXPR_LIST (REG_EH_REGION, XEXP (eh_note, 0),
8547 /* This is used by reload pass, that does emit some instructions after
8548 abnormal calls moving basic block end, but in fact it wants to emit
8549 them on the edge. Looks for abnormal call edges, find backward the
8550 proper call and fix the damage.
8552 Similar handle instructions throwing exceptions internally. */
8554 fixup_abnormal_edges (void)
8556 bool inserted = false;
8564 /* Look for cases we are interested in - calls or instructions causing
8566 FOR_EACH_EDGE (e, ei, bb->succs)
8568 if (e->flags & EDGE_ABNORMAL_CALL)
8570 if ((e->flags & (EDGE_ABNORMAL | EDGE_EH))
8571 == (EDGE_ABNORMAL | EDGE_EH))
8574 if (e && !CALL_P (BB_END (bb))
8575 && !can_throw_internal (BB_END (bb)))
8579 /* Get past the new insns generated. Allow notes, as the insns
8580 may be already deleted. */
8582 while ((NONJUMP_INSN_P (insn) || NOTE_P (insn))
8583 && !can_throw_internal (insn)
8584 && insn != BB_HEAD (bb))
8585 insn = PREV_INSN (insn);
8587 if (CALL_P (insn) || can_throw_internal (insn))
8591 stop = NEXT_INSN (BB_END (bb));
8593 insn = NEXT_INSN (insn);
8595 FOR_EACH_EDGE (e, ei, bb->succs)
8596 if (e->flags & EDGE_FALLTHRU)
8599 while (insn && insn != stop)
8601 next = NEXT_INSN (insn);
8606 /* Sometimes there's still the return value USE.
8607 If it's placed after a trapping call (i.e. that
8608 call is the last insn anyway), we have no fallthru
8609 edge. Simply delete this use and don't try to insert
8610 on the non-existent edge. */
8611 if (GET_CODE (PATTERN (insn)) != USE)
8613 /* We're not deleting it, we're moving it. */
8614 INSN_DELETED_P (insn) = 0;
8615 PREV_INSN (insn) = NULL_RTX;
8616 NEXT_INSN (insn) = NULL_RTX;
8618 insert_insn_on_edge (insn, e);
8622 else if (!BARRIER_P (insn))
8623 set_block_for_insn (insn, NULL);
8628 /* It may be that we don't find any such trapping insn. In this
8629 case we discovered quite late that the insn that had been
8630 marked as can_throw_internal in fact couldn't trap at all.
8631 So we should in fact delete the EH edges out of the block. */
8633 purge_dead_edges (bb);
8637 /* We've possibly turned single trapping insn into multiple ones. */
8638 if (flag_non_call_exceptions)
8641 blocks = sbitmap_alloc (last_basic_block);
8642 sbitmap_ones (blocks);
8643 find_many_sub_basic_blocks (blocks);
8644 sbitmap_free (blocks);
8648 commit_edge_insertions ();
8650 #ifdef ENABLE_CHECKING
8651 /* Verify that we didn't turn one trapping insn into many, and that
8652 we found and corrected all of the problems wrt fixups on the
8654 verify_flow_info ();
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